IDT 84329AV-01

ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS84329-01 is a general purpose, single output high
frequency synthesizer. The VCO operates at a frequency range
of 200MHz to 700MHz. The VCO frequency is programmed in
steps equal to the value of thecrystal frequency divided by
16. The VCO and output frequency can be programmed
using the serial or parallel interfaces to the configuration logic.
The output can be configured to divide the VCO frequency by
1, 2, 4, and 8. Output frequency steps as small as 125kHz to
1MHz can be achieved using a 16MHz crystal depending on
the output dividers.
•
•
•
•
•
•
•
•
•
•
•
•
Fully integrated PLL, no external loop filter requirements
1 differential 3.3V LVPECL output
Crystal oscillator interface
Output frequency range: 25MHz to 700MHz
VCO range: 200MHz to 700MHz
Parallel interface for programming counter
and output dividers during power-up
Serial 3 wire interface
RMS Period jitter: 5.5ps (maximum)
Cycle-to-cycle jitter: 35ps (maximum)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free
(RoHS 6) packages
BLOCK DIAGRAM
PIN ASSIGNMENT
M0
M1
M2
M3
M4
M5
M6
M7
M8
N0
N1
VEE
TEST
VCC
XTAL1
OSC
XTAL2
÷ 16
PLL
PHASE DETECTOR
1
VCO
÷M
FOUT
nFOUT
nP_LOAD
VCC
XTAL2
XTAL1
nc
nc
VCCA
S_LOAD
S_DATA
S_CLOCK
VCC
FOUT
nFOUT
VEE
TEST
VEE
TEST
VCC
VEE
VCC
nFOUT
CONFIGURATION
INTERFACE
LOGIC
28-Lead SOIC
7.5mm x 18.05mm x 2.25mm package body
M Package
Top View
M0:M8
25 24 23 22 21 20 19
N0:N1
S_CLOCK
26
18
N1
S_DATA
27
17
N0
S_LOAD
28
VCCA
nc
nc
XTAL1
M8
M7
12
M4
4
7
8
9 10 11
M6
M5
M0
M1
M3
6
M2
5
nP_LOAD
1
16
28-Lead PLCC
15
11.6mm x 11.4mm x 4.1mm
2
14
V Package
3
13
Top View
Vcc
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ICS84329-01
1
XTAL2
84329AM-01
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ICS84329-01
0
FOUT
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
÷1
÷2
÷4
÷8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
REV. D AUGUST 7, 2010
ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes
operation using a 16MHz crystal. Valid PLL loop divider
values for different crystal or input frequencies are defined
in the Input Frequency Characteristics, Table 6, NOTE 1.
to the M divider and N output divider. On the LOW-to-HIGH
transition of the nP_LOAD input, the data is latched and the
M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. The TEST output is
Mode 000 (shift register out) when operating in the parallel
input mode. The relationship between the VCO frequency,
the crystal frequency and the M divider is defined as follows:
fxtal x
fVCO =
M
16
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve
lock are defined as 200 ≤ M ≤ 511. The frequency out is
defined as follows:
fout = fVCO = fxtal x M
N
N
16
The ICS84329-01 features a fully integrated PLL and therefore requires no external components for setting the loop
bandwidth. A series-resonant, fundamental crystal is used
as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a
16MHz crystal this provides a 1MHz reference frequency.
The VCO of the PLL operates over a range of 200MHz to
700MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency ÷ 16 by
adjusting the VCO control voltage. Note that for some values
of M (either too high or too low), the PLL will not achieve lock.
The output of the VCO is scaled by a divider prior to being
sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS84329-01 support
two input modes to program the M divider and N output
divider. The two input operational modes are parallel and
serial. Figure 1 shows the timing diagram for each mode. In
parallel mode the nP_LOAD input is LOW. The data on inputs M0 through M8 and N0 through N1 is passed directly
T2
0
0
0
0
T1
0
0
1
1
T0
0
1
0
1
1
0
0
1
1
0
1
1
0
1
1
1
VCO ÷
Serial operation occurs when nP_LOAD is HIGH and
S_LOAD is LOW. The shift register is loaded by sampling
the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and
N output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the
S_DATA input is passed directly to the M divider on each
rising edge of S_CLOCK. The serial mode can be used to
program the M and N bits and test bits T2:T0. The internal
registers T2:T0 determine the state of the TEST output as
follows:
TEST Output
fOUT
Shift Register Out
fOUT
High
fOUT
PLL Reference Xtal ÷ 16
fOUT
M (non 50% Duty M divider)
fOUT
fOUT
LVCMOS Output Frequency < 200MHz
Low
S_CLOCK ÷ M
(non 50% Duty Cycle M divider)
fOUT ÷ 4
fOUT
fOUT
S_CLOCK ÷ N divider
fOUT
SERIAL LOADING
S_CLOCK
S_DATA
S_LOAD
T2
t
S
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
H
nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N1
M, N
nP_LOAD
t
S
t
H
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
84329AM-01
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REV. D AUGUST 7, 2010
ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Name
M0, M1, M2, M3,
M4, M5, M6, M7, M8
Type
Input
Pullup
N0, N1
Input
Pullup
VEE
Power
TEST
Output
VCC
Power
nFOUT, FOUT
Output
S_CLOCK
Input
S_DATA
Input
S_LOAD
Input
VCCA
Power
nc
Unused
Description
M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input.
LVCMOS / LVTTL interface levels.
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
Negative supply pins.
Test output which is used in the serial mode of operation.
LVCMOS / LVTTL interface levels.
Core supply pins.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Clocks the serial data present at S_DATA input into the shift register
Pulldown
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
Pulldown
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the M divider.
Pulldown
LVCMOS / LVTTL interface levels.
Analog supply pin.
No connect.
Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Parallel load input. Determines when data present at M8:M0 is loaded into
the M divider, and when data present at N1:N0 sets the N output divider value.
nP_LOAD
Input
Pullup
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
XTAL1, XTAL2
Input
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
84329AM-01
Test Conditions
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3
Minimum
Typical
Maximum
Units
REV. D AUGUST 7, 2010
ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL
AND
SERIAL MODE FUNCTION TABLE
Inputs
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA
X
X
X
X
X
X
L
Data
Data
X
X
X
↑
Data
Data
L
X
X
H
X
X
L
↑
Data
H
X
X
↑
L
Data
H
X
X
↓
L
Data
H
X
X
L
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
X
X
Conditions
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to M divider and
N output divider. TEST mode 000.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider
and N output divider.
M divide and N output divide values are latched.
Parallel or serial input do not affect shift registers.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
128
64
32
16
8
4
2
1
M8
M7
M6
M5
M4
M3
M2
M1
M0
200
0
1
1
0
0
1
0
0
0
201
0
1
1
0
0
1
0
0
1
202
202
0
1
1
0
0
1
0
1
0
203
203
0
1
1
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
VCO Frequency
(MHz)
M Divider
200
201
•
•
•
•
•
•
•
•
•
•
•
509
509
1
1
1
1
1
1
1
0
1
510
510
1
1
1
1
1
1
1
1
0
511
511
1
1
1
1
1
1
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
N Divider Value
Output Frequency (MHz)
N1
N0
0
0
1
200
700
0
1
2
100
350
1
0
4
50
175
1
1
8
25
87.5
84329AM-01
Minimum
Maximum
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4
REV. D AUGUST 7, 2010
ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5 V
Outputs, VO
-0.5V to VCC + 0.5V
Package Thermal Impedance, θJA
46.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. DC POWER SUPPLY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
110
mA
ICCA
Analog Supply Current
15
mA
Maximum
Units
2
VCC + 0.3
V
-0.3
0.8
V
VCC = VIN = 3.465V
5
µA
VCC = VIN = 3.465V
150
µA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VIH
VIL
IIH
IIL
VOH
Parameter
S_LOAD, nP_LOAD,
Input High Voltage
S_DATA, S_CLOCK,
M0:M8, N0:N1
S_LOAD, nP_LOAD,
Input Low Voltage
S_DATA, S_CLOCK,
M0:M8, N0:N1
M0-M8, N0, N1,
nP_LOAD
Input High Current
S_LOAD,
S_DATA, S_CLOCK
M0-M8, N0, N1,
nP_LOAD
Input Low Current
S_LOAD,
S_DATA, S_CLOCK
Output High Voltage; NOTE 1
Test Conditions
Minimum Typical
VCC = 3.465V, VIN = 0V
-150
µA
VCC = 3.465V, VIN = 0V
-5
µA
2.6
V
Output Low Voltage; NOTE 1
VOL
NOTE 1: Outputs terminated with 50Ω to VCC/2. See figure "3.3V Output Load Test Circuit" in the
"Parameter Measurement Information" section.
0.5
V
Maximum
Units
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage; NOTE 1
VCC - 1.4
VCC - 0.9
V
V OL
Output Low Voltage; NOTE 1
VCC - 2.0
VCC - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
84329AM-01
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REV. D AUGUST 7, 2010
ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
25
MHz
Equivalent Series Resistance (ESR)
Frequency
10
70
Ω
Shunt Capacitance
7
pF
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
fIN
Parameter
Input Frequency
Test Conditions
Minimum
Typical
Maximum
Units
XTAL; NOTE 1
10
17
MHz
XTAL; NOTE 1, 2
17
25
MHz
S_CLOCK
50
MHz
NOTE 1: For the cr ystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency
range of 200MHz or 700MHz. Using the minimum frequency of 10MHz valid values of M are 320 ≤ M ≤ 511.
Using the maximum frequency of 25MHz valid values of M are 128 ≤ M ≤ 448.
NOTE 2: For cr ystal frequencies greater than 17MHz, a series tuning capacitor is required for proper operation.
For more information, please refer to the Application Information, "Cr ystal Input and Oscillator Interface".
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
FOUT
Output Frequency
tjit(per)
Period Jitter, RMS; NOTE 1, 2
Test Conditions
Minimum
fOUT ≥ 65MHz
Maximum
Units
700
MHz
5.5
ps
fOUT < 65MHz
12
ps
fOUT ≥ 50MHz
35
ps
50
ps
800
ps
tjit(cc)
Cycle-to-Cycle Jitter ; NOTE 1, 2
tR / tF
Output Rise/Fall Time
tS
Setup Time
5
tH
Hold Time
5
tL
PLL Lock Time
fOUT < 50MHz
20% to 80%
odc
Output Duty Cycle
See Parameter Measurement Information section.
Characterized using a 16MHz XTAL.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: See Applications section.
84329AM-01
Typical
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6
300
45
ns
ns
50
10
ms
55
%
REV. D AUGUST 7, 2010
ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
VCC,
VCCA
Qx
SCOPE
nFOUT
FOUT
➤
nQx
➤
LVPECL
t cycle n
➤
t cycle n+1
➤
t jit(cc) = t cycle n – t cycle n+1
1000 Cycles
VEE
-1.3V ± 0.165V
CYCLE-TO-CYCLE JITTER
3.3V OUTPUT LOAD AC TEST CIRCUIT
nFOUT
VOH
FOUT
VREF
t PW
t
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
odc =
PERIOD
t PW
x 100%
t PERIOD
Histogram
Reference Point
Mean Period
(Trigger Edge)
(First edge after trigger)
PERIOD JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
S_DATA
S_CLOCK
80%
S_LOAD
20%
20%
tR
t HOLD
80%
VSW I N G
Clock
Outputs
t SET-UP
t SET-UP
M0:M8
tF
N0:N1
nP_LOAD
OUTPUT RISE/FALL TIME
84329AM-01
SETUP
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7
AND
t HOLD
t SET-UP
HOLD
REV. D AUGUST 7, 2010
ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84329-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and VCCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
10Ω
.01μF
10 μF
VCCA
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
VCC - 2V
Zo = 50Ω
RTT
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
84329AM-01
FIN
50Ω
84Ω
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. D AUGUST 7, 2010
ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
14
12
Time (pS)
10
8
6
4
2
0
25
50
75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525
Output Frequency (MHz)
FIGURE 4A. RMS JITTER VS. fOUT (USING A 16MHZ XTAL)
60
50
Time (pS)
40
30
20
10
0
25
50
75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525
Output Frequency (MHz)
FIGURE 4B. CYCLE-TO-CYCLE JITTER VS. fOUT (USING A 16MHZ XTAL)
84329AM-01
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REV. D AUGUST 7, 2010
ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
CRYSTAL INPUT AND OSCILLATOR INTERFACE
The ICS84329-01 features an internal oscillator that uses an
external quartz crystal as the source of its reference frequency.
The oscillator is a series resonant, multi-vibrator type design. This
design provides better stability and eliminates the need for large
on chip capacitors. Though a series resonant crystal is preferred,
a parallel resonant crystal can be used. A parallel resonant mode
crystal used in a series resonant circuit will exhibit a frequency
of oscillation a few hundred ppm lower than specified. A few
hundred ppm translates to KHz inaccuracy. In general computing
applications, this level of inaccuracy is irrelevant. If better ppm
accuracy is required, an external capacitor can be added to a
quartz crystal in series to XTAL1. Figure 5A shows how to
interface with a crystal.
ICS84329-01
XTAL2
XTAL1
Figures 5A and 5B show various crystal parameters which are
recommended only as guidelines. Figure 5A shows how to interface a capacitor with a parallel resonant crystal. Figure 5B shows
the capacitor value needed for the optimum ppm performance
over various series resonant crystal frequencies. For IA64/32
platforms which required a Raltron Parallel Resonant Quartz
crystal part #AS-16.66-18-SMD-T-M1, a 7pF series capacitor can
be used to better the ppm accuracy.
FIGURE 5A. CRYSTAL INTERFACE
NOTE: For crystal frequencies higher than 17MHz,
a series tuning capacitor is required for proper operation.
FIGURE 5B. Recommended tuning capacitance for various series
resonant crystals.
Series Capacitor (pf)
30
10.000
25
12.000
20
14.318
15
16.000
20.000
10
24.000
5
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Series Resonant Crystal Frequency (MHz)
84329AM-01
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REV. D AUGUST 7, 2010
ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
The layout in the actual system will depend on the selected component types, the density of the components, the density of the
traces, and the stack up of the P.C. board.
M3
M2
M1
M0
nPLOAD
VCC
The schematic of the ICS84329-01 layout example used in
this layout guideline is shown in Figure 6A. The ICS84329-01
recommended PCB board layout for this example is shown in
Figure 6B. This layout example is used as a general guideline.
M4
M5
M6
M7
M8
N2
N1
SP = Space (i.e. not intstalled)
M[8:0]= 110010000 (400)
N[1:0] =01 (Divide by 2)
12
13
14
15
16
17
18
M4
M5
M6
M7
M8
N0
N1
19
20
21
22
23
24
25
U1
VCC
84329_01_PLCC
RD1
1K
RD7
SP
RD8
SP
RD9
1K
RU11
SP
RD10
SP
4
3
2
1
28
27
26
X1
VCC
R7
10
VCCA
C11
0.01u
C16
10u
C1
0.1uF
VCC
RU10
1K
nPLoad
RU9
SP
N1
RU8
1K
N0
M7
M0
RD0
1K
RU7
1K
M8
RU1
SP
M1
RU0
SP
XTAL1
nc
nc
VCCA
S_LOAD
S_DATA
S_CLOCK
VEE
TEST
VCC
VEE
nFOUT
FOUT
VCC
VCC=3.3V
16MHz
M3
M2
M1
M0
nP_LOAD
VCC
XTAL2
11
10
9
8
7
6
5
C3
0.1u
C2
0.1u
RD6
1K
Zo = 50 Ohm
Fout = 200 MHz
Zo = 50 Ohm
R2
50
R1
50
R3
50
FIGURE 6A. SCHEMATIC
84329AM-01
OF
RECOMMENDED LAYOUT
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ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example:
• The differential 50Ω output traces should have the
same length.
All the resistors and capacitors are size 0603.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
POWER
AND
GROUNDING
Place the decoupling capacitors C1, C2 and C3, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via.
• Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
• Make sure no other signal traces are routed between the
clock trace pair.
CLOCK TRACES
• The matching termination resistors should be located as
close to the receiver input pins as possible.
AND
TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
X1
C3
U1
GND
VCC
PIN 2
C11
PIN 1
C16
VCCA
VCCA
R7
VIA
Signals
Traces
C1
C2
50 Ohm
Traces
FIGURE 6B. PCB BOARD LAYOUT FOR ICS84329-01
84329AM-01
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ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84329-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84329-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 110mA = 381.2mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 381.2mW + 30mW = 411.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 8A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.411W * 39.7°C/W = 86.3°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8A. THERMAL RESISTANCE θJA
FOR
28-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
76.2°C/W
46.2°C/W
60.8°C/W
39.7°C/W
53.2°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 8B. THERMAL RESISTANCE θJA
FOR
28-PIN PLCC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
84329AM-01
0
200
500
37.8°C/W
31.1°C/W
28.3°C/W
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ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in the Figure 7.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
For logic high, VOUT = V
OH_MAX
(V
CC_MAX
•
-V
OH_MAX
OL_MAX
CC_MAX
CC_MAX
– 0.9V
) = 0.9V
For logic low, VOUT = V
(V
=V
=V
CC_MAX
– 1.7V
) = 1.7V
-V
OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R ] * (V
CC_MAX
L
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
CC_MAX
L
-V
OH_MAX
)=
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 9A. θJAVS. AIR FLOW SOIC TABLE
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
76.2°C/W
46.2°C/W
60.8°C/W
39.7°C/W
53.2°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 9B. θJAVS. AIR FLOW PLCC TABLE
θJA by Velocity (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
37.8°C/W
31.1°C/W
28.3°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84329-01 is: 4408
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700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - M SUFFIX FOR 28 LEAD SOIC
TABLE 10A. PACKAGE DIMENSIONS
SYMBOL
Millimeters
MINIMUM
N
A
MAXIMUM
28
--
2.65
A1
0.10
--
A2
2.05
2.55
B
0.33
0.51
C
0.18
0.32
D
17.70
18.40
E
7.40
e
7.60
1.27 BASIC
H
10.00
10.65
h
0.25
0.75
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-013, MO-119
84329AM-01
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REV. D AUGUST 7, 2010
ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - V SUFFIX FOR 28 LEAD PLCC
TABLE 10B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
28
N
A
4.19
4.57
A1
2.29
3.05
A2
1.57
2.11
b
0.33
0.53
c
0.19
0.32
D
12.32
12.57
D1
11.43
11.58
D2
4.85
5.56
E
12.32
12.57
E1
11.43
11.58
E2
4.85
5.56
Reference Document: JEDEC Publication 95, MS-018
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ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 11. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
84329AM-01
ICS84329AM-01
84329AM-01T
ICS84329AM-01
28 Lead SOIC
Tube
0°C to 70°C
28 Lead SOIC
1000 Tape & Reel
0°C to 70°C
84329AM-01LF
ICS84329AM-01LF
Lead-Free, 28 Lead SOIC
Tube
0°C to 70°C
84329AM-01LFT
ICS84329AM-01LF
Lead-Free, 28 Lead SOIC
1000 Tape & Reel
0°C to 70°C
84329AV-01
ICS84329AV-01
28 Lead PLCC
Tube
0°C to 70°C
84329AV-01T
ICS84329AV-01
28 Lead PLCC
500 Tape & Reel
0°C to 70°C
84329AV-01LF
ICS84329A01L
Lead-Free, 28 Lead PLCC
Tube
0°C to 70°C
84329AV-01LFT
ICS84329A01L
Lead-Free, 28 Lead PLCC
500 Tape & Reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Rev
B
B
Table
T6
Page
6
12
2
Added Cr ystal Input and Oscillator Interface section.
Updated Parallel & Serial Load Operations diagram.
T1
3
Changed VCC and cr ystal descriptions.
T6
1
6
C
10
T2
T4C
1
2
3
5
D
13 - 14
D
84329AM-01
Description of Change
Input Frequency Characteristics Table • updated XTAL from 25MHz Max. to 20MHz Max.
• added another XTAL row to include Notes 1 and 2
T11
18
T11
18
20
Date
02/14/02
12/18/02
Updated format.
Block Diagram, replaced ÷N with dividers.
Changed 20MHz max. limit to 17MHz max. and changed 20MHz min. limit to
17MHz min. Revised Note 2.
Cr ystal Input & Oscillator Interface section, added same cr ystal frequency
note.
Features Section - added lead-free bullet.
Corrected Figure 1, Parallel & Serial Load Operations Diagram.
Pin Characteristics - changed CIN from 4pF max. to 4pF typical.
LVPECL DC Characteristics Table -corrected VOH max. from VCC - 1.0V to
VCC - 0.9V.
Power Considerations - corrected power dissipation to reflect VOH max in Table
4C.
Ordering Information Table - added lead-free par t number for ICS84329AM-01,
and added lead-free par t number and marking for ICS84329AV-01. Added
lead-free note.
Ordering Information Table - removed ICS prefix from Par t/Order Number
column. Added lead-free marking for 28 lead SOIC package.
Added Contact Page.
Updated datasheet's header/footer with IDT from ICS.
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19
4/3/03
4/10/07
8/7/10
REV. D AUGUST 7, 2010
ICS84329-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
We’ve Got Your Timing Solution.
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Tech Support
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
[email protected]
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
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