ICS ICS84314AY-02

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS84314-02 is a general purpose quad
output frequency synthesizer and a member of
HiPerClockS™
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. When the device uses
parallel loading, the M bits are programmable and
the output divider is hard-wired for divide by 2 thus providing
a frequency range of 125MHz to 350MHz. In serial programming mode, the M bits are programmable and the output
divider can be set for either divide by 1, 2, 4 or divide by 8,
providing a frequency range of 31.25MHz to 700MHz.
Additionally, the device supports spread spectrum clocking
(SSC) for minimizing Electromagnetic Interference (EMI). The
low cycle-cycle jitter and broad frequency range of the
ICS84314-02 make it an ideal clock generator for a variety of
demanding applications which require high performance.
• Fully integrated PLL
ICS
• Four differential 3.3V or 2.5V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK input
• Output frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• Supports Spread Spectrum Clocking (SSC)
• Parallel interface for programming counter
and output dividers during power-up
• Serial 3 wire interface
• Cycle-to-cycle jitter: 20ps (typical)
• Output skew: TBD
• Output duty cycle: TBD
• Full 3.3V or mixed 3.3V core, 2.5V output operating supply
• 0°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-complaint
packages
XTAL_IN
nP_LOAD
M0
M1
M2
M3
32 31 30 29 28 27 26 25
VCO_SEL
MR
VCO
0
1
÷M
Output Divider N
÷1 Serial Mode
÷2 Parallel/Serial Mode
(Power-up Default)
÷4 Serial Mode
÷8 Serial Mode
÷2
4
M8
5
VEE
6
VCC
7
VCCO
8
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Top View
Q0
nQ0
9 10 11 12 13 14 15 16
Q1
nQ1
22
VCCA
21
S_LOAD
20
S_DATA
19
S_CLOCK
18
MR
17
VCCO
nQ3
PLL
PHASE DETECTOR
M7
ICS84314-02
Q3
÷ 16
3
Q2
1
XTAL_SEL
M6
nQ2
OSC
XTAL_OUT
TEST_CLK
23
Q1
XTAL_IN
24
2
nQ1
0
1
M5
Q0
TEST_CLK
M4
nQ0
XTAL_SEL
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
XTAL_OUT
PIN ASSIGNMENT
VCO_SEL
BLOCK DIAGRAM
Q2
nQ2
Q3
nQ3
CONFIGURATION
INTERFACE
LOGIC
M0:M8
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84314AY-02
www.icst.com/products/hiperclocks.html
1
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes
operation using a 16MHz crystal. Valid PLL loop divider
values for different crystal or input frequencies are defined
in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS84314-02 features a fully integrated PLL and therefore requires no external components for setting the loop
bandwidth. A parallel-resonant, fundamental crystal is used
as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a
16MHz crystal, this provides a 1MHz reference frequency.
The VCO of the PLL operates over a range of 250MHz to
700MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values
of M (either too high or too low), the PLL will not achieve
lock. The output of the VCO is scaled by a divider prior to
being sent to each of the LVPECL output buffers. The divider
provides a 50% output duty cycle.
The programmable features of the ICS84314-02 support
two input modes to program the M divider. The two input
operational modes are parallel and serial. Figure 1 shows
the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 is passed directly to the M divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or until
a serial event occurs. As a result, the M bits can be hardwired to
set the M divider to a specific default state that will automatically
occur during power-up. In parallel mode, the N output divider is
set to 2. In serial mode, the N output divider can be set for either
÷1, ÷2, ÷4 or ÷8. The relationship between the VCO frequency,
the crystal frequency and the M divider is defined as follows:
fxtal x 2M
fVCO =
16
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 16MHz reference are defined as 125 ≤ M ≤ 350. The frequency out
is defined as follows: fout = fVCO x 1 = fxtal x 2M x 1
N 16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA bits
with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
passed directly to the M divider and N output divider on each
rising edge of S_CLOCK.
SERIAL LOADING
S_CLOCK
*NULL *NULL SSC0 **N1
S_DATA
t
S_LOAD
S
t
**N0 M8
M7
M6
M5
M4
M3
M2
M1
M0
H
nP_LOAD
t
S
PARALLEL LOADING
M, N
M0:M8
nP_LOAD
t
S
t
H
S_LOAD
Time
TABLE 1A. N OUTPUT DIVIDER
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
FUNCTION TABLE (SERIAL LOAD)
TABLE 1B. SSC FUNCTION TABLE
N1 Logic Value
0
N0 Logic Value
0
N Output Divide
÷1
SSC0
SSC State
0
Off (Power-up Default)
0
1
1
TBD
1
1
0
1
÷2 (Power-up Default)
÷4
÷8
*NOTE: The NULL timing slot must be observed.
84314AY-02
**NOTE: “N” can only be controlled through serial loading.
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2
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 2. PIN DESCRIPTIONS
Number
1, 2, 5
29, 30, 31
3, 4, 32
Name
M4, M5, M8,
M0, M1, M2
M6, M7, M3
Type
Input
6
VEE
Power
Negative supply pin.
7
VCC
Power
Core power supply pin.
Input
Description
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS / LVTTL interface levels.
Pullup
Output supply pins.
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs Qx to go low and the inver ted
18
MR
Input Pulldown outputs nQx to go high. When logic LOW, the internal dividers and
the outputs are enabled. Asser tion of MR does not affect loaded
M values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
19
S_CLOCK
Input Pulldown
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
20
S_DATA
Input Pulldown
of S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
21
S_LOAD
Input Pulldown
LVCMOS / LVTTL interface levels.
Power
Analog supply pin.
22
VCCA
Selects between the crystal oscillator or test clock as the PLL
reference source. Selects XTAL inputs when HIGH. Selects
23
XTAL_SEL
Input
Pullup
TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
24
TEST_CLK
Input Pulldown Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_IN,
25, 26
Input
XTAL_OUT is the output.
XTAL_OUT
Parallel load input. Determines when data present at M8:M0
27
nP_LOAD
Input Pulldown
is loaded into the M divider. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
28
VCO_SEL
Input
Pullup
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8, 17
9, 10
11, 12
13, 14
15, 16
VCCO
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Power
Output
Output
Output
Output
TABLE 3. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
84314AY-02
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3
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
TABLE 4A. PARALLEL
AND
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR
nP_LOAD
M
S_LOAD
S_CLOCK
S_DATA
H
X
X
X
X
X
Reset. Forces outputs LOW.
L
L
Data
X
X
X
L
↑
Data
L
X
X
L
H
X
L
↑
Data
L
H
X
↑
L
Data
L
H
X
↓
L
Data
Data on M inputs passed directly to the M divider.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
L
H
X
L
X
X
L
H
X
H
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
↑
Data
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
TABLE 4B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
VCO Frequency
(MHz)
M Divide
250
125
256
M8
0
12 8
M7
0
64
M6
1
32
M5
1
16
M4
1
8
M3
1
4
M2
1
2
M1
0
1
M0
1
252
126
0
0
1
1
1
1
1
1
0
254
256
12 7
128
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
•
•
•
•
696
348
698
349
700
35 0
NOTE 1: These M divide values and
frequency of 16MHz.
•
•
•
•
•
•
•
•
•
•
1
0
1
0
1
1
0
1
0
1
1
0
1
0
1
the resulting frequencies correspond to
•
•
•
•
•
•
•
•
1
1
0
0
1
1
0
1
1
1
1
0
cr ystal or TEST_CLK input
TABLE 4C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE (SERIAL PROGRAMMING MODE ONLY)
Input
Output Frequency (MHz)
Q0:Q3, nQ0:nQ3
Minimum
Maximum
250
700
N1 Logic
N0 Logic
N Divide
0
0
1
0
1
1
0
2
4
12 5
62.5
35 0
175
1
1
8
31.25
87.5
84314AY-02
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4
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5 V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
TBD
mA
ICCA
Analog Supply Current
TBD
mA
TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 85°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VCC
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
2.375
2.5
2.625
VCCO
Output Supply Voltage
IEE
Power Supply Current
TBD
mA
ICCA
Analog Supply Current
TBD
mA
84314AY-02
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5
V
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 5C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 85°C
Symbol
Parameter
Test Conditions
VIH
Input High Voltage
VIL
Input Low Voltage
M0:M2, M4, M5, M8, MR,
nP_LOAD, S_CLOCK,
S_DATA, S_LOAD
Input
M
3, M6, M7,
High Current
XTAL_SEL, VCO_SEL
TEST_CLK
M0:M2, M4, M5, M8, MR,
nP_LOAD, S_CLOCK,
Input
S_DATA, S_LOAD
Low Current
M3, M6, M7,
XTAL_SEL, VCO_SEL
IIH
IIL
Minimum
Typical
Maximum
Units
2
VCC + 0.3
V
-0.3
0.8
V
VCC = VIN = 3.465V
150
µA
VCC = VIN = 3.465V
5
µA
VCC = VIN = 3.465V
200
µA
VCC = 3.465V,
VIN = 0V
-5
µA
VCC = 3.465V,
VIN = 0V
-150
µA
TABLE 5D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 85°C
Symbol
Maximum
Units
VOH
Output High Voltage; NOTE 1
Parameter
Test Conditions
Minimum
VCCO - 1.4
Typical
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
1.0
V
VSWING
Peak-to-Peak Output Voltage Swing
0. 6
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. See "Parameter Measurement Information" section,
"Output Load Test Circuit" diagrams.
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
TEST_CLK; NOTE 1
10
40
MHz
XTAL_IN, XTAL_OUT;
Input Frequency
12
40
MHz
fIN
NOTE 1
S_CLOCK
50
MH z
NOTE 1: For the input crystal and reference frequency range, the M value must be set for the VCO to operate within the
250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 167 ≤ M ≤ 466.
Using the maximum frequency of 40MHz, valid values of M are 50 ≤ M ≤ 140.
TABLE 7. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
40
MHz
Fundamental
Frequency
12
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
84314AY-02
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6
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 8A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
Test Conditions
FMAX
Output Frequency Range
t jit(cc)
Cycle-to-Cycle Jitter ; NOTE 1, 3
t jit(per)
Period Jitter, RMS; NOTE 1
t sk(o)
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
tS
Setup Time
tH
Hold Time
Minimum
Typical
31.25
20% to 80%
Maximum
Units
700
MHz
20
ps
TBD
ps
TBD
ps
460
ps
M to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
30
FM
SSC Modulation Frequency; NOTE 4
FMF
SSC Modulation Factor ; NOTE 4
SSCred
Spectral Reduction; NOTE 4
odc
Output Duty Cycle
0.4
7
33.33
kHz
0.6
%
10
dB
50
%
PLL Lock Time
tLOCK
See Parameter Measurement Information section.
NOTE 1: Jitter performance using cr ystal inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Spread Spectrum clocking enabled.
1
ms
Maximum
Units
700
MHz
TABLE 8B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 85°C
Symbol
Parameter
Test Conditions
FMAX
Output Frequency Range
Minimum
Typical
31.25
t jit(cc)
Cycle-to-Cycle Jitter ; NOTE 1, 3
t jit(per)
Period Jitter, RMS; NOTE 1
t sk(o)
Output Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
tS
Setup Time
20% to 80%
20
ps
TBD
ps
TBD
ps
460
ps
M to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
tH
Hold Time
S_CLOCK to S_LOAD
5
FM
SSC Modulation Frequency; NOTE 4
30
FMF
SSC Modulation Factor ; NOTE 4
SSCred
Spectral Reduction; NOTE 4
odc
Output Duty Cycle
tLOCK
PLL Lock Time
ns
33.33
0.4
7
0.6
kHz
%
10
dB
50
%
1
ms
See notes in Table 8A above.
84314AY-02
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7
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
2.8V±0.04V
V CC ,
VCCA, VCCO
Qx
SCOPE
2V
VCC ,
VCCA V
CCO
LVPECL
Qx
SCOPE
LVPECL
VEE
nQx
nQx
VEE
-1.3V ± 0.165V
-0.5V ± 0.125V
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx
nQx
Qx
Qx
➤
nQy
tcycle n
➤
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
➤
tcycle n+1
➤
Qy
t jit(cc) = tcycle n –tcycle n+1
tsk(o)
1000 Cycles
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
VOH
VREF
80%
80%
VSW I N G
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Clock
Outputs
20%
20%
tR
tF
Histogram
Reference Point
Mean Period
(Trigger Edge)
(First edge after trigger)
PERIOD JITTER
OUTPUT RISE/FALL TIME
nQ0:nQ3
Q0:Q3
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
84314AY-02
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8
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84314-02 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
10Ω
VCCA
.01μF
10μF
FIGURE 2. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the TEST_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
84314AY-02
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9
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
CRYSTAL INPUT INTERFACE
The ICS84314-02 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 3 below were determined using a 25MHz, 18pF paral-
lel resonant crystal and were chosen to minimize the ppm
error. The optimum C1 and C2 values can be slightly adjusted
for different board layouts.
XTAL_IN
C1
22p
X1
18pF Parallel Cry stal
XTAL_OUT
C2
22p
ICS84332
Figure 3. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
1
RTT =
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
84314AY-02
125Ω
84Ω
FIGURE 4B. LVPECL OUTPUT TERMINATION
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10
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
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Systems, Inc.
TERMINATION
FOR
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
close to ground level. The R3 in Figure 5A can be eliminated
and the termination is shown in Figure 5C.
2.5V
VCCO=2.5V
2.5V
2.5V
VCCO=2.5V
Zo = 50 Ohm
R1
250
+
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
84314AY-02
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11
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
LAYOUT GUIDELINE
The schematic of the ICS84314-02 layout example used in
this layout guideline is shown in Figure 6A. The ICS84314-02
recommended PCB board layout for this example is shown
in Figure 6B. This layout example is used as a general
guideline. The layout in the actual system will depend on the
selected component types, the density of the components,
the density of the traces, and the stack up of the P.C. board.
Logic Input Pin Examples
C1
X1
C2
Set Logic
Input to
'1'
VCCO
M4
M5
M6
M7
M8
VEE
VCC
VCCO
T_CLK
XTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
VCCO
VCC
C4
0.1u
Set Logic
Input to
'0'
VCC
RU2
Not Install
VCCO
To Logic
Input
pins
R7
10
24
23
22
21
20
19
18
17
VCCA
RD1
Not Install
To Logic
Input
pins
RD2
1K
C11
0.01u
C16
10u
C3
0.1u
9
10
11
12
13
14
15
16
C5
0.1u
RU1
1K
ICS84314_02
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
VCC
VCC
1
2
3
4
5
6
7
8
M3
M2
M1
M0
VCO_SEL
nP_LOAD
X_OUT
X_IN
U1
32
31
30
29
28
27
26
25
VCC
Zo = 50 Ohm
+
Zo = 50 Ohm
-
R2
50
VCC=3.3V
R1
50
VCCO=3.3V
C6 (Option)
0.1u
R3
50
Zo = 50 Ohm
+
Zo = 50 Ohm
-
R5
50
C7 (Option)
0.1u
R4
50
R6
50
FIGURE 6A. SCHEMATIC OF 3.3V/3.3V RECOMMENDED LAYOUT
84314AY-02
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REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
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Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
• The traces with 50Ω transmission lines TL1 and TL2
at FOUT and nFOUT should have equal delay and
run adjacent to each other. Avoid sharp angles on the
clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as
possible to the power pins. If space allows, placing the
decoupling capacitor at the component side is preferred. This
can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via.
• Keep the clock trace on the same layer. Whenever possible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
• To prevent cross talk, avoid routing other signal traces
in parallel with the clock traces. If running parallel traces
is unavoidable, allow more space between the clock
trace and the other signal trace.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the
power (ground) plane and the component power (ground) pins.
• Make sure no other signal trace is routed between the
clock trace pair.
If VCCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the VCCA as possible.
The matching termination resistors R1, R2, R3 and R4
should be located as close to the receiver input pins as
possible. Other termination schemes can also be used but
are not shown in this example.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive
ring back can cause system failure. The trace shape and the
trace delay might be restricted by the available space on the
board and the component location. While routing the traces, the
clock signal traces should be routed first and should be locked
prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the
pins 25 (XTAL_IN) and 26 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid
unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
FIGURE 6B. PCB BOARD LAYOUT FOR ICS84314-02
84314AY-02
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13
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled,
a 30kHz triangle waveform is used with 0.5% down-spread
(+0.0% / -0.5%) from the nominal 200MHz clock frequency.
An example of a triangle frequency modulation profile is shown
in Figure 7A below. The ramp profile can be expressed as:
The ICS84314-02 triangle modulation frequency deviation will
not exceed 0.6% down-spread from the nominal clock frequency (+0.0% / -0.5%). An example of the amount of down
spread relative to the nominal clock frequency can be seen in
the frequency domain, as shown in Figure 7B. The ratio of
this width to the fundamental frequency is typically 0.4%,
and will not exceed 0.6%. The resulting spectral reduction
will be greater than 7dB, as shown in Figure 7B. It is important to note the ICS84314-02 7dB minimum spectral reduction is the component-specific EMI reduction, and will not
necessarily be the same as the system EMI reduction.
• Fnom = Nominal Clock Frequency in Spread OFF mode
(200MHz with 16MHz IN)
• Fm = Nominal Modulation Frequency (30kHz)
• δ = Modulation Factor (0.5% down spread)
➤
(1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t < 1 ,
2 fm
(1 - δ) fnom - 2 fm x δ x fnom x t when 1 < t < 1
2 fm
fm
Δ − 10 dBm
Fnom
B
(1 - δ) Fnom
A
δ = 0.4% ➤
➤
➤
0.5/fm
1/fm
FIGURE 6A. TRIANGLE FREQUENCY MODULATION
FIGURE 6B. 200MHZ CLOCK OUTPUT
IN
FREQUENCY DOMAIN
(A) SPREAD-SPECTRUM OFF
(B) SPREAD-SPECTRUM ON
84314AY-02
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14
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
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Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 9. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84314-02 is: 5051
84314AY-02
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15
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
FOR
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
32 LEAD LQFP
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
1.60
A
A1
0.05
0.15
A2
1.35
1.40
b
0.30
0.37
c
0.09
9.00 BASIC
D1
7.00 BASIC
D2
5.60
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60
e
0.80 BASIC
L
0.45
0°
0.45
0.20
D
θ
1.45
0.60
0.75
7°
0.10
ccc
Reference Document: JEDEC Publication 95, MS-026
84314AY-02
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16
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL
FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 11. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS84314AY-02
ICS84314AY02
32 Lead LQFP
tray
0°C to 85°C
ICS84314AY-02T
ICS84314AY02
32 Lead LQFP
1000 tape & reel
0°C to 85°C
ICS84314AY-02LF
ICS84314A02L
32 Lead "Lead-Free" LQFP
tray
0°C to 85°C
ICS84314AY-02LFT
ICS84314A02L
32 Lead "Lead-Free" LQFP
1000 tape & reel
0°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
84314AY-02
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17
REV. B NOVEMBER 17, 2005