LTC7130 20V 20A Monolithic Buck Converter with Ultralow DCR Sensing DESCRIPTION FEATURES Wide VIN Range: 4.5V to 20V Optimized for Low Duty Cycle Applications nn High Efficiency: Up to 95% nn LTC Proprietary Current Mode Architecture nn High Current Parallel Operation nn Ultralow DCR Current Sensing with Temperature Compensation nn Programmable Output Current Limit nn High Speed Differential Remote Sense Amplifier nn ±0.5% Output Voltage Regulation Accuracy nn Output Short-Circuit Protection with Soft Recovery nn Programmable Soft-Start, Tracking nn Programmable Fixed Frequency: 250kHz to 770kHz nn EXTV CC for Reduced Power Dissipation nn Fault Indicator for Output UV/OV Conditions nn 6.25mm × 7.5mm × 2.22mm BGA Package The LTC®7130 is a current mode synchronous step-down monolithic converter that can deliver up to 20A continuous load current. It employs a unique architecture which enhances the signal-to-noise ratio of the current sense signal, allowing the use of a very low DC resistance power inductor to maximize efficiency in high current applications. This feature also reduces the switching jitter commonly found in low DCR applications. The LTC7130 also includes a high speed differential remote sense amplifier and a programmable current sense limit that can be selected from 10mV to 30mV to set the output current limit up to 20A. In addition, the DCR temperature compensation feature limits the maximum output current precisely over temperature. nn nn The LTC7130 also features a precise 0.6V reference with a guaranteed limit of ±0.5% that provides an accurate output voltage. A 5V to 20V input voltage range supports a wide variety of bus voltages and various types of batteries. APPLICATIONS The LTC7130 is offered in a compact and low profile BGA package available with SnPb/RoHS compliant terminal finishes. DSP, FPGA, ASIC Reference Designs Telecom/Datacom Systems nn Distributed High Power Density Systems nn L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, μModule, Linear Technology and the Linear logo are registered trademarks and No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6177787, 6580258, 6498466, 6611131, patent pending. nn TYPICAL APPLICATION High Efficiency, 1.5V/20A Step-Down Converter with Very Low DCR Sensing 2.2Ω + 470µF INTVCC 4.7µF SVIN INTVCC ITEMP VIN BOOST ILIM 1k SW RUN SNSD+ MODE/PLLIN 220pF ITH LTC7130 SNS– TK/SS 1nF 0.1µF 20k 20k 30.1k CMDSH2-3 SNSA+ EXTVCC DIFFP VFB DIFFN DIFFOUT SGND GND FREQ 2.2Ω 0.1µF 3.09k 220nF 90 0.25µH (0.37mΩ DCR) + VOUT 1.5V 20A 470µF ×2 10 70 60 8 50 VIN = 12V VOUT = 1.5V L = 0.25μH (DCR = 0.37mΩ) EXTVCC = 5V CCM 40 30 220nF 20 619Ω 10 0 121k 12 EFFICIENCY 80 POWER LOSS 0 2 4 6 8 10 12 14 16 18 20 LOAD CURRENT (A) 6 4 POWER LOSS (W) PINS NOT USED IN THIS CIRCUIT: PGOOD CLKOUT 3.01k 14 100 1µF EFFICIENCY (%) VIN = 5V TO 20V Efficiency vs Load Current 2 0 7130 TA01b 7130 TA01a 7130f For more information www.linear.com/LTC7130 1 LTC7130 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) Input Supply Voltage................................... –0.3V to 20V EXTVCC, RUN, PGOOD.................................. –0.3V to 6V SNSD+, SNSA+, SNS– Voltages.............. –0.3V to INTVCC MODE/PLLIN, ILIM, TK/SS, FREQ.......... –0.3V to INTVCC DIFFP, DIFFN.......................................... –0.3V to INTVCC ITEMP, ITH, VFB Voltages....................... –0.3V to INTVCC Operating Junction Temperature Range (Note 2)................................................... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C Peak Solder Reflow Body Temperature.................. 260°C A B C D 1 2 3 NC1 DIFFN TOP VIEW 4 SNSD+ SNS– SNSA+ 5 DIFFP DIFFOUT ITH TK/SS 7 NC2 RUN FREQ MODE/ PLLIN PGOOD ILIM CLKOUT SGND INTVCC 6 VFB ITEMP EXTVCC SVIN GND E F VIN BOOST G GND SW H J BGA PACKAGE 63-PIN (6.25mm × 7.5mm × 2.22mm) TJMAX = 125°C, θJA = 21°C/W, θJC = 10°C/W θJA DERIVED FROM LTC7130 DEMO BOARD, Weight = 0.24g ORDER INFORMATION (http://www.linear.com/product/LTC7130#orderinfo) PART MARKING* PART NUMBER PAD OR BALL FINISH DEVICE FINISH CODE PACKAGE TYPE MSL RATING TEMPERATURE RANGE (SEE NOTE 2) LTC7130EY#PBF SAC305 (RoHS) LTC7130 e1 BGA 3 –40°C to 125°C LTC7130IY#PBF SAC305 (RoHS) LTC7130 e1 BGA 3 –40°C to 125°C • Device temperature grade is indicated by a label on the shipping container. • Pad or ball finish code is per IPC/JEDEC J-STD-609. • Terminal Finish Part Marking: www.linear.com/leadfree • This product is not recommended for second side reflow. For more information, go to www.linear.com/BGA-assy • Recommended BGA PCB Assembly and Manufacturing Procedures: www.linear.com/BGA-assy • BGA Package and Tray Drawings: www.linear.com/packaging • This product is moisture sensitive. For more information, go to: www.linear.com/BGA-assy ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN = 5V unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loops VIN Input Voltage Range (Note 3) 4.5 20 V VOUT Output Voltage Range with Diffamp Low DCR Sensing 0.6 0.6 3.5 5.5 V V 0.603 0.6045 V V without Diffamp and No Low DCR Sensing VFB 2 Regulated Feedback Voltage Current ITH Voltage = 1.2V (Note 4) –40°C to 85°C –40°C to 125°C l l 0.597 0.5955 0.6 0.6 7130f For more information www.linear.com/LTC7130 LTC7130 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN = 5V unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN IFB Feedback Current (Note 4) VREFLNREG Reference Voltage Line Regulation VIN = 4.5V to 20V (Note 4) VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop; ∆ITH Voltage = 1.2V to 0.7V Measured in Servo Loop; ∆ITH Voltage = 1.2V to 1.6V gm Error Amplifier (EA) Transconductance ITH =1.2V, Sink/Source 5µA (Note 4) IQ Input DC Supply Current Normal Mode Shutdown (Note 5) VIN = 15V VIN = 15V, VRUN = 0V VINTVCC Ramping Down UVLO Undervoltage Lockout UVLOHYS UVLO Hysteresis Voltage VFBOVL Feedback Overvoltage Lockout Measured at VFB ISNSD+ SNSD+ Pin Bias Current ISNSA+ SNSA+ Pin Bias Current AVT_SNS Total Sense Signal Gain to Current Comparator l l TYP MAX UNITS –15 –50 nA 0.002 0.02 % 0.01 0.01 0.1 0.1 % % 2 3.4 mmho 3.8 30 50 mA µA 3.75 4.1 V 0.5 0.66 0.68 VSNSD+ = 3.3V 30 100 nA VSNSA+ = 3.3V 1 2 µA l 0.64 V 5 VSENSE(MAX) Maximum Current Sense Threshold –40°C to 125°C ITEMP DCR Temperature Compensation Current ITK/SS Soft-Start Charge Current V V/V l l l l l 8.8 14 19 23.5 28.3 10 15 20 25 30 11.2 16 21 26.5 31.7 mV mV mV mV mV VITEMP = 0.3V l 9 10 11 µA VTK/SS = 0V l 1.0 1.25 1.5 µA VRUN RUN Pin on Threshold Voltage VRUN Rising l 1.1 1.22 1.35 VRUN(HYS) RUN Pin on Hysteresis Voltage tON(MIN) Minimum On-Time VSNS– = 1.8V, ILIM = 0V ILIM = 1/4VINTVCC ILIM = 1/2VINTVCC or Float ILIM = 3/4VINTVCC ILIM = VINTVCC (Note 6) V 80 mV 90 ns INTVCC Linear Regulator VINTVCC VEXTVCC Internal VCC Voltage 6V < VIN < 20V Load Regulation IINTVCC = 0mA to 20mA External VCC Switchover Voltage EXTVCC Ramping Positive EXTVCC Voltage Drop IEXTVCC = 20mA, VEXTVCC = 5.5V 5.25 4.5 5.5 5.75 V 0.5 2 % 4.7 40 EXTVCC Hysteresis V 100 250 mV mV Oscillator and Phase-Locked Loop fNOM Nominal Frequency VFREQ = 1.2V 450 500 550 kHz fLOW Lowest Frequency VFREQ = 0.4V 225 250 275 kHz fHIGH Highest Frequency VFREQ > 2.4V 700 770 850 kHz RMODE/PLLIN MODE/PLLIN Input Resistance IFREQ 250 Frequency Setting Current 9 10 kΩ 11 µA 7130f For more information www.linear.com/LTC7130 3 LTC7130 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN = 5V unless otherwise specified. SYMBOL PARAMETER CLKOUT Phase Relative to the Oscillator Clock CLKOUTHI Clock Output High Voltage CLKOUTLO Clock Output Low Voltage CONDITIONS MIN TYP MAX 180 VINTVCC = 5.5V 4.5 UNITS Deg 5.5 V 0 0.2 V 0.1 0.3 V 2 µA PGOOD Output VPGDLO PGOOD Voltage Low IPGOOD = 2mA IPGD PGOOD Leakage Current VPGOOD = 5.5V VPGD PGOOD Trip VFB with Respect to Set Output Voltage VFB Going Negative VFB Going Positive –10 10 % % Differential Amplifier AV Gain –40°C to 125°C RIN Input Resistance Measured at DIFFP Input VOS Input Offset Voltage VDIFFP = 1.5V, VDIFFOUT = 100µA PSRR Power Supply Rejection Ratio 5V < VIN < 20V (Note 7) IOUT Maximum Sourcing Output Current l 0.997 1 1.003 V/V 2 mV 80 1.5 kΩ 90 dB 2 mA VOUT Maximum Output Voltage VINTVCC = 5.5V, IDIFFOUT = 300µA GBW Gain-Bandwidth Product (Note 7) VINTVCC – 1.4 VINTVCC – 1.1 3 MHz V SR Slew Rate (Note 7) 2 V/µs RDS(ON) RTOP Top Power NMOS OnResistance 7.3 mΩ RBOTTOM Bottom Power NMOS OnResistance 2.1 mΩ Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC7130 is tested under pulsed load conditions such that TJ ≈ TA. The LTC7130E is guaranteed to meet performance specifications from 0°C to 85°C operating junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC7130I is guaranteed to meet performance specifications over the full –40°C to 125°C operating junction temperature range. The maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the package thermal impedance and other environmental factors. The thermal derating curves are based on the LTC7130 demo board. 4 Note 3: When 4.5V ≤ VIN ≤ 5.5V, INTVCC must be tied to VIN. Guaranteed by design. Note 4: The LTC7130 is tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VFB. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: The minimum on-time condition corresponds to the on inductor peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time Considerations in the Applications Information section). Note 7: Guaranteed by design. 7130f For more information www.linear.com/LTC7130 LTC7130 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Load Current and Mode 100 100 90 100 VIN = 12V fSW = 500kHz 90 80 70 70 60 50 VOUT = 1.5V L = 0.25μH (DCR = 0.37mΩ) FRONT PAGE CIRCUIT 40 30 10 0 0.1 1 10 LOAD CURRENT (A) 60 50 30 0 0.1 100 3681 G01 80 50 40 5 30 POWER LOSS (W) 10 60 6 9 11 14 LOAD CURRENT (A) 17 100 3681 G03 20 VOUT AC–COUPLED 100mV/DIV ILOAD 5A/DIV 1A to 15A 20µs/DIV VIN = 12V VOUT = 1.5V FRONT PAGE CIRCUIT POWER LOSS 3 1 10 LOAD CURRENT (A) Load Step (Continuous Conduction Mode) ILOAD 5A/DIV 1A to 15A 20 0 CCM Burst Mode OPERATION PULSE–SKIPPING MODE 0 0.1 3681 G02 VOUT AC–COUPLED 100mV/DIV 70 0 30 (Burst Mode Operation) EFFICIENCY 10 VOUT = 1V L = 0.25μH (DCR = 0.37mΩ) FRONT PAGE CIRCUIT 40 15 VOUT = 1.5V VIN = 20V EXTVCC = 5V 50 10 100 VIN = 12V 60 Load Step (Burst Mode® Operation) vs Load Current 90 1 10 LOAD CURRENT (A) fSW = 400kHz 20 CCM Burst Mode OPERATION PULSE–SKIPPING MODE 10 Efficiency and Power Loss vs Load Current 100 VOUT = 1.5V L = 0.25μH (DCR = 0.37mΩ) FRONT PAGE CIRCUIT 40 20 CCM Burst Mode OPERATION PULSE–SKIPPING MODE EFFICIENCY (%) 80 70 20 EFFICIENCY (%) Efficiency vs Load Current and Mode 80 EFFICIENCY (%) EFFICIENCY (%) 90 Efficiency vs Load Current and Mode VIN = 5V fSW = 500kHz TA = 25°C, unless otherwise noted. 0 7130 G05 20µs/DIV VIN = 12V VOUT = 1.5V FRONT PAGE CIRCUIT 7130 G06 7130 G04 Load Step (Pulse-Skipping Mode) Inductor Current at Light Load Prebiased Output at 1V CONTINUOUS CONDUCTION MODE 10A/DIV VOUT AC–COUPLED 100mV/DIV VOUT 500mV/DIV Burst Mode OPERATION 10A/DIV ILOAD 5A/DIV 1A TO 15A TRACK/SS 500mV/DIV VFB 500mV/DIV PULSE–SKIP MODE 10A/DIV 20µs/DIV VIN = 12V VOUT = 1.5V FRONT PAGE CIRCUIT 7130 G07 VIN = 12V VOUT = 1.5V LOAD = 300mA 10µs/DIV 7130 G08 VIN = 12V VOUT = 1.5V 20ms/DIV 7130 G09 7130f For more information www.linear.com/LTC7130 5 LTC7130 TYPICAL PERFORMANCE CHARACTERISTICS Tracking Up and Down with TK/SS External Ramp CC 6 CURRENT SENSE THRESHOLD (mV) 40 5 INTVCC VOLTAGE (V) VOUT VOUT 0.5V/DIV 0V VIN = 12V VOUT = 1.5V 1Ω LOAD Current Sense Threshold vs ITH Voltage INTVCC Line Regulation VTK/SS VTK/SS 0.2V/DIV TA = 25°C, unless otherwise noted. 20ms/DIV 4 2 7130 G10 1 0 0 5 10 15 INPUT VOLTAGE (V) 30 25 20 15 10 5 0 –5 –10 20 ILIM = 0V ILIM = 1/4 INTVCC ILIM = 1/2 INTVCC ILIM = 3/4 INTVCC ILIM = INTVCC 35 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 VITH (V) 0 7130 G11 7130 G12 Maximum Current Sense Threshold Voltage vs Feedback Voltage (Current Foldback) Maximum Current Sense Threshold vs Common Mode Voltage 35 ILIM = INTVCC 30 ILIM = 3/4 INTVCC 25 ILIM = 1/2 INTVCC 20 ILIM = 1/4 INTVCC 15 ILIM = 0V 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VSENSE COMMON MODE VOLTAGE (V) 4.0 1.8 40 1.6 35 30 25 ILIM = INTVCC 1.4 ILIM = 3/4 INTVCC 1.2 ILIM = 1/2 INTVCC 20 ILIM = 1/4 INTVCC 15 0.2 0.1 0 0.2 0.4 0.5 0.3 FEEDBACK VOLTAGE (V) ON 1.20 OFF 1.15 1.10 1.05 –25 0 25 50 75 TEMPERATURE (°C) 100 125 7130 G16 25 50 75 100 125 Oscillator Frequency vs Temperature 600 VFREQ = 1.2V 575 601.0 550 FREQUENCY (kHz) REGULATED FEEDBACK VOLTAGE (mV) RUN THRESHOLD (V) 1.30 0 7130 G15 601.5 1.35 –25 TEMPERATURE (°C) Regulated Feedback Voltage vs Temperature 1.40 6 0 –50 0.6 7130 G14 Shutdown (RUN) Threshold vs Temperature 1.25 0.8 0.4 5 0 1.0 0.6 ILIM = 0V 10 7130 G13 1.00 –50 TK/SS (µA) MAXIMUM CURRENT SENSE THRESHOLD (mV) CURRENT SENSE THRESHOLD (mV) 40 TK/SS Pull-Up Current vs Temperature 600.5 600.0 599.5 525 500 475 450 599.0 598.5 –50 425 –25 0 25 50 75 TEMPERATURE (°C) 100 125 7130 G17 400 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 7130 G18 7130f For more information www.linear.com/LTC7130 LTC7130 TYPICAL PERFORMANCE CHARACTERISTICS Oscillator Frequency vs Input Voltage Undervoltage Lockout Threshold (INTVCC) vs Temperature VFREQ = 2.5V 800 90 600 VFREQ = 1.2V 500 400 VFREQ = 0V 300 3.9 3.5 3.3 3.1 2.9 100 2.7 5 10 15 FALL 3.7 200 0 SHUTDOWN CURRENT (µA) 4.1 UVLO THRESHOLD (V) 20 –25 INPUT VOLTAGE (V) 0 25 50 75 TEMPERATURE (°C) 100 7130 G19 20 –25 0 25 50 75 TEMPERATURE (°C) 100 3.50 3.25 3.00 2.50 125 0 5 10 15 VOUT = 1.5V fSW = 500kHz DC2341A DEMO BOARD 0 25 50 75 100 AMBIENT TEMPERATURE (°C) 3.2 3.0 2.8 2.4 –50 20 125 7130 G25 –25 0 25 50 75 TEMPERATURE (°C) 100 NO HEAT SINK 20 Thermal Derating V VIN 20V IN == 20V 25 0LFM 200LFM 400LFM 15 10 5 0 VOUT = 1.5V fSW = 500kHz DC2341A DEMO BOARD 0 25 50 75 100 AMBIENT TEMPERATURE (°C) 125 7130 G24 Thermal IN == 12V Thermal Derating Derating V VIN 12V 10 5 3.4 2.6 25 15 20 7130 G23 MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) 20 10 15 INPUT VOLTAGE (V) 3.6 INPUT VOLTAGE (V) 0LFM 200LFM 400LFM 5 3.8 3.75 ThermalDerating DeratingVIN VIN==5V 5V Thermal NO HEAT SINK 0 4.0 7130 G22 25 20 Quiescent Current vs Temperature without EXTVCC 2.75 15 10 –50 30 7130 G21 QUIESCENT CURRENT (mA) QUIESCENT CURRENT (mA) SHUTDOWN CURRENT (µA) 45 25 40 0 125 4.00 30 50 Input Quiescent Current vs Input Voltage without EXTVCC 50 35 60 7130 G20 Shutdown Current vs Temperature 40 80 70 10 2.5 –50 MAXIMUM LOAD CURRENT (A) FREQUENCY (kHz) 100 RISE 4.3 700 0 Shutdown Current vs Input Voltage 4.5 900 0 TA = 25°C, unless otherwise noted. 125 7130 G26 NO HEAT SINK 20 0LFM 200LFM 400LFM 15 10 5 0 VOUT = 1.5V fSW = 500kHz DC2341A DEMO BOARD 0 25 50 75 100 AMBIENT TEMPERATURE (°C) 125 7130 G27 7130f For more information www.linear.com/LTC7130 7 LTC7130 PIN FUNCTIONS FREQ (B7): Oscillator Frequency Control Input. A 10µA current source flows out of this pin. Connecting a resistor between this pin and ground sets a DC voltage which in turn programs the oscillator frequency. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator. RUN (B6): Run Control Input. A voltage above 1.22V turns on the IC. Pulling this pin below 1.14V causes the IC to shut down. There is a 1μA pull-up current for the pin. Once the RUN pin rises above 1.22V, an additional 4.5μA pull-up current is added to the pin. TK/SS (B5): Output Voltage Tracking and Soft-Start Input. An internal soft-start current of 1.25μA charges the external soft-start capacitor connected to this pin. ITH (A5): Current Control Threshold and Error Amplifier Compensation Pin. The current comparator tripping threshold is proportional with this voltage. VFB (A6): Error Amplifier Feedback Input. This pin receives the remotely sensed feedback voltage to set the output voltage through an external resistive divider connected to the DIFFOUT pin or the output. DIFFOUT (A4): Output of Remote Sensing Differential Amplifier. Connect this pin to VFB through a resistive divider to set the desired output voltage. DIFFN (A2): Negative Input of Remote Sensing Differential Amplifier. Connect this pin close to the ground of the output load. DIFFP (A3): Positive Input of Remote Sensing Differential Amplifier. Connect this pin close to the output load. SNSD+ (B1): DC Current Sense Comparator Input. The (+) output to the DC current. Comparator is normally connected to a DC current sensing network with a time constant that matches the bandwidth, L/DCR, of the inductor. 8 SNS– (B2): Negative Current Sense Input. This negative input of the current comparator is to be connected to the output. SNSA+ (C1): AC Current Sense Comparator Input. The (+) output to the AC current comparator is normally connected to a DCR sensing network. When combined with the SNSD+ pin, the DCR sensing network can be skewed to increase the AC ripple voltage by a factor of 5. ILIM (C2): Current Comparator Sense Voltage Limit. Apply a DC voltage to set the maximum current sense threshold for the current comparator. CLKOUT (C3): Clock Output Pin. The CLKOUT signal is 180° out of phase to the rising edge of the IC internal clock. GND (D2, D3, D4, E1, E2, E3, F2, F3, G4, G5, G6, H4, H5, H6, H7, J4, J5, J6, J7): Power Ground. Connect this pin closely to the (–) terminal of CVCC and the (–) terminal of CIN. SW (G1, G2, G3, H1, H2, H3, J1, J2, J3): Switch Node Connection. Connect this pin to the output filter inductor, bottom N-channel MOSFET drain and top N-channel MOSFET source. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. BOOST (E1): Boosted Top Gate Driver Supply. The (+) terminal of the bootstrap capacitor connects to this pin. This pins swings from a diode voltage drop below INTVCC up to VIN + INTVCC. INTVCC (D1): Internal 5.5V Regulator Output. The internal control circuits are powered from this voltage. Decouple this pin to PGND with a 4.7μF low ESR tantalum or ceramic capacitor. 7130f For more information www.linear.com/LTC7130 LTC7130 PIN FUNCTIONS SVIN (D5): Main Input Supply. Decouple this pin to PGND with a capacitor (0.1μF to 1μF). For applications where the main input power is 5V, tie the SVIN and INTVCC pins together. PGOOD (C7): Power Good Indicator Output. Open-drain logic out that is pulled to ground when the output exceeds the 10% regulation window, after the internal 20μs power bad mask timer expires. VIN (E4, E5, E6, E7, F4, F5, F6, F7, G7): Main Input Supply. These pins connect to the drain of the internal power MOSFETs. Decouple this pin to GND with the input capacitance CIN. MODE/PLLIN (C6): Mode Operation or External Clock Synchronization. Connect this pin to SGND to set the continuous mode of operation. Connect to INTVCC to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock signal applied to the pin will force the controller into continuous mode of operation and synchronizes the internal oscillator. EXTVCC (D7): External Supply Voltage Input. Whenever an external voltage supply greater than 4.7V is connected to this pin, an internal switch will close and bypass the internal low dropout regulator, and the external supply will power the IC. Do not exceed 6V on this pin and ensure VIN > VEXTVCC at all times. ITEMP (D6): Temperature DCR Compensation Input. Connect to a NTC (negative tempco) resistor placed near the output inductor to compensate for its DCR change over temperature. Floating this pin or tying it to INTVCC disables the DCR temperature compensation function. SGND (B3, B4, C4, C5): Signal Ground. This is the ground of the controller. Connect compensation components and output setting resistors to this ground. NC (A1, A7): Do not connect. These pins are not connected to anything internally. 7130f For more information www.linear.com/LTC7130 9 LTC7130 FUNCTIONAL BLOCK DIAGRAM MODE/PLLIN ITEMP EXTVCC FREQ VIN 4.7V + + – TEMPSNS F MODE/SYNC DETECT 0.6V 5.5V REG + – PLL-SYNC CIN SVIN INTVCC F BOOST CVCC DB BURST EN CLKOUT OSC FCNT S R Q ICOMP IREV + – CB VOUT SNSA+ SWITCH LOGIC AND ANTISHOOTTHROUGH – + SW ON SNS– INTVCC + RUN OV COUT GND ILIM PGOOD SLOPE COMPENSATION + INTVCC UVLO 0.54V UV – 1 R SNSD+ + ACTIVE CLAMP ITHB AMP – – + – – + + 0.5V SS RUN + EA 0.66V + 1.25µA DIFFAMP 40k RUN + – ITH RC CC1 TK/SS CSS 40k DIFFP 40k – 1µA/5.5µA 1.22V 0.55V 10 VSNS– OV VIN 0.6V REF – + SLEEP VFB SGND RA RB 40k DIFFN DIFFOUT 7130 BD 7130f For more information www.linear.com/LTC7130 LTC7130 OPERATION Main Control Loop The LTC7130 uses a LTC proprietary current sensing, current mode step-down architecture. During normal operation, the top MOSFET is turned on every cycle when the oscillator sets the RS latch, and turned off when the main current comparator, ICMP , resets the RS latch. The peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier, EA. The remote sense amplifier (diffamp) produces a signal equal to the differential voltage sensed across the output capacitor divided down by the feedback divider and re-references it to the local IC ground reference. The VFB pin receives this feedback signal and compares it to the internal 0.6V reference. When the load current increases, it causes a slight decrease in the VFB pin voltage relative to the 0.6V reference, which in turn causes the ITH voltage to increase until the inductor’s average current equals the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator, IREV , or the beginning of the next cycle. The main control loop is shut down by pulling the RUN pin low. Releasing RUN allows an internal 1.0µA current source to pull up the RUN pin. When the RUN pin reaches 1.22V, the main control loop is enabled and the IC is powered up. When the RUN pin is low, all functions are kept in a controlled state. Sensing Signal of Very Low DCR The LTC7130 employs a unique architecture to enhance the signal-to-noise ratio that enables it to operate with a small sense signal of a very low value inductor DCR, 1mΩ or less, to improve power efficiency, and reduce jitter due to the switching noise which could corrupt the signal. The LTC7130 comprises two positive sense pins, SNSD+ and SNSA+, to acquire signals and processes them internally to provide the response as with a DCR sense signal that has a 14dB signal-to-noise ratio improvement. In the meantime, the current limit threshold is still a function of the inductor peak current and its DCR value, and can be accurately set from 10mV to 30mV in a 5mV steps with the ILIM pin. The filter time constant, R1 • C1, of the SNSD+ should match the L/DCR of the output inductor, while the filter at SNSA+ should have a bandwidth of five times larger than SNSD+, R2 • C2 equals R1 • C1/5 (see Figure 3). INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is tied to a voltage less than 4.7V, an internal 5.5V linear regulator supplies INTVCC power from VIN. Ground EXTVCC if it is not used. If EXTVCC is taken above 4.7V, the 5.5V regulator is turned off and an internal switch is turned on connecting EXTVCC to INTVCC. Using the EXTVCC pin allows the INTVCC power to be derived from a high efficiency external source such as a switching regulator output. The top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during the off cycle through an external diode when the top MOSFET turns off. If the input voltage, VIN, decreases to a voltage close to VOUT , the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about one-twelfth of the clock period plus 100ns every third cycle to allow CB to recharge. However, it is recommended that a load be present or the IC operates at low frequency during the dropout transition to ensure CB is recharged. Internal Soft-Start By default, the start-up of the output voltage is normally controlled by an internal soft-start ramp. The internal soft-start ramp connects to the noninverting input of the error amplifier. The VFB pin is regulated to the lower of the error amplifier’s three noninverting inputs (the internal soft-start ramp, the TK/SS pin or the internal 600mV reference). As the ramp voltage rises from 0V to 0.6V over approximately 600µs, the output voltage rises smoothly from its prebiased value to its final set value. Certain applications can result in the start-up of the converter into a non-zero load voltage, where residual charge is stored on the output capacitor at the onset of converter switching. In order to prevent the output from discharging under these conditions, the bottom MOSFET is disabled until soft-start is greater than VFB. 7130f For more information www.linear.com/LTC7130 11 LTC7130 OPERATION Shutdown and Start-Up (RUN and TK/SS Pins) The LTC7130 can be shut down using the RUN pin. Pulling the RUN pin below 1.14V shuts down the main control loop for the controller and most internal circuits, including the INTVCC regulator. Releasing the RUN pin allows an internal 1.0µA current to pull up the pin and enable the controller. Alternatively, the RUN pin may be externally pulled up or driven directly by logic. Be careful not to exceed the absolute maximum rating of 6V on this pin. The start-up of the controller’s output voltage, VOUT , is controlled by the voltage on the TK/SS pin, if the internal soft-start has expired. When the voltage on the TK/SS pin is less than the 0.6V internal reference, the LTC7130 regulates the VFB voltage to the TK/SS pin voltage instead of the 0.6V reference. This allows the TK/SS pin to be used to program a soft-start by connecting an external capacitor from the TK/SS pin to SGND. An internal 1.25µA pull-up current charges this capacitor, creating a voltage ramp on the TK/SS pin. As the TK/SS voltage rises linearly from 0V to 0.6V (and beyond), the output voltage, VOUT , rises smoothly from zero to its final value. Alternatively, the TK/SS pin can be used to cause the start-up of VOUT to track that of another supply. Typically, this requires connecting to the TK/SS pin an external resistor divider from the other supply to ground (see the Applications Information section). When the RUN pin is pulled low to disable the controller, or when INTVCC drops below its undervoltage lockout threshold of 3.75V, the TK/SS pin is pulled low by an internal MOSFET. When in undervoltage lockout, the controller is disabled and the MOSFETs are held off. Light Load Current Operation (Burst Mode Operation, Pulse-Skipping or Continuous Conduction) The LTC7130 can be enabled to enter high efficiency Burst Mode operation, constant-frequency pulse-skipping mode or forced continuous conduction mode. To select forced continuous operation, tie the MODE/PLLIN pin to SGND. To select pulse-skipping mode of operation, tie the MODE/ PLLIN pin to INTVCC. To select Burst Mode operation, float the MODE/PLLIN pin. When the controller is enabled for Burst Mode operation, the peak current in the inductor 12 is set to approximately one-third of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the load current, the error amplifier, EA, will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.5V, the internal sleep signal goes high (enabling “sleep” mode) and both MOSFETs are turned off. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top MOSFET on the next cycle of the internal oscillator. When the controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IREV) turns off the bottom MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. When the MODE/PLLIN pin is connected to INTVCC, the LTC7130 operates in PWM pulse skipping mode at light loads. At very light loads, the current comparator, ICMP , may remain tripped for several cycles and force the top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. 7130f For more information www.linear.com/LTC7130 LTC7130 OPERATION Frequency Selection and Phase-Locked Loop (FREQ and MODE/PLLIN Pins) The selection of switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. If the MODE/PLLIN pin is not being driven by an external clock source, the FREQ pin can be used to program the controller’s operating frequency from 250kHz to 770kHz. There is a precision 10µA current flowing out of the FREQ pin so that the user can program the controller’s switching frequency with a single resistor to SGND. A curve is provided later in the Applications Information section showing the relationship between the voltage on the FREQ pin and switching frequency. A phase-locked loop (PLL) is available on the LTC7130 to synchronize the internal oscillator to an external clock source that is connected to the MODE/PLLIN pin. The PLL loop filter network is integrated inside the LTC7130. The phase‑locked loop is capable of locking any frequency within the range of 250kHz to 770kHz. The frequency setting resistor should always be present to set the controller’s initial switching frequency before locking to the external clock. The controller operates in forced continuous mode when it is synchronized. Sensing the Output Voltage with a Differential Amplifier The LTC7130 includes a low offset, high input impedance, unity-gain, high bandwidth differential amplifier for applications that require true remote sensing. Sensing the load across the load capacitors directly greatly benefits regulation in high current, low voltage applications, where board interconnection losses can be a significant portion of the total error budget. Connect DIFFP to the output load, and DIFFN to the load ground. See Figure 1. The LTC7130 differential amplifier has a typical output slew rate of 2V/µs. The amplifier is configured for unity gain, meaning that the difference between DIFFP and DIFFN is translated to DIFFOUT, relative to SGND. VOUT LTC7130 DIFFP COUT DIFFN + DIFFAMP – DIFFOUT VFB 7130 F01 Figure 1. Differential Amplifier Connection Care should be taken to route the DIFFP and DIFFN PCB traces parallel to each other all the way to the remote sensing points on the board. In addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit. Ideally, the DIFFP and DIFFN traces should be shielded by a low impedance ground plane to maintain signal integrity. The maximum output voltage is limited to 3.5V when using the differential amplifier. If the differential amplifier is not used, tie the feedback divider directly across the output with its center point connected to VFB and ground the SNSD+ pin. In this case the maximum supported VOUT is 5V. Power Good (PGOOD Pin) The PGOOD pin is connected to the open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOOD pin low when the VFB pin voltage is not within ±10% of the 0.6V reference voltage. The PGOOD pin is also pulled low when the RUN pin is below 1.14V or when the LTC7130 is in the soft-start or tracking up phase. When the VFB pin voltage is within the ±10% regulation window, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6V. The PGOOD pin will flag power good immediately when the VFB pin is within the regulation window. However, there is an internal 20µs power-bad mask when the VFB goes out of the window. Inductor DCR Sensing Temperature Compensation (ITEMP Pin) Inductor DCR current sensing provides a lossless method of sensing the instantaneous current. Therefore, it can provide higher efficiency for applications with high output currents. However, the DCR of a copper inductor typically 7130f For more information www.linear.com/LTC7130 13 LTC7130 OPERATION has a positive temperature coefficient. As the temperature of the inductor rises, its DCR value increases. The current limit of the controller is therefore reduced. The LTC7130 offers a method to counter this inaccuracy by allowing the user to place an NTC temperature sensing resistor near the inductor. A constant and precise 10μA current flows out of the ITEMP pin. By connecting a linearized NTC resistor network from the ITEMP pin to SGND, the maximum current sense threshold can be varied over temperature according to the following equation: VSENSEMAX( ADJ) = VSENSE(MAX) • 2.2 – VITEMP 1.5 Where: VSENSEMAX(ADJ) is the maximum adjusted current sense threshold. VSENSE(MAX) is the maximum current sense threshold specified in the Electrical Characteristics table. It is typically 10mV, 15mV, 20mV, 25mV or 30mV, depending on the ILIM pin’s voltage. VITEMP is the voltage of the ITEMP pin. The valid voltage range for DCR temperature compensation on the ITEMP pin is between 0.7V to SGND with 0.7V or above being no DCR temperature correction. An NTC resistor has a negative temperature coefficient, meaning that its resistance decreases as its temperature rises. The VITEMP voltage, therefore, decreases as the inductor’s temperature increases, and in turn the VSENSEMAX(ADJ) 14 will increase to compensate for the inductor’s DCR temperature coefficient. The NTC resistor, however, is non-linear and the user can linearize its value by building a resistor network with regular resistors. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (>10%) as well as other more serious conditions that may overvoltage the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Undervoltage Lockout The LTC7130 has two functions that help protect the controller in case of undervoltage conditions. A precision UVLO comparator constantly monitors the INTVCC voltage to ensure that an adequate gate-drive voltage is present. It locks out the switching action when INTVCC is below 3.75V. To prevent oscillation when there is a disturbance on the INTVCC, the UVLO comparator has 500mV of precision hysteresis. Another way to detect an undervoltage condition is to monitor the VIN supply. Because the RUN pin has a precision turn-on reference of 1.22V, one can use a resistor divider to VIN to turn on the IC when VIN is high enough. An extra 4.5µA of current flows out of the RUN pin once the RUN pin voltage passes 1.22V. The RUN comparator itself has about 80mV of hysteresis. One can program additional hysteresis for the RUN comparator by adjusting the values of the resistive divider. For accurate VIN undervoltage detection, VIN needs to be higher than 4.75V. 7130f For more information www.linear.com/LTC7130 LTC7130 APPLICATIONS INFORMATION The Typical Application on the first page of this data sheet is a basic LTC7130 application circuit. The LTC7130 is designed and optimized for use with a very low DCR value by utilizing a novel approach to reduce the noise sensitivity of the sensing signal by a factor of 14dB. DCR sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. However, as the DCR value drops below 1mΩ, the signal-to-noise ratio is low and current sensing is difficult. LTC7130 uses an LTC proprietary technique to solve this issue. In general, external component selection is driven by the load requirement, and begins with the DCR and inductor value. Next, input and output capacitors are selected. Current Limit Programming The ILIM pin is a 5-level logic input which sets the maximum current limit of the controller. When ILIM is either grounded, floated or tied to INTVCC, the typical value for the maximum current sense threshold will be 10mV, 20mV or 30mV, respectively. Setting ILIM to one-fourth INTVCC and three-fourths INTVCC for maximum current sense thresholds of 15mV and 25mV. Which setting should be used? For the best current limit accuracy, use the highest setting that is applicable to the output requirements. SNSD+, SNSA+ and SNS– Pins Compared to the conventional DCR sensing where there are only 2 sense pins, SENSE+ and SENSE– to sense across the DCR value of an inductor, the LTC7130 is designed to sense very low DCR value inductors in the sub milliohms range by adding an extra current sensing loop with SNSD+ pin. The SNSA+ and SNS– pins are the inputs to the current comparators, while the SNSD+ pin is the input of an internal amplifier. input bias currents of less than 1μA, but there is also a resistance of about 300k from the SNS– pin to ground. The SNS– should be connected directly to VOUT. The SNSD+ pin connects to the filter that has a R1 • C1 time constant matched to L/DCR of the inductor. The SNSA+ pin is connected to the second filter with the time constant one-fifth that of R1 • C1. Care must be taken not to float these pins during normal operation. Filter components, especially capacitors, must be placed close to the LTC7130, and the sense lines should run close together to a Kelvin connection underneath the current sense element (Figure 2). Because the LTC7130 is designed to be used with a very low DCR value to sense inductor current, without proper care, the parasitic resistance, capacitance and inductance will degrade the current sense signal integrity, making the programmed current limit unpredictable. As shown in Figure 3, resistors R1 and R2 are placed close to the inductor and capacitors C1 and C2 are close to the IC pins to prevent noise coupling to the sense signal. When the SNSD+ pin is in use for low DCR sensing, the maximum output voltage allowed is 3.5V due to the limitation of the internal amplifiers’ inputs operating range. If low DCR sensing is not needed, the LTC7130 could also be used like any typical current mode controller by disabling the SNSD+ pin, shorting it to ground. RC filter can be used to sense the output inductor signal and connects to the SNSA+ pin. Its time constant, R • C, is equaled to L/DCR of the output inductor. In these applications, the current limit, VSENSE(MAX), will be five times larger for the specified ILIM, and the operating voltage range of SNSA+ and SNS– is from 0V to 5V. Without using the internal differential amplifier, the output voltage of 5V can be generated as shown in the Typical Application section. TO SENSE FILTER, NEXT TO THE CONTROLLER All the positive sense pins that are connected to the current comparator or the amplifier are high impedance with 7130 F02 COUT INDUCTOR Figure 2. Sense Lines Placement with Inductor DCR 7130f For more information www.linear.com/LTC7130 15 LTC7130 APPLICATIONS INFORMATION VIN SVIN VIN INTVCC BOOST LTC7130 RITEMP INDUCTOR L SW VOUT ITEMP RS 20k R1 SNSD+ RP 100k SGND R2 C1 SNS– RNTC 100k DCR C2 SNSA+ GND 7130 F03 PLACE C1, C2 NEXT TO IC PLACE R1, R2 NEXT TO INDUCTOR R1C1 = 5 • R2C2 Figure 3. Inductor DCR Current Sensing Inductor DCR Sensing ∆IL: Inductor ripple current The LTC7130 is specifically designed for high load current applications requiring the highest possible efficiency; it is capable of sensing the signal of an inductor DCR in the sub milliohm range (Figure 3). The DCR is the DC winding resistance of the inductor’s copper, which is often less than 1mΩ for high current inductors. In high current and low output voltage applications, a conduction loss of a high DCR or a sense resistor will cause a significant reduction in power efficiency. For a specific output requirement, chose the inductor with the DCR that satisfies the maximum desirable sense voltage, and uses the relationship of the sense pin filters to output inductor characteristics as depicted below. L, DCR: Output inductor characteristics DCR = VSENSE(MAX) ∆I IMAX + L 2 L/DCR = R1 • C1 = 5 • R2 • C2 where: VSENSE(MAX): Maximum sense voltage for a given ILIM threshold IMAX: Maximum load current 16 R1, C1: Filter time constant of the SNSD+ pin R2, C2: Filter time constant of the SNSA+ pin To ensure that the load current will be delivered over the full operating temperature range, the temperature coefficient of DCR resistance, approximately 0.4%/°C, should be taken into account. The LTC7130 features a DCR temperature compensation circuit that uses an NTC temperature sensing resistor for this purpose. See the Inductor DCR Sensing Temperature Compensation section for details. Typically, C1 and C2 are selected in the range of 0.047µF to 0.47µF. If C1 and C2 are chosen to be 220nF, and an inductor of 0.25μH with 0.37mΩ DCR is selected, R1 and R2 will be 3.09k and 619Ω respectively. The bias current at SNSD+ and SNSA+ is about 30nA and 500nA respectively, and it causes some small error to the sense signal. There will be some power loss in R1 and R2 that relates to the duty cycle, and will be the most in continuous mode at the maximum input voltage: PLOSS (R) = ( VIN(MAX) – VOUT ) • VOUT R 7130f For more information www.linear.com/LTC7130 LTC7130 APPLICATIONS INFORMATION Ensure that R1 and R2 have a power rating higher than this value. However, DCR sensing eliminates the conduction loss of a sense resistor; it will provide a better efficiency at heavy loads. The actual ripple voltage will be determined by the following equation: ∆VSENSE = VOUT VIN – VOUT • VIN R1• C1• fOSC Use the following equations: V ITEMP100C = ⎛ (100°C – 25°C) • 0.4 ⎞ ⎟ ⎜ IMAX •DCR (Max)• 100 0.7 – 1.5 ⎜ ⎟ VSENSE(MAX) ⎟ ⎜ ⎠ ⎝ = 0.25V Inductor DCR Sensing Temperature Compensation with NTC Thermistor For DCR sensing applications, the temperature coefficient of the inductor winding resistance should be taken into account when the accuracy of the current limit is critical over a wide range of temperature. The main element used in inductors is Copper; that has a positive tempco of approximately 4000ppm/°C. The LTC7130 provides a feature to correct for this variation through the use of the ITEMP pin. There is a 10µA precision current source flowing out of the ITEMP pin. A thermistor with a NTC (negative temperature coefficient) resistance can be used in a network, RITEMP (Figure 3) connected to maintain the current limit threshold constant over a wide operating temperature. The ITEMP voltage range that activates the correction is from 0.7V or less. If floating this pin, its voltage will be at INTVCC potential, about 5.5V. When the ITEMP voltage is higher than 0.7V, the temperature compensation is inactive. The following guidelines will help to choose components for temperature correction. The initial compensation is for 25°C ambient temperature: 1. Set the ITEMP pin resistance to 70k at 25°C. With 10µA flowing out of the ITEMP pin, the voltage on the ITEMP pin will be 0.7V at room temperature. Current limit correction will occur for inductor temperatures greater than 25°C. 2. Calculate the ITEMP pin resistance at the maximum inductor temperature, which is typically 100°C. Since VSENSE(MAX) = IMAX • DCR (Max): VITEMP100C = 25k RITEMP100C = 10µA where: RITEMP100C = ITEMP pin resistance at 100°C; VITEMP100C = ITEMP pin voltage at 100°C; VSENSE(MAX) = Maximum current sense threshold at room temperature; IMAX = Maximum load current; and DCR (Max) = Maximum DCR value. Calculate the values for the NTC network’s parallel and series resistors, RP and RS. A simple method is to graph the following RS versus RP equations with RS on the y-axis and RP on the x-axis. RS = RITEMP25C – RNTC25C||RP RS = RITEMP100C – RNTC100C||RP Next, find the value of RP that satisfies both equations, which will be the point where the curves intersect. Once RP is known, solve for RS. The resistance of the NTC thermistor can be obtained from the vendor’s data sheet in the form of graphs, tabulated data, or formulas. The approximate value for the NTC thermistor for a given temperature can be calculated from the following equation: 1 1 – R = RO • exp B • T + 273 TO + 273 7130f For more information www.linear.com/LTC7130 17 LTC7130 APPLICATIONS INFORMATION where: VITEMP = 10µA • (RS + RP||RNTC); R = Resistance at temperature T, which is in degrees C. RO = Resistance at temperature TO, typically 25°C. B = B-constant of the thermistor. Figure 4 shows a typical resistance curve for a 100k thermistor and the ITEMP pin network over temperature. 10k THERMISTOR RESISTANCE RO = 100k, TO = 25°C B = 4334 FOR 25°C TO 100°C 100 TL is the inductor temperature. The resulting current limit should be greater than or equal to IMAX for inductor temperatures between 25°C and 100°C. With the front page circuit where the current limit setting is 15mV, and inductor DCR is 0.37mΩ, the LTC7130 can deliver 20A of load current from 25°C to 125°C without the need for temperature compensation, however, if another inductor with a higher DCR is chosen, say 0.53mΩ, the current limit can be compensated by using the temperature compensation network. (Figure 5). 30 10 28 RITEMP RS = 20k RP = 100k 1 –50 –25 UNCORRECTED IMAX DCR = 0.53mΩ L = 0.33μH 26 24 0 25 50 75 TEMPERATURE (°C) 100 125 7130 F04 Figure 4. Resistance Versus Temperature for the ITEMP Pin Network and the 100k NTC IMAX (A) RESISTANCE (Ω) 1k IDC(MAX) = Maximum average inductor current; and 22 20 18 16 14 CORRECTED IMAX NOMINAL IMAX RITEMP: RS = 20k RP = 100k THERMISTOR: RO = 100k TO = 25°C B = 4334 FOR 25°C TO 125°C Starting values for the NTC compensation network are: 12 • NTC RO = 100k 10 –50 –25 0 25 50 75 100 125 150 INDUCTOR TEMPERATURE (°C) • RS = 20k 7130 F05 • RP =100k But, the final values should be calculated using the above equations and checked at 25°C and 100°C. After determining the components for the temperature compensation network, check the results by plotting IMAX versus inductor temperature using the following equations: Figure 5. Worst-Case IMAX Versus Inductor Temperature Curve with and without NTC Temperature Compensation VOUT IDC(MAX) = ΔV VSENSEMAX(ADJ) – SENSE 2 0.4 ⎞ ⎛ DCR(MAX) at 25°C • ⎜ 1+ TL(MAX) – 25°C • ⎟ ⎝ 100 ⎠ ( ) where: VSENSEMAX(ADJ) = VSENSE(MAX) • 18 2.2 – VITEMP ; 1.5 RNTC L1 SW1 7130 F06 Figure 6. Thermistor Location. Place the Thermistor Next to the Inductor for Accurate Sensing of the Inductor Temperature, But Keep the ITEMP Pin Away from the Switch Nodes and Gate Drive Traces 7130f For more information www.linear.com/LTC7130 LTC7130 APPLICATIONS INFORMATION For the most accurate temperature detection, place the thermistor next to the output inductor as shown in Figure 6. Care should be taken to keep the ITEMP sense line away from switch nodes. Pre-Biased Output Start-Up There may be situations that require the power supply to start up with a pre-bias on the output capacitors. In this case, it is desirable to start up without discharging that output pre-bias. The LTC7130 can safely power up into a pre-biased output without discharging it. The LTC7130 accomplishes this by turning off both top and bottom MOSFETs until the TK/SS pin voltage and the internal soft-start voltage are above the VFB pin voltage. When VFB is higher than TK/SS or the internal soft-start voltage, the error amp output is railed low. The control loop would like to turn bottom MOSFET on, which would discharge the output. Disabling both MOSFETs will prevent the pre-biased output voltage from being discharged. When TK/SS and the internal soft-start both cross 500mV or VFB, whichever is lower, both MOSFETs are enabled. If the pre-bias is higher than the OV threshold, the bottom MOSFET is turned on immediately to pull the output back into the regulation window. Overcurrent Fault Recovery Upon removal of the short, the output soft starts using the internal soft-start, thus reducing output overshoot. In the absence of this feature, the output capacitors would have been charged at current limit, and in applications with minimal output capacitance this may have resulted in output overshoot. Current limit foldback is not disabled during an overcurrent recovery. The load must step below the folded back current limit threshold in order to restart from a hard short. Thermal Considerations In some applications where the LTC7130 is operated at high ambient temperature, high VIN, high switching frequency and maximum output current load, the heat dissipated may exceed the maximum junction temperature of the part. To avoid the LTC7130 from exceeding the maximum junction temperature, current rating shall be derated in accordance to Ambient Temperature vs Maximum Load Current in the Typical Performance Characteristics. The junction to ambient thermal resistance will vary depending on the size amount of heat sinking copper on the PCB board where the part is mounted, as well as the amount of air flow on the device. Figure 7, 8 and 9 show temperature derating with both heatsink and airflow. Thermal Derating VIN = 5V MAXIMUM LOAD CURRENT (A) When the output of the power supply is loaded beyond its preset current limit, the regulated output voltage will collapse depending on the load. The output may be shorted to ground through a very low impedance path or it may be a resistive short, in which case the output will collapse partially, until the load current equals the preset current limit. The controller will continue to source current into the short. The amount of current sourced depends on the ILIM pin setting and the VFB voltage as shown in the Current Foldback graph in the Typical Performance Characteristics section. 25 WITH HEAT SINK 20 0LFM 200LFM 400LFM 15 10 VIN = 5V VOUT = 1.5V fSW = 500kHz DC2341A DEMO BOARD 5 0 0 25 50 75 100 AMBIENT TEMPERATURE (°C) 125 7130 G07 Figure 7. Temperature Derating Curve Based on the DC2341A Demo Board 7130f For more information www.linear.com/LTC7130 19 LTC7130 APPLICATIONS INFORMATION Thermal Derating VIN = 12V MAXIMUM LOAD CURRENT (A) 25 WITH HEAT SINK 20 Inductor Value Calculation 0LFM 200LFM 400LFM Given the desired input and output voltages, the inductor value and operating frequency, fOSC, directly determine the inductor’s peak-to-peak ripple current: 15 10 0 VIN = 12V VOUT = 1.5V fSW = 500kHz DC2341A DEMO BOARD 5 0 25 50 75 100 AMBIENT TEMPERATURE (°C) 125 7130 F08 Figure 8. Temperature Derating Curve Based on the DC2341A Demo Board Thermal Derating VIN = 20V MAXIMUM LOAD CURRENT (A) 25 WITH HEAT SINK 20 0LFM 200LFM 400LFM 0 25 50 75 100 AMBIENT TEMPERATURE (°C) 125 Figure 9. Temperature Derating Curve Based on the DC2341A Demo Board Tables 1 and 2 provide heat sink and thermal conductive adhesive tape information. Table 1. Heat Sink Manufacturer (Thermally Conductive Adhesive Tape Pre-Attached) HEAT SINK MANUFACTURER PART NUMBER WEBSITE Cool Innovations 3-040404U www.coolinnovations.com Table 2. Thermally Conductive Adhesive Tape Vendor THERMALLY CONDUCTIVE ADHESIVE TAPE MANUFACTURER PART NUMBER WEBSITE 20 T411 VIN – VOUT VOUT • fOSC •IRIPPLE VIN Inductor Core Selection VIN = 20V VOUT = 1.5V fSW = 500kHz DC2341A DEMO BOARD 5 7130 F09 Chomerics It is recommended to choose a ripple current that is about 50% of IOUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: L≈ 10 VOUT VIN – VOUT VIN fOSC • L Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however, requires a large inductor. 15 0 IRIPPLE = www.chomerics.com Once the inductance value is determined, the type of inductor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (VOUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the 7130f For more information www.linear.com/LTC7130 LTC7130 APPLICATIONS INFORMATION maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Required IRMS 1/2 I ≈ MAX ( VOUT ) ( VIN – VOUT ) VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC7130, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. Ceramic capacitors are becoming very popular for small designs but several cautions should be observed. X7R, X5R and Y5V are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions applied. Physically, if the capacitance value changes due to applied voltage change, there is a concomitant piezo effect which results in radiating sound! A load that draws varying current at an audible rate may cause an attendant varying input voltage on a ceramic capacitor, resulting in an audible signal. A secondary issue relates to the energy flowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge. The voltage can increase at a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing! Nevertheless, ceramic capacitors, when properly selected and used, can provide the lowest overall loss due to their extremely low ESR. A small (0.1µF to 1µF) bypass capacitor, CIN, between the chip VIN pin and ground, placed close to the LTC7130, is also suggested. A 2.2Ω to 10Ω resistor placed between CIN and VIN pin provides further isolation. The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR requirement is satisfied the capacitance is adequate for filtering. The steady-state output ripple (∆VOUT) is determined by: 1 ∆VOUT ≈ ∆IRIPPLE ESR + 8fCOUT where f = operating frequency, COUT = output capacitance and ∆IRIPPLE = ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IRIPPLE increases with input voltage. The output ripple will be less than 50mV at maximum VIN with ∆IRIPPLE = 0.4IOUT(MAX) assuming: COUT required ESR < N • RSENSE and COUT > 1 (8f) (RSENSE ) The emergence of very low ESR capacitors in small, surface mount packages makes very small physical implementations possible. The ability to externally compensate the switching regulator loop using the ITH pin allows a much wider selection of output capacitor types. The impedance characteristic of each capacitor type is significantly different than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design. Manufacturers such as Nichicon, Nippon Chemi-Con and Sanyo should be considered for high performance through-hole capacitors. The OS-CON semiconductor dielectric capacitors available from Sanyo and the Panasonic SP surface mount types have a good (ESR)(size) product. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. Ceramic capacitors from AVX, Taiyo Yuden, Murata and TDK offer high capacitance value and very low ESR, especially applicable for low output voltage applications. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several 7130f For more information www.linear.com/LTC7130 21 LTC7130 APPLICATIONS INFORMATION excellent choices are the AVX TPS, AVX TPSV, the KEMET T510 series of surface mount tantalums or the Panasonic SP series of surface mount special polymer capacitors available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo POSCAP, Sanyo OS-CON, Nichicon PL series and Sprague 595D series. Consult the manufacturers for other specific recommendations. Differential Amplifier The LTC7130 has true remote voltage sense capability. The sense connections should be returned from the load, back to the differential amplifier’s inputs through a common, tightly coupled pair of PC traces. The differential amplifier rejects common mode signals capacitively or inductively radiated into the feedback PC traces as well as ground loop disturbances. The LTC7130 diffamp has 80kΩ input impedance on DIFFP. It is designed to be connected directly to the output. The output of the diffamp connects to the VFB pin through a voltage divider, setting the output voltage. External Soft-Start and Tracking The LTC7130 has the ability to either soft-start by itself or track the output of another channel or external supply. When the controller is configured to soft-start by itself, a capacitor may be connected to its TK/SS pin or the internal soft-start may be used. The controller is in the shutdown state if its RUN pin voltage is below 1.14V and its TK/SS pin is actively pulled to ground in this shutdown state. If the RUN pin voltage is above 1.22V, the controller powers up. A soft-start current of 1.25µA then starts to charge the TK/SS soft-start capacitor. Note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the TK/SS pin. Current foldback is disabled during this phase to ensure smooth soft-start or tracking. The soft-start or tracking range is defined to be the voltage range from 0V to 0.6V on the TK/SS pin. The total soft-start time can be calculated as: tSOFTSTART = 0.6 • 22 CSS 1.25µA Regardless of the mode selected by the MODE/PLLIN pin, the controller always starts in discontinuous mode up to TK/SS = 0.5V. Between TK/SS = 0.5V and 0.54V, it will operate in forced continuous mode and revert to the selected mode once TK/SS > 0.54V. The output ripple is minimized during the 40mV forced continuous mode window, ensuring a clean PGOOD signal. When the channel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the TK/SS pin. Therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supply’s voltage. It is only possible to track another supply that is slower than the internal soft-start ramp. Note that the small soft-start capacitor charging current is always flowing, producing a small offset error. To minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. In order to track down another channel or supply after the soft-start phase expires, the LTC7130 is forced into continuous mode of operation as soon as VFB is below the undervoltage threshold of 0.54V regardless of the setting on the MODE/PLLIN pin. However, the LTC7130 should always be set in forced continuous mode tracking down when there is no load. After TK/SS drops below 0.1V, the controller operates in discontinuous mode. The LTC7130 allows the user to program how its output ramps up and down by means of the TK/SS pin. Through these pins, the output can be set up to either coincidentally or ratiometrically track another supply’s output, as shown in Figure 10. In the following discussions, VOUT2 refers to the LTC7130’s output as a slave and VOUT1 refers to another supply output as a master. To implement the coincident tracking in Figure 10a, connect an additional resistive divider to VOUT1 and connect its mid-point to the TK/SS pin of the slave controller. The ratio of this divider should be the same as that of the slave controller’s feedback divider shown in Figure 11a. In this tracking mode, VOUT1 must be set higher than VOUT2. To implement the ratiometric tracking in Figure 10b, the ratio of the VOUT2 divider should be exactly the same as the master controller’s feedback divider shown in Figure 11b . By selecting different resistors, the LTC7130 can achieve different modes of tracking including the two in Figure 10. 7130f For more information www.linear.com/LTC7130 LTC7130 APPLICATIONS INFORMATION VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE VOUT1 VOUT2 VOUT2 TIME TIME (10a) Coincident Tracking 7130 F08 (10b) Ratiometric Tracking Figure 10. Two Different Modes of Output Voltage Tracking VOUT1 VOUT2 TO TK/SS2 PIN R3 R1 R4 R2 TO VFB1 PIN TO VFB2 PIN R3 R4 VOUT1 TO TK/SS2 PIN VOUT2 R1 R2 TO VFB1 PIN TO VFB2 PIN R3 R4 7130 F09 (11a) Coincident Tracking Setup (11b) Ratiometric Tracking Setup Figure 11. Setup and Coincident and Ratiometric Tracking So which mode should be programmed? While either mode in Figure 10 satisfies most practical applications, some trade-offs exist. The ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. Under ratiometric tracking, when the master controller’s output experiences dynamic excursion (under load transient, for example), the slave controller output will be affected as well. For better output regulation, use the coincident tracking mode instead of ratiometric. INTVCC (LDO) and EXTVCC The LTC7130 features a true PMOS LDO that supplies power to INTVCC from the VIN supply. INTVCC powers the gate drivers and much of the LTC7130’s internal circuitry. The LDO regulates the voltage at the INTVCC pin to 5.5V when VIN is greater than 6V. EXTVCC connects to INTVCC through a P-channel MOSFET and can supply the needed power when its voltage is higher than 4.7V. Either of these can supply a peak current of 100mA and must be bypassed to ground with a minimum of 4.7µF ceramic capacitor or low ESR electrolytic capacitor. No matter what type of bulk capacitor is used, an additional 0.1µF ceramic capacitor placed directly adjacent to the INTVCC and PGND pins is highly recommended. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers. High input voltage applications in which the internal MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC7130 to be exceeded. The INTVCC current, which is dominated by the gate charge current, also known as the driver current, may be supplied by either the 5.5V LDO or EXTVCC. When the voltage on the EXTVCC pin is less than 4.5V, the LDO is enabled. The gate charge current is dependent on operating frequency as discussed on Efficiency Considerations section. The power dissipation for the IC in this case is equal to VIN • INTVCC. For example, the LTC7130 INTVCC current is about 27.5mA from a 20V supply in the BGA package not using the EXTVCC: PD = 20V • 27.5mA = 0.55W 7130f For more information www.linear.com/LTC7130 23 LTC7130 APPLICATIONS INFORMATION To reduce the total power loss and prevent the maximum junction temperature from being exceeded due to the IC, the EXTVCC pin can be used to provide MOSFET gate drive and control power. When the voltage applied to EXTVCC rises above 4.7V, the INTVCC LDO is turned off and the EXTVCC is connected to the INTVCC. The EXTVCC remains on as long as the voltage applied to EXTVCC remains above 4.5V. Using the EXTVCC allows the MOSFET driver and control power to be derived from an efficient switching regulator output during normal operation. If more current is required through the EXTVCC than is specified, an external Schottky diode can be added between the EXTVCC and INTVCC pins. Do not apply more than 6V to the EXTVCC pin and make sure that EXTVCC < VIN. in Figure 12 to minimize the voltage drop caused by the gate charge current. This will override the INTVCC linear regulator and will prevent INTVCC from dropping too low due to the dropout voltage. Make sure the INTVCC voltage is at or exceeds the RDS(ON) test voltage for the MOSFET which is typically 4.5V for logic-level devices. Significant efficiency and thermal gains can be realized by powering INTVCC from EXTVCC, since the VIN current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). Tying the EXTVCC pin to a 5V supply reduces power loss of the IC to: Topside MOSFET Driver Supply (CB, DB) PD = 5V • 24.5mA = 0.14W However, for low voltage outputs, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the three possible connections for EXTVCC: 1.EXTVCC grounded. This will cause INTVCC to be powered from the internal LDO resulting in an efficiency penalty of up to 10% at high input voltages. 2.EXTVCC connected to an external supply. If a 5V external supply is available, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. 3.EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 4.7V. For applications where the main input power is 5V, tie the VIN and INTVCC pins together and tie the combined pins to the 5V input with a 1Ω or 2.2Ω resistor as shown 24 LTC7130 VIN INTVCC RVIN 1Ω CINTVCC 4.7µF + 5V CIN 7130 F12 Figure 12. Setup for a 5V Input External bootstrap capacitor, CB, connected to the BOOST pin supplies the gate drive voltages for the topside MOSFET. Capacitor CB in the Functional Diagram is charged though external diode DB from INTVCC when the SW pin is low. When the topside MOSFET is to be turned on, the driver places the CB voltage across the gate source of the MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC – VDB The value of the boost capacitor, CB, needs to store approximately 100 times the gate charge required by the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency. For applications that require high VIN and high output current, in order to minimize SW node ringing and EMI, connect a 2Ω to 10Ω resistor RBOOST in series with the BOOST pin. Make the CB and DB connections on the other side of the resistor. This series resistor helps to 7130f For more information www.linear.com/LTC7130 LTC7130 APPLICATIONS INFORMATION slow down the SW node rise time, limiting the high dl/ dt current through the top MOSFET that causes SW node ringing (see Figure 13). LTC7130 INTVCC BOOST DB RBOOST CBB SW 7130 F13 Figure 13. Using Boost Resistor Setting Output Voltage The LTC7130 output voltage is set by an external feedback resistive divider carefully placed across the DIFFOUT pin, as shown in Figure 14. The regulated output voltage is determined by: R VOUT = 0.6V • 1+ B RA RB ∆IL(SC) = tON(MIN) • VIN L The resulting short-circuit current is: 1/3 VSENSE(MAX) 1 ISC = – ∆IL (SC) 2 RSENSE After a short, or while starting with internal soft-start, make sure that the load current takes the folded-back current limit into account. DIFFOUT LTC7130 maximum sense voltage is progressively lowered from its maximum programmed value to one-third of the maximum value. Foldback current limiting is disabled during the soft-start or tracking up using the TK/SS pin. It is not disabled for internal soft-start. Under short-circuit conditions with very low duty cycles, the LTC7130 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The short circuit ripple current is determined by the minimum on-time tON(MIN) of the LTC7130 (≈90ns), the input voltage and inductor value: CFF VFB Phase-Locked Loop and Frequency Synchronization RA 7130 F14 Figure 14. Setting Output Voltage To improve the frequency response, a feedforward capacitor, CFF , may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. To minimize the effect of the voltage drop caused by high current flowing through board conductance; connect DIFFN and DIFFP sense lines close to the ground and the load output respectively. Fault Conditions: Current Limit and Current Foldback The LTC7130 includes current foldback to help limit load current when the output is shorted to ground. If the output falls below 50% of its nominal output level, then the The LTC7130 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the top MOSFET to be locked to the rising edge of an external clock signal applied to the MODE/PLLIN pin. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter network. There is a precision 10µA current flowing out of the FREQ pin. This allows the user to use a single resistor to SGND to set the switching frequency when no external clock is applied to the MODE/PLLIN pin. The internal switch between the FREQ pin and the integrated PLL filter network is on, allowing the filter network to be pre-charged to the same voltage as the FREQ pin. The 7130f For more information www.linear.com/LTC7130 25 LTC7130 APPLICATIONS INFORMATION relationship between the voltage on the FREQ pin and operating frequency is shown in Figure 15 and specified in the Electrical Characteristics table. If an external clock is detected on the MODE/PLLIN pin, the internal switch mentioned above turns off and isolates the influence of the FREQ pin. Note that the LTC7130 can only be synchronized to an external clock whose frequency is within range of the LTC7130’s internal VCO. This is guaranteed to be between 250kHz and 770kHz. A simplified block diagram is shown in Figure 16. If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the filter network. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down 900 800 the filter network. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the filter network is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor CLP holds the voltage. Typically, the external clock (on the MODE/PLLIN pin) input high threshold is 1.6V, while the input low threshold is 1V. Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest time duration that the LTC7130 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: FREQUENCY (kHz) 700 600 tON(MIN) < VOUT VIN ( f) 500 400 If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the voltage ripple and current ripple will increase. The minimum on-time for the LTC7130 is approximately 90ns, with good PCB layout, minimum 50% inductor current ripple and at least 2mV ripple on the current sense signal. The minimum on-time can be affected by PCB switching noise in the voltage and current loop. As the peak sense voltage decreases the minimum on-time gradually increases to about 110ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. 300 200 100 0 0 0.5 1 1.5 FREQ PIN VOLTAGE (V) 2 2.5 7130 F15 Figure 15. Relationship Between Oscillator Frequency and Voltage at the FREQ Pin 2.4V 5.5V 10µA RSET FREQ MODE/PLLIN EXTERNAL OSCILLATOR DIGITAL SYNC PHASE/ FREQUENCY DETECTOR VCO Efficiency Considerations 7130 F16 Figure 16. Phase-Locked Loop Block Diagram 26 The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine 7130f For more information www.linear.com/LTC7130 LTC7130 APPLICATIONS INFORMATION what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100%–(L1 + L2 + L3 +…) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in LTC7130 circuits: 1) I2R losses, 2) switching and biasing losses, 3) other losses. 1. I2R losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In continuous mode, the average output current flows through inductor L but is “chopped” between the internal top and bottom power MOSFETs. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1-DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus to obtain I2R losses: I2R losses = IOUT2(RSW + RL) 2. The INTVCC current is the sum of the power MOSFET driver and control currents. The power MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a power MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the DC control bias current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the internal top and bottom power MOSFETs and f is the switching frequency. Since INTVCC is a low dropout regulator output powered by VIN, its power loss equals: PLDO = VIN • IINTVCC 3. Other “hidden” losses such as transition loss and copper trace and internal load resistances can account for additional efficiency degradations in the overall power system. It is very important to include these “system” level losses in the design of a system. Transition loss arises from the brief amount of time the top power MOSFET spends in the saturated region during switch node transitions. Other losses including diode conduction losses during dead-time and inductor core losses which generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD • ESR, where ESR is the effective series resistance of COUT . ∆ILOAD also begins to charge or discharge COUT, generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Typical Application circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a 7130f For more information www.linear.com/LTC7130 27 LTC7130 APPLICATIONS INFORMATION rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT , causing a rapid drop in VOUT . No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 17. Check the following in the PC layout: 1.The INTVCC decoupling capacitor should be placed immediately adjacent to the IC between the INTVCC pin and PGND plane. A 1µF ceramic capacitor of the X7R or X5R type is small enough to fit very close to the IC to minimize the ill effects of the large current pulses drawn to drive the bottom MOSFETs. An additional 4.7µF to 10µF of ceramic, tantalum or other very low ESR capacitance is recommended in order to keep the internal IC supply quiet. 2.Place the feedback divider between the + and – terminals of COUT. Route DIFFP and DIFFN with minimum PC trace spacing from the IC to the feedback divider. 3.Are the SNSD+, SNSA+ and SNS– printed circuit traces routed together with minimum PC trace spacing? The filter capacitors between SNSD+, SNSA+ and SNS– should be as close as possible to the pins of the IC. Connect the SNSD+ and SNSA+ pins to the filter resistors as illustrated in Figure 3. L1 VIN SW2 RIN + CIN D1 VOUT DCR SW1 COUT + RL 7130 F17 BOLD LINES INDICATE HIGH, SWITCHING CURRENTS. KEEP LINES TO A MINIMUM LENGTH Figure 17. Branch Current Waveforms 28 7130f For more information www.linear.com/LTC7130 LTC7130 APPLICATIONS INFORMATION 4.Do the (+) plates of CIN connect to the drain of the topside MOSFET as closely as possible? This capacitor provides the pulsed current to the MOSFET. 5.Keep the switching nodes, SW, BOOST away from sensitive small-signal nodes (SNSD+, SNSA+, SNS–, DIFFP, DIFFN, VFB). Ideally the SW, and BOOST printed circuit traces should be routed away and separated from the IC and especially the quiet side of the IC. Separate the high dv/dt traces from sensitive small-signal nodes with ground traces or ground planes. 6.Use a low impedance source such as a logic gate to drive the MODE/PLLIN pin and keep the lead as short as possible. 7.The 47pF to 330pF ceramic capacitor between the ITH pin and signal ground should be placed as close as possible to the IC. Figure 17 illustrates all branch currents in a switching regulator. It becomes very clear after studying the current waveforms why it is critical to keep the high switching current paths to a small physical size. High electric and magnetic fields will radiate from these loops just as radio stations transmit signals. The output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. The left half of the circuit gives rise to the noise generated by a switching regulator. The GND terminations and Schottky diode should return to the bottom plate(s) of the input capacitor(s) with a short isolated PC trace since very high switched currents are present. External OPTI-LOOP® compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure. 8.Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined COUT (–) terminals. The VFB and ITH traces should be as short as possible. The output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. 9.Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC. Design Example As a design example of the front page circuit for a single channel high current regulator, assume VIN = 12V(nominal), VIN = 20V(maximum), VOUT = 1.5V, IMAX = 20A, and f = 500kHz (see front page schematic). The regulated output voltage is determined by: R VOUT = 0.6V • 1+ B RA Using a 20k 1% resistor from the VFB node to ground, the top feedback resistor is (to the nearest 1% standard value) 30.1k. The frequency is set by biasing the FREQ pin to 1.2V (see Figure 15). The inductance value is based on a 50% maximum ripple current assumption (10A). The highest value of ripple current occurs at the maximum input voltage: L= VOUT f • ∆IL(MAX) 1− VOUT V IN(MAX) This design will require 0.25µH. The Würth 744308025, 0.25µH inductor is chosen. At the nominal input voltage (12V), the ripple current will be: ∆IL(NOM) = VOUT V 1− OUT f • L VIN(NOM) It will have 10.5A (52.5%) ripple. The peak inductor current will be the maximum DC value plus one-half the ripple current, or around 25A. 7130f For more information www.linear.com/LTC7130 29 LTC7130 TYPICAL APPLICATIONS The minimum on-time occurs at the maximum VIN, and should not be less than 90ns: tON(MIN) = VOUT VIN(MAX)f = 1.5V = 150ns 20V(500kHz) DCR sensing is used in this circuit. If C1 and C2 are chosen to be 220nF, based on the chosen 0.25µH inductor with 0.37mΩ DCR, R1 and R2 can be calculated as: L = 3.07k DCR • C1 L R2 = = 614Ω DCR • C2 • 5 R1= For a 0.37mΩ DCR, a short-circuit to ground will result in a folded back current of: ISC = (1/ 3) 15mV 1 90ns(20V) – ≈ 10A 0.37mΩ 2 0.25µH COUT is chosen with an equivalent ESR of 4.5mΩ for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR (∆IL) ≈ 0.0045Ω • 10A = 45mVP-P Further reductions in output voltage ripple can be made by placing a 100µF ceramic capacitor across COUT. Choose R1 = 3.09k and R2 = 619Ω. Very Low Output Ripple Converter The maximum DCR of the inductor is 0.4mΩ. The VSENSE(MAX) is calculated as: Although the LTC7130 recommends 50% inductor ripple for most it’s applications, for applications that need very small output ripple, the inductance can be increased to achieve smaller output ripple. VSENSE(MAX) = 25A • DCRMAX = 10mV The current limit is chosen to be 15mV. If temperature variation is considered, please refer to Inductor DCR Sensing Temperature Compensation with NTC Thermistor. 30 The schematic as shown Figure 18 is similar to that of the front page circuit, except that three times the inductance and double the output capacitance are used. The compensation components are changed to maintain the same crossover frequency and phase margin. Figure 19 shows the transient response of 10A load step, and Figure 20 demonstrates that the output voltage ripple is a factor of six smaller than that of typical current mode converters. 7130f For more information www.linear.com/LTC7130 LTC7130 TYPICAL APPLICATIONS VIN 5V TO 20V 2.2Ω 1µF 10µF x2 220µF SVIN INTVCC ILIM ITEMP BOOST 0.22µF RUN SW MODE/PLLIN SNSD+ ITH 26.1k CMDSH3 VIN PINS NOT USED IN THIS CIRCUIT: EXTVCC PGOOD CLKOUT 3.3nF 4.7µF 220pF LTC7130 220nF SNSA+ VFB 20k 30.1k COUT 470µF ×4 220nF FREQ 121k 2.49k VOUT 1.5V 20A SNS– TK/SS 0.1µF 0.72µH, DCR = 1.3mΩ, 744325072 DIFFOUT SGND GND DIFFN 499Ω DIFFP 7130 F18 Figure 18. High Efficiency, 1.5V/15A Step-Down Converter with Very Low Output Ripple Very Low Output Voltage Ripple VOUT TYPICAL FRONT PAGE AC–COUPLED 10mV/DIV VOUT AC–COUPLED 100mV/DIV VOUT LOW RIPPLE FIGURE 18 AC–COUPLED 10mV/DIV ILOAD 5A/DIV 20µs/DIV 7130 F19 2µs/DIV VIN = 12V ILOAD = 1A to 10A Figure 19. Load Step Transient Response 7130 F20 Figure 20. Very Low Output Voltage Ripple 7130f For more information www.linear.com/LTC7130 31 LTC7130 TYPICAL APPLICATIONS High Efficiency, Dual Phase Very Low DCR Sensing 1.2V/40A Step-Down Supply VIN 7V TO 14V 2.2Ω 180µF ×2 INTVCC SW MODE/PLLIN RUN RUN TK/SS 120pF U1 LTC7130 TK/SS 0.1µF 137k 1.8Ω 0.22µF ILIM ITH 2.49k PGOOD BOOST VIN 1/4 VINTVCC ITH CMDSH3 120k PGOOD SVIN U1 PINS NOT USED IN THIS CIRCUIT: EXTVCC PGOOD ITEMP 3.3nF 4.7µF 1µF 10µF ×2 220nF 20k COUT 330µF ×2 VOUT 1.2V 40A SNS– 220nF 619Ω SNSA+ VFB 20k 100µF ×2 3.09k SNSD+ FREQ VFB 0.25µH, DCR = 0.37mΩ, WURTH 744308025 DIFFOUT CLKOUT SGND GND DIFFN DIFFP 2.2Ω SVIN U2 PINS NOT USED IN THIS CIRCUIT: EXTVCC CLKOUT DIFFOUT ITEMP 4.7µF 1µF 10µF ×2 220µF MODE/PLLIN INTVCC PGOOD BOOST VIN ITH RUN RUN 1/4 VINTVCC ILIM ITH 120pF TK/SS TK/SS CMDSH3 PGOOD 1.8Ω 0.22µF SW SNSD+ U2 LTC7130 220nF VFB COUT 330µF ×2 220nF SNSA+ VFB SGND 100µF ×2 SNS– FREQ 137k 3.09k 0.25µH, DCR = 0.37mΩ, WURTH 744308025 GND DIFFN 619Ω DIFFP 7130 TA03 PACKAGE PHOTOGRAPHS 32 7130f For more information www.linear.com/LTC7130 SUGGESTED PCB LAYOUT TOP VIEW 1.60 aaa Z 0.4 ±0.025 Ø 63x 0.80 PACKAGE TOP VIEW E 0.000 4 0.80 PIN “A1” CORNER 1.60 Y Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC7130 3.20 2.40 1.60 0.80 0.000 0.80 1.60 2.40 3.20 X D aaa Z 2.40 2.40 NOM 2.22 0.40 1.82 0.50 0.40 7.50 6.25 0.80 6.40 4.80 0.32 1.50 DIMENSIONS b1 A A2 0.37 1.55 0.15 0.10 0.12 0.15 0.08 MAX 2.37 0.45 1.92 0.55 0.43 NOTES DETAIL B PACKAGE SIDE VIEW TOTAL NUMBER OF BALLS: 63 0.27 1.45 MIN 2.07 0.35 1.72 0.45 0.37 DETAIL A SYMBOL A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee H1 SUBSTRATE A1 ddd M Z X Y eee M Z DETAIL B H2 MOLD CAP ccc Z Z (Reference LTC DWG # 05-08-1988 Rev Ø) Øb (63 PLACES) // bbb Z BGA Package 63-Lead (7.5mm × 6.25mm × 2.22mm) e b 5 G 4 3 e 2 1 DETAIL A PACKAGE BOTTOM VIEW 6 PIN 1 3 SEE NOTES J H G F E D C B A 7 SEE NOTES DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE BALL DESIGNATION PER JESD MS-028 AND JEP95 TRAY PIN 1 BEVEL COMPONENT PIN “A1” 7 ! PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX µModule BGA 63 0914 REV Ø PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu 5. PRIMARY DATUM -Z- IS SEATING PLANE 4 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 F b 7 LTC7130 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC7130#packaging for the most recent package drawings. 7130f 33 LTC7130 TYPICAL APPLICATION 5V/5A Step-Down Converter 2.2Ω VIN 12V 4.7µF 1µF 10µF x2 180µF x2 SVIN PINS NOT USED IN THIS CIRCUIT: ITEMP CLKOUT DIFFOUT INTVCC 28.7k PGOOD BOOST VIN ILIM CMDSH3 2.2Ω SW MODE/PLLIN SNSA+ ITH 2.2nF 120k 100pF 0.1µF 100k LTC7130 1.8µH DCR = 4.05mΩ, COILCRAFT 0.22µF XAL7070-182ME VOUT 5V 5A 1.82k 100µF ×2 220nF TK/SS SNS– FREQ EXTVCC COUT 470µF ×2 147k VFB RUN SNSD+ SGND GND DIFFN DIFFP 20k 7130 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3605/ LTC3605A 20V, 5A Synchronous Step-Down Regulator 4V < VIN < 20V, 0.6V < VOUT < 20V, 96% Max Efficiency, 4mm × 4mm QFN-24 Package LTC3633A LTC3633A-1 Dual Channel 3A, 20V Monolithic Synchronous Step‑Down Regulator 3.6V < VIN < 20V, 0.6V < VOUT < VIN, 95% Max Efficiency, 4mm × 5mm QFN-28 and TSSOP-28 Package LTC3622 17V, Dual 1A Synchronous Step-Down Regulator with Ultralow Quiescent Current 2.7V < VIN < 17V, 0.6V < VOUT < VIN, 95% Max Efficiency, 3mm × 4mm DFN-14 and MSOP-16 Package LTC3613 24V, 15A Monolithic Step-Down Regulator with Differential Output Sensing 4.5V < VIN < 24V, 0.6V < VOUT < 5.5V, 0.67% Output Voltage Accuracy, Valley Current Mode, Programmable from 200kHz to 1MHz, Current Sensing, 7mm × 9mm QFN-56 Package LTC3624 17V, 2A Synchronous Step-Down Regulator with 3.5μA Quiescent Current 2.7V < VIN < 17V, 0.6V < VOUT < VIN, 95% Max Efficiency, 3.5μA IQ, Zero‑Current Shutdown, 3mm × 3mm DFN-8 Package LTM®4639 Low VIN 20A DC/DC μModule® Step-Down Regulator Complete 20A Switch Mode Power Supply, 2.375V < VIN < 7V, 0.6V < VOUT < 5.5V, 1.5% Max Total DC Output Voltage Error, Differential Remote Sense Amp, 15mm × 15mm BGA Package LTM4637 20A DC/DC μModule Step-Down Regulator Complete 20A Switch Mode Power Supply, 4.5V < VIN < 20V, 0.6V < VOUT < 5.5V, 1.5% Max Total DC Output Voltage Error, Differential Remote Sense Amp, 15mm × 15mm BGA or LGA Package 34 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC7130 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC7130 7130f LT 0316 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2016