LT1374 4.5A, 500kHz Step-Down Switching Regulator U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LT ®1374 is a 500kHz monolithic buck mode switching regulator. A 4.5A switch is included on the die along with all the necessary oscillator, control and logic circuitry. High switching frequency allows a considerable reduction in the size of external components. The topology is current mode for fast transient response and good loop stability. Both fixed output voltage and adjustable parts are available. Constant 500kHz Switching Frequency High Power 16-Pin TSSOP Package Available Uses All Surface Mount Components Inductor Size Reduced to 1.8µH Saturating Switch Design: 0.07Ω Effective Supply Current: 2.5mA Shutdown Current: 20µA Cycle-by-Cycle Current Limiting Easily Synchronizable A special high speed bipolar process and new design techniques achieve high efficiency at high switching frequency. Efficiency is maintained over a wide output current range by using the output to bias the circuitry and by utilizing a supply boost capacitor to saturate the power switch. U APPLICATIO S ■ ■ ■ ■ Portable Computers Battery-Powered Systems Battery Chargers Distributed Power The LT1374 is available in standard 7-pin DD, TO-220, fused lead SO-8 and 16-pin exposed pad TSSOP packages. Full cycle-by-cycle short-circuit protection and thermal shutdown are provided. Standard surface mount external parts may be used, including the inductor and capacitors. There is the optional function of shutdown or synchronization. A shutdown signal reduces supply current to 20µA. Synchronization allows an external logic level signal to increase the internal oscillator from 580kHz to 1MHz. , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO 5V Buck Converter Efficiency vs Load Current D2 CMDSH3 OR FMMD914 INPUT 6V TO 25V C3* 10µF TO 50µF VIN + BOOST L1** 5µH OUTPUT** 5V, 4.25A VSW LT1374-5 BIAS DEFAULT = ON SHDN GND SENSE VC CC 1.5nF VOUT = 5V VIN = 10V L = 10µH 95 D1 MBRS330T3 + * RIPPLE CURRENT RATING ≥ IOUT/2 ** INCREASE L1 TO 10µH FOR LOAD CURRENTS ABOVE 3.5A AND TO 20µH ABOVE 4A SEE APPLICATIONS INFORMATION C1 100µF, 10V SOLID TANTALUM 1374 TA01 EFFICIENCY (%) C2 0.27µF 100 90 85 80 75 70 0 0.5 1.0 1.5 2.0 2.5 3.0 LOAD CURRENT (A) 3.5 4.0 1374 TA02 1374fb 1 LT1374 W W W AXI U U ABSOLUTE RATI GS (Note 1) Input Voltage LT1374 ............................................................... 25V LT1374HV .......................................................... 32V BOOST Pin Voltage ................................................. 38V BOOST Pin Above Input Voltage ............................. 15V SHDN Pin Voltage ..................................................... 7V BIAS Pin Voltage ...................................................... 7V FB Pin Voltage (Adjustable Part) ............................ 3.5V FB Pin Current (Adjustable Part) ............................ 1mA SENSE Voltage (Fixed 5V Part) ................................. 7V SYNC Pin Voltage ..................................................... 7V Operating Junction Temperature Range LT1374C ............................................... 0°C to 125° C LT1374I ........................................... – 40°C to 125°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C U U W PACKAGE/ORDER I FOR ATIO FRONT VIEW 7 6 5 4 3 2 1 TAB IS GND FB OR SENSE* BOOST VIN GND VSW SYNC OR SHDN* VC R PACKAGE 7-LEAD PLASTIC DD TJMAX = 125°C, θJA = 30°C/ W WITH PACKAGE SOLDERED TO 0.5 SQUARE INCH COPPER AREA OVER BACKSIDE GROUND PLANE OR INTERNAL POWER PLANE. θJA CAN VARY FROM 20°C/W TO > 40°C/W DEPENDING ON MOUNTING TECHNIQUES GND 1 16 GND NC 2 15 VSW VIN 3 14 VSW VIN 4 13 SYNC BOOST 5 12 SHDN FB/SENSE 6 11 VC NC 7 10 BIAS 8 ORDER PART NUMBER LT1374CR LT1374CR-5 LT1374CR-SYNC LT1374CR-5 SYNC LT1374HVCR LT1374IR LT1374IR-5 LT1374IR-SYNC LT1374IR-5 SYNC LT1374HVIR LT1374CS8 LT1374CS8-5 LT1374CS8-SYNC LT1374CS8-5 SYNC LT1374HVCS8 LT1374IS8 LT1374IS8-5 LT1374IS8-SYNC LT1374IS8-5 SYNC LT1374HVIS8 TOP VIEW VIN 1 9 GND FE16 PACKAGE 16-LEAD PLASTIC TSSOP θJA = 40°C/ W EXPOSED PAD SOLDERED TO GROUND PLANE 8 VSW SYNC 7 OR SHDN* 6 VC BOOST 2 FB OR 3 SENSE* FGND 4 5 BIAS S8 PACKAGE 8-LEAD PLASTIC SO θJA = 80°C/ W WITH FUSED (FGND) GROUND PIN CONNECTED TO GROUND PLANE OR LARGE LANDS ORDER PART NUMBER TOP VIEW GND ORDER PART NUMBER LT1374CFE LT1374IFE TAB IS GND FRONT VIEW 7 6 5 4 3 2 1 FB OR SENSE* BOOST VIN GND VSW SHDN VC T7 PACKAGE 7-LEAD PLASTIC TO-220 S8 PART MARKING 1374 1374I 13745 1374I5 1374SN 374ISN 3745SN 74I5SN 1374HV 1374HVI ORDER PART NUMBER LT1374CT7 LT1374CT7-5 LT1374IT7 LT1374IT7-5 TJMAX = 125°C, θJA = 50°C/ W, θJC = 4°C/ W *Default is the adjustable output voltage device with FB pin and shutdown function. Option -5 replaces FB with SENSE pin for fixed 5V output applications. -SYNC replaces SHDN with SYNC pin for applications requiring synchronization. Consult LTC Marketing for parts specified with wider operating temperature ranges. 1374fb 2 LT1374 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C. VIN = 15V, VC = 1.5V, Boost = VIN + 5V, switch open, unless otherwise noted. PARAMETER Feedback Voltage (Adjustable) CONDITIONS All Conditions ● All Conditions ● Sense Voltage (Fixed 5V) SENSE Pin Resistance Reference Voltage Line Regulation 5V ≤ VIN ≤ 25V (5V ≤ VIN ≤ 32V for LT1374HV) Feedback Input Bias Current Error Amplifier Voltage Gain Error Amplifier Transconductance (Notes 2, 8) ∆I (VC) = ±10µA (Note 8) ● ● VC Pin to Switch Current Transconductance Error Amplifier Source Current Error Amplifier Sink Current VC Pin Switching Threshold VC Pin High Clamp Switch Current Limit Slope Compensation (Note 9) Switch On Resistance (Note 7) MIN 2.39 2.36 4.94 4.90 7 200 1500 1000 VFB = 2.1V or VSENSE = 4.4V VFB = 2.7V or VSENSE = 5.6V Duty Cycle = 0 ● ● 140 140 VC Open, VFB = 2.1V or VSENSE = 4.4V, DC ≤ 50% DC = 80% ISW = 4.5A ● 4.5 TYP 2.42 5.0 10 0.01 0.5 400 2000 5.3 225 225 0.9 2.1 6 0.8 0.07 ● Maximum Switch Duty Cycle VFB = 2.1V or VSENSE = 4.4V ● Switch Frequency VC Set to Give 50% Duty Cycle ● Switch Frequency Line Regulation Frequency Shifting Threshold on FB Pin Minimum Input Voltage (Note 3) Minimum Boost Voltage (Note 4) Boost Current (Note 5) VIN Supply Current (Note 6) BIAS Supply Current (Note 6) Shutdown Supply Current 5V ≤ VIN ≤ 25V, (5V ≤ VIN ≤ 32V for LT1374HV) ∆f = 10kHz 90 86 460 440 ● ● 0.8 ● ISW ≤ 4.5A ISW = 1A ISW = 4.5A VBIAS = 5V VBIAS = 5V VSHDN = 0V, VIN ≤ 25V, VSW = 0V, VC Open ● ● ● ● ● 93 93 500 0 1.0 5.0 2.3 20 90 0.9 3.2 20 ● VSHDN = 0V, VIN ≤ 32V, VSW = 0V, VC Open 30 ● Lockout Threshold Shutdown Thresholds VC Open VC Open Device Shutting Down Device Starting Up Synchronization Threshold Synchronizing Range SYNC Pin Input Resistance Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Gain is measured with a VC swing equal to 200mV above the switching threshold level to 200mV below the upper clamp level. Note 3: Minimum input voltage is not measured directly, but is guaranteed by other tests. It is defined as the voltage where internal bias lines are still ● ● ● 2.3 0.13 0.25 ● 2.38 0.37 0.45 1.5 580 40 MAX 2.45 2.48 5.06 5.10 14 0.03 2 2700 3100 320 320 8.5 0.1 0.13 540 560 0.15 1.3 5.5 3.0 35 140 1.4 4.0 50 75 75 100 2.46 0.60 0.7 2.2 1000 UNITS V V V V kΩ %/V µA µMho µMho A/ V µA µA V V A A Ω Ω % % kHz kHz %/ V V V V mA mA mA mA µA µA µA µA V V V V kHz kΩ regulated so that the reference voltage and oscillator frequency remain constant. Actual minimum input voltage to maintain a regulated output will depend on output voltage and load current. See Applications Information. Note 4: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. 1374fb 3 LT1374 ELECTRICAL CHARACTERISTICS Note 5: Boost current is the current flowing into the boost pin with the pin held 5V above input voltage. It flows only during switch on time. Note 6: VIN supply current is the current drawn when the BIAS pin is held at 5V and switching is disabled. If the BIAS pin is unavailable or open circuit, the sum of VIN and BIAS supply currents will be drawn by the VIN pin. Note 7: Switch on resistance is calculated by dividing VIN to VSW voltage by the forced current (4.5A). See Typical Performance Characteristics for the graph of switch voltage at other currents. Note 8: Transconductance and voltage gain refer to the internal amplifier exclusive of the voltage divider. To calculate gain and transconductance, refer to the SENSE pin on the fixed voltage parts. Divide values shown by the ratio VOUT/2.42. Note 9: Slope compensation is the current subtracted from the switch current limit at 80% duty cycle. See Maximum Output Load Current in the Applications Information section for further details. U W TYPICAL PERFOR A CE CHARACTERISTICS Switch Peak Current Limit Switch Voltage Drop 6.0 125°C SWITCH PEAK CURRENT (A) 350 25°C 300 250 – 40°C 200 150 100 TYPICAL 5.5 5.0 MINIMUM 4.5 4.0 3.0 0 1 2 4 3 SWITCH CURRENT (A) 5 0 20 60 40 DUTY CYCLE (%) Shutdown Pin Bias Current 80 100 2.410 – 50 200 AT 2.38V STANDBY THRESHOLD (CURRENT FLOWS OUT OF PIN) 4 0 –50 –25 25 50 75 100 125 Shutdown Supply Current 25 VSHDN = 0V STANDBY SHUTDOWN PIN VOLTAGE (V) 300 0 1374 G03 2.40 CURRENT REQUIRED TO FORCE SHUTDOWN (FLOWS OUT OF PIN). AFTER SHUTDOWN, CURRENT DROPS TO A FEW µA –25 TEMPERATURE (°C) Standby and Shutdown Thresholds 500 CURRENT (µA) 2.415 1374 G02 1374 G18 8 2.420 3.5 50 400 2.425 INPUT SUPPLY CURRENT (µA) SWITCH VOLTAGE (mV) 400 FEEDBACK VOLTAGE (V) 450 0 Feedback Pin Voltage 2.430 6.5 500 2.36 2.32 0.8 START-UP 0.4 20 15 10 5 SHUTDOWN 50 25 75 0 TEMPERATURE (°C) 100 125 1374 G04 0 –50 –25 0 50 100 25 75 0 JUNCTION TEMPERATURE (°C) 125 1374 G05 0 5 10 15 INPUT VOLTAGE (V) 20 25 1374 G06 1374fb 4 LT1374 U W TYPICAL PERFOR A CE CHARACTERISTICS Shutdown Supply Current Error Amplifier Transconductance VIN = 25V 50 VIN = 10V 40 30 20 3000 2000 2500 200 PHASE GAIN (µMho) TRANSCONDUCTANCE (µMho) 60 Error Amplifier Transconductance 2500 1500 1000 500 150 GAIN 2000 100 VC ( ) COUT 12pF ROUT 200k 1500 VFB 2 × 10–3 1000 ERROR AMPLIFIER EQUIVALENT CIRCUIT 50 PHASE (DEG) INPUT SUPPLY CURRENT (µA) 70 0 10 RLOAD = 50Ω 0 50 0 75 100 25 –50 –25 JUNCTION TEMPERATURE (°C) 0 0.1 0.2 0.3 SHUTDOWN VOLTAGE (V) 0 0.4 125 1k 10k 100k FREQUENCY (Hz) Frequency Foldback 1374 G09 Minimum Input Voltage with 5V Output Switching Frequency 6.4 550 500 540 6.2 FREQUENCY (kHz) 300 200 INPUT VOLTAGE (V) 530 400 SWITCHING FREQUENCY 520 510 500 490 480 470 100 FEEDBACK PIN CURRENT 0.5 1.5 2.0 1.0 FEEDBACK PIN VOLTAGE (V) 5.8 5.6 MINIMUM RUNNING VOLTAGE 5.4 5.2 450 – 50 2.5 5.0 –25 0 25 50 75 100 1 125 10 100 LOAD CURRENT (mA) TEMPERATURE (°C) 1000 1374 G12 1374 G11 1374 G10 Maximum Load Current at VOUT = 10V Maximum Load Current at VOUT = 3.3V Maximum Load Current at VOUT = 5V 4.5 4.5 4.5 VOUT = 10V MINIMUM STARTING VOLTAGE 6.0 460 0 0 –50 10M 1M 1374 G08 1374 G07 SWITCHING FREQUENCY (kHz) OR CURRENT (µA) 500 100 L = 20µH L = 20µH L = 20µH L = 10µH L = 10µH L = 5µH 4.0 3.5 3.5 3.0 3.0 L = 5µH CURRENT (A) 4.0 CURRENT (A) CURRENT (A) L = 10µH 4.0 L = 5µH 3.5 VOUT = 5V VOUT = 3.3V 0 5 10 15 INPUT VOLTAGE (V) 20 25 1374 G13 3.0 0 5 10 15 INPUT VOLTAGE (V) 20 25 1374 G14 0 5 10 15 INPUT VOLTAGE (V) 20 25 1374 G15 1374fb 5 LT1374 U W TYPICAL PERFOR A CE CHARACTERISTICS VC Pin Shutdown Threshold BOOST Pin Current DUTY CYCLE = 100% THRESHOLD VOLTAGE (V) 70 60 50 40 30 20 1.2 1.0 0.8 0 1 3 2 4 SWITCH CURRENT (A) 5 Kool Mµ 0.4 PERMALLOY µ = 125 0.01 0.2 CORE LOSS IS INDEPENDENT OF LOAD CURRENT UNTIL LOAD CURRENT FALLS LOW ENOUGH FOR CIRCUIT TO GO INTO DISCONTINUOUS MODE 0.6 0.4 –50 2 1.2 0.8 ® 10 0 4 TYPE 52 POWDERED IRON 0.1 0.12 0.08 0.04 0.001 –25 0 25 50 75 100 JUNCTION TEMPERATURE (°C) 1374 G16 125 1374 G11 CORE LOSS (% OF 5W LOAD) 80 20 12 8 VOUT = 5V, VIN = 10V, IOUT = 1A SHUTDOWN 90 BOOST PIN CURRENT (mA) Inductor Core Loss 1.0 1.4 CORE LOSS (W) 100 0.02 0 5 10 15 INDUCTANCE (µH) 20 25 1374 G01 U U U PI FU CTIO S FB/SENSE: The feedback pin is the input to the error amplifier which is referenced to an internal 2.42V source. An external resistive divider is used to set the output voltage. The fixed voltage (-5) parts have the divider included on-chip and the FB pin is used as a SENSE pin, connected directly to the 5V output. Three additional functions are performed by the FB pin. When the pin voltage drops below 1.7V, switch current limit is reduced. Below 1.5V the external sync function is disabled. Below 1V, switching frequency is also reduced. See Feedback Pin Function section in Applications Information for details. BOOST: The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar NPN power switch. Without this added voltage, the typical switch voltage loss would be about 1.5V. The additional boost voltage allows the switch to saturate and voltage loss approximates that of a 0.07Ω FET structure. Efficiency improves from 75% for conventional bipolar designs to > 89% for these new parts. VIN: This is the collector of the on-chip power NPN switch. This pin powers the internal circuitry and internal regulator when the BIAS pin is not present. At NPN switch on and off, high dI/dt edges occur on this pin. Keep the external bypass and catch diode close to this pin. All trace inductance on this path will create a voltage spike at switch off, adding to the VCE voltage across the internal NPN. Both VIN 6 pins of the 16-lead TSSOP package must be shorted together on the PC board. GND: The GND pin connection needs consideration for two reasons. First, it acts as the reference for the regulated output, so load regulation will suffer if the “ground” end of the load is not at the same voltage as the GND pin of the IC. This condition will occur when load current or other currents flow through metal paths between the GND pin and the load ground point. Keep the ground path short between the GND pin and the load and use a ground plane when possible. The second consideration is EMI caused by GND pin current spikes. Internal capacitance between the VSW pin and the GND pin creates very narrow (<10ns) current spikes in the GND pin. If the GND pin is connected to system ground with a long metal trace, this trace may radiate excess EMI. Keep the path between the input bypass and the GND pin short. VSW: The switch pin is the emitter of the on-chip power NPN switch. This pin is driven up to the input pin voltage during switch on time. Inductor current drives the switch pin negative during switch off time. Negative voltage is clamped with the external catch diode. Maximum negative switch voltage allowed is – 0.8V. Both VSW pins of the 16-lead TSSOP package must be shorted together on the PC board. 1374fb LT1374 U U U PI FU CTIO S SYNC: (Excludes T7 package) The sync pin is used to synchronize the internal oscillator to an external signal. It is directly logic compatible and can be driven with any signal between 10% and 90% duty cycle. The synchronizing range is equal to initial operating frequency, up to 1MHz. This pin replaces SHDN on -SYNC option parts. See Synchronizing section in Applications Information for details. SHDN: The shutdown pin is used to turn off the regulator and to reduce input drain current to a few microamperes. Actually, this pin has two separate thresholds, one at 2.38V to disable switching, and a second at 0.4V to force complete micropower shutdown. The 2.38V threshold functions as an accurate undervoltage lockout (UVLO). This can be used to prevent the regulator from operating until the input voltage has reached a predetermined level. used for frequency compensation, but can do double duty as a current clamp or control loop override. This pin sits at about 1V for very light loads and 2V at maximum load. It can be driven to ground to shut off the regulator, but if driven high, current must be limited to 4mA. BIAS: (SO-8 and FE16 Packages) The BIAS pin is used to improve efficiency when operating at higher input voltages and light load current. Connecting this pin to the regulated output voltage forces most of the internal circuitry to draw its operating current from the output voltage rather than the input supply. This is a much more efficient way of doing business if the input voltage is much higher than the output. Minimum output voltage setting for this mode of operation is 3.3V. Efficiency improvement at VIN = 20V, VOUT = 5V, and IOUT = 25mA is over 10%. NC: No Connect. Leave floating or solder to any node. VC: The VC pin is the output of the error amplifier and the input of the peak switch current comparator. It is normally W BLOCK DIAGRA The LT1374 is a constant frequency, current mode buck converter. This means that there is an internal clock and two feedback loops that control the duty cycle of the power switch. In addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. A switch cycle starts with an oscillator pulse which sets the RS flip-flop to turn the switch on. When switch current reaches a level set by the inverting input of the comparator, the flip-flop is reset and the switch turns off. Output voltage control is obtained by using the output of the error amplifier to set the switch current trip point. This technique means that the error amplifier commands current to be delivered to the output rather than voltage. A voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt 180° shift will occur. The current fed system will have 90° phase shift at a much lower frequency, but will not have the additional 90° shift until well beyond the LC resonant frequency. This makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response. Most of the circuitry of the LT1374 operates from an internal 2.9V bias line. The bias regulator normally draws power from the regulator input pin, but if the BIAS pin is connected to an external voltage higher than 3V, bias power will be drawn from the external source (typically the regulated output voltage). This will improve efficiency if the BIAS pin voltage is lower than regulator input voltage. High switch efficiency is attained by using the BOOST pin to provide a voltage to the switch driver which is higher than the input voltage, allowing the switch to saturate. This boosted voltage is generated with an external capacitor and diode. Two comparators are connected to the shutdown pin. One has a 2.38V threshold for undervoltage lockout and the second has a 0.4V threshold for complete shutdown. 1374fb 7 LT1374 W BLOCK DIAGRA 0.01Ω INPUT + BIAS* 2.9V BIAS REGULATOR – CURRENT SENSE AMPLIFIER VOLTAGE GAIN = 20 INTERNAL VCC Σ SLOPE COMP BOOST 0.9V 500kHz OSCILLATOR SYNC S + SHUTDOWN COMPARATOR DRIVER CIRCUITRY RS FLIP-FLOP CURRENT COMPARATOR R – Q1 POWER SWITCH VSW – + 0.4V FREQUENCY SHIFT CIRCUIT SHDN 3.5µA FOLDBACK CURRENT LIMIT CLAMP + Q2 – LOCKOUT COMPARATOR ERROR AMPLIFIER gm = 2000µMho VC 2.38V FB + – 2.42V GND *BIAS PIN IS AVAILABLE ONLY ON THE S0-8 AND FE16 PACKAGES 1374 BD Figure 1. Block Diagram U W U U APPLICATIO S I FOR ATIO FEEDBACK PIN FUNCTIONS The feedback (FB) pin on the LT1374 is used to set output voltage and provide several overload protection features. The first part of this section deals with selecting resistors to set output voltage and the remaining part talks about foldback frequency and current limiting created by the FB pin. Please read both parts before committing to a final design. The fixed 5V LT1374-5 has internal divider resistors and the FB pin is renamed SENSE, connected directly to the output. The suggested value for the output divider resistor (see Figure 2) from FB to ground (R2) is 5k or less, and a formula for R1 is shown below. The output voltage error caused by ignoring the input bias current on the FB pin is less than 0.25% with R2 = 5k. A table of standard 1% values is shown in Table 1 for common output voltages. Please read the following if divider resistors are increased above the suggested values. R1 = ( ) R2 VOUT − 2.42 2.42 Table 1 OUTPUT VOLTAGE (V) R2 (kΩ) R1 (NEAREST 1%) (kΩ) % ERROR AT OUTPUT DUE TO DISCREET 1% RESISTOR STEPS 3 4.99 1.21 + 0.23 3.3 4.99 1.82 + 0.08 5 4.99 5.36 + 0.39 6 4.99 7.32 – 0.5 8 4.99 11.5 – 0.04 10 4.99 15.8 + 0.83 12 4.99 19.6 – 0.62 15 4.99 26.1 + 0.52 1374fb 8 LT1374 U U W U APPLICATIONS INFORMATION More Than Just Voltage Feedback foldback operation. Again, it is nearly transparent to the user under normal load conditions. The only loads that may be affected are current source loads which maintain full load current with output voltage less than 50% of final value. In these rare situations the feedback pin can be clamped above 1.5V with an external diode to defeat foldback current limit. Caution: clamping the feedback pin means that frequency shifting will also be defeated, so a combination of high input voltage and dead shorted output may cause the LT1374 to lose control of current limit. The feedback pin is used for more than just output voltage sensing. It also reduces switching frequency and current limit when output voltage is very low (see the Frequency Foldback graph in Typical Performance Characteristics). This is done to control power dissipation in both the IC and in the external diode and inductor during short-circuit conditions. A shorted output requires the switching regulator to operate at very low duty cycles, and the average current through the diode and inductor is equal to the short-circuit current limit of the switch (typically 6A for the LT1374, folding back to less than 3A). Minimum switch on time limitations would prevent the switcher from attaining a sufficiently low duty cycle if switching frequency were maintained at 500kHz, so frequency is reduced by about 5:1 when the feedback pin voltage drops below 1V (see Frequency Foldback graph). This does not affect operation with normal load conditions; one simply sees a gear shift in switching frequency during start-up as the output voltage rises. The internal circuitry which forces reduced switching frequency also causes current to flow out of the feedback pin when output voltage is low. The equivalent circuitry is shown in Figure 2. Q1 is completely off during normal operation. If the FB pin falls below 1V, Q1 begins to conduct current and reduces frequency at the rate of approximately 5kHz/µA. To ensure adequate frequency foldback (under worst-case short-circuit conditions), the external divider Thevinin resistance must be low enough to pull 150µA out of the FB pin with 0.6V on the pin (RDIV ≤ 4k). The net result is that reductions in frequency and current limit are affected by output voltage divider impedance. Although divider impedance is not critical, caution should be used if resistors are increased beyond the suggested values and short-circuit conditions will occur with high input voltage. High frequency pickup will increase and the protection accorded by frequency and current foldback will decrease. In addition to lower switching frequency, the LT1374 also operates at lower switch current limit when the feedback pin voltage drops below 1.7V. Q2 in Figure 2 performs this function by clamping the VC pin to a voltage less than its normal 2.1V upper clamp level. This foldback current limit greatly reduces power dissipation in the IC, diode and inductor during short-circuit conditions. External synchronization is also disabled to prevent interference with LT1374 VSW TO FREQUENCY SHIFTING ERROR AMPLIFIER 1.6V + R5 5k OUTPUT 5V – Q1 2.4V R1 R3 1k R4 1k FB Q2 TO SYNC CIRCUIT VC GND + R2 5k 1374 F02 Figure 2. Frequency and Current Limit Foldback 1374fb 9 LT1374 U U W U APPLICATIONS INFORMATION MAXIMUM OUTPUT LOAD CURRENT Maximum load current for a buck converter is limited by the maximum switch current rating (IP) of the LT1374. This current rating is 4.5A up to 50% duty cycle (DC), decreasing to 3.7A at 80% duty cycle. This is shown graphically in Typical Performance Characteristics and as shown in the formula below: IP = 4.5A for DC ≤ 50% IP = 3.21 + 5.95(DC) – 6.75(DC)2 for 50% < DC < 90% Note that there is less load current available at the higher input voltage because inductor ripple current increases. This is not always the case. Certain combinations of inductor value and input voltage range may yield lower available load current at the lowest input voltage due to reduced peak switch current at high duty cycles. If load current is close to the maximum available, please check maximum available current at both input voltage extremes. To calculate actual peak switch current with a given set of conditions, use: DC = Duty cycle = VOUT/VIN Example: with VOUT = 5V, VIN = 8V; DC = 5/8 = 0.625, and; ISW(MAX) = 3.21 + 5.95(0.625) – 6.75(0.625)2 = 4.3A ISW(PEAK ) = IOUT + ( ) 2(L)(f)(V ) VOUT VIN − VOUT IN Current rating decreases with duty cycle because the LT1374 has internal slope compensation to prevent current mode subharmonic switching. For more details, read Application Note 19. The LT1374 is a little unusual in this regard because it has nonlinear slope compensation which gives better compensation with less reduction in current limit. For lighter loads where discontinuous operation can be used, maximum load current is equal to: Maximum load current would be equal to maximum switch current for an infinitely large inductor, but with finite inductor size, maximum load current is reduced by one-half peak-to-peak inductor current. The following formula assumes continuous mode operation, implying that the term on the right is less than one-half of IP. Example: with L = 1.2µH, VOUT = 5V, and VIN(MAX) = 15V, IOUT(MAX) = IP − Continuous Mode (V )(V − V ) 2(L)(f)(V ) OUT IN OUT IN For the conditions above and L = 3.3µH, IOUT (MAX ) = 4.3 − (5)(8 − 5) () 2 3.3 • 10 − 6 500 • 10 3 8 = 4.3 − 0.57 = 3.73 A At VIN = 15V, duty cycle is 33%, so IP is just equal to a fixed 4.5A, and IOUT(MAX) is equal to: 4.5 − (5)(15 − 5) = 4.5 − 1 = 3.5A 10 ( ) 2 3.3 • 10 − 6 500 • 10 3 15 (IP) (f)(L)(VIN) 2(VOUT )(VIN − VOUT ) 2 IOUT(MAX) = Discontinuous mode 4.5) 500 • 10 1.2 • 10 (15) ( = 1.82A )= 2(5)(15 − 5) 2 IOUT (MAX 3 −6 The main reason for using such a tiny inductor is that it is physically very small, but keep in mind that peak-to-peak inductor current will be very high. This will increase output ripple voltage. If the output capacitor has to be made larger to reduce ripple voltage, the overall circuit could actually wind up larger. CHOOSING THE INDUCTOR AND OUTPUT CAPACITOR For most applications the output inductor will fall in the range of 3µH to 20µH. Lower values are chosen to reduce physical size of the inductor. Higher values allow more output current because they reduce peak current seen by the LT1374 switch, which has a 4.5A limit. Higher values also reduce output ripple voltage, and reduce core loss. Graphs in the Typical Performance Characteristics section show maximum output load current versus inductor size and input voltage. A second graph shows core loss versus inductor size for various core materials. 1374fb LT1374 U U W U APPLICATIONS INFORMATION When choosing an inductor you might have to consider maximum load current, core and copper losses, allowable component height, output voltage ripple, EMI, fault current in the inductor, saturation, and of course, cost. The following procedure is suggested as a way of handling these somewhat complicated and conflicting requirements. 1. Choose a value in microhenries from the graphs of maximum load current and core loss. Choosing a small inductor may result in discontinuous mode operation at lighter loads, but the LT1374 is designed to work well in either mode. Keep in mind that lower core loss means higher cost, at least for closed core geometries like toroids. The core loss graphs show both absolute loss and percent loss for a 5W output, so actual percent losses must be calculated for each situation. Assume that the average inductor current is equal to load current and decide whether or not the inductor must withstand continuous fault conditions. If maximum load current is 0.5A, for instance, a 0.5A inductor may not survive a continuous 4.5A overload condition. Dead shorts will actually be more gentle on the inductor because the LT1374 has foldback current limiting. 2. Calculate peak inductor current at full load current to ensure that the inductor will not saturate. Peak current can be significantly higher than output current, especially with smaller inductors and lighter loads, so don’t omit this step. Powdered iron cores are forgiving because they saturate softly, whereas ferrite cores saturate abruptly. Other core materials fall somewhere in between. The following formula assumes continuous mode of operation, but it errs only slightly on the high side for discontinuous mode, so it can be used for all conditions. IPEAK = IOUT + ( ) 2(f)(L)(V ) VOUT VIN − VOUT IN VIN = Maximum input voltage f = Switching frequency, 500kHz 3. Decide if the design can tolerate an “open” core geometry like a rod or barrel, with high magnetic field radiation, or whether it needs a closed core like a toroid to prevent EMI problems. One would not want an open core next to a magnetic storage media, for instance! This is a tough decision because the rods or barrels are temptingly cheap and small and there are no helpful guidelines to calculate when the magnetic field radiation will be a problem. 4. Start shopping for an inductor (see representative surface mount units in Table 2) which meets the requirements of core shape, peak current (to avoid Table 2 VENDOR/ PART NO. VALUE DC (µH) (Amps) CORE TYPE SERIES CORE RESIS- MATER- HEIGHT TANCE(Ω) IAL (mm) Coiltronics CTX2-1 2 4.1 Tor 0.011 KMµ 4.2 CTX5-4 5 4.4 Tor 0.019 KMµ 6.4 CTX8-4 8 3.5 Tor 0.020 KMµ 6.4 CTX2-1P 2 3.4 Tor 0.014 52 4.2 CTX2-3P 2 4.6 Tor 0.012 52 4.8 CTX5-4P 5 3.3 Tor 0.027 52 6.4 CDRH125 10 4.0 SC 0.025 Fer 6 CDRH125 12 3.5 SC 0.027 Fer 6 CDRH125 15 3.3 SC 0.030 Fer 6 CDRH125 18 3.0 SC 0.034 Fer 6 DT3316-222 2.2 5 SC 0.035 Fer 5.1 DT3316-332 3.3 5 SC 0.040 Fer 5.1 DT3316-472 4.7 3 SC 0.045 Fer 5.1 PE-53650 4 4.8 Tor 0.017 Fer 9.1 PE-53651 5 5.4 Tor 0.018 Fer 9.1 Sumida Coilcraft Pulse PE-53652 9 5.5 Tor 0.022 Fer 10 PE-53653 16 5.1 Tor 0.032 Fer 10 IHSM-4825 2.7 5.1 Open 0.034 Fer 5.6 IHSM-4825 4.7 4.0 Open 0.047 Fer 5.6 IHSM-5832 10 4.3 Open 0.053 Fer 7.1 IHSM-5832 15 3.5 Open 0.078 Fer 7.1 IHSM-7832 22 3.8 Open 0.054 Fer 7.1 Dale Tor = Toroid SC = Semi-closed geometry Fer = Ferrite core material 52 = Type 52 powdered iron core material KMµ = Kool Mµ 1374fb 11 LT1374 U W U U APPLICATIONS INFORMATION saturation), average current (to limit heating), and fault current (if the inductor gets too hot, wire insulation will melt and cause turn-to-turn shorts). Keep in mind that all good things like high efficiency, low profile, and high temperature operation will increase cost, sometimes dramatically. Get a quote on the cheapest unit first to calibrate yourself on price, then ask for what you really want. 5. After making an initial choice, consider the secondary things like output voltage ripple, second sourcing, etc. Use the experts in the Linear Technology’s applications department if you feel uncertain about the final choice. They have experience with a wide range of inductor types and can tell you about the latest developments in low profile, surface mounting, etc. Output Capacitor The output capacitor is normally chosen by its Effective Series Resistance (ESR), because this is what determines output ripple voltage. At 500kHz, any polarized capacitor is essentially resistive. To get low ESR takes volume, so physically smaller capacitors have high ESR. The ESR range for typical LT1374 applications is 0.05Ω to 0.2Ω. A typical output capacitor is an AVX type TPS, 100µF at 10V, with a guaranteed ESR less than 0.1Ω. This is a “D” size surface mount solid tantalum capacitor. TPS capacitors are specially constructed and tested for low ESR, so they give the lowest ESR for a given volume. The value in microfarads is not particularly critical, and values from 22µF to greater than 500µF work well, but you cannot cheat mother nature on ESR. If you find a tiny 22µF solid tantalum capacitor, it will have high ESR, and output ripple voltage will be terrible. Table 3 shows some typical solid tantalum surface mount capacitors. Table 3. Surface Mount Solid Tantalum Capacitor ESR and Ripple Current E Case Size ESR (Max., Ω ) Ripple Current (A) AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1 AVX TAJ 0.7 to 0.9 0.4 0.1 to 0.3 0.7 to 1.1 0.2 (typ) 0.5 (typ) D Case Size AVX TPS, Sprague 593D C Case Size AVX TPS Many engineers have heard that solid tantalum capacitors are prone to failure if they undergo high surge currents. This is historically true, and type TPS capacitors are specially tested for surge capability, but surge ruggedness is not a critical issue with the output capacitor. Solid tantalum capacitors fail during very high turn-on surges, which do not occur at the output of regulators. High discharge surges, such as when the regulator output is dead shorted, do not harm the capacitors. Unlike the input capacitor, RMS ripple current in the output capacitor is normally low enough that ripple current rating is not an issue. The current waveform is triangular with a typical value of 200mARMS. The formula to calculate this is: Output Capacitor Ripple Current (RMS): IRIPPLE(RMS) = ( )( (L)(f)(V ) 0.29 VOUT VIN − VOUT ) IN Ceramic Capacitors Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. These are tempting for switching regulator use because of their very low ESR. Unfortunately, the ESR is so low that it can cause loop stability problems. Solid tantalum capacitor’s ESR generates a loop “zero” at 5kHz to 50kHz that is instrumental in giving acceptable loop phase margin. Ceramic capacitors remain capacitive to beyond 300kHz and usually resonate with their ESL before ESR becomes effective. They are appropriate for input bypassing because of their high ripple current ratings and tolerance of turn-on surges. Linear Technology plans to issue a design note on the use of ceramic capacitors in the near future. OUTPUT RIPPLE VOLTAGE Figure 3 shows a typical output ripple voltage waveform for the LT1374. Ripple voltage is determined by the high frequency impedance of the output capacitor, and ripple current through the inductor. Peak-to-peak ripple current through the inductor into the output capacitor is: 1374fb 12 LT1374 U W U U APPLICATIONS INFORMATION IP-P (V )(V − V ) = (V )(L)(f) OUT IN CATCH DIODE OUT IN For high frequency switchers, the sum of ripple current slew rates may also be relevant and can be calculated from: Σ dI VIN = dt L Peak-to-peak output ripple voltage is the sum of a triwave created by peak-to-peak ripple current times ESR, and a square wave created by parasitic inductance (ESL) and ripple current slew rate. Capacitive reactance is assumed to be small compared to ESR or ESL. ( )( ) ( ) VRIPPLE = IP-P ESR + ESL Σ dI dt Example: with VIN =10V, VOUT = 5V, L = 10µH, ESR = 0.1Ω, ESL = 10nH: (5)(10 − 5) = 0.5A 10 10 • 10 − 6 500 • 103 dI 10 = 10 6 Σ = dt 10 • 10 − 6 VRIPPLE = 0.5A 0.1 + 10 • 10 − 9 10 6 = 0.05 + 0.01 = 60mVP-P IP-P = ( ) The suggested catch diode (D1) is a 1N5821 Schottky, or its Motorola equivalent, MBR330. It is rated at 3A average forward current and 30V reverse voltage. Typical forward voltage is 0.5V at 3A. The diode conducts current only during switch off time. Peak reverse voltage is equal to regulator input voltage. Average forward current in normal operation can be calculated from: ID(AVG) = ) VIN This formula will not yield values higher than 3A with maximum load current of 4.25A unless the ratio of input to output voltage exceeds 3.4:1. The only reason to consider a larger diode is the worst-case condition of a high input voltage and overloaded (not shorted) output. Under shortcircuit conditions, foldback current limit will reduce diode current to less than 2.6A, but if the output is overloaded and does not fall to less than 1/3 of nominal output voltage, foldback will not take effect. With the overloaded condition, output current will increase to a typical value of 5.7A, determined by peak switch current limit of 6A. With VIN = 15V, VOUT = 4V (5V overloaded) and IOUT = 5.7A: ID(AVG) = ( )( ) ( IOUT VIN − VOUT ( ) = 4.18A 5.7 15 − 4 15 This is safe for short periods of time, but it would be prudent to check with the diode manufacturer if continuous operation under these conditions must be tolerated. BOOST␣ PIN␣ CONSIDERATIONS VOUT AT IOUT = 1A 20mV/DIV VOUT AT IOUT = 50mA INDUCTOR CURRENT AT IOUT = 1A 0.5A/DIV 0.5µs/DIV 1374 F03 INDUCTOR CURRENT AT IOUT = 50mA Figure 3. LT1374 Ripple Voltage Waveform For most applications, the boost components are a 0.27µF capacitor and a FMMD914 diode. The anode is connected to the regulated output voltage and this generates a voltage across the boost capacitor nearly identical to the regulated output. In certain applications, the anode may instead be connected to the unregulated input voltage. This could be necessary if the regulated output voltage is very low (< 3V) or if the input voltage is less than 5V. Efficiency is not affected by the capacitor value, but the capacitor should have an ESR of less than 1Ω to ensure 1374fb 13 LT1374 U W U U APPLICATIONS INFORMATION that it can be recharged fully under the worst-case condition of minimum input voltage. Almost any type of film or ceramic capacitor will work fine. CMIN = (I OUT / 50 ( f )( V )(V OUT WARNING! Peak voltage on the BOOST pin is the sum of unregulated input voltage plus the voltage across the boost capacitor. This normally means that peak BOOST pin voltage is equal to input voltage plus output voltage, but when the boost diode is connected to the regulator input, peak BOOST pin voltage is equal to twice the input voltage. Be sure that BOOST pin voltage does not exceed its maximum rating. OUT / VIN − 3V ) ) f = Switching frequency VOUT = Regulated output voltage VIN = Minimum input voltage This formula can yield capacitor values substantially less than 0.27µF, but it should be used with caution since it does not take into account secondary factors such as capacitor series resistance, capacitance shift with temperature and output overload. For nearly all applications, a 0.27µF boost capacitor works just fine, but for the curious, more details are provided here. The size of the boost capacitor is determined by switch drive current requirements. During switch on time, drain current on the capacitor is approximately IOUT/ 50. At peak load current of 4.25A, this gives a total drain of 85mA. Capacitor ripple voltage is equal to the product of on time and drain current divided by capacitor value; ∆V = (tON)(85mA/C). To keep capacitor ripple voltage to less than 0.6V (a slightly arbitrary number) at the worstcase condition of tON = 1.8µs, the capacitor needs to be 0.27µF. Boost capacitor ripple voltage is not a critical parameter, but if the minimum voltage across the capacitor drops to less than 3V, the power switch may not saturate fully and efficiency will drop. An approximate formula for absolute minimum capacitor value is: SHUTDOWN FUNCTION AND UNDERVOLTAGE LOCKOUT Figure 4 shows how to add undervoltage lockout (UVLO) to the LT1374. Typically, UVLO is used in situations where the input supply is current limited, or has a relatively high source resistance. A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. UVLO prevents the regulator from operating at source voltages where these problems might occur. RFB LT1374 IN INPUT OUTPUT VSW 2.38V + STANDBY RHI – 3.5µA + SHDN + TOTAL SHUTDOWN C1 RLO 0.4V – GND 1374 F04 Figure 4. Undervoltage Lockout 1374fb 14 LT1374 U U W U APPLICATIONS INFORMATION Threshold voltage for lockout is about 2.38V, slightly less than the internal 2.42V reference voltage. A 3.5µA bias current flows out of the pin at threshold. This internally generated current is used to force a default high state on the shutdown pin if the pin is left open. When low shutdown current is not an issue, the error due to this current can be minimized by making RLO 10k or less. If shutdown current is an issue, RLO can be raised to 100k, but the error due to initial bias current and changes with temperature should be considered. ( ) input rises back to 13.5V. ∆V is therefore 1.5V and VIN = 12V. Let RLO = 25k. ) ] 2.38 − 25k (3.5µA) 25k (10.41) = = 114k RHI = [ ( 25k 12 − 2.38 1.5 / 5 + 1 + 1.5 2.29 RFB = 114k 5 / 1.5 = 380k ( ) RLO = 10k to 100k 25k suggested RHI = ( RLO VIN − 2.38V ( ) SWITCH NODE CONSIDERATIONS ) 2.38V − RLO 3.5 µA VIN = Minimum input voltage Keep the connections from the resistors to the shutdown pin short and make sure that interplane or surface capacitance to the switching nodes are minimized. If high resistor values are used, the shutdown pin should be bypassed with a 1000pF capacitor to prevent coupling problems from the switch node. If hysteresis is desired in the undervoltage lockout point, a resistor RFB can be added to the output node. Resistor values can be calculated from: RHI = [ ( ) RLO VIN − 2.38 ∆V / VOUT + 1 + ∆V ( )( ( 2.38 − R2 3.5µA RFB = RHI VOUT / ∆V ) ) ] 25k suggested for RLO VIN = Input voltage at which switching stops as input voltage descends to trip level ∆V = Hysteresis in input voltage level Example: output voltage is 5V, switching is to stop if input voltage drops below 12V and should not restart unless For maximum efficiency, switch rise and fall times are made as short as possible. To prevent radiation and high frequency resonance problems, proper layout of the components connected to the switch node is essential. B field (magnetic) radiation is minimized by keeping catch diode, switch pin, and input bypass capacitor leads as short as possible. E field radiation is kept low by minimizing the length and area of all traces connected to the switch pin and BOOST pin. A ground plane should always be used under the switcher circuitry to prevent interplane coupling. A suggested layout for the critical components is shown in Figure 5. Note that the feedback resistors and compensation components are kept as far as possible from the switch node. Also note that the high current ground path of the catch diode and input capacitor are kept very short and separate from the analog ground line. The high speed switching current path is shown schematically in Figure 6. Minimum lead length in this path is essential to ensure clean switching and low EMI. The path including the switch, catch diode, and input capacitor is the only one containing nanosecond rise and fall times. If you follow this path on the PC layout, you will see that it is irreducibly short. If you move the diode or input capacitor away from the LT1374, get your resumé in order. The other paths contain only some combination of DC and 500kHz triwave, so are much less critical. 1374fb 15 LT1374 U W U U APPLICATIONS INFORMATION CONNECT TO GROUND PLANE MINIMIZE LT1374, C3, D1 LOOP VIN C3 D1 C5 GND C6 VOUT 1 GND C1 CONNECT TO GROUND PLANE R3 TAKE OUTPUT DIRECTLY FROM END OF OUTPUT CAPACITOR L1 U1 D2 PLACE FEEDTHROUGHS AROUND GND PIN FOR GOOD THERMAL CONDUCTIVITY KEEP FB AND VC COMPONENTS AWAY FROM HIGH FREQUENCY, HIGH CURRENT COMPONENTS R2 C4 KELVIN SENSE VOUT 13745 F05a Figure 5a. Suggested Layout (Topside Only Shown) SO-8 1374fb 16 LT1374 U W U U APPLICATIONS INFORMATION SOLDER EXPOSED PAD AND USE FEEDTHROUGHS FOR BETTER THERMAL CONDUCTIVITY KEEP FB AND VC COMPONENTS AWAY FROM HIGH FREQUENCY, HIGH CURRENT COMPONENTS GND VIN C4 C2 R3 KELVIN SENSE OUTPUT C3 D2 R2 R1 C1 VOUT D1 C1 1374 F05b Figure 5b. Suggested Layout (Topside Only Shown) TSSOP 1374fb 17 LT1374 U U W U APPLICATIONS INFORMATION MINIMIZE LT1374 C3, D1 LOOP CONNECT TO GND PLANE C3 D1 VOUT VIN TAKE OUTPUT DIRECTLY FROM END OF OUTPUT CAPACITOR L1 PLACE FEEDTHROUGHS AROUND GND TAB, C3, D1 FOR GOOD THERMAL CONDUCTIVITY KELVIN SENSE VOUT VOUT D2 C4 C5 C6 CC2 R2 R3 CC 7 6 5 4 3 2 1 U1 RC TAB IS GND GND 1374 F05c KEEP FB AND VC COMPONENTS AWAY FROM ANY HIGH FREQUENCY, HIGH CURRENT CMPONENTS OR PATHS Figure 5c. Suggested Layout (Topside Only Shown) DD SWITCH NODE L1 5V VIN HIGH FREQUENCY CIRCULATING PATH LOAD 1374 F06 Figure 6. High Speed Switching Path 1374fb 18 LT1374 U W U U APPLICATIONS INFORMATION PARASITIC RESONANCE Resonance or “ringing” may sometimes be seen on the switch node (see Figure 7). Very high frequency ringing following switch rise time is caused by switch/diode/input capacitor lead inductance and diode capacitance. Schottky diodes have very high “Q” junction capacitance that can ring for many cycles when excited at high frequency. If total lead length for the input capacitor, diode and switch path is 1 inch, the inductance will be approximately 25nH. At switch off, this will produce a spike across the NPN output device in addition to the input voltage. At higher currents this spike can be in the order of 10V to 20V or higher with a poor layout, potentially exceeding the absolute max switch voltage. The path around switch, catch diode and input capacitor must be kept as short as possible to ensure reliable operation. When looking at this, a >100MHz oscilloscope must be used, and waveforms should be observed on the leads of the package. This switch off spike will also cause the SW node to go below ground. The LT1374 has special circuitry inside which mitigates this problem, but negative voltages over 1V lasting longer than 10ns should be avoided. Note that 100MHz oscilloscopes are barely fast enough to see the details of the falling edge overshoot in Figure 7. A second, much lower frequency ringing is seen during switch off time if load current is low enough to allow the inductor current to fall to zero during part of the switch off time (see Figure 8). Switch and diode capacitance resonate with the inductor to form damped ringing at 1MHz to 10 MHz. This ringing is not harmful to the regulator and it has not been shown to contribute significantly to EMI. Any attempt to damp it with a resistive snubber will degrade efficiency. INPUT BYPASSING AND VOLTAGE RANGE Input Bypass Capacitor Step-down converters draw current from the input supply in pulses. The average height of these pulses is equal to load current, and the duty cycle is equal to VOUT/ VIN. Rise and fall time of the current is very fast. A local bypass capacitor across the input supply is necessary to ensure proper operation of the regulator and minimize the ripple RISE AND FALL WAVEFORMS ARE SUPERIMPOSED (PULSE WIDTH IS NOT 120ns) 5V/DIV 20ns/DIV 1374 F07 Figure 7. Switch Node Resonance 5V/DIV SWITCH NODE VOLTAGE INDUCTOR CURRENT 100mA/DIV 20ns/DIV 1375/76 F11 0.5µs/DIV 1374 F08 Figure 8. Discontinuous Mode Ringing current fed back into the input supply. The capacitor also forces switching current to flow in a tight local loop, minimizing EMI. Do not cheat on the ripple current rating of the Input bypass capacitor, but also don’t get hung up on the value in microfarads. The input capacitor is intended to absorb all the switching current ripple, which can have an RMS value as high as one half of load current. Ripple current ratings on the capacitor must be observed to ensure reliable operation. In many cases it is necessary to parallel two capacitors to obtain the required ripple rating. Both capacitors must be of the same value and manufacturer to guarantee power sharing. The actual value of the capacitor in microfarads is not particularly important because at 500kHz, any value above 5µF is essentially resistive. RMS ripple current rating is the critical parameter. Actual RMS current can be calculated from: ( ) IRIPPLE(RMS) = IOUT VOUT VIN − VOUT / VIN 2 1374fb 19 LT1374 U W U U APPLICATIONS INFORMATION The term inside the radical has a maximum value of 0.5 when input voltage is twice output, and stays near 0.5 for a relatively wide range of input voltages. It is common practice therefore to simply use the worst-case value and assume that RMS ripple current is one half of load current. At maximum output current of 4.5A for the LT1374, the input bypass capacitor should be rated at 2.25A ripple current. Note however, that there are many secondary considerations in choosing the final ripple current rating. These include ambient temperature, average versus peak load current, equipment operating schedule, and required product lifetime. For more details, see Application Notes 19 and 46, and Design Note 95. Larger capacitors may be necessary when the input voltage is very close to the minimum specified on the data sheet. Small voltage dips during switch on time are not normally a problem, but at very low input voltage they may cause erratic operation because the input voltage drops below the minimum specification. Problems can also occur if the input-to-output voltage differential is near minimum. The amplitude of these dips is normally a function of capacitor ESR and ESL because the capacitive reactance is small compared to these terms. ESR tends to be the dominate term and is inversely related to physical capacitor size within a given capacitor type. SYNCHRONIZING (Available as -SYNC Option) Input Capacitor Type Some caution must be used when selecting the type of capacitor used at the input to regulators. Aluminum electrolytics are lowest cost, but are physically large to achieve adequate ripple current rating, and size constraints (especially height), may preclude their use. Ceramic capacitors are now available in larger values, and their high ripple current and voltage rating make them ideal for input bypassing. Cost is fairly high and footprint may also be somewhat large. Solid tantalum capacitors would be a good choice, except that they have a history of occasional spectacular failures when they are subjected to large current surges during power-up. The capacitors can short and then burn with a brilliant white light and lots of nasty smoke. This phenomenon occurs in only a small percentage of units, but it has led some OEM companies to forbid their use in high surge applications. The input bypass capacitor of regulators can see these high surges when a battery or high capacitance source is connected. Several manufacturers have developed a line of solid tantalum capacitors specially tested for surge capability (AVX TPS series for instance, see Table 3), but even these units may fail if the input voltage surge approaches the maximum voltage rating of the capacitor. AVX recommends derating capacitor voltage by 2:1 for high surge applications. The highest voltage rating is 50V, so 25V may be a practical upper limit when using solid tantalum capacitors for input bypassing. The LT1374-SYNC has the SHDN pin replaced with a SYNC pin, which is used to synchronize the internal oscillator to an external signal. The SYNC input must pass from a logic level low, through the maximum synchronization threshold with a duty cycle between 10% and 90%. The input can be driven directly from a logic level output. The synchronizing range is equal to initial operating frequency up to 1MHz. This means that minimum practical sync frequency is equal to the worst-case high selfoscillating frequency (550kHz), not the typical operating frequency of 500kHz. Caution should be used when synchronizing above 700kHz because at higher sync frequencies the amplitude of the internal slope compensation used to prevent subharmonic switching is reduced. This type of subharmonic switching only occurs at input voltages less than twice output voltage. Higher inductor values will tend to eliminate this problem. See Frequency Compensation section for a discussion of an entirely different cause of subharmonic switching before assuming that the cause is insufficient slope compensation. Application Note 19 has more details on the theory of slope compensation. At power-up, when VC is being clamped by the FB pin (see Figure 2, Q2), the sync function is disabled. This allows the frequency foldback to operate in the shorted output condition. During normal operation, switching frequency is controlled by the internal oscillator until the FB pin reaches 1.5V, after which the SYNC pin becomes operational. If no synchronization is required, this pin should be connected to ground. 1374fb 20 LT1374 U U W U APPLICATIONS INFORMATION THERMAL CALCULATIONS Power dissipation in the LT1374 chip comes from four sources: switch DC loss, switch AC loss, boost circuit current, and input quiescent current. The following formulas show how to calculate each of these losses. These formulas assume continuous mode operation, so they should not be used for calculating efficiency at light load currents. Switch loss: PSW = ( ) (VOUT ) + 24ns(I )(V )(f) OUT IN VIN RSW IOUT PBOOST = ( VOUT IOUT / 50 TJ = TA + θJA (PTOT) With the TSSOP16 package (θJA = 40°C/W), at an ambient temperature of 50°C, TJ = 50 + 40 (0.87) = 85°C 2 For the DD package with a good copper plane under the device, thermal resistance will be about 30°C/W. For the conditions above: Boost current loss: 2 Thermal resistance for LT1374 package is influenced by the presence of internal or backside planes. With a full plane under the 16-lead TSSOP package, thermal resistance will be about 40°C/W. To calculate die temperature, use the proper thermal resistance number for the desired package and add in worst-case ambient temperature: TJ = 50 + 30 (0.87) = 76°C ) Die temperature is highest at low input voltage, so use lowest continuous input operating voltage for thermal calculations. VIN Quiescent current loss: ( ) PQ = VIN 0.001 + VOUT ( ) FREQUENCY COMPENSATION 2 VOUT 0.002 0.005 + VIN ( ) RSW = Switch resistance (≈ 0.07) 24ns = Equivalent switch current/voltage overlap time f = Switch frequency Example: with VIN = 10V, VOUT = 5V and IOUT = 3A: (0.07)(3) (5) + 24 • 10 (3)(10) 500 • 10 = 10 2 PSW −9 3 = 0.32 + 0.36 = 0.68W (5) (3 / 50) = 0.15W = 2 PBOOST 10 (5) (0.002) = 0.04W = 10(0.001) + 5(0.005) + 2 PQ 10 Total power dissipation is 0.68 + 0.15 + 0.04 = 0.87W. Loop frequency compensation of switching regulators can be a rather complicated problem because the reactive components used to achieve high efficiency also introduce multiple poles into the feedback loop. The inductor and output capacitor on a conventional step-down converter actually form a resonant tank circuit that can exhibit peaking and a rapid 180° phase shift at the resonant frequency. By contrast, the LT1374 uses a “current mode” architecture to help alleviate phase shift created by the inductor. The basic connections are shown in Figure 9. Figure 10 shows a Bode plot of the phase and gain of the power section of the LT1374, measured from the VC pin to the output. Gain is set by the 5.3A/V transconductance of the LT1374 power section and the effective complex impedance from output to ground. Gain rolls off smoothly above the 600Hz pole frequency set by the 100µF output capacitor. Phase drop is limited to about 70°. Phase recovers and gain levels off at the zero frequency (≈16kHz) set by capacitor ESR (0.1Ω). 1374fb 21 LT1374 U U W U APPLICATIONS INFORMATION Error amplifier transconductance phase and gain are shown in Figure 11. The error amplifier can be modeled as a transconductance of 2000µMho, with an output impedance of 200kΩ in parallel with 12pF. In all practical applications, the compensation network from VC pin to ground has a much lower impedance than the output impedance of the amplifier at frequencies above 500Hz. This means that the error amplifier characteristics themselves do not contribute excess phase shift to the loop, and the phase/gain characteristics of the error amplifier section are completely controlled by the external compensation network. In Figure 12, full loop phase/gain characteristics are shown with a compensation capacitor of 1.5nF, giving the error amplifier a pole at 530Hz, with phase rolling off to 90° and staying there. The overall loop has a gain of 74dB at low frequency, rolling off to unity-gain at 100kHz. Phase shows a two-pole characteristic until the ESR of the output capacitor brings it back above 10kHz. Phase margin is about 75° at unity-gain. Analog experts will note that around 4.4kHz, phase dips very close to the zero phase margin line. This is typical of switching regulators, especially those that operate over a wide range of loads. This region of low phase is not a problem as long as it does not occur near unity-gain. In practice, the variability of output capacitor ESR tends to dominate all other effects with respect to loop response. Variations in ESR will cause unity-gain to move around, but at the same time phase moves with it so that adequate phase margin is maintained over a very wide range of ESR (≥ ±3:1). LT1374 3000 VSW 150 ESR 2.42V + GAIN 2000 1500 – + C1 100 ( ) ROUT 200k VFB 2 × 10–3 1000 R2 VC COUT 12pF ERROR AMPLIFIER EQUIVALENT CIRCUIT 1k 10k 100k FREQUENCY (Hz) Figure 9. Model for Loop Response 1374 F11 20 40 0 –40 PHASE –20 –80 100 1k 10k FREQUENCY (Hz) 100k –120 1M 1374 F10 Figure 10. Response from VC Pin to Output 200 GAIN 60 150 40 100 PHASE 20 50 VIN = 10V VOUT = 5V, IOUT = 2A COUT = 100µF, 10V, AVX TPS CC = 1.5nF, RC = 0, L = 10µH 0 –20 10 100 1k 10k FREQUENCY (Hz) LOOP PHASE (DEG) 0 80 LOOP GAIN (dB) GAIN VIN = 10V VOUT = 5V IOUT = 2A Figure 11. Error Amplifier Gain and Phase PHASE: VC PIN TO OUTPUT (DEG) GAIN: VC PIN TO OUTPUT (dB) 40 –50 10M 1M 1374 F09 10 0 RLOAD = 50Ω 500 100 CC –40 50 PHASE (DEG) FB RC CF PHASE 2500 R1 VC GND 200 OUTPUT ERROR AMPLIFIER GAIN (µMho) CURRENT MODE POWER STAGE gm = 5.3A/V 0 100k –50 1M 1374 F12 Figure 12. Overall Loop Characteristics 1374fb 22 LT1374 U U W U APPLICATIONS INFORMATION What About a Resistor in the Compensation Network? It is common practice in switching regulator design to add a “zero” to the error amplifier compensation to increase loop phase margin. This zero is created in the external network in the form of a resistor (RC) in series with the compensation capacitor. Increasing the size of this resistor generally creates better and better loop stability, but there are two limitations on its value. First, the combination of output capacitor ESR and a large value for RC may cause loop gain to stop rolling off altogether, creating a gain margin problem. An approximate formula for RC where gain margin falls to zero is: ( ) (G )(G )(ESR)(2.42) VOUT R C Loop Gain = 1 = MP MA GMP = Transconductance of power stage = 5.3A/V GMA = Error amplifier transconductance = 2(10–3) ESR = Output capacitor ESR 2.42 = Reference voltage With VOUT = 5V and ESR = 0.03Ω, a value of 6.5k for RC would yield zero gain margin, so this represents an upper limit. There is a second limitation however which has nothing to do with theoretical small signal dynamics. This resistor sets high frequency gain of the error amplifier, including the gain at the switching frequency. If switching frequency gain is high enough, output ripple voltage will appear at the VC pin with enough amplitude to muck up proper operation of the regulator. In the marginal case, subharmonic switching occurs, as evidenced by alternating pulse widths seen at the switch node. In more severe cases, the regulator squeals or hisses audibly even though the output voltage is still roughly correct. None of this will show on a theoretical Bode plot because Bode is an amplitude insensitive analysis. Tests have shown that if ripple voltage on the VC is held to less than 100mVP-P, the LT1374 will be well behaved. The formula below will give an estimate of VC ripple voltage when RC is added to the loop, assuming that RC is large compared to the reactance of CC at 500kHz. VC(RIPPLE ) = (R )(G )(V − V )(ESR)(2.4) (V )(L)(f) C MA IN OUT IN GMA = Error amplifier transconductance (2000µMho) If a computer simulation of the LT1374 showed that a series compensation resistor of 3k gave best overall loop response, with adequate gain margin, the resulting VC pin ripple voltage with VIN = 10V, VOUT = 5V, ESR = 0.1Ω, L = 10µH, would be: 3k ) 2 • 10 (10 − 5)(0.1)(2.4) ( = 0.144V )= 10 • 10 500 • 10 10 ( ) −3 VC (RIPPLE −6 3 This ripple voltage is high enough to possibly create subharmonic switching. In most situations a compromise value (< 2k in this case) for the resistor gives acceptable phase margin and no subharmonic problems. In other cases, the resistor may have to be larger to get acceptable phase response, and some means must be used to control ripple voltage at the VC pin. The suggested way to do this is to add a capacitor (CF) in parallel with the RC /CC network on the VC pin. Pole frequency for this capacitor is typically set at one-fifth of switching frequency so that it provides significant attenuation of switching ripple, but does not add unacceptable phase shift at loop unity-gain frequency. With RC = 3k, CF = 5 (2π)(f)(R ) C = 5 ( ) 2π 500 • 103 3k = 531pF How Do I Test Loop Stability? The “standard” compensation for LT1374 is a 1.5nF capacitor for CC, with RC = 0. While this compensation will work for most applications, the “optimum” value for loop compensation components depends, to various extent, on parameters which are not well controlled. These include inductor value (±30% due to production tolerance, load 1374fb 23 LT1374 U W U U APPLICATIONS INFORMATION current and ripple current variations), output capacitance (±20% to ±50% due to production tolerance, temperature, aging and changes at the load), output capacitor ESR (±200% due to production tolerance, temperature and aging), and finally, DC input voltage and output load current . This makes it important for the designer to check out the final design to ensure that it is “robust” and tolerant of all these variations. After verifying that the setup is working correctly, I start varying load current and input voltage to see if I can find any combination that makes the transient response look suspiciously “ringy.” This procedure may lead to an adjustment for best loop stability or faster loop transient response. Nearly always you will find that loop response looks better if you add in several kΩ for RC. Do this only if necessary, because as explained before, RC above 1k may require the addition of CF to control VC pin ripple. If everything looks OK, I use a heat gun and cold spray on the circuit (especially the output capacitor) to bring out any temperature-dependent characteristics. I check switching regulator loop stability by pulse loading the regulator output while observing transient response at the output, using the circuit shown in Figure 13. The regulator loop is “hit” with a small transient AC load current at a relatively low frequency, 50Hz to 1kHz. This causes the output to jump a few millivolts, then settle back to the original value, as shown in Figure 14. A well behaved loop will settle back cleanly, whereas a loop with poor phase or gain margin will “ring” as it settles. The number of rings indicates the degree of stability, and the frequency of the ringing shows the approximate unity-gain frequency of the loop. Amplitude of the signal is not particularly important, as long as the amplitude is not so high that the loop behaves nonlinearly. Keep in mind that this procedure does not take initial component tolerance into account. You should see fairly clean response under all load and line conditions to ensure that component variations will not cause problems. One note here: according to Murphy, the component most VOUT AT IOUT = 500mA BEFORE FILTER VOUT AT IOUT = 500mA AFTER FILTER VOUT AT IOUT = 50mA AFTER FILTER LOAD PULSE THROUGH 50Ω f ≈ 780Hz 10mV/DIV The output of the regulator contains both the desired low frequency transient information and a reasonable amount of high frequency (500kHz) ripple. The ripple makes it difficult to observe the small transient, so a two-pole, 100kHz filter has been added. This filter is not particularly critical; even if it attenuated the transient signal slightly, this wouldn’t matter because amplitude is not critical. 5A/DIV 0.2ms/DIV 1374 F14 Figure 14. Loop Stability Check RIPPLE FILTER SWITCHING REGULATOR ADJUSTABLE INPUT SUPPLY ADJUSTABLE DC LOAD 470Ω + 100µF TO 1000µF 3300pF TO X1 OSCILLOSCOPE PROBE 4.7k 330pF 50Ω TO OSCILLOSCOPE SYNC 100Hz TO 1kHz 100mV TO 1VP-P 1374 F13 Figure 13. Loop Stability Test Circuit 1374fb 24 LT1374 U W U U APPLICATIONS INFORMATION likely to be changed in production is the output capacitor, because that is the component most likely to have manufacturer variations (in ESR) large enough to cause problems. It would be a wise move to lock down the sources of the output capacitor in production. A possible exception to the “clean response” rule is at very light loads, as evidenced in Figure 14 with ILOAD = 50mA. Switching regulators tend to have dramatic shifts in loop response at very light loads, mostly because the inductor current becomes discontinuous. One common result is very slow but stable characteristics. A second possibility is low phase margin, as evidenced by ringing at the output with transients. The good news is that the low phase margin at light loads is not particularly sensitive to component variation, so if it looks reasonable under a transient test, it will probably not be a problem in production. Note that frequency of the light load ringing may vary with component tolerance but phase margin generally hangs in there. POSITIVE-TO-NEGATIVE CONVERTER The circuit in Figure 15 is a classic positive-to-negative topology using a grounded inductor. It differs from the standard approach in the way the IC chip derives its feedback signal, however, because the LT1374 accepts only positive feedback signals, the ground pin must be tied to the regulated negative output. A resistor divider to ground or, in this case, the sense pin, then provides the proper feedback voltage for the chip. D1 CMDSH-3 INPUT 5.5V TO 20V C3 10µF TO 50µF BOOST VIN C2 0.27µF L1* 5µH VSW LT1374-5 + GND SENSE VC CC RC + D2 MBRS330T3 C1 100µF 10V TANT ×2 * INCREASE L1 TO 10µH OR 20µH FOR HIGHER CURRENT APPLICATIONS. SEE APPLICATIONS INFORMATION ** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION OUTPUT** –5V, 1.8A 1374 F15 Inverting regulators differ from buck regulators in the basic switching network. Current is delivered to the output as square waves with a peak-to-peak amplitude much greater than load current. This means that maximum load current will be significantly less than the LT1374’s 4.5A maximum switch current, even with large inductor values. The buck converter in comparison, delivers current to the output as a triangular wave superimposed on a DC level equal to load current, and load current can approach 4.5A with large inductors. Output ripple voltage for the positiveto-negative converter will be much higher than a buck converter. Ripple current in the output capacitor will also be much higher. The following equations can be used to calculate operating conditions for the positive-to-negative converter. Maximum load current: ( )( ) (V )(V − 0.35 ) )( )( ) OUT IN )(VOUT + VF) VIN VOUT IP − 2 VOUT + VIN f L IMAX = VOUT + VIN − 0.35 ( ( IP = Maximum rated switch current VIN = Minimum input voltage VOUT = Output voltage VF = Catch diode forward voltage 0.35 = Switch voltage drop at 4.5A Example: with VIN(MIN) = 5.5V, VOUT = 5V, L = 10µH, VF = 0.5V, IP = 4.5A: IMAX = 2A. Note that this equation does not take into account that maximum rated switch current (IP) on the LT1374 is reduced slightly for duty cycles above 50%. If duty cycle is expected to exceed 50% (input voltage less than output voltage), use the actual IP value from the Electrical Characteristics table. Operating duty cycle: DC = VOUT + VF VIN − 0.3 + VOUT + VF (This formula uses an average value for switch loss, so it may be several percent in error.) Figure 15. Positive-to-Negative Converter 1374fb 25 LT1374 U W U U APPLICATIONS INFORMATION With the conditions above: DC = 5 + 0.5 = 51% 5.5 − 0.3 + 5 + 0.5 This duty cycle is close enough to 50% that IP can be assumed to be 4.5A. OUTPUT DIVIDER If the adjustable part is used, the resistor connected to VOUT (R2) should be set to approximately 5k. R1 is calculated from: R1 = ( ) R2 VOUT – 2.42 2.42 INDUCTOR VALUE lowest value of inductance that can be used, but in some cases (lower output load currents) it may give a value that creates unnecessarily high output ripple voltage. A compromise value is often chosen that reduces output ripple. As you can see from the graph, large inductors will not give arbitrarily low ripple, but small inductors can give high ripple. The difficulty in calculating the minimum inductor size needed is that you must first know whether the switcher will be in continuous or discontinuous mode at the critical point where switch current is 4.5A. The first step is to use the following formula to calculate the load current where the switcher must use continuous mode. If your load current is less than this, use the discontinuous mode formula to calculate minimum inductor needed. If load current is higher, use the continuous mode formula. Output current where continuous mode is needed: Unlike buck converters, positive-to-negative converters cannot use large inductor values to reduce output ripple voltage. At 500kHz, values larger than 25µH make almost no change in output ripple. The graph in Figure 16 shows peak-to-peak output ripple voltage for a 5V to – 5V converter versus inductor value. The criteria for choosing the inductor is therefore typically based on ensuring that peak switch current rating is not exceeded. This gives the (V ) (I ) 4(V + V )(V + V 2 IN ICONT = IN OUT + VF IN ) Minimum inductor discontinuous mode: L MIN = ( )( ) (f)(I ) 2 VOUT IOUT 2 P 250 OUTPUT RIPPLE VOLTAGE (mVP-P) OUT 2 P 5V TO – 5V CONVERTER OUTPUT CAPACITOR’S ESR = 0.05Ω 200 Minimum inductor continuous mode: (V )(V ) IN L MIN = 150 ILOAD = 1A ( )( 2 f VIN + VOUT 100 ) ILOAD = 0.25A 50 OUT ( V +V I − I 1 + OUT F P OUT VIN ) For the example above, with maximum load current of 1A: 0 0 5 15 10 INDUCTOR SIZE (µH) 20 (5.5) (4.5) = 1.15 A 4 (5.5 + 5)(5.5 + 5 + 0.5 ) 2 1374 F16 Figure 16. Ripple Voltage on Positive-to-Negative Converter ICONT = 2 1374fb 26 LT1374 U W U U APPLICATIONS INFORMATION This says that discontinuous mode can be used and the minimum inductor needed is found from: L MIN = ( )( ) 500 • 10 4.5 ( ) 25 1 3 2 = 1µH In practice, the inductor should be increased by about 30% over the calculated minimum to handle losses and variations in value. This suggests a minimum inductor of 1.3µH for this application, but looking at the ripple voltage chart shows that output ripple voltage could be reduced by a factor of two by using a 15µH inductor. There is no rule of thumb here to make a final decision. If modest ripple is needed and the larger inductor does the trick, go for it. If ripple is noncritical use the smaller inductor. If ripple is extremely critical, a second filter may have to be added in any case, and the lower value of inductance can be used. Keep in mind that the output capacitor is the other critical factor in determining output ripple voltage. Ripple shown on the graph (Figure 16) is with two parallel capacitor’s ESR of 0.1Ω. This is reasonable for AVX type TPS “D” or “E” size surface mount solid tantalum capacitors, but the final capacitor chosen must be looked at carefully for ESR characteristics. Ripple Current in the Input and Output Capacitors Positive-to-negative converters have high ripple current in both the input and output capacitors. For long capacitor lifetime, the RMS value of this current must be less than the high frequency ripple current rating of the capacitor. The following formula will give an approximate value for RMS ripple current. This formula assumes continuous mode and large inductor value. Small inductors will give somewhat higher ripple current, especially in discontinuous mode. The exact formulas are very complex and appear in Application Note 44, pages 30 and 31. For our purposes here I have simply added a fudge factor (ff). The value for ff is about 1.2 for higher load currents and L ≥10µH. It increases to about 2.0 for smaller inductors at lower load currents. ( )( ) Capacitor IRMS = ff IOUT VOUT VIN ff = Fudge factor (1.2 to 2.0) Diode Current Average diode current is equal to load current. Peak diode current will be considerably higher. Peak diode current: Continuous Mode = IOUT (VIN + VOUT ) + (VIN)(VOUT ) VIN 2(L)( f)( VIN + VOUT ) Discontinuous Mode = ( )( ) (L)(f) 2 IOUT VOUT Keep in mind that during start-up and output overloads, average diode current may be much higher than with normal loads. Care should be used if diodes rated less than 3A are used, especially if continuous overload conditions must be tolerated. 1374fb 27 LT1374 U W U U APPLICATIONS INFORMATION FE Package 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663, Exposed Pad Variation BB) 4.95 – 5.05* (.196 – .204) 3.8 (.149) 16 1514 13 12 1110 6.60 ±0.10 9 EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE 4.50 ±0.10 3.0 6.25 – 6.50 (.118) (.246 – .256) 0.45 ±0.05 1.05 ±0.10 0.65 BSC 1 2 3 4 5 6 7 8 RECOMMENDED SOLDER PAD 1.15 (.0453) MAX 4.30 – 4.48* (.169 – .176) 0° – 8° 0.105 – 0.180 (.0041 – .0071) 0.50 – 0.70 (.020 – .028) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) 0.05 – 0.15 (.002 – .006) FE16 TSSOP 1101 NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 1374fb 28 LT1374 U PACKAGE DESCRIPTION R Package 7-Lead Plastic DD Pak (LTC DWG # 05-08-1462) 0.256 (6.502) 0.060 (1.524) 0.060 (1.524) TYP 0.390 – 0.415 (9.906 – 10.541) 0.165 – 0.180 (4.191 – 4.572) 15° TYP 0.060 (1.524) 0.183 (4.648) 0.059 (1.499) TYP 0.330 – 0.370 (8.382 – 9.398) BOTTOM VIEW OF DD PAK HATCHED AREA IS SOLDER PLATED COPPER HEAT SINK ( +0.008 0.004 –0.004 +0.203 0.102 –0.102 ) 0.095 – 0.115 (2.413 – 2.921) 0.075 (1.905) 0.300 (7.620) 0.045 – 0.055 (1.143 – 1.397) ( +0.012 0.143 –0.020 +0.305 3.632 –0.508 ) 0.040 – 0.060 (1.016 – 1.524) 0.026 – 0.036 (0.660 – 0.914) 0.013 – 0.023 (0.330 – 0.584) 0.050 ± 0.012 (1.270 ± 0.305) R (DD7) 0396 1374fb 29 LT1374 U PACKAGE DESCRIPTION S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 2 3 4 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) TYP SO8 0996 1374fb 30 LT1374 U PACKAGE DESCRIPTION T7 Package 7-Lead Plastic TO-220 (Standard) (LTC DWG # 05-08-1422) 0.390 – 0.415 (9.906 – 10.541) 0.165 – 0.180 (4.191 – 4.572) 0.147 – 0.155 (3.734 – 3.937) DIA 0.045 – 0.055 (1.143 – 1.397) 0.230 – 0.270 (5.842 – 6.858) 0.460 – 0.500 (11.684 – 12.700) 0.570 – 0.620 (14.478 – 15.748) 0.330 – 0.370 (8.382 – 9.398) 0.620 (15.75) TYP 0.700 – 0.728 (17.780 – 18.491) 0.152 – 0.202 0.260 – 0.320 (3.860 – 5.130) (6.604 – 8.128) 0.040 – 0.060 (1.016 – 1.524) 0.095 – 0.115 (2.413 – 2.921) 0.013 – 0.023 (0.330 – 0.584) 0.026 – 0.036 (0.660 – 0.914) 0.135 – 0.165 (3.429 – 4.191) 0.155 – 0.195 (3.937 – 4.953) T7 (TO-220) (FORMED) 1197 1374fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LT1374 U TYPICAL APPLICATION Dual Output SEPIC␣ Converter losses. C4 provides a low impedance path to maintain an equal voltage swing in L1B, improving regulation. In a flyback converter, during switch on time, all the converter’s energy is stored in L1A only, since no current flows in L1B. At switch off, energy is transferred by magnetic coupling into L1B, powering the – 5V rail. C4 pulls L1B positive during switch on time, causing current to flow, and energy to build in L1B and C4. At switch off, the energy stored in both L1B and C4 supply the – 5V rail. This reduces the current in L1A and changes L1B current waveform from square to triangular. For details on this circuit see Design Note 100. The circuit in Figure 17 generates both positive and negative 5V outputs with a single piece of magnetics. The two inductors shown are actually just two windings on a standard BH Electronics inductor. The topology for the 5V output is a standard buck converter. The – 5V topology would be a simple flyback winding coupled to the buck converter if C4 were not present. C4 creates the SEPIC (Single-Ended Primary Inductance Converter) topology which improves regulation and reduces ripple current in L1. Without C4, the voltage swing on L1B compared to L1A would vary due to relative loading and coupling INPUT 6V TO 25V VIN BOOST C2 0.27µF + L1A* 6.8µH SENSE VC C3 22µF 35V TANT OUTPUT 5V VSW LT1374-5 BIAS SHDN GND D2 CMDSH-3 RC 470Ω CC 0.01µF + C1** 100µF 10V TANT + C5** 100µF 10V TANT D1 MBRD340 GND * L1 IS A SINGLE CORE WITH TWO WINDINGS BH ELECTRONICS #501-0726 ** TOKIN IE475ZY5U-C304 † IF LOAD CAN GO TO ZERO, AN OPTIONAL PRELOAD OF 1k TO 5k MAY BE USED TO IMPROVE LOAD REGULATION C4** 4.7nF + L1B* D3 MBRD340 OUTPUT –5V† 1374 F17 Figure 17. Dual Output SEPIC Converter RELATED PARTS PART NUMBER DESCRIPTION LT1074/LT1076 Step-Down Switching Regulators LTC®1148 High Efficiency Synchronous Step-Down Switching Regulator LTC1149 High Efficiency Synchronous Step-Down Switching Regulator LTC1174 High Efficiency Step-Down and Inverting DC/DC Converter LT1176 Step-Down Switching Regulator LT1370 High Efficiency DC/DC Converter LT1371 High Efficiency DC/DC Converter LT1372/LT1377 500kHz and 1MHz High Efficiency 1.5A Switching Regulators LTC1735 High Efficiency Step-Down Converter LT1765 3A Step-Down Switching Regulator LT1766 1.5A Step-Down Switching Regulator LT1767 1.5A Step-Down Switching Regulator Burst Mode is a registered trademark of Linear Technology Corporation. COMMENTS 40V Input, 100kHz, 5A and 2A External FET Switches External FET Switches 0.5A, 150kHz Burst Mode® Operation PDIP LT1076 42V, 6A, 500kHz Switch 35V, 3A, 500kHz Switch Boost Topology External Switches, Very High Efficiency 1.25MHz, 3A, 25V Input, SO-8 and TSSOP16 Packages 200kHz, 1.5A, 60V Input, SO-8 and GN16 Packages 1.25MHz, 1.5A, 25V Input, MS8 Package 1374fb 32 Linear Technology Corporation LT/TP 0102 1.5K REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 1998