CXA3621GE
Fingerprint Sensor
Description
The CXA3621GE is an electrostatic capacitance
method fingerprint sensor.
This monolithic IC integrates the sensor block,
sense amplifier (3-bit gain adjustment), sample-andhold, output amplifier and output buffer needed to
acquire fingerprint images, as well as the timing
generator for determining the operation of these
functions onto a single chip.
30 pin LLGA (Plastic)
Features
• Electrostatic capacitance type sensor (charge transfer method)
• Number of pixels: 192 × 128
• 317 DPI
• Low power consumption (50mW or less) ∗ When P/S: 18µW or less
• Single 3.0V power supply
• Sensor gain control: 3 bits
• S/N ratio improved by on-chip sensor block parasitic capacitance cancel function
Applications
Fingerprint verification units
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25°C)
VSS – 0.5 to +7.0
• Supply voltage
AVDD, DVDD
• Input voltage
VI
VSS – 0.5 to VDD + 0.5
• Output voltage
VO
VSS – 0.5 to VDD + 0.5
• Operating temperature
Topr
–20 to +75
• Storage temperature
Tstg
–25 to +125
• Allowable power dissipation
PD
1100
Recommended Operating Conditions
• Supply voltage
AVDD, DVDD
• Ambient operating temperature Ta
2.7 to 3.6
0 to +50
V
V
V
°C
°C
mW
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02127-PS
CXA3621GE
Block Diagram
C_SP
UC
UC
SENSOR
........ 128 .........
CLK (D/I)
Timing
Generator
XSP (D/I)
UC
128
Column Shift Register
C_CLK
UC
UC
ADCLK (D/O)
UC UC UC UC ........... 192 ........... UC UC UC UC
192
S_CNT
Sense AMP (×192)
3bit
DAC
DI (D/I)
192
Load
S/H & SW (×192)
Output
Buffer
AOUT (A/O)
192
R_SP
Row Shift Register
VOS (Bias)
R_CLK
–2–
3
CXA3621GE
BUF
VOS
VCS_O
PAMP_S
PAMP_D
Pin Symbol
DC_VOS
C_CLK
BIAS_O
OAMP
Detailed Block Diagram
C_COUT
SR
SR[1:128]
SVss
SVss[1:128]
128
128
DUMMY OUT
SAMP
DUMMY SENSOR
S[6:7]
S[6:7]N
C_CO
XSP
DCLK
VCSN
VM
SVDS
SVDD
CLK
R_LOG
SC[1:192]N
SC[1:192]
192
SC[1:192]N
SC[1:192]
192
SAMP (192)
S[3:5]N
BIAS_SA
DCLK
SR
SD1
SD
DI[0:1]
DC_VM
C_CLK
TG
DSVss
S[3:5]N
S[4:5]
S[4:5]
DSR
C_SP
IN_N[1:192]
192
UC UC UC
UC UC UC
C[1:192]
UC
................ 192................
........ 128 .........
UC
SR[1:128]
SENSOR (UC)
UC
UC
UC
SVss[1:128]
OUT
SD1
UC UC UC
28
SGND (P/S)
7C
27
AVDD (P/S)
7D
26
AVss (P/S)
7E
25
AOUT (A/O)
7F
24
VOS (Bias)
6B
23
VCS_O (Bias)
6C
22
NC
6D
21
DVDD (P/S)
6E
20
DVSS (P/S)
6F
19
CSRO (D/O)
5B
18
RSRO (D/O)
5C
17
C_CK (D/O)
5D
16
ADCLK (D/O)
5E
15
SVDS (D/O)
5F
14
PS (D/I)
4F
13
CLK (D/I)
4E
12
XSP (D/I)
4D
11
DI2 (D/I)
4C
10
DI1 (D/I)
4B
9
DI0 (D/I)
3F
8
TEST3 (D/I)
3E
7
TEST2 (D/I)
3D
6
TEST1 (D/I)
3C
5
VCS_S (Bias)
3B
4
VM (Bias)
2F
3
AVSS (P/S)
2E
2
AVDD (P/S)
2D
1
SGND (P/S)
2C
C_LOG
C_SP
UC UC UC ........... 192 (Dummy) ...........
LAND No.
–3–
CXA3621GE
Pin Description
Serial
No.
Land No.
—
2B
SUB
Power
Substrate electrode (chip rear surface electrode) 3.0V (VDD).
1
2C
SGND
Power
Sensor lightning conductor electrode. (Connect to the GND which
is the other system of operating power supply.)
2
2D
AVDD
Power
Analog power supply 3.0V.
3
2E
AVSS
Power
Analog GND.
4
2F
VM
A/O
Sense amplifier reference voltage monitor 1.5V (1/2 VDD).
(Do not connect.)
5
3B
VCS_S
A/O
Sense amplifier current source bias monitor. (Do not connect.)
6
3C
TEST1
D/I
Test mode selection. (Connect to GND.)
7
3D
TEST2
D/I
Test mode selection. (Connect to GND.)
8
3E
TEST3
D/I
Test mode selection. (Connect to GND.)
9
3F
DI0
D/I
Gain setting input (LSB).
10
4B
DI1
D/I
Gain setting input.
11
4C
DI2
D/I
Gain setting input (MSB).
12
4D
XSP
D/I
Sense start pulse (negative pulse).
The column and row shift registers and the timing generator are
cleared by this signal.
13
4E
CLK
D/I
Main clock 2MHz.
14
4F
PS
D/I
Power saving mode setting. (Low: Operation; High: Standby)
15
5F
SVDS
D/O
Integrating pulse monitor. (Do not connect.)
16
5E
ADCLK
D/O
Delay clock. (Do not connect.)
17
5D
C_CK
D/O
Column shift register clock. (Do not connect.)
18
5C
RSRO
D/O
Column shift register final output. (Do not connect.)
19
5B
CSRO
D/O
Row shift register final output. (Do not connect.)
20
6F
DVSS
Power
Digital GND.
21
6E
DVDD
Power
Digital power supply 3.0V.
22
6D
NC
23
6C
VCS_O
A/O
Output amplifier current source bias monitor. (Do not connect.)
24
6B
VOS
A/O
Output amplifier reference voltage monitor 1.09V (4/11VDD).
(Do not connect.)
25
7F
AOUT
A/O
Sensor output.
26
7E
AVSS
Power
Analog GND.
27
7D
AVDD
Power
Analog power supply 3.0V.
28
7C
SGND
Power
Sensor lightning conductor electrode. (Connect to the GND which
is the other system of operating power supply.)
Symbol
I/O
—
Description
No connection. (Do not connect.)
–4–
CXA3621GE
Electrical Characteristics
DC Characteristics
Item
(Vss = 0V, Ta = 25°C)
Conditions
Symbol
Min.
Typ.
Max.
Unit
Analog supply voltage
AVDD
2.7
3.0
3.6
V
Digital supply voltage
DVDD
2.7
3.0
3.6
V
Current consumption
(for operation)
IDD1
VDD = 3V, P/S = L
5.0
8.5
13.0
mA
Current consumption
(for standby)
IDD2
VDD = 3V, P/S = H, CLK = L
5
µA
Input voltage (High)
VIH
Digital (CMOS) input cell
0.7VDD
VDD
V
Input voltage (Low)
VIL
Digital (CMOS) input cell
Vss
0.3VDD
V
Output voltage (High)
VOH
VDD = 3V, IOH = –800µA
2.6
3.0
V
Output voltage (Low)
VOL
VDD = 3V, IOL = 2.4mA
0
0.4
V
Input leak current
IL
VDD = 3V,
digital (CMOS) input cell [3V/0V]
–1
1
µA
Output voltage
VM
VDD = 3V
1.4
1.5
1.6
V
Output voltage
VOS
VDD = 3V
1.00
1.09
1.20
V
AC Characteristics
Item
Clock input period
(VDD = 3.0V, VSS = 0V, Ta = 25°C)
Conditions
Symbol
CLK
Min.
Typ.
Max.
400
Number of sensor defects
Unit
ns
0
3
Defects
AOUT
∗1
850
1090
1350
mV
Output voltage (Water_Level) AOUT
∗2
950
1200
1450
mV
Output voltage (Air_Level)
∗1 Output voltage Air Level means the output level in the condition where nothing is placed against the sensor
surface (in other words, in air). This rating value is obtained by measuring 32 points within one line of the
sensor output and then taking the average.
The gain setting for this measurement is (011).
∗2 Output voltage Water Level specifies the degree to which the output level changes from the Air Level when
a drop of water is placed on the sensor surface. However, it is unrealistic to place a drop of water on each
sensor surface when sorting products, so 32 virtual capacitors (parasitic capacitance equal to the level
when a drop of water is placed on the surface) are built into the sensor chip, and the average of these
output values is calculated. The difference from the Air Level noted above becomes the Water Level.
The gain setting for this measurement is (011).
–5–
CXA3621GE
Electrical Characteristics Measurement Circuit
Digital input pin
Digital output pin
Analog output pin
SGND
AVDD
1.0µF
AOUT/O
VCS_O/O
27
28
25
26
23
24
DVDD
0.1µF
CSRO/O
21
22
19
20
17
18
0.1µF
15
16
13
14
11
12
9
10
7
8
5
6
3
4
DVSS
RSRO/O
SVDS/O
ADCLK/O
CLK/I
PS/I
DI2/I
XSP/I
DI0/I
DI1/I
TEST2/I
TEST3/I
VCS_S/O
SGND
VOS/O
NC
C_CK/O
AVSS
AVSS
TEST1/I
1
2
VM/O
0.1µF
AVDD
1.0µF
Vcc
3.0V
The load of 30pF or more is added to each pin.
–6–
CXA3621GE
Application Circuit
Flash
Registered data
Microcomputer
During
registration
DRAM
During
verification
Fingerprint sensor chip
ASIC
Binary value, verification
8-bit A/D
Verification results
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
–7–
CXA3621GE
Description of Operation
• Fingerprint sensor principle
The principle of this newly developed fingerprint sensor is described below (Fig. 1). The sensor block
contains an array of metal electrodes which are covered on top by an insulating film (overcoat). When a
finger (which is conductive matter) is placed directly against this surface, the three elements of the metal
electrode, the insulating film and the finger form a capacitor.
The difference between the fingerprint ridges and valleys is the difference in distance to the metal electrodes,
and becomes the difference in the capacitance values of the individually formed capacitors. (The ridge
capacitance values are determined by the dielectric constant of the insulating film, but the valleys contain air
in addition to this, making the difference between the ridge and valley capacitance values even greater than
the difference in distance.)
Using this principle, by applying a constant voltage to all metal electrodes, the charge level accumulated in
each electrode differs, making it possible to output the unevenness of the fingerprint as an electric signal by
transferring and converting these charges to voltages.
Ridge
Valley
Fingerprint unevenness
Overcoat
Metal electrode
Inter-layer film
Si
Fig. 1
–8–
CXA3621GE
S4
SS
S6
Cf1
Cs
Vcel
Cf2
Vsns
Sr
Vsl
S5
Sensor Array
Sc
Ssig
S7
Ch1
S_Amp
Cp'
P_Amp
SVDD
VDD
VOS
VM
S4
SD
Cf1
Cf2
Vsnsd
Sr
O_Amp
VM
Upper: Sensor cell
Lower: Dummy block
Vsld
S5
Dummy Block
Sd1
Sdmy
S3
Cp
SVss
S_Amp
Cp'
Ch1
P_Amp
SVDD
VDD
Sensor block
(192 × 128: Sensor cell)
(128: Dummy block)
Voo
S3
Cp
SVss
Vceld
Cf3
Voi
Cs1
VM
VM
Sense amplifier block
(192: Sensor cell)
(1: Dummy block)
Output block
(1)
Fig. 2
• Fingerprint sensor operation (Fig. 2)
Description of characters
Cs: Capacitance formed between the finger and the metal electrode
Cp: Parasitic capacitance formed between the metal electrode and the silicon substrate
Cp': Capacitance for canceling Cp (Cp ≈ Cp')
Ch∗: Hold capacitance
Cf∗: Feedback capacitance for determining the gain
S∗: Switch
V∗: Node voltage
VM = 1 VDD, VOS = 4 VDD
2
11
–9–
Buffer Aout
Ch2
CXA3621GE
Appearance and Readout Order
15.36mm
Cell (1, 1)
Scan Formation
Cell (1, 1) to Cell (1, 192)
Cell (1, 192)
Sensor Area
192 × 128
10.24mm
Cell (128, 1)
16.8mm
Cell (128, 192)
Cell (128, 1) to
Cell (128, 192)
19.8mm
Flip
G
F
4
9
14
15
20
25
E
3
8
13
16
21
26
D
2
7
12
17
22
27
C
1
6
11
18
23
28
5
10
19
24
3
4
5
6
B
A
1
2
– 10 –
7
8
CXA3621GE
Notes on Operation
Sensor surface electrostatic strength
Aerial discharge (150pF, 330Ω): ±12kV or more
Sony conducts tests using the 50% flash-over method∗ from the viewpoint of reproducibility and comparison of
performance. This method allows more stable measurement than the general method of approaching a
discharge gun (approach method). However the discharge distance tends to be longer than for the approach
method, so the above performances may not be satisfied if testing is performed by the approach method.
∗The discharge distance (distance between the probe tip and the test piece) is determined, and a trigger is
applied at fixed time intervals to raise the applied voltage and start discharge. The applied voltage when
discharge occurs at just 1/2 of the number of trigger times is the 50% flash-over voltage. The flash-over voltage
changes when the distance is changed, but it has been confirmed that there are no problems in terms of
sensor performance up to ±12kV.
Sensor surface strength
The sensor surface may be broken by the contact of the metal and others.
Therefore, be sure to pay the sufficient attention to handling this IC.
∗Never handle sensors with metal tweezers or similar tools on mounting lines, etc.
– 11 –
CXA3621GE
Timing Chart
500ns
XSP
(3F)
CLK
(4C)
Strobe
Point
250ns
250ns
250ns
480ns
Input level
VIH = 0.7VDD
VIL = 0.3VDD
Output level
High
0.65VDD
X
0.35VDD
Low
– 12 –
CXA3621GE
Input/Output Signal
CLK
(Pin 13 • 4E)
Input
F = 2MHz
500ns (1CLK)
250ns
XSP
(Pin 12 • 4D)
Input
750ns
16512.5µs
(33025CLK) {(192 + 1 + 63) × (2 + 126) + (192 + 1 + 63) + 1}
750ns
(Repeat 128 Times)
AOUT
(Pin 25 • 7F)
Output
1 to 1.2V
256.5µs
(513CLK)
((192 + 1 + 63) × 2 + 1)
96µs
(192CLK)
1st line
output
32µs
(64CLK)
Sensor
read
96µs
(192CLK)
2nd line
output
32µs
(64CLK)
Sensor
read
2.3V
AOUT
(Pin 25 • 7F)
Detail
1.1V
500ns (1CLK)
– 13 –
CXA3621GE
Package Outline
Unit: mm
30PIN LLGA
S A
0.2
PIN 1 INDEX
0.5 ± 0.3
2.6 ± 0.3
19.0 ± 0.25
15.16 ± 0.25∗
S
X
1.2 ± 0.1
0.1 S
20.0
0.5 ± 0.3
2.42 ± 0.3
1.
0
17.0
AX
R
x4
16.0 ± 0.25
0M
1.
0.2 S B
R
10.04 ± 0.25∗
0.08MAX
(0.4)
DETAIL X
Y
4-
0.15
SENSOR AREA
2.3
0.8
A
G
F
DETAIL Y
B
E
7.1
0.25MAX
φ0.1 M S A B
2.54
2.07
52 – φ1.2 ± 0.08
10.16
0.25MAX
3 – φ2.2
3.42
D
2.07
C
NOTE : ∗ Not include flash burr.
B
A
2.2
1
2
2.2
2.3
SONY CODE
3
4
5
6
7 8
3.65
PACKAGE STRUCTURE
2.54
LLGA-30P-02
PACKAGE MATERIAL
ORGANIC SUBSTRATE
TERMINAL TREATMENT
NICKEL & GOLD PLATING
JEITA CODE
TERMINAL MATERIAL
JEDEC CODE
PACKAGE MASS
– 14 –
COPPER
0.7g
Sony Corporation