ADC1207S080 Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling Rev. 03 — 2 July 2012 Product data sheet 1. General description The ADC1207S080 is a 12-bit Analog-to-Digital Converter (ADC) optimized for direct Input Frequency (IF) sampling and supporting the most demanding use conditions in ultra high IF radio transceivers for cellular infrastructure and other applications such as wireless infrastructure, optical networking and fixed telecommunication. Due to its broadband input capabilities, the ADC1207S080 is ideal for single and multiple carriers data conversion. Operating at a maximum sampling rate of 80 MHz, analog input signals are converted into 12-bit binary coded digital words. All static digital inputs are CMOS compatible. All output signals are Low-Voltage Complementary Metal-Oxide Semiconductor (LVCMOS) compatible. The ADC1207S080 offers the most flexible acquisition control system because of its programmable Complete Conversion Signal (CCS) that allows to adjust the delay of the acquisition clock. The ADC1207S080 offers the lowest input capacitance (< 1 pF) and therefore the highest flexibility in front-end aliasing filter strategy because of its internal front-end buffer. 2. Features 12-bit resolution Differential input with 375 MHz bandwidth 90 dB SFDR; 71 dB S/N (fi = 225 MHz; fclk = 80 MHz; B = 5 MHz) 74 dB SFDR; 66.5 dB S/N (fi = 175 MHz; fclk = 80 MHz; B = Nyquist) High speed sampling rate up to 80 MHz Internal front-end buffer (input capacitance < 1 pF) Programmable acquisition output clock (complete conversion signal) Full-scale controllable from 1.5 V to 2 V (p-p); continuous scale Single 5 V power supply 3.3 V LVCMOS compatible digital outputs Binary or two’s-complement LVCMOS outputs CMOS compatible static digital inputs Only 2 clock cycles latency Industrial temperature range from 40 C to +85 C HTQFP48 package ® ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling 3. Applications High speed analog to digital conversion for: Radio transceivers Wireless infrastructure Cable modem Digital storage scope Fixed telecommunication, Optical networking Wireless Local Area Network (WLAN) infrastructure. General purpose applications 4. Ordering information Table 1. Ordering information Type number ADC1207S080HW Package Sampling frequency (MHz) Name Description Version HTQFP48 plastic thermal enhanced thin quad flat package; 48 leads; body 7 7 1 mm; exposed die pad SOT545-2 80 5. Block diagram CLK CLKN ADC1207S080 DEL0 to DEL1 2 CLOCK DRIVER CCS 12 LATCH 12 D0 to D11 front-end buffer IN INN OTC TRACK AND HOLD RESISTOR LADDERS ADC CORE VCCO U/I IR LATCH FSIN FSOUT VREF REFERENCE CMADC REFERENCE OUTPUTS ENABLE DEC CE_N 014aaa430 CMADC Fig 1. Block diagram ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 2 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling 6. Pinning information 37 CCS 38 DGND1 39 CLKN 40 CLK 41 VCCD1 42 DGND1 43 AGND2 44 VCCA2 45 VCCA1 46 AGND1 47 VCCA1 48 AGND1 6.1 Pinning n.c. 1 36 D0 AGND1 2 35 D1 IN 3 34 D2 CMADC 4 33 D3 INN 5 32 D4 AGND1 6 DEC 7 n.c. 8 29 D7 FSOUT 9 28 D8 31 D5 ADC1207S080HW FSIN 10 30 D6 27 D9 DGND n.c. 11 26 D10 IR 24 VCCO 23 OGND 22 VCCO 21 OGND 20 OTC 19 CE_N 18 DGND2 17 VCCD2 16 DEL0 15 n.c. 13 25 D11 DEL1 14 n.c. 12 014aaa431 Fig 2. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Type [1] Description n.c. 1 - not connected AGND1 2 G analog ground 1 IN 3 I analog input voltage CMADC 4 O regulator common mode ADC output INN 5 I complementary analog input voltage AGND1 6 G analog ground 1 DEC 7 I/O decoupling node n.c. 8 - not connected FSOUT 9 O full-scale reference voltage output FSIN 10 I full-scale reference voltage input n.c. 11 - not connected n.c. 12 - not connected n.c. 13 - not connected DEL1 14 I complete conversion signal delay input 1 DEL0 15 I complete conversion signal delay input 0 VCCD2 16 P digital supply voltage 2 (5.0 V) ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 3 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling Table 2. Pin description …continued Symbol Pin Type [1] Description DGND2 17 G digital ground 2 CE_N 18 I chip enable input (CMOS level; active LOW) OTC 19 I control input for two’s complement output (active HIGH) OGND 20 G data output ground VCCO 21 P data output supply voltage (3.3 V) OGND 22 G data output ground VCCO 23 P data output supply voltage (3.3 V) IR 24 O in-range output D11 25 O data output bit 11 (Most Significant Bit (MSB)) D10 26 O data output bit 10 D9 27 O data output bit 9 D8 28 O data output bit 8 D7 29 O data output bit 7 D6 30 O data output bit 6 D5 31 O data output bit 5 D4 32 O data output bit 4 D3 33 O data output bit 3 D2 34 O data output bit 2 D1 35 O data output bit 1 D0 36 O data output bit 0 (Least Significant Bit (LSB)) CCS 37 O complete conversion signal output DGND1 38 G digital ground 1 CLKN 39 I complementary clock input CLK 40 I clock input VCCD1 41 P digital supply voltage 1 (5.0 V) DGND1 42 G digital ground 1 AGND2 43 G analog ground 2 VCCA2 44 P analog supply voltage 2 (5.0 V) VCCA1 45 P analog supply voltage 1 (5.0 V) AGND1 46 G analog ground 1 VCCA1 47 P analog supply voltage 1 (5.0 V) AGND1 48 G analog ground 1 DGND exposed G die pad [1] digital ground P: power supply; G: ground; I: input; O: output. ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 4 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCCA analog supply voltage [1] 0.5 +7.0 V VCCD digital supply voltage [1] 0.5 +7.0 V VCCO output supply voltage [2] 0.5 +5.0 V VCC supply voltage difference VCCA VCCD 1.0 +1.0 V VCCD VCCO 1.0 +4.0 V VCCA VCCO 1.0 +4.0 V Vi(IN) input voltage on pin IN referenced to AGND 0 VCCA + 1 V Vi(INN) input voltage on pin INN referenced to AGND 0 VCCA + 1 V Vi(CLK) input voltage on pin CLK referenced to DGND 0 VCCD + 1 V Vi(CLKN) input voltage on pin CLKN referenced to DGND 0 VCCD + 1 V IO output current - 10 mA Tstg storage temperature 55 +150 C Tamb ambient temperature 40 +85 C Tj junction temperature - 150 C [1] The supply voltages VCCA and VCCD may have any value between 0.5 V and +7.0 V provided that the supply voltage differences VCC are respected. [2] The supply voltage VCCO may have any value between 0.5 V and +5.0 V provided that the supply voltage differences VCC are respected. 8. Thermal characteristics Table 4. Thermal characteristics Symbol Parameter Rth(j-a) thermal resistance from junction to ambient thermal resistance from junction to case Rth(j-c) [1] Conditions Unit [1] 36.2 K/W [1] 14.3 K/W In compliance with JEDEC test board, in free air. ADC1207S080_3 Product data sheet Typ © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 5 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling 9. Characteristics Table 5. Characteristics VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = 40 C to +85 C; Vi(IN) Vi(INN) = 0.5 dBFS; Vref(fs) = VCCA 1.87 V; VI(cm) = VCCA 1.95 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 2.7 3.3 3.6 V ICCA analog supply current - 120 135 mA ICCD digital supply current - 50 65 mA ICCO output supply current fclk = 80 MHz; fi = 93 MHz - 10 15 mA Ptot total power dissipation fclk = 80 MHz; DC input - 840 990 mW Clock inputs: pins CLK and VIL CLKN[1] LOW-level input voltage referenced to DGND; VCCD = 5 V Positive Emitter-Coupled Logic (PECL) mode 3.19 - 3.52 V Transistor-Transistor Logic (TTL) mode DGND - 0.8 V 3.83 - 4.12 V 2.0 - VCCD V - - 28 A VCLK or VCLKN = 0.80 V 1 - - nA IIH HIGH-level input current VCLK or VCLKN = 3.83 V - - 30 A VCLK or VCLKN = 2.00 V 2 - - nA Vi(clk)dif differential clock input voltage VCLK VCLKN; AC mode; DC voltage level is 2.5 V 1.3 1.5 1.7 V Ri input resistance fclk = 80 MHz [2] - 6.3 - k Ci input capacitance fclk = 80 MHz [2] - 1.1 - fF - 5 - A VIH HIGH-level input voltage referenced to DGND; VCCD = 5 V PECL mode TTL mode IIL LOW-level input current VCLK or VCLKN = 3.52 V [2] Analog inputs: pins IN and INN Vref(fs) = VCCA 1.75 V IIL LOW-level input current IIH HIGH-level input current Vref(fs) = VCCA 1.75 V - 5 - A Ri input resistance [2] 6.3 - - M Ci input capacitance [2] - - 700 fF VI(cm) common-mode input voltage VCCA 2 VCCA 1.8 VCCA 1.6 V Vi(IN) = Vi(INN); output code = 2 047 Digital inputs: pins OTC and CE_N VIL LOW-level input voltage DGND - 0.3 VCCD V VIH HIGH-level input voltage 0.7 VCCD - VCCD V ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 6 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling Table 5. Characteristics …continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = 40 C to +85 C; Vi(IN) Vi(INN) = 0.5 dBFS; Vref(fs) = VCCA 1.87 V; VI(cm) = VCCA 1.95 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IIL LOW-level input current VIL = 0.8 V - 1 - A IIH HIGH-level input current VIH = 2.0 V - 1 - A Digital inputs: pins DEL0 and DEL1 VIL LOW-level input voltage DGND - 0.3 VCCD V VIH HIGH-level input voltage 0.7 VCCD - VCCD V IIL LOW-level input current VIL = 0.8 V - 8 - A IIH HIGH-level input current VIH = 2.0 V - 20 - A IL = 0 mA - VCCA 1.88 - V IL = 2 mA - VCCA 1.95 - V Voltage controlled regulator output: pin CMADC VO(cm) common-mode output voltage Reference voltage input: pin FSIN[3] Vref(fs) full-scale reference voltage - VCCA 1.80 - V Iref(fs) full-scale reference current - 0.1 - A Vi(a)(p-p) peak-to-peak analog input voltage - 1.85 - V reference output voltage IL = Iref(fs) - VCCA 1.80 - V IL = 2 mA - VCCA 1.82 - V see Figure 5; Vi = Vi(IN) Vi(INN); VI(cm) = VCCA 1.95 V Full-scale voltage controlled regulator output: pin FSOUT VO(ref) Digital outputs: pins D11 to D0, IR and CCS Output levels VOL LOW-level output voltage IOL = 2 mA DGND - DGND + 0.5 V VOH HIGH-level output voltage IOH = 0.4 mA VCCO 0.5 - VCCO V IOZ OFF-state output current output level between 0.5 V and VCCO 0.1 0 +0.1 A td(s) sampling delay time CL = 10 pF - 0.1 0.24 ns th(o) output hold time CL = 10 pF 2.6 3.8 - ns td(o) output delay time CL = 10 pF - 4.7 7.8 ns Timing[4] 3-state output delay tdZH float to active HIGH delay time - 3.6 - ns tdZL float to active LOW delay time - 3.9 - ns tdHZ active HIGH to float delay time - 9.2 - ns tdLZ active LOW to float delay time - 7.2 - ns ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 7 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling Table 5. Characteristics …continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = 40 C to +85 C; Vi(IN) Vi(INN) = 0.5 dBFS; Vref(fs) = VCCA 1.87 V; VI(cm) = VCCA 1.95 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 45 - 55 % - - 9.5 MHz 80 - - MHz CL = 10 pF; DEL0 = HIGH; DEL1 = LOW - 0.3 - ns CL = 10 pF; DEL0 = LOW; DEL1 = HIGH - 1.3 - ns CL = 10 pF; DEL0 = HIGH; DEL1 = HIGH - 2.3 - ns Clock timing inputs: pins CLK and CLKN duty cycle fclk(min) minimum clock frequency fclk(max) maximum clock frequency fclk = 80 MHz; fi = 175 MHz = 45 % to 55 % Timing complete conversion signal: pin CCS; see Figure 6 td(CCS) CCS delay time Analog signal processing (clock duty cycle 50 %) INL integral non-linearity fclk = 20 MHz; fi = 21.4 MHz - 2.0 - LSB DNL differential non-linearity fclk = 20 MHz; fi = 21.4 MHz; no missing code guaranteed - 0.6 - LSB Eoffset offset error VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 C; output code = 2 047 4 +8 +24 mV EG gain error VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 C - 2.5 - %FS B bandwidth fclk = 80 MHz; 3 dB; full-scale input 320 375 - MHz 2H second harmonic level fi = 21.4 MHz - 79 - dBc fi = 93 MHz - 78 - dBc fi = 175 MHz - 74 - dBc fi = 21.4 MHz - 84 - dBc fi = 93 MHz - 80 - dBc - 76 - dBc 3H third harmonic level [5] fi = 175 MHz THD Nth(RMS) - 75 - dBc fi = 93 MHz - 73 - dBc fi = 175 MHz - 68 - dBc Vi(IN) = Vi(INN); fclk = 80 MHz - 0.45 - LSB total harmonic distortion fi = 21.4 MHz RMS thermal noise [6] ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 8 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling Table 5. Characteristics …continued VCCA = 4.75 V to 5.25 V; VCCD = 4.75 V to 5.25 V; VCCO = 2.7 V to 3.6 V; AGND and DGND shorted together; Tamb = 40 C to +85 C; Vi(IN) Vi(INN) = 0.5 dBFS; Vref(fs) = VCCA 1.87 V; VI(cm) = VCCA 1.95 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions S/N signal-to-noise ratio fi = 21.4 MHz SFDR spurious free dynamic range Min Typ Max Unit - 67.4 - dBc fi = 93 MHz 63 67.2 - dBc fi = 175 MHz - 66.5 - dBc fi = 21.4 MHz - 76 - dBc fi = 93 MHz 68 78 - dBc fi = 175 MHz - 74 - dBc - 70 - dB - 89 - dBFS fi 1 = 91.5 MHz; fi 2 = 94.5 MHz - 86 - dBFS fi 1 = 174 MHz; fi 2 = 176 MHz - 83 - dBFS - 88 - dBFS fi 1 = 91.5 MHz; fi 2 = 93.5 MHz - 82 - dBFS fi 1 = 174 MHz; fi 2 = 176 MHz - 83 - dBFS ACPR adjacent channel power fi = 93 MHz; 5 MHz ratio channel spacing; B = 3.84 MHz IMD2 second-order intermodulation distortion IMD3 [1] third-order intermodulation distortion fi 1 = 21 MHz; fi 2 = 22 MHz fi 1 = 21 MHz; fi 2 = 22 MHz [7] [8] [8] The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation: a) PECL mode 1: (DC levels vary 1:1 with VCCD) CLK and CLKN inputs are at differential PECL levels. b) PECL mode 2: (DC levels vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC levels vary 1:1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF capacitor. e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has to be connected to the ground. [2] Guaranteed by design. [3] The ADC input range can be adjusted with an external reference connected to pin FSIN. This voltage has to be referenced to VCCA. [4] Output data acquisition: the output data is available after the maximum delay of td(o). [5] The 3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. [6] The total harmonic distortion is obtained with the addition of the first five harmonics. [7] The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency. [8] Intermodulation measured relative to either tone with analog input frequencies fi 1 and fi 2. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (6 dB below full-scale for each input signal). IMD3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product; IMD2 is the ratio of the RMS value of either input tone to the RMS value of the worst case second order intermodulation product. ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 9 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling 10. Additional information relating to Table 5 Table 6. Output coding with differential inputs Vi(IN) Vi(INN) = 1.9 V; Vref(fs) = VCCA1 1.87 V; typical values to AGND. Code Vi(IN) (V) Vi(INN) (V) IR Binary outputs (D11 to D0) Two’s complement outputs (D11 to D0) Underflow < 2.675 > 3.625 0 0000 0000 0000 1000 0000 0000 0 2.675 3.625 1 0000 0000 0000 1000 0000 0000 1 - - 1 0000 0000 0001 1000 0000 0001 2 047 3.15 3.15 1 0111 1111 1111 1111 1111 1111 4 094 - - 1 1111 1111 1110 0111 1111 1110 4 095 3.625 2.675 1 1111 1111 1111 0111 1111 1111 Overflow > 3.625 < 2.675 0 1111 1111 1111 0111 1111 1111 Table 7. Mode selection Two’s complement output (OTC) Chip enable input (CE_N) Data output (D0 to D11; IR) 0 0 binary; active 1 0 two’s complement; active X [1] 1 high-impedance [1] X = don’t care. CLK n 50 % td(o) data n−1 D0 to D11 data n VCCO − 0.5 V data n+1 0.5 V th(o) td(s) IN sample n sample n+1 sample n+2 sample n+3 sample n+4 014aaa432 Fig 3. Output timing diagram ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 10 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling 014aaa435 0 (1) power spectrum (dBc) −40 (2) −80 (3) (4) (5) (6) −120 −160 0 10 20 30 40 fi (MHz) (1) fi 1H = 15 MHz; 0 dBc (2) fi 2H = 5.1 MHz; 79.6 dBc (3) fi 3H = 9.88 MHz; 82.1 dBc (4) fi 4H = 20.1 MHz; 80.6 dBc (5) fi 5H = 30 MHz; 74.7 dBc (6) fi 6H = 35.1 MHz; 93.9 dBc THD (5H): 72.2 dBc SFDR: 74.7 dBc Fig 4. Single tone; fi = 175 MHz; fCLK = 80 MHz 014aaa436 2.2 Vi(a)(p-p) (V) 2.0 1.8 1.6 1.4 1.4 1.6 1.8 2.0 2.2 Vref(fs) (V) Fig 5. ADC full-scale; Vi(a)(p-p) as a function of Vref(fs) The ADC1207S080 allows modifying the ADC full-scale. This could be done with FSIN (full-scale input) according to Figure 5. ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 11 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling The ADC1207S080 generates an adjustable clock output called Complete Conversion Signal (CCS), which can be used to control the acquisition of converted output data by the digital circuit connected to the ADC1207S080 output data bus. Two logic inputs, DEL0 and DEL1 pins, allow adjusting the delay of the edge of the CCS signal to achieve an optimal position in the stable, usable zone of the data. Table 8. Complete conversion signal selection DEL1 DEL0 CCS output 0 0 high-impedance 0 1 active, typical delay 0.3 ns 1 0 active, typical delay 1.3 ns 1 1 active, typical delay 2.3 ns (1) D0 to D11 td(CCS) CCS 014aaa433 (1) td(CSS) is referenced to the middle of the active data. Fig 6. Complete conversion signal timing diagram ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 12 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling 11. Definitions 11.1 Static parameters 11.1.1 Integral Non-Linearity (INL) It is defined as the deviation of the transfer function from a best fit straight line (linear regression computation). The INL of the code i is obtained from the equation: V i i – V i ideal INL i = ----------------------------------------S where: S corresponds to the slope of the ideal straight line (code width); i corresponds to the code value; Vi is the input voltage. 11.1.2 Differential Non-Linearity (DNL) It is the deviation in code width from the value of 1 LSB. Vi i + 1 – Vi i DNL i = --------------------------------------S where: Vi is the input voltage; i from 0 to (2n 2). 11.2 Dynamic parameters Figure 7 shows the spectrum of a single tone full-scale input sine wave with frequency f, conforming to coherent sampling (f/fs = M/N, with M number of cycles and N number of samples, M and N being relatively prime), and digitized by the ADC under test. magnitude a1 SFDR s a2 a3 ak frequency 014aaa437 Fig 7. Single tone spectrum of full-scale input sine wave with frequency ft ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 13 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling Remark: In the following equations, Pnoise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and ‘quantization noise’. 11.2.1 SIgnal-to-Noise And Distortion (SINAD) The ratio of the output signal power to the noise plus distortion power for a given sample rate and input frequency, excluding the DC component: P signal SINAD dB = 10log 10 ---------------------------------------- P noise + distortion 11.2.2 Effective Number Of Bits (ENOB) It is derived from SINAD and gives the theoretical resolution an ideal ADC would require to obtain the same SINAD measured on the real ADC. A good approximation gives: SINAD – 1.76 ENOB = ---------------------------------6.02 11.2.3 Total Harmonic Distortion (THD) The ratio of the power of the harmonics to the power of the fundamental. For k 1 harmonics the THD is: P harmonics THD dB = 10log 10 ------------------------- P signal where: 2 2 2 P harmonics = 2 + 3 + + k 2 P signal = 1 The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics). 11.2.4 Signal-to-Noise ratio (S/N) The ratio of the output signal power to the noise power, excluding the harmonics and the DC component is: P signal S N dB = 10log 10 ---------------- P noise 11.2.5 Spurious Free Dynamic Range (SFDR) The number SFDR specifies available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious harmonic and non-harmonic, excluding DC component: 1 SFDR dB = 20log 10 ------------------ max S ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 14 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling 11.2.6 IMD2 (IMD3) magnitude f2 f1 2f1 − f2 2f2 − f1 f1 + 2f2 f1 + f2 f1 − f2 2f2 2f1 + f2 2f1 3f2 3f1 frequency 014aaa439 Fig 8. Spectral of dual tone input sine wave with frequency From a dual tone input sinusoid (ft1 and ft2, these frequencies being chosen according to the coherence criterion), the intermodulation distortion products IMD2 and IMD3 (respectively, 2nd and 3rd order components) are defined, as follows. The ratio of the RMS value of either tone to the RMS value of the worst second (third) order intermodulation product. The total InterModulation Distortion (IMD) is given by: P intermod IMD dB = 10log 10 ---------------------- P signal where: 2 P intermod = im f t1 – f t2 2 – im f t1 + f t2 2 + im 2f 2 with im f t1 t1 – f t2 2 + im f – 2f t2 2 + im 2f t1 2 + im f t1 + 2f t2 + + f t2 corresponding to the power in the intermodulation component at frequency ft. 2 2 P signal = f + f t1 t2 ADC1207S080_3 Product data sheet t1 © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 15 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling 12. Application information 12.1 ADC1207S080 in 3G radio receivers The ADC1207S080 has been proven in many 3G radio receivers with various operating conditions regarding Input Frequency (IF), signal IF bandwidth and sampling frequency. The ADC1207S080 is provided with a maximum analog input signal frequency of 400 MHz. It allows a significant cost-down of the RF front-end, from two mixers to only one, even in multi-carriers architecture. Table 9 describes some possible applications with the ADC1207S080 in high IF sampling mode. Table 9. Examples of possible fi, fclk, IF BW combinations supported fi (MHz) fclk (MHz) IF BW (MHz) [1] SNR (dB) SFDR (dBc) 350 80 5.00 65 71 243.95 9.60 0.25 71 80 96 76.80 1.60 72 76 96 76.80 4.80 71 77 96 76.80 20.00 68 76 80 61.44 10.00 70 85 78.4 44.80 3.50 71 76 70 40.00 1.25 72 79 [1] IF bandwidth corresponds to the observed area on the ADC output spectrum. For a dual carrier Wideband-Code-Division-Multiple-Access (W-CDMA) receiver, the most important parameters are sensitivity and Adjacent Channel Selectivity (ACS). The sensitivity is defined as the lowest detectable signal level. In W-CDMA, it can be far below the noise floor. This difference, between the sensitivity and the noise floor, is defined by the Sensitivity-to-Noise Ratio (SENR). Its value is negative due to the gain processing. The Adjacent Channel Power Ratio (ACPR) is the difference between the full-scale 3 dB peak and the noise floor. It represents the ratio of the adjacent-channel power and the average power level of the channel. The ACS is defined by the sum of SENR and ACPR. interfering channel wanted channel ACS ACPR noise floor NF SENR sensibility thermal noise 014aaa434 Fig 9. Adjacent channel sensitivity and ADC sensibility ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 16 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling 12.2 Application diagram ADT1_1WT 100 nF VCCA 6 3 2 5 4 1 n.c. CLK 50 Ω VCCD 2.2 kΩ 48 47 46 45 43 42 41 40 39 100 nF CCS DGND1 CLKN CLK VCCD1 AGND2 44 DGND1 VCCA2 VCCA1 AGND1 VCCA1 AGND1 VCCD1 TL431CPK 38 37 330 nF AGND1 100 Ω DEC 10 nF n.c. 100 nF FSOUT FSIN n.c. n.c. 34 4 33 5 32 6 31 ADC1207S080 7 30 29 8 9 28 DGND 10 27 11 26 12 25 14 DEL1 n.c. 13 15 16 17 18 10 nF 19 20 21 22 23 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 24 G1 IR INN 3 VCCO 4 35 OGND 1 CMADC 2 VCCO 100 nF 2 IN OGND IN 5 100 Ω OTC n.c. 6 36 CE_N 3 1 DGND2 AGND1 VCCD2 ADT1_1WT DEL0 n.c. VCCD VCCO VCCD 4700_000_S (16) (41) analog ground digital ground 330 nF 100 nF 10 nF 10 nF VCCA 4700_000_S (44) 100 nF 330 nF (45) 10 nF (47) 10 nF HF70ACB VCCO 5V XX GND XX IN 10 V 4.7 μF 3 LM317MDT 1 2 (21) OUT 240 Ω 470 nF ADJ 100 nF 10 nF (23) 10 nF 10 nF 300 Ω 014aaa438 Fig 10. Application diagram ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 17 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling 13. Package outline HTQFP48: plastic thermal enhanced thin quad flat package; 48 leads; body 7 x 7 x 1 mm; exposed die pad SOT545-2 c y exposed die pad side X Dh 36 25 A 24 37 ZE e E HE Eh (A 3) A A2 A1 w M θ bp Lp L pin 1 index 13 48 detail X 1 12 ZD w M bp v M A e D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. 1.2 mm A1 A2 A3 bp c D(1) Dh E(1) Eh e HD HE L Lp v w y 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 7.1 6.9 4.6 4.4 7.1 6.9 4.6 4.4 0.5 9.1 8.9 9.1 8.9 1 0.75 0.45 0.2 0.08 0.08 ZD(1) ZE(1) 0.9 0.6 0.9 0.6 θ 7° 0° Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT545-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 03-04-07 04-01-29 MS-026 Fig 11. Package outline SOT545-2 (HTQFP48) ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 18 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes ADC1207S080_3 20120702 Product data sheet - ADC1207S080_2 ADC1207S080_2 20080807 Product data sheet - ADC1207S080_1 Modifications: ADC1207S080_1 • • • • Corrections made to version number in Table 1. Corrections made to several entries in Table 5. Corrections made to alignment in Figure 10. Corrections made to Figure 11. 20080611 Product data sheet - - 15. Contact information For more information or sales office addresses, please visit: http://www.idt.com ADC1207S080_3 Product data sheet © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 19 of 20 ADC1207S080 Integrated Device Technology Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling 16. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 11.1 11.1.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additional information relating to Table 5 . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Static parameters . . . . . . . . . . . . . . . . . . . . . . 13 Integral Non-Linearity (INL) . . . . . . . . . . . . . . 13 11.1.2 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 12 12.1 12.2 13 14 15 16 ADC1207S080_3 Product data sheet Differential Non-Linearity (DNL) . . . . . . . . . . . Dynamic parameters . . . . . . . . . . . . . . . . . . . SIgnal-to-Noise And Distortion (SINAD) . . . . Effective Number Of Bits (ENOB) . . . . . . . . . Total Harmonic Distortion (THD) . . . . . . . . . . Signal-to-Noise ratio (S/N) . . . . . . . . . . . . . . . Spurious Free Dynamic Range (SFDR). . . . . IMD2 (IMD3) . . . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . ADC1207S080 in 3G radio receivers. . . . . . . Application diagram . . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 14 14 14 14 15 16 16 17 18 19 19 20 © IDT 2012. All rights reserved. Rev. 03 — 2 July 2012 20 of 20