INTEGRATED CIRCUITS DATA SHEET TDA8760 10-bit high-speed analog-to-digital converter Product specification Supersedes data of April 1994 File under Integrated Circuits, IC02 1996 Sep 12 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 FEATURES APPLICATIONS • 10-bit resolution • High-speed analog-to-digital conversion for • Sampling rate up to 40 MHz – Video signal digitizing • Total Harmonic Distortion (THD): −65 dB at 4.43 MHz full-scale and a 40 MHz clock frequency – High Definition TV (HDTV) – Digital video broadcasting (satellite and cable) • High signal-to-noise ratio over a large analog input frequency range (8.8 effective bits at 10 MHz full-scale input at a 40 MHz clock frequency) – Transient signal analysis – High energy physics research • +5 V power supplies – Sigma-delta (SD) modulators • Binary or two’s complement 3-state TTL outputs – Medical imaging • In-range 3-state TTL output – Radar pulse digitizing. • TTL compatible digital inputs • LOW-level AC clock input signal allowed GENERAL DESCRIPTION • Power dissipation 850 mW (typical) The TDA8760 is a monolithic bipolar 10-bit Analog-to-Digital Converter (ADC) for video or other applications. It converts the analog input signal into 10-bit binary coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are TTL compatible. However, a sine wave clock input signal is allowed. • Low analog input capacitance (typ. 4.5 pF), no buffer amplifier required • No external sample-and-hold circuit required • Analog Input; single or differential • External amplitude range control • Voltage controlled regulator included. 1996 Sep 12 2 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 4.75 5.0 5.25 V ICCA analog supply current − 95 100 mA ICCD digital supply current − 40 45 mA ICCO output supply current − 35 40 mA ILE DC integral linearity error fclk = 4 MHz − ±1.0 ±2.0 LSB DLE DC differential linearity error fclk = 4 MHz − ±0.6 ±1.0 LSB AILE AC integral linearity error fclk = 40 MHz; fi = 4.43 MHz − ±1.2 ±2.0 LSB fclk(max) maximum clock frequency TDA8760K/2 20 − − MHz TDA8760K/4 40 − − MHz Ptot total power dissipation − 850 970 mW Tamb operating ambient temperature 0 − +70 °C ORDERING INFORMATION TYPE NUMBER TDA8760K/2 TDA8760K/4 1996 Sep 12 PACKAGE NAME PLCC44 DESCRIPTION plastic leaded chip carrier; 44 leads 3 VERSION SOT187-2 SAMPLING FREQUENCY (MHz) 20 40 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 14 V CCA2 V CCA3 13 17 7 V CCD1 3 VCCD2 CLK CLK 21 2 1 AMP TDA8760 VI 10 VI 11 AMP SAMPLE AND HOLD COARSE ADC FINE DAC FINE ADC 24 OGND1 output ground 30 OGND2 output ground 37 OGND3 output ground 44 OGND4 output ground 42 43 V CCO3 V CCO4 Philips Semiconductors 15 VCCA1 10-bit high-speed analog-to-digital converter V refL BLOCK DIAGRAM 1996 Sep 12 V refH data outputs 27 4 29 31 32 33 ERROR CORECTION 34 TTL OUTPUTS 35 36 40 41 26 8 9 12 16 4 20 22 23 28 D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) IR 25 MBD222 - 2 AGND3 DGND1 DGND2 digital ground Fig.1 Block diagram for SO187 package. TDA8760 analog ground AGND4 handbook, full pagewidth AGND2 Product specification AGND1 VCCO1 OTC V CCO2 CS Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 PINNING SYMBOL PIN DESCRIPTION CLK 1 clock input CLK 2 complementary clock input VCCD1 3 digital supply voltage (+5 V) DGND1 4 digital ground n.c. 5 not connected n.c. 6 not connected VCCA1 7 analog supply voltage (+5 V) AGND1 8 analog ground AGND2 9 analog ground VI 10 analog input voltage VI 11 complementary analog input voltage AGND3 12 analog ground VCCA2 13 analog supply voltage (+5 V) VrefL 14 reference voltage LOW VrefH 15 reference voltage HIGH AGND4 16 analog ground VCCA3 17 analog supply voltage (+5 V) n.c. 18 not connected n.c. 19 not connected DGND2 20 digital ground VCCD2 21 digital supply voltage (+5 V) CS 22 chip select input (TTL level input; active HIGH) OTC 23 output two’s complement OGND1 24 output ground VCCO1 25 output supply voltage (+5 V) IR 26 in-range output D9 27 data output, bit 9 (MSB) VCCO2 28 output supply voltage (+5 V) D8 29 data output, bit 8 OGND2 30 output ground D7 31 data output, bit 7 D6 32 data output, bit 6 D5 33 data output, bit 5 D4 34 data output, bit 4 D3 35 data output, bit 3 D2 36 data output, bit 2 OGND3 37 output ground n.c. 38 not connected n.c. 39 not connected D1 40 data output, bit 1 1996 Sep 12 5 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter SYMBOL TDA8760 PIN DESCRIPTION CLK CLK OGND4 VCCO4 VCCO3 D0 (LSB) D1 44 43 42 41 40 handbook, full pagewidth 1 output ground 2 44 VCCD1 OGND4 3 output supply voltage (+5 V) DGND1 output supply voltage (+5 V) 43 4 42 VCCO4 n.c. VCCO3 5 data output, bit 0 (LSB) n.c. 41 6 D0 VCCA1 7 39 n.c. AGND1 8 38 n.c. AGND2 9 37 OGND3 V I 10 VI 36 D2 11 35 D3 AGND3 12 34 D4 TDA8760 V CCA2 13 33 D5 VrefL 14 32 D6 VrefH 15 31 D7 28 VCCO2 D9 (MSB) 27 26 IR VCCO1 25 OGND1 24 OTC 23 CS 22 21 VCCD2 DGND2 20 29 D8 n.c. 19 30 OGND2 V CCA3 17 n.c. 18 AGND4 16 Fig.2 Pin configuration for SOT187-2. 1996 Sep 12 6 MGA928-1 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage −0.3 +7.0 V VCCD digital supply voltage −0.3 +7.0 V VCCO output supply voltage −0.3 +7.0 V ∆VCC1 supply voltage difference between VCCA and VCCD −0.5 +0.5 V ∆VCC2 supply voltage difference between VCCO and VCCD −0.5 +0.5 V ∆VCC3 supply voltage difference between VCCA and VCCO −0.5 0.5 V VI input voltage 0.3 VCCA V VI(p-p) input voltage for differential clock drive (peak-to-peak value) − VCCD V IO output current − 10 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature 0 +70 °C Tj junction temperature − +150 °C referenced to AGND HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1996 Sep 12 PARAMETER THERMAL RESISTANCE Thermal resistance from junction to ambient in free air TDA8760K/4 35 K/W TDA8760K/2 46 K/W 7 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 CHARACTERISTICS VCCA = VCCD = VCCO = 4.75 to 5.25 V; AGND and DGND shorted together; VCCA − VCCD = VCCO − VCCD = VCCA − VCCO = −0.25 to +0.25 V; Tamb = 0 to +70 °C; unless otherwise specified. Typical values measured at VCCA = VCCD = VCCO = 5 V; Tamb = 25 °C. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 4.75 5.0 5.25 V ICCA analog supply current − 95 100 mA ICCD digital supply current − 40 45 mA ICCO output supply current − 35 40 mA all outputs LOW Inputs CLK AND CLK (REFERENCED TO DGND); note 1 VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VCCD V IIL LOW level input current Vclk or Vclk = 0.4 V −400 − − mA IIH HIGH level input current Vclk or Vclk = 2.0 V − − 100 mA Vclk or Vclk = VCCD − − 300 mA fclk = 40 MHz − 2 − kΩ ZI input impedance CI input capacitance fclk = 40 MHz − 4.5 − pF ∆Vclk AC input voltage for switching (Vclk − Vclk) DC level = 1.5 V 0.5 − 2.0 V DC level = 2.5 V 1.5 − 5.0 V 0 − 0.8 V OTC AND CS (REFERENCED TO DGND); see Table 3 VIL LOW level input voltage VIH HIGH level input voltage 2.0 − VCCD V IIL LOW level input current VIL = 0.8 V −400 − − µA IIH HIGH level input current VIH = 2.0 V − − 20 µA 1996 Sep 12 8 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter SYMBOL PARAMETER TDA8760 CONDITIONS MIN. TYP. MAX. UNIT VI AND VI (REFERENCED TO AGND); see also Tables 1 and 2 IIL LOW level input current VrefH − VrefL = 1.5 V − 7 − µA IIH HIGH level input current VrefH − VrefL = 1.5 V − 22 − µA ZI input impedance fi = 4.43 MHz − 2 − kΩ CI input capacitance fi = 4.43 MHz − 4.5 − pF VIoffset(d) input offset voltage differential mode; VI = VI; output code 511; Table 1 VCCA = 5 V 3.3 3.4 3.6 V VCCA = 4.75 V 3.2 − 3.45 V VCCA = 5.25 V 3.3 − 3.8 V VIoffset(s) input offset voltage single mode; VI = VIoffset(s); output code 511; Table 2 VCCA = 5 V 3.6 3.7 3.8 V VCCA = 4.75 V 3.5 − 3.65 V VCCA = 5.25 V 3.6 − 4.0 V Voltage controlled regulator inputs VrefH and VrefL (referenced to AGND); differential input VrefH reference voltage HIGH 4.0 4.5 VCCA V VrefL reference voltage LOW 2.5 3.0 3.5 V VI(p-p) input voltage amplitude (peak-to-peak value) 1.4 1.5 1.6 V IrefH input current at VrefH − 10 − µA IrefL input current at VrefL − 10 − µA Voltage controlled regulator inputs VrefH and VrefL (referenced to AGND); single input VrefH reference voltage HIGH 4.0 4.4 VCCA V VrefL reference voltage LOW 2.5 3.0 3.5 V VI(p-p) input voltage amplitude (peak-to-peak value) 1.3 1.4 1.5 V IrefH input current at VrefH − 10 − µA IrefL input current at VrefL − 10 − µA Outputs (referenced to DGND) DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO DGND) VOL LOW level output voltage IO = 2 mA 0 − 0.4 V VOH HIGH level output voltage IO = −0.4 mA 2.4 − VCCD V IO output current in 3-state mode 0.4 V < VO < VCCO −20 − +20 µA 1996 Sep 12 9 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter SYMBOL PARAMETER TDA8760 CONDITIONS MIN. TYP. MAX. UNIT Switching characteristics CLOCK FREQUENCY fclk (note 1; see Fig.3) fclk(min) minimum clock frequency fclk(max) maximum clock frequency − − 1 MHz TDA8760K/4 40 − − MHz TDA8760K/2 20 − − MHz 10 − − ns 8 − − ns tCPH clock pulse width HIGH tCPL clock pulse width LOW note 7 Analog signal processing in differential input mode; see Table 1; 50% clock duty factor; VI(p-p) = VrefH − VrefL = 1.5 V LINEARITY ILE DC integral linearity error fclk = 4 MHz − ±1.0 ±2.0 LSB DLE DC differential linearity error fclk = 4 MHz − ±0.6 ±1.0 LSB AILE AC integral linearity error note 3 − ±1.2 ±2.0 LSB OFE offset error VCCA = VCCD = VCCO = 5 V; VI = VI; Tamb = 25 °C; output code = 511 −3 − +3 LSB GE gain error; amplitude spread between devices VCCA = VCCD = VCCO = 5 V; Tamb = 25 °C; VrefH − VrefL = 1.5 V −10 − +10 LSB −1 dB − 140 − MHz −3 dB − 220 − MHz − − 0 dB BANDWIDTH (fclk = 40 MHZ); note 9 B Analog bandwidth HARMONICS (fclk = 40 MHZ); see Figs 6, 8 and 9 f1 fundamental harmonics (full scale) fi = 4.43 MHz fall harmonics (full scale); all components fi = 4.43 MHz THD second harmonics − −70 −63 dB third harmonics − −70 −63 dB − −65 −60 dB 54 56 − dB total harmonic distortion fi = 4.43 MHz; note 2 SIGNAL-TO-NOISE RATIO; notes 4 and 5; see Figs 6, 8 and 9 SNR signal-to-noise ratio 1996 Sep 12 without harmonics; fclk = 40 MHz; fi = 4.43 MHz; Tamb = 25 °C 10 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter SYMBOL PARAMETER TDA8760 CONDITIONS MIN. TYP. MAX. UNIT EFFECTIVE BITS; notes 4 and 5; see Figs 6, 8 and 9 EB effective bits TDA8760K/2 (fclk = 20 MHz) fi = 4.43 MHz − 8.90 − bits fi = 7.5 MHz − 8.70 − bits effective bits TDA8760K/4 (fclk = 40 MHz) fi = 4.43 MHz − 8.80 − bits fi = 10 MHz − 8.80 − bits fi = 15 MHz − 8.70 − bits fclk = 40 MHz; note 8 − −65 − dB fclk = 40 MHz; fi = 4.43 MHz; VI = ±16 LSB at code 512 − 2 × 10−12 − times/ samples TWO-TONE Two-tone two-tone intermodulation rejection BIT ERROR RATE BER bit error rate DIFFERENTIAL GAIN; SEE Fig.5 Gdiff differential gain fclk = 20 MHz; fi = 4.43 MHz − 0.5 − % fclk = 40 MHz; fi = 4.43 MHz − 1.0 − % fclk = 40 MHz; fi = 4.43 MHz − 0.1 0.2 deg DIFFERENTIAL PHASE Φdiff differential phase Analog signal processing in single input mode; see Table 2; 50% clock duty factor; VI(p-p) = VrefH − VrefL = 1.4 V LINEARITY ILE DC integral linearity error fclk = 4 MHz − ±1.0 ±2.0 LSB DLE DC differential linearity error fclk = 4 MHz − ±0.6 ±1.0 LSB AILE AC integral linearity error note 3 − ±1.2 ±2.0 LSB −1 dB − 140 − MHz −3 dB − 220 − MHz − − 0 dB second harmonics − −61 − dB third harmonics − −62 − dB − −59 − dB BANDWIDTH (fclk = 40 MHZ); note 9 B Analog bandwidth HARMONICS (fclk = 40 MHZ); see Fig.7 f1 fundamental harmonics (full scale) fi = 4.43 MHz fall harmonics (full scale); all components fi = 4.43 MHz THD total harmonic distortion 1996 Sep 12 fi = 4.43 MHz; note 2 11 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter SYMBOL PARAMETER TDA8760 CONDITIONS MIN. TYP. MAX. UNIT SIGNAL-TO-NOISE RATIO; notes 4 and 5; see Fig.7 SNR without harmonics; fclk = 40 MHz; fi = 4.43 MHz; Tamb = 25 °C 54 56 − dB effective bits TDA8760K/2 (fclk = 20 MHz) fi = 4.43 MHz − 8.70 − bits fi = 7.5 MHz − 8.50 − bits effective bits TDA8760K/4 (fclk = 40 MHz) fi = 4.43 MHz − 8.50 − bits fi = 10 MHz − 8.20 − bits two-tone intermodulation rejection fclk = 40 MHz; note 8 − −60 − dB fclk = 40 MHz; fi = 4.43 MHz; VI = ±16 LSB at code 512 − 2 × 10−12 − times/ samples fclk = 20 MHz; fi = 4.43 MHz − 0.5 − % fclk = 40 MHz; fi = 4.43 MHz − 1.0 − % fclk = 40 MHz; fi = 4.43 MHz − 0.1 0.2 deg signal-to-noise ratio EFFECTIVE BITS; notes 4 and 5; see Fig.7 EB TWO-TONE Two-tone BIT ERROR RATE BER bit error rate DIFFERENTIAL GAIN; see Fig.5 Gdiff differential gain DIFFERENTIAL PHASE Φdiff differential phase Timing (note 6; see Fig.3; CL = 15 pF) tds sampling delay time − − 2 ns th output hold time 8 − − ns td output delay time − 12 16 ns 16 ns 3-state output delay times (see Fig.4) tdZH enable HIGH − 12 tdZL enable LOW − 12 16 ns tdHZ disable HIGH − 8 12 ns tdLZ disable LOW − 16 20 ns 1996 Sep 12 12 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 Notes 1. The circuit has two clock inputs: CLK and CLK. There are three modes of operation: a) TTL mode 1: CLK input is at TTL level with a threshold voltage of 1.5 V and sampling is taken on the falling edge of the clock input signal. CLK decoupled to DGND via a 100 nF capacitor. b) TTL mode 2: CLK input is at TTL level with threshold voltage of 1.5 V and sampling is taken on the rising edge of the clock input signal. CLK decoupled to DGND via a 100 nF capacitor. c) TTL mode 3: CLK and CLK inputs are at differential TTL levels. d) AC driving modes: When driving the CLK input directly and with any AC signal of minimum 0.5 V (p-p) and with a DC level of 1.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal.It is recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor. 2. THD (total harmonic distortion) is obtained with the addition of the first five harmonics: F a) THD = 20 log --------------------------------------------------------------------------------------------------------------2 2 2 2 2 (2nd) + (3rd) + (4th) + (5th) + (6th) b) F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input. 3. AC linearity: full-scale differential sine wave (fi = 4.43 MHz; fclk = 40 MHz). 4. Effective bits with differential input and single input are respectively executed with full scale differential input and full-scale single sine wave. 5. Effective bits are obtained via a Fast Fourier Transformer (FFT) treatment taking 8K acquisition points per period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to SNR: SNR = EB × 6.02 + 1.76 dB. 6. Output data acquisition: the output data is available after the maximum delay of td. 7. tCPH of 9 ns (minimum) can be applied at the penalty of 0.5 effective bit drop compared to typical values. 8. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter. 9. The −3 dB (or −1 dB) analog bandwidth is determined by the 3 dB (or 1 dB) reduction in the reconstructed output, the input being a full-scale sine wave. 1996 Sep 12 13 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 Table 1 Output coding with differential inputs (typical values to AGND); VI(p-p) = VrefH − VrefL = 1.5 V CODE VI(p-p) VI(p-p) BINARY OUTPUTS TWO’S COMPLEMENT OUTPUTS D9 TO D0 D9 TO D0 IR underflow <3.025 >3.775 0 0000000000 1000000000 0 3.025 3.775 1 0000000000 1000000000 1 − − 1 0000000001 1000000001 • − − • •••••••••• •••••••••• 511 3.40 3.40 1 0111111111 1111111111 • − − • •••••••••• •••••••••• 1022 − − 1 1111111110 0111111110 1023 3.775 3.025 1 1111111111 0111111111 overflow >3.775 <3.025 0 1111111111 0111111111 Table 2 Output coding with single inputs (typical values to AGND); VI(p-p) = VrefH − VrefL = 1.4 V; VI(p-p) = 3.7 V CODE BINARY OUTPUTS TWO’S COMPLEMENT OUTPUTS D9 TO D0 D9 TO D0 IR VI(p-p) underflow <3.0 0 0000000000 1000000000 0 3.0 1 0000000000 1000000000 1 − 1 0000000001 1000000001 • − • •••••••••• •••••••••• 511 3.7 1 0111111111 1111111111 • − • •••••••••• •••••••••• 1022 − 1 1111111110 0111111110 1023 4.4 1 1111111111 0111111111 overflow >4.4 0 1111111111 0111111111 Table 3 Mode selection. OTC CS D0 TO D9 AND IR 1 1 binary; active 0 1 two’s complement; active X(1) 0 high impedance Note 1. Where: X = don’t care. 1996 Sep 12 14 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 t CPL t CPH 1.4 V CLK sample N sample N + 1 sample N + 2 Vl t dS t HD 2.4 V DATA D0 to D7 DATA N-2 DATA N-1 DATA N DATA N+1 1.4 V 0.4 V td MBD721 Fig.3 Timing diagram. full pagewidth V CCD CS 50 % t dHZ t dZH HIGH 90 % output data 50 % t dLZ LOW t dZL HIGH output data 50 % LOW TEST 10 % V CCD 3.3 kΩ S1 TDA8760 15 pF tdLZ VCCD tdZL VCCD tdHZ GND tdZH GND MBD723 CS CS = 100 kHz. Fig.4 Timing diagram and test conditions of 3-state output delay time. 1996 Sep 12 15 S1 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 digital output handbook, full pagewidth f i = 4.43 MHz Vi CODE 1023 V4 (1) f i = 4.43 MHz V3 (1) f i = 4.43 MHz V2 (1) f i = 4.43 MHz V1 (1) f i = 4.43 MHz (1) V0 DC offset voltage CODE 0 MBD722 (1) Full-scale divided-by-5. V n ( 1 to 4 ) – V0 G diff = maximum of ------------------------------------------ × 100% V0 Fig.5 Differential gain measurement conditions. MGA931 - 2 9.0 effective bits effective bits 40 MHz 8.8 f clk = 20 MHz 8.8 8.6 8.6 8.4 8.4 8.2 8.2 40 MHz 8.0 8.0 0 Fig.6 MBD223 - 1 9.0 f clk = 20 MHz 4 8 12 0 20 16 f i (MHz) Typical effective bits under differential input mode as a function of input signal frequency. 1996 Sep 12 Fig.7 16 2 4 6 8 10 f i (MHz) Typical effective bits under single input mode as a function of input signal frequency. Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 MRC299 0 amplitude (dB) –20.2 –40.4 –60.6 –80.8 –101 –121 0 1.25 2.50 3.75 5.00 6.25 7.50 8.75 10.0 f (MHz) Effective bits: 9.1; THD = −65.81 dB; Harmonic levels (dB): 2nd = −75.54; 3rd = −76.29; 4th = −74.90; 5th = −67.50; 6th = −90.87. Fig.8 Fast Fourier Transformer (fclk = 20 MHz; fi = 4.43 MHz); for differential input mode. MBD220 0 amplitude (dB) –20 –40 –60 –80 –100 –120 0 2.5 5 7.5 10 12.5 15 17.5 20 f (MHz) Effective bits: 8.92; THD = −65.86 dB; Harmonic levels (dB): 2nd = −70.92; 3rd = −68.48; 4th = −75.32; 5th = − 81.40; 6th = −72.69. Fig.9 Fast Fourier Transformer (fclk = 40 MHz; fi = 4.43 MHz); for differential input mode. 1996 Sep 12 17 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 INTERNAL PIN CONFIGURATION VCCA1 V CCA2 VCCA3 handbook, full pagewidth 7 VI and VI 13 V CCD1 V CCD2 17 3 CLK 21 CLK 1 2 VCCD VCCA 10 and 11 30 kΩ 30 kΩ AGND 1.5 V V CCA DGND V refL V refH 14 25 and 43 15 VCCO1 / VCCO4 AGND V CCO3 20 kΩ CS and OTC 22 and 23 31 to 36, 40 and 41 1.5 V 30 and 37 TDA8760 DGND 8 9 12 16 4 20 MGA978 AGND1 AGND2 AGND3 AGND4 DGND1 DGND2 analog ground digital ground Fig.10 Description of input and output circuitry. 1996 Sep 12 18 data output bit 7 to 0 OGND2 / OGND3 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 APPLICATION INFORMATION 100 nF handbook, full pagewidth CLK 5V differential analog inputs IN (1) 5V 100 nF 100 nF IN D0 (LSB) D1 100 nF 4.7 µF 4.7 µF 7 IN IN (2) (2) R1 R2 R3 (2) 5 4 R4 100 nF 3 2 1 44 43 42 41 40 38 9 37 10 36 D2 11 35 D3 TDA8760 34 D4 13 33 D5 14 32 D6 15 31 D7 16 30 17 (3) 100 nF 29 D8 18 19 20 21 22 23 24 25 26 27 28 (3) 100 nF 39 8 12 100 nF (2) 6 D9 (MSB) 5V 100 nF 3 V 4.5 V 100 nF 100 nF 5V 5V output format select chip select input The analog, digital and output supplies should be separated and decoupled. (1) Differential clock signals can be applied if required. (2) R1 and R2 must be determined in order to obtain a middle voltage of 3.4 V; see Table 1. (3) VrefH and VrefL must be decoupled to AGND. Fig.11 Application diagram for differential input mode. 1996 Sep 12 19 MGA979 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 100 nF handbook, full pagewidth single analog input CLK 5V (1) 5V 100 nF 100 nF IN D0 (LSB) D1 100 nF 7 100 nF IN 6 5 4 3 2 1 44 43 42 41 40 38 9 37 10 36 D2 35 D3 34 D4 13 33 D5 14 32 D6 15 31 D7 16 30 11 IN (2) (2) R1 R2 TDA8760 12 100 nF 100 nF 17 (3) 100 nF 29 D8 18 19 20 21 22 23 24 25 26 27 28 (3) 100 nF 39 8 D9 (MSB) 5V 100 nF 3 V 4.5 V 100 nF 100 nF 5V 5V output format select chip select input MGA980 The analog, digital and output supplies should be separated and decoupled. (1) Differential clock signals can be applied if required. (2) R1 and R2 must be determined in order to obtain 3.4 V at the transformer; see Table 1. Adaptation with the single input signal impedance must be taken care of. (3) VrefH and VrefL must be decoupled to AGND. Fig.12 Application diagram for differential input mode using an input transformer. 1996 Sep 12 20 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 100 nF handbook, full pagewidth single analog input CLK 5V (1) 5V 100 nF 100 nF IN D0 (LSB) D1 100 nF 4.7 µF 4.7 µF 7 IN IN (2) (2) R1 R2 R3 (2) 5 4 R4 100 nF 3 2 1 44 43 42 41 40 38 9 37 10 36 D2 11 35 D3 34 D4 13 33 D5 14 32 D6 15 31 D7 16 30 TDA8760 17 (3) 100 nF 29 D8 18 19 20 21 22 23 24 25 26 27 28 (3) 100 nF 39 8 12 100 nF (2) 6 D9 (MSB) 5V 100 nF 3 V 4.5 V 100 nF 100 nF 5V 5V output format select chip select input The analog, digital and output supplies should be separated and decoupled. (1) Differential clock signals can be applied if required. (2) R1 = R3; R2 = R4. R1, R2, R3 and R4 must be determined in order to obtain a middle voltage of 3.7 V; see Table 2. (3) VrefH and VrefL must be decoupled to AGND. Fig.13 Application diagram for single input mode. 1996 Sep 12 21 MGA981 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 PACKAGE OUTLINE PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 eD eE y X 39 A 29 28 40 bp ZE b1 w M 44 1 E HE pin 1 index A A4 A1 e (A 3) 6 β 18 k 1 Lp k 7 detail X 17 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT A A1 min. A3 A4 max. bp b1 mm 4.57 4.19 0.51 0.25 3.05 0.53 0.33 0.81 0.66 0.180 inches 0.020 0.01 0.165 D (1) E (1) e eD eE HD HE k 16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 k1 max. Lp v w y 0.51 1.44 1.02 0.18 0.18 0.10 Z D(1) Z E (1) max. max. 2.16 β 2.16 45 o 0.630 0.630 0.695 0.695 0.048 0.057 0.021 0.032 0.656 0.656 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.12 0.590 0.590 0.685 0.685 0.042 0.040 0.013 0.026 0.650 0.650 Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT187-2 112E10 MO-047AC 1996 Sep 12 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-25 97-12-16 22 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 SOLDERING Wave soldering Introduction Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream corners. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all PLCC packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 1996 Sep 12 23 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATION These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Sep 12 24 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 NOTES 1996 Sep 12 25 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 NOTES 1996 Sep 12 26 Philips Semiconductors Product specification 10-bit high-speed analog-to-digital converter TDA8760 NOTES 1996 Sep 12 27 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1200/02/pp28 Date of release: 1996 Sep 12 Document order number: 9397 750 01092