DP AK BUK6217-55C N-channel TrenchMOS intermediate level FET Rev. 3 — 9 July 2012 Product data sheet 1. Product profile 1.1 General description Intermediate level gate drive N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using advanced TrenchMOS technology. This product has been designed and qualified to the appropriate AEC Q101 standard for use in high performance automotive applications. 1.2 Features and benefits AEC Q101 compliant Suitable for standard and logic level gate drive sources Suitable for thermally demanding environments due to 175 °C rating 1.3 Applications 12 V and 24 V Automotive systems Start-Stop micro-hybrid applications Electric and electro-hydraulic power steering Transmission control Motors, lamps and solenoid control Ultra high performance power switching 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 55 V ID drain current VGS = 10 V; Tmb = 25 °C; see Figure 1 - - 44 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 80 W VGS = 10 V; ID = 12 A; Tj = 25 °C; see Figure 11 - 16 19 mΩ ID = 25 A; VDS = 44 V; VGS = 10 V; see Figure 13; see Figure 14 - 11.2 - nC ID = 44 A; Vsup ≤ 55 V; RGS = 50 Ω; VGS = 10 V; Tj(init) = 25 °C; unclamped - - 45 mJ Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy BUK6217-55C NXP Semiconductors N-channel TrenchMOS intermediate level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 G gate 2 D drain Simplified outline Graphic symbol mb 3 S source mb D mounting base; connected to drain D G mbb076 S 2 1 3 DPAK (SOT428) 3. Ordering information Table 3. Ordering information Type number BUK6217-55C Package Name Description Version DPAK plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428 4. Marking Table 4. Marking codes Type number Marking code BUK6217-55C BUK6217-55C BUK6217-55C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 July 2012 © NXP B.V. 2012. All rights reserved. 2 of 14 BUK6217-55C NXP Semiconductors N-channel TrenchMOS intermediate level FET 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C gate-source voltage VGS drain current ID Min Max Unit - 55 V DC [1] -16 16 V Pulsed [2] -20 20 V Tmb = 25 °C; VGS = 10 V; see Figure 1 - 44 A Tmb = 100 °C; VGS = 10 V; see Figure 1 - 31 A IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3 - 175 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 80 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Source-drain diode IS source current Tmb = 25 °C - 44 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 175 A ID = 44 A; Vsup ≤ 55 V; RGS = 50 Ω; VGS = 10 V; Tj(init) = 25 °C; unclamped - 45 mJ - - J Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy EDS(AL)R repetitive drain-source avalanche energy [1] -16V accumulated duration not to exceed 168 hrs [2] Accumulated pulse duration not to exceed 5mins. [3][4][5] [3] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. [4] Repetitive avalanche rating limited by an average junction temperature of 170 °C. [5] Refer to application note AN10273 for further information. BUK6217-55C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 July 2012 © NXP B.V. 2012. All rights reserved. 3 of 14 BUK6217-55C NXP Semiconductors N-channel TrenchMOS intermediate level FET 003aae797 50 03na19 120 ID (A) Pder (%) 40 80 30 20 40 10 0 0 0 Fig 1. 50 100 150 200 Tmb (°C) 0 50 100 150 200 Tmb (°C) Continuous drain current as a function of mounting base temperature Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aae798 103 ID (A) Limit RDSon = V DS / ID 102 tp =10 μ s 100 μ s 10 DC 1 1 ms 10 ms 100 ms 10-1 10-1 Fig 3. 1 10 102 VDS (V) 103 Safe operating area; continuous and peak drain currents as a function of drain-source voltage BUK6217-55C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 July 2012 © NXP B.V. 2012. All rights reserved. 4 of 14 BUK6217-55C NXP Semiconductors N-channel TrenchMOS intermediate level FET 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - - 1.87 K/W 003aae795 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 0.05 10-1 δ= P 0.02 tp T single shot t tp T -2 10 10-6 Fig 4. 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration BUK6217-55C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 July 2012 © NXP B.V. 2012. All rights reserved. 5 of 14 BUK6217-55C NXP Semiconductors N-channel TrenchMOS intermediate level FET 7. Characteristics Table 7. Symbol Characteristics Parameter Conditions Min Typ Max Unit 55 - - V Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C VGS(th) gate-source threshold voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 50 - - V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 9; see Figure 10 1.8 2.3 2.8 V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 10 - - 3.3 V ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 10 0.8 - - V IDSS drain leakage current VDS = 55 V; VGS = 0 V; Tj = 175 °C - - 500 µA VDS = 55 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µA IGSS gate leakage current VGS = 20 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - 2 100 nA - 16 19 mΩ VGS = 5 V; ID = 12 A; Tj = 25 °C; see Figure 11 - 19.6 24.5 mΩ VGS = 4.5 V; ID = 12 A; Tj = 25 °C; see Figure 11 - 21.2 28.5 mΩ VGS = 10 V; ID = 12 A; Tj = 175 °C; see Figure 12; see Figure 11 - - 42 mΩ ID = 25 A; VDS = 44 V; VGS = 5 V; see Figure 13; see Figure 14 - 19.3 - nC ID = 25 A; VDS = 44 V; VGS = 10 V; see Figure 13; see Figure 14 - 33.8 - nC - 5.2 - nC - 11.2 - nC - 1453 1950 pF - 156 190 pF - 110 152 pF RDSon drain-source on-state resistance VGS = 10 V; ID = 12 A; Tj = 25 °C; see Figure 11 Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) VGS = 0 V; VDS = 25 V; f = 1 MHz; Tj = 25 °C; see Figure 15 VDS = 45 V; RL = 1.8 Ω; VGS = 10 V; RG(ext) = 10 Ω - 9.8 - ns - 29.7 - ns turn-off delay time - 56 - ns tf fall time - 45.6 - ns LD internal drain inductance from upper edge of drain mounting base to centre of die ; Tj = 25 °C - 3.5 - nH LS internal source inductance from source lead to source bond pad ; Tj = 25 °C - 7.5 - nH BUK6217-55C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 July 2012 © NXP B.V. 2012. All rights reserved. 6 of 14 BUK6217-55C NXP Semiconductors N-channel TrenchMOS intermediate level FET Table 7. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit - 0.9 1.2 V Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 16 trr reverse recovery time Qr recovered charge IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 25 V 003aae799 100 43 - ns 70 - nC 003aae800 50 VGS (V) = 10 ID (A) - ID (A) 6.0 80 40 5.0 60 30 4.5 Tj = 175 °C 40 4.0 20 10 3.8 3.6 3.4 0 0 Fig 5. Tj = 25 °C 20 0.5 1 1.5 2 0 2.5 VDS(V) Output characteristics: drain current as a function of drain-source voltage; typical values 003aae805 100 0 Fig 6. 2 4 6 Transfer characteristics: drain current as a function of gate-source voltage; typical values 003aae801 50 gfs (S) RDSon (mΩ) VGS (V) 40 75 30 50 20 25 10 0 0 0 Fig 7. 4 8 12 16 0 20 VGS (V) Drain-source on-state resistance as a function of gate-source voltage; typical values BUK6217-55C Product data sheet Fig 8. 10 30 40 I D (A) 50 Forward transconductance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 July 2012 20 © NXP B.V. 2012. All rights reserved. 7 of 14 BUK6217-55C NXP Semiconductors N-channel TrenchMOS intermediate level FET 003aad806 10-1 003aad805 4 ID (A) VGS(th) (V) 10-2 3 min 10-3 typ max max typ 2 min -4 10 1 10-5 10-6 0 Fig 9. 1 2 3 VGS (V) 0 -60 4 Sub-threshold drain current as a function of gate-source voltage 003aae803 80 4.0 3.8 4.5 RDSon (mΩ) 0 60 120 180 Fig 10. Gate-source threshold voltage as a function of junction temperature 003aad803 2.5 VGS (V) = 5.0 Tj (°C) a 2 60 1.5 40 6.0 1 8.0 10 20 0.5 0 0 25 50 75 I D (A) 100 Fig 11. Drain-source on-state resistance as a function of drain current; typical values BUK6217-55C Product data sheet 0 -60 0 60 120 Tj (°C) 180 Fig 12. Normalized drain-source on-state resistance factor as a function of junction temperature All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 July 2012 © NXP B.V. 2012. All rights reserved. 8 of 14 BUK6217-55C NXP Semiconductors N-channel TrenchMOS intermediate level FET 003aae804 10 VDS VGS (V) ID 7.5 14V VGS(pl) VGS(th) VDS = 44V 5 VGS QGS1 QGS2 QGS 2.5 QGD QG(tot) 003aaa508 0 0 Fig 13. Gate charge waveform definitions 20 30 QG (nC) 40 Fig 14. Gate-source voltage as a function of gate charge; typical values 003aae802 104 10 003aae807 60 IS (A) C (pF) 45 Ciss 103 30 Coss Crss 102 Tj = 175 °C Tj = 25 °C 15 10 10-2 10-1 1 10 VDS (V) 0 102 0 Fig 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values BUK6217-55C Product data sheet 0.3 0.6 0.9 VSD (V) 1.2 Fig 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 July 2012 © NXP B.V. 2012. All rights reserved. 9 of 14 BUK6217-55C NXP Semiconductors N-channel TrenchMOS intermediate level FET 8. Package outline Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428 y E A A A1 b2 E1 mounting base D2 D1 HD 2 L L2 1 L1 3 b1 b w M c A e e1 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 b2 c D1 D2 min E E1 min e e1 HD L L1 min L2 w y max mm 2.38 2.22 0.93 0.46 0.89 0.71 1.1 0.9 5.46 5.00 0.56 0.20 6.22 5.98 4.0 6.73 6.47 4.45 2.285 4.57 10.4 9.6 2.95 2.55 0.5 0.9 0.5 0.2 0.2 OUTLINE VERSION SOT428 REFERENCES IEC JEDEC JEITA TO-252 SC-63 EUROPEAN PROJECTION ISSUE DATE 06-02-14 06-03-16 Fig 17. DPAK (SOT428) BUK6217-55C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 July 2012 © NXP B.V. 2012. All rights reserved. 10 of 14 BUK6217-55C NXP Semiconductors N-channel TrenchMOS intermediate level FET 9. Revision history Table 8. Revision history Document ID Release date Data sheet status Change notice Supersedes BUK6217-55C v.3 20120709 Product data sheet - BUK6217-55C v.2 - BUK6217-55C v.1 Modifications: BUK6217-55C v.2 BUK6217-55C Product data sheet • Various changes to content. 20101004 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 July 2012 © NXP B.V. 2012. All rights reserved. 11 of 14 BUK6217-55C NXP Semiconductors N-channel TrenchMOS intermediate level FET 10. Legal information 10.1 Data sheet status Document status[1] [2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 10.2 Definitions Preview — The document is a preview version only. The document is still subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 10.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 July 2012 © NXP B.V. 2012. All rights reserved. 12 of 14 BUK6217-55C NXP Semiconductors N-channel TrenchMOS intermediate level FET Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published athttp://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 10.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante,Bitport,Bitsound,CoolFlux,CoReUse,DESFire,EZ-HV,FabKey,G reenChip,HiPerSmart,HITAG,I²C-bus logo,ICODE,I-CODE,ITEC,Labelution,MIFARE,MIFARE Plus,MIFARE Ultralight,MoReUse,QLPAK,Silicon Tuner,SiliconMAX,SmartXA,STARplug,TOPFET,TrenchMOS,TriMedia andUCODE — are trademarks of NXP B.V. HD Radio andHD Radio logo — are trademarks of iBiquity Digital Corporation. 11. Contact information For more information, please visit:http://www.nxp.com For sales office addresses, please send an email to:[email protected] BUK6217-55C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 9 July 2012 © NXP B.V. 2012. All rights reserved. 13 of 14 BUK6217-55C NXP Semiconductors N-channel TrenchMOS intermediate level FET 12. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 10.1 10.2 10.3 10.4 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Contact information. . . . . . . . . . . . . . . . . . . . . .13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 9 July 2012 Document identifier: BUK6217-55C