BF1215 Dual N-channel dual gate MOSFET Rev. 01 — 6 May 2010 Product data sheet 1. Product profile 1.1 General description The BF1215 is a combination of two dual gate MOSFET amplifiers with shared source lead, shared gate2 lead and an integrated switch. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross modulation performance during AGC. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor is availiable as a SOT363 micro-miniature plastic package. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling. 1.2 Features and benefits Two low noise gain controlled amplifiers in a single package; one with full internal bias and one with partial internal bias Superior cross modulation performance during AGC High forward transfer admittance to input capacitance ratio Suitable for VHF and UHF applications: both amplifiers are optimized for VHF applications. Internal switch reduces external components 1.3 Applications Gain controlled low noise amplifiers for VHF and UHF applications with a 5 V supply Digital and analog television tuners Professional communication equipment BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 1.4 Quick reference data Table 1. Quick reference data for amplifier A and B Symbol Parameter Conditions Min Typ Max Unit - - 6 V - - 30 mA - - 180 mW 23 27 38 mS VDS drain-source voltage DC ID drain current DC Ptot total power dissipation Tsp ≤ 107 °C |yfs| forward transfer admittance f = 100 MHz; Tj = 25 °C; ID = 19 mA Ciss(G1) input capacitance at gate1 f = 100 MHz [2] - 2.5 - pF Crss reverse transfer capacitance f = 100 MHz [2] - 27 - fF NF noise figure - 1.5 - dB - 1.9 - dB 105 107 - dBμV - - 150 °C [1] f = 400 MHz; YS = YS(opt) f = 800 MHz; YS = YS(opt) Xmod cross modulation Tj junction temperature [3] input level for k = 1 % at 40 dB AGC; fw = 50 MHz; funw = 60 MHz [1] Tsp is the temperature at the soldering point of the source lead. [2] Calculated from S-parameters. [3] Measured in Figure 32 and Figure 33 test circuits. 2. Pinning information Table 2. Discrete pinning Pin Description 1 gate1 (amplifier A) 2 gate2 3 Simplified outline 6 5 Graphic symbol 4 AMP a gate1 (amplifier B) 4 drain (amplifier B) 5 source 6 drain (amplifier A) 1 2 3 G1 (A) D (A) G2 S G1 (B) D (B) AMP b sym033 3. Ordering information Table 3. Ordering information Type number BF1215 BF1215_1 Product data sheet Package Name Description Version - plastic surface-mounted package; 6 leads SOT363 All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 2 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 4. Marking Table 4. Marking Type number Marking Description BF1215 M4p made in Hong Kong M4t made in Malaysia M4w made in China 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per MOSFET VDS drain-source voltage DC - 6 V ID drain current DC - 30 mA IG1 gate1 current - ±10 mA IG2 gate2 current - ±10 mA Tsp ≤ 107 °C [1] Ptot total power dissipation - 180 mW Tstg storage temperature −65 +150 °C Tj junction temperature - 150 °C [1] Tsp is the temperature at the soldering point of the source lead. 001aac193 250 Ptot (mW) 200 150 100 50 0 0 50 100 150 200 Tsp (˚C) Fig 1. BF1215_1 Product data sheet Power derating curve All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 3 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Rth(j-sp) thermal resistance from junction to solder point Typ Unit 240 K/W 7. Static characteristics Table 7. Static characteristics Tj = 25 °C. Symbol Parameter Conditions Min Typ Max Unit amplifier A 6 - - V amplifier B 6 - - V Per MOSFET; unless otherwise specified V(BR)DSS drain-source breakdown voltage VG1-S = VG2-S = 0 V; ID = 10 μA V(BR)G1-SS gate1-source breakdown voltage VG2-S = VDS = 0 V; IG1-S = 10 mA 6 - 10 V V(BR)G2-SS gate2-source breakdown voltage VG1-S = VDS = 0 V; IG2-S = 10 mA 6 - 10 V VF(S-G1) forward source-gate1 voltage VG2-S = VDS = 0 V; IS-G1 = 10 mA 0.5 - 1.5 V VF(S-G2) forward source-gate2 voltage VG1-S = VDS = 0 V; IS-G2 = 10 mA 0.5 - 1.5 V VG1-S(th) gate1-source threshold voltage VDS = 5 V; VG2-S = 4 V; ID = 100 μA 0.3 - 1.0 V VG2-S(th) gate2-source threshold voltage VDS = 5 V; VG1-S = 5 V; ID = 100 μA 0.4 - 1.0 V IDS drain-source current VG2-S = 4 V; VDS(B) = 5 V; RG1 = 39 kΩ IG1-S IG2-S gate1 cut-off current gate2 cut-off current amplifier A: VDS(A) = 5 V [1] - - 19.5 mA amplifier B [2] - - 23 mA amplifier A: VG1-S(A) = 5 V - - 50 nA amplifier B: VG1-S(B) = 5 V - - 50 nA - - 20 nA VG2-S = 0 V; VDS(A) = VDS(B) = 0 V VG2-S = 4 V; VDS(A) = VDS(B) = 0 V; VG1-S(A) = VG1-S(B) = 0 V [1] RG1 connects gate1 amplifier B to VGG = 0 V, see Figure 2. [2] RG1 connects gate1 amplifier B to VGG = 5 V, see Figure 2. G1 (A) D (A) G2 S G1 (B) D (B) RG1 VGG 001aaa553 VGG = 5 V: amplifier A is off; amplifier B is on. VGG = 0 V: amplifier A is on; amplifier B is off. Fig 2. BF1215_1 Product data sheet Functional diagram All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 4 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 8. Dynamic characteristics Table 8. Dynamic characteristics for amplifier A and B Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 19 mA. Symbol Parameter Conditions |yfs| f = 100 MHz; Tj = 25 °C forward transfer admittance Min Typ Max Unit 23 27 38 mS Ciss(G1) input capacitance at gate1 f = 100 MHz [1] - 2.5 - pF Ciss(G2) input capacitance at gate2 f = 100 MHz [1] - 2.5 - pF f = 100 MHz [1] - 0.8 - pF reverse transfer capacitance f = 100 MHz [1] - 27 - fF transducer power gain [1] f = 200 MHz; GS = 2 mS; GL = 0.5 mS 30 34 38 dB f = 400 MHz; GS = 2 mS; GL = 1 mS 26 30 34 dB 22 26 30 dB f = 200 MHz; GS = 2 mS; GL = 0.5 mS 30 34 38 dB f = 400 MHz; GS = 2 mS; GL = 1 mS 26 31 34 dB f = 800 MHz; GS = 3.3 mS; GL = 1 mS 22 26 30 dB f = 11 MHz; GS = 20 mS; BS = 0 S - - 6 dB f = 400 MHz; YS = YS(opt) - 1.5 - dB - 1.9 - dB at 0 dB AGC 95 104 - dBμV at 10 dB AGC - 100 - dBμV at 20 dB AGC - 104 - dBμV at 40 dB AGC 105 107 - dBμV Coss Crss Gtr output capacitance amplifier A: BS = BS(opt); BL = BL(opt) f = 800 MHz; GS = 3.3 mS; GL = 1 mS amplifier B: BS = BS(opt); BL = BL(opt) NF noise figure [1] f = 800 MHz; YS = YS(opt) Xmod cross modulation input level for k = 1 %; fw = 50 MHz; funw = 60 MHz [1] Calculated from S-parameters. [2] Measured in Figure 32 and Figure 33 test circuits. BF1215_1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 [2] © NXP B.V. 2010. All rights reserved. 5 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 8.1 Graphics for amplifier A 001aal549 30 (1) (2) (3) (4) ID (mA) 001aal550 30 ID (mA) (5) 20 20 (1) (2) (6) (3) (4) 10 10 (5) (7) (6) (7) (8) (9) 0 0 0 0.5 1.0 1.5 2.0 2.5 VG1-S (V) 0 2 6 VDS (V) (1) VG2-S = 4 V. (1) VG1-S(A) = 1.9 V. (2) VG2-S = 3.5 V. (2) VG1-S(A) = 1.8 V. (3) VG2-S = 3 V. (3) VG1-S(A) = 1.7 V. (4) VG2-S = 2.5 V. (4) VG1-S(A) = 1.6 V. (5) VG2-S = 2 V. (5) VG1-S(A) = 1.5 V. (6) VG2-S = 1.5 V. (6) VG1-S(A) = 1.4 V. (7) VG2-S = 1 V. (7) VG1-S(A) = 1.3 V. VDS(A) = 5 V; VG1-S(B) = VDS(B) = 0 V; Tj = 25 °C. 4 (8) VG1-S(A) = 1.2 V. (9) VG1-S(A) = 1.1 V. VG2-S = 4 V; VG1-S(B) = VDS(B) = 0 V; Tj = 25 °C. Fig 3. Amplifier A transfer characteristics; typical values BF1215_1 Product data sheet Fig 4. Amplifier A output characteristics; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 6 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 001aal551 30 (1) (2) |yfs| (mS) 001aal552 16 ID(A) (mA) (3) 12 (4) 20 8 10 (5) 4 (6) 0 0 0 5 10 15 20 0 25 20 40 60 ID(B) (μA) ID (mA) (1) VG2-S = 4 V. VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = 5 V; VG1-S(B) = 0 V; Tj = 25 °C. (2) VG2-S = 3.5 V. ID(B) = internal gate1 current = current on pin drain (amplifier B) if MOSFET (B) is switched off. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. VDS(A) = 5 V; VG1-S(B) = VDS(B) = 0 V; Tj = 25 °C. Fig 5. Amplifier A forward transfer admittance as a function of drain current; typical values BF1215_1 Product data sheet Fig 6. Amplifier A drain current as a function of internal gate1 current; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 7 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 001aal553 20 001aal554 40 ID (mA) ID (mA) 15 30 (1) (2) 10 20 (3) (4) 5 10 (5) (6) 0 0 0 1 2 3 4 5 0 1 2 3 4 5 VG2-S (V) Vsup (V) VDS(A) = VDS(B) = Vsup; VG2-S = 4 V; Tj = 25 °C; RG1 = 39 kΩ (connected to ground); see Figure 2. (1) VDS(B) = 4 V. (2) VDS(B) = 3.5 V. (3) VDS(B) = 3 V. (4) VDS(B) = 2.5 V. (5) VDS(B) = 2 V. (6) VDS(B) = 1.5 V. VDS(A) = 5 V; VG1-S(B) = 0 V; gate1 (amplifier A) is open; Tj = 25 °C. Fig 7. Amplifier A drain current as a function of the supply voltage to amplifiers A and B; typical values 001aal555 120 Fig 8. Amplifier A drain current as a function of gate2 voltage; typical values 001aal556 0 gain reduction (dB) 10 Xmod (dBμV) 110 20 100 30 90 40 80 50 0 10 20 30 40 50 gain reduction (dB) 0 Amplifier A unwanted voltage for 1 % cross modulation as a function of gain reduction; typical values BF1215_1 Product data sheet 2 3 4 VAGC (V) VDS(A) = VDS(B) = 5 V; VG1-S(B) = 0 V; fw = 50 MHz; funw = 60 MHz; Tamb = 25 °C; see Figure 32. Fig 9. 1 VDS(A) = VDS(B) = 5 V; VG1-S(B) = 0 V; f = 50 MHz; Tj = 25 °C; see Figure 32. Fig 10. Amplifier A gain reduction as a function of AGC voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 8 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 001aal557 40 001aal558 102 gis, bis (mS) ID (mA) 30 10 bis 20 1 10 10−1 gis 10−2 0 0 10 20 30 40 50 gain reduction (dB) 10 001aal559 102 |yfs| (mS) −102 ϕfs (deg) |yfs| VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V; ID(A) = 19 mA; Tj = 25 °C. Fig 12. Amplifier A input admittance as a function of frequency; typical values 001aal560 103 ϕrs 1 10 −10 10 −1 103 102 1 10 f (MHz) Fig 13. Amplifier A forward transfer admittance and phase as a function of frequency; typical values Product data sheet −1 103 102 f (MHz) VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V; ID(A) = 19 mA; Tj = 25 °C. BF1215_1 −102 |yrs| −10 ϕfs −103 ϕrs (deg) |yrs| (mS) 102 10 103 f (MHz) VDS(A) = VDS(B) = 5 V; VG1-S(B) = 0 V; f = 50 MHz; Tj = 25 °C; see Figure 32. Fig 11. Amplifier A drain current as a function of gain reduction; typical values 102 VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V; ID(A) = 19 mA; Tj = 25 °C. Fig 14. Amplifier A reverse transfer admittance and phase as a function of frequency; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 9 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 001aal561 10 bos, gos (mS) 1 bos 10−1 gos 10−2 102 10 103 f (MHz) VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V; ID(A) = 19 mA; Tj = 25 °C. Fig 15. Amplifier A output admittance as a function of frequency; typical values 8.2 Scattering parameters for amplifier A Table 9. Scattering parameters for amplifier A VDS(A) = 5 V; VG2-S = 4 V; ID(A) = 19 mA; VDS(B) = 0 V; VG1-S(B) = 0 V; Tamb = 25 °C; typical values. f (MHz) s11 s21 s12 s22 Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) 50 0.992 −4.61 2.80 175.87 0.00078 95.65 0.993 −1.38 100 0.991 −8.79 2.80 172.12 0.00145 83.73 0.994 −2.76 200 0.986 −17.57 2.77 164.25 0.00292 78.53 0.992 −5.50 300 0.977 −26.11 2.74 156.52 0.00415 73.60 0.991 −8.21 400 0.966 −34.46 2.69 148.98 0.00528 69.27 0.989 −10.91 500 0.952 −42.75 2.64 141.49 0.00620 64.79 0.986 −13.58 600 0.936 −50.92 2.58 134.13 0.00691 60.71 0.984 −16.22 700 0.920 −58.79 2.50 127.01 0.00733 57.37 0.982 −18.86 800 0.902 −66.40 2.43 120.04 0.00758 54.40 0.979 −21.47 900 0.881 −73.87 2.36 113.24 0.00763 52.13 0.978 −24.00 1000 0.861 −81.10 2.28 106.69 0.00749 50.46 0.976 −26.55 8.3 Noise data for amplifier A Table 10. Noise data for amplifier A VDS(A) = 5 V; VG2-S = 4 V; ID(A) = 19 mA; VDS(B) = 0 V; VG1-S(B) = 0 V; Tamb = 25 °C; typical values; unless otherwise specified. f (MHz) BF1215_1 Product data sheet NFmin (dB) Γopt rn (ratio) (ratio) (degree) 400 0.9 0.810 27.95 0.884 800 1.4 0.697 56.50 0.717 All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 10 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 8.4 Graphics for amplifier B 001aal562 30 (1) (2) (3) (4) ID (mA) 001aal563 30 ID (mA) (5) 20 20 (1) (2) (6) (3) (4) 10 10 (5) (7) (6) (7) (8) (9) 0 0 0 0.5 1.0 1.5 2.0 2.5 VG1-S (V) 0 2 6 VDS (V) (1) VG2-S = 4 V. (1) VG1-S(B) = 1.9 V. (2) VG2-S = 3.5 V. (2) VG1-S(B) = 1.8 V. (3) VG2-S = 3 V. (3) VG1-S(B) = 1.7 V. (4) VG2-S = 2.5 V. (4) VG1-S(B) = 1.6 V. (5) VG2-S = 2 V. (5) VG1-S(B) = 1.5 V. (6) VG2-S = 1.5 V. (6) VG1-S(B) = 1.4 V. (7) VG2-S = 1 V. (7) VG1-S(B) = 1.3 V. VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C. 4 (8) VG1-S(B) = 1.2 V. (9) VG1-S(B) = 1.1 V. VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C. Fig 16. Amplifier B transfer characteristics; typical values BF1215_1 Product data sheet Fig 17. Amplifier B output characteristics; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 11 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 001aal564 100 001aal565 30 (1) IG1 (μA) (1) (2) |yfs| (mS) (2) (3) 75 (4) 20 (3) 50 (4) 10 (5) 25 (5) (6) (6) 0 0 0 0.5 1.0 1.5 2.0 2.5 VG1-S (V) 0 5 10 15 20 25 ID (mA) (1) VG2-S = 4 V. (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (6) VG2-S = 1.5 V. VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C. (7) VG2-S = 1 V. VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C. Fig 18. Amplifier B gate1 current as a function of gate1 voltage; typical values 001aal566 16 Fig 19. Amplifier B forward transfer admittance as a function of drain current; typical values 001aal567 20 ID (mA) ID (mA) 12 15 8 10 4 5 0 0 0 20 40 0 60 1 IG1 (μA) Fig 20. Amplifier B drain current as a function of gate1 current; typical values Product data sheet 3 4 5 VGG (V) VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C. BF1215_1 2 VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C; RG1 = 39 kΩ (connected to VGG); see Figure 2. Fig 21. Amplifier B drain current as a function of gate1 supply voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 12 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 001aal568 40 001aal569 40 (1) ID (mA) ID (mA) 30 30 (2) (1) (2) 20 20 (3) (3) (4) (4) 10 10 (5) (5) (6) 0 0 0 1 2 3 4 5 VGG = VDS (V) 0 1 (1) RG1 = 12 kΩ. (1) VGG = 4.0 V. (2) RG1 = 27 kΩ. (2) VGG = 3.5 V. (3) RG1 = 39 kΩ. (3) VGG = 3.0 V. (4) RG1 = 67 kΩ. (4) VGG = 2.5 V. (5) RG1 = 80 kΩ. (5) VGG = 2.0 V. VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C; RG1 is connected to VGG; see Figure 2. Fig 22. Amplifier B drain current as a function of gate1 supply voltage and drain supply voltage; typical values BF1215_1 Product data sheet 2 3 4 5 VG2-S (V) (6) VGG = 1.5 V. VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C; RG1 = 39 kΩ (connected to VGG); see Figure 2. Fig 23. Amplifier B drain current as a function of gate2 voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 13 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 001aal570 100 IG1 (μA) 75 001aal571 120 (1) Xmod (dBμV) (2) 110 (3) (4) 50 100 (5) 25 90 80 0 0 1 2 3 4 5 VG1-S (V) 0 10 20 30 40 50 gain reduction (dB) VDS(B) = 5 V; VGG = 5 V; VDS(A) = VG1-S(A) = 0 V; RG1 = 39 kΩ (connected to VGG); fw = 50 MHz; funw = 60 MHz; Tamb = 25 °C; see Figure 33. (1) VGG = 5.0 V. (2) VGG = 4.5 V. (3) VGG = 4.0 V. (4) VGG = 3.5 V. (5) VGG = 3.0 V. VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C; RG1 = 39 kΩ (connected to VGG); see Figure 2. Fig 24. Amplifier B gate1 current as a function of gate2 voltage; typical values 001aal572 0 gain reduction (dB) 10 Fig 25. Amplifier B unwanted voltage for 1 % cross modulation as a function of gain reduction; typical values 001aal573 40 ID (mA) 30 20 20 30 10 40 0 50 0 1 2 3 4 0 10 VAGC (V) BF1215_1 Product data sheet 30 40 50 gain reduction (dB) VDS(B) = 5 V; VGG = 5 V; VDS(A) = VG1-S(A) = 0 V; RG1 = 39 kΩ (connected to VGG); f = 50 MHz; Tamb = 25 °C; see Figure 33. VDS(B) = 5 V; VGG = 5 V; VDS(A) = VG1-S(A) = 0 V; RG1 = 39 kΩ (connected to VGG); f = 50 MHz; Tamb = 25 °C; see Figure 33. Fig 26. Amplifier B gain reduction as a function of AGC voltage; typical values 20 Fig 27. Amplifier B drain current as a function of gain reduction; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 14 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 001aal574 102 001aal575 102 −102 gis, bis (mS) |yfs| (mS) 10 ϕfs (deg) |yfs| bis 1 −10 10 ϕfs gis 10−1 10−2 10 102 1 103 10 −1 103 102 f (MHz) f (MHz) VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; ID(B) = 19 mA; Tj = 25 °C. Fig 28. Input admittance as a function of frequency; typical values 001aal576 103 −103 ϕrs (deg) |yrs| (mS) ϕrs 102 −102 VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; ID(B) = 19 mA; Tj = 25 °C. Fig 29. Forward transfer admittance and phase as a function of frequency; typical values 001aal577 10 bos, gos (mS) 1 bos |yrs| −10 10 1 10 −1 103 102 10−1 gos 10−2 10 VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; ID(B) = 19 mA; Tj = 25 °C. Fig 30. Reverse transfer admittance and phase as a function of frequency; typical values BF1215_1 Product data sheet 102 103 f (MHz) f (MHz) VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; ID(B) = 19 mA; Tj = 25 °C. Fig 31. Output admittance as a function of frequency; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 15 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 8.5 Scattering parameters for amplifier B Table 11. Scattering parameters for amplifier B VDS(B) = 5 V; VG2-S = 4 V; ID(B) = 15 mA; VDS(A) = 0 V; VG1-S(A) = 0 V; Tamb = 25 °C; typical values. f (MHz) s11 s21 s12 s22 Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) 50 0.987 −4.68 2.77 175.73 0.00074 100.59 0.992 −1.47 100 0.983 −8.74 2.75 171.97 0.00147 85.47 0.992 −3.03 200 0.979 −17.33 2.73 164.04 0.00291 83.85 0.991 −6.07 300 0.970 −25.74 2.70 156.20 0.00422 82.04 0.989 −9.06 400 0.961 −33.99 2.66 148.55 0.00547 80.56 0.987 −12.03 500 0.948 −42.21 2.60 140.92 0.00654 79.15 0.986 −14.99 600 0.932 −50.29 2.54 133.41 0.00744 78.33 0.983 −17.97 700 0.917 −58.13 2.47 126.14 0.00822 78.46 0.981 −20.93 800 0.900 −65.75 2.40 119.00 0.00890 78.92 0.978 −23.84 900 0.981 −73.19 2.33 112.02 0.00947 80.11 0.977 −26.71 1000 0.962 −80.36 2.25 105.26 0.00997 81.84 0.975 −29.63 8.6 Noise data for amplifier B Table 12. Noise data for amplifier B VDS(B) = 5 V; VG2-S = 4 V; ID(B) = 19 mA; VDS(A) = 0 V; VG1-S(A) = 0 V; Tamb = 25 °C; typical values; unless otherwise specified. f (MHz) BF1215_1 Product data sheet NFmin (dB) Γopt rn (Ω) (ratio) (deg) 400 1.1 0.755 27.61 0.860 800 1.6 0.659 56.19 0.712 All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 16 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 9. Test information VDS(A) 5V VAGC 4.7 nF 10 kΩ RGEN 50 Ω 50 Ω L1 2.2 μH 4.7 nF G1 (A) 4.7 nF G2 4.7 nF BF1215 G1 (B) Vi 50 Ω 4.7 nF D (A) RL 50 Ω S D (B) L2 2.2 μH RG1 4.7 nF VGG 0V VDS(B) 5V 001aal578 Fig 32. Cross-modulation test set-up for amplifier A. VDS(A) 5V VAGC 4.7 nF 10 kΩ 50 Ω 4.7 nF G1 (A) 4.7 nF G2 4.7 nF RGEN 50 Ω 50 Ω G1 (B) D (A) BF1215 L1 2.2 μH S D (B) RG1 4.7 nF L2 2.2 μH RL 50 Ω 4.7 nF Vi VGG 5V VDS(B) 5V 001aal579 Fig 33. Cross-modulation test set-up for amplifier B. BF1215_1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 17 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 10. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT363 JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 34. Package outline SOT363 BF1215_1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 18 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 11. Abbreviations Table 13. Abbreviations Acronym Description AGC Automatic Gain Control DC Direct Current MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor UHF Ultra High Frequency VHF Very High Frequency 12. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes BF1215_1 20100506 Product data sheet - - BF1215_1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 19 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 13.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. BF1215_1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 20 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] BF1215_1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 6 May 2010 © NXP B.V. 2010. All rights reserved. 21 of 22 BF1215 NXP Semiconductors Dual N-channel dual gate MOSFET 15. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Graphics for amplifier A . . . . . . . . . . . . . . . . . . 6 Scattering parameters for amplifier A . . . . . . . 10 Noise data for amplifier A . . . . . . . . . . . . . . . . 10 Graphics for amplifier B . . . . . . . . . . . . . . . . . 11 Scattering parameters for amplifier B . . . . . . . 16 Noise data for amplifier B . . . . . . . . . . . . . . . . 16 Test information . . . . . . . . . . . . . . . . . . . . . . . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 6 May 2010 Document identifier: BF1215_1