LatticeXP2 Brevia 2 Development Kit User’s Guide November 2011 Revision: EB67_01.0 LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor Introduction Thank you for choosing the Lattice Semiconductor LatticeXP2™ Brevia 2 Development Kit! This user’s guide describes how to start using the LatticeXP2 Brevia 2 Development Kit, an easy-to-use platform for evaluating and designing with LatticeXP2 FPGAs. Along with the evaluation board and accessories, this kit includes a pre-loaded Brevia System-on-Chip (SoC) demonstration design based on the LatticeMico8™ microcontroller. Note: Static electricity can severely shorten the life span of electronic components. Features The LatticeXP2 Brevia 2 Development Kit includes: • LatticeXP2 Brevia 2 Evaluation Board with the following on-board components and circuits: – LatticeXP2-5E 6TN144C – 2-Mbit SPI Flash memory – 128K by 8-bit SRAM – On-board USB controller for JTAG programming (FTDI - FT2232H) – 2x20 expansion header for general I/O – 1x8 JTAG programming header (unpopulated) – 2x5 expansion header for general I/O – Four debounced general purpose pushbuttons – One debounced reset pushbutton – 4-bit DIP switch (with 3 of 4 switches debounced) – Eight status LEDs • Pre-loaded Demo – The kit includes a pre-loaded demo design that integrates several Lattice reference designs including the LatticeMico8 microcontroller, SRAM controller, SPI Flash memory controller, and a UART peripheral. • USB Mini Cable – For power and JTAG programming. • LatticeXP2 Brevia 2 Development Kit Web Page — The LatticeXP2 Brevia 2 Development Kit web page on the Lattice web site provides access to the latest documentation, demo designs and drivers for the kit. The contents of this user’s guide include demo operation, top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, switches and a complete set of schematics of the LatticeXP2 Brevia 2 Evaluation Board. 2 LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor Figure 1. LatticeXP2 Brevia 2 Evaluation Board, Top Side 20x20 Expansion Header LatticeXP2 FPGA Reset Button SRAM Memory (128K x 8) DIP Switches JTAG Interface (Not Populated) Push-buttons USB Mini Interface 2x5 Expansion Header Status LEDs LatticeXP2 Device This board features a LatticeXP2 FPGA with a 1.2V core supply. It can accommodate all pin-compatible LatticeXP2 devices in the 144-pin TQFP (20x20 mm) package. A complete description of this device can be found in the LatticeXP2 Family Data Sheet. Demonstration Design Lattice provides a demo that illustrates key applications of the LatticeXP2 device. Demo_LatticeXP2_Brevia_SoC The Demo_LatticeXP2_Brevia_SoC is pre-programmed into the non-volatile Flash memory of the LatticeXP2 FPGA and is operational upon power-up. The design provides the following features: • Prints the ASCII representation of any characters received by the UART on the eight LEDS (D0-D7). • Prints the SPI memory ID code on demand. • Displays the current DIP switch setting on demand. • Logs Read ID and Read Switch commands, along with their results, into the asynchronous SRAM. • Stores the contents of the SRAM into the SPI ROM on demand. • Restores the SRAM contents from the SPI ROM on demand. 3 LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor The demo design integrates the following Lattice reference designs: • LatticeMico8 Microcontroller (RD1026) • WISHBONE UART (RD1042) • SPI WISHBONE Controller (RD1044) • LatticeMico8 to WISHBONE Interface Adapter (RD1043) Firmware running on the LatticeMico8 demonstrates control logic for the peripherals connected to a shared on-chip WISHBONE bus and communication between the LatticeXP2 Brevia 2 Evaluation Board and a host PC connected to the USB cable. Figure 2. Demo_LatticeXP2_Brevia_SoC Block Diagram LatticeXP2 Brevia Evaluation Board LED Bank Switch Bank LatticeXP2 FPGA LatticeMico8 UART PC Host USB FTDI Controller RS-232, JTAG WISHBONE Bus SPI Memory Controller SPI SPI 2-Mbit Flash Memory SRAM Memory Controller SRAM SRAM 1-Mbit Memory Set Up a VT100/ANSI Terminal Emulator The Demo_LatticeXP2_Brevia_SoC preloaded in the LatticeXP2 Brevia 2 Evaluation Board is operated by interacting with a monitor program. The monitor program sends and receives data across the RS232 communications port on the LatticeXP2 Brevia 2 Evaluation Board. It is necessary to start and configure a VT100 or ANSI style terminal emulator program like PuTTY, PuTTY Portable, Tera Term Pro (Windows) or Minicom (Linux). Follow these steps to interact with the monitor program: 1. Connect the Brevia 2 Evaluation Board to your computer using the supplied USB cable. 2. Install the required device drivers a. Install the FTDI USB driver during the installation of Lattice Diamond or standalone ispVM programming software. If you have already installed Diamond or ispVM without the driver, you can run the Diamond or ispVM installation again and install only the driver. b. Configure a Virtual COM port driver as described in the FTDI installation guide available on the FTDI website. 3. Start a terminal emulation program. The RS232 UART on the LatticeXP2 Brevia Evaluation Board is configured to operate at 115.2bps, 8 data bits, 1 stop bit, no parity, and no flow control. 4 LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor 4. Press the RESET button on the evaluation board. When configured correctly you will see a banner displayed, like the one shown below. ========================================================================= Welcome to the LatticeXP2 Brevia Development Kit SoC Demonstration Rev 1.0, April 2010 Main Menu -----------------------------------------------------------0: Re-display Main Menu 1: Read SPI Flash Memory IDCode 2: Read DIP Switch Bank 3: Read Data History from SRAM 4: Copy Data History from SRAM to SPI Flash Memory 5: Read Data History from SPI Flash Memory 6: Write Data to SRAM (Specified Address and Data) 7: Read Data from SRAM (Specified Address) 8: Write Data to SPI (Specified Address and Data) 9: Read Data from SPI (Specified Address) a: SRAM Auto-Test b: SPI Auto-Test Press 0-b to select an option. ========================================================================= SoC Command Monitor Features The LatticeXP2 Brevia 2 Evaluation Board, after it powers up or is reset, begins running a command interpreter monitor under the control of the LatticeMico8 microcontroller. The monitor code waits for a keypress and immediately performs the requested function. When the Read ID and Read Switch Bank commands are executed the ASCII output from the command is stored into the SRAM. The LatticeMico8 stores the next address to write in three of its general purpose registers. After power up the registers are cleared to 0x000000. Commands that have their results logged to the SRAM print out the address of the next available SRAM location. Read SPI Flash Memory IDCode Command The SPI ROM device on the LatticeXP2 Brevia 2 Evaluation Board can be queried and will return the ID code implemented by the ROM manufacturer. The LatticeMico8 initiates memory transactions using the SPI Memory controller to acquire the data. To scan the SPI Flash Memory IDCode: 1. From the terminal Main Menu, press 1. The LatticeMico8 performs the manufacturer specific SPI memory transactions to acquire the ID code. The ID number is returned as a hex value. This command logs the result to the SRAM. Example: ID:0x44 (SRAM ADDR:0x00006) Note: The ID for your board may differ. 5 LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor Read DIP Switch Bank The LatticeMico8 has the ability to read the state of switches 1-4 on the DIP switch bank. The pushbutton switches are can also be read. Each pushbutton press toggles the internal state of a register in the FPGA. The current state of the register is displayed on the high nibble of the output. The hexadecimal representation of the switches is printed and logged to the SRAM. A DIP switch that is set ON has a '0' value, and one that is OFF has a value of '1'. To read the DIP switch: 1. From the terminal window press 2. Example: SW:0x00 (SRAM ADDR:0x0000C) Read Data History from SRAM Use the Read Data History from SRAM command to see the results from each command that is logged to the SRAM memory. The output from this command does not get written into the SRAM. To read data history from SRAM: 1. From the terminal window press 3. The transaction log is listed. Example: SRAM: 0x44 0x00 Copy Data History from SRAM to SPI Flash Memory This command erases a portion of the SPI ROM, and stores the command results logged in the SRAM. The LatticeMico8 starts writing from SRAM address 0x000000 and continues writing values into the SPI ROM until it reaches the last valid entry in the SRAM. To copy data history from SRAM to SPI Flash memory: 1. From the terminal window press 4. The data log is transferred and the terminal indicates “Done”. Example: SRAM => SPI: 0x44 0x00 Done. Read Data History From SPI Flash Memory This command copies the Data History from the SPI ROM into the SRAM. After power is supplied, or RESET asserted the SRAM Data History log information is no longer available. Running this command permits the history to be restored from the non-volatile SPI ROM. To read data history from the SPI ROM into SRAM: 1. From the terminal window press 5. The transaction log is listed. Example: SPI Flash: 0x44 0x00 6 LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor Write Data to SRAM (Specified Address and Data) This command allows you to write a single data value to any location in the SRAM memory space. 1. From the terminal window press 6. Example: Please Enter the Address(17 bits,Hex), eg: 1f26a, no Spaces, then Press ENTER: 10000 Please Enter the Data(8 bits,Hex), eg: b7, no Spaces, then Press ENTER: 93 SRAM Write Done. Read Data from SRAM (Specified Address) This command allows you to read the data value from any address in the SRAM. 1. From the terminal window press 7. Example: Please Enter the Address(17 bits,Hex), eg: 1f26a, no Spaces, then Press ENTER: 10000 Read Data: 93 SRAM Read Done. Write Data to SPI (Specified Address and Data) This command allows you to write a single data value to any location in the SPI memory space. 1. From the terminal window press 8. Example: Please Enter the Address(18 bits,Hex), eg: 1f26a, no Spaces, then Press ENTER: 10000 Please Enter the Data(8 bits,Hex), eg: b7, no Spaces, then Press ENTER: 93 SPI Write Done. Read Data from SPI (Specified Address) This command allows you to read the data value from any address in the SPI. 1. From the terminal window press 9. Example: Please Enter the Address(18 bits,Hex), eg: 1f26a, no Spaces, then Press ENTER: 10000 Read Data: 93 SPI Read Done. 7 LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor Perform SRAM Auto-test This command automatically tests SRAM. 1. From the terminal window press a. Example: > a Starting SRAM Auto-Test......................................................... ....................................................................... SRAM Test Done: Successful. Perform SPI Auto-test This command automatically tests SPI. 1. From the terminal window press b. Example: >b Starting SPI Auto-Test.......................................................... ...................................................................... SPI Test Done: Successful. Download Demo Designs Lattice distributes source and programming files for a variety of demonstration designs compatible with the LatticeXP2 Brevia 2 Evaluation Board. To download demo designs: 1. Browse to the LatticeXP2 Brevia 2 Development Kit web page of the Lattice web site. Select the Demo Applications download and save the file. 2. Extract the contents of Demo_LatticeXP2_Brevia_Soc_vhdl.zip or Demo_LatticeXP2_Brevia_Soc_verilog.zip to an accessible location on your hard drive. One or more designs will be extracted and each will follow the following basic form. Demo Demo1 Directories Demo1 .\project .\source .\LatticeMico8_Vx_y_Verilog .\RD1042 .\project .\source .\RD1043 .\project .\source .\RD1044 .\project .\source .\RD1046 .\project .\source 8 LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor Where: • \project – Lattice Diamond® project (.ldf), preferences (.lpf), and programming file (.jed). This directory may contain intermediate results of the Diamond build process. • \source – HDL source for the Diamond project. • .\LatticeMico8_Vx_y_Verilog – LatticeMico8 Microcontroller Reference Design (RD1026). • .\RDxxxx – Reference designs integrated by the demo. Programming a Demo Design with the Lattice Diamond Programmer Demo_LatticeXP2_Brevia_SoC is pre-programmed into the LatticeXP2 Brevia Evaluation Board by Lattice. To restore a LatticeXP2 Brevia 2 Evaluation Board to factory settings, use the procedure described below. To program the LatticeXP2 FPGA: 1. Connect the USB cable to the host PC and the LatticeXP2 Brevia Evaluation Board. 2. From Diamond, click on the Programmer icon. Select Create a new Project from a Scan and browse for the .XCF file to import. 3. Click on Detect Cable. The Programmer will detect the cable (Cable: USB2, Port: FTUSB-0). 4. Click on the Program icon. When complete, PASS is displayed in the Status column. Recompile a Demonstration Project with Lattice Diamond® Design Software Use the procedure described below to recompile a demo project for the LatticeXP2 Brevia 2 Evaluation Board. 1. Install and license Lattice Diamond software. See www.latticesemi.com/latticediamond for download and licensing information. 2. Download the demo source files from the LatticeXP2 Brevia 2 Development Kit web page. 3. Run Lattice Diamond. 4. Use File > Open Project and open the Diamond <demo>.ldf. 5. From the Process view, select JEDEC File from the Export Files process. 6. Choose Export Files, right-click and choose Run. After a few moments the JEDEC programming file is output. 7. See the Programming a Demo Design with the Lattice Diamond Programmer section for details on how to download the demo design to the board. Reassembling the Demo LatticeMico8 Firmware Use this procedure to reassemble and download changes to the LatticeMico8 microcontroller firmware. 1. Install the LatticeMico8 Tool Code. Note: The LatticeMico8 tool executables are also provided in the . \Demo_LatticeXP2_Brevia_SoC\LatticeMico8_Vx_y_Verilog\utils directory and . \Demo_LatticeXP2_Brevia_SoC\LatticeMico8_Vx_y_VHDL\utils directory 2. The C source code for the LatticeMico8 Assembler and Simulator is included in the tools package. An optional step you can perform is to compile this source instead of using the pre-compiled versions supplied by Lattice. 9 LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor 3. Modify the Assembly source (.s) file, if desired, and recompile to a memory image (.hex). Source for Demo_LatticeXP2_Brevia_SoC is provided as Demo_LatticeXP2_Brevia_SoC.s. The assembler and simulator are command line applications. The tools display their invocation syntax if they are started without command line parameters. 4. Once the assembly code has been recompiled it is necessary to update the LatticeMico8 PROM contents. The fastest way to update the PROM contents is to use the Diamond Memory Initialization tool. The tool updates the PROM contents without modifying the connectivity of the design. Launch the Memory Initialization tool, and select the isp8_prom component, choose the new memory initialization file, click on the Apply Changes button, and save the new NCD file. 5. Run the Generate Data File (JEDEC) process. 6. Download the new JED file to the FPGA. You will see the effects of your assembly code changes. LatticeXP2 Brevia 2 Evaluation Board This section describes the features of the LatticeXP2 Brevia 2 Evaluation Board in detail. Overview The LatticeXP2 Brevia 2 Evaluation Board is a complete development platform for the LatticeXP2 FPGA. The board includes on-board SRAM and SPI Flash memory, and SPI microcontroller communication interfaces, a USB port, and an expansion header to support test connections. Figure 3. LatticeXP2 Brevia 2 Evaluation Board Block Diagram Debounced Pushbutton (x4) 2x20 Header 31 2x5 Header 8 SPI Flash GSRN/IO GPIO 4 Debounced Pushbutton 4-Bit DIP Switch (Debounced except 4-to-5) 4 8 SPI 1 Mbit SRAM USB to JTAG or 1x8 JTAG Header 28 LatticeXP2 LFXP2-5E-6TN144C JTAG Programming 8 LEDs 50 MHz Crystal Serial Communication USB to RS232 Serial 10 LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor I/O Mapping Details Expansion Header 1 Interface Access to 40 I/Os are available to the user via the expansion header J3. The connector type is a 2x20 0.100" center-to-center Berg stick, male. The interface details are included in Table 1. Table 1. Expansion Header 1 Interface Expansion Connector Pin Number Expansion Connector/FPGA Pin Name FPGA Pin Number Pin Functionality Expansion Connector J3 1 3.3V 2 3.3V 3 EXP_IO15 4 5 6 7 8 9 Power Power 103 I/O EXP_IO31 69 I/O EXP_IO14 102 I/O EXP_IO30 66 I/O EXP_IO13 101 I/O EXP_IO29 65 I/O EXP_IO12 100 I/O 10 EXP_IO28 62 I/O 11 EXP_IO11 99 I/O 12 EXP_IO27 61 13 GND I/O Ground 14 GND 15 EXP_IO10 98 Ground I/O 16 EXP_IO26 116 I/O 17 EXP_IO9 96 I/O 18 EXP_IO25 115 I/O 19 EXP_IO8 94 I/O 20 EXP_IO24 114 I/O 21 EXP_IO7 93 I/O 22 EXP_IO23 113 I/O 23 EXP_IO6 92 I/O 24 EXP_IO22 78 25 GND I/O Ground 26 GND 27 EXP_IO5 91 Ground I/O 28 EXP_IO21 77 I/O 29 EXP_IO4 90 I/O 30 EXP_IO20 74 I/O 31 EXP_IO3 89 I/O 32 EXP_IO19 73 I/O 33 EXP_IO2 88 I/O 34 EXP_IO18 108 I/O 35 EXP_IO1 87 I/O 36 EXP_IO17 107 37 GND I/O Ground 11 LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor Table 1. Expansion Header 1 Interface (Continued) Expansion Connector Pin Number Expansion Connector/FPGA Pin Name FPGA Pin Number 38 GND 39 XP2_RESET 19 Reset 40 EXP_IO16 104 I/O Pin Functionality Ground Expansion Header 2 Interface The connector is a 10-pin dual-row Berg stick, male. The interface details are included in Table . Table 2. Expansion Header 2 Interface Expansion Connector Pin Number Expansion Connector Pin Name FPGA Pin Number Pin Functionality EXP_IO36 31 I/O Expansion Connector J2 1 2 3.3V 3 EXP_IO37 32 Power I/O 4 EXP_IO32 27 I/O 5 EXP_IO38 35 I/O 6 EXP_IO33 28 I/O 7 EXP_IO39 36 I/O 8 EXP_IO34 29 9 GND 10 EXP_IO35 I/O Ground 30 I/O LEDs and Switches Eight LEDs, four debounced pushbutton switches and one DIP (4) switch are provided. All DIP switches are debounced except the SW1D connection (4-to-5, #55 on the silkscreen). Table 3. LED Interface LED FPGA Pin Number D1 46 D2 45 D3 44 D4 43 D5 40 D6 39 D7 38 D8 37 12 LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor Table 4. Switch Interface Switch FPGA Pin Number SW1A 58 SW1B 57 SW1C 56 1 SW1D 55 SW3 54 SW4 53 SW5 52 SW6 50 1. SW1D is not debounced. Flash Interface The LatticeXP2 Brevia 2 Evaluation Board provides 2 Mbits of non-volatile Flash memory. The Flash uses the fourwire SPI communication interface. Table 5. Flash Interface Flash Signal Name FPGA Pin Number FPGA Flash 2 Mbit (U1) XP2_SPI_CS0 11 XP2_SPI_CLK 13 XP2_SPI_IN 15 XP2_SPI_OUT 16 FLASH_RSTn 17 FLASH_Wn 18 SRAM Interface The LatticeXP2 Brevia 2 Evaluation Board provides 1Mbit of asynchronous SRAM memory in a 128K x 8-bit configuration. Table 6. SRAM Interface SRAM Signal Name FPGA Pin Number FPGA SRAM 1 Mbit (U2) Data_0 1 Data_1 2 Data_2 5 Data_3 6 Data_4 7 Data_5 8 Data_6 9 Data_7 10 Addr_0 119 Addr_1 120 Addr_2 121 Addr_3 122 13 LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor SRAM Signal Name FPGA Pin Number Addr_4 123 Addr_5 124 Addr_6 125 Addr_7 127 Addr_8 129 Addr_9 130 Addr_10 131 Addr_11 132 Addr_12 133 Addr_13 134 Addr_14 137 Addr_15 138 Addr_16 141 SRAM_CSb 142 SRAM_OEb 143 SRAM_WEb 144 Please note the JTAG header is not populated by default. It is recommended to use the USB mini cable and onboard USB configuration circuit as described elsewhere in this document. Table 7. JTAG Programming Interface JTAG Connector Pin Number JTAG Connector Pin Name FPGA Pin Number FPGA Pin Name Pin Functionality JTAG Connector J1 1 3.3V — — VCC 2 TDO 82 TDO TDO 3 TDI 80 TDI TDI 4 — — — None 5 — — — None 6 TMS 79 TMS TMS 7 GND — — GND 8 TCK 81 TCK TCK FPGA The Lattice XP2 Brevia 2 Evaluation Board is based on the LatticeXP2 non-volatile FPGA. The board is populated with a 5K LUT device in a 144 TQFP package. A complete description of the device can be found in the LatticeXP2 Family Data Sheet and on the LatticeXP2 web page. Software Requirements Install the Lattice Diamond software before you begin developing designs for the evaluation board. Mechanical Specifications Dimensions: 3 in (L) x 3 in (W) x 1/2 in (H) Environmental Requirements The evaluation board must be stored between -40° C and 100° C. The recommended operating temperature is between 0° C and 55° C. The evaluation board can be damaged without proper anti-static handling. 14 LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor Glossary DIP: Dual In-line Package FPGA: Field-Programmable Gate Array LED: Light Emitting Diode LUT: Look-Up Table PCB: Printed Circuit Board RoHS: Restriction of Hazardous Substances Directive PLL: Phase Locked Loop SPI: Serial Peripheral Interface SRAM: Static Random Access Memory UART: Universal Asynchronous Receiver/Transmitter WDT: Watchdog Timer Troubleshooting The LatticeXP2 Brevia 2 Evaluation Board is not responsive. • Verify the LatticeXP2 device is programmed. The functionality displayed by the board does not match the demo features described. It is possible the LatticeXP2 Brevia 2 Evaluation Board has been reprogrammed. You can either reprogram the FPGA with the demonstration bitstream, or read the checksum of the bitstream loaded in the FPGA. To restore the LatticeXP2 Brevia 2 Evaluation Board to the factory default, see the Download Demo Designs section of this document for details on downloading and reprogramming the device. You can use Diamond Programmer to read the checksum of the bitstream programmed into the FPGA. This value can be compared against the checksum stored in the JEDEC file. The JEDEC file checksum value is the last line in the file. This may allow you to determine the contents of the FPGA. A final option is to use Diamond Programmer to read the current bitstream in the FPGA, and then to reprogram the FPGA with your desired bitstream. Ordering Information Description LatticeXP2 Brevia 2 Development Kit Ordering Part Number LFXP2-5E-B2-EVN Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com 15 China RoHS Environment-Friendly Use Period (EFUP) LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor Revision History Date Version November 2011 01.0 Change Summary Initial release. (c) 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 17 A 5 4 Battery and Power from USB 5V OSC 50MHz 3 JTAG 3 BANK 7 B C 4 FLASH BANK 1 RS232 BANK 4 2 LEDs and Switches BANK 5 FPGA LFXP2-5E-TN144 BANK 0 SRAM 2 1 Date: Thursday, December 09, 2010 LFXP2-5E-B2-EVN Document Number 1 Sheet 1 of 5 Rev A Lattice XP2 Brevia 2 Evaluation Board - Block Diagram AXELSYS Exp Header Size B Title Exp Header BANK 2 BANK 3 D 5 A B C D Lattice Semiconductor LatticeXP2 Brevia 2 Development Kit User’s Guide Appendix A. Schematics Figure 4. LatticeXP2 Brevia 2 Evaluation Board Block Diagram BANK 6 USB to JTAG / RS232 USB CON A B C C12 0.1uF +3.3V 8 7 6 5 CS CLK DI DO 5 93LC56-SO8 VCC NU ORG VSS U2 1 2 3 4 0.1uF 0.1uF 0.1uF R11 10k +3.3V C6 C9 C5 +3.3V R12 10k 0.1uF C7 R14 R13 10k 2k2 0.1uF C8 4 L2 1 2 600ohm 500mA L1 2 1 600ohm 500mA C13 18pF 0.1uF 10uF 2 1 C11 C10 VCC1_8FT +3.3V +3.3V 3 12MHZ 4 3 +3.3V C3 4u7 C1 4u7 G1 G2 1 X1 1 2 1 2 D 4 5 5 12k 1% R9 C14 18pF 3 FT_EECS FT_EECLK FT_EEDATA R10 5k1 0.1uF C4 0.1uF C2 3 DM DP 13 3 2 63 62 61 6 14 7 8 49 50 VCC1_8FT FT2232H +3.3V PWREN# BCBUS0 BCBUS1 BCBUS2 BCBUS3 BCBUS4 BCBUS5 BCBUS6 BCBUS7 BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 ACBUS0 ACBUS1 ACBUS2 ACBUS3 ACBUS4 ACBUS5 ACBUS6 ACBUS7 ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 SUSPEND# FTDI High-Speed USB TEST OSCO OSCI EECS EECLK EEDATA REF RESET# DM DP VREGOUT VREGIN U1 FT2232HL AGND 10 5 4 9 VPHY VPLL 12 37 64 VCORE VCORE VCORE 20 31 42 56 VCCIO VCCIO VCCIO VCCIO GND GND GND GND GND GND GND GND 18 1 5 11 15 25 35 47 51 36 60 48 52 53 54 55 57 58 59 38 39 40 41 43 44 45 46 26 27 28 29 30 32 33 34 16 17 18 19 21 22 23 24 TDO TDI TMS 2 2 0 0 0 0 R1 5k1 DNI 1 2 3 4 5 6 7 8 AXELSYS 4 4 +3.3V TCK TCK TMS TDO TDI 1 TCK 5 TDI 5 TDO 5 TMS 5 R4 5k1 Date: Size B Thursday, December 09, 2010 LFXP2-5E-B2-EVN Document Number 1 Sheet 2 of 5 Rev A Lattice XP2 Brevia 2 Evaluation Board-USB to JTAG/RS232 Title 1 2 3 4 5 6 7 8 J1 header_1x8 DNI R3 5k1 DNI RS232_Rx_TTL RS232_Tx_TTL RTSn 4 CTSn 4 DTRn 4 DSRn 4 DCDn 4 R5 R6 R7 R8 R2 5k1 DNI +3.3V A B C D Lattice Semiconductor LatticeXP2 Brevia 2 Development Kit User’s Guide Figure 5. USB to JTAG/RS232 A B C 4 1 1 1 1 4 3 2 1 D1 Red R15 470 +3.3V 2k2 R23 SW3 4 5 SW_SPST_4DIP_LP 6 SW_SPST_4DIP_LP 7 SW_SPST_4DIP_LP 8 SW_SPST_4DIP_LP 5 SPST-NO SW6 4 SPST-NO SW5 4 SPST-NO SW4 4 SPST-NO SW1D SW1C SW1B SW1A STATUS_LED[0:7] 5 1 2 1 STATUS_LED7 2 2k2 R24 2k2 R25 D2 Red R16 470 LEDs 1 2 1 STATUS_LED6 2 1 2 1 2k2 R26 STATUS_LED5 2 2k2 R27 2k2 R28 +3.3V D3 Red R17 470 1 2 1 STATUS_LED4 2 2k2 R29 D4 Red R18 470 2k2 R30 4 1 2 1 4 STATUS_LED3 2 SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 D5 Red R19 470 1 2 1 STATUS_LED2 2 4 D7 Red R21 470 Switches XP2_SW3 D6 Red R20 470 1 2 1 STATUS_LED1 2 1 2 1 STATUS_LED0 2 D 2 3 2 3 2 2 3 3 SW_RESET D8 Red R22 470 3 3 10 2 3 4 5 6 7 8 9 1 Vcc CH OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 MAX6818 GND IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 EN U5 4 FLASH_RSTn 4 FLASH_Wn 0.1uF C15 +3.3V 11 19 18 17 16 15 14 13 12 20 U3 S C D Q 1 6 5 2 4 XP2_SW0 XP2_SW1 XP2_SW2 XP2_SW4 XP2_SW5 XP2_SW6 XP2_SW7 RESET 4 0.1uF C18 Addr_[0:16] SST25VF020-20-4C-SAE Vcc Reset W Vss +3.3V 8 7 3 4 4 4 4 4 4 4 4 SPI Flash 2 4 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 GND GND CS1 WE OE 25 9 5 12 28 AXELSYS 4 4 4 1 SRAM Data_[0:7] 4 Thursday, December 09, 2010 LFXP2-5E-B2-EVN Document Number 1 Sheet 3 of 5 Rev A Lattice XP2 Brevia 2 Evaluation Board - Mem, LEDs, Sw Date: Size B 0.01uF SW_RESET SRAM_CSb SRAM_WEb SRAM_OEb Data_0 Data_1 Data_2 Data_3 Data_4 Data_5 Data_6 Data_7 GLOBAL RESET R32 0 C19 R31 10k +3.3V IDT71V124SA15TYG8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 Title 1 2 3 4 13 14 15 16 17 18 19 20 21 29 30 31 32 VCC VCC 6 7 10 11 22 23 26 27 0.1uF 0.1uF U4 C17 C16 8 24 SPST-NO XP2_RESET 1 SW2 4 Addr_0 Addr_1 Addr_2 Addr_3 Addr_4 Addr_5 Addr_6 Addr_7 Addr_8 Addr_9 Addr_10 Addr_11 Addr_12 Addr_13 Addr_14 Addr_15 Addr_16 +3.3V XP2_SPI_CS0 4 XP2_SPI_CLK 4 XP2_SPI_IN 4 XP2_SPI_OUT 4 2 2 19 3 A B C D Lattice Semiconductor LatticeXP2 Brevia 2 Development Kit User’s Guide Figure 6. Memory, LEDs, Switching 20 A B C D 3 Data_[0:7] 3 5 XOUT XIN 0.1uF C20 3 3 3 3 3 3 3 3 C21 0.1uF +3.3V Data_0 Data_1 Data_2 Data_3 Data_4 Data_5 Data_6 Data_7 5 0.1uF C26 2 RTSn 2 CTSn XP2_SW7 XP2_SW6 XP2_SW5 XP2_SW4 XP2_SW3 XP2_SW2 XP2_SW1 XP2_SW0 STATUS_LED[0:7] 5 XP2_SPI_CS0 XP2_SPI_CLK XP2_SPI_IN 3 XP2_SPI_OUT 3 FLASH_RSTn 3 FLASH_Wn 3 RESET 3 3 3 5 BANK 7 C27 0.1uF +3.3V 42 49 41 51 37 38 39 40 43 44 45 46 47 48 50 52 53 54 55 56 57 58 LFXP2-5E-6TN144C VCCIO6 VCCIO7 GNDIO6 GNDIO7 PB8A PB7A PB8B PB7B PB13B PB13A PB15A PB14A PB15B PB14B PB16A PB16B PB17A PB17B PB18A PB19A PB18B PB19B BANK 5 U6-4 LFXP2-5E-6TN144C VCCIO9 VCCIO10 GNDIO9 GNDIO10 PL2A PL2B PL5A PL5B PL6A PL6B PL7A PL7B PL8A PL8B PL9A PL10A PL9B PL10B PL11A PL11B PL12A PL12B STATUS_LED0 STATUS_LED1 STATUS_LED2 STATUS_LED3 STATUS_LED4 STATUS_LED5 STATUS_LED6 STATUS_LED7 14 4 12 3 1 2 5 6 7 8 9 10 11 13 15 16 17 18 19 20 21 22 U6-5 VCCIO11 GNDIO11 PL15A PL14A PL15B PL14B PL16B PL16A PL25A PL25B BANK 6 VCCIO8 GNDIO8 63 64 61 62 65 66 69 70 71 72 4 2 2 2 0.01uF C28 +3.3V +3.3V EXP_IO32 EXP_IO33 EXP_IO34 EXP_IO35 EXP_IO27 EXP_IO28 EXP_IO29 EXP_IO30 EXP_IO31 DTRn DSRn DCDn 0.01uF C22 +3.3V EXP_IO32 EXP_IO33 EXP_IO34 EXP_IO35 EXP_IO36 EXP_IO37 EXP_IO38 EXP_IO39 PB20A PB20B PB26A PB26B PB27A PB28A PB27B PB28B BANK 4 33 34 27 28 29 30 31 32 35 36 4 2 4 6 8 10 1 3 5 7 9 C29 0.01uF 2 RS232_Tx_TTL 2 RS232_Rx_TTL 0.01uF C25 +3.3V 3 112 111 109 110 113 114 115 116 LFXP2-5E-6TN144C VCCIO3 GNDIO3 PR24A PR24B PR14B PR14A BANK 3 U6-3 EXP_IO23 EXP_IO24 EXP_IO25 EXP_IO26 76 75 73 74 77 78 +3.3V EXP_IO36 EXP_IO37 EXP_IO38 EXP_IO39 EXP_IO[32:39] EXP_IO19 EXP_IO20 EXP_IO21 EXP_IO22 header 2x5 J2 3 LFXP2-5E-6TN144C VCCIO0 GNDIO0 PT28B PT28A PT21B PT20B PT21A PT20A BANK 1 U6-2 VCCIO4 VCCIO5 GNDIO4 GNDIO5 PR12B PR12A PR11B PR11A PR10B PR9B PR10A PR9A PR8B PR8A PR7B PR6B PR7A PR6A PR5B PR5A PR2B PR2A BANK 2 VCCIO1 VCCIO2 GNDIO1 GNDIO2 PT19B PT19A PT18B PT17B PT18A PT17A PT16B PT16A PT15B PT14B PT15A PT14A PT13B PT13A PT9B PT9A PT7B PT8B PT7A PT8A BANK 0 95 105 97 106 87 88 89 90 91 92 93 94 96 98 99 100 101 102 103 104 107 108 128 136 126 135 119 120 121 122 123 124 125 127 129 130 131 132 133 134 137 138 141 142 143 144 2 0.1uF C30 3 3 3 +3.3V 0.1uF Date: Size B Title Addr_[0:16] C31 +3.3V SRAM_CSb SRAM_OEb SRAM_WEb 0.1uF Addr_0 Addr_1 Addr_2 Addr_3 Addr_4 Addr_5 Addr_6 Addr_7 Addr_8 Addr_9 Addr_10 Addr_11 Addr_12 Addr_13 Addr_14 Addr_15 Addr_16 C24 EXP_IO16 0.1uF +3.3V EXP_IO21 EXP_IO20 EXP_IO19 EXP_IO18 EXP_IO17 EXP_IO26 EXP_IO25 EXP_IO24 EXP_IO23 EXP_IO22 C23 EXP_IO1 EXP_IO2 EXP_IO3 EXP_IO4 EXP_IO5 EXP_IO6 EXP_IO7 EXP_IO8 EXP_IO9 EXP_IO10 EXP_IO11 EXP_IO12 EXP_IO13 EXP_IO14 EXP_IO15 EXP_IO16 EXP_IO17 EXP_IO18 EXP_IO31 EXP_IO30 EXP_IO29 EXP_IO28 EXP_IO27 2 3 +3.3V AXELSYS Header2x20 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 EXP_IO[1:31] XP2_RESET XP2_RESET EXP_IO5 EXP_IO4 EXP_IO3 EXP_IO2 EXP_IO1 EXP_IO10 EXP_IO9 EXP_IO8 EXP_IO7 EXP_IO6 EXP_IO15 EXP_IO14 EXP_IO13 EXP_IO12 EXP_IO11 3 Thursday, December 09, 2010 LFXP2-5E-B2-EVN Document Number 1 Sheet 4 of 5 Rev A Lattice XP2 Brevia 2 Evaluation Board - FPGA Banks 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 J3 1 A B C D Lattice Semiconductor LatticeXP2 Brevia 2 Development Kit User’s Guide Figure 7. FPGA Banks 21 A B C J4 1K VCC DD+ ID GND 5 SKT_MINIUSB_B_RA D9 Green R35 Input 1 2 3 4 5 3 IN U8 Tab Output FAN1112 1 R37 C56 0.1uF 0 2 4 0.1uF C53 NCP1117 OUT TAB GND 4 2 600ohm 500mA L5 VBUS_5V 10uF C50 3 VBUS_5V 10uF C48 U7 GND 1 D 1 2 VBUS_5V 1 2 5 22uF C49 4 2 2 22uF DM DP L3 0.1uF C52 L4 +3.3V 1 2 600ohm 500mA +1.2V 2 1 600ohm 500mA C51 4 0.1uF C34 X2 Output Vcc 3 4 CB3LV-3C-50M0000 GND EN 3 4 LFXP2-5E-6TN144C 50MHz OSC 2 1 0.1uF C36 +3.3V LRC_VCCPLL1 LRC_GNDPLL2 ULC_VCCPLL3 ULC_GNDPLL4 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCC1 VCC2 VCC3 VCC4 U6-1 0.1uF C35 XIN 67 68 140 139 23 60 85 117 24 59 84 118 This is optional R36 to enable or disable the 0 crystal. +3.3V 1uF 10uF +1.2V C33 C32 3 +1.2V 0.1uF C55 TOE CFG0 GND 0.1uF C37 XOUT 25 26 86 0.01uF C38 4 10k R33 2 +3.3V 10k DNI R34 10uF C39 2 C54 +3.3V 0.1uF C43 82 80 79 81 83 JTAG 0.01uF C45 LFXP2-5E-6TN144C TDO TDI TMS TCK VCCJ JTAG U6-6 0.1uF C44 1 0.01uF C46 0.01uF C47 Thursday, December 09, 2010 LFXP2-5E-B2-EVN Document Number 1 Sheet 5 of 5 Rev A Lattice XP2 Brevia 2 Evaluation Board - Power / JTAG AXELSYS 0.1uF C42 0.01uF Date: Size B Title TDO TDI TMS TCK 0.1uF 1uF 2 2 2 2 C41 C40 +3.3V A B C D Lattice Semiconductor LatticeXP2 Brevia 2 Development Kit User’s Guide Figure 8. Power/JTAG LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor Appendix B. Bill of Materials Table 8. Bill of Materials Reference Description Quantity 1 2 C1,C3 2 33 C2, C4, C5, C6, C7, C8, C9, C11, C12, C15, C16, C17, C18, C20, C21, C23, CAP CERAMIC 0.1UF 16V X7R C24, C26, C27, C30, C31, Kemet 0402 C34, C35, C36, C37, C41, C42, C43, C44, C52, C53, C55, C56 3 5 C10, C32, C39, C48, C50 CAP CECAP CER 10UF 10V X5R 20% 0603 4 2 C13, C14 CAP CER 18PF 25V C0G 0402 Kemet 5 10 C19, C22, C25, C28, C29, CAP CERAMIC 10nF 16V 5% C38, C45, C46, C47, C54 X7R 0402 Kemet C0402C103J4RACTU 6 2 C33, C40 CAP CERAMIC 1uF 6.3V X5R 0402 Kemet C0402C105K9PACTU 7 2 C49, C51 CAP CERAMIC 22uF 10V X5R 0805 Taiyo Yuden LMK212BJ226MG-T 8 8 D1, D2, D3, D4, D5, D6, D7, D8 LED SUPER RED CLEAR 0603 LITE-On INC SMD LTST-C190KRKT 9 1 D9 LED SUPER GREEN CLEAR 0603 SMD LITE-On INC LTST-C190KGKT 11 1 J2 CONN HEADER 10POS .100" SMT Align TIN Samtec TSM-105-01-T-DV-A 12 1 J3 Header 2x10 .100 20POS Align Samtec VER TSM-120-01-T-DV-A-P 13 1 J4 CONN MINI USB RCPT RA TYPE B SMD 5075BMR-05-SM-CR 14 5 L1, L2, L3, L4, L5 Ferrite Bead 600ohm@100MHz Murata 500mA 0603 BLM18AG601SN1D 16 2 R4, R9 Res 1/16W 5.1K 1% 0402 Yageo RC0402FR-075K1L 17 7 R5, R6, R7, R8, R32, R36, R37 Res 1/10W 0.0 Ohm 5% 0603 Yageo RC0603JR-070RL 18 1 R10 Res 1/16W 12.0K 1% 0402 Yageo RC0402FR-0712KL 19 5 R11, R12, R13, R31, R33 Res 1/16W 10.0K 1% 0402 Yageo RC0402FR-0710KL 20 9 R14, R23, R24, R25, R26, Res 1/16W 2.2K 1% 0402 R27, R28, R29, R30 Yageo RC0402FR-072K2L 21 8 R15, R16, R17, R18, R19, Res 1/16W 470R 1% 0402 R20, R21, R22 Yageo RC0402FR-07470RL 23 1 R35 Res 1/16W 1.0K 1% 0402 Yageo RC0402FR-071KL 24 1 SW1 SWITCH DIP SPST SEALED 4POS SMD C&K Components SD04H1SB 25 5 SW2, SW3, SW4, SW5, SW6 SWITCH TACT 6MM MOM SMD C&K Components PTS645SH50SMTRLFS H=5.0MM 26 1 U1 USB to UART / FIFO FTDI FT2232HL 27 1 U2 IC 93LC56 EEPROM Microchip 93LC56C-I/SN 28 1 U3 SPI Flash 256Kx8 20Mhz SST / Microchip SST25VF020-20-4C-SAE 29 1 U4 SRAM 128Kx8, 15ns IDT IDT71V124SA15TYG8 30 1 U5 CMOS Switch Debouncer Octal Maxim Cap Cer 4.7uF 6.3V 10% X5R 0603 22 Manufacturer Manufacturer Part Number Item Panasonic Taiyo Yuden Neltron ECJ-1VB0J475K C0402C104K4RACTU LMK107BJ106MALTD C0402C180K3GACTU MAX6818EAP+ LatticeXP2 Brevia 2 Development Kit User’s Guide Lattice Semiconductor Table 8. Bill of Materials (Continued) Reference Description Quantity 31 1 U6 FPGA XP2 Lattice LFXP2-5E-6TN144C 32 1 U7 IC REG LDO 1A 1.2V SOT-223 Fairchild Semi FAN1112SX 33 1 U8 IC Reg LDO 3.3V SOT-223 On Semi NCP1117ST33T3G 34 1 X1 12Mhz Crystal TXC 7M-12.000MAAJ-T 35 1 X2 OSC 50MHz 3.3V 50ppm CTS CB3LV-3C-50M0000 23 Manufacturer Manufacturer Part Number Item