AN-784 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/461-3113 • www.analog.com 10-Bit Interface Board for High Performance Display Interface Evaluation Boards by Del Jones INTRODUCTION The purpose of the 10-bit display interface board (DIB) is to aid in the evaluation of the AD9981 or AD9980. It is designed to be used in conjunction with the evaluation boards for these parts, and is included as part of the evaluation board kits. It is a conduit for displaying images on any flat panel monitor, CRT, LCD (or DLP) projector, or TFT panel (with LVDS interface). • An evaluation board for the AD9981 or AD9980 • A 5 V dc power supply • A Centronix printer cable or USB A to B cable for serial bus programming REQUIREMENTS In addition to the items included with the kit, the following items are needed to run this board: • A computer with the evaluation software installed • A 5 V dc power supply • Any flat panel monitor, CRT, or projector 10-bit display interface board 05441-001 LIMITATIONS The evaluation system using the 10-bit DIB is intended to provide the user a platform with which to evaluate the functionality and, to a limited extent, performance of the AD9981 or AD9980. When evaluating the 8-bit AD9980, the DVI or LVDS outputs of the 10-bit DIB offer the highest quality image for performance evaluation. However, since both of these ports only offer 8-bit accuracy, they cannot truly reflect the enhanced performance provided by the 10-bit ADCs of the AD9981. The analog output of the 10-bit DIB uses high accuracy 12-bit DACs and can potentially offer a preferred interface for evaluation, depending on the display device that is used. PACKAGE CONTENTS Figure 1. Board Shown in Centimeters REV. 0 AN-784 EVALUATION BOARD HARDWARE DE GENERATION The DVI and LVDS interfaces require a data enable (DE) signal which indicates when there is active image data. Since the analog graphics signal does not contain DE, the FPGA on the 10-bit display interface board is required to generate it. The duration of DE is programmable via the 10-bit DIB register map of the display electronics (DEPL) evaluation software and supports any display resolution up to 4096 pixels 4096 pixels. POWER This board is designed to receive 5 V dc through connector J4. The power supply that is included in the kit plugs into this connector. BOARD FUNCTIONS A block diagram of the 10-bit display interface board is shown in Figure 2. The following sections briefly describe these functional blocks. COLOR SPACE CONVERSION The FPGA contains circuitry to perform color space conversion for 30-bit YPbPr data. This can be enabled via the 10-bit DIB register map of the DEPL evaluation software. This can be used in conjunction with the midscale clamp feature on the analog interface of the AD998x devices to provide the proper colors for an YPbPr video signal. The color space conversion also works with YPbPr signals transmitted over the DVI interface. For the most accurate color space conversion, the conversion results in a 12-bit output for each of the digital RGB output channels. This minimizes the rounding errors that can result from the conversion process. DATA DEMULTIPLEXING The Altera EP1C6QC240 FPGA (U6) performs most of the logic functions on the 10-bit display interface board. Among these functions is the demultiplexing of the digital RGB data output from the AD998x when it is in single-port data output (30-bit) mode (the AD9981 and AD9980 are 30-bit only). The DVI and LVDS transmitters, as well as the digital-to-analog converters (DACs), require dual-port digital RGB data. Therefore, demultiplexing is required when in single-port mode. TO TFT PANEL LVDS XMIT WITH CONNECTOR 10 12 8 BLU B 10 8 RED A 10 12 FPGA 12 [DATA DEMUX (SINGLE PORT MODE), 12 DE GENERATION, DE CONTROL, COLOR CONVERSION] 12 RED B 10 12 8 GRN B 10 8 8 8 8 8 8 8 TMDS XMIT 8 TO FLAT PANEL MONITOR OR LCD PROJECTOR TO CRT OR FLAT PANEL MONITOR 12 SYNCS 12 DAC SERIAL INTERFACE B 12 12 DAC G 12 R 05441-002 12 DAC PARALLEL INTFC CONN DVI CONNECTOR BLU A GRN A 10 DIGITAL RGB AND SYNCS FROM AD988x 8 VGA CONN POWER USB INTFC Figure 2. 10-Bit Display Interface Board Block Diagram –2– REV. 0 AN-784 cable to any display device (flat panel monitor, CRT, or projector) to display any image from VGA to UXGA-75. DVI OUTPUT The 10-bit display interface board provides a DVI output via SiI160 transmitter (U15) and DVI-I connector (J8). This can be connected via DVI cable to any display device (flat panel monitor or LCD projector) to display any image from VGA to UXGA-60 (the SiI160 is limited to 25 MHz to 165 MHz operation). Note that the SiI160 is capable of processing only 8-bit data. Therefore, only the 8 MSBs of the data output from the FPGA are used for the DVI output. SERIAL BUS TO COMPUTER INTERFACE (USB OR PRINTER PORT) Some circuitry is needed in order to interface the AD998x and the 10-bit display interface board’s serial register interface with a computer. The 10-bit display interface board provides both a USB and a parallel (printer) port interface. The USB interface consists of a USB-B connector (J2), USB controller (U14), and an EEPROM (U16) that contains board ID information. The circuitry for the printer port’s serial interface use U1 and U9, in addition to the Centronix connector, J1. LVDS OUTPUT The 10-bit display interface board provides an LVDS output via DS90C387 transmitter (U5) and LVDS data connector (J9). This can be connected via user-provided cable to any board flat panel with LVDS interface (such as Samsung’s 21.3’’ UXGA panel, LTM213U3-L01-0, or Sharp’s 18’’ SXGA panel, LQ181E1LW31) to display an image using that panel’s native resolution. This interface is capable of operating up to UXGA-75 (202.5 MHz). Note that the DS90C387 is capable of processing only 8-bit data. Therefore, only the 8 MSBs of the data output from the FPGA are used for the DVI output. POWER The 10-bit display interface board has two voltage regulators that generate 1.5 V and 3.3 V for its own logic. These voltages are regulated off of the 5 V input at J4. The 5 V input is also routed to the AD998x evaluation board interface connector (J3) to provide power for the AD998x evaluation board. EVALUATION BOARD CONNECTIONS Figure 3 shows how the 10-bit display interface board interfaces with the AD9981 evaluation board. It also indicates the various connections needed to evaluate an image. ANALOG OUTPUT The 10-bit display interface board provides an analog output via high performance AD9753 DACs (U11 to U13) and 15-pin VGA connector (J6). The AD9753 is a 12-bit DAC that provides precision digital-to-analog conversion. Therefore, the analog output port is the best choice to demonstrate the full 10-bit performance of the AD998x devices. The analog output can be connected via VGA PARALLEL INTERFACE USB INTERFACE LVDS OUTPUT ANALOG INPUTS FOR AD9981 5V INPUT ANALOG OUTPUT Figure 3. 10-Bit Display Interface Board with AD9981 Evaluation Board REV. 0 –3– 05441-004 DVI OUTPUT AN-784 CONFIGURING THE BOARD To USB Driver Installation Follow these steps to install the USB drivers on your PC: 1. Connect the board to the power supply. 2. Connect the USB cable from the PC to the board. 3. Windows sees the new device and asks to install drivers for it. 4. Select Search for Drivers and click Next. 5. Specify a location and browse on the CD-ROM to the USB Drivers\win2k directory. 6. Click Next and follow any remaining instructions. 7. If asked for any files, always browse to the same USB Drivers\win2k (or \win98) folder to find them. DE Generation The VS_SEL (W15 on schematic) and HS_SEL (W16 on schematic) jumpers allow you to choose raw VSYNC and HSYNC or the VSOUT and HSOUT outputs of the AD998x to generate DE. If the jumpers are placed between Pins 1 and 2 (closer to U2), the raw HSYNC and VSYNC are selected. If the jumpers are placed between Pins 2 and 3, the sync outputs (HSOUT and VSOUT) of the AD998x are selected. Either configuration works, although the HSYNC and VSYNC delay values used for DE generation vary slightly in each case. PC Port Selection The jumpers at W1 and W2 must be configured appropriately to use the desired PC port for software control. To select USB, the jumpers must be placed between Pins 2 and 3. To select the printer port, the jumpers should be placed between Pin 1 and Pin 2. DCLK Selection The 10-bit display interface board is configured so that the DCLK output of the AD998x drives the generation of PANEL_DCLK and PANEL_DE. This is accomplished through the placement of a jumper between Pins 1 and 2 of Header W3. –4– REV. 0 AN-784 EVALUATION BOARD SOFTWARE program located in the Program Files\Analog Devices\ DEPL Evaluation Software\DriverX directory. The 10-bit display interface board (DIB) registers can be controlled using the 10-bit DIB register map of the DEPL evaluation software. This software is a Visual Basic® program requiring a Windows® 95, or later, operating system. It is on a self-installing CD package included with the evaluation board (in the \DEPL Evaluation Software subdirectory). The 10-bit DIB register map of the DEPL evaluation software should be loaded into the \Program Files\ADI Software directory upon completion of a successful installation. The 10-bit DIB register map can be accessed two ways. From the menu bar, select Device > 10Bit DIB. The 10-bit DIB register map can also be accessed by selection Tools > 10-Bit Display Interface Board Configuration. The 10-bit DIB register map is shown in Figure 4. Using this screen, the user can control the features of the 10-bit DIB. To implement the controls, click Load. This is true unless the Load Register on Change box is checked or the Read button is clicked. In this case, the registers are updated as soon as any change is made in the window. 05441-003 Note: If a DriverX Install error is encountered during the software installation, rerun the driverxinstall.exe Figure 4. Display Interface Board Configuration Setup Window REV. 0 –5– AN-784 DE Select (07–7) This bit allows you to select the source for data enable generation. If the analog interface of the AD998x is being used, Generated DE must be selected since the analog interface does not include a DE signal. If the DVI interface of the AD998x is being used, either Generated DE of Digital DE can be used. However, it is recommended that the Digital DE be selected in this case. 10-BIT DIB REGISTER DESCRIPTIONS Hsync Delay (01–7:0) Register 01 controls the number of data clock cycles that occur between Hsync and the beginning of DE. This is a decimal number that is written to an 8-bit register. For ease of use, a sliding bar is also included as an alternative method for controlling the Hsync delay. Moving the bar to the right increases the delay and is reflected in the box to the right. Moving the bar left decreases the delay. If using the DVI output of the 10-bit display interface board, note that an image might not be visible until the Hsync Delay is near the appropriate amount of delay from Hsync to active video. Port Mode (07–6) This bit allows the user to select the operating mode of the AD998x. If the AD998x is operating in single-channel (30-bit) output mode (the AD9981 and the AD9980 have single-channel output only), single port mode must be selected. If the AD998x is operating in dual-channel (60bit) output mode, Dual Port (60 bit) must be selected. Vsync Delay (02–7:2) Bits 7:2 of Register 02 control the number of Hsync periods that occur between Vsync and the beginning of DE. This is a decimal number that is written to a 6-bit register. A sliding bar is also included for Vsync delay control. DAC Frequency (07–5:4) From the DAC Frequency Range menu, you can select the operating range of the analog output. The 12 MHz to 100 MHz range should be adequate to display all resolutions XGA and above (including 720p and 1080p). For lower speed resolutions, the appropriate range should be selected. LVDS/DVI Interface Enable (02–1:0) Bits 1:0 of Register 02 serve as enable bits to turn on the LVDS and DVI interface outputs of the 10-bit DIB. It is recommended that these interfaces be powered down when not in use. Color Conversion Enable (07–3) The color conversion enable bit allows you to turn on the 30-bit color space converter in the FPGA. Horizontal Resolution (03–7:04–4) Horizontal resolution must be set using the 12 bits spanning Register 3, Bit 7 (MSB) to Register 4, Bit 4 (LSB). The resolution is set in number of pixels by typing the decimal number directly into the text box on the right or by moving the scroll bar next to it. The maximum value is 4096. Half Clock Invert (07–2) The bit allows the user to route the first pixel of demultiplexed 30-bit data to the even output port of the FPGA rather than the odd output port. The timing relation between data and the data clock (PANEL_CLK_OUT) remain the same. This bit is useful when centering the image using the Hsync delay register. Vertical Resolution (05–7:06–4) Vertical resolution must be set using the 12 bits spanning Register 5, Bit 7 (MSB) to Register 6, Bit 4 (LSB). The resolution is set in number of lines by typing the decimal number directly into the text box on the right or by moving the scroll bar next to it. The maximum value is 4096. PC Port Selection To select between the USB and parallel ports for the software interface click on the Options pull-down menu and click on Device Interface and then select either USB or Parallel. Refer to the PC Port Selection section for further setup instructions. DE Settings for Interlaced Video (06–3:0) When generating a data enable (DE) from an interlaced video source, it is necessary to provide for an offset between the odd and even fields. Bits 3:1 of Register 6 allow you to program the amount of offset (in number of lines) between the two fields. Bit 0 allows you to select how the even and odd fields are differentiated from each other. The AD998x devices have an ODD_EVEN~ signal that is routed to the 10-bit DIB’s FPGA and can be used to determine the differentiation by setting this bit to a Logic 1. If using a device that does not provide this signal, the FPGA generates its own signal to provide this function. This signal can be selected by setting Bit 0 to Logic 0. –6– REV. 0 05441-005 TP34 TP33 TP48 TP49 TP32 NC 2 ALT_DATA 4 3 1 J7 VCC2 VCC3 10 8 6 4 2 ASDI DCLK EPCS1 U2 GND VCC1 DATA NCS 9 7 5 3 1 10k� R54 REDA_IN0 REDA_IN1 REDA_IN2 REDA_IN3 REDA_IN4 REDA_IN5 REDA_IN6 REDA_IN7 REDA_IN8 REDA_IN9 GRNA_IN0 GRNA_IN1 GRNA_IN2 GRNA_IN3 GRNA_IN4 GRNA_IN5 GRNA_IN6 GRNA_IN7 GRNA_IN8 GRNA_IN9 BLUA_IN0 BLUA_IN1 BLUA_IN2 BLUA_IN3 BLUA_IN4 BLUA_IN5 BLUA_IN6 BLUA_IN7 BLUA_IN8 BLUA_IN9 3.3V R56 10k� ALT_CSO ALT_NCE 3.3V ADD THIS TEXT TO SILKSCREEN 5 ALT_ASDO VSYNC TP47 RAW VSOUT RAW BLUB_IN0 BLUB_IN1 BLUB_IN2 BLUB_IN3 BLUB_IN4 BLUB_IN5 BLUB_IN6 BLUB_IN7 3.3V W15 VSYNC_IN HSYNC_IN REDA_IN0 REDA_IN1 REDA_IN2 REDA_IN3 REDA_IN4 REDA_IN5 REDA_IN6 REDA_IN7 GRNB_IN0 GRNB_IN1 GRNB_IN2 GRNB_IN3 GRNB_IN4 GRNB_IN5 GRNB_IN6 GRNB_IN7 GRNB_IN8 GRNB_IN9 3.3V ALT_DCLK ALT_ASDO SDA SPARE23 ALT_NCE DCLK_IN SCL BLUB_IN8 BLUB_IN9 GRNA_IN0 GRNA_IN1 GRNA_IN2 GRNA_IN3 GRNA_IN4 GRNA_IN5 GRNA_IN6 GRNA_IN7 GRNA_IN8 3.3V GRNA_IN9 ALT_CSO ALT_DATA ALT_NCONFIG W16 1 W3 DCLK DCLK HSOUT HS_SEL VSOUT HSYNC HSOUT 1 DCLK TP30 SOGOUT 1 TP28 HSOUT TP27 1 VSOUT 1 TP29 ODD_EVEN~ TP31 NC 1 DIG_DE TP6 CTL0 1 CTL2 NC 6 ALT_DCLK 7 8 10k� R55 MOLEX_52760-100 J3 ALT_CSO 3.3V ALT_ASDO ALT_DATA ALT_NCONFIG ALT_CFG_DN ALT_DCLK DCLK 1 CLK_INV 1 HSYNC 1 VSYNC 1 PWR_DN 1 NC NC CTL1 CTL3 REDB_IN0 REDB_IN1 REDB_IN2 REDB_IN3 REDB_IN4 REDB_IN5 REDB_IN6 REDB_IN7 REDB_IN8 REDB_IN9 GRNB_IN0 GRNB_IN1 GRNB_IN2 GRNB_IN3 GRNB_IN4 GRNB_IN5 GRNB_IN6 GRNB_IN7 GRNB_IN8 GRNB_IN9 BLUB_IN0 BLUB_IN1 BLUB_IN2 BLUB_IN3 BLUB_IN4 BLUB_IN5 BLUB_IN6 BLUB_IN7 BLUB_IN8 BLUB_IN9 1 SCL SDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 U6 3.3V BLUB_IN0 BLUB_IN1 BLUB_IN2 BLUB_IN3 BLUB_IN4 BLUB_IN5 BLUB_IN6 BLUB_IN7 VCCIO1 GND1 BLUB_IN8 BLUB_IN9 GRNA_IN0 GRNA_IN1 GRNA_IN2 GRNA_IN3 GRNA_IN4 GRNA_IN5 GRNA_IN6 GRNA_IN7 GRNA_IN8 VCCIO2 GRNA_IN9 NCSO DATA0 NCONFIG VCCPLL1 DCLK_IN_CLK0 SCL_CLK1 GNDA_PLL1 GNDB_PLL1 NCEO NCE MSEL0 MSEL1 DCLK ASDO SDA SPARE_IO1 GND2 GRNB_IN0 GRNB_IN1 GRNB_IN2 GRNB_IN3 GRNB_IN4 GRNB_IN5 GRNB_IN6 GRNB_IN7 GRNB_IN8 GRNB_IN9 VCCIO3 GND3 REDA_IN0 REDA_IN1 REDA_IN2 REDA_IN3 REDA_IN4 REDA_IN5 REDA_IN6 REDA_IN7 3.3V NC RST BLUA_IN9 BLUA_IN8 BLUA_IN7 BLUA_IN6 BLUA_IN5 BLUA_IN4 BLUA_IN3 REDA_IN8 REDA_IN9 REDB_IN0 REDB_IN1 REDB_IN2 REDB_IN3 REDB_IN4 REDB_IN5 NC 3.3V D1 SMT_LED TP38 COAST CLAMP 1 TP37 1 1 TP35 1 1 TP45 1 TP44 1 TP42 TP43 TP46 ADD THIS TEXT TO SILKSCREEN: "DE ON" PEV 1.5V 1 TP25 1 TP16 1 TP15 1 TP17 1 TP26 TP22 TP24 TP23 10BIT_DIB_FPGA EP1C6QC240 U6 1.5V TP36 R57 1k� 1 1.5V BLUA_IN2 BLUA_IN1 BLUA_IN0 SPARE22 SPARE21 SPARE20 SPARE19 SPARE18 1 TP41 TP40 1 RST PANEL_EN SPARE17 SPARE16 DE_DETECT1 DE_DETECT2 LATCH_DE 1 1 1 3.3V SPARE15 SPARE14 SPARE13 SPARE12 SPARE11 SPARE10 SPARE9 SPARE8 1 1 1 1 TP8 1 TP3 1 TP1 1 TP4 TP20 TP19 TP5 SPARE7 SPARE6 SPARE5 SPARE4 REGEN_VS REGEN_HS DE_OUT TP39 1 SPARE3 5V LATCH_DE 1.5V REDB_IN6 REDB_IN7 REDB_IN8 REDB_IN9 HSYNC_IN VSYNC_IN DIG_DE ODD_EVEN~ DAC_DIV1 DAC_DIV0 SPARE1 SPARE2 RED_ODD0 RED_ODD1 RED_ODD2 RED_ODD3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 1.5V 1.5V –7– 3.3V RED_ODD4 RED_ODD5 RED_ODD6 RED_ODD7 RED_ODD8 RED_ODD9 RED_ODD10 RED_ODD11 RED_EVEN0 RED_EVEN1 RED_EVEN2 RED_EVEN3 RED_EVEN4 RED_EVEN5 RED_EVEN6 RED_EVEN7 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 3.3V 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 BLU_EVEN5 BLU_EVEN4 BLU_EVEN3 BLU_EVEN2 BLU_EVEN1 BLU_EVEN0 PNL_CLK_LVDS BLU_ODD11 VCCIO9 GND12 BLU_ODD10 BLU_ODD9 BLU_ODD8 BLU_ODD7 BLU_ODD6 BLU_ODD5 BLU_ODD4 BLU_ODD3 BLU_ODD2 BLU_ODD1 BLU_ODD0 PNL_CLK_DVI DVI_EN VCCIO8 PNL_CLK_OUT TDI VCCA_PLL2 PNL_CLK_IN_CLK2 SPARE_CLK3 GNDA_PLL2 GNDG_PLL2 TDO TMS TCK NSTATUS CONF_DONE GRN_EVEN11 GRN_EVEN10 GND11 GRN_EVEN9 GRN_EVEN8 GRN_EVEN7 GRN_EVEN6 GRN_EVEN5 GRN_EVEN4 GRN_EVEN3 GRN_EVEN2 GRN_EVEN1 GRN_EVEN0 GRN_ODD11 VCCIO7 GND10 GRN_ODD10 GRN_ODD9 GRN_ODD8 GRN_ODD7 GRN_ODD6 GRN_ODD5 GRN_ODD4 PNL_CLK_ALG DEV_CLRN BLUA_IN9 BLUA_IN8 BLUA_IN7 BLUA_IN6 BLUA_IN5 BLUA_IN4 BLUA_IN3 GND18 VCCIO12 GND17 VCCINT6 BLUA_IN2 BLUA_IN1 BLUA_IN0 SPARE_IO24 SPARE_IO23 SPARE_IO22 SPARE_IO21 SPARE_IO20 RST PANEL_EN SPARE_IO19 SPARE_IO18 DE_DETECT1 DE_DETECT2 LATCH_DE LATCH_DE GND16 VCCINT5 GND15 VCCIO11 SPARE_IO17 SPARE_IO16 SPARE_IO15 SPARE_IO14 SPARE_IO13 SPARE_IO12 SPARE_IO11 SPARE_IO10 SPARE_IO9 SPARE_IO8 SPARE_IO7 SPARE_IO6 SPARE_IO5 REGEN_VS REGEN_HS DE_OUT GND14 VCCINT4 GND13 VCCIO10 SPARE_IO4 LVDS_EN BLU_EVEN11 BLU_EVEN10 BLU_EVEN9 BLU_EVEN8 BLU_EVEN7 BLU_EVEN6 REDA_IN8 REDA_IN9 REDB_IN0 REDB_IN1 REDB_IN2 REDB_IN3 REDB_IN4 REDB_IN5 GND4 VCCIO4 GND5 VCCINT1 REDB_IN6 REDB_IN7 REDB_IN8 REDB_IN9 HSYNC_IN VSYNC_IN DIG_DE ODD_EVEN~ DAC_DIV1 DAC_DIV0 SPARE_IO2 SPARE_IO3 RED_ODD0 RED_ODD1 RED_ODD2 RED_ODD3 GND6 VCCINT2 GND7 VCCIO5 RED_ODD4 RED_ODD5 RED_ODD6 RED_ODD7 RED_ODD8 RED_ODD9 RED_ODD10 RED_ODD11 RED_EVEN0 RED_EVEN1 RED_EVEN2 RED_EVEN3 RED_EVEN4 RED_EVEN5 RED_EVEN6 RED_EVEN7 GND8 VCCINT3 GND9 VCCIO6 RED_EVEN8 RED_EVEN9 RED_EVEN10 RED_EVEN11 GRN_ODD0 GRN_ODD1 GRN_ODD2 GRN_ODD3 REV. 0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Figure 5. 3.3V RED_EVEN8 RED_EVEN9 RED_EVEN10 RED_EVEN11 GRN_ODD0 GRN_ODD1 GRN_ODD2 GRN_ODD3 ADD NET NAMES FOR ALL TPs (EXCEPT SPARES) TO SILKSCREEN 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 TP7 1 R58 10k� TP18 3.3V PANEL_CLK_IN R6 PNL_CLK_ALG 0� GRN_ODD10 GRN_ODD9 GRN_ODD8 GRN_ODD7 GRN_ODD6 GRN_ODD5 GRN_ODD4 CLK_ALG GRN_EVEN9 GRN_EVEN8 GRN_EVEN7 GRN_EVEN6 GRN_EVEN5 GRN_EVEN4 GRN_EVEN3 GRN_EVEN2 GRN_EVEN1 GRN_EVEN0 GRN_ODD11 3.3V ALT_STATUS ALT_CFG_DN GRN_EVEN11 GRN_EVEN10 SPARE_CLK PNL_CLK_DVI R13 0� PANEL_CLK_OUT BLU_ODD10 BLU_ODD9 BLU_ODD8 BLU_ODD7 BLU_ODD6 BLU_ODD5 BLU_ODD4 BLU_ODD3 BLU_ODD2 BLU_ODD1 BLU_ODD0 CLK_DVI DVI_EN 3.3V TP2 BLU_EVEN5 BLU_EVEN4 BLU_EVEN3 BLU_EVEN2 BLU_EVEN1 BLU_EVEN0 PNL_CLK_LVDS BLU_ODD11 3.3V LVDS_EN BLU_EVEN11 BLU_EVEN10 BLU_EVEN9 BLU_EVEN8 BLU_EVEN7 BLU_EVEN6 AN-784 SCHEMATICS AND LAYOUT The schematics and layout for this board can also be found on the CD. VS_SEL –8– 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 GRN_EVEN11 GRN_EVEN10 GRN_EVEN9 GRN_EVEN8 GRN_EVEN7 GRN_EVEN6 GRN_EVEN5 GRN_EVEN4 GRN_ODD7 GRN_ODD6 GRN_ODD5 GRN_ODD4 GRN_ODD3 GRN_ODD2 GRN_ODD1 GRN_ODD0 RED_EVEN3 RED_EVEN2 RED_EVEN1 RED_EVEN0 RED_ODD11 RED_ODD10 RED_ODD9 RED_ODD8 05441-006 1 2 3 4 5 6 7 8 22 16 15 14 13 12 11 10 9 RED_B3 RED_B2 RED_B1 RED_B0 RED_A11 RED_A10 RED_A9 RED_A8 RED_ODD7 RED_ODD6 RED_ODD5 RED_ODD4 RED_ODD3 RED_ODD2 RED_ODD1 RED_ODD0 1 2 3 4 5 6 7 8 22 RA10 RA9 1 2 3 4 5 6 7 8 22 RED_EVEN11 RED_EVEN10 RED_EVEN9 RED_EVEN8 RED_EVEN7 RED_EVEN6 RED_EVEN5 RED_EVEN4 22 GRN_A7 GRN_A6 GRN_A5 GRN_A4 GRN_A3 GRN_A2 GRN_A1 GRN_A0 RA8 16 15 14 13 12 11 10 9 RA7 1 2 3 4 5 6 7 8 22 GRN_EVEN3 GRN_EVEN2 GRN_EVEN1 GRN_EVEN0 GRN_ODD11 GRN_ODD10 GRN_ODD9 GRN_ODD8 22 GRN_B11 GRN_B10 GRN_B9 GRN_B8 GRN_B7 GRN_B6 GRN_B5 GRN_B4 RA6 16 15 14 13 12 11 10 9 RA5 1 2 3 4 5 6 7 8 22 BLU_ODD7 BLU_ODD6 BLU_ODD5 BLU_ODD4 BLU_ODD3 BLU_ODD2 BLU_ODD1 BLU_ODD0 22 BLU_B7 BLU_B6 BLU_B5 BLU_B4 BLU_B3 BLU_B2 BLU_B1 BLU_B0 RA4 16 15 14 13 12 11 10 9 BLU_ODD8 BLU_ODD9 RA2 BLU_B8 BLU_EVEN8 BLU_EVEN7 BLU_EVEN6 BLU_EVEN5 BLU_EVEN4 BLU_EVEN3 BLU_EVEN2 BLU_EVEN1 BLU_EVEN0 BLU_B9 BLU_EVEN9 BLU_ODD10 BLU_ODD11 RA3 22 BLU_B10 RA1 22 BLU_B11 BLU_EVEN10 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 RED_A7 RED_A6 RED_A5 RED_A4 RED_A3 RED_A2 RED_A1 RED_A0 RED_B11 RED_B10 RED_B9 RED_B8 RED_B7 RED_B6 RED_B5 RED_B4 GRN_B3 GRN_B2 GRN_B1 GRN_B0 GRN_A11 GRN_A10 GRN_A9 GRN_A8 BLU_A7 BLU_A6 BLU_A5 BLU_A4 BLU_A3 BLU_A2 BLU_A1 BLU_A0 BLU_A8 BLU_A9 BLU_A10 BLU_A11 H2 H3 PNL_CLK_LVDS PLACE NEAR U6:174 U10 OUT2 OUT4 OUT6 OUT10 OUT9 OUT8 10 OUT7 5 11 OUT5 4 12 OUT3 3 13 OUT1 OUT7 3.3V; 14 OUT8 6 9 OUT9 8 OUT10 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 3D7110 GND; 7 R14 0Ω R20 0Ω IN 11 PLACE U10 AS CLOSE AS POSSIBLE TO U6. KEEP THESE TRACES AS SHORT AS POSSIBLE. THE CLOCK DELAY CIRCUIT SHOWN HERE IS A STUFFING OPT. H1 PLACE MOUNTING HOLES IN EACH CORNER OF THE PCB. PANEL_CLK_LVDS1 BLU_EVEN11 OUT789 W22 OUT456 W25 OUT123 W24 H4 W23 PLACE NEAR W23 PNL_CLK_LVDS2 R22 0Ω PANEL_CLK_IN_DLY2 R15 22Ω PANEL_CLK_IN_DLY AN-784 Figure 6. REV. 0 05441-007 80 PNL_CLK_DVI AVDD DVI_EN R8 510Ω EDGE IDCK DE VSYNC HSYNC BE[7:0] GE[7:0] RE[7:0] BO[7:0] GO[7:0] RO[7:0] PIXS EXT_SWING R7 4.75kΩ 78 DE_OUT R3 4.75kΩ 77 REGEN_VS 3.3V 76 [9:16] [99:100], [1:6] [90:97] [68:75] [58:65] [48:55] REGEN_HS BLU_A[11:4] GRN_A[11:4] RED_A[11:4] BLU_B[11:4] GRN_B[11:4] RED_B[11:4] 3.3V 98 IVCC4 EDGE 24 AVDD SII160 U15 3.3V; 8, 30, 56, 88 GND; 7, 19, 31, 33,37, 41 GND; 47, 57, 67, 79, 86, 89 PIXS 25 CTL2 81 IVCC3 66 IVCC2 44 AVCC3 38 AVCC2 17 IVCC1 PD 26 EXT_SWING 32 CTL1 36 AVCC1 CTL3 82 –9– 84 Figure 7. 83 85 PVCC2 REV. 0 18 RES1 RES2 RES3 RES4 RES5 RES6 RES7 RES8 TXC– TXC+ TX0– TX0+ TX1– TX1+ TX2– TX2+ 20 21 22 23 27 28 29 87 34 3.3V DVI_TXC– DVI_TXC+ DVI_TX0– 35 DVI_TX0+ 39 DVI_TX1– 42 40 DVI_TX1+ DVI_TX2– DVI_TX2+ 43 45 46 DVI_PVCC PVCC1 23 24 18 17 10 9 2 1 7 6 25 8 26 27 28 GND; 3,11,15,19,22 DVI_AD (VIEW FROM BOTTOM) J8 RXC+ RXC– RX0+ RX0– RX1+ RX1– RX2+ RX2– DDCSDA DDCSCL HSYC VSYC RED GREN BLUE ROUTE THESE AS 50Ω DIFFERENTIAL PAIRS AN-784 05441-008 77 78 79 80 81 84 RED_B9 RED_B8 RED_B7 RED_B6 RED_B5 RED_B4 GRN_A4 GRN_A5 GRN_A6 100 GRN_A7 99 GRN_A8 96 GRN_A9 95 GRN_A10 94 GRN_A11 93 BLU_A4 92 BLU_A5 91 BLU_A6 90 BLU_A7 89 BLU_A8 88 BLU_A9 87 BLU_A10 86 BLU_A11 85 76 RED_B10 75 U5 DS90C387 G12 G13 G14 G15 G16 G17 B10 B11 B12 B13 B14 B15 B16 GND; 13, 16, 17, 19, 25, 35, 51, 52, 43, 68, 83, 98 3.3V; 53, 67, 82, 97 LVPLL_VCC; 12, 18 LVDS_VCC; 30, 40, 48 LVDS_EN PNL_CLK_LVDS2 27 R27 4.75kΩ R25 4.75kΩ R23 4.75kΩ R24 4.75kΩ R26 4.75kΩ 3.3V 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 FI-WE31P-HF J9 31 29 27 29 TXOUT7– 28 TXOUT7+ TXOUT7– 25 23 TXOUT6– 21 TXOUT5– 19 TXOUT4– 17 15 TXOUT3– 13 TXOUTCLK– 11 9 TXOUT2– 7 TXOUT1– 5 TXOUT0– 3 1 TXOUT7+ TXOUT6+ TXOUT5+ TXOUT4+ TXOUT3+ TXOUTCLK+ TXOUT2+ TXOUT1+ TXOUT0+ LVDS OUTPUT CONNECTOR 31 TXOUT6+ 32 TXOUT6– 33 TXOUT5+ 34 TXOUT5– 36 TXOUT4+ 37 TXOUT4– 38 TXOUT3+ 39 TXOUT3– 41 TXOUTCLK+ 42 TXOUTCLK– 44 TXOUT2+ 45 TXOUT2– 46 TXOUT1+ 47 TXOUT1– 49 TXOUT0+ 50 TXOUT0– CLK2P/NC 26 CLK2M/NC A7P A7M A6P A6M A5P A5M A4P A4M A3P A3M CLK1P B17 A2M R22 A2P A1P R23 CLK1M A1M R24 R20 AOP R25 R21 AOM R26 1 RED_B11 2 G10 3 RED_A11 R17 4 RED_A10 R16 5 RED_A9 R15 6 RED_A8 R14 7 RED_A7 R13 8 RED_A6 R12 9 RED_A5 R11 10 RED_A4 R10 11 CLKIN PRE 14 PRE 15 PLLSEL 20 R_FB R_FB 21 R_FDE R_FDE 22 PD DUAL DUAL 23 BAL 24 –10– BAL FROM FPGA GRN_B4 DE_OUT GRN_B5 74 G11 R27 GRN_B6 73 G20 GRN_B7 72 G21 GRN_B8 71 G22 GRN_B9 70 G23 GRN_B10 69 G24 GRN_B11 66 G25 BLU_B4 65 G26 BLU_B5 64 G27 BLU_B6 63 B20 62 B21 BLU_B7 61 B22 BLU_B8 60 B23 BLU_B9 59 B24 BLU_B10 58 B25 BLU_B11 57 B26 56 B27 55 DE REGEN_VS HSYNC 54 VSYNC REGEN_HS AN-784 Figure 8. REV. 0 R44 4.75kΩ R28 392Ω 1µF C8 R34 392Ω DAC_DIV0 DAC_DIV1 LPF RST [7:18] LPF GPLL_LOCK 42 GOUT– 43 6 R31 0.1µF 2kΩ C5 R35 0.1µF 2kΩ C6 40 GFSADJ FSADJ 39 GREF REFIO IOUTB IOUTA PLLLOCK GND; 4, 22, 44, 45 U12 AD9753 PORT2B[11:0] 37 DIV0 38 DIV1 46 CLKVDD PLLVDD AVDD 3.3V PORT1B[11:0] 2 CLK+ 3 CLK– 1 ACLKG R45 4.75kΩ 46 RPLL_LOCK 42 ROUT– 43 6 40 RFSADJ FSADJ 39 RREF REFIO IOUTB IOUTA PLLLOCK GND; 4, 22, 44, 45 PORT2B[11:0] U11 AD9753 PORT1B[11:0] 37 DIV0 38 DIV1 GRN_B[11:0] [23:34] PLLVDD 05441-009 [7:18] PNL_CLK_ALG 1µF C9 GRN_A[11:0] PLLVDD DAC_DIV0 DAC_DIV1 RST 2 CLK+ 3 CLK– RED_B[11:0] [23:34] RED_A[11:0] PNL_CLK_ALG 47 1 ACLKR R29 4.75kΩ CLKVDD 48 21 DVDD1 5 DVDD2 R30 4.75kΩ 48 CLKVDD 47 PLLVDD R37 75Ω AGRN_OUT TP13 R36 37.4Ω 1 R33 75Ω ARED_OUT TP12 R32 37.4Ω 1 PLLVDD 1µF C10 R38 392Ω DAC_DIV0 DAC_DIV1 RST [7:18] 4 5 ARED_OUT 13 REGEN_HS 15 14 12 REGEN_VS 11 10 9 8 7 6 3 AGRN_OUT 2 1 J6 BPLL_LOCK 42 BOUT– 43 6 R39 0.1µF 2kΩ C7 40 BFSADJ FSADJ 39 BREF REFIO IOUTB IOUTA PLLLOCK GND; 4, 22, 44, 45 ABLU_OUT LPF U13 AD9753 PORT2B[11:0] 37 DIV0 38 DIV1 46 CLKVDD PLLVDD AVDD 3.3V PORT1B[11:0] 2 CLK+ 3 CLK– 1 ACLKB R43 4.75kΩ BLU_B[11:0] [23:34] BLU_A[11:0] PNL_CLK_ALG R42 4.75kΩ 48 CLKVDD 41 AVDD 47 PLLVDD 41 AVDD 41 AVDD –11– PLLVDD 21 DVDD1 5 DVDD2 REV. 0 21 DVDD1 5 DVDD2 Figure 9. CON-HD-15HM CLKVDD PLLVDD AVDD 3.3V R41 75Ω ABLU_OUT TP14 R40 37.4Ω 1 AN-784 05441-010 19 20 21 22 23 24 25 26 27 28 29 P31 G28 P5 P4 P3 P2 P1 G25 G24 G23 G22 G21 3 W1 2 1 36CRPX J1 [10:18] G19 G20 P6 G26 G27 P32 G29 G30 SDA_PAR 30 SDA_USB [33:36] SER_DAT_2PC 3 SCL 1 SDA 2 4 1 U9 2 1Q 2Q 3Q 4Q 5Q U1 EN 1D 2D 3D 4D 5D 6D 7D 8D C1 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 2 3 5 6 8 9 XIN GND +DATA 4 3 22pF C101 22pF 3.3V AVDD C102 XTAL2 2 XOUT 1 XTAL1 1 –DATA 2 PWR_IN J2 USB_A GND; 5, 6 SCL_PAR R19 2kΩ 3.3V SDA_PAR R18 2kΩ 3.3V X2 12MHz CRYSTAL 11 12 13 14 16 17 19 6Q 20 7Q 22 8Q 23 U1 LCX16374A EN 1D 2D 3D 4D C1 NOTE: PLACE W1 AND W2 IN A ROW AND ADD THIS TEXT TO THE SILKSCREEN. 1 47 46 44 43 41 40 38 37 48 24 36 35 33 32 30 5D 29 6D 27 7D 26 8D 25 SOFTWARE INTERFACE SELECTION USING W1-W2: SELECT USB: STRAPS BETWEEN PINS 2 AND 3 SELECT PARALLEL: STRAPS BETWEEN PINS 1 AND 2 74VHC14 74VHC14 STROBE R46 FROM PC 2kΩ 3 U9 SER_CLK SER_DAT_2BD WR_EN R21 2kΩ 3.3V 3.3V W2 1 2 3 4 5 6 31 32 CENTRONICS 36 PIN PRINTER PORT CONNECTOR SCL_USB PAR_STRB 3-STATE DATA LINE SCL_PAR 11 10 9 8 7 6 5 4 3 2 1 AVCC XOUT XIN AGND GND4 GND3 GND2 GND1 CLK24 GND R51 1.5kΩ R47 24.3Ω USB_DATA USB_DATA USBD VCC C11 1µF R49 10kΩ USBRST LCX16374A GND; 4, 10, 15, 21, 28, 34, 39, 45 3.3V; 7, 18, 31, 42 USBD R48 24.3Ω R50 2.21kΩ AN2126SC U14 SCL_SEL SDA_SEL 1 2 3 4 VCC2 24 25 26 27 28 29 30 31 32 33 D0 GND6 23 D1 D2 D3 D4 D5 D6 D7 BKPT USB_SDA 3.3V R12 10kΩ 2A 1OE 1A 2B3 2B2 2B1 1B4 1B3 1B2 1B1 4.75kΩ 4.75kΩ R52 15 2OE 2B4 GND; 8 S0 S1 U7 14 2 R17 9 1 1 2 1 2 SN74CBLTV3253 3.3V; 16 SCL_EE SDA_EE USB_SCL 7 24LCO4B U16 8 A0 VCC 7 A1 WP 6 A2 SCL 5 VSS SDA R16 2.21kΩ 3.3V 44 43 42 41 40 39 38 37 36 35 34 VCC3 DISCON# USBD+ USBD– PA5/FRD# PA4/FWR# GND8 WAKEUP# SCL SDA GND7 GND5 RESET PC0/RXD0 PC1/TXD0 PC2/INT0# PC3/INT1# PC4/T0 PC5/T1 PC6/WR# PC7/RD# VCC1 –12– 12 13 14 15 16 17 18 19 20 21 22 SERIAL INTERFACE CIRCUIT 8 9 10 11 1 2 1 2 R10 10kΩ 74VHC14 74VHC14 SDA_USB SCL_U R5 10kΩ SCL_USB U9 U9 13 12 11 10 3 4 5 6 R11 10kΩ AN-784 Figure 10. REV. 0 REV. 0 Figure 11. –13– 05441-011 + 1 2 3 0.1µF C14 SRT RST_PWR S1 U3 3 2 1 R60 24.3Ω VCC RST LP3470 U4 VCC1 GND SRT C34 C28 C36 C35 C31 C29 C30 C13 C40 C39 C43 C37 C44 C48 C45 C46 C47 C12 C42 C41 C56 C57 C58 C59 C55 C54 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C18 C20 C25 C89 C90 C19 1.5V C15 C23 C24 C22 C21 4 5 R4 1kΩ 3.3V RST LATCH_DE LATCH_DE 2 1 2 1 0.1µF 0.1µF 0.1µF C103 CR2 HSMS-2814 CR1 HSMS-2814 C3 C38 DAC CLK SUPPLY 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF C16 ADD TEXT TO SILKSCREEN: "PWR ON" C32 1µF 3 C33 1µF 3 10µF C1 + FB6 1 R1 10kΩ R2 10kΩ MHz CLKVDD 2 1 2 DE_DETECT2 1 2 DE_DETECT1 C104 0.1µF C17 C61 C62 C63 C64 C60 C65 + AVDD C69 C70 C72 C67 + C71 C73 + LVDS_VCC 2 0.1µF 0.1µF C51 10µF C66 C75 + LVPLL_VCC 2 0.1µF 0.1µF C53 10µF C74 2 2 DVI_PVCC 2 0.1µF 0.1µF 0.1µF C52 10µF LVDS PLL SUPPLY LVDS SUPPLY C68 + 0.1µF 0.1µF 0.1µF C50 10µF DVI PLL SUPPLY DAC PLL SUPPLY PLLVDD 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF C49 10µF 3.3V ANALOG SUPPLY FOR DACS AND DVI TRANSMITTER 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF C76 MHz FB4 MHz FB5 MHz FB2 MHz FB3 MHz FB1 1 1 1 1 1 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF R59 121Ω + C27 POWER-ON RESET 1 GND VOUT 2 ADJ 3.3V + C4 D2 SMT_LED R53 1 1kΩ TP11 1 TP10 1 U8 2 3.3V VOUT LM1086CS VIN C26 10µF 3 TP21 1 1 GND LM1085IT TP9 VIN C2 10µF + 3.3V R9 2kΩ PB_SW J4 2 5V C95 0.1µF C97 0.1µF C99 0.1µF C98 0.1µF C96 0.1µF AN-784 05441-012 AN-784 Figure 12. –14– REV. 0 05441-013 AN-784 Figure 13. REV. 0 –15– 05441-014 AN-784 Figure 14. –16– REV. 0 05441-015 AN-784 Figure 15. REV. 0 –17– 05441-016 AN-784 Figure 16. –18– REV. 0 05441-017 AN-784 Figure 17. REV. 0 –19– –20– –21– –22– –23– AN05481–0– 4/05(0) © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. –24–