IDT709379/69L HIGH-SPEED 32/16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9/12ns (max.) – Insustrial: 9ns (max.) Low-power operation – IDT709379/69L Active: 1.2W (typ.) Standby: 2.5mW (typ.) Flow-Through or Pipelined output mode on either Port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion without additional logic ◆ ◆ ◆ ◆ ◆ Full synchronous operation on both ports – 4ns setup to clock and 0ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 6.5ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 10ns cycle time, 100MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility TTL- compatible, single 5V (±10%) power supply Industrial temperature range (–40°C to +85°C) is available for selected speeds Available in a 100-pin Thin Quad Flatpack (TQFP) package Green parts available, see ordering information Functional Block Diagram R/WL R/WR UBL UBR CE0L 1 0 0/1 CE1L CE0R 1 0 0/1 CE1R LBL OEL LBR OER FT /PIPEL 0/1 1b 0b b a 0a 1a 1a 0a I/O9L-I/O17L a 0b 1b b 0/1 FT/PIPER I/O9R-I/O17R I/O Control I/O Control I/O0L-I/O8L I/O0R-I/O8R A14L(1) A0L CLKL ADSL CNTENL CNTRSTL A14R(1) Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A0R CLKR ADSR CNTENR CNTRSTR 4845 drw 01 NOTE: 1. A14 X is a NC for IDT709369. JULY 2010 1 ©2010 Integrated Device Technology, Inc. DSC-4845/6 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT709379/69 is a high-speed 32/16K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT709379/69 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 1.2W of power. 01/15/04 INDEX A9L A10L A11L A12L A13L 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 11 12 709379/69PF PN100-1(5) 13 14 15 66 65 64 63 100-Pin TQFP Top View(6) 62 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 24 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O9L I/O8L VCC I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R VCC I/O7R I/O8R I/O9R I/O10R A14L(1) NC LBL UBL CE0L CE1L CNTRSTL R/WL OEL VCC FT/PIPEL I/O17L I/O16L GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L CNTENR A0R A1R A2R A3R A4R A5R A6R A7R A8L A7L A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL GND GND ADSR CLKR Pin Configurations(1,2,3) NOTES: 1. A14x is a NC for IDT709369. 2. All VCC pins must be connected to power supply. 3. All GND pins must be connected to ground. 4. Package body is approximately 14mm x 14mm x 1.4mm 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 2 6.42 A8R A9R A10R A11R A12R A13R A14R(1) NC LBR UBR CE0R CE1R CNTRSTR R/WR GND OER . FT/PIPER I/O17R GND I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R 4845 drw 02 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables (3) R/WL R/WR Read/Write Enable OEL OER (1) Output Enable (1) A0L - A14L A0R - A14R Address I/O0L - I/O17L I/O0R - I/O17R Data Input/Output CLKL CLKR Clock UBL UBR Upper Byte Select(2) LBL LBR Lower Byte Selectt(2) ADSL ADSR Address Strobe CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPEL FT/PIPER Flow-Through/Pipeline VCC Power GND Ground NOTES: 1. A14x is a NC for IDT709369. 2. LB and UB are single buffered regardless of state of FT/PIPE. 3. CEo and CE1 are single buffered when FT/PIPE = VIL, CEo and CE 1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect. 4845 tbl 01 Truth Table I—Read/Write and Enable Control(1,2,3) OE CLK CE0 CE1 UB LB R/W Upper Byte I/O9-17 Lower Byte I/O0-8 X ↑ H X X X X High-Z High-Z Deselected—Power Down X ↑ X L X X X High-Z High-Z Deselected—Power Down X ↑ L H H H X High-Z High-Z Both Bytes Deselected X ↑ L H L H L DATAIN High-Z Write to Upper Byte Only X ↑ L H H L L High-Z DATAIN Write to Lower Byte Only X ↑ L H L L L DATAIN DATAIN Write to Both Bytes L ↑ L H L H H DATAOUT High-Z Read Upper Byte Only L ↑ L H H L H High-Z DATAOUT Read Lower Byte Only L ↑ L H L L H DATAOUT DATAOUT Read Both Bytes H X L H L L X High-Z High-Z Outputs Disabled Mode 4845 tbl 02 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. 6.42 3 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table II—Address Counter Control(1,2,6) External Address Previous Internal Address Internal Address Used CLK An X An ↑ ADS CNTEN CNTRST I/O(3) X H DI/O (n) L(4) MODE External Address Used X An An + 1 ↑ H L H DI/O(n+1) Counter Enabled—Internal Address generation X An + 1 An + 1 ↑ H H H DI/O(n+1) External Address Blocked—Counter disabled (An + 1 reused) X X A0 ↑ X X L(4) DI/O(0) (5) Counter Reset to Address 0 4845 tbl 03 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE 0, CE1, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE 0, CE1, UB and LB. 6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily. Recommended Operating Temperature and Supply Voltage Grade Commercial Industrial Recommended DC Operating Conditions Symbol Ambient Temperature(2) GND VCC 0OC to +70OC 0V 5.0V + 10% -40OC to +85OC 0V 5.0V + 10% Parameter VCC Supply Voltage GND Ground Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V VIH Input High Voltage 2.2 ____ VIL Input Low Voltage -0.5(2) ____ (1) 6.0 V 4845 tbl 04 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. 0.8 V 4845 tbl 05 NOTES: 1. VTERM must not exceed VCC + 10%. 2. VIL > -1.5V for pulse width less than 10ns. Capacitance(1) Absolute Maximum Ratings(1) Symbol (2) VTERM Rating Terminal Voltage with Respect to GND Commercial & Industrial Unit -0.5 to +7.0 V Symbol Temperature Under Bias -55 to +125 TSTG Storage Temperature -65 to +150 o C +150 o C IOUT DC Output Current 50 C mA Parameter Input Capacitance COUT TBIAS Junction Temperature CIN (3) o TJN (TA = +25°C, f = 1.0MHz) Output Capacitance Conditions(2) Max. Unit VIN = 3dV 9 pF VOUT = 3dV 10 pF 4845 tbl 07 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. 4845 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%. 3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected. 4 6.42 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range (VCC = 5.0V ± 10%) 709379/69L Symbol Parameter Test Conditions (1) Min. Max. Unit 5 µA |ILI| Input Leakage Current VCC = 5.5V, VIN = 0V to VCC ___ |ILO| Output Leakage Current CE0 = VIH or CE1 = VIL, VOUT = 0V to VCC ___ 5 µA VOL Output Low Voltage IOL = +4mA ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ V 4845 tbl 08 NOTE: 1. At Vcc < 2.0V input leakages are undefined. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(3) (VCC = 5V ± 10%) 709379/69L6 Com'l Only Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Test Condition 709379/69L7 Com'l Only 709379/69L9 Com'l & Ind 709379/69L12 Com'l Only Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Unit L 270 525 250 440 250 400 230 355 mA ____ ____ ____ ____ 300 430 ____ ____ 80 135 70 110 ____ Version Dynamic Operating Current (Both Ports Active) CEL and CER= V IL Outputs Disabled f = fMAX(1) COM'L IND L Standby Current (Both Ports - TTL Level Inputs) CEL = CER = V IH f = fMAX(1) COM'L L 80 175 65 145 IND L ____ ____ ____ ____ 95 160 ____ Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = V IH(3) Active Port Outputs Disabled, f=fMAX(1) COM'L L 180 360 160 295 175 275 150 240 ____ ____ ____ ____ L 295 ____ IND 175 ____ Full Standby Current (Both Ports CMOS Level Inputs) Both Ports CE R and CEL > V CC - 0.2V V IN > V CC - 0.2V or V IN < 0.2V, f = 0(2) COM'L L 0.2 5 0.2 5.0 0.5 3.0 0.5 3.0 IND L ____ ____ ____ ____ 0.5 6.0 ____ ____ Full Standby Current (One Port CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) V IN > V CC - 0.2V or V IN < 0.2V, Active Port Outputs Disabled, f = fMAX(1) COM'L L 170 340 150 290 170 270 140 225 IND L ____ ____ ____ ____ 190 290 ____ ____ mA mA mA mA 4845 tbl 09 NOTES: 1. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC , using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VCC = 5V, TA = 25°C for Typ, and are not production tested. I CC DC(f=0) = 150mA (Typ). 5. CE X = VIL means CE0X = VIL and CE1X = VIH CE X = VIH means CE0X = VIH or CE1X = VIL CE X < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V CE X > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port. 6.42 5 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Test Conditions GND to 3.0V Input Pulse Levels 3ns Max. Input Rise/Fall Times Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Figures 1,2 and 3 Output Load 4845 tbl 10 5V 5V 893Ω 893Ω DATAOUT DATAOUT 30pF 347Ω 4845 drw 04 4845 drw 05 Figure 1. AC Output Test load. 8 7 Figure 2. Output Test Load (For tCKLZ , tCKHZ, tOLZ, and tOHZ). *Including scope and jig. - 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance 6 tCD1, tCD2 (Typical, ns) 5 4 3 2 1 0 -1 5pF* 347Ω 20 40 60 80 100 120 140 160 180 200 Capacitance (pF) 4845 drw 06 Figure 3. Typical Output Derating (Lumped Capacitive Load). 6 6.42 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3) (VCC = 5V ± 10%) 709379/69L6 Com'l Only Symbol tCYC1 Parameter Clock Cycle Time (Flow-Through)(2) (2) 709379/69L7 Com'l Only 709379/69L9 Com'l & Ind 709379/69L12 Com'l Only Min. Max. Min. Max. Min. Max. Min. Max. Unit 19 ____ 22 ____ 25 ____ 30 ____ ns ns tCYC2 Clock Cycle Time (Pipelined) 10 ____ 12 ____ 15 ____ 20 ____ tCH1 Clock High Time (Flow-Through)(2) 6.5 ____ 7.5 ____ 12 ____ 12 ____ ns tCL1 (2) 6.5 ____ 7.5 ____ 12 ____ 12 ____ ns tCH2 (2) Clock High Time (Pipelined) 4 ____ 5 ____ 6 ____ 8 ____ ns tCL2 Clock Low Time (Pipelined)(2) 4 ____ 5 ____ 6 ____ 8 ____ ns Clock Low Time (Flow-Through) Clock Rise Time ____ 3 ____ 3 ____ 3 ____ 3 ns tF Clock Fall Time ____ 3 ____ 3 ____ 3 ____ 3 ns tSA Address Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns 0 ____ 0 ____ 1 ____ 1 ____ ns 4 ____ 4 ____ 4 ____ ns 0 ____ 1 ____ 1 ____ ns 4 ____ 4 ____ ns 1 ____ 1 ____ ns ns tR tHA Address Hold Time tSC Chip Enable Setup Time 3.5 ____ tHC Chip Enable Hold Time 0 ____ 4 ____ 0 ____ tSB Byte Enable Setup Time 3.5 ____ tHB Byte Enable Hold Time 0 ____ 3.5 ____ 4 ____ 4 ____ 4 ____ 0 ____ 0 ____ 1 ____ 1 ____ ns 3.5 ____ 4 ____ 4 ____ 4 ____ ns 0 ____ 0 ____ 1 ____ 1 ____ ns 4 ____ 4 ____ 4 ____ ns 0 ____ 1 ____ 1 ____ ns 4 ____ 4 ____ 4 ____ ns ns tSW R/W Setup Time tHW R/W Hold Time tSD Input Data Setup Time tHD Input Data Hold Time tSAD ADS Setup Time 3.5 ____ tHAD ADS Hold Time 0 ____ tSCN CNTEN Setup Time 3.5 ____ tHCN CNTEN Hold Time 0 ____ 0 ____ 1 ____ 1 ____ tSRST CNTRST Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns tHRST CNTRST Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns ____ 6.5 ____ 7.5 ____ 9 ____ 12 ns tOLZ (1) Output Enable to Output Low-Z 2 ____ 2 ____ 2 ____ 2 ____ ns tOHZ Output Enable to Output High-Z(1) 1 7 1 7 1 7 1 7 ns ____ 15 ____ 18 ____ 20 ____ 25 ns ____ 6.5 ____ 7.5 ____ 9 ____ 12 ns 2 ____ 2 ____ 2 ____ 2 ____ ns tOE Output Enable to Data Valid tCD1 Clock to Data Valid (Flow-Through) tCD2 Clock to Data Valid (Pipelined)(2) tDC (2) Data Output Hold After Clock High tCKHZ (1) Clock High to Output High-Z 2 9 2 9 2 9 2 9 ns tCKLZ Clock High to Output Low-Z(1) 2 ____ 2 ____ 2 ____ 2 ____ ns Port-to-Port Delay tCWDD Write Port Clock High to Read Data Delay ____ 24 ____ 28 ____ 35 ____ 40 ns tCCS Clock-to-Clock Setup Time ____ 9 ____ 10 ____ 15 ____ 15 ns 4845 tbl 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2 ) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port . 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER and FT/PIPEL. 6.42 7 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL)(3,7) tCYC1 tCH1 tCL1 CLK CE0 tSC tSC tHC tHC (4) CE1 tSB tHB UB, LB tHB tSB R/W tSW tHW tSA tHA (5) ADDRESS An An + 1 tCD1 tCKLZ An + 3 tCKHZ (1) Qn DATAOUT OE An + 2 tDC Qn + 1 (1) tOHZ Qn + 2 (1) tOLZ tDC (1) (2) tOE 4845 drw 07 Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE"X" = VIH)(3,7) tCYC2 tCH2 tCL2 CLK CE0 tSC tSC tHC tHC (4) CE1 UB, LB R/W (5) ADDRESS tSB tSB tHB tHB (6) tSW tHW tSA tHA An An + 1 (1 Latency) An + 2 tDC tCD2 DATAOUT Qn tCKLZ An + 3 Qn + 1 (1) tOHZ Qn + 2 (1) tOLZ (6) (1) (2) OE tOE 4845 drw 08 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). 7. "X" here denotes Left or Right port. The diagram is with respect to that port. 8 6.42 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of a Bank Select Pipelined Read(1,2) tCH2 tCYC2 tCL2 CLK tSA A0 ADDRESS(B1) CE0(B1) tHA tSC A6 A5 A4 A3 A2 A1 tHC tSC tHC tCD2 Q0 DATAOUT(B1) tCD2 Q3 tCKLZ (3) tCKHZ (3) tHA A0 ADDRESS(B2) tCKHZ Q1 tDC tDC tSA (3) tCD2 A6 A5 A4 A3 A2 A1 tSC tHC CE0(B2) tSC tHC tCKHZ (3) tCD2 DATAOUT(B2) tCKLZ (3) Q2 tCD2 Q4 tCKLZ (3) 4845 drw 09 Timing Waveform of Write with Port-to-Port Flow-Through Read(4,5,7) CLK "A" tSW tHW R/W "A" tSA ADDRESS "A" NO MATCH MATCH tSD DATAIN "A" tHA tHD VALID tCCS (6) CLK "B" tCD1 R/W "B" ADDRESS "B" tSW tHW tSA tHA NO MATCH MATCH tCWDD (6) tCD1 DATAOUT "B" VALID VALID tDC tDC 4845 drw 10 NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709379/69 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS (B2) in this situation. 2. UB, LB, OE, and ADS = VIL; CE 1(B1), CE1(B2) , R/W and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0, UB, LB, and ADS = VIL; CE1 and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. t CWDD does not apply in this case. 7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A". 6.42 9 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3) tCYC2 tCH2 tCL2 CLK CE0 tSC tHC tSB tHB CE1 UB, LB tSW tHW R/W (4) ADDRESS tSW tHW An tSA tHA An +1 An + 2 An + 3 An + 2 An + 4 tSD tHD DATAIN Dn + 2 tCD2 (2) tCKHZ (1) (1) tCKLZ tCD2 Qn + 3 Qn DATAOUT (5) READ NOP WRITE READ 4845 drw 11 Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled)(3) tCYC2 tCH2 tCL2 CLK CE0 tSC tHC tSB tHB CE1 UB, LB tSW tHW R/W (4) ADDRESS tSW tHW An tSA tHA An +1 An + 2 tSD DATAIN An + 4 An + 5 tHD Dn + 2 tCD2 (2) An + 3 Dn + 3 tCKLZ(1) tCD2 Qn DATAOUT Qn + 4 tOHZ(1) OE READ WRITE READ 4845 drw 12 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1 and CNTRST = V IH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 10 6.42 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3) tCH1 tCYC1 tCL1 CLK CE0 tSC tHC tSB tHB CE1 UB, LB tSW tHW R/W tSW tHW (4) ADDRESS tSA An tHA An +1 An + 2 An + 4 An + 3 An + 2 tSD tHD DATAIN Dn + 2 tCD1 (2) tCD1 Qn DATAOUT tCD1 tCD1 Qn + 3 Qn + 1 tDC tCKHZ (5) NOP READ (1) (1) tCKLZ WRITE tDC READ 4845 drw 13 Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3) tCYC1 tCH1 tCL1 CLK CE0 tSC tHC tSB tHB CE1 UB, LB tSW tHW R/W tSW tHW (4) ADDRESS tSA An tHA An +1 An + 2 DATAIN Dn + 2 (2) DATAOUT An + 3 An + 4 An + 5 tSD tHD Dn + 3 tDC tCD1 Qn tOE tCD1 (1) tOHZ tCKLZ (1) tCD1 Qn + 4 tDC OE READ WRITE READ 4845 drw 14 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals. 3. CE 0, UB, LB, and ADS = VIL; CE1 and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 11 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read with Address Counter Advance(1) tCH2 tCYC2 tCL2 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD CNTEN tSCN tHCN tCD2 DATAOUT Qx - 1(2) Qn + 2(2) Qn + 1 Qn Qx Qn + 3 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 4845 drw 15 Timing Waveform of Flow-Through Read with Address Counter Advance(1) tCH1 tCYC1 tCL1 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tCD1 DATAOUT Qx(2) Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 4845 drw 16 NOTES: 1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks. 12 6.42 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs)(1) tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL(3) ADDRESS An(7) An + 2 An + 1 An + 4 An + 3 tSAD tHAD ADS CNTEN tSD tHD Dn + 1 Dn DATAIN WRITE EXTERNAL ADDRESS Dn + 1 Dn + 4 Dn + 3 Dn + 2 WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 4845 drw 17 Timing Waveform of Counter Reset (Pipelined Outputs)(2) tCH2 tCYC2 tCL2 CLK tSA tHA ADDRESS(4) INTERNAL(3) ADDRESS An Ax(6) 0 1 An + 2 An + 1 An + 1 An tSW tHW R/W ADS CNTEN tSRST tHRST CNTRST tSD tHD D0 DATAIN Qn Q1 Q0 DATAOUT(5) . COUNTER(6) RESET WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 READ ADDRESS n READ ADDRESS n+1 4845 drw 18 NOTES: 1. CE0, UB, LB, and R/W = V IL; CE1 and CNTRST = VIH. 2. CE0, UB, LB = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. 7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’ Address is written to during this cycle. 6.42 13 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges A Functional Description Depth and Width Expansion The IDT709379/69 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. CE0 = VIH or CE1 = VIL for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT709379/69's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are required with CE0 = VIL and CE1 = VIH to reactivate the outputs. The IDT709379/69 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT709379/69 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 36-bit or wider applications. A15/A14(1) IDT709379/69 CE0 CE1 CE1 VCC CE1 IDT709379/69 VCC CE1 CE0 CE0 Control Inputs CE0 Control Inputs Control Inputs IDT709379/69 IDT709379/69 Control Inputs 4845 drw 19 Figure 4. Depth and Width Expansion with IDT709379/69 NOTE: 1. A14 is for IDT709369. 14 6.42 CNTRST CLK ADS CNTEN R/W LB, UB OE IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Ordering Information XXXXX A 99 A Device Type Power Speed Package A A Process/ Temperature Range Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G(2) Green PF 100-pin TQFP (PN100-1) 6 7 9 12 Commercial Commercial Commercial Commercial Only Only & Industrial Only L Low Power 709379 709369 576K (32K x 18-Bit) Synchronous Dual-Port RAM 288K (16K x 18-Bit) Synchronous Dual-Port RAM Speed in nanoseconds 4845 drw 20 NOTE: 1. Industrial temperature range is available. For other speeds, packages and powers contact your sales office 2. Green parts available. For specific speeds, packages and powers contact your sales office. IDT Clock Solution for IDT709379/69 Dual-Port Dual-Port I/O Specitications IDT Dual-Port Part Number Voltage 709379/69 5 Clock Specifications I/O Input Capacitance Input Duty Cycle Requirement Maximum Frequency Jitter Tolerance IDT PLL Clock Device IDT Non-PLL Clock Device TTL 9pF 40% 100 150ps FCT88915TT 49FCT805T 49FCT806T 74FCT807T 4860 tbl 12 6.42 15 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Datasheet Document History 9/30/99: 11/10/99: 12/22/99: 1/12/01: Page 1 Page 4 Page 5 04/26/04: Page 2 Page 4 Page 5 Page 7 Page 15 01/29/09: 07/26/10: Page 1 & 16 Page 15 Page 1 Page 15 Page 7 Pages 8-11 Initial Public Release Replaced IDT log Added nmissing diamond Changed information in Truth Table II Increased storage temperature parameter Clarified TA parameter DC Electrical parameters–changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes Removed Preliminary status Consolidated multiple devices into one datasheet Removed I-temp footnote Added date revision to pin configuration Added Junction Temperature to Absolute Maximum Ratings Table Added Ambient Temperature footnote Added I-temp numbers for 9ns speed to the DC Electrical Characteristics Table Added 6ns speed DC timing numbers to the DC Electrical Characteristics Table Added I-temp for 9ns speed to AC Electrical CharacteristicsTable Added 6ns speed AC timing numbers to the AC Electrical Characteristics Table Added 6ns speed grade and 9ns I-temp to ordering information Added IDT Clock Solution Table Replaced old TM logo with new TM logo Removed "IDT" from orderable part number Added green parts availability to features Added green indicator to ordering information In order to correct the header notes of the AC Elect Chars Table and align them with the Industrial temp range values located in the table, the commercial TA header note has been removed In order to correct the footnotes of timing diagrams, CNTEN has been removed to reconcile the footnotes with the CNTEN logic definition found in Truth Table II - Address Counter Control CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 16 6.42 for Tech Support: 408-284-2794 [email protected]