HIGH-SPEED 64K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM PRELIMINARY IDT709089S/L Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 9/12/15ns (max.) Low-power operation – IDT709089S Active: 950mW (typ.) Standby: 5mW (typ.) – IDT709089L Active: 950mW (typ.) Standby: 1mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pin Counter enable and reset features Dual chip enables allow for depth expansion without additional logic ◆ ◆ ◆ Full synchronous operation on both ports – 4ns setup to clock and 1ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 9ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 15ns cycle time, 66MHz operation in the Pipelined output mode TTL- compatible, single 5V (±10%) power supply Industrial temperature range (–40°C to +85°C) is available for selected speeds Available in 100-pin Thin Quad Flatpack (TQFP) package Functional Block Diagram R/WR R/WL OEL OER CE0L FT/PIPEL 0/1 1 0 0 I/O0L - I/O7L 1 0/1 FT/PIPER I/O0R - I/O7R A15L ADSL CNTENL CNTRSTL CE1R I/O Control I/O Control A0L CLKL CE0R 1 0 0/1 1 0 0/1 CE1L A15R Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A0R CLKR ADSR CNTENR CNTRSTR 3242 drw 01 FEBRUARY 2000 1 ©2000 Integrated Device Technology, Inc. DSC-3242/10 IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Description: With an input data register, the IDT709089 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 950mW of power. The IDT709089 is a high-speed 64K x 8 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. A0R A1R A2R A3R A4R A5R A6R NC NC CNTENR ADSR CLKR ADSL GND CLKL NC NC A6L A5L A4L A3L A2L A1L A0L Index CNTENL Pin Configuration(1,2,3) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 3 73 4 72 NC NC A7L A8L A9L A10L A11L A12L A13L A14L A15L NC VCC NC NC NC NC 1 CE0L CE1L 19 CNTRSTL R/WL OEL FT/PIPEL 20 NC NC 24 2 5 71 6 7 70 69 8 68 67 9 10 11 12 13 14 IDT709089PF PN100-1(4) 66 100-PIN TQFP TOP VIEW(5) 63 65 64 62 NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R NC GND NC NC NC NC 16 61 60 17 59 18 58 57 CE0R 56 55 CNTRSTR R/WR OER FT/PIPER 15 21 54 22 23 53 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CE1R GND NC GND NC I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R I/O7R NC NC NC 3242 drw 02 NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 6.42 2 IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A15L A0R - A15R Address I/O0L - I/O7L I/O0R - I/O7R Data Input/Output CLKL CLKR Clock ADSL ADSR Address Strobe CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPE L FT/PIPE R Flow-Through/Pipeline VCC Power GND Ground 3242 tbl 01 Truth Table I Read/Write and Enable Control(1,2,3) OE CLK CE0 CE1 R/W I/O0-7 X ↑ H X X High-Z Deselected X ↑ X L X High-Z Deselected X ↑ L H L DIN Write L ↑ L H H DOUT Read H X L H X High-Z Outputs Disabled Mode 3242 tbl 02 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. Truth Table IIAddress Counter Control(1,2) Address Previous Address CLK ADS CNTEN CNTRST I/O(3) X X ↑ H H L DI/O(0) Counter Reset to Address 0 An X ↑ L(4) H H DI/O(n) External Address Utilized X An ↑ H H H DI/O(n) External Address Blocked—Counter Disabled An ↑ H DI/O(n+1) Counter Enable—Internal Address Generation X H (5) L Mode NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0 and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE0 and CE1. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1. 3 6.42 3242 tbl 03 IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Recommended Operating Recommended DC Operating (1,2) Temperature and Supply Voltage Conditions Grade Commercial Industrial Symbol Ambient Temperature GND Vcc 0OC to +70OC 0V 5.0V + 10% -40OC to +85OC 0V 5.0V + 10% Parameter VCC Supply Voltage GND Ground VIH Input High Voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V 2.2 ____ (1) 6.0 V 3242 tbl 04 NOTES: 1. This is the parameter TA. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office. VIL VTERM (2) Rating Terminal Voltage with Respect to GND ____ 0.8 V 3242 tbl 05 Capacitance(1) Commercial & Industrial Unit -0.5 to +7.0 V (TA = +25°C, f = 1.0MHz) Symbol COUT TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -55 to +125 o IOUT DC Output Current C C mA Parameter Input Capacitance CIN (3) 50 -0.5 NOTES: 1. VTERM must not exceed VCC + 10%. 2. VIL > -1.5V for pulse width less than 10ns. Absolute Maximum Ratings(1) Symbol Input Low Voltage (2) Output Capacitance Conditions(2) Max. Unit VIN = 3dV 9 pF VOUT = 3dV 10 pF 3242 tbl 07 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. 3242 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. 6.42 4 IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 709089S/L Symbol Parameter Test Conditions (1) Min. Max. Unit 10 µA |ILI| Input Leakage Current VCC = 5.5V, VIN = 0V to V CC ___ |ILO| Output Leakage Current CE0 = VIH or CE1 = VIL, VOUT = 0V to V CC ___ 10 µA VOL Output Low Voltage IOL = +4mA ___ 0.4 V 2.4 ___ V VOH Output High Voltage IOH = -4mA 3242 tbl 08 NOTE: 1. At Vcc < 2.0V input leakages are undefined. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6,7) (VCC = 5V ± 10%) 709089X9 Com'l Only Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports CMOS Level Inputs) Full Standby Current (One Port CMOS Level Inputs) Test Condition CEL and CER= VIL Outputs Open f = fMAX(1) CEL = CER = VIH Version Active Port Outputs Open, f=fMAX(1) Both Ports CER and CEL > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(2) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX(1) 709089X15 Com'l Only Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Unit mA COM'L S L 210 210 390 350 200 200 345 305 190 190 325 285 IND S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ COM'L S L 50 50 135 115 50 50 100 90 50 50 110 90 IND S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ COM'L S L 140 140 270 240 130 130 230 200 120 120 220 190 IND S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 IND S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ COM'L S L 130 130 245 225 120 120 205 185 110 110 195 175 IND S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ f = fMAX(1) CE"A" = VIL and CE"B" = VIH(3) 709089X12 Com'l Only mA mA mA mA 3242 tbl 09 NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port. 6. 'X' in part numbers indicate power (S or L). 7. Industrial temperature: for specific speeds, packages and powers contact your sales office. 5 6.42 IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1,2 and 3 3242 tbl 10 5V 5V 893Ω 893Ω DATAOUT DATAOUT 30pF 347Ω 5pF* 347Ω 3242 drw 04 3242 drw 05 Figure 1. AC Output Test load. 8 7 Figure 2. Output Test Load (For tCKLZ, tCKHZ, tOLZ, and tOHZ). *Including scope and jig. -10 pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance 6 tCD1, tCD2 (Typical, ns) 5 4 3 2 1 0 -1 20 40 60 80 100 120 140 160 180 200 Capacitance (pF) 3242 drw 06 Figure 3. Typical Output Derating (Lumped Capacitive Load). 6.42 6 , IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3,4,5) (VCC = 5V ± 10%, TA = 0°C to +70°C) 709089X9 Com'l Only Symbol tCYC1 Parameter (2) Clock Cycle Time (Flow-Through) (2) Min. Max. 25 ____ 709089X12 Com'l Only Min. Max. 30 ____ 709089X15 Com'l Only Min. Max. Unit 35 ____ ns ns tCYC2 Clock Cycle Time (Pipelined) 15 ____ 20 ____ 25 ____ tCH1 Clock High Time (Flow-Through)(2) 12 ____ 12 ____ 12 ____ ns tCL1 (2) 12 ____ 12 ____ 12 ____ ns 6 ____ 8 ____ 10 ____ ns 6 ____ 8 ____ 10 ____ ns 3 ns tCH2 tCL2 Clock Low Time (Flow-Through) Clock High Time (Pipelined) (2) (2) Clock Low Time (Pipelined) Clock Rise Time ____ 3 ____ 3 ____ tF Clock Fall Time ____ 3 ____ 3 ____ 3 ns tSA Address Setup Time 4 ____ 4 ____ 4 ____ ns tHA Address Hold Time 1 ____ 1 ____ 1 ____ ns 4 ____ 4 ____ 4 ____ ns 1 ____ 1 ____ 1 ____ ns 4 ____ 4 ____ 4 ____ ns ns tR tSC Chip Enable Setup Time tHC Chip Enable Hold Time tSW R/W Setup Time tHW R/W Hold Time 1 ____ 1 ____ 1 ____ tSD Input Data Setup Time 4 ____ 4 ____ 4 ____ ns tHD Input Data Hold Time 1 ____ 1 ____ 1 ____ ns tSAD ADS Setup Time 4 ____ 4 ____ 4 ____ ns tHAD ADS Hold Time 1 ____ 1 ____ 1 ____ ns tSCN CNTEN Setup Time 4 ____ 4 ____ 4 ____ ns tHCN CNTEN Hold Time 1 ____ 1 ____ 1 ____ ns tSRST CNTRST Setup Time 4 ____ 4 ____ 4 ____ ns tHRST CNTRST Hold Time 1 ____ 1 ____ 1 ____ ns ____ 12 ____ 12 ____ 15 ns 2 ____ 2 ____ 2 ____ ns 1 7 1 7 1 7 ns tOE Output Enable to Data Valid tOLZ Output Enable to Output Low-Z(1) tOHZ Output Enable to Output High-Z(1) tCD1 tCD2 tDC (2) ____ Clock to Data Valid (Flow-Through) (2) Clock to Data Valid (Pipelined) Data Output Hold After Clock High 20 ____ 25 ____ 30 ns ____ 9 ____ 12 ____ 15 ns 2 ____ 2 ____ 2 ____ ns tCKHZ (1) Clock High to Output High-Z 2 9 2 9 2 9 ns tCKLZ Clock High to Output Low-Z(1) 2 ____ 2 ____ 2 ____ ns Write Port Clock High to Read Data Delay ____ 40 ____ 40 ____ 50 ns Clock-to-Clock Setup Time ____ 15 ____ 15 ____ 20 Port-to-Port Delay tCWDD tCCS ns 3242 tbl 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a DC signal, i.e. steady state during operation. 4. 'X' in part number indicates power rating (S or L). 5. Industrial temperature: for specific speeds, packages and powers contact your sales office. 7 6.42 IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL)(3,6) tCYC1 tCH1 tCL1 CLK CE0 tSC tHC tSC tHC (4) CE1 R/W (5) ADDRESS tSW tHW tSA tHA An An + 1 tCKHZ (1) Qn DATAOUT tCKLZ An + 3 tDC tCD1 OE An + 2 Qn + 1 (1) tOHZ Qn + 2 (1) tOLZ tDC (1) (2) tOE 3242 drw 07 Timing Waveform of Read Cycle for Pipelined Output (FT/PIPE"X" = VIH)(3,6) tCYC2 tCH2 tCL2 CLK CE0 tSC tSC tHC (4) CE1 R/W ADDRESS(5) tHC tSW tHW tSA tHA An An + 1 (1 Latency) An + 2 tDC tCD2 DATAOUT Qn tCKLZ An + 3 Qn + 1 (1) tOHZ Qn + 2 (1) tOLZ (1) (2) OE tOE NOTES: 3242 drw 08 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. "X" denotes Left or Right port. The diagram is with respect to that port. 6.42 8 IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of a Bank Select Pipelined Read(1,2) tCH2 tCYC2 tCL2 CLK tSA ADDRESS(B1) +-0(B1) tHA A0 tSC tHC tSC tHC tCD2 tCD2 Q0 DATAOUT(B1) tSC tCD2 Q3 tCKLZ (3) tCKHZ (3) A6 A5 A4 A3 A2 A1 tSC +-0(B2) (3) tHA A0 ADDRESS(B2) tCKHZ Q1 tDC tDC tSA A6 A5 A4 A3 A2 A1 tHC tHC tCD2 DATAOUT(B2) tCKLZ (3) tCKHZ (3) tCD2 Q2 Q4 tCKLZ (3) 3242 drw 09 Timing Waveform of a Bank Select Flow-Through Read(6,7) tCH1 tCYC1 tCL1 CLK tSA ADDRESS(B1) CE0(B1) tHA A0 tSC A6 A5 A4 A3 A2 A1 tHC tSC tHC tCD1 tCD1 D0 DATAOUT(B1) tCKHZ tCD1 D3 tCKLZ tDC (1) D5 tCKHZ (1) tCKLZ (1) tHA A0 ADDRESS(B2) tCD1 D1 tDC tSA (1) A1 A6 A5 A4 A3 A2 tSC tHC CE0(B2) tSC tHC tCD1 DATAOUT(B2) tCKLZ (1) tCKHZ (1) tCD1 D2 tCKLZ (1) tCKHZ (1) D4 3242 drw 09a NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one 709089 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case. 7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A". 9 6.42 IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform with Port-to-Port Flow-Through Read(1,2,3,5) CLK "A" tSW tHW tSA tHA R/W"A" ADDRESS"A" tSD DATAIN"A" NO MATCH MATCH tHD VALID tCCS (4) CLK"B" tCD1 R/W"B" tSW tHW tSA ADDRESS"B" tHA NO MATCH MATCH tCWDD (4) tCD1 DATAOUT"B" VALID tDC VALID tDC 3242 drw 10 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 3. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 4. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case. 5. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A". 6.42 10 IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3) tCYC2 tCH2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W (4) ADDRESS tSW tHW An tSA tHA An +1 An + 2 An + 3 An + 2 An + 4 tSD tHD DATAIN Dn + 2 tCD2 (2) tCKHZ (1) tCKLZ (1) tCD2 Qn + 3 Qn DATAOUT READ NOP (5) WRITE READ 3242 drw 11 Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3) tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 tSW tHW R/W (4) ADDRESS tSW tHW An tSA tHA An +1 An + 2 tSD DATAIN Dn + 2 tCD2 (2) An + 3 An + 4 An + 5 tHD Dn + 3 tCKLZ(1) tCD2 Qn DATAOUT Qn + 4 tOHZ(1) OE READ WRITE READ 3242 drw 12 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 11 6.42 IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform Flow-Through Read-to-Write-to-Read (OE = VIL)(3) tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW (4) ADDRESS tSA An tHA An +1 An + 2 An + 4 An + 3 An + 2 tSD tHD DATAIN Dn + 2 tCD1 (2) tCD1 tCD1 Qn DATAOUT tCD1 Qn + 3 Qn + 1 tDC tCKHZ (5) NOP READ (1) (1) tCKLZ WRITE tDC READ 3242 drw 13 Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3) tCYC1 tCH1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW (4) ADDRESS tSA An tHA An +1 An + 2 DATAIN Dn + 3 Dn + 2 (2) DATAOUT An + 3 An + 4 An + 5 tSD tHD tDC tCD1 Qn tOE tCD1 (1) tOHZ tCKLZ (1) tCD1 Qn + 4 tDC OE READ WRITE READ 3242 drw 14 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals. 3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 12 IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read with Address Counter Advance(1) tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS tSAD tHAD ADS tSAD tHAD CNTEN tSCN tHCN tCD2 DATAOUT Qx - 1(2) Qn + 2(2) Qn + 1 Qn Qx Qn + 3 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 3242 drw 15 Timing Waveform of Flow-Through Read with Address Counter Advance(1) tCYC1 tCH1 tCL1 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tCD1 DATAOUT Qx(2) Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 3242 drw 16 NOTES: 1. CE0 and OE = VIL; CE1, R/W, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks. 13 6.42 IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs)(1) tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL(3) ADDRESS An(7) An + 2 An + 1 An + 4 An + 3 tSAD tHAD ADS CNTEN tSD tHD Dn + 1 Dn DATAIN WRITE EXTERNAL ADDRESS Dn + 1 Dn + 4 Dn + 3 Dn + 2 WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 3242 drw 17 Timing Waveform of Counter Reset (Pipelined Outputs)(2) tCH2 tCYC2 tCL2 CLK tSA tHA (4) An ADDRESS INTERNAL(3) ADDRESS Ax (6) 0 1 An + 1 An + 2 An + 1 An tSW tHW R/W ADS tSAD tHAD CNTEN tSCN tHCN tSRST tHRST CNTRST tSD tHD D0 DATAIN (5) Q1 Q0 DATAOUT COUNTER RESET (6) WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 READ ADDRESS n Qn READ ADDRESS n+1 3242 drw 18 NOTES: 1. CE0 and R/W = VIL; CE1 and CNTRST = VIH. 2. CE0 = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. ADDR0 will be accessed. Extra cycles are shown here simply for clarification. 7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written to during this cycle. 6.42 14 IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Functional Description Depth and Width Expansion The IDT709089 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT709089's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are required with CE0 LOW and CE1 HIGH to reactivate the outputs. The IDT709089 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The 709089 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 16-bit or wider applications. A15 IDT709089 CE0 CE1 IDT709089 CE1 VCC VCC Control Inputs Control Inputs IDT709089 CE0 IDT709089 CE1 CE1 CE0 CE0 Control Inputs Control Inputs 3242 drw 19 Figure 4. Depth and Width Expansion with IDT709089 15 6.42 CNTRST CLK ADS CNTEN R/W OE IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX A 99 A A Device Type Power Speed Package Process/ Temperature Range Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) PF 100-pin TQFP (PN100-1) 9 12 15 Commercial Only Commercial Only Commercial Only S L Standard Power Low Power Speed in nanoseconds 709089 512K (64K x 8-Bit) Synchronous Dual-Port RAM 3242 drw 20A NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. Ordering Information for Flow-through Devices Old Flow-through Part New Combined Part 70908S/L20 709089S/L9 70908S/L25 709089S/L12 70908S/L30 709089S/L15 3242 tbl 12 Preliminary Datasheet: "PRELIMINARY' datasheets contain descriptions for products that are in early release. 6.42 16 IDT709089S/L High-Speed 64K x 8 Synchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Datasheet Document History 1/12/99: 6/7/99: 11/10/99: 12/22/99: 1/12/00: 2/18/00: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Page 15 Added Depth and Width Expansion note Changed drawing format Page 4 Deleted note 6 for Table II Replaced IDT logo Page 1 Removed "Separate upper-byte..." line Combined Pipelined 709089 family and Flow-through 70908 family offerings into one data sheet Changed ±200mV in waveform notes to 0mV Added corrresponding part chart with ordering information Pages 8 and 9 Changed ±220mV waveform notes to 0mV Page 9 Changed "Operation" in heading to "Pipelined Output", fixed drawing 08 Removed PGA pin CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 17 6.42 for Tech Support: 831-754-4613 [email protected]