HIGH-SPEED 3.3V 16K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM IDT70V9269S/L Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 9/12/15ns (max.) Low-power operation – IDT70V9269S Active: 429mW (typ.) Standby: 3.3mW (typ.) – IDT70V9269L Active: 429mW (typ.) Standby: 1.32mW (typ.) Flow-through or Pipelined output mode on either port via the FT/PIPE pin Counter enable and reset features Dual chip enables allow for depth expansion without ◆ ◆ ◆ ◆ ◆ additional logic Full synchronous operation on both ports – 4ns setup to clock and 1ns hold on all Control, data, and address inputs – Data input, address, and control registers – Fast 9ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 15ns cycle time, 66MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 3.3V (±0.3V) power supply Industrial temperature range (–40°C to +85°C) is available for selected speeds Available in a 128-pin Thin Quad Flatpack (TQFP) package Functional Block Diagram R/WL R/WR UBR UBL CE0L 1 0 CE1L CE0R 1 0 0/1 0/1 CE1R LBL OEL LBR OER FT/PIPEL 0/1 1b 0b b a 0a 1a 1a 0a a b 0b 1b I/O8L-I/O15L 0/1 FT/PIPER I/O8R-I/O15R I/O Control I/O Control I/O0L-I/O7L I/O0R-I/O7R A13R A13L A0L CLKL ADSL Counter/ Address Reg. MEMORY ARRAY CNTENL CNTRSTL Counter/ Address Reg. A0R CLKR ADSR CNTENR CNTRSTR 3752 drw 01 JANUARY 2001 1 ©2000 Integrated Device Technology, Inc. DSC 3752/6 IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Description: 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 70V9269PRF PK-128(4) 128-Pin TQFP Top View(5) 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 A10L A11L A12L A13L N/C N/C N/C N/C LBL UBL CE 0L CE 1L CNTRST L VCC GND R/WL OEL FT/PIPEL GND I/O15L I/O14L I/O13L I/O12L VCC GND I/O11L N/C N/C N/C N/C A9R A8R A7R A6R A5R A4R A3R A2R A1R A0R NC CNTENR CLKR ADSR GND VCC ADSL CLKL CNTENL NC A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L N/C N/C N/C N/C 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Configuration(1,2,3) With an input data register, the IDT70V9269 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 429mW of power. A10R A11R A12R A13R N/C N/C N/C N/C LBR UB R CE 0R CE 1R CNTRST R VCC GND R/WR OER FT/PIPER GND I/O15R I/O14R I/O13R I/O12R VCC VCC I/O11R The IDT70V9269 is a high-speed 16K x 16 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address in-puts provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 14mm x 20mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 6.42 2 I/O10R I/O9R GND N/C I/O8R N/C N/C I/O7R VCC I/O6R I/O5R I/O4R GND I/O3R VCC I/O2R I/O1R I/O0R GND VCC I/O0L I/O1L GND I/O2L I/O3L GND I/O4L I/O5L I/O6L I/O7L VCC N/C N/C I/O8L N/C VCC I/O9L I/O10L 3752 drw 02 IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A13L A0R - A13R Address I/O0L - I/O15L I/O0R - I/O15R Data Input/Output CLKL CLKR Clock UBL UBR Upper Byte Select LBL LBR Lower Byte Select ADSL ADSR Address Strobe Enable CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPEL FT/PIPER Flow-Through / Pipeline VCC Power GND Ground 3752 tbl 01 Truth Table IRead/Write and Enable Control(1,2,3) OE CLK CE0 CE1 UB LB R/W Upper Byte I/O8-15 Lower Byte I/O0-7 X ↑ H X X X X High-Z High-Z Deselected–Power Down X ↑ X L X X X High-Z High-Z Deselected–Power Down X ↑ L H H H X High-Z High-Z Both Bytes Deselected X ↑ L H L H L DATAIN High-Z Write to Upper Byte Only X ↑ L H H L L High-Z DATAIN Write to Lower Byte Only X ↑ L H L L L DATAIN DATAIN Write to Both Bytes L ↑ L H L H H DATAOUT High-Z Read Upper Byte Only L ↑ L H H L H High-Z DATAOUT Read Lower Byte Only L ↑ L H L L H DATAOUT DATAOUT Read Both Bytes H ↑ L H L L X High-Z High-Z Outputs Disabled MODE 3752 tbl 02 NOTES: 1. "H" = VIH, "L" = V IL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. 6.42 3 IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Truth Table IIAddress Counter Control(1,2) Address Previous Address Addr Used CLK ADS CNTEN CNTRST I/O(3) X X 0 ↑ X X L DI/O(0) Counte r Reset to Address 0 An X An ↑ L(4) X H DI/O(n) External Address Loaded into Counter An Ap Ap ↑ H H H DI/O(p) External Address Blocked—Counter disabled (Ap reused) Ap + 1 ↑ H DI/O(p+1) X Ap (5) H L MODE Counter Enabled—Internal Address generation 3752 tbl 03 NOTES: 1. "H" = VIH, "L" = V IL, "X" = Don't Care. 2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE0, CE1, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB. Recommended Operating Temperature and Supply Voltage(1,2) Grade Commercial Industrial Recommend DC Operating Conditions Symbol Ambient Temperature GND Vcc 0OC to +70OC 0V 3.3V + 0.3V -40OC to +85OC 0V 3.3V + 0.3V Parameter VCC Supply Voltage GND Ground VIH Input High Voltage Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 2.2 ____ V VCC+0.3V (2) V 3752 tbl 04 NOTE: 1. Industrial temperature: for specific speeds, packages and powers contact your sales office. 2. This is the parameter TA. This is the "instant on" case temperature. VTERM(2) Rating Commercial & Industrial Unit Terminal Voltage with Respect to GND -0.5 to +4.6 V -0.3 0.8 V 3752 tbl 05 NOTES: 1. VIL > -1.5V for pulse width less than 10 ns. 2. VTERM must not exceed VCC + 0.3V. Symbol CIN COUT(3) TBIAS Temperature Under Bias -55 to +125 o C TSTG Storage Temperature -65 to +150 o C IOUT DC Output Current 50 Input Low Voltage ____ Capacitance(1) (TA = +25°C, f = 1.0MHz) Absolute Maximum Ratings(1) Symbol VIL (1) Parameter Input Capacitance Output Capacitance Conditions(2) Max. Unit VIN = 3dV 9 pF VOUT = 3dV 10 pF 3752 tbl 07 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. mA 3752 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VCC + 0.3V. 6.42 4 IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V) 70V9269S Symbol Parameter Test Conditions 70V9269L Min. Max. Min. Max. Unit 10 ___ 5 µA 5 µA Input Leakage Current(1) V CC = 3.6V, VIN = 0V to V CC ___ |ILO| Output Leakage Current CE = VIH or CE1 = VIL, VOUT = 0V to V CC ___ 10 ___ VOL Output Low Voltage IOL = +4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ V |ILI| 3752 tbl 08 NOTE: 1. At Vcc < 2.0V input leakages are undefined. DC Electrical Characteristics Over the Operating Temperture and Supply Voltage Range(3,6,7) (VCC = 3.3V ± 0.3V) 70V9269X9 Com'l Only Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Test Condition CEL and CER= VIL, Outputs Disabled, f = fMAX(1) CEL = CER = VIH f = fMAX Version 70V9269X12 Com'l Only 70V9269X15 Com'l Only Typ. (4) Max. Typ.(4) Max. Typ.(4) Max. Unit mA COM'L S L 180 180 260 225 150 150 240 205 130 130 220 185 IND S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ COM'L S L 50 50 75 65 40 40 65 50 30 30 55 35 IND S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ S L 110 110 170 150 100 100 160 140 90 90 150 130 S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ COM'L S L 1.0 0.4 5 3 1.0 0.4 5 3 1.0 0.4 5 3 IND S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ COM'L S L 100 100 160 140 90 90 150 130 80 80 140 120 IND S L ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ mA (1) COM'L CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, IND f=fMAX(1) Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0(2) Full Standby Current (One Port - CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V, Active Port, Outputs Disable d, f = fMAX(1) mA mA mA 3752 tbl 09 NOTES: 1. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. Vcc = 3.3V, T A = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ). 5. CE X = VIL means CE0X = VIL and CE1X = VIH CE X = VIH means CE0X = VIH or CE1X = V IL CE X < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V CE X > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V 'X' represents "L" for left port or "R" for right port. 6. 'X' in part number indicates power rating (S or L). 7. Industrial temperature: for specific speeds, packages and powers contact your sales office. 6.42 5 IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges AC Test Conditions GND to 3.0V Input Pulse Levels Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Figures 1, 2, and 3 Output Load 3752 tbl 10 3.3V 3.3V 590Ω 590Ω DATAOUT DATAOUT 30pF 435Ω 3752 drw 03 3752 drw 04 Figure 2. Output Test Load (For tCKLZ, tCKHZ, tOLZ, and tOHZ ). *Including scope and jig. Figure 1. AC Output Test load. 8 7 5pF* 435Ω - 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance 6 tCD1, tCD2 (Typical, ns) 5 4 3 2 1 0 -1 20 40 60 80 100 120 140 160 180 200 Capacitance (pF) 3752 drw 05 Figure 3. Typical Output Derating (Lumped Capacitive Load). 6.42 6 , IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Tempurature Range (Read and Write Cycle Timing)(3,4,5) (VCC = 3.3V ± 0.3v, TA = 0°C to +70°C) 70V9269X9 Com'l Only Symbol tCYC1 tCYC2 tCH1 Parameter Clock Cycle Time (Flow-Through) Clock Cycle Time (Pipelined) (2) (2) (2) Clock High Time (Flow-Through) (2) Min. Max. 25 ____ 15 ____ 12 ____ 70V9269X12 Com'l Only Min. Max. 30 ____ 20 ____ 12 ____ 70V9269X15 Com'l Only Min. Max. Unit 35 ____ ns 25 ____ ns 12 ____ ns ns 12 ____ 12 ____ 12 ____ tCH2 (2) Clock High Time (Pipelined) 6 ____ 8 ____ 10 ____ ns tCL2 Clock Low Time (Pipelined)(2) 6 ____ 8 ____ 10 ____ ns tR Clock Rise Time ____ 3 ____ 3 ____ 3 ns Clock Fall Time ____ 3 ____ 3 ____ 3 ns 4 ____ 4 ____ 4 ____ ns 1 ____ 1 ____ 1 ____ ns 4 ____ 4 ____ 4 ____ ns 1 ____ 1 ____ 1 ____ ns 4 ____ 4 ____ 4 ____ ns ns tCL1 tF tSA tHA tSC tHC tSW Clock Low Time (Flow-Through) Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time R/W Setup Time tHW R/W Hold Time 1 ____ 1 ____ 1 ____ tSD Input Data Setup Time 4 ____ 4 ____ 4 ____ ns tHD Input Data Hold Time 1 ____ 1 ____ 1 ____ ns tSAD ADS Setup Time 4 ____ 4 ____ 4 ____ ns tHAD ADS Hold Time 1 ____ 1 ____ 1 ____ ns tSCN CNTEN Setup Time 4 ____ 4 ____ 4 ____ ns tHCN CNTEN Hold Time 1 ____ 1 ____ 1 ____ ns tSRST CNTRST Setup Time 4 ____ 4 ____ 4 ____ ns tHRST CNTRST Hold Time 1 ____ 1 ____ 1 ____ ns ____ 12 ____ 12 ____ 15 ns 2 ____ 2 ____ 2 ____ ns 1 7 1 7 1 7 ns tOE tOLZ tOHZ tCD1 tCD2 Output Enable to Data Valid (1) Output Enable to Output Low-Z (1) Output Enable to Output High-Z (2) ____ Clock to Data Valid (Flow-Through) (2) Clock to Data Valid (Pipelined) 20 ____ 25 ____ 30 ns ____ 9 ____ 12 ____ 15 ns ns tDC Data Output Hold After Clock High 2 ____ 2 ____ 2 ____ tCKHZ Clock High to Output High-Z(1) 2 9 2 9 2 9 ns tCKLZ Clock High to Output Low-Z(1) 2 ____ 2 ____ 2 ____ ns Write Port Clock High to Read Data Delay ____ 35 ____ 40 ____ 50 ns Clock-to-Clock Setup Time ____ 15 ____ 15 ____ 20 Port-to-Port Delay tCWDD tCCS ns 70V9269 tbl 11 NOTES: 1. Transition is measured 0mV from Low or High-Impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right when FT/PIPE = V IH. Flow-through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPEX. 4. 'X' in part number indicates power rating (S or L). 5. Industrial temperature: for specific speeds, packages and powers contact your sales office. 6.42 7 IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Flow-through Output on Either Port (FT/PIPEX = VIL)(3) tCYC1 tCH1 tCL1 CLK CE0 tSC tSC tHC tHC (4) CE1 tSB tHB UB, LB tSB R/W (5) ADDRESS tSW tHW tSA tHA An An + 1 tCKHZ Qn DATAOUT tCKLZ An + 3 tDC tCD1 OE An + 2 tHB Qn + 1 (1) tOHZ (1) Qn + 2 (1) tOLZ tDC (1) (2) tOE 3752 drw 06 Timing Waveform of Read Cycle for Pipelined Operation on Either Port (FT/PIPEX = VIH)(3) tCYC2 tCH2 tCL2 CLK CE0 tSC tSC tHC tHC (4) CE1 tSB tSB tHB UB, LB R/W (5) ADDRESS tSW tHW tSA tHA An An + 1 (1 Latency) An + 2 Qn tCKLZ An + 3 tDC tCD2 DATAOUT OE tHB (6) (1) Qn + 1 Qn + 2 (1) tOHZ tOLZ (6) (1) (2) tOE NOTES: 3752 drw 07 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE0 = V IH, CE1 = VIL, UB = VIH, or LB = V IH following the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). 6.42 8 IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of a Multi-device Pipelined Read(1,2) tCH2 tCYC2 tCL2 CLK tSA tHA A0 ADDRESS(B1) tSC tHC CE0(B1) tSC tHC tCD2 tCD2 Q0 DATAOUT(B1) tDC tSA tSC (3) tCD2 Q3 Q1 tDC tCKLZ (3) tCKHZ (3) A6 A5 A4 A3 A2 A1 tSC CE0(B2) tCKHZ tHA A0 ADDRESS(B2) A6 A5 A4 A3 A2 A1 tHC tHC tCKHZ(3) tCD2 DATAOUT(B2) tCKLZ(3) tCD2 Q2 tCKLZ Q4 (3) 3752 drw 08 Timing Waveform of Left Port Write to Flow-through Right Port Read(4,5) CLK L tSW tHW tSA tHA R/W L ADDRESS L tSD DATAIN L NO MATCH MATCH tHD VALID tCCS (6) CLK R tCD1 R/W R ADDRESS R tSW tHW tSA tHA NO MATCH MATCH tCWDD (6) tCD1 DATAOUT R VALID VALID tDC tDC 3752 drw 09 NOTES: 1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V9269 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS (B2) in this situation. 2. UB, LB, OE, and ADS = VIL; CE1(B1) , CE1(B2), R/W, CNTEN, and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-Impedance voltage with the Output Test Load (Figure 2). 4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = V IH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD . If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case. 6.42 9 IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3) tCYC2 tCH2 tCL2 CLK CE0 tSC tHC tSB tHB CE1 UB, LB tSW tHW R/W (4) ADDRESS tSW tHW An tSA tHA An +1 An + 2 An + 4 An + 3 An + 2 tSD tHD DATAIN Dn + 2 tCD2 (2) tCKHZ (1) (1) tCD2 tCKLZ Qn + 3 Qn DATAOUT READ NOP (5) WRITE READ 3752 drw 10 Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3) tCH2 tCYC2 tCL2 CLK CE0 tSC tHC tSB tHB CE1 UB, LB tSW tHW R/W (4) ADDRESS tSW tHW An tSA tHA An +1 An + 2 tSD DATAIN Dn + 3 Dn + 2 tCD2 (2) An + 3 An + 4 An + 5 tHD tCKLZ(1) tCD2 Qn DATAOUT Qn + 4 tOHZ(1) OE READ WRITE READ 3752 drw 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = V IH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 10 IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Flow-through Read-to-Write-to-Read (OE = VIL)(3) tCH1 tCYC1 tCL1 CLK CE0 tSC tHC tSB tHB CE1 UB, LB tSW tHW R/W tSW tHW An tSA tHA (4) ADDRESS An +1 An + 2 An + 4 An + 3 An + 2 tSD tHD DATAIN Dn + 2 tCD1 (2) tCD1 Qn DATAOUT tCD1 tCD1 Qn + 1 tDC tCKHZ (5) NOP READ (1) tCKLZ Qn + 3 tDC (1) READ WRITE 3752 drw 12 Timing Waveform of Flow-through Read-to-Write-to-Read (OE Controlled)(3) tCYC1 tCH1 tCL1 CLK CE0 tSC tHC tSB tHB CE1 UB, LB tSW tHW R/W tSW tHW (4) An tSA tHA ADDRESS An +1 DATAIN (2) DATAOUT An + 2 tSD tHD An + 3 Dn + 2 Dn + 3 tDC tCD1 Qn An + 4 tOE tCD1 (1) tOHZ (1) An + 5 tCKLZ tCD1 Qn + 4 tDC OE READ WRITE READ 3752 drw 13 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or HIgh-impedance) is determined by the previous cycle control signals. 3. CE 0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH . 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 11 IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read with Address Counter Advance (1) tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS tSAD tHAD ADS tSAD tHAD CNTEN tSCN tHCN tCD2 DATAOUT Qx - 1(2) Qn + 2(2) Qn + 1 Qn Qx Qn + 3 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 3752 drw 14 Timing Waveform of Flow-through Read with Address Counter Advance(1) tCH1 tCYC1 tCL1 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tCD1 DATAOUT Qx(2) Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 3752 drw 15 NOTES: 1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = V IH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address, i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks. 6.42 12 IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs) (1) tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL(3) ADDRESS An(7) An + 2 An + 1 An + 4 An + 3 tSAD tHAD ADS CNTEN(7) tSD tHD Dn + 1 Dn DATAIN WRITE EXTERNAL ADDRESS Dn + 1 Dn + 4 Dn + 3 Dn + 2 WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 3752 drw 16 Timing Waveform of Counter Reset (Pipelined Outputs)(2) tCH2 tCYC2 tCL2 CLK tSA tHA (4) An ADDRESS INTERNAL(3) ADDRESS Ax (6) 0 1 An + 1 An + 2 An + 1 An tSW tHW R/W ADS tSAD tHAD CNTEN tSCN tHCN tSRST tHRST CNTRST tSD tHD D0 DATAIN (5) Q1 Q0 DATAOUT COUNTER RESET (6) WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 READ ADDRESS n Qn READ ADDRESS n+1 NOTES: 3752 drw 17 1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 2. CE0, UB, LB = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles are shown here simply for clarification. 7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An + 1’. The transition show indicates the time required for the counter to advance. The ‘An +1’ Address is written to during this cycle. 6.42 13 IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Functional Description Depth and Width Expansion The IDT70V9269 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple Chip Enables allow easier banking of multiple IDT70V9269's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are required with CE0 LOW and CE1 HIGH to re-activate the outputs. The IDT70V9269 features dual chip enables (refer to Truth Table 1) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT70V9269 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 32-bit or wider applications. A14 IDT70V9269 CE0 CE1 CE1 VCC CE1 IDT70V9269 VCC CE1 CE0 CE0 Control Inputs CE0 Control Inputs Control Inputs IDT70V9269 IDT70V9269 Control Inputs 3752 drw 18 Figure 4. Depth and Width Expansion with IDT70V9269 6.42 14 CNTRST CLK ADS CNTEN R/W LB, UB OE IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX A 99 A A Device Type Power Speed Package Process/ Temperature Range Blank I (1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) PRF 128-pin TQFP (PK128-1) 9 12 15 Commercial Only Commercial Only Commercial Only S L Standard Power Low Power Speed in nanoseconds 70V9269 256K (16K x 16-Bit) Synchronous Dual-Port RAM 3752 drw 19 NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. Datasheet Document History 1/12/99: 6/15/99: 8/20/99: 4/4/00: 1/17/01: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Page 14 Added Depth and Width Expansion section Page 4 Deleted note 6 for Table II Fixed Pin Configuration Replaced IDT logo Added FT/PIPE to left port Changed ±200mV to 0mV in notes Page 4 Changed information in Truth Table II Increased storage temperature parameters Clarified TA parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Removed Preliminary status CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 15 for Tech Support: 831-754-4613 [email protected]