Application Note AN 2012-03 V1.1 March 2012 Infineon OptiMOSTMPower MOSFET Datasheet Explanation Infineon Technologies Austria AG Power Management and Multimarket Application Engineer Alan Huang Infineon OptiMOSTM Power MOSFET Datasheet Explanation Application Note AN 2012-03 V1.1 March 2012 Edition 2012-03-16 Published by Infineon Technologies Austria AG 9500 Villach, Austria © Infineon Technologies Austria AG 2011. All Rights Reserved. Attention please! THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMEN-TATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. 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Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. AN 2012-03 Revision History: date (12-03-16) , V1.1 Previous Version: V1.0 Authors: Alan Huang, Power Management & Multimarket We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [[email protected]] 2 Infineon OptiMOSTM Power MOSFET Datasheet Explanation Application Note AN 2012-03 V1.1 March 2012 Table of contents 1 Introduction .................................................................................................................................................... 4 2 Datasheet Parameters ................................................................................................................................... 5 2.1 Power dissipation ............................................................................................................................... 5 2.2 Drain current ...................................................................................................................................... 7 2.3 Safe operating area ........................................................................................................................... 9 2.4 Maximum transient thermal impedance ZthJC ................................................................................... 11 2.5 Typical output characteristics........................................................................................................... 12 2.6 Drain-source on-state resistance as a function of Drain current .....................................................13 2.7 Transfer characteristics .................................................................................................................... 14 2.8 Forward transconductance .............................................................................................................. 15 2.9 Drain-source on-state resistance ..................................................................................................... 17 2.10 Gate threshold voltage ..................................................................................................................... 18 2.11 Capacitances ................................................................................................................................... 19 2.12 Reverse diode characteristics .......................................................................................................... 21 2.13 Avalanche characteristics ................................................................................................................ 23 2.14 Drain-source breakdown voltage ..................................................................................................... 24 2.15 Typical gate charge .......................................................................................................................... 25 2.16 Leakage Currents ............................................................................................................................ 28 2.17 Other important parameters ............................................................................................................. 29 2.17.1 Switching Times ....................................................................................................................... 29 2.17.2 Gate resistance .........................................................................................................................30 2.17.3 Additional maximum ratings ......................................................................................................30 3 Infineon OptiMOSTM Power MOSFET Datasheet Explanation 1 Application Note AN 2012-03 V1.1 March 2012 Introduction A datasheet is the most important tool for the electronics engineer to understand a Power MOSFET device and to fully appreciate its intended functionalities. Due to a great amount of information a datasheet offers, it is sometimes deemed to be complicated and a difficult document to comprehend. Furthermore important parameters can be often missed. This could lead to numerous problems, for example, device failure, PCB redesign, project delay, etc. The document provides a general guideline about how to read and understand a datasheet with all its parameters and diagrams. TM TM This application note describes Infineon’s OptiMOS Power MOSFET datasheets in detail. OptiMOS is the trademark for Infineon’s low voltage (up to 300V) Power MOSFET product line. This document provides background information on each specification parameter and explanation on each of the specification diagrams. It aims to help the designer to acquire a better understanding of the data sheet. The parameters and diagrams mentioned in the datasheet provide a complete picture of a MOSFET. With such information, the designer should be able to understand the device’s intended operation, to determine the operational limits of the device, and to compare quantitatively against different devices. This document explains the interaction between the parameters and the influence of temperature or gate voltage on these parameters. This document is merely aimed to provide clear explanations of the datasheet figures. For design recommendation, please go to www.infineon.com or contact Infineon team. 4 Infineon OptiMOSTM Power MOSFET Datasheet Explanation 2 Application Note AN 2012-03 V1.1 March 2012 Datasheet Parameters Datasheets might be deemed hard to analyze due to its large amount of information in a rather compact format. Instead of reading the datasheet line by line, it is suggested for the reader to look at each topic separately. Thus, this section clearly divides datasheets into smaller segments in order to avoid causing confusion for the reader. Each sub-section presents a single datasheet diagram and its relevant parameters. Note: This document uses diagrams and parameters from IPP029N06N datasheet rev2.0 as examples. For TM TM the latest version of Infineon OptiMOS datasheets please refer to our OptiMOS (20V – 300V) webpage. 2.1 Power dissipation The first diagram included in the datasheet is the power dissipation versus case temperature chart (Figure1). At a certain case temperature, the maximum allowable power dissipation is governed as illustrated. Power dissipation Ptot=f(TC) Figure 1 Power dissipation Ptot = f(TC) There are two power dissipation parameters listed in the datasheet – total junction-to-case and total junctionto-ambient power dissipation. These two numbers can be obtained using eq. (1) and (2).The junction-to-case thermal resistance is material and dimension dependent. With increasing case temperature, the allowable power dissipation decreases 5 Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation (1) Ptot (TC ) = (2) Ptot (TA ) = V1.1 March 2012 T j − TC RthJC T j − TA RthJA Using these examples, the maximum power dissipation with the highest allowable temperature increase can be calculated. Eq. (3) demonstrates how the numbers in the example (as in Figure 2) were derived. Ptot (TC ) max (3) (175 − 25) K = = 136W 1.1 K W Ptot (T A ) max = (175 − 25) K = 3.0W K 50 W Note: The temperature difference in unit K is the same as in unit °C. Parameter Power dissipation 2) Symbol Conditions Ptot Value TC=25 °C 136 TA=25 °C, RthJA=50 K/W2) 3.0 Unit W Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 μm thick) copper area for drain connection. PCB is vertical in still air. Figure 2 Maximum ratings for Ptot (datasheet) The junction-to-ambient thermal resistance is layout dependent; therefore, in most cases, a footnote regarding the junction-to-ambient thermal resistance is included. It specifies the condition where the specified RthJA rating is estimated. 6 Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation 2.2 V1.1 March 2012 Drain current The datasheet specifies the maximum continuous drain current (ID) under different operating conditions and the pulsed drain current (ID,pulse) as in Figure 3. The maximum pulsed drain current is specified at 4 times the maximum continuous drain current. As the pulse width increases, the pulsed drain current rating decreases due to the thermal characteristics of the device. This can be clearly observed in the safe operating area diagram in Section 2.3. ID Continuous drain current ID,pulse Pulsed drain current 2) VGS=10 V, TC=25 °C 100 VGS=10 V, TC=100 °C 100 VGS=10 V, TC=25 °C, RthJA =50K/W 2) 24 TC=25 °C A 400 Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Figure 3 Maximum ratings for ID (datasheet) When the maximum continuous drain current depends solely on the maximum power dissipation (Section 2 2.1), the maximum ID would be defined by the rearranged Power Law (P = I *R). Substituting P in eq. (1) derives eq. (4), where the junction-to-case temperature difference (Tj - TC), thermal resistance (RthJC), and on-state resistance at maximum junction temperature (RDS(on),Tj(max)) come into play. See Section 2.9 for the temperature dependency of the on-state resistance. T j − TC (4) I D (TC ) = RthJC I D (25°C ) = RDS ( on ),Tj (max) (175 − 25) K 0.8 K W = 169 A 0.0066Ω Note: The temperature difference in unit K is the same as in unit °C. However, in reality, additional boundary conditions, governed by bond wire diameter, chip design and assembly, limit the maximum continuous drain current as illustrated in Figure 4. At TC = 25°C, ID is capped at 100 A instead of 169 A as calculated in eq. (4). This diagram illustrates that at low TC, maximum ID stays constant; at high TC, it rolls off with acceleration until reaching zero at TC = Tj(max). Note: This diagram only presents the limit of the continuous drain current limit. For pulsed current, refer to the safe operating area diagram in Section 2.3. 7 Infineon OptiMOSTM Power MOSFET Datasheet Explanation Drain current ID=f(TC); VGS≥10 V Figure 4 Drain current ID = f(TC) 8 Application Note AN 2012-03 V1.1 March 2012 Infineon OptiMOSTM Power MOSFET Datasheet Explanation 2.3 Application Note AN 2012-03 V1.1 March 2012 Safe operating area Figure 5 shows the drain current (ID) as a function of the drain-source voltage (VDS) with different pulse lengths. This is one of the most complicated but important figure that should not be ignored in the datasheet. This section briefly describes each region of operation and its boundary limits. In complementary to this short section, Infineon also provides a comprehensive application note regarding this topic - Linear Mode Operation and Safe Operating Diagram of Power MOSFETs, where details regarding the linear mode operation and the SOA diagram are discussed. Safe operating area ID=f(VDS); TC=25 °C; D=0 parameter: tp Figure 5 Safe operating area ID=f(VDS) Note: The SOA diagram is defined for single pulses. Mathematically, the duty cycle of a single pulse is equivalent to zero (D=0) as the period (T) is infinite. There are several limitations in this diagram and labels (A) to (E) are used to explain the boundary limits using the 100 µs curve as an example. A) The top line is a limit of the maximum pulsed drain current. B) This area is limited by the on-state resistance RDS(on) at maximum junction temperature. 9 Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation V1.1 March 2012 C) At fixed TC, the device is limited by the constant power line in this area. Depending on the applied power pulse width, the maximum power loss varies according to the thermal impedance variation. Next section (Section 2.4) discusses about maximum transient thermal impedance at a different pulse length. D) In linear mode operation, there is a risk of getting hot spots at low gate-source voltages due to thermal run away. This effect becomes more important for latest trench technologies with high current densities, where the “zero temperature coefficient” point of the transfer characteristic is shifted to higher drain currents. More information can be found in the application note mentioned above Linear Mode Operation and Safe Operating Diagram of Power MOSFETs With the hot spot effect for higher VDS and longer pulse times considered, the SOA characteristic has a different slope in this region (eq. (5)). (5) E) I D (VDS ) = T j − TC VDS * Z thJC The maximum breakdown voltage (V(BR)DSS), which is determined by the technology, limits the SOA curve on the right hand side. 10 Infineon OptiMOSTM Power MOSFET Datasheet Explanation 2.4 Application Note AN 2012-03 V1.1 March 2012 Maximum transient thermal impedance ZthJC Thermal impedance (Zth) consists of two components – thermal resistance (Rth) and thermal capacitance (Cth). RthJC is the thermal resistance from the junction of the die to the case. The heat through this path is generated by the power loss in the device itself. This parameter is directly linked to the temperature that the chip reaches relative to the case. Transient thermal impedance (ZthJC) takes also the heat capacity (CthJC) of the device into account. It is used to estimate the temperature resulted from transient power loss. Max. transient thermal impedance ZthJC=f(tp) parameter: D=tp/T Figure 6 Maximum transient thermal impedance ZthJC=f(tp) Figure 6 shows that for each specified duty cycle (D=tp/T), the variation of the thermal resistance (ZthJC) as a function of the loading time tp (pulse width). To dissipate the heat out of the device, it has to pass several different layers of its characteristic thermal resistances and capacitances. As a result, depending on the pulse width, either the thermal resistance or the thermal capacitance dominates the behavior of the device. The increase of the junction temperature can be calculated as shown in eq. (6). Before power pulse is applied, Tj,start is equal to TC at thermal equilibrium. 11 Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation (6) V1.1 March 2012 T j = T j ,start + ∆T j = T j ,start + Z thJC (t P , D) ∗ Ptot The maximum of RthJC is also listed in the table section of the datasheet as in Figure 7. Thermal characteristics Thermal resistance, junction - case Figure 7 2.5 RthJC bottom - - 1.1 K/W Thermal characteristics Typical output characteristics Typical output characteristics graph, Figure 8, illustrates the drain current ID as a function of the drain-source voltage VDS at given gate-source voltages VGS and chip temperature Tj of 25 °C. Typ. output characteristics ID=f(VDS); Tj=25 °C parameter: VGS Ohmic Region Figure 8 Typical output characteristics ID=f(VDS) 12 Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation V1.1 March 2012 For optimal efficiency, the MOSFET should be operated in the “ohmic” region, which is shown in Figure 8 (Note that this diagram includes current range up to the maximum pulsed current limit). This boundary line between ohmic and saturation region is defined by VDS = VGS – VGS(th). At any given gate-source voltage, the drain current of the MOSFET saturates beyond the ohmic region. As the operating point goes into the saturation region, any further increase in drain current leads to a significant rise in drain-source voltage (linear operation mode) and as a result conduction loss increases. In this case, if the power dissipation is not limited, the device may fail. Gate-source voltage (VGS) is deterministic to the MOSFET’s output characteristics as shown in the diagram. The allowable range of VGS is specified in the table section of the datasheet as shown in Figure 9. The effects of gate-source voltage on drain-source on-state resistance will be discussed in the Section 2.6. VGS Gate source voltage Figure 9 2.6 ±20 V Gate source voltage limit Drain-source on-state resistance as a function of Drain current In Figure 10, for each gate-source voltage, the drain source on-state resistances over drain current curve is directly calculated from the typical output characteristic diagram (Figure 8a) using Ohms Law, eq. (7). (7) RDS ( on ) ( I D ) = VDS ID Notice that VGS plays an important role in this diagram. The on-resistance curves change tremendously while a different level of VGS is applied. To fully turn on a device, a VGS of 10V is required. For normal level devices, 10V is recommended for efficiency-optimized low drain-source on-state resistance. For logic level devices, shifted RDS(on) curves (Figure 8b) make a lower-than-10V VGS acceptable for fast switching applications, whereas the conduction loss due to higher RDS(on) is less critical. An example application could be synchronous rectification at low load. 13 Infineon OptiMOSTM Power MOSFET Datasheet Explanation Application Note AN 2012-03 V1.1 March 2012 b) Typ. drain-source on resistance a) Typ. drain-source on resistance RDS(on)=f(ID); Tj=25 °C parameter: VGS Figure 10 2.7 RDS(on)=f(ID); Tj=25 °C parameter: VGS Typical drain-source on-state resistance RDS(on)=f(ID) for a) normal level device and b) logic level device (BSC010N04LS) Transfer characteristics This diagram shows the typical drain current as a function of the applied gate-source voltage. Normally the graphs at different junction temperatures are given. For example, Figure 11 has one curve at 25°C and the other at 175°C. All the graphs should intersect at one point, the so-called temperature stable operating point. When the gate-source voltage applied to the MOSFET is below this point (in the example VGS < 5.2V), the MOSFET operates with a positive temperature coefficient, meaning with increasing junction temperature the drain current will also increase. Operating at this condition with constant VGS should be avoided due to the possibility of thermal runaway. Beyond the temperature stable operating point the temperature coefficient is negative, meaning that with increasing junction temperature the drain current decreases. The MOSFET self-limits its current handling capability at high temperatures. Operating in this region is generally safe as long as the junction temperature stays within specification. Note: For current level higher than the specified maximum continuous conduction current, only pulsed currents are allowed. 14 Infineon OptiMOSTM Power MOSFET Datasheet Explanation Application Note AN 2012-03 V1.1 March 2012 Typ. transfer characteristics ID=f(VGS); |VDS|>2|ID|RDS(on)max parameter: Tj Figure 11 Typical transfer characteristics ID=f(VGS) To approximate the maximum or minimum rating of this characteristic the curves can be moved in parallel according to the min-max ratings of the threshold voltage (+/- 1V for normal level devices). 2.8 Forward transconductance Transconductance (gfs) is a measure of sensitivity of the drain current to the variation of the gate-source voltage. Figure 12 shows the typical forward transconductance as a function of drain current at junction temperature of 25°C. 15 Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation V1.1 March 2012 Typ. forward transconductance gfs=f(ID); Tj=25 °C Figure 12 Typical forward transconductance gfs=f(ID) The forward transconductance (gfs) can be calculated from the typical transfer characteristics diagram from Figure 11 using eq. (8). (8) g fs ( I D ) = ∆I D ∆VGS VDS The minimum and typical values of gfs at the test current are listed in Figure 13. Transconductance Figure 13 gfs |VDS|>2|ID|RDS(on)max, ID=100 A Transconductance in Static Characteristics section 16 80 160 - S Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation 2.9 V1.1 March 2012 Drain-source on-state resistance The drain-source on-state resistance is one of the key parameters of a MOSFET. In the datasheet there are two sections dealing with this parameter. In the table section, the typical and maximum ratings at room temperature are listed as in Figure 14. These values are determined during production testing at the specified conditions. For a surface-mount device (SMD), the resistance is measured between the source pin and the backside drain contact of the device. For a through-hole package, the RDS(on) is specified between the drain and source pins at a defined soldering point (approx. 4.5 mm lead lengths for TO-220), which results in an additional 0.3 mΩ of parasitic resistance. Drain-source on-state resistance Figure 14 RDS(on) VGS=10 V, ID=100 A - 2.7 2.9 VGS=6 V, ID=25 A - 5.4 - mΩ Drain to Source on-state resistance In addition to the table, the datasheet contains a diagram of the on-state resistance as a function of the junction temperature (Figure 15). The higher the junction temperature, the higher the RDS(on) will be. Due to this positive temperature coefficient, it is possible to use multiple devices in parallel. Note that typical and maximum RDS(on) values are shown in the diagram. Drain-source on-state resistance RDS(on)=f(Tj); ID=100 A; VGS=10 V Figure 15 Typical drain-source on-state resistance RDS(on)=f(Tj) 17 Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation V1.1 March 2012 To calculate the dependency of the junction temperature, the following formula is used: (9) RDS ( on ) (T j ) = RDS ( on ), 25°C ⋅ (1 + α is a technology dependent constant. For OptiMOS RDS(on) approximation. TM α 100 ) T j − 25°C Power MOSFET, α value of 0.4 can be used for 2.10 Gate threshold voltage The gate threshold voltage defines the required gate-source voltage at a specified drain current. During the production, the threshold voltage is measured at room temperature with VDS = VGS and test drain currents in the µA range. The minimum, typical, and maximum ratings are specified in the table as shown in Figure 16. VGS(th) Gate threshold voltage Figure 16 VDS=VGS, ID=75 µA 2.0 2.8 3.6 V Threshold voltage The threshold voltage decreases with increasing junction temperature. This dependency at typical condition as specified in the table section is illustrated in the Figure 17. Typ. gate threshold voltage VGS(th)=f(Tj); VGS=VDS Figure 17 Typical gate threshold voltage VGS(th)=f(Tj) 18 Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation V1.1 March 2012 2.11 Capacitances The capacitances of the MOSFETs are defined both in the table and the diagram sections of the data sheet. The table specifies the ranges for the capacitances (Figure 18), and the diagram shows the dependencies of the drain-source voltage on the capacitances (Figure 19). The gate-source, gate-drain, and drain-source capacitances cannot be measured directly; however, they can be calculated from the measurable input, output, and reverse transfer capacitances. The three equations (10) below describe the relationships among them. C iss = C GS + C GD (10) C oss = C DS + C GD C rss = C GD Dynamic characteristics Input capacitance Ciss Output capacitance Coss Reverse transfer capacitance Crss Figure 18 VGS=0 V, VDS=30 V, f=1 MHz Dynamic characteristics: capacitances 19 - 4100 - - 980 - - 39 - pF Infineon OptiMOSTM Power MOSFET Datasheet Explanation Application Note AN 2012-03 V1.1 March 2012 In the diagram section of the datasheet, the typical capacitances as a function of the drain-source voltage are defined. Clear dependencies of the voltages are shown for reverse (Crss) and output (Coss) capacitances. This is due to the change in the space charge region during the switching transition of the MOSFET Typ. capacitances C=f(VDS); VGS=0 V; f=1 MHz Figure 19 Capacitance C=f(VDS) 20 Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation V1.1 March 2012 2.12 Reverse diode characteristics The characteristics of the MOSFET’s body diode are given both in the table and the diagram sections. In the table section, as in Figure 20, the minimum, typical and the maximum values of the diode parameters are given. Reverse Diode Diode continuous forward current IS Diode pulse current IS,pulse Diode forward voltage VSD Reverse recovery time trr Reverse recovery charge Qrr Figure 20 TC=25 °C VGS=0 V, IF=100 A, Tj=25 °C VR=30 V, IF=100 A, diF/dt=100 A/µs - - 120 A - - 480 - 1.0 1.2 V - 37 - ns - 44 - nC Diode characteristics • Diode continuous forward current: The maximum permissible DC forward current of the body diode at the specified case temperature TC =25°C, which is normally equal to the MOSFET’s continuous current limit. • Diode pulse current: The maximum permissible pulsed forward current of the inverse diode at the specified case temperature TC =25°C, which is normally equal to the MOSFET’s pulse current limit. • Diode forward voltage: The source-to-drain voltage during diode’s on-state (MOSFET off-state) at test diode forward current (IF), zero gate-source voltage (VGS) and junction temperature (Tj) of 25°C. • Reverse recovery time: The time needed for the reverse recovery charge to be removed. The graphical explanation of trr is given in Figure 21. • Reverse recovery charge: The charge stored in the diode during its on-state. This charge needs to be completely removed immediately following the diode conduction period before the diode’s blocking capability resumes as shown in Figure 21. The higher the switching rate of the current (di/dt on the order of 100A/µs or more), the higher the reverse recovery charge. The graphical explanation of Qrr is also given in Figure 21. 21 Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation V1.1 March 2012 Figure 21 demonstrates that during device turn-on, the diode forward current (IF) drops from the on-state drain current (ID(on)) to beneath zero. IF then recovers back to zero before the drain-source voltage (VDS) starts to decrease (discharging of Coss). Reverse recovery occurs during the time IF is below zero, and the charge (Qrr) can be approximated using the area between IF negative and the zero current line. VDD ID(on)+Irr ID(on) Qrr ID VDS Qrr ID(on)-Irr Figure 21 IF trr Explanation of Qrr and trr 22 Infineon OptiMOSTM Power MOSFET Datasheet Explanation Application Note AN 2012-03 V1.1 March 2012 Figure 22 illustrates the typical diode forward currents, IF, of the functions of source-drain voltages, VSD, at junction temperatures, Tj, of 25°C and 175°C. Forward characteristics of reverse diode IF=f(VSD) parameter: Tj Figure 22 Typical forward diode characteristics IF=f(VSD) 2.13 Avalanche characteristics The dependence of the pulsed avalanche current IAV on the time in avalanche tAV is presented in Figure 23. Operating MOSFET under the conditions below the curve is allowed with consideration of the maximum junction temperature. This characteristic is bounded by the total avalanche energy of a pulse. The longer the avalanche pulse, the lower the maximum allowed avalanche current. This figure also includes multiple curves for different junction temperatures at the start of the avalanche event. It shows that with higher temperature, the avalanche capability decreases. 23 Infineon OptiMOSTM Power MOSFET Datasheet Explanation Application Note AN 2012-03 V1.1 March 2012 Avalanche characteristics IAS=f(tAV); RGS=25 Ω parameter: Tj(start) Figure 23 Avalanche characteristics IAS=f(tAV) The table section of the datasheet provides the maximum single-pulse avalanche energy at a given avalanche current and the maximum allowable single-pulse current in avalanche. Avalanche energy, single pulse Figure 24 EAS ID=100 A, RGS=25 Ω 110 mJ Avalanche energy and current 2.14 Drain-source breakdown voltage The diagram in Figure 25 shows the linear temperature dependence of the typical minimum value of the drain-to-source breakdown voltage over the complete allowable temperature range (-55°C…+175°C). The table as shown in Figure 26 gives the minimum value of the breakdown voltage at 25°C. 24 Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation V1.1 March 2012 Drain-source breakdown voltage VBR(DSS)=f(Tj); ID=1 mA Figure 25 Drain-source breakdown voltage VBR(DSS)=f(Tj) Drain-source breakdown voltage Figure 26 V(BR)DSS VGS=0 V, ID=1 mA 60 - - V Drain-source breakdown voltage VBR(DSS)=f(Tj) 2.15 Typical gate charge Figure 27 includes two diagrams: 1) typical gate charge diagram and 2) gate charge waveform. The typical gate charge diagram shows the typical variation of the requisite gate charge to switch on a MOSFET at given gate-source voltages and drain-source supply voltages (Vdd). The on-state current is given as a parameter. 25 Infineon OptiMOSTM Power MOSFET Datasheet Explanation Application Note AN 2012-03 V1.1 March 2012 As indicated in gate charge waveform, the gate charge (Qg) comprises the gate-source charge (Qgs), the gate-drain charge (Qgd), and the charge required to increase VGS from the plateau to the desired VGS level. Qgs is the charge required for charging the gate-source capacitance (CGS) to the plateau level. During this period, the drain current (ID) rises up to the load value after the gate threshold voltage (Vgs(th)) has been reached. The drain-source voltage (VDS) behaves differently based on different loads. For resistive loads, the drain-source voltage falls simultaneously with the rise of the drain current. For inductive loads, VDS starts falling after the drain current reaches the load level. Before the voltage VDS falls to its on-state value (VDS = RDS(on) *ID), the gate-to-drain capacitance (CGD), the Miller capacitance, has to be discharged. This component is defined as the gate-to-drain charge (Qgd). Qgs and Qgs are not sufficient to fully switch on the transistor, because the drain-source on-state resistance is not yet minimized. Only with a charge corresponding to a full gate-source voltage (typically VGS = 10 V for both normal level and logic level MOSFETs), the full turn-on resistance is reached, and thus static loss is optimized. The complete gate-charge waveform changes with the drain-source voltage level (or the supply voltage level). The parameters relevant to gate charge are also listed in the table section as shown in Figure 28. Note: The plateau level is not fixed. It varies with load conditions. 26 Infineon OptiMOSTM Power MOSFET Datasheet Explanation Typ. gate charge Gate charge waveforms VGS=f(Qgate); ID=100 A pulsed parameter: VDD Figure 27 Typical gate charge VGS=f(Qgate) and gate charge waveforms 27 Application Note AN 2012-03 V1.1 March 2012 Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation V1.1 March 2012 Gate Charge Characteristics5) Gate to source charge Qgs - 20 - Gate charge at threshold Qg(th) - 11 - Gate to drain charge Qgd - 11 - Switching charge Qsw - 19 - Gate charge total Qg - 56 - Gate plateau voltage Vplateau - 4.8 - V Gate charge total, sync. FET Qg(sync) VDS=0.1 V, VGS=0 to 10 V - 49 - nC Output charge Qoss VDD=30 V, VGS=0 V - 65 - Figure 28 VDD=30 V, ID=100 A, VGS=0 to 10 V nC Gate charge and plateau voltage 2.16 Leakage Currents There are two types of leakage currents specified for a MOSFET (Figure 29): 1) IDSS is the drain-source leakage current at a specified drain-source voltage (typically the minimum drain-source breakdown voltage) and at VGS = 0V. 2) IGSS is the gate-source leakage current at a specified gate-source voltage (typically the maximum gate-source voltage) and at VDS = 0V. Zero gate voltage drain current Gate-source leakage current Figure 29 IDSS IGSS VDS=60 V, VGS=0 V, Tj=25 °C - 0.5 1 VDS=60 V, VGS=0 V, Tj=125 °C - 10 100 VGS=20 V, VDS=0 V - 10 100 Leakage Currents 28 µA nA Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation V1.1 March 2012 2.17 Other important parameters 2.17.1 Switching Times Figure 30 shows the switching time parameters listed in the table section of the datasheet. Turn-on delay time td(on) Rise time tr Turn-off delay time td(off) Fall time tf Figure 30 VDD=30 V, VGS=10 V, ID=100 A, RG=3 Ω - 17 - - 15 - - 30 - - 8 - ns Switching Times The turn-on time (ton) of a MOSFET is the sum of the turn-on delay time (td(on)) and the rise time (tr). td(on) is measured between the 10% value of the gate-source voltage and the 90% value of the drain-source voltage. tr is measured between the 90% value and the 10% value of the drain-source voltage. The turn-off time (toff) of a MOSFET is the sum of the turn-off delay time (td(off)) and the fall time (tf). td(off) is measured between the 90% value of the gate-source voltage and the 10% value of the drain-source voltage. tf is measured between the 10% value and the 90% value of the drain-source voltage. Figure 31 graphically defines the above mentioned parameters. Figure 31 Definition of switching times Note: this diagram is used for definition only and the real-life waveforms do not necessary look alike due to different application conditions. For a better representation of the switching waveform, please refer to gate charge waveform in Figure 27. 29 Application Note AN 2012-03 Infineon OptiMOSTM Power MOSFET Datasheet Explanation V1.1 March 2012 2.17.2 Gate resistance Internal gate resistance is also listed in the datasheet as in Figure 32. Gate resistance Figure 32 RG - 1.3 - Ω Gate resistance 2.17.3 Additional maximum ratings The maximum ratings section of the datasheet also lists operating and storage temperature and the IEC climate category as in Figure 33. Operating and storage temperature Tj, Tstg -55 ... 175 IEC climatic category; DIN IEC 68-1 Figure 33 55/175/56 Additional maximum ratings 30 °C