ISL837030, ISL83740 ® Datasheet FN8013.5 May 2002 Modem Reference Designs Features • Programmable modulation Both: QPSK, 8PSK, 16QAM, 32QAM ISL83740 only: 64QAM, 128QAM The ISL837030 and ISL83740 Broadband Wireless Modem Reference Designs support a wide range of modulation orders and symbol rates.* • Flexible data rates ISL83740: up to 238Mbps ISL837030: up to 160Mbps In both Reference Designs, sophisticated coding, equalization, and symbol recovery techniques are employed, resulting in robust wireless link performance. • Programmable symbol rates The ISL837030 and ISL83740 Reference Designs support high-capacity digital microwave radios with data rates up to 238Mbps (ISL83740) and 160Mbps (ISL837030). They provide a flexible, high performance, economical solution for fixed wireless applications. • Reed Solomon (RS) encoding/decoding • Concatenated coding using RS and PTCM inner code • FCC and ETSI spectral mask compliance • Powerful equalization * Differences between the ISL837030 and ISL83740 are marked in text as needed. Also see Release Notes on page 25. Includes • Sample ISL87060MIK Modulator and ISL87060DIK Demodulator Chip Sets for development and test. Benefits • Eliminates the need to develop custom ASICs • Optimizes wireless link capacity and Bit Error Rate (BER) performance • Complete Manufacturing Documentation Package: Bill of Materials, Schematics, PCBA Fabrication Files, including Gerber Files. • Enables rapid prototyping and compliance testing • Test Documentation. • Proven technology • Embedded Monitor and Control Software provides comprehensive setup and test capabilities. Accepts commands in binary or ASCII format. • Optional Evaluation Kit supports demo requirements, performance evaluation, and lab testing Optional Evaluation Kit Modem Digital/Power Connector (P2) The modem PCBA is mounted on an Evaluation Platform, allowing the modem to be set up and tested in a standard lab environment. Includes VHF and L-band IF Interfaces and a sophisticated Graphical User Interface for Windows operating systems. (ISL83700EVAL/ISL83740EVAL) Data ISL87060MIK Modulator/ Encoder Differential Baseband Outputs LPF DAC Level TrimDAC ASYNC Serial Offset Baseband Loopback Controller Modem PCBA FLASH Data ISL87060DIK Demodulator/ Decoder Decimating Matched Filter ADC LPF Differential Baseband Inputs FIGURE 1 Simplified Block Diagram 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved CommLink™ is a trademark of Intersil Americas Inc. ISL837030, ISL83740 CONTENTS Functional Description . . . . . . . . . . . . . . . . . . . . . . . . 3 Modulator Functions . . . . . . . . . . . . . . . . . . . . . . 5 1. ISL87060MIK Modulator ASSP . . . . . . . 5 2. Digital to Analog Converter (DAC) . . . . . 5 3. Low Pass Filter (LPF) . . . . . . . . . . . . . . 5 4. Rate Exchange . . . . . . . . . . . . . . . . . . . 5 Demodulator Functions . . . . . . . . . . . . . . . . . . . 5 1. Low Pass Filter (LPF) . . . . . . . . . . . . . . 5 2. ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. FPGA Decimating Filter . . . . . . . . . . . . . 5 4. ISL87060DIK Demodulator ASSP . . . . . 5 5. Baseband Loopback . . . . . . . . . . . . . . . 5 6. Automatic Gain Control (AGC) . . . . . . . . 6 The Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Monitor and Control Software . . . . . . . . . . . . . . 6 Performance Specifications . . . . . . . . . . . . . . . . . . . . 7 Modem Parameters . . . . . . . . . . . . . . . . . . . . . . 7 Modulation, Inner Code Rates, and Ranges . . . 7 Modulator Performance Specifications . . . . . . . 8 Modulator Input Requirements . . . . . . . . . . . . . . 8 Modulator Output Electrical Specifications . . . . . 8 Demodulator Input Requirements . . . . . . . . . . . 9 Demodulator Input Electrical Specifications . . . . 9 Demodulator Performance Specifications . . . . 10 BER Performance (Typical) . . . . . . . . . . . . . . . 10 Controller Parameters . . . . . . . . . . . . . . . . . . . 11 Environmental & Physical Specifications . . . . . . . . . 12 Physical Interface Definition . . . . . . . . . . . . . . . . . . . 13 80-Pin Digital/Power Connector . . . . . . . . . . . . 14 Power Supply Signals . . . . . . . . . . . . . . . 15 M&C Port Signals . . . . . . . . . . . . . . . . . . . 15 Modulator Data Interface Signals . . . . . . . 15 Demodulator Data Interface Signals . . . . 16 Miscellaneous Signals . . . . . . . . . . . . . . . 17 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . 17 8-Pin Baseband Connectors . . . . . . . . . . . . . . 18 Data Timing and Packet Definition . . . . . . . . . . . . . . 19 Modulator Data Input Timing . . . . . . . . . . . . . . 19 Modulator Packet Definition . . . . . . . . . . . . . . . 19 Demodulator Data Output Timing . . . . . . . . . . 20 Demodulator RS Data Packet Definition . . . . . 20 AGC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . 22 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Support Related Documentation . . . . . . . . . . . . . . . . . . . . . . 25 Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . 25 LIST OF FIGURES 1. Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Modem Printed Circuit Board Assembly (PCBA) . . . . . . . . . . . . 4 4. Acquisition/Tracking Range at Low Baud Rates . . . . . . . . . . . 10 5. Modem PCBA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6. Digital/Power Connector Pin Configuration . . . . . . . . . . . . . . . 14 7. Modulator Connector Pin Configuration . . . . . . . . . . . . . . . . . . 18 8. Demodulator Connector Pin Configuration . . . . . . . . . . . . . . . 18 9. Modulator Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10. Modulator Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11. Demodulator Data Output Timing . . . . . . . . . . . . . . . . . . . . . 20 12. Demodulator Data Packet Definition . . . . . . . . . . . . . . . . . . . 20 13. AGC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 14. Modem PCBA Mechanical Dimensions (Top View) . . . . . . . . 22 15. Modulator Baseband Interface to ISL83740EVAL/ISL83700EVAL Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 16. Unbalanced Demodulator Baseband Interface, Shorter Runs 24 17. Unbalanced Demodulator Baseband Interface, Longer Runs 24 Ordering Information PART NUMBER DESCRIPTION ISL83740REF-CD ISL83740 Reference Design (QPSK, 8PSK, 16QAM, 32QAM, 64QAM, 128QAM) ISL837030REF-CD ISL837030 Reference Design (QPSK, 8PSK, 16QAM, 32QAM) ISL837030KIT-xxx Kit versions supply sample chips in lots of 24 to 120, in 24-unit increments. Applies to either Reference Design. ISL83740EVAL ISL83740 Evaluation Kit (QPSK, 8PSK, 16QAM, 32QAM, 64QAM, 128QAM) ISL83700EVAL ISL837030 Evaluation Kit (QPSK, 8PSK, 16QAM, 32QAM) ISL87060MIK Modulator Chip ISL87060DIK Demodulator Chip All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 7585 Irvine Center Drive Suite 100 Irvine, CA 92618 TEL: (949) 341-7000 FAX: (949) 341-7123 FN8013.5 Intersil Corporation 2401 Palm Bay Rd. Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7946 2 EUROPE Intersil Europe Sarl Ave. William Graisse, 3 1006 Lausanne Switzerland TEL: +41 21 6140560 FAX: +41 21 6140579 ASIA Intersil Corporation Unit 1804 18/F Guangdong Water Building 83 Austin Road TST, Kowloon Hong Kong TEL: +852 2723 6339 FAX: +852 2730 1433 ISL837030, ISL83740 Functional Description . The modem PCBA architecture implements a complete baseband transmit and receive function: Intersil’s broadband wireless modem devices are fully integrated and support a wide range of modulation orders and symbol rates. Sophisticated coding, equalization, and symbol recovery techniques are employed to enable robust wireless link performance. 1. Modulator Function Converts byte-wide parallel data, encodes and digitizes it, and generates a differential baseband analog signal. This signal can then be up-converted to any IF/RF frequency the user requires. The complete modem Printed Circuit Board Assemblies (PCBAs) with standard hardware and software interfaces enable equipment manufacturers to rapidly integrate Intersil modem functionality into their system products. 2. Demodulator Function Accepts a differential analog baseband signal. Filters, decodes, corrects, and converts it to byte-wide digital data and clock. The ISL837030 and ISL83740 Modem Reference Designs provide a flexible, high performance, economical solution for fixed wireless applications. The modem design provides an off-the-shelf solution for users interested in easily integrating a complete modem into their products. 3. Controller Incorporates everything necessary to control and monitor the modem. 10 External Sync ISL87060MIK Modulator/ Encoder Data Input Byte Clock 2-1 Mux 10 200 Msps DAC Passive LPF 10 200 Msps DAC Passive LPF Modulator Baseband Connector I Data Q Data 10 2-1 Mux +3.3V +5V Rate Exchange Sample Clock FPGA -12V Q Level/Bal I Level/Bal VCO ASYNC Serial Q Offset Controller FLASH 512k X 16 Digital AGC Analog AGC I Offset TrimDAC Baseband Loopback XO AGC DAC Clock PLL Modem PCBA AGC Packet Sync 8 10 ISL87060DIK Demodulator/ Decoder Data Output Data Clock I Data 10 Q Data Data Flag 10 FPGA Decimating Matched Filter 100 Msps ADC Passive LPF 100 Msps ADC Passive LPF 8 FIGURE 2 Functional Block Diagram FN8013.5 3 Demodulator Baseband Connector Digital/Power Connector +12V ISL837030, ISL83740 Functional Description D1 Controller FPGA D4 Rate Exchange D3 ISL87060DIK Demodulator FLASH Memory ISL87060MIK Modulator FPGA Decimating Matched Filter D5 D6 MUX MUX DAC MUX DAC MUX Trim DAC ADC FIGURE 3 Modem Printed Circuit Board Assembly (PCBA) LED INDICATORS D1 Controller Status D3 Modem Ready D4 PLL Lock Detect D5 Alarm IRQ D6 Demod Lock FN8013.5 4 LIGHT INDICATORS Blinking indicates controller is functional. Solid off or on indicates not functional. Light on indicates modem is ready to accept user commands. Equivalent to the MODEM_RDY signal on the interface connector. Light on indicates that the modulator rate exchange has successfully locked to the interface input byte clock. Light on signals active alarm condition. Equivalent to the IRQ signal on the interface connector. Light on indicates that the demodulator has successfully locked to the input baseband signal. ISL837030, ISL83740 Functional Description Modulator Functions Demodulator Functions The modulator accepts byte-wide parallel data, encodes it, digitizes it, and produces a balanced analog signal output. This signal can then be up-converted to whatever RF/IF frequency the application requires. It consists of four functions: The demodulator accepts differential analog baseband I and Q signals, then filters, decodes, corrects, and converts them to byte-wide digital data and clock. It consists of six functions: 1. ISL87060MIK Modulator ASSP The modulator ASSP provides a digital representation of a modulated analog signal. The chip accepts byte-wide TTL data and applies: • Energy Dispersal • Reed-Solomon Forward Error Correction (FEC) • Convolutional Interleaving • Symbol Generation for various modulation formats with or without Convolutional Coding • Pulse Shaping • Tuning The digital output from the ASSP consists of eight 10-bit ports, four for I and four for Q. Each port represents at least one of four samples per symbol which requires multiplexing before it is applied to the Digital to Analog Converter (DAC). 2. Digital to Analog Converter (DAC) The DAC section muxes each of the four 10-bit ports and converts them into an analog signal representation of the digital values produced by the ASSP. The DAC samples at a minimum of four samples per symbol based on the ASSP’s Interpolator setting. TrimDACs, controlled by the processor, provide fine adjustment of the amplitude and DC offset of the I and Q output signals. Two of the TrimDACs control the reference voltage used by the output DACs, thereby adjusting the output signal amplitude. The default setting corresponds to a zero adjustment. 3. Low Pass Filter (LPF) The analog signal from the DAC is then filtered to eliminate undesired digitizing effects. The TrimDAC is used to control the offset voltage of the output signal, allowing the user to adjust the balance between the I and Q baseband output signals for upconverter optimization. 4. Rate Exchange The Rate Exchange function generates clocks by converting the byte-wide interface clock to an ASSP processing clock. It then provides the sample clocks to the DAC and Mux sections. The relationship between the byte clock input and the other clocks varies dramatically depending on the FEC and Interpolator settings within the ASSP. FN8013.5 5 1. Low Pass Filter (LPF) The LPF eliminates any undesired baseband high frequency artifacts caused by the down conversion process. 2. ADC The Analog to Digital Converter (ADC) provides a digital representation of the modulated baseband analog signal. It provides eight bits of data for each of the I and Q channels. 3. FPGA Decimating Filter A Field Programmable Gate Array (FPGA) based Decimating Matched Filter is provided for additional filtering based on the desired symbol rate. Multiple FPGA designs are required to cover the full symbol range. They are stored in the processor’s FLASH memory and loaded as required, based on configuration parameters. The modem automatically toggles between the FPGA designs depending on the baud rate. 4. ISL87060DIK Demodulator ASSP The demodulator ASSP accepts quantized baseband I and Q signals and provides all necessary demodulation functions including: • Carrier and Symbol Acquisition and Tracking • Adaptive Equalization • Data Estimation • Convolutional Deinterleaving • Energy Dispersal Removal • Decoding Functions, including Reed-Solomon decoding 5. Baseband Loopback The modulator baseband output can be configured to be connected to the input of the demodulator. This allows insystem functional verification of the modem. The loop-back circuit is implemented with a fully differential buffered/switch circuit. When engaged, the loop-back signals are summed with the normal I and Q input signals to the demodulator. This configuration does not require that either the normal modulator I/Q outputs or the normal demodulator I/Q inputs be disconnected. Operation is transparent to the normal loading on these interfaces. The loop-back signals are summed with the normal input signals. Therefore, when loopback is enabled the system must be set to minimize the signal input from the normal demodulator I/Q input path. ISL837030, ISL83740 Functional Description Demodulator (Continued) Monitor and Control Software 6. Automatic Gain Control (AGC) The demodulator ASSP provides a parallel data word to be used by the AGC to optimize the dynamic range of the input signal to the demodulator. The ASSP averages the magnitude of the input baseband signal, subtracts that from a target value, and accumulates the results. The AGC value is available in either serial digital or analog form. The AGC value output is proportional to the amount by which the incoming signal’s amplitude must be increased in order for its level to reach the desired target. Therefore, an increase in the AGC value indicates that the signal level at the input to the AGC amplifier/attenuator has actually decreased. The modem operates in two different AGC modes: The modem PCBA is configured and monitored using Intersil’s embedded Monitor and Control (M&C) software. This software is used to set parameters such as: • Open loop is used when there is no external AGC loop implemented. • Closed loop is used when the modem’s AGC features are to be used. For best performance, closed loop mode is suggested. This automatically sets the demodulator input level to the optimum value. The system default is open loop mode until any AGC parameter is initialized from the host. The Controller The Controller is a highly integrated device used to eliminate the complexities of interfacing with the Intersil ASSPs directly. It incorporates everything necessary to control and monitor the modem. • modulation type • code rate • payload rate • symbol rate • output level/offset • AGC control • diagnostics • self-test • loopback • alarms • baseband loopback • Alpha (pulse shape) • statistics • • • • BER EVM demodulator stress phase & amplitude imbalance • and more For details, see the Programmer’s Reference AN9935. The Controller’s processor takes high-level commands from the user and determines what is required to configure and monitor the ASSPs. This relieves the user from any real-time interfacing and algorithm implementation issues. The executable firmware is held in FLASH memory that is incircuit upgradeable. This allows the user to upgrade the code or load in a new algorithm as required via the asynchronous serial port (the Monitor and Control port). FN8013.5 6 ISL837030, ISL83740 Performance Specifications Modem Parameters ITEM DESCRIPTION Symbol Rate Range Payload Data Rate Range 3.0Mbaud to 42.514Mbaud 5.6Mbps to 238Mbps (ISL83740) 5.6Mbps to 160Mbps (ISL837030) (255, 238) Internal Sync Mode only (240, 223) External Sync Mode only See Demodulator RS Data Packet Definition on page 20. 18.75W Maximum FEC disabled, RS FEC only, concatenated convolutional inner code with RS outer code Square Root Nyquist, programmable α (0.15 to 0.35) in 0.05 steps ± 500kHz, programmable in 1kHz steps Non-zero tuner offsets may not meet more stringent mask requirements. 32-tap Root Raised Cosine 0.20 rolloff factor Bandwidth tracks selected symbol rate Outer Code (Reed Solomon) Packet Size Power Consumption FEC Modes Pulse Shape (Alpha) Tx Carrier Tuning Range Rx Digital Matched Filter Modulation, Inner Code Rates, and Ranges MODULATION TYPE INNER CODE RATE1 PAYLOAD RATE RANGE IN Mbps2 SYMBOL RATE RANGE IN Mbaud BINARY ASCII BINARY QPSK 0 1 12 5.6000 to 79.3595 5.6000 to 79.3595 8PSK 1 1 12 8.4000 to 119.0392 8.4000 to 119.0392 16QAM 2 3/4 2 8.4000 to 119.0392 8.4000 to 119.0392 7/8 6 9.8000 to 138.8791 9.8000 to 138.8791 ASCII 32QAM 64QAM 128QAM 4 6 8 ISL83740 ISL837030 ISL83740 ISL837030 3.0000 to 42.5140 1 12 All Payload Rates: 11.2000 to 158.7189 11.2000 to 158.7189 3.0000 to 42.5140 4/5 3 11.2000 to 158.7189 11.2000 to 158.7189 9/10 8 12.6000 to 178.5588 12.6000 to 160.0000 3.0000 to 38.0953 3.0000 to 34.2857 1 12 14.0000 to 198.3987 14.0000 to 160.0000 5/6 4 14.0000 to 198.3987 11/12 9 15.4000 to 218.2385 1 12 16.8000 to 238.0784 5 16.8000 to 238.0784 6/7 N/A N/A 1 A rate of 1 is equivalent to No Inner Code. 2Ranges valid for Internal Sync (RS 255, 238). To avoid significant performance degradation, interleaving must be enabled when using concatenated coding rates (any rate other than 1). See the mdLeaver command in the Programmer’s Reference AN9935. FN8013.5 7 ISL837030, ISL83740 Performance Specifications Modulator Performance Specifications ITEM Baseband Amplitude Imbalance DESCRIPTION < 0.1dB after initial trim, over temperature and life < 0.2dB typical without trim Spectral flatness (relative to ideal RRC spectrum) +0.1dB, -0.5dB Baseband Phase Imbalance < 0.5°, over temperature and life I/Q Average Group Delay Imbalance 0.3ns maximum Residual Output Voltage Noise Floor (>100MHz) Less than -110dBmV/Hz rms differential I/Q Anti-alias Filter Low Pass Response 3-pole, -3dB at 32.0MHz I/Q AC Coupling High Pass Response 1-pole, -3dB at 75Hz Tx Symbol Timing Jitter (1kHz to baud/2) 1.0° rms, referred to symbol period Spurious Components (below 140MHz) DAC Aliasing Component (15Mbaud to 17.5Mbaud, 29.75Mbaud to 35Mbaud) -55dBc or better DAC Aliasing Component (other baud rates) -65dBc or better Miscellaneous Spurious Components Spurious Outputs (above 140MHz) Less than -80dBc Modulator Input Requirements ITEM DESCRIPTION Input Data Byte Clock Phase Noise FBYTE < (2.0 X F BAUD FBYTE ) rms, when integrated from 300Hz to 2 EVM and BER may be degraded if this parameter When integrated over an offset bandwidth of 500Hz to half the byte is exceeded. rate frequency, then scaled proportionally to the symbol rate frequency. Modulator Output Electrical Specifications ITEM Output Signal Type DESCRIPTION Fully balanced differential, AC Coupled Baseband Output Level into recommended load1 Nominal: 1.9V p-p. Maximum: 2.2V p-p Baseband Output Adjust/Resolution1 Programmable -4dB to +1.5dB, in approximately 0.04dB steps. Baseband Offset Trim Programmable ± 31mV in 0.244mV steps into 1.2kΩ load at +2.5V bias (Offset adjustment of 0VDC to +5VDC through 95kΩ connected to output). For details, see the Programmer’s Reference AN9935. Load Impedance (Required) 1.20kΩ ± 20%, < 20pF, each leg to ground 1 The modulator pulse shaping, interpolation, and Applicable Standards: FCC 47CFR 101.111; ETSI EN 300-197, analog anti-alias filtering have been designed to 198, 430, and 431; ETSI EN 301-128. meet the requirements of applicable FCC, IC, ITU, and ETSI standard spectral masks. 1 FN8013.5 Output levels are not guaranteed when using the modulator tuner. 8 ISL837030, ISL83740 Performance Specifications Demodulator Input Requirements ITEM Symbol Frequency Error Spectral Slope Error Average I/Q Group Delay Imbalance I/Q Group Delay Response Flatness (p-p delay variation across 3dB spectrum) Carrier Leakage Component Baseband Source Amplitude Error Baseband Source Phase Imbalance DESCRIPTION ± 200 ppm of symbol rate Up to ± 2dB average tilt across passband < 6% of symbol period, up to 40Mbaud < 1.5ns for 40Mbaud to 42.5Mbaud -30dBc or better for QPSK, 8PSK, 16QAM -35dBc or better for 32QAM, 64QAM, 128QAM (64QAM and 128QAM available in ISL83740 only) < 1.0dB maximum < 5° maximum Demodulator Input Electrical Specifications ITEM Input Signal Type Input Impedance Baseband Input Level Baseband Input Bias Open Circuit Input Bias Voltage Input Overload Level FN8013.5 9 DESCRIPTION Balanced differential, DC Coupled Balanced: 1.00kΩ differential Unbalanced: 1.00kΩ In unbalanced mode, source impedances of both legs should be approximately equal to avoid DC offset at the ADCs. Matched source impedances of < 100Ω are recommended. 1.00V p-p for full scale at ADC Current: Source outputs must sink 0.4mA for 0.00VDC input source, each leg Offset: < 10µA 600mVDC (baseband loopback off) Approximately 2.5V p-p ISL837030, ISL83740 Performance Specifications Demodulator Performance Specifications ITEM DESCRIPTION ± 400kHz 1 Rx Carrier Tracking Range Rx Carrier Acquisition Range1 Programmable from 50kHz to 400kHz in increments of 1kHz. For details, see the Programmer’s Reference AN9935. 1The maximum Acquisition and Tracking Rate Range is less than 400kHz when the baud rate is less than 6.6Mbaud, as shown in FIGURE 4. 450 Max rxAcqRange (kHz) 400 350 300 250 200 150 100 3 4 5 6 Symbol Rate (MBaud) 7 8 FIGURE 4 Acquisition/Tracking Range at Low Baud Rates BER Performance (Typical) PARAMETERS BER 1.0E-8 BER 1.0E-10 BER 64QAM and 128QAM available in ISL83740 only. MODULATION TYPE CONDITIONS 1 8.1dB 8PSK, 1 11.6dB 16QAM 1 12.2dB 32QAM 1 14.8dB 64QAM 1 18.7dB 16QAM 3/4 7.8dB 7/8 9.0dB 4/5 9.7dB 9/10 11.4dB 5/6 12.7dB 11/12 15.0dB 128QAM 6/7 17.2dB 32QAM 1 BER < 1.0E-11 • Standard setup using low-cost VHF IF interface loopback1 • No added noise • Baseband loopback, no noise 0 64QAM 1 Performance Eb/No QPSK 32QAM Residual BER, FEC disabled INNER CODE RATE • Standard setup using low-cost VHF IF interface loopback1 is based on a standard setup using the Evaluation Platform’s VHF interface under typical operating conditions at baud rates > 10Mbaud as defined in Demodulator Input Requirements on page 9. All loop bandwidths are set by default to accommodate severe multipath distortions. Performance can be increased significantly by adjusting loop bandwidths for a less severe environment. Performance is 0.5dB to 1dB better when using the Evaluation Platform’s high performance L-band interface. FN8013.5 10 ISL837030, ISL83740 Performance Specifications Controller Parameters ITEM Monitor and Control (M&C) Port FPGA Configuration Update FN8013.5 DESCRIPTION • • • • • • • • • Application Code Update • • • • Reset Time from Power Up • 11 TTL Level UART, RXD, TXD only, no handshake 115.2kBaud 8 bits No Parity 1 Stop Bit Can be performed via M&C port Independent of Application Code Update Cannot be done during modem operation On-board FLASH memory holds up to four Decimating Matched Filter configurations Can be performed via M&C port Independent of FPGA Configuration Update Cannot be done during modem operation Boot-loader write protected to ensure unconditional recovery. 8 seconds ISL837030, ISL83740 Environmental & Physical Specifications Reliability MTBF 457,000 hours (52 years) per Bellcore Standard TR-332 Power Supply Requirements VOLTAGE CURRENT +5VDC ± 5% +3.3VDC ± 5% -8.75VDC to -12VDC +8.75VDC to +12VDC 100mA 5A 100mA 100mA Temperature and Humidity Tolerances ENVIRONMENT OPERATING Temperature Humidity (non-condensing) -40°C to 85°C <95% Operating humidity tolerance can be increased by conformal coating. STORAGE -50°C to 150°C 99% Board Size and Weight (Excluding connectors) Length and Width Height on Top Height on Bottom Weight 6” X 6” 0.3” plus heatsink 0.11” 5 oz. Demodulator ASSP Airflow Requirements AAVID HEATSINK 372024 3719241 372824 1Included FN8013.5 12 HEATSINK HEIGHT 1.100” 0.550” 0.230” FOR 85°C OPERATION (4.3°C/W REQUIRED) ≥ 125 ≥ 265 ≥ 400 FOR 70°C OPERATION (6.1°C/W REQUIRED) 0 ≥ 165 ≥ 300 UNIT linear feet per minute in ISL83740EVAL/ISL83700EVAL Evaluation Platform configurations. ISL837030, ISL83740 Physical Interface Definition The following figure highlights the board connectors: BOTTOM VIEW 80-pin Connector Pin 1 2 4 6 1 3 5 80 79 Actual Connector Pins are on Bottom 8-Pin Modulator Baseband Connector 2 4 6 8 1 3 5 7 8-Pin Demodulator Baseband Connector TOP VIEW 80-pin Connector 80 78 76 79 77 75 2 1 8-Pin Demodulator Baseband Connector 8 6 4 2 8-Pin Modulator Baseband Connector Pin 1 FIGURE 5 Modem PCBA Connectors FN8013.5 13 7 5 3 1 ISL837030, ISL83740 Physical Interface Definition 80-Pin Digital/Power Connector Modem Connector Part #: Samtec TSW-140-07-T-D Suggested Mating Connector: SAMTEC SSW-140-22-T-D The following figure shows the pin configuration for the 80-pin digital/power connector. For additional details, see the following pages. DGROUND DIN 1 DIN 3 DIN 5 DIN 7 DGROUND MOD _PSYNC reserved reserved RESET RXD DGROUND reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved MODEM_PRESENT 2 reserved reserved DGROUND MODEM_RDY +5VDC DMD _DCLK DGROUND DMD _DFLAG DOUT1 DOUT3 DOUT5 DOUT 7 DMD_DATAOK reserved AGROUND +ANALOG_VDC ANALOG_AGC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 +3.3VDC DIN 0 DIN 2 DIN 4 DIN 6 +3.3VDC MOD_DCLK reserved reserved IRQ TXD +3.3VDC reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved MODEM_PRESENT1 AGC _DATA AGC _CLK +3.3VDC AGC _SYNC DEMOD _LK D GROUND +3.3VDC DMD_PSYNC DOUT0 DOUT2 DOUT4 DOUT6 D GROUND reserved AGROUND -ANALOG_VDC reserved FIGURE 6 Digital/Power Connector Pin Configuration FN8013.5 14 ISL837030, ISL83740 Physical Interface Definition Power Supply Signals PIN(S) 78 77 1 11 23 51 59 56 75 76 2 12 24 52 57 60 71 SIGNAL NAME +ANALOG_VDC -ANALOG_VDC +3.3VDC DESCRIPTION CHARACTERISTIC Positive Analog Voltage Negative Analog Voltage +8.75VDC to +12VDC -8.75VDC to -12VDC Digital Voltage ± 5% +5VDC AGROUND Analog Ground DGROUND Digital Ground M&C Port Signals PIN(S) SIGNAL NAME DESCRIPTION 22 RXD Status data from modem (output) 21 TXD Control data to modem (input) CHARACTERISTIC TTL VOH = 2.4V minimum VOL = 0.6V maximum TTL VIH = 2.3V minimum VIL = 0.8V maximum Modulator Data Interface Signals PIN(S) FN8013.5 SIGNAL NAME 3 4 5 6 7 8 9 10 13 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 MOD_DCLK 14 MOD_PSYNC 15 DESCRIPTION CHARACTERISTIC Data input LSB Data Input TTL VIH = 2.3V minimum VIL = 0.8V maximum Data input MSB Byte rate input clock. Data sampled on rising edge. When in external sync byte mode, active high flag indicates sync byte location in input transport stream. When not used leave open or tie low. ISL837030, ISL83740 Physical Interface Definition Demodulator Data Interface Signals PIN(S) FN8013.5 SIGNAL NAME 63 64 65 66 67 68 69 70 61 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DMD_PSYNC 62 DMD_DFLAG 58 DMD_DCLK 72 DMD_DATAOK 80 ANALOG_AGC 49 AGC_CLK 53 AGC_SYNC 47 AGC_DATA 16 DESCRIPTION CHARACTERISTIC Data output LSB Data Output Data output MSB Active high signal indicates sync byte is available on bus. Active high signal indicates valid data is available on bus. Low indicates Reed Solomon Parity or sync byte is on bus. Byte output clock. Data transitions on falling edge. This clock is ASSP Process Clock gated when valid data is output from the ASSP. Valid data includes sync and parity bytes. Active high signal indicates presence of RS-correctable packet. Indicates the current output packet contains no errors. A voltage representative of the digital value calculated by the ASSP. The ASSP averages the magnitude of the input baseband signal, subtracts that from a target value, and accumulates the results. Serial clock output. Data transitions on rising edge, should be stored on the falling edge. Active low signal used to bound valid data out. Serial data, 12 bits AGC, 4 bits padding. Data transitions on rising edge of AGC_CLK. See AGC Timing on page 21. TTL VOH ≥ 2.4V minimum VOL ≤ 0.4V maximum Range: 0VDC to 3.0VDC Impedance: 100Ω Current: ± 3mA maximum Update Rate: approximately every 2,000 symbols TTL VOH ≥ 2.4V minimum VOL ≤ 0.4V maximum ISL837030, ISL83740 Physical Interface Definition Miscellaneous Signals PIN(S) SIGNAL NAME 20 RESET 19 IRQ 55 DEMOD_LK 54 MODEM_RDY 45 OR 46 MODEM_PRESENT1 MODEM_PRESENT2 DESCRIPTION Active low hard reset. Resets processor and ASSPs to their initial conditions. This signal is extended by 350ms by a device used to monitor VCC and the state of the reset signal. Active low interrupt request indicates modem requires attention. When enabled this signal asserts, indicating that a fault condition exists on the modem. Demodulator lock indicator. low = lock Active high indicates modem is Ready. Indicates modem is available after power up or reset. Typical time is less than 8 seconds after valid 3.3V or RESET. 4.7k pullup to 3.3V Use either 45 or 46; do not tie together. Reserved PIN(S) 15-18 25-44 48 50 73-74 79 FN8013.5 17 DESCRIPTION Leave all unused pins unconnected. Some are used for test and some are reserved for future expansion. CHARACTERISTIC Open Drain VIH ≥ 2.0V minimum VIL ≤ 0.8V maximum 5k pullup to 3.3V on modem TTL VOH ≥ 2.4V minimum VOL ≤ 0.4V maximum Can be used for modem presence detect. ISL837030, ISL83740 Physical Interface Definition 8-Pin Baseband Connectors Modem Connector Part Number: Samtec TSW-104-07-T-D Modulator Analog Baseband Connector MOD IGND MOD QGND 2 4 6 8 1 3 5 7 MOD I+ GND MOD Q+ GND FIGURE 7 Modulator Connector Pin Configuration PIN(S) 1 2 5 6 3 4 7 8 SIGNAL NAME MOD MOD MOD MOD GND DESCRIPTION CHARACTERISTIC I Baseband Analog Output I+ IQ+ Q- Q Baseband Analog Output 1.9V p-p differential with 1.2kΩ, < 20pF load Ground Demodulator Analog Baseband Connector DMD IGND DMD QGND 2 4 6 8 1 3 5 7 DMD I+ GND DMD Q+ GND FIGURE 8 Demodulator Connector Pin Configuration PIN(S) 1 2 5 6 3 4 7 8 FN8013.5 18 SIGNAL NAME DMD DMD DMD DMD GND I+ IQ+ Q- DESCRIPTION CHARACTERISTIC I Baseband Analog Input Q Baseband Analog Input Ground 1.0V p-p nominal 1.0kΩ, < 25pF load ISL837030, ISL83740 Data Timing and Packet Definition Modulator Data Input Timing Tscpw Tscf MOD_DCLK Tddhld Tddsu FIGURE 9 Modulator Data Input Timing SYMBOL DESCRIPTION MIN Tscf Shift_Clk Clock Period 50.0 Tscpw Shift_Clk Pulse Width Tddsu Data Setup Time 12.0 Tddhld Data Hold Time 1.0 8.0 UNITS nsec Modulator Packet Definition Reed Solomon Packet DIN [7..0] Sync Byte (1) Data (223 bytes) MOD_PSYNC External Sync Byte Mode.1 FIGURE 10 Modulator Packet Definition 1 FN8013.5 When using Internal Sync Byte Mode, byte-wide data is input to the modulator at a constant rate defined by the configured data rate. Reed Solomon packetization is transparent to the input interface. 19 ISL837030, ISL83740 Data Timing and Packet Definition Demodulator Data Output Timing Tper Thpul 1 DMD_DCLK Tdcf DMD_PSYNC, DMD_DFLAG, DMD_DATAOK Tdcd DOUT[7..0] 1The DMD_DCLK is asynchronous to the output data rate and is a gated version of the demodulator’s process clock. Its periodicity varies significantly based on Symbol Rate and Decimating Filter configurations. If a continuous output clock is desired, the user must provide some form of “elastic buffer” external to the modem. FIGURE 11 Demodulator Data Output Timing SYMBOL Tper Thpul Tdcf Tdcd DESCRIPTION MIN DMD_DCLK Clock Period Note: Worst case, assumes consecutive pulses are gated by the demodulator. DMD_DCLK High Width Delay Clock to DMD_DFLAG, DMD_PSYNC Delay Clock to DOUT 11.76 MAX UNITS N/A nsec 3.7 -.05 N/A 2 Demodulator RS Data Packet Definition DOUT[7..0] Sync Byte (1) Payload Bytes Reed Solomon 1 Parity DMD_PSYNC DMD_DFLAG DMD_DATAOK Valid Packet 1 Sixteen Reed Solomon parity bytes are output whether encoding is enabled or disabled. FIGURE 12 Demodulator Data Packet Definition Reed Solomon (RS) packet size is calculated as follows: • RS Packet Size = 1 Sync Byte + Payload Bytes + 16 RS Parity Bytes • Sync byte: (external sync mode) supplied by the host connected to the transmitting modem, (internal sync mode) supplied internally by the transmitting modem • Payload bytes: supplied by the host connected to the transmitting modem • RS parity bytes: supplied internally by the transmitting modem • An RS packet length of 240 = 1 Sync Byte + 223 Payload Bytes + 16 RS Parity Bytes. Supported by External Sync Mode only. • An RS packet length of 255 = 1 Sync Byte + 238 Payload Bytes + 16 RS Parity Bytes. Supported by Internal Sync Mode only. FN8013.5 20 ISL837030, ISL83740 Data Timing and Packet Definition AGC Timing Tper AGC_CLK // Tsdly / AGC_SYNC // Tddly / Tupdate Tupdate AGC_DATA Ignore First 4 Clock Cycles D11 (MSB) D10 // // D1 D0 (LSB) FIGURE 13 AGC Timing SYMBOL Tper Tsdly Tddly Tupdate FN8013.5 21 DESCRIPTION AGC_CLK Clock Period, 50% ± 5% Duty Cycle AGC_SYNC delay from AGC_CLK AGC_DATA delay from AGC_CLK Delay between updates MIN MAX 200 N/A 0 5 0 10 3.2 Typical UNITS nsec µs ISL837030, ISL83740 Mechanical Drawings Measurements are in inches. .000 .125 .175 5.616 .858 .125 .000 SAMTEC P/N TSW-140-07-T-D 2 .125 DIA. NON-PLATED THRU HOLES 4 PLC'S 80 79 1 MODEM PCBA SAMTEC P/N TSW-104-07-T-D 2 8 1 7 1 7 5.741 5.741 8 3.308 2 2.008 5.335 5.616 FIGURE 14 Modem PCBA Mechanical Dimensions (Top View) FN8013.5 22 ISL837030, ISL83740 Applications Suggested Baseband Interfaces to the Modem I DAC 0mA to 20mA + 1.8mf 0.42VDC 124 0.1% V bias 143 0.1% I-input 124 0.1% 0mA to 20mA - + 143 0.1% 12k 0.42VDC 4x 2.43k* 1.8mF 2.2V p-p max 12k 95k 1 2 3 4 5 6 7 8 - Opt. TrimDACs I level/bal I offset -Vr Q offset Q level/bal AD8346 Direct U/C V bias Q-input + 95k Q DAC 12k 0mA to 20mA + 0.42VDC 143 0.1% 2.2V p-p max - 143 0.1% 124 0.1% - 4x 2.43k* 12k 124 0.1% 0mA to 20mA 1.8mf 0.42VDC 1.8mF Modem PCBA *Matched resistor networks recommended. FIGURE 15 Modulator Baseband Interface to ISL83740EVAL/ISL83700EVAL Platform This figure shows an IF interface to an L-band daughterboard (included with the Evaluation Platform). FN8013.5 23 ISL837030, ISL83740 Applications . 1.00k Modem PCBA 270nH, 5% 1.00k Direct Down Convert Baseband Output Amplifiers I Ch. ADC AD8132 + - - + 1.00k 49.9 56.2 15pF 5% 2x 3.9pF 85Msps 68pF 2% 270nH, 5% 49.9 1 2 3 4 5 6 7 8 I Data + 56.2 I Ch. 1.05V p-p - 1.30k 1.00V p-p 1.00k 49.9 Q Ch. 1.05V p-p 49.9 1.00k 270nH, 5% 1.00k For Shorter Runs Q Ch. ADC AD8132 56.2 + - - + 1.00k 15pF 5% 2x 3.9pF - 1.30k 68pF 2% 85Msps Q Data + 56.2 270nH, 5% 1.00V p-p 1.00k FIGURE 16 Unbalanced Demodulator Baseband Interface, Shorter Runs 1.00k Modem PCBA 270nH, 5% 1.00k Direct Down Convert Baseband Output Amplifiers I Ch. + - - + 1.00k 49.9 I Ch. ADC AD8132 56.2 15pF 5% 2x 3.9pF 1 2 3 4 5 6 7 8 68pF 2% 56.2 270nH, 5% 2.00V p-p - 1.30k 85Msps I Data + 1.00V p-p 1.00k 52.3 24.9 49.9 Q Ch. 2.00V p-p 52.3 1.00k 270nH, 5% 24.9 1.00K For Longer Runs AD8132 + - - + 1.00K 1.30k 15pF 5% 2x 3.9pF 68pF 2% 56.2 270nH, 5% 1.00k Q Ch. ADC 56.2 1.00V p-p FIGURE 17 Unbalanced Demodulator Baseband Interface, Longer Runs FN8013.5 24 85Msps + Q Data ISL837030, ISL83740 Support Note: In some cases, users may enter parameters outside of ranges listed in this document; however, only listed ranges are supported. Related Documentation For a list and description of documentation included with Intersil CommLink Broadband products, see the ReadMeFirst Application Note (AN9940). Additional documentation, product information, and press releases may be posted on the Intersil web page: www.intersil.com/design/commlink/broadbandmodem.asp. Release Notes ISL83740 Rev 5 The following is a change to the documentation to make it match the system. Changed Binary modulation type for 128QAM to 8 (was 7). See Modulation, Inner Code Rates, and Ranges on page 7. ISL837030 and ISL83740 Rev 4 Added support for ISL83740 functionality, higher data rates. See Modulation, Inner Code Rates, and Ranges on page 7. Manual updated in other places where rates are listed to show which rates apply to ISL83740 and ISL837030. Changed Baseband Output Level into recommended load: Nominal 1.9V p-p (was 1.95V p-p), Maximum 2.2V p-p (was 2.45V p-p). Changed Baseband Output Adjust Resolution: Programmable +1.5dB to -4dB (was +2dB to -4dB). See Modulator Output Electrical Specifications on page 8, FIGURE 7 Modulator Connector Pin Configuration on page 18 (configuration), and FIGURE 15 Modulator Baseband Interface to ISL83740EVAL/ISL83700EVAL Platform on page 23. Updated BER performance table to add new data rates/related information. See BER Performance (Typical) on page 10. Changed ANALOG_AGC current to be ± 3mA maximum (was ± 6mA maximum). See ANALOG_AGC on page 16. Added Acquisition and Tracking Range chart. See Demodulator Performance Specifications on page 10. A reference to baud rates being > 10Mbaud added to note under BER performance. See BER Performance (Typical) on page 10. Added support for mdleaver command (ISL83740 only). See Programmer’s Reference AN9935. ISL837030 Rev 3 Added Tupdate to AGC Timing Diagram. Changed Tper MIN to be 200 (was 100). See AGC Timing on page 21. Rev 2 Corrected Thpul minimum from 5.29 to 3.7. , page 20. Updated Demodulator Airflow Requirements. Demodulator ASSP Airflow Requirements on page 12. Corrected MTBF. Reliability on page 12 Rev 1 Initial Release Customer Support Intersil CommLink Broadband creates reference designs and related products for broadband wireless digital communications. If you have questions, comments, or suggestions concerning the product or this manual, please contact Intersil Customer Support at www.intersil.com. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8013.5 25