CD54ACT623F3A S E M I C O N D U C T O R Octal Bus Transceiver Three-State, Non-Inverting July 1998 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The CD54ACT623F3A is an octal bus transceiver that utilizes Harris Advanced CMOS Logic technology. It is a noninverting three-state bidirectional transceiver-buffer that allows for two-way transmission from “A” bus to “B” bus or “B” bus to “A” bus depending on the logic levels of the Output Enable (OEAB, OEBA) inputs. • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 • Meets JEDEC Standard No. 20 The dual Output Enable provision gives these devices the capability to store data by simultaneously enabling OEAB and OEBA. Each output reinforces its input under these conditions, and when all other data sources to the bus lines are at high-impedance, both sets of bus lines will remain in their last states. • SCR - Latch-Up-Resistant CMOS Process and Circuit Design • Speed of Bipolar FAST/A/S with Significantly Reduced Power Consumption • Functionally and Pin-Compatible with Industry 54 Bipolar Types in the FAST, AS and S Series Ordering Information • Balanced Propagation Delays • Military Operating Temperature Range - Ceramic (CERDIP) 54 Series: . . . . . . . . -55 to 125oC • ±24mA Output Drive Current, Drives 75Ω Lines without Need for Terminations A1 A2 A3 A4 A5 A6 A7 3 17 4 16 5 15 6 14 7 13 8 12 9 11 -55 to 125 20 Ld CERDIP F20.3 Pinout Functional Diagram 18 CD54ACT623F3A PKG. NO. PACKAGE 1. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. • Operation Voltage . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V 2 TEMP. RANGE (oC) NOTE: • Fan Out (Over Temperature) - ACL Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400 - FAST Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - AS Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 A0 PART NUMBER B0 B1 B2 B3 B4 OEAB 1 A0 2 19 OEBA A1 3 18 B0 A2 4 17 B1 A3 5 16 B2 A4 6 15 B3 A5 7 14 B4 A6 8 13 B5 A7 9 12 B6 GND 10 11 B7 20 VCC B5 B6 B7 1 OEAB OEBA 19 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 1 File Number 3917.1 CD54ACT623F3A Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or Ground Current, ICC or IGND (Note 2) . . . . . . . . .±100mA Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 80 22 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 3) . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. For up to 4 outputs per device, add ±25mA for each additional output. 3. Unless otherwise specified, all voltages are referenced to ground. 4. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) High Level Input Voltage VIH - - Low Level Input Voltage VIL - - High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - V -24 4.5 3.94 (Note 5) - 3.7 (Note 5) - V -50 (Note 6, 7) 5.5 - - 3.85 - V 0.05 4.5 - 0.1 - 0.1 V 24 4.5 - 0.36 (Note 5) - 0.5 (Note 5) V 50 (Note 6, 7) 5.5 - - - 1.65 V PARAMETER Low Level Output Voltage VOL VIH or VIL MIN MAX MIN MAX UNITS 4.5 to 5.5 2 (Note 5) - 2 (Note 5) - V 4.5 to 5.5 - 0.8 (Note 5) - 0.8 (Note 5) V II VCC or GND - 5.5 - ±0.1 (Note 5) - ±1 (Note 5) µA Three-State or Leakage Current IOZ VIH or VIL VO = VCC or GND - 5.5 - ±0.5 (Note 5) - ±10 (Note 5) µA Quiescent Device Current ICC VCC or GND 0 5.5 - 8 (Note 5) - 160 (Note 5) µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 2.4 - 3 mA Input Leakage Current Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load NOTES: 5. Tested 100%. 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum transmission-line-drive capability of 75Ω for 54ACT Series. 2 CD54ACT623F3A ACT Input Load Table INPUT UNIT LOAD An, Bn 0.83 OEBA 0.64 OEAB 0.15 NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) -55oC TO 125oC PARAMETER SYMBOL VCC (V) MIN TYP MAX UNITS Propagation Delay, Data to Output tPLH, tPHL 5 (Note 10) 1.8 - 10.6 (Note 8 ns Propagation Delay, Output Disable to Output tPLZ, tPHZ 5 2.5 - 14.4 (Note 8) ns Propagation Delay, Output Enable to Output tPZL, tPZH 5 2.5 - 14.4 (Note 8) ns - V Minimum (Valley) VOH During Switching of Other Outputs (Output Under Test Not Switching) VOHV See Figure 1 5 - 4 at 25oC Maximum (Peak) VOL During Switching of Other Outputs (Output Under Test Not Switching) VOLP See Figure 1 5 - 1 at 25oC - V CO - - - 15 pF Three-State Output Capacitance Input Capacitance Power Dissipation Capacitance CI - - - 10 pF CPD (Note 11) - - 79 - pF NOTES: 8. Limits tested 100%. 9. 3.3V Min = 3.6V, Max = 3V. 10. 5V Min = 5.5V, Max = 4.5V 11. CPD is used to determine the dynamic power consumption per gate. PD = VCC2 fi (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. Burn-In Test Circuit Connections (Use DC II for F3A Burn-In and AC for Life Test) DC BURN-IN I DC CD54ACT623 DC BURN-IN II OPEN GROUND VCC (6V) OPEN GROUND VCC (6V) 2-9 1, 10-19 20 11-18 10 1-9, 19, 20 OPEN GROUND 1/2 VCC (3V) VCC (6V) 50kHz 25kHz - 10 11-18 19, 20 2-9 1 OSCILLATOR AC CD54ACT623 NOTE: Each pin except VCC and Gnd will have a resistor of 2kΩ-47kΩ. OUTPUT RL 500Ω DUT OUTPUT LOAD CL 50pF CD54ACT Input Level 3V Input Switching Voltage, VS Output Switching Voltage, VS 1.5V 0.5 VCC FIGURE 1. PROPAGATION DELAY TIMES 3