CD54AC00F3A, CD54ACT00F3A Semiconductor Quad 2-Input NAND Gate July 1998 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The CD54AC00F3A and CD54ACT00F3A are quad 2-input NAND gates that utilize the Harris Advanced CMOS Logic technology. • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 Ordering Information • Meets JEDEC Standard No. 20 PART NUMBER • SCR - Latch-Up-Resistant CMOS Process and Circuit Design • Speed of Bipolar FAST/A/S with Significantly Reduced Power Consumption TEMP. RANGE (oC) PKG. NO. PACKAGE CD54AC00F3A -55 to 125 14 Ld CERDIP F14.3 CD54ACT00F3A -55 to 125 14 Ld CERDIP F14.3 NOTE: • Functionally and Pin-Compatible with Industry 54 Bipolar Types in the FAST, AS and S Series 1. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. • Balanced Propagation Delays • Military Operating Temperature Range - Ceramic (CERDIP) 54 Series: . . . . . . . . -55 to 125oC Functional Diagram • ±24mA Output Drive Current, Drives 75Ω Lines without Need for Terminations 1A 1B • Fan Out (Over Temperature) - ACL Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400 - FAST Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - AS Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2A 2B 3B 3A • Balanced Noise Immunity at 30% of Supply for AC Types 4B 4A 1 3 2 4 5 6 9 8 1Y 2Y 3Y 10 12 11 13 4Y GND = 7 VCC = 14 • Supply Voltage Range - AC Types . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 5.5V - ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V TRUTH TABLE INPUTS Pinout A B Y 1A 1 14 VCC L L H 1B 2 13 4A H L H 1Y 3 12 4B L H H 2A 4 11 4Y H H L 2B 5 10 3A 2Y 6 9 3B GND 7 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright OUTPUTS © Harris Corporation 1998 1 File Number 3876.1 CD54AC00F3A, CD54ACT00F3A Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or Ground Current, ICC or IGND (Note 2) . . . . . . . . .±100mA Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 80 24 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 3) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) 4.5V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. For up to 4 outputs per device, add ±25mA for each additional output. 3. Unless otherwise specified, all voltages are referenced to ground. 4. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) IO (mA) VCC (V) VIH - - 1.5 25oC -55oC TO 125oC MIN MAX MIN MAX UNITS 1.2 - 1.2 - V AC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL VOH - VIH or VIL - 3 2.1 - 2.1 - V 4.5 3.15 (Note 5) - 3.15 (Note 5) - V 5.5 3.85 - 3.85 - V 1.5 - 0.3 - 0.3 V 3 - 0.9 - 0.9 V 4.5 - 1.35 (Note 5) - 1.35 (Note 5) V 5.5 - 1.65 - 1.65 V -0.05 1.5 1.4 - 1.4 - V -0.05 3 2.9 - 2.9 - V -0.05 4.5 4.4 - 4.4 - V -4 3 2.58 - 2.4 - V -24 4.5 3.94 (Note 5) - 3.7 (Note 5) - V -50 (Note 6, 7) 5.5 - - 3.85 - V 2 CD54AC00F3A, CD54ACT00F3A DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage Input Leakage Current Quiescent Device Current 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 V 0.05 3 - 0.1 - 0.1 V 0.05 4.5 - 0.1 - 0.1 V 12 3 - 0.36 - 0.5 V 24 4.5 - 0.36 (Note 5) - 0.5 (Note 5) V 50 (Note 6, 7) 5.5 - - - 1.65 V - 5.5 - ±0.1 (Note 5) - ±1 (Note 5) µA 0 5.5 - 4 (Note 5) - 80 (Note 5) µA II VCC or GND ICC MIN MAX MIN MAX UNITS ACT TYPES High Level Input Voltage VIH - - 4.5 to 5.5 2 (Note 5) - 2 (Note 5) - V Low Level Input Voltage VIL - - 4.5 to 5.5 - 0.8 (Note 5) - 0.8 (Note 5) V High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - V -24 4.5 3.94 (Note 5) - 3.7 (Note 5) - V -50 (Note 6, 7) 5.5 - - 3.85 - V 0.05 4.5 - 0.1 - 0.1 V 24 4.5 - 0.36 (Note 5) - 0.5 (Note 5) V 50 (Note 6, 7) 5.5 - - - 1.65 V Low Level Output Voltage Input Leakage Current Quiescent Device Current Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load VOL VIH or VIL II VCC or GND - 5.5 - ±0.1 (Note 5) - ±1 (Note 5) µA ICC VCC or GND 0 5.5 - 4 (Note 5) - 80 (Note 5) µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 2.4 - 3 mA NOTES: 5. Tested at 100%. 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum transmission-line-drive capability of 75Ω for 54AC/ACT Series. ACT Input Load Table INPUT UNIT LOAD All 0.15 NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. 3 CD54AC00F3A, CD54ACT00F3A Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) -55oC TO 125oC PARAMETER SYMBOL VCC (V) MIN TYP MAX UNITS tPLH, tPHL 1.5 - - 91 ns 3.3 (Note 9) 3.1 - 10.2 ns 5 (Note 10) 2.2 - 7.3 (Note 8) ns CI - - - 10 pF CPD (Note 11) - - 45 - pF tPLH 5 (Note 10) 3.2 - 10.8 (Note 8) ns 4 - 13.2 (Note 8) ns AC TYPES Propagation Delay, Input to Output Input Capacitance Power Dissipation Capacitance ACT TYPES Propagation Delay, Input to Output tPHL Input Capacitance Power Dissipation Capacitance CI - - - 10 pF CPD (Note 11) - - 45 - pF NOTES: 8. Limits tested at 100%. 9. 3.3V Min at 3.6V, Max at 3V. 10. 5V Min at 5.5V, Max at 4.5V 11. CPD is used to determine the dynamic power consumption per gate. AC: PD = VCC2 fi (CPD + CL) ACT: PD = VCC2 fi (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. Burn-In Test Circuit Connections (Use DC II for F3A Burn-In and AC for Life Test) DC BURN-IN I DC BURN-IN II DC OPEN GROUND VCC (6V) OPEN GROUND VCC (6V) CD54AC/ACT00 3, 6, 8, 11 1, 2, 4, 5, 7, 9, 10, 12, 13 14 3, 6, 8, 11 7 1, 2, 4, 5, 9, 10, 12 - 14 OSCILLATOR AC OPEN GROUND 1/2 VCC (3V) VCC (6V) 50kHz 25kHz CD54AC/ACT00 - 7 3, 6, 8, 11 14 1, 2, 4, 5, 9, 10, 12, 13 - NOTE: Each pin except VCC and Gnd will have a resistor of 2kΩ-47kΩ. INPUT LEVEL RL (NOTE) 500Ω 90% VS VI DUT OUTPUT LOAD tf = 3ns tr = 3ns OUTPUT 10% VO CL 50pF VS NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ. tPHL CD54AC CD54ACT VCC 3V Input Switching Voltage, VS 0.5 VCC 1.5V Output Switching Voltage, VS 0.5 VCC 0.5 VCC Input Level tPLH FIGURE 2. WAVEFORMS FIGURE 1. PROPAGATION DELAY TIMES 4 GND