IDT MK1493

DATASHEET
MK1493-03B
PCI CLOCK GENERATOR
Description
Features
The MK1493-03B is a general purpose clock generator
device that provides an integrated clocking solution for PCI
/networking applications. It provides eight individually
programmable PCI clocks, one CPU clock, three additional
fixed PCI clocks, and a 25 MHz reference clock for LAN
support. This part incorporates IDT’s newest clock
technology, offering more robust features and functionality.
The device provides a gradual transition from its initial clock
frequency to the new one. Using a serially programmable
SMBus interface, the MK1493-03B can select the output
clock frequency and the transition from the original value to
the new value. The SMBus also allows each of the 8
programmable PCI clocks to be individually enabled and
disabled.
• Individually programmable (25, 33.33, 50, 66.66 MHz)
•
•
•
•
•
•
•
•
•
•
•
•
•
PCI clocks (Serial or external pin control)
1 CPU clock at 100/125 MHz Selectable; single
ended/differential selectable
1 Clock at 66.66 MHz
1 Clock at 66/71/83 MHz selectable
1 Clock at 50 MHz
25 MHz reference clock
SMBus Programming
Power-up default frequency can be selected through FS
inputs
25 MHz crystal or clock input required
PCICLK cycle to cycle jitter <250 ps
CPUCLK cycle to cycle jitter <150 ps
48-pin, 240 mil TSSOP Package
Operating Voltage 3.3 V ±5%
Commercial (0 to +70°C) and Industrial temperature
ranges (-40 to +85°C)
Block Diagram
VDD
7
8
SCLK
PCICLK(0:7)
Each PCI Output Clock
Individually Programmable
CPUCLK 100M/125M
SDATA
FS(0:7)_A
8
FS(0:7)_B
8
PLL
Divider
Buffer Circuits
SMBus Programmable
FS8
FS9
FS10
CPUCLKB 100M/125M
CLK66M/71M/83M
CLK66M
CLK50M
X1/CLK
Clock Buffer/
Crystal
Ocsillator
25 MHz
REF25(25MHz)
X2
External caps required
with crystal for accurate
tuning of the clock
IDT™ PCI CLOCK GENERATOR
7
GND
1
MK1493-03B
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
Pin Assignment
CLOCK SYNTHESIZER
48-pin TSSOP
FS3_A
FS2_A
FS1_A
1
2
3
48
47
46
FS4_A
FS5_A
FS6_A
FS0_A
GND
VDD
SCL
SDA
GND
4
5
6
7
8
9
45
44
43
42
41
40
FS7_A
FS0_B
FS1_B
PCICLK7
GND
VDD
X1 / ICLK
X2
VDD
10
11
12
39
38
37
PCICLK6
PCICLK5
PCICLK4
REF25
VDD
GND
13
14
15
36
35
34
GND
VDD
CPUCLK
CPUCLK
FS7_B
16
17
18
19
20
33
32
31
30
29
FS2_B
VDD
GND
CLK66/71/83
CLK50M
FS6_B
21
22
28
27
PCICLK2/FS10
PCICLK1/FS9
FS5_B
FS4_B
23
24
26
25
PCICLK0
PCICLK3
Table 1. Frequency Select
1)
FS(0:7)_B
FS(0:7)_A
PCICLK(0:7)* 1 2
0
0
25 MHz
0
1
33.3333 MHz
1
0
50 MHz
1
1
66.6666 MHz
Each PCI clock is individually selectable.
Table 2. Input Select (FS8, FS9,FS10&FS11)
CLK66M/FS8
FS3_B
VDD
GND
FS8 (pin 32)
CPUCLK/CPUCLK 2
0
125MHz
1
100MHz3
FS9
(pin 27)
FS10
(pin 28)
CLK66M/71M/83M 2
(pin 33)
0
0
83.33 MHz3
0
1
71.42 MHz
1
0
66.66 MHz
1
1
OFF
2)
The changes in frequency are step changes.
3) Default Value upon Power up.
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
FS3_A
Input
Freq select input pin for PCI CLK3 per table 1. Internal pull-up resistor 120K.
2
FS2_A
Input
Freq select input pin for PCI CLK2 per table 1. Internal pull-up resistor 120K.
3
FS1_A
Input
Freq select input pin for PCI CLK1 per table 1. Internal pull-up resistor 120K.
4
FS0_A
Input
Freq select input pin for PCI CLK0 per table 1. Internal pull-up resistor 120K.
5
GND
Power
Connect to ground.
6
VDD
Power
Connect to +3.3 V.
7
SCL
Input
Clock pin for SMBus circuitry, 5 V tolerant.
8
SDA
Input
Data pin for SMBus circuitry, 5 V tolerant.
9
GND
Power
Connect to ground.
10
X1/ICLK
Input
Crystal connection/input clock. Connect to a 25 MHz fundamental mode crystal or clock input.
11
X2
XO
12
VDD
Power
IDT™ PCI CLOCK GENERATOR
Pin Description
Connect to a 25 MHz fundamental mode crystal or leave open for clock input.
Connect to +3.3 V.
2
MK1493-03B
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
Pin
Number
Pin
Name
13
REF25
14
VDD
Power
Connect to +3.3 V.
15
GND
Power
Connect to ground.
16
GND
Power
Connect to ground.
17
VDD
Power
Connect to +3.3 V.
18
CPUCLK
Output 100/125 MHz CPU clock.
19
CPUCLK
Output 100/125 MHz CPU clock.
20
FS7_B
21
CLK50M
22
FS6_B
Input
Freq select input pin for PCI CLK6 per table 1. Internal pull-up resistor 120 KΩ.
23
FS5_B
Input
Freq select input pin for PCI CLK5 per table 1. Internal pull-up resistor 120 KΩ.
24
FS4_B
Input
Freq select input pin for PCI CLK4 per table 1. Internal pull-up resistor 120 KΩ.
25
PCICLK3
Output PCI CLK3 (Programmable PCI Clock 3).
26
PCICLK0
Output PCI CLK0 (Programmable PCI Clock 0).
27
PCICLK1/FS9
I/O
PCI CLK1 (For CLK66/71/83 selection on pin 33, using FS9) (See table 2).
28
PCICLK2/FS10
I/O
PCI CLK2 (For CLK66/71/83 selection on pin 33, using FS10) (See table 2).
29
GND
Power
Connect to ground.
30
VDD
Power
Connect to +3.3 V.
31
FS3_B
Input
Freq select input pin for PCI CLK3 per table 1. Internal pull-up resistor 120 KΩ.
32
CLK66M/FS8
I/O
33
CLK66/71/83
34
GND
Power
Connect to ground.
35
VDD
Power
Connect to +3.3 V.
36
FS2_B
Input
Freq select input pin for PCI CLK2 per table 1. Internal pull-up resistor 120 KΩ.
37
PCICLK4
Output PCI CLK4 (Programmable PCI Clock 4).
38
PCICLK5
Output PCI CLK5 (Programmable PCI Clock 5).
39
PCICLK6
Output PCI CLK6 (Programmable PCI Clock 6).
40
VDD
Power
Connect to +3.3 V.
41
GND
Power
Connect to ground.
42
PCICLK7
43
FS1_B
Input
Freq select input pin for PCI CLK1 per table 1. Internal Pull up resistor 120 KΩ.
44
FS0_B
Input
Freq select input pin for PCI CLK0 per table 1. Internal Pull up resistor 120 KΩ.
45
FS7_A
Input
Freq select input pin for PCI CLK7 per table 1. Internal Pull up resistor 120 KΩ.
46
FS6_A
Input
Freq select input pin for PCI CLK6 per table 1. Internal Pull up resistor 120 KΩ.
47
FS5_A
Input
Freq select input pin for PCI CLK5 per table 1. Internal Pull up resistor 120 KΩ.
48
FS4_A
Input
Freq select input pin for PCI CLK4 per table 1. Internal Pull up resistor 120 KΩ.
IDT™ PCI CLOCK GENERATOR
Pin
Type
Pin Description
Output Buffered reference output of 25 MHz, (See table2, FS11=0 turns this clock off).
Input
1 of 4 freq select input pin for PCI CLK7 per table 1. Internal pull-up resistor 120 KΩ.
Output 50 MHz clock output.
66.66 MHz clock, FS8=1 CPUCLK=100 MHz, FS8=0 CPUCLK=125 MHz) (table 2).
Output Clock66/71/83. Default Value is 83.33 MHz.
Output PCI CLK7.
3
MK1493-03B
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
Power Groups
Index Block Write Operation
Beginning Byte N
Description
Pin Number
GND
12
9
Ref, Crystal Osc Power
supply
29, 41
PCICLK
35
34
PCI 66 clocks
6
5
SMBus
17
16
CPU Clocks(100MHz)
14
15
PLL
30, 40
ACK
O
O
X Byte
VDD
O
O
O
O
Byte N + X - 1
ACK
P
stoP
General SM-Bus Serial Interface
Information
How to Write:
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address D2 (H)
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller sends Byte Count X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
T
starT
Slave
Address D2
WR
IDT (Slave/Receiver)
(H)
ACK
Beg Location = N
ACK
Data Byte Count = X
ACK
IDT™ PCI CLOCK GENERATOR
4
MK1493-03B
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send a start bit
Controller (host) sends the write address D2 (H)
IDT clock will acknowledge
Controller (host) sends the beginning Byte location = N
IDT clock will acknowledge
Controller (host) will send a repeat start bit
Controller (host) sends the read address Byte D3 (H)
IDT clock will acknowledge
IDT clock will send the data Byte count = X
IDT clock sends Byte N
IDT clock sends Byte N+X-1
Controller (host) will need to acknowledge each Byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
IDT (Slave/Receiver)
Controller (Host)
T
starT bit
Slave Address
D2 (H)
WR
=0
ACK
Beginning Loc = N
ACK
RT
repeat
starT
Slave Address
D2 (H)
RD
=1
ACK
Data Byte Count=X
ACK
Beginning Byte N
X
B
Y
T
E
S
ACK
O
O
O
O
O
O
Byte N + X - 1
N
NAK
P
stoP bit
SMBus Table 3: Read-Back Register
Name
Control
Function
FS vs. SMBus
prog
HW/SW select
Type
0
1
RW
HW
SW
Power
UP State
Byte 0
Pin #
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
0
Bit 0
-
0
RESERVED
IDT™ PCI CLOCK GENERATOR
0
RESERVED
0
0
0
Frequency
Selection
See Frequency table 4
0
0
5
MK1493-03B
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
SMBus Table 3 (cont.): Output Enable Control Register
Byte 1
Pin #
Name
Control
Function
Type
0
1
Power
UP State
Bit 7
40
PCICLK7
Output Control
RW
Disable
Enable
1
Bit 6
39
PCICLK6
Output Control
RW
Disable
Enable
1
Bit 5
38
PCICLK5
Output Control
RW
Disable
Enable
1
Bit 4
37
PCICLK4
Output Control
RW
Disable
Enable
1
Bit 3
31
PCICLK3
Output Control
RW
Disable
Enable
1
Bit 2
28
PCICLK2
Output Control
RW
Disable
Enable
1
Bit 1
27
PCICLK1
Output Control
RW
Disable
Enable
1
Bit 0
26
PCICLK0
Output Control
RW
Disable
Enable
1
0
1
Power
UP State
SMBus Table 3 (cont.): Output Enable Control Register
Name
Control
Function
Type
Byte 2
Pin #
Bit 7
-
RESERVED
0
Bit 6
-
RESERVED
0
Bit 5
32
CLK66
Output Control
RW
Disable
Enable
1
Bit 4
33
CLK66/71/83
Output Control
RW
Disable
Enable
1
Bit 3
13
REF25
Output Control
RW
Disable
Enable
1
Bit 2
19
CPUCLK
Output Control
RW
Disable
Enable
1
Bit 1
18
CPUCLK
Output Control
RW
Disable
Enable
1
Bit 0
21
CLK50
Output Control
RW
Disable
Enable
1
Type
0
1
Power
UP State
SMBus Table 3 (cont.): Frequency Control Register
Byte 3
Pin #
Name
Control
Function
Bit 7
4
-
FS0_A
RW
X
Bit 6
44
-
FS0_B
RW
X
Bit 5
3
-
FS1_A
RW
X
Bit 4
43
-
FS1_B
RW
X
Bit 3
2
-
FS2_A
RW
Bit 2
36
-
FS2_B
RW
X
Bit 1
1
-
FS3_A
RW
X
Bit 0
31
-
FS3_B
RW
X
IDT™ PCI CLOCK GENERATOR
See Frequency Table 1
6
X
MK1493-03B
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
SMBus Table 3 (cont.): Frequency Control Register
Byte 4
Pin #
Control Function
Type
0
1
Power
UP State
Bit 7
48
FS4_A
RW
X
Bit 6
24
FS4_B
RW
X
Bit 5
47
FS5_A
RW
X
Bit 4
23
FS5_B
RW
X
See Frequency Table 1
Bit 3
46
FS6_A
RW
Bit 2
22
FS6_B
RW
X
X
Bit 1
45
FS7_A
RW
X
Bit 0
20
FS7_B
RW
X
SMBus Table 3 (cont.): Frequency Control Register
Control Function
Type
0
1
Power
UP State
Bit 7
FS8
RW
CPU=125M
CPU=100M
1
Bit 6
FS9
RW
Bit 5
FS10
RW
Bit 4
RESERVED
-
0
Bit 3
RESERVED
-
1
Bit 2
RESERVED
-
1
Bit 1
RESERVED
-
1
Bit 0
RESERVED
-
1
Byte 5
Pin #
00=83.33M, 01=71.42M
10=66.66M, 11=OFF
0
0
SMBus Table 3 (cont.): Reserved
Control Function
Type
Bit 7
RESERVED
-
1
Bit 6
RESERVED
-
1
Bit 5
RESERVED
-
1
Bit 4
RESERVED
-
1
Bit 3
RESERVED
-
1
Bit 2
RESERVED
-
1
Bit 1
RESERVED
-
1
Bit 0
RESERVED
-
1
Byte 6
Pin #
IDT™ PCI CLOCK GENERATOR
0
1
7
Power
UP State
MK1493-03B
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
SMBus Table 3 (cont.): Vendor and Revision ID Register
Byte 7
Pin #
Control Function
Type
0
1
REVISION
Power
UP State
Bit 7
RID3
R
Bit 6
RID2
R
0
0
Bit 5
RID1
R
1
Bit 4
RID0
R
0
Bit 3
VID3
R
Bit 2
VID2
R
0
Bit 1
VID1
R
0
Bit 0
VID0
R
1
VENDOR ID
0
SMBus Table 3 (cont.): Byte Count Register
Control Function
Type
Bit 7
BC7
RW
Bit 6
BC6
RW
Bit 5
BC5
RW
Bit 4
BC4
RW
Bit 3
BC3
RW
1
Bit 2
BC2
RW
0
Bit 1
BC1
RW
0
Bit 0
BC0
RW
0
Byte 8
Pin #
0
1
Writing to this Register
will confirm how many
bytes will be read
back, default
08=8 bytes
Power
UP State
0
0
0
0
SMBus Table 3 (cont.): Reserved
Control Function
Type
Bit 7
RESERVED
-
1
Bit 6
RESERVED
-
1
Bit 5
RESERVED
-
1
Bit 4
RESERVED
-
1
Bit 3
RESERVED
-
1
Bit 2
RESERVED
-
1
Bit 1
RESERVED
-
1
Bit 0
RESERVED
-
1
Byte 9
Pin #
IDT™ PCI CLOCK GENERATOR
0
1
8
Power
UP State
MK1493-03B
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
SMBus Table 3 (cont.): Programming Enable
Name
Control Function
Type
0
1
Power
UP State
Bit 7
Programming
M/N
Enable
Enables prog
bytes
11-12
RW
Disabled
Enabled
0
Bit 6
RESERVED
RESERVED
RW
0
Bit 5
RESERVED
RESERVED
RW
0
Bit 4
RESERVED
RESERVED
RW
0
Bit 3
RESERVED
RESERVED
RW
0
Bit 2
RESERVED
RESERVED
RW
0
Bit 1
RESERVED
RESERVED
RW
0
Bit 0
RESERVED
RESERVED
RW
0
Name
Control Function
Type
Bit 7
N Div8
N Divider Bit 8
RW
X
Bit 6
M Div6
RW
X
Bit 5
M Div5
RW
X
Bit 4
M Div4
RW
X
Bit 3
M Div3
RW
X
Bit 2
M Div2
RW
X
Bit 1
M Div1
RW
X
Bit 0
M Div0
The decimal
representation of
M Div(6:0) is equal
to reference
divider value.
default
Powerup=latch-in
or Byte o ROM
table.
RW
X
Byte 10
Pin #
SMBus Table 3 (cont.): MN
Byte 11
Pin #
0
1
Power
UP State
SMBus Table 3 (cont.): MN
Name
Control Function
Type
Bit 7
N Div7
X
N Div6
RW
X
Bit 5
N Div5
RW
X
Bit 4
N Div4
RW
X
Bit 3
N Div3
RW
X
Bit 2
N Div2
RW
X
Bit 1
N Div1
RW
X
Bit 0
N Div0
The decimal
representation of
N Div(8:0) is equal
to feedback
divider value.
default
Powerup=latch-in
or Byte o ROM
table.
N Div8 is in byte11
RW
Bit 6
RW
X
Byte 12
Pin #
IDT™ PCI CLOCK GENERATOR
9
0
1
Power
UP State
MK1493-03B
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
Table 4. Frequency Margin Selection through SMBus (Byte 0)
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
CPUCLK 4
CPUCLK
(MHz)
CLK50 (MHz) 4
CLK66, 66/71/83
(MHz) 4
PCICLK (MHz) 4
0
0
0
0
0
100.00/125.00
50.00
66, 66/71/83
nominal
0
0
0
0
1
nominal + 1%
nominal + 1%
nominal + 1%
nominal + 1%
0
0
0
1
0
nominal + 2%
nominal + 2%
nominal + 2%
nominal + 2%
0
0
0
1
1
nominal + 3%
nominal + 3%
nominal + 3%
nominal + 3%
0
0
1
0
0
nominal + 4%
nominal + 4%
nominal + 4%
nominal + 4%
0
0
1
0
1
nominal + 5%
nominal + 5%
nominal + 5%
nominal + 5%
0
0
1
1
0
nominal + 6%
nominal + 6%
nominal + 6%
nominal + 6%
0
0
1
1
1
nominal + 7%
nominal + 7%
nominal + 7%
nominal + 7%
0
1
0
0
0
nominal + 8%
nominal+ 8%
nominal + 8%
nominal + 8%
0
1
0
0
1
nominal + 9%
nominal + 9%
nominal + 9%
nominal + 9%
0
1
0
1
0
nominal + 10%
nominal + 10%
nominal + 10%
nominal + 10%
0
1
0
1
1
nominal + 11%
nominal + 11%
nominal + 11%
nominal + 11%
0
1
1
0
0
nominal + 12%
nominal + 12%
nominal + 12%
nominal + 12%
0
1
1
0
1
nominal + 13%
nominal + 13%
nominal + 13%
nominal + 13%
0
1
1
1
0
nominal + 14%
nominal + 14%
nominal + 14%
nominal + 14%
0
1
1
1
1
nominal + 15%
nominal + 15%
nominal + 15%
nominal + 15%
1
0
0
0
0
nominal + 16%
nominal + 16%
nominal + 16%
nominal + 16%
1
0
0
0
1
nominal + 17%
nominal + 17%
nominal + 17%
nominal + 17%
1
0
0
1
0
nominal + 18%
nominal + 18%
nominal + 18%
nominal + 18%
1
0
0
1
1
nominal + 19%
nominal + 19%
nominal + 19%
nominal + 19%
1
0
1
0
0
nominal +20%
nominal +20%
nominal +20%
nominal +20%
1
0
1
0
1
nominal +21%
nominal +21%
nominal +21%
nominal +21%
1
0
1
1
0
nominal +22%
nominal +22%
nominal +22%
nominal +22%
1
0
1
1
1
nominal +23%
nominal +23%
nominal +23%
nominal +23%
1
1
0
0
0
nominal +24%
nominal +24%
nominal +24%
nominal +24%
1
1
0
0
1
nominal +25%
nominal +25%
nominal +25%
nominal +25%
1
1
0
1
0
nominal - 3%
nominal - 3%
nominal - 3%
nominal - 3%
1
1
0
1
1
nominal - 5%
nominal - 5%
nominal - 5%
nominal - 5%
1
1
1
0
0
nominal - 10%
nominal - 10%
nominal - 10%
nominal - 10%
1
1
1
0
1
nominal - 15%
nominal - 15%
nominal - 15%
nominal - 15%
1
1
1
1
0
nominal - 20%
nominal - 20%
nominal - 20%
nominal - 20%
1
1
1
1
1
nominal - 25%
nominal - 25%
nominal - 25%
nominal - 25%
4
The transition of each of these clock frequencies is
gradual.
IDT™ PCI CLOCK GENERATOR
10
MK1493-03B
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
External Components
Figure 1
The MK1493-03B requires a minimum number of external
components for proper operation.
V ia to
V DD
P rogramming
Header
Decoupling Capacitor
2K
V ia to G nd
Decoupling capacitors of 0.1µF and 0.001µF must be
connected between each VDD and GND (pins 12&9,
30&29, 40&41, 35&34, 6&5, 17&16, 14&15) as close to the
device as possible. For optimum device performance, the
decoupling capacitor should be mounted on the component
side of the PCB. Avoid the use of vias in the decoupling
circuit.
Device
Pad
8.2K
C lock trace to load
S eries Term. R es.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic
1) power supply or the GND (logic 0) voltage potential. A
10Kilo ohm (10 K) resistor is used to provide both the solid
CMOS programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance), place a 33Ω resistor in series with the clock
line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20Ω.
Figure 1 above shows a means of implementing this
function when a switch or 2-pin header is used. With no
jumpers installed the pin will be pulled high. With the jumper
in place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor
Crystal Information
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should
be connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
Crystal caps (pF) = (CL - 6) x 2
In the equation, CL is the crystal load capacitance. So, for a
crystal with a 16 pF load capacitance, two 20 pF [(16-6) x 2]
capacitors should be used.
Shared Pin Operation- Input/Output
Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level(voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
IDT™ PCI CLOCK GENERATOR
11
MK1493-03B
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MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1493-03B. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Recommended Operation Conditions
Item
Rating
Max Supply Voltage, VDD
5.5 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature (commercial)
0 to +70° C
Ambient Operating Temperature (industrial)
-40 to +85° C
Storage Temperature
-65 to +150° C
Junction Temperature
125° C
Soldering Temperature
260° C
Parameter
Min.
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
IDT™ PCI CLOCK GENERATOR
12
Max.
Units
0
+70
°C
-40
+85
°C
+3.45
V
+3.15
Typ.
3.3
MK1493-03B
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Current
IIH
VIN=VDD
-5
Input Low Current
IIL1
VIN=0V, SDA, SCL
no pull-up resistors.
-5
µA
IIL2
VIN=0V, All other inputs
with pull-up resistors
-200
µA
Supply Current
IDD
CL = full load
Input Frequency
FIN
Pin Inductance
LPIN
Input Capacitance
CIN
CLK Stabilization
2
Units
V
0.8
V
5
µA
155
mA
25
MHz
7
nH
Logic inputs
5
pF
COUT
Output pin capacitance
6
pF
CINX
X1 and X2 pins
5
pF
TSTAB
From VDD Power-up
3
ms
Electrical Characteristics - Input
Unless stated otherwise, VDD = 3.3 V±5%, CL=20 pF Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
Input Frequency
FIN
Crystal or clock input
25
SM Bus clock
SCL
SM Bus clock
100
Max. Units
MHz
110
KHz
Electrical Characteristics - CPUCLK (Single-ended)
Unless stated otherwise, VDD = 3.3 V±5%, CL=20 pF Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Output Frequency
FO1
Output Impedance
RDSP
VO = VDD*(0.5)
12
Output High Voltage
VOH
IOH = -12 mA,
2.4
Output Low Voltage
VOL
IOL = 12 mA,
0.3
Rise Time
tr
VOL = 0.4 V,
VOH = 2.4 V
2.0
ns
Fall Time
tf
VOH = 2.4 V,
VOL = 0.4 V
3.0
ns
Duty Cycle
dt
Measured @ VDD/2
C-C Jitter Single ended
IDT™ PCI CLOCK GENERATOR
100
Measured @ VDD/2
13
45
MHz
55
Ω
V
50
0.4
55
150
MK1493-03B
V
%
ps
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
Electrical Characteristics - CPUCLK, CPUCLK (CMOS complimentary)
Unless stated otherwise, VDD = 3.3 V±5%, CL= 20 pF, Ambient Temperature 0 to +70° C
Parameter
Output Impedance
Symbol
ZO
Output High Voltage
VOH2B
Output Low Voltage
VOL2B
Conditions
Vo=Vx
Min.
Typ.
Max. Units
15
55
2.4
Ohms
V
0.4V
V
Rise Time
VOL = 0.4 V,
VOH = 2.4 V
2
2
ns
Fall Time
VOH = 2.4 V,
VOL = 0.4 V
2
3
ns
VCM
Common Mode Voltage
1.5
V
Duty Cycle
Measured @ VDD/2
Jitter, Cycle-to-Cycle
Measured @ VDD/2
110
Output to Output Skew between
CPU to CPU clocks
Measured @ VDD/2
50
45
55
%
ps
Electrical Characteristics - CPUCLK, CPUCLK (CMOS complimentary)
Unless stated otherwise, VDD = 3.3 V±5%, CL= 20 pF, Ambient Temperature -40 to +85° C
Parameter
Output Impedance
Symbol
ZO
Output High Voltage
VOH2B
Output Low Voltage
VOL2B
Conditions
Vo=Vx
Min.
Typ.
15
Max. Units
55
2.4
Ohms
V
0.4V
V
Rise Time
VOL = 0.4 V,
VOH = 2.4 V
2
ns
Fall Time
VOH = 2.4 V,
VOL = 0.4 V
3
ns
VCM
Common Mode Voltage
1.5
V
Duty Cycle
Measured @ VDD/2
Jitter, Cycle-to-Cycle
Measured @ VDD/2
110
Output to Output Skew between
CPU to CPU clocks
Measured @ VDD/2
50
IDT™ PCI CLOCK GENERATOR
14
45
55
MK1493-03B
%
ps
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MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
Electrical Characteristics - CLK50M, CLK66M & CLK66M/71M/83M
Unless stated otherwise, VDD = 3.3 V±5%, CL= 20 pF, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
RDSP
VO = VDD*(0.5)
12
Output High Voltage
VOH
IOH = -12 mA
2.4
Output Low Voltage
VOL
IOL = 12 mA
0.3
Rise Time
tr
VOL = 0.4 V,
VOH = 2.4 V
2.0
ns
Fall Time
tf
VOH = 2.4 V,
VOL = 0.4 V
2.4
ns
Duty Cycle
Measured @ VDD/2
Cycle to Cycle Jitter
Measured @ VDD/2
45
55
Ω
Output Impedance
V
0.4
50
55
250
V
%
ps
Electrical Characteristics - PCICLK
Unless stated otherwise, VDD = 3.3 V±5%, CL=30 pF, Ambient Temperature 0 to +70° C
Parameter
Symbol
Conditions
Min.
Output Impedance
RDSP
VO = VDD*(0.5)
12
Output High Voltage
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
IOL = 1 mA
Rise Time
tr
VOL = 0.4 V,
VOH = 2.4 V
Fall Time
tf
VOH = 2.4 V,
VOL = 0.4 V,
Max. Units
55
Ω
V
0.55
V
2.0
2.4
ns
2.0
3.0
ns
50
55
%
Duty Cycle
Measured @ VDD/2
Output to Output Skew
Measured @ VDD/2
250
ps
Cycle to Cycle Jitter
Measured @ VDD/2
250
ps
IDT™ PCI CLOCK GENERATOR
15
45
Typ.
MK1493-03B
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
Electrical Characteristics - PCICLK
Unless stated otherwise, VDD = 3.3 V±5%, CL=30 pF, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
55
Ω
Output Impedance
RDSP
VO = VDD*(0.5)
12
Output High Voltage
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
IOL = 1 mA
Rise Time
tr
VOL = 0.4 V,
VOH = 2.4 V
3.0
ns
Fall Time
tf
VOH = 2.4 V,
VOL = 0.4 V,
3.0
ns
V
0.55
45
50
55
V
Duty Cycle
Measured @ VDD/2
%
Output to Output Skew
Measured @ VDD/2
250
ps
Cycle to Cycle Jitter
Measured @ VDD/2
250
ps
Electrical Characteristics - 25 MHz Reference
Unless stated otherwise, VDD = 3.3 V±5%, CL=20 pF VDD = 3.3 V, Ambient Temperature 0 to +70° C
Parameter
Symbol
Conditions
Min.
Output Frequency
FO
Output Impedance
RDSP
VO = VDD*(0.5)
20
Output High Voltage
VOH
IOH = -1 mA,
2.4
Output Low Voltage
VOL
IOL = 1 mA,
Typ.
Max. Units
25
MHz
60
Ω
V
0.4
V
Rise Time
tr
VOL = 0.4 V, VOH = 2.4 V
2.0
ns
Fall Time
tf
VOH = 2.4 V, VOL = 0.4 V
2.0
ns
Duty Cycle
Measured @ VDD/2
Jitter Cycle to Cycle
Measured @ VDD/2
45
50
55
150
%
ps
Electrical Characteristics - 25 MHz Reference
Unless stated otherwise, VDD = 3.3 V±5%, CL=20 pF VDD = 3.3 V, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Output Frequency
FO
Output Impedance
RDSP
VO = VDD*(0.5)
20
Output High Voltage
VOH
IOH = -1 mA,
2.4
Output Low Voltage
VOL
IOL = 1 mA,
Typ.
Max. Units
25
MHz
60
Ω
V
0.4
V
Rise Time
tr
VOL = 0.4 V, VOH = 2.4 V
2.0
ns
Fall Time
tf
VOH = 2.4 V, VOL = 0.4 V
2.0
ns
Duty Cycle
Measured @ VDD/2
Jitter Cycle to Cycle
Measured @ VDD/2
IDT™ PCI CLOCK GENERATOR
16
40
50
60
150
MK1493-03B
%
ps
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
Package Outline and Package Dimensions (48-pin TSSOP, 6.10 mm Body, .50mm pitch)
Package dimensions are kept current with JEDEC Publication No. 95
20
48
S YMB O L
E1
A
A1
A2
b
c
D
E
E1
e
L
E
INDEX
AREA
1 2
D
aaa
Millim e te rs
MIN
MAX
-1 .1 0
0 .0 5
0 .1 5
0 .8 5
1 .0 5
0 .1 7
0 .2 7
0 .0 9
0 .2 0
1 2 .4 0
1 2 .6 0
8 .1 0 B AS IC
6 .0 0
6 .2 0
0 .5 B AS IC
0 .5 0
0 .7 5
0°
8°
-0 .0 8
A
A2
A1
c
-Ce
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
MK1493-03BGLF
MK1493-03BGLFTR
MK1493-03BGILF
MK1493-03BGILFTR
MK1493-03BGLF
MK1493-03BGLF
1493-03BGIL
1493-03BGIL
Tubes
Tape and Reel
Tubes
Tape and Reel
48-pin TSSOP
48-pin TSSOP
48-pin TSSOP
48-pin TSSOP
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ PCI CLOCK GENERATOR
17
MK1493-03B
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MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
ERRATA
Changes from MK1493-03 to MK1493-03A Data Sheet
Page 1 The part number changed from MK1493-03 to MK1493-03A
FS11 on the block diagram is removed
Page 2, Table 2, FS11 column removed
Default Output clock value for CLK66M/71M/83M is 83M.
Page3 Pin 33 description/function changed from I/O pin to Output pin only. The FS11 input option is deleted
Page6 Table 3 Byte2, bit3 (pin13) and bit5 (pin32) changed from Disable upon power upon to Enable upon powerup.
Page 7 Table 3 Byte 5, Bit 4 changed from FS11 to reserved
Byte 5 bit 5 and 6 changed to 0 upon power up.
Page 8 Byte 7 bit 4 changed from 0 to 1
Page 13 SMBUs max clock speed increased from 64KHz to 110KHz
Page 17 Ordering Information changed from MK1493-03G to MK1493-03AG
Changes from MK1493-03A to MK1493-03B Data Sheet
Page 1 The part number changed from MK1493-03A to MK1493-03B
Page 8 SMBUS vendor Revision ID
Byte 7 Power up state changed from o to 1, Bit 4 Power up state changed from 1 to 0
Page 13 The fall time for CPUCLK (single ended) and complimentary the VOL=0.8V changed to VOL=0.4V
Page 16 The part ordering number changed from MK1493-03AG to MK1493-03BG; added LF.
IDT™ PCI CLOCK GENERATOR
18
MK1493-03B
REV H 051310
MK1493-03B
PCI CLOCK GENERATOR
CLOCK SYNTHESIZER
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© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
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trademarks used to identify products or services of their respective owners.
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