Analog Power AM60N10-13D N-Channel 100-V (D-S) MOSFET Key Features: • Low rDS(on) trench technology • Low thermal impedance • Fast switching speed VDS (V) 100 PRODUCT SUMMARY rDS(on) (mΩ) 13 @ VGS = 10V 14 @ VGS = 5.5V ID (A) 51 49 Typical Applications: • LED Inverter Circuits • DC/DC Conversion Circuits • Motor drives ABSOLUTE MAXIMUM RATINGS (TA = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Limit VDS Drain-Source Voltage 100 VGS Gate-Source Voltage ±20 a TC=25°C ID 51 Continuous Drain Current IDM Pulsed Drain Current b 200 TC=25°C IS 55 Continuous Source Current (Diode Conduction) a a T =25°C P 50 Power Dissipation C D TJ, Tstg -55 to 175 Operating Junction and Storage Temperature Range THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambient Maximum Junction-to-Case c Symbol Maximum RθJA 40 RθJC 3 Units V A A W °C Units °C/W Notes a. Package Limited b. Pulse width limited by maximum junction temperature c. Surface Mounted on 1” x 1” FR4 Board. © Preliminary 1 Publication Order Number: DS_AM60N10-13D_1A Analog Power AM60N10-13D Electrical Characteristics Parameter Symbol Gate-Source Threshold Voltage Gate-Body Leakage VGS(th) IGSS Zero Gate Voltage Drain Current IDSS On-State Drain Current a ID(on) Drain-Source On-Resistance a rDS(on) Forward Transconductance a Diode Forward Voltage a gfs VSD Test Conditions Static VDS = VGS, ID = 250 uA VDS = 0 V, VGS = ±20 V VDS = 80 V, VGS = 0 V VDS = 80 V, VGS = 0 V, TJ = 55°C VDS = 5 V, VGS = 10 V VGS = 10 V, ID = 20 A VGS = 5.5 V, ID = 16 A VDS = 15 V, ID = 20 A IS = 28 A, VGS = 0 V Min Typ Max 1 ±100 1 10 62.5 Unit V nA uA A 13 14 19 0.85 mΩ S V Dynamic b Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss VDS = 50 V, VGS = 5.5 V, ID = 20 A VDS = 50 V, RL = 2.5 Ω, ID = 20 A, VGEN = 10 V, RGEN = 6 Ω VDS = 15 V, VGS = 0 V, f = 1 Mhz 89 24 27 18 23 188 52 18691 346 328 nC ns pF Notes a. Pulse test: PW <= 300us duty cycle <= 2%. b. Guaranteed by design, not subject to production testing. Analog Power (APL) reserves the right to make changes without further notice to any products herein. APL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does APL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in APL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. APL does not convey any license under its patent rights nor the rights of others. APL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the APL product could create a situation where personal injury or death may occur. Should Buyer purchase or use APL products for any such unintended or unauthorized application, Buyer shall indemnify and hold APL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that APL was negligent regarding the design or manufacture of the part. APL is an Equal Opportunity/Affirmative Action Employer. © Preliminary 2 Publication Order Number: DS_AM60N10-13D_1A Analog Power AM60N10-13D Typical Electrical Characteristics 0.025 30 0.02 ID - Drain Current (A) RDS(on) - On-Resistance(Ω) TJ = 25°C 3.5V 0.015 0.01 4V,4.5V,6V,8V,10V 20 10 0.005 0 0 0 10 20 30 0 40 ID-Drain Current (A) 2 3 4 5 VGS - Gate-to-Source Voltage (V) 1. On-Resistance vs. Drain Current 2. Transfer Characteristics 0.05 100 TJ = 25°C ID = 20A TJ = 25°C 0.04 IS - Source Current (A) RDS(on) - On-Resistance(Ω) 1 0.03 0.02 0.01 0 10 1 0.1 0.01 0 2 4 6 8 10 0.2 0.4 0.6 0.8 1 1.2 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) 3. On-Resistance vs. Gate-to-Source Voltage 4. Drain-to-Source Forward Voltage 40 30000 F = 1MHz 25000 Capacitance (pf) ID - Drain Current (A) 10V,8V,6V,4.5V,4V 30 3.5V 20 Ciss 20000 15000 10000 10 5000 0 Coss Crss 0 0 0.2 0.4 0.6 0.8 0 10 15 20 VDS-Drain-to-Source Voltage (V) VDS - Drain-to-Source Voltage (V) 5. Output Characteristics © Preliminary 5 6. Capacitance 3 Publication Order Number: DS_AM60N10-13D_1A Analog Power AM60N10-13D Typical Electrical Characteristics 2.5 VDS = 50V ID = 20A RDS(on) - On-Resistance(Ω) (Normalized) VGS-Gate-to-Source Voltage (V) 10 8 6 4 2 0 2 1.5 1 0.5 0 50 100 150 200 -50 -25 Qg - Total Gate Charge (nC) 25 50 75 100 125 150 TJ -JunctionTemperature(°C) 7. Gate Charge 8. Normalized On-Resistance Vs Junction Temperature 1000 PEAK TRANSIENT POWER (W) 350 10 uS 100 100 uS 1 mS ID Current (A) 0 10 mS 10 100 mS 1 SEC 1 10 SEC 100 SEC DC 1 0.1 Idm limit 300 250 200 150 100 50 Limited by RDS 0.01 0.1 1 10 100 0 0.001 1000 0.01 0.1 1 10 100 1000 VDS Drain to Source Voltage (V) t1 TIME (SEC) 9. Safe Operating Area 10. Single Pulse Maximum Power Dissipation 1 D = 0.5 RθJA(t) = r(t) + RθJA 0.2 0.1 RθJA = 40 °C /W 0.1 0.05 P(pk) 0.02 0.01 t1 t2 Single Pulse TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 t1 TIME (sec) 11. Normalized Thermal Transient Junction to Ambient © Preliminary 4 Publication Order Number: DS_AM60N10-13D_1A Analog Power AM60N10-13D Package Information Note: 1. All Dimension Are In mm. 2. Package Body Sizes Exclude Mold Flash, Protrusion Or Gate Burrs. Mold Flash, Protrusion Or Gate Burrs Shall Not Exceed 0.10 mm Per Side. 3. Package Body Sizes Determined At The Outermost Extremes Of The Plastic Body Exclusive Of Mold Flash, Gate Burrs And Interlead Flash, But Including Any Mismatch Between The Top And Bottom Of The Plastic Body. © Preliminary 5 Publication Order Number: DS_AM60N10-13D_1A