5 4 3 2 1 LAN9500 / LAN9500A USB 2.0 -to- 10/100 Ethernet w / MII Customer Evaluation Board Assy 6516 D D PCB Revision C Schematic Revision 1.2 Design Details Board: Assy 6516 Chip: SMSC LAN9500 / LAN9500A Circuit Diagrams utilizing SMSC Products Are Included As A Means Of Illustrating Typical Semiconductor Applications: Consequently Complete Information Sufficient For Construction Purposes Is Not Necessarily Given. The Information Has Been Carefully Checked And Is Believed To Be Entirely Reliable. However, No Responsibility Is Assumed For Inaccuracies. Furthermore, Such Information Does Not Convey To The Purchaser Of The Semiconductor Devices Described Any License Under The Patent Rights Of SMSC Or Others. SMSC Reserves The Right To Make Changes At Any Time In Order To Improve Design And Supply The Best Product Possible. Board Form Factor: USB / MII Stand-Alone C Assembly: 56 Lead QFN w/ Exposed GND Pad Revision History ITEM BLOCK DIAGRAM Rev 1.0: Page(s) Title Page 1 LAN9500 / LAN9500A, USB / Ethernet 2 3 Power / MII / uWire EEPROM / Misc. Unreleased, Rev B C Rev 1.1: Relabeled RJ45 LEDs B Rev 1.2: B Added support for LAN9500A R59 changed from 39.2K to 20.5K. R60 changed from 69.8K to 41.2K R63 10.0K added as rework to U3, Pin-5. A A Title LAN9500 / LAN9500A USB 2.0 -to- 10/100 Ethernet w/ MII Size Engineer Assembly No. R. W. Date: 5 4 3 2 6516 Friday, May 21, 2010 1 PCB Rev Schematic Rev C Sheet 1.2 1 of 2 5 4 3 2 1 VDD33A NOTE: Place 49.9 Ohm resistors near LAN9500 / LAN9500A. Place 0 Ohm / 10 Ohm resistor near transformers. +3.3V TEST1 TEST2 CHS GND C1 0.022uF 50V 10% 0805 YEL nPHY_INT 1 1 NOTE: In an EMI constrained environment, populate these capacitors. These components must be placed close to the transformer. 2 R44 nSPD_LED/GPIO10 1x2 NC XO XI Device LAN9500 LAN9500A * 1.00M 1 DNP R22 1M Ohm 1% DNP * Default Configuration 50V EP 1 57 10% LED1 nFDX_LED/GPIO8 R21 1 10M 2 5% 1/10W 2 3 2 2 2 2 2 2 2 2 2 2 TXD1/GPIO5/RMT_WKP 1 JP3 1 C22 1.0uF 16V 10% 2 +3.3V 3 1x3 2 1 1 USBDM USBDP 16V 10% C24 50V +3.3V EECLK/PWR_SEL 4700pF 10% 2 R28 5% 10.0K R42 DNP EEDO/AUTOMDIX_EN 1 2 10.0K 1 VCC 2 3 DD+ 4 GND 5 6 SHLD1 SHLD2 B USB Type-B Right Angle AMP_292304-1 1 R41 DNP TXD3/GPIO7/EEP_SIZE P1 R35 DNP 2 10.0K 1x10 C23 0.1uF +3.3V 10.0K R46 DNP TXD2/GPIO6/PORT_SWAP FB3 0.5amp 120 Ohm 100MHz 1 2 +3.3V PHY_SEL 10.0K R45 DNP 10.0K 10.0K 10.0K 10.0K 10.0K 10.0K 10.0K 10.0K Notes: JP3(1-2)=External Ehternet PHY. JP3(2-3)=Internal Ehternet PHY. 1 1 +3.3V 1 R33 DNP 2 DNP DNP DNP DNP DNP DNP DNP DNP 1 1 1 1 1 1 1 1 2 Ethernet 2 B R30 R32 R34 R36 R38 R40 R37 R39 1 LED_0805 VCC_USB COL/GPIO0 MDIO/GPIO1 MDC/GPIO2 CRS/GPIO3 TXD0/GPIO4/EEP_DISABLE TXD1/GPIO5/RMT_WKP TXD2/GPIO6/PORT_SWAP TXD3/GPIO7/EEP_SIZE R20 332 1% 1/10W FDX C9 30pF 50V 5% +3.3V J3 C 4700pF 2 LAN9500 / LAN9500A TXD0/GPIO4/EEP_DISABLE 2 1% +3.3V C6 1 Y1 25.000MHz HC49US 2 1 C10 30pF 50V 5% 1 2 3 4 5 6 7 8 9 10 +3.3V 332 1 1/10W 19 18 R22 2 +3.3V SPD 49 13 JP1 14 A C5 15pF 50V 5% DNP 12 12.0K 2 1% C4 15pF 50V 5% DNP C R15 1 16 C3 15pF 50V 5% DNP NC 8 2 kV 11 1% C2 15pF 50V 5% DNP Device R14 LAN9500 12.4K Ohm 1% LAN9500A * 12.0K Ohm 1% * Default Configuration 6 1000 pF 7 MTG 8 12.0K 2 7&8 MTG VBUS_DET 3 3 75 16 EXRES USBRBIAS TEST3 A 2 VBUS_DET LAN9500/LAN9500A 33 9 10 1 1 RD- 20 nPHY_INT C 2 2 6 VBUS_DET 75 15 PHY_SEL RXCT USBDP USBDM USBDP USBDM 5 12 11 1 75 RCV GND 34 RD+ GND PHY_SEL 3 14 EECLK/PWR_SEL EECS EEDO/AUTOMDIX_EN EEDI nFDX_LED/GPIO8 nLNKA_LED/GPIO9 nSPD_LED/GPIO10 13 29 30 31 32 26 27 28 1 EECLK/PWR_SEL EECS EEDO/AUTOMDIX_EN EEDI 2 nFDX_LED/GPIO8 nLNKA_LED/GPIO9 nSPD_LED/GPIO10 2 nRESET 4&5 75 TD- 1 24 TXCT 2 R14 1 D TD+ 4 RXP RXN U1 RJ45 1 6 5 RXP RXN 2 nRESET Pulse - J0011D01BNL * Default Configuration 1 RXCLK RXDV TXEN RXER CRS/GPIO3 COL/GPIO0 TXCLK TXD3/GPIO7/EEP_SIZE TXD2/GPIO6/PORT_SWAP TXD1/GPIO5/RMT_WKP TXD0/GPIO4/EEP_DISABLE LINK/ACT C 4 7 9 15 VDD33A VDD33A/NC VDD33A VDD33A 25 35 48 51 52 VDD33IO VDD33IO VDD33IO VDD33IO VDD33IO VDDPLL VDDUSBPLL 41 42 43 44 45 46 47 53 54 55 56 T1 2 EECLK/PWR_SEL EECS EEDO/AUTOMDIX_EN EEDI RXCLK RXDV TXEN RXER CRS/GPIO3 COL/GPIO0 TXCLK TXD3/GPIO7/EEP_SIZE TXD2/GPIO6/PORT_SWAP TXD1/GPIO5/RMT_WKP TXD0/GPIO4/EEP_DISABLE R7 10 Ohm 1% 0 Ohm 1 3 3 3 3 nTRST/RXD0 TDO/nPHY_RST TCK/RXD1 TMS/RXD2 TDI/RXD3 TXP TXN 2 3 nRESET 36 37 38 39 40 Device LAN9500 LAN9500A * R7 0 +3.3V 332 2 1% GRN 1 RXCLK RXDV TXEN RXER CRS/GPIO3 COL/GPIO0 TXCLK TXD3/GPIO7/EEP_SIZE TXD2/GPIO6/PORT_SWAP TXD1/GPIO5/RMT_WKP TXD0/GPIO4/EEP_DISABLE nTRST/RXD0 TDO/nPHY_RST TCK/RXD1 TMS/RXD2 TDI/RXD3 R6 49.9 1/10W 1% R61 1 XMIT 2 3 3 3 3 3 3 3 3 3 3 3 MDC/GPIO2 MDIO/GPIO1 R5 49.9 1/10W 1% nLNKA_LED/GPIO9 TXP TXN 3 2 1 3 TCK/RXD1 3 TMS/RXD2 3 TDI/RXD3 22 23 R4 49.9 1/10W 1% 2 3 nTRST/RXD0 MDC/GPIO2 MDIO/GPIO1 R3 49.9 1/10W 1% 1 3 MDC/GPIO2 3 MDIO/GPIO1 10 17 21 50 VDDCORE VDDCORE D 1 VDD33A 2 +3.3V 1 VDDUSBPLL VDDCORE VDDPLL 10M 1/10W R29 0 GND_USB 2 10.0K GPIO Header + Straps USB Connector Straps +3.3V +3.3V VDD33A VDDCORE VDDUSBPLL +3.3V C21 0.1uF 16V 10% C28 0.1uF 16V 10% 1OE 1A TCK/RXD1 4 5 2OE 2A TMS/RXD2 10 9 3OE 3A TDI/RXD3 13 12 4OE 4A 1B 3 nTRST 2B 6 TCK 3B 8 TMS 4B 11 TDI 1 1 1 2 R24 10.0K 1/10W 1% 2x10 JTAG HEADER A R27 1.00K 1/10W 1% DNP 1 7 2 JP2 1x2 R25 10.0K 1/10W 1% DNP 2 1 nTRST/RXD0 2 14 U2 SN74CBTLV3125PW 2 C27 0.1uF 16V 10% 2 2 C20 0.1uF 16V 10% 1 1 1 1 C19 0.1uF 16V 10% 2 C18 0.1uF 16V 10% 2 C26 0.1uF 16V 10% 2 2 C25 0.1uF 16V 10% 1 1 1 1 2 C17 0.1uF 16V 10% 2 4 6 8 10 12 14 16 18 20 2 VDDPLL FB4 0.5amp 120 Ohm 100MHz 1 2 1 VDDCORE 2 +3.3V A nTRST 1 1 TDO/nPHY_RST3 TDI 5 TMS 7 TCK 9 11 13 15 17 19 R23 3.32K 1/10W 1% VCC J2 TP2 2 R26 0 DNP C16 0.1uF 16V 10% GND 1 +3.3V C15 0.1uF 16V 10% 2 C14 0.1uF 16V 10% 2 2 0.5amp 120 Ohm 100MHz 2 C13 0.1uF 16V 10% 2 C12 0.1uF 16V 10% 2 2 C11 0.1uF 16V 10% 1 1 1 1 2 1 1 0.5amp 120 Ohm 100MHz 1 FB2 1 FB1 Bypass and Filtering NOTE: Populate JP2 and R27 when using external JTAG. JTAG Title LAN9500 / LAN9500A, USB / Ethernet / JTAG Size C Date: 5 4 3 2 Engineer Assembly No. R. W. 6516 Friday, May 21, 2010 1 PCB Rev Schematic Rev C Sheet 1.2 2 of 3 5 4 3 2 1 +3.3V JP4 2 J4 1 CS 4 2 6 VCC 5 1 GND 2 EEDI EEDI 2 D R49 10.0K 1/10W 1% DNP NOTE: Pull-down resistor R63 on U3-Pin 5 (EEPROM chip select (CS) signal) has been added in rework. R63 10.0K 1/16W 1% 93AA56A-OT SOT23-6 NOTE: 256 BYTE EEPROM. 2 R48 10.0K 1/10W 1% 1 2 CLK DO MDIO/GPIO1 TXEN Microwire Serial EEPROM +3.3V 1 MDC/GPIO2 TMS/RXD2 nTRST/RXD0 RXCLK TXER TXEN TXD1/GPIO5/RMT_WKP TXD3/GPIO7/EEP_SIZE CRS/GPIO3 EECS +3.3V U4 MIC6315 SOT-143_BIG1 VTH = 2.93 V Treset = 20 mS 1 1 41 42 R51 10.0K 1/10W 1% +3.3V 1 HEADER_2x11 S1 1 VCC 3 MR 2 100 1/10W 1% 2 nRESET 2 RESET C nRESET 2 1 J5 4 R62 10.0K 1/10W 1% TP3 1 R52 2 C30 0.1uF 16V 10% 2 C 2 4 6 8 10 12 14 16 18 20 22 DI 2 J6 1 3 5 7 9 11 13 15 17 19 21 MDIO/GPIO1 TDI/RXD3 TCK/RXD1 RXDV RXER TXCLK TXD0/GPIO4/EEP_DISABLE TXD2/GPIO6/PORT_SWAP COL/GPIO0 3 EECLK/PWR_SEL Chassis1 Chassis2 MII Test Points 2 EECS R47 10.0K 1/10W 1% 2 EECLK/PWR_SEL DNP EEDO/AUTOMDIX_EN C29 0.1uF 16V 10% GND 1 1% 1/10W 49.9K R50 +3.3V 1 TXCLK TXEN TXD0/GPIO4/EEP_DISABLE TXD1/GPIO5/RMT_WKP TXD2/GPIO6/PORT_SWAP TXD3/GPIO7/EEP_SIZE COL/GPIO0 CRS/GPIO3 U3 2 EEDO/AUTOMDIX_EN 1 2 2 2 2 2 2 2 2 MDIO/GPIO1 MDC/GPIO2 TDI/RXD3 TMS/RXD2 TCK/RXD1 nTRST/RXD0 RXDV RXCLK RXER TXER TXCLK TXEN TXD0/GPIO4/EEP_DISABLE TXD1/GPIO5/RMT_WKP TXD2/GPIO6/PORT_SWAP TXD3/GPIO7/EEP_SIZE COL/GPIO0 CRS/GPIO3 2 MDIO/GPIO1 MDC/GPIO2 TDI/RXD3 TMS/RXD2 TCK/RXD1 nTRST/RXD0 RXDV RXCLK RXER 2 D 2 2 2 2 2 2 2 2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 2 1x2 MII Connector RA Female 1 1 +5V 1x2 MII Reset R53 R54 MTG1 1 0 B MTG2 1 NC NC 0 B NUM3 Plated Hole .250 Dia. R55 1 NUM3 Plated Hole .250 Dia. R56 MTG3 MTG4 1 NC 0 NC 0 NUM3 Plated Hole .250 Dia. Note: R59 changed from 39.2K to 20.5K. R60 changed from 69.8K to 41.2K from Rev. 1.0 to Rev 1.1. Rev 1.0 was never built. NUM3 Plated Hole .250 Dia. Mounting Holes NOTE: JP5 and JP7 should be populated identically. +3.3V VCC_USB VCC_USB 2 GND - C33 1.0uF 16V 10% 1 C34 1.0uF 16V 10% LP38693MP-3.3 SOT223_5 500mA 1 1x3 C32 22uF 16V 10% 2 C35 0.1uF 16V 10% TP4 DNP 2 C31 0.1uF 16V 10% 1 2 3 + 3 1 2 VOUT 2 1 2A/125V GND INT +5V_BRICK JP6 VIN VEN NC 2 3 2 1 C36 0.1uF 16V 10% 20.5K 1/10W 1% 2 1 2 R60 41.2K 1/10W 1% 1 1 +V A 4 1 2 2 Pin 5 is TAB 1 1 F1 2 2 1 1 3 VR1 +5V GND JP5 R59 2 JP7 +5V_BRICK 5 P2 1 A POWER 2 POWER SUPPLY R57 604 1/10W 1% Note: LP38693 requires only 55uA typ, 100uA max quiescent current. Also requires only 1uF on Vin and Vout pins. Has extremely low dropout voltage of 250mV @ 500mA. LED2 LED_0805 Title 1 2 VBUS_DET +3.3V 0 1 R58 2 1x3 Power VBUS_DET Power / MII / uWire EEPROM / Misc. Size C Date: 5 4 3 2 Engineer Assembly No. R. W. 6516 Friday, May 21, 2010 1 PCB Rev Schematic Rev C Sheet 1.2 3 of 3