5 4 3 2 1 LAN9730 HSIC USB 2.0 to 10/100 Ethernet w / MII Interface Customer Evaluation Board D D PCB Revision A Schematic Revision 1.2 Design Details Board: Assy 6660 Chip: SMSC LAN9730 Circuit Diagrams utilizing SMSC Products Are Included As A Means Of Illustrating Typical Semiconductor Applications: Consequently Complete Information Sufficient For Construction Purposes Is Not Necessarily Given. The Information Has Been Carefully Checked And Is Believed To Be Entirely Reliable. However, No Responsibility Is Assumed For Inaccuracies. Furthermore, Such Information Does Not Convey To The Purchaser Of The Semiconductor Devices Described Any License Under The Patent Rights Of SMSC Or Others. SMSC Reserves The Right To Make Changes At Any Time In Order To Improve Design And Supply The Best Product Possible. Board Form Factor: 3.7" x 2.575" C Revision History ITEM BLOCK DIAGRAM Rev 1.0: Initial Release C Page Title Page 1 Power and Reset 2 LAN9730 3 Page 3: R49 changed from a pull-down to a pull-up. Rework required to connect R49 to +3.3V. Rev 1.1: B B Page 3: Corrected part number for R15 & R16. BOM change only. Rev 1.2: Page 1: Corrected Title A A Title LAN9730 CEB with MII Size C Date: 5 4 3 2 Assembly No. Engineer J.M. 6660 Friday, April 13, 2012 1 PCB Rev Schematic Rev A Sheet 1.2 1 of 3 5 4 3 +5V Brick Supply +3.3V Regulator +5V P1 1 Optional +1.2V Regulator VR1 +3.3V VR2 +1.2V 1 1 + FAN1112SX - C7 22uF 16V 10% 2 1 Vout Vout 2 4 2 - C6 0.1uF 16V 10% 2 - C5 10uF 16V 20% 1 + C4 10uF 16V 20% Vin 1 1 1 + 2 LT1086CM-3.3 C3 0.1uF 16V 10% 2 1 R1 1.0K 1/8W 1% DNP 2 - Vout Vout 3 1 C2 10uF 16V 20% 2 4 2 2 1 2.1mm ID 5p5mm OD + C1 0.1uF 16V 10% Gnd D1 SMA6J6.0A 6V 2 Vin 1 2A/125V 1 2 3 1 2 2 3 1 GND F1 1 D 2 C8 0.1uF 16V 10% D 2 R2 0 Optional POR Circuit +3.3V C9 0.1uF 16V 10% U1 3 C +3.3V TPS3125 SOT23-5 Threshold = 2.64V Delay = 180ms +3.3V C10 0.1uF 16V 10% 1 J1 1 RESET 1 INA 2 INB 1 1 1 3 4 1 2 nRESET 3 U2 74LVC1G08 SOT23-5 1 TP1 Test Point - White 2 R7 1.00K 1/10W 1% 2 2 J2 2 JP1 GND R6 10.0K JP5 Y 1 +3.3V R5 10.0K 1/10W 1% 2 2 RESET# 5 MR# VCC 4 2 1 2 1/10W 1% 1 1 R4 100 2 2 S1 GND 1 C VDD 2 2 R3 10.0K 5 1 1 +3.3V NOTE: Use J2 to cable reset over from host. If Host is an FPGA platform, R7 will hold nRST low until FPGA configures and can drive nRST high. Remove JP1 to use on board reset only. B B Power LED Test Points +3.3V 1 TP2 1 +5V 2 R8 332 1 TP3 Test Point - Red +5V 1 TP6 Test Point - Orange +3.3V 1 TP9 Test Point - Green +1.2V 2 +3.3V LED1 LED_0805 1 +1.2V 1 TP4 DNP 1 TP5 1 TP7 1 TP8 1 TP10 A A Mount Holes MTG1 MTG2 MTG3 MTG4 1 1 1 1 NC NC NC NC Title LAN9730 CEB with MII NUM3 Plated Hole .250 Dia. NUM3 Plated Hole .250 Dia. NUM3 Plated Hole .250 Dia. NUM3 Plated Hole .250 Dia. Size Assembly No. Engineer J.M. Date: 5 4 3 2 6660 Friday, April 13, 2012 1 PCB Rev Schematic Rev A Sheet 1.2 2 of 3 3 2 10/100 Ethernet NOTE: Place 49.9 ohm resistors near LAN9730. Place 0 ohm resistor near transformer. VDD12PLL VDD12USBA VDD12USBPLL +3.3V nLNKA_LED 7 EXRES U.FL SMD Coax USBRBIAS 16 USBRBIAS CORE_REG_EN 49 CORE_REG_EN nPHY_INT C 1 2 1 2 RJ45 1 TD+ 4 TXCT 4&5 2 TD- 2 3 RD+ 5 RXCT 7&8 6 RD- 6 7 NC 8 CHS GND 75 1 75 1 1000 pF SPD 2 1 19 18 EP 57 C16 33pF 50V 5% LAN9730 C 1 Y1 25.000MHz HC49US nSPD_LED/GPIO10 nLNKA_LED/GPIO9 nFDX_LED/GPIO8 0 1210 1 3 5 C17 33pF 50V 5% 2 4 6 R18 1 2 332 R19 1 2 332 nLNKA_LED C MII Interface 1 +3.3V nPHY_INT 1 JTAG Header 1 2 TP13 1 2 2 NOTE: Use TP13 to cable nPHY_RST to external PHY. 2 4 6 8 10 12 14 16 18 20 +3.3V Test Points R28 0 C28 10uF 16V 20% Connector R39 49.9K 1/10W 1% J7 1 3 5 7 9 11 13 15 17 19 21 MDIO/GPIO1 TDI/RXD3 TCK/RXD1 RXDV RXER TXCLK TXD0/GPIO4/EEP_DISABLE TXD2/GPIO6/PORT_SWAP COL/GPIO0 C36 0.1uF 16V 10% Test Straps 2 4 6 8 10 12 14 16 18 20 22 MDC/GPIO2 TMS/RXD2 nTRST/RXD0 RXCLK TXER TXEN TXD1/GPIO5/RMT_WKP TXD3/GPIO7/50DRIVER_EN CRS/GPIO3 +5V +3.3V Core Regulator Enable 0 0 Rework Note: R49 connected to +3.3V in rework (formerly connected to GND). TEST2 must always be connected to +3.3V for revision A devices and must always be connected to VSS for subsequent revisions. Please refer to the LAN9730(i) Anomaly Sheet for details. +3.3V JP9 1 CORE_REG_EN R48 R49 2 3 Optional EEPROM U5 R29 10.0K PHY_SEL 1 +3.3V R27 10.0K 1 2 SLEW_TUNE 2 +3.3V JP8 R33 10.0K 1 1 TXD3/GPIO7/50DRIVER_EN 2 2 1 2 R34 10.0K TXD0/GPIO4/EEP_DISABLE 1 2 3 +3.3V EEDO/AUTOMDIX_EN EEDI EECLK/PWR_SEL JP11 1 2 EECS 3 1 JP12 1 R35 10.0K EECLK/PWR_SEL 1 2 2 3 +3.3V JP13 1 R36 10.0K TXD1/GPIO5/RMT_WKP 1 2 2 +3.3V JP14 1 R37 10.0K TXD2/GPIO6/PORT_SWAP 3 1 2 2 +3.3V JP15 1 R38 10.0K EEDO/AUTOMDIX_EN 1 2 DI DO CLK 1 6 7 CS NC NC VCC R44 10.0K 1/10W 1% +3.3V COL/GPIO0 MDC/GPIO2 CRS/GPIO3 8 2Kbit 2 2 +3.3V 3 4 2 JP7 2 3 1 3 JP10 1 DNP GPIO Pull-ups +3.3V 1 +3.3V JP4 3 R30 R32 R31 GND 93LC56A/SN SOIC-8 Title LAN9730 CEB with MII Size Date: 4 3 2 A 5 Assembly No. Engineer J.M. 5 2 10.0K DNP 2 10.0K DNP 2 10.0K DNP 1 1 1 C37 0.1uF 16V 10% 2 3 MII Connector RA Female AMP 5787170-4 2 Configuration Straps A B 41 42 TEST1 TEST2 J5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 2 1 3 5 7 9 11 13 15 17 19 2 1 2 2.0A/120 Ohm/100MHz 1 J6 nTRST/RXD0 TDO/nPHY_RST TDI/RXD3 TMS/RXD2 TCK/RXD1 VDD12USBA FB4 R26 10.0K 1/10W 1% - 1 NOTE: Place the 1uF at pin 17 R25 10.0K 1/10W 1% 2 2 C35 0.1uF 16V 10% 1 C34 1.0uF 16V 10% DNP 1 1 2 1 2 2.0A/120 Ohm/100MHz R24 10.0K 1/10W 1% 2 1 R23 10.0K 1/10W 1% 1 +3.3V + 2 1 MDIO/GPIO1 MDC/GPIO2 TDI/RXD3 TMS/RXD2 TCK/RXD1 nTRST/RXD0 RXDV RXCLK RXER TXER TXCLK TXEN TXD0/GPIO4/EEP_DISABLE TXD1/GPIO5/RMT_WKP TXD2/GPIO6/PORT_SWAP TXD3/GPIO7/50DRIVER_EN COL/GPIO0 CRS/GPIO3 TP11 VDD12USBPLL R21 10.0K Chassis1 Chassis2 2 2 1 C27 0.1uF 16V 10% 2 1 2 1 2 C26 0.1uF 16V 10% C33 0.1uF 16V 10% FB3 B 1 2 1 2 1 C32 0.1uF 16V 10% NOTE: Place the 1uF at pin 50 C25 0.1uF 16V 10% 2 1 1 2 2.0A/120 Ohm/100MHz 2 1 2 2 C31 0.1uF 16V 10% C24 0.1uF 16V 10% VDD12PLL FB2 C30 1.0uF 16V 10% C23 0.1uF 16V 10% 1 VDD12CORE 2 NOTE: JP2 must NOT be installed when using internal regulator C22 1.0uF 16V 10% 2 1 C21 0.1uF 16V 10% 2 C20 0.1uF 16V 10% 2 1 1 1 R20 10.0K DNP R40 10.0K 1/10W 1% 2 JP2 DNP 1 1 +1.2V C19 0.1uF 16V 10% 2 1 C18 1.0uF 16V 10% 2 1 2 2.0A/120 Ohm/100MHz 1 +3.3V 2 VDD33A FB1 +5V +3.3V nPHY_INT LAN9730 Bypass +3.3V LED2 LED_0805 FDX 2 JP6 2 2 PHY_SEL +3.3V A C MTG MTG 11 NOTE: Place EMI caps close to the transformer. 2 kV YEL GND C15 0.022uF 50V 10% GND C14 15pF 50V 5% DNP 2 1 2 1 2 1 2 1 2 C13 15pF 50V 5% DNP R17 XO XI D 3 75 16 nPHY_INT C12 15pF 50V 5% DNP 15 1 R16 12.0K 1/10W 1% C11 15pF 50V 5% DNP 14 TEST1 TEST2 J3 75 13 33 13 3 34 GRN XMIT 1 TEST1 TEST2 R15 12.0K 1/10W 1% 2 PHY_SEL 1 2 20 U.FL SMD Coax 1 J4 1 EECLK/PWR_SEL EECS EEDO/AUTOMDIX_EN EEDI 1 SLEW_TUNE EXRES Pulse - J0011D01BNL R14 0 RCV 2 nRESET 29 30 31 32 10 11 HSIC1_DATA HSIC1_STROBE SLEW_TUNE R13 49.9 1/10W 1% HSIC Coax 1 24 nFDX_LED/GPIO8 nLNKA_LED/GPIO9 nSPD_LED/GPIO10 HSIC_DATA HSIC_STROBE R12 49.9 1/10W 1% LINK/ACT 6 5 26 27 28 nFDX_LED/GPIO8 nLNKA_LED/GPIO9 nSPD_LED/GPIO10 2 1 4 8 15 VDD33IO VDD33IO VDD33IO VDD33IO VDD33IO VDD33A VDD33A VDD33A 25 35 48 51 52 12 9 VDD12PLL 17 VDD12A VDD12USBPLL 21 50 MDC/GPIO2 MDIO/GPIO1 TXER nTRST/RXD0 TDO/nPHY_RST TCK/RXD1 TMS/RXD2 TDI/RXD3 RXCLK RXDV TXEN RXER CRS/GPIO3 COL/GPIO0 TXCLK TXD3/GPIO7/50DRIVER_EN TXD2/GPIO6/PORT_SWAP TXD1/GPIO5/RMT_WKP TXD0/GPIO4/EEP_DISABLE R11 49.9 1/10W 1% 3 2 1 EECLK/PWR_SEL EECS EEDO/AUTOMDIX_EN EEDI RXP RXN 22 23 14 36 37 38 39 40 41 42 43 44 45 46 47 53 54 55 56 R10 49.9 1/10W 1% 1 2 nRESET TXP TXN 2 MDC/GPIO2 MDIO/GPIO1 TXER nTRST/RXD0 TDO/nPHY_RST TCK/RXD1 TMS/RXD2 TDI/RXD3 RXCLK RXDV TXEN RXER CRS/GPIO3 COL/GPIO0 TXCLK TXD3/GPIO7/50DRIVER_EN TXD2/GPIO6/PORT_SWAP TXD1/GPIO5/RMT_WKP TXD0/GPIO4/EEP_DISABLE 10 VDD33A T1 VDD12CORE VDD12CORE D 2 332 VDD33A +3.3V VDD12CORE U3 R9 1 9 LAN9730 1 A 4 12 5 6660 Friday, April 13, 2012 1 PCB Rev Schematic Rev A Sheet 1.2 3 of 3