Si7270DP-DS

SPICE Device Model Si7270DP
Vishay Siliconix
Dual N-Channel 30 V (D-S) MOSFET
DESCRIPTION
CHARACTERISTICS
The attached SPICE model describes the typical electrical
characteristics of the n-channel vertical DMOS. The
subcircuit model is extracted and optimized over the - 55 °C
to + 125 °C temperature ranges under the pulsed 0 V to 10 V
gate drive. The saturated output impedance is best fit at the
gate bias near the threshold voltage. A novel gate-to-drain
feedback capacitance network is used to model the gate
charge characteristics while avoiding convergence
difficulties of the switched Cgd model. All model parameter
values are optimized to provide a best fit to the measured
electrical data and are not intended as an exact physical
interpretation of the device.
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the - 55 °C to + 125 °C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse
Recovery Characteristics
SUBCIRCUIT MODEL SCHEMATIC
D
CGD
R1
3
M2
Gy
G
RG
–
+
ETCV
Gx
CGS
DBD
M1
S
Note
This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer to
the appropriate datasheet of the same number for guaranteed specification limits.
Document Number: 67150
S10-2447-Rev. A, 25-Oct-10
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SPICE Device Model Si7270DP
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SIMULATED MEASURED
DATA
DATA
SYMBOL
TEST CONDITIONS
VGS(th)
VDS = VGS, ID = 250 μA
1.7
-
VGS = 10 V, ID = 8 A
0.0178
0.0175
VGS = 4.5 V, ID = 6 A
0.0207
0.0205
UNIT
Static
Gate-Source Threshold Voltage
Drain-Source On-State Resistancea
RDS(on)
V

Forward Transconductancea
gfs
VDS = 10 V, ID = 8 A
24
31
S
Body Diode Voltage
VSD
IS = 3 A
0.76
0.77
V
866
900
149
150
57
60
VDS = 15 V, VGS = 10 V, ID = 10 A
13
14
6.3
6.6
VDS = 15 V, VGS = 4.5 V, ID = 10 A
2.5
2.5
1.7
1.7
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS = 15 V, VGS = 0 V, f = 1 MHz
pF
nC
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
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Document Number: 67150
S10-2447-Rev. A, 25-Oct-10
SPICE Device Model Si7270DP
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA TJ = 25 °C, unless otherwise noted
10
50
8
40
ID - Drain Current (A)
ID - Drain Current (A)
VGS = 10 V, 7 V, 6 V, 5 V, 4 V
30
20
10
TJ = 125 °C
6
TJ = 25 °C
4
2
VGS = 3 V
0
0.0
TJ = - 55 °C
0
0.5
1.0
1.5
2.0
2.5
0
1
0.025
1100
0.023
880
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
2
3
4
5
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
VGS = 4.5 V
0.021
0.019
Ciss
660
440
220
0.017
Coss
VGS = 10 V
Crss
0
0.015
0
8
16
24
32
0
40
5
ID - Drain Current (A)
10
15
20
25
30
1.0
1.2
VDS - Drain-to-Source Voltage (V)
100
10
10
8
TJ = 150 °C
IS - Source Current (A)
VGS - Gate-to-Source Voltage (V)
ID = 10 A
VDS = 15 V
6
VDS = 20 V
4
1
TJ = 25 °C
0.1
0.01
2
0.001
0
0
3
6
9
Qg - Total Gate Charge (nC)
12
15
0
0.2
0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)
Note
Dots and squares represent measured data.
Document Number: 67150
S10-2447-Rev. A, 25-Oct-10
www.vishay.com
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Document Number: 91000
Revision: 18-Jul-08
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