SiB417EDK-DS

SPICE Device Model SiB417EDK
Vishay Siliconix
P-Channel 1.2 V (G-S) MOSFET
DESCRIPTION
CHARACTERISTICS
The attached SPICE model describes the typical electrical
characteristics of the p-channel vertical DMOS. The
subcircuit model is extracted and optimized over the - 55 °C
to + 125 °C temperature ranges under the pulsed 0 V to 5 V
gate drive. The saturated output impedance is best fit at the
gate bias near the threshold voltage. A novel gate-to-drain
feedback capacitance network is used to model the gate
charge characteristics while avoiding convergence
difficulties of the switched Cgd model. All model parameter
values are optimized to provide a best fit to the measured
electrical data and are not intended as an exact physical
interpretation of the device.
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the - 55 °C to + 125 °C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse
Recovery Characteristics
SUBCIRCUIT MODEL SCHEMATIC
D
CGD
R1
3
M2
Gy
G
RG
+ –
ETCV
Gx
CGS
DBD
M1
S
Note
This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer to
the appropriate datasheet of the same number for guaranteed specification limits.
Document Number: 66505
S10-0747-Rev. A, 05-Apr-10
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SPICE Device Model SiB417EDK
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
SIMULATED MEASURED
DATA
DATA
UNIT
Static
Gate-Source Threshold Voltage
Drain-Source On-State Resistancea
VGS(th)
RDS(on)
VDS = VGS, ID = - 250 μA
0.74
-
VGS = - 4.5 V, ID = - 5.8 A
0.048
0.042
VGS = - 2.5 V, ID = - 5 A
0.066
0.058
V

Forward Transconductancea
gfs
VDS = - 10 V, ID = - 5.8 A
10
11
S
Diode Forward Voltage
VSD
IS = - 4.6 A
- 0.86
- 0.80
V
561
565
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS = - 4 V, VGS = 0 V, f = 1 MHz
217
215
136
138
VDS = - 4 V, VGS = - 5 V, ID = - 5.8 A
5.8
8
5.2
7.3
VDS = - 4 V, VGS = - 4.5 V, ID = - 5.8 A
0.95
0.95
1.35
1.35
pF
nC
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
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Document Number: 66505
S10-0747-Rev. A, 05-Apr-10
SPICE Device Model SiB417EDK
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA TJ = 25 °C, unless otherwise noted
2.0
15
VGS = 5 V, 3.5 V, 3 V, 2.5 V
1.6
12
ID - Drain Current (A)
ID - Drain Current (A)
TJ = 125 °C
VGS = 2 V
9
6
VGS = 1.5 V
3
1.2
TJ = 25 °C
0.8
0.4
TJ = - 55 °C
0
0
1
2
3
4
0.0
0.0
5
0.5
1.0
1.5
2.0
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
0.4
1000
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
800
0.3
0.2
0.1
VGS = 2.5 V
600
Ciss
400
Coss
200
Crss
VGS = 4.5 V
0.0
0
0
3
6
9
12
0
15
2
ID - Drain Current (A)
6
8
VDS - Drain-to-Source Voltage (V)
0.20
5
ID = 5.8 A
ID = 5.8 A
0.16
4
RDS(on) - On-Resistance (Ω)
VGS - Gate-to-Source Voltage (V)
4
3
VDS = 4 V
2
VDS = 6.4 V
0.12
0.08
TJ = 125 °C
0.04
1
TJ = 25 °C
0.00
0
0
2
4
Qg - Total Gate Charge (nC)
6
8
0
1
2
3
4
5
VGS - Gate-to-Source Voltage (V)
Note
Dots and squares represent measured data.
Document Number: 66505
S10-0747-Rev. A, 05-Apr-10
www.vishay.com
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Document Number: 91000
Revision: 18-Jul-08
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