AN58827 PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations Author: Mark Hastings Associated Project: No Associated Part Family: All PSoC 3 and PSoC 5LP parts Software Version: PSoC Creator™ 1.0 or Higher Related Application Notes: None AN58827 discusses how internal trace and switch resistance can affect the performance of a design and how these ® issues can be avoided by understanding a few basic details about the PSoC 3 and PSoC 5LP internal analog architecture. Trace and switch resistance are not a concern for most applications. However, this application note teaches the designer when resistance in the signal path may cause measurement errors. Introduction When you add a wire or trace on your PCB, you add some amount of resistance in the signal path. This is also true when adding signal paths and switches in an integrated circuit. The only difference is the scale, but Ohms law still holds true. The PSoC 3 and PSoC 5LP parts are possibly the most flexible mixed signal controllers on the market today. The internal analog switch matrix provides many options when routing signals between analog blocks and GPIO (General Purpose Input and Output) pins. The signal paths and switches required to provide this flexibility also add resistance between the signal source and its destination. A detailed diagram of the analog blocks, GPIOs, and switch matrix is located in the Appendix at the end of the application note. Calculating Path Resistance To determine the resistance of a path between an analog block and a GPIO pin, add up the resistance for each switch and trace in the signal path. Table 1 gives an approximation for the worse case resistance of each analog path and switch. Table 1. Typical Resistance of Internal Paths and Switches Label Typical Resistance Small Switch (colored white) 500 - 700 Ω Large Switch (colored red) 200 - 350 Ω XLarge Switch (colored green) ~ 50 Ω Analog Global AGL[7:0], AGR[7:0] ~ 200 Ω Analog Mux Bus AMUXBUSR, AMUXBUSL ~ 100 Ω Analog Local Bus AbusR[3:0], AbusL[3:0] ~ 100 Ω Item For a simple path between a GPIO pin and the ADC, an estimation of the signal path resistance can be calculated. See Figure 1 for a representation of a simple circuit where P0[6] is connected to the positive input of the DelSig ADC. www.cypress.com Document No. 001-58827 Rev. *E 1 PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations Figure 2. Design with Equivalent Resistance Figure 1. Simple Signal Route Analog Block VBlock Rpath Vin RInput The two resistors Rpath and RInput form a voltage divider so the actual voltage seen at the input by the ADC (VBlock) is not the same as the input voltage, Vin. The following equation calculates the error created due to these resistors: abusl3 RAG Rsw2 abusl2 abusl0 GPIO P0[6] abusl1 Rsw1 MUXBUSL + dsm0 - Vssa ADC DelSig 01 2 3 4 56 7 Analog Globals RTotal 250SW 1 200AG 250SW 2 700 Equation 1 Equation 2 Substituting the actual resistance values in the equation, you get a signal path resistance of about 700 Ω. The actual resistance may be less, because the resistance of the analog global shown in Table 1 is the worst case. Values between the absolute minimum and maximum were used for this example. Most signals follow only a section of the global, not the entire length, so its resistance will be less. After calculating an approximate signal path resistance, the designer must ask himself, “Does the 700 Ω affect the design?” The buffered input to the ADC has an input resistance of greater than 100 MΩ. Figure 2 shows how a voltage divider is created for any analog block that has an input resistance less than infinity and more than zero. www.cypress.com R path ( Rinput R path ) *100 Equation 3 Substituting with the actual resistor values; % Error The upper half of Figure 1 shows a schematic in PSoC Creator™. The lower half of Figure 1 shows one possible path routed by PSoC Creator to connect a GPIO pin to the positive input of the ADC block. If we analyze the signal path, the signal will pass through two switches and an analog global bus. The total resistance of this path may be approximated by the following equation for this example: RTotal RSW1 RAG RSW 2 % Error 700 (100,000,000 700 ) *100 0.0007 % Equation 4 Because the input resistance is greater than 100 MΩ and the actual path resistance is less than 700 Ω, the error introduced by the path resistance is less than 0.0007% or 7 ppm, which is insignificant for most applications. This is also true when using the Comparator, Opamp, and PGA where the input resistance is also greater than 100 MΩ. When does Resistance Matter? The input resistance for most PSoC 3 and PSoC 5LP blocks is shown in Table 2. When the input resistance is greater than 100 MΩ as in the example described earlier, the error is insignificant. On the other hand, where the input resistance is less than a 100 MΩ, the path resistance may be significant. A couple of examples where this is a concern is the un-buffered mode of the DelSig ADC and the inverting input of the PGA. Table 2. Typical Input Resistance to Some Analog Blocks Analog Block Input Resistance Affected by Routing Resistance DelSig ADC (Buffered Input and Internal source) >100 MΩ No DelSig ADC (Buffered Input and GPIO source) >10 MΩ No, but the difference here is because of the GPIO pin leakage DelSig ADC (Un-buffered Input) >80 KΩ Input resistance is a function of ADC clock and input capacitor Op Amp >100 MΩ No PGA >100 MΩ No Document No. 001-58827 Rev. *E 2 PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations Table 2. Typical Input Resistance to Some Analog Blocks (continued) Analog Block Input Resistance Affected by Routing Resistance Example Project 20 KΩ or 40 KΩ Yes Mixer 20 KΩ or 40 KΩ Yes SAR ADC (PSoC 5LP only) >150 KΩ Input resistance is a function of the sample rate Comparator >100 MΩ No Inverting PGA When using the DelSig ADC in the un-buffered mode, the input resistance may be low enough to adversely affect the accuracy of the design. The input resistance of the DelSig ADC is a function of the ADC clock and input capacitance. The input capacitance of the DelSig ADC is between 1 and 16 pF depending on the range and resolution. The actual input capacitance for each range of the DelSig ADC may be found in the ADC’s datasheet. The following equation is used to calculate the input resistance of the DelSig ADC. Rinput 1 (Cinput * Fclk ) R1 is either 20 K or 40 KΩ for in the Inverting PGA. If the path resistance is as high as 700 Ω and R1 is 20 KΩ the gain error is about 3.5% less than expected or about 1.7% if R1 is 40 KΩ. Equation 5 For example, if the DelSig ADC clock is 3.0 MHz, the resolution is 15 bits and the range is set to ±1 V, the input capacitance is about 4 pF. Using this equation, the input resistance is about 83 KΩ. Using Equation 3, a path resistance of about 700 Ω can introduce an error of 0.7%, which may be significant. The user has the option to either use the ADC’s input buffer to eliminate this error, or to continue using the unbuffered input and compensate using firmware. In the case of the Inverting PGA, the input trace resistance affects the gain. The path resistance adds to R1 in Figure 3. The example project demonstrates a method to measure the temperature of an external diode, called Delta-VBE. This is a popular method to measure the die temperature of large CPUs and FPGAs. Manufacturers of these parts place a PN junction on the die and expose the two terminals from this junction to pins on the package. The Delta-VBE method is immune to VBE offsets and does not require temperature calibration. All that is required is an accurate voltmeter and an adjustable current source. The current source only needs to apply two different currents with a known ratio. The absolute value of these currents is not important, just the ratio of the two currents. When each of the currents is applied, the voltage across the P-N junction is measured. The ratio of the currents should be about 10 or more so that the difference in VBE is large enough to make an accurate measurement. PSoC 3 and PSoC 5LP contain the two components required to perform this measurement, an accurate ADC and an adjustable current source. The following equation is used to calculate the temperature for this method. VBE KT (q ln( N )) Equation 7 Where: VBE is the difference in junction voltage measured at each current -23 K is Boltmann’s constant (1.380658x10 ) joules/K q is the charge of an electron ( 1.602176x10 -19 ) Coulombs T is absolute temperature in Kelvin N is the ratio of the two currents Figure 3. PGA Schematic with Path Resistance First solve for degrees Kelvin: R2 VIN Rpath T K R1 VOUT R2 R1 Equation 5 If you add the input path resistance to the equation, it is easy to see how it affects the gain in Equation 5. R2 Gain ( R1 R path ) www.cypress.com Equation 8 Next, covert to degrees Centigrade: Normally the gain equation for the Inverting PGA is: Gain VBE q ln( N ) K Equation 6 VBE TC 11604 273 ln( N ) Equation 9 If we fix the current ratio to 10, the equation gets even simpler. TC (VBE 5040 ) 273 Equation 10 Now that the method and equation are fixed, all that is left is to implement it with a PSoC. Figure 4 shows the schematic from PSoC Creator with an external 2N3904 NPN transistor, as the temperature sensor. Document No. 001-58827 Rev. *E 3 PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations Figure 6 shows the actual internal routing for this project and correlates the schematic resistors with the actual switches. Figure 4. Temperature Sensor Schematic Figure 6. Actual Routing of Project GPIO P0[5] R3 GPIO P0[6] R4 GPIO P0[7] C B E V0 I0 V2 I2 R1 Because the circuit uses a current source and we know that switches and internal traces are resistive, an I*R drop is the most likely suspect. Adding the actual resistors to the schematic that are inherent from routing generates a more accurate schematic as shown in Figure 5. The input resistance to the ADC is relatively high; therefore, the voltage drop across R2, R4, and R5 are insignificant. There is a voltage drop across R1, but it is out of the measurement path. R3 on the other hand, is directly in the measurement path. The current path between the current source (IDAC8) and the external transistor is directly through R3, which causes a significant I*R drop across R3. When the ADC measures the Base-Emitter voltage (VBE) of the external transistor, it also measures this voltage drop across R3. Figure 5. Schematic Showing Routing Resistance R1 R2 abusl3 abusl2 VIDAC R2-b + dsm0 - R5 MUXBUSL The project is implemented, compiled, and downloaded, but the temperature measurement is much higher than expected, over 60 °C. You had expected something closer to 25 °C, room temperature. This is an error of about 35 °C, what could have caused this error? abusl0 Test the Project abusl1 R2-a Vssa ADC DelSig 01 2 3 4 56 7 With a current ratio of 10, the volts per degree Centigrade is approximately 200 µV/C. The temperature error is the measured temperature minus the actual temperature. In this case, it is about 35 °C (60 °Cmeasured – 25 °Cactual). So, the voltage error is 35 °C * 200 µV/°C or about 7 mV. This voltage error is the I*R drop across R3. The resistance of the switches and the path is estimated by dividing the error voltage by the difference in current. Remember, this method switches between 10 µA and 100 µA so the current delta is 90 µA. The resistance is the voltage drop divided by the current delta, 7 mV/90 µA = 78 Ω. This can easily be explained by the resistance of a switch (XLarge) and some internal routing resistance defined in Table 1 on page 1, which confirms that the error is caused by the routing resistance. IDAC Current Path C B E www.cypress.com R3 R4 R5 Document No. 001-58827 Rev. *E 4 PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations Fixing the Problem Alternative Solution Now that the mystery is solved, how do you fix the problem? One way is to route the current source out to its own pin. This eliminates the switch resistance that was shared by both the current source and measurement path. The ADC now measures only VBE and not the extra voltages caused by an I*R drop. See Figure 7 for the new schematic. When the project is rebuilt, compiled, and run, the calculated temperature is within a couple degrees of the actual temperature expected. This small change in the circuit has a big impact on the accuracy of the design, but does cost an extra GPIO pin. This design is a corner case, but it emphasizes how a designer should always be aware of trace resistance both inside and outside the device. Review the internal routing in Figure 8. With PSoC there is almost always an alternative solution to every design. In the previous solution the temperature error was eliminated, but at the cost of an additional GPIO pin. This may not always be an alternative if your design is tight on pins. Perhaps a better solution is to use the fact that there is both the standard analog global connection as well as the dedicated high current connection to GPIO P0[6]. This way, the path from the IDAC8 and the path from the ADC can be separate until the actual connection to the pad at GPIO P0[6], and not require a separate pin. See the routing schematic at Figure 9. Figure 9. Alternative Solution Schematic Figure 7. Schematic with Separate Current Path R1 R1 R2 R5 B R5 R6 C R6 P05_BC R3 IDAC Current Path R3 P06_iDAC R2 R4 E C B R4 E If you evaluate the internal routing in Figure 10, you can see that the current and measurement paths are truly independent up to P0[6]. If the external diode sensor is near the PSoC, or the PCB trace resistance is low, this is a good solution. If the sensor is connected via a resistive path from the PSoC, the initial solution may be a better alternative, since sharing the current and measurement path is what originally caused the problem. Figure 8. Actual Routing of Solution R6 GPIO P0[5] R3 Figure 10. Routing of Alternative Solution GPIO P0[6] GPIO P0[5] R4 GPIO P0[7] V0 I0 V2 I2 VIDAC R6 R4 GPIO P0[7] abusl3 abusl2 abusl1 R1 abusl0 R3 GPIO P0[6] R1 V0 I0 V2 I2 ADC DelSig abusl2 Vssa R2 + dsm0 - R5 MUXBUSL 01 2 3 4 56 7 VIDAC abusl3 MUXBUSL R5 abusl0 + dsm0 - abusl1 R2 Vssa ADC DelSig 01 2 3 4 56 7 www.cypress.com Document No. 001-58827 Rev. *E 5 PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations The schematic of the alternative solution and the original have the same schematic Figure 4, so how do you force this different route? As of PSoC Creator 2.0, an additional tool was added to allow the designer to review and change the route taken by any path. This tool is called the “Analog Device Editor”. It allows the designer to alter a signal path, and to select alternate analog blocks. The route and block can then be locked so that the route will be static even if you rebuild the project. Figure 12. Analog Device Editor view of Alternative Solution Separate Current Path P0[6] P0[7] Figure 11 shows a partial view from the Analog Device Editor of the original temperature sensor design. Notice that the template is very similar to the Analog Interconnect Diagram provide in the appendix, Figure 15. Figure 11. Analog Device Editor View of Original Project P0[6] Measurement Path P0[7] Analog Device Editor Documentation A complete description of the Analog Device Editor and how to use it can be found in the PSoC Creator Document Manager. To find this document, click on the “Help” menu and select “Document Manager”. See Figure 13. Shared Current and Measurement Path Figure 13. Document Manager Location By rerouting the design, you can see the difference in the actual route. The voltage measurement point becomes the actual GPIO, P0[6]. No current from the IDAC8 flows in the measurement path from the ADC. Although these two solutions are the exact same schematic, they are routed differently. The Analog Device Editor allows you to make minor changes in just a few minutes. In the case of this example project, it reduced the temperature measurement error from totally unacceptable to down to a degree or two. In the Document Manager, select “PSoC Creator Help” under the “Contents” tab and navigate down to Using Design Entry Tools/Design-Wide Resources/Analog Device Editor. This section of the help manual will show you how to examine and to edit your circuit’s analog. See Figure 14. www.cypress.com Document No. 001-58827 Rev. *E 6 PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations Figure 14. Analog Device Editor Documentation Summary This application note helps you to think about what is going on inside the PSoC. Usually, the current through the switches and internal traces is so low, that you can completely ignore voltage drops that may occur. When dealing with current sources or inputs that do not have high input resistance, pay extra attention to the signal path and any voltage drops that may occur. Also, remember that Ohms Law is the same whether the circuit is implemented inside the PSoC or the old way, using discrete components on a PCB. Make use of the Analog Device Editor to review how you design has been routed. If you do find an issue, this powerful tool can help you force a more desirable route to achieve optimal performance. About the Author Some Analog Device Editor features include: View actual signal paths Examine Analog Mux routing and configuration Measure the resistance of a signal path Lock components to a specific analog block Change which analog blocks are used for a given component Re-route signal paths and analog mux routes View individual switch resistance Display individual switch control register address and mask values www.cypress.com Name: Mark Hastings Title: Applications Engineer MTS Background: Mark Hastings received his BSEE degree from Washington State University in 1984. For most of the last 29 years he has been involved in embedded and mixed signal designs. In his free time he can be found hiking the North Cascades of Washington State. Contact: [email protected] Document No. 001-58827 Rev. *E 7 PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations Appendix Figure 15. Analog Interconnect Diagram Vssd Vcca * Vssa Vdda * * * AGR[5] AGL[6] AGR[6] AGR[7] * AGL[6] AGL[7] AGL[4] AGL[5] swinp 01 2 3 4 56 7 0123 * opamp1 swfol swfol GPIO P3[5] GPIO swinp P3[4] GPIO swinn P3[3] GPIO P3[2] GPIO P3[1] GPIO P3[0] GPXT *P15[1] GPXT *P15[0] swinn swfol swfol opamp3 3210 76543210 swinn * + - comp2 sc0 Vin Vref out vssa sc0_bgref (1.024V) sc2_bgref (1.024V) Vssa sc1_bgref (1.024V) sc3_bgref (1.024V) Vin Vref out sc3 ABUSL0 ABUSL1 ABUSL2 ABUSL3 v0 DAC0 i0 DAC1 v1 i1 v2 DAC2 i2 DAC3 v3 i3 USB IO USB IO * P15[6] GPIO P5[7] GPIO P5[6] GPIO P5[5] GPIO P5[4] SIO P12[7] SIO P12[6] GPIO *P1[7] GPIO *P1[6] dac_vref (0.256V) vssd dsm0_vcm_vref1 (0.8V) dsm0_vcm_vref2 (0.7V) + DSM0 - vssa DSM vcm refs qtz_ref vref_vss_ext dsm0_qtz_vref2 (1.2V) dsm0_qtz_vref1 (1.024V) Vdda/3 Vdda/4 ExVrefL ExVrefR refmux[2:0] PSoC 5LP Only Vp (+) Vn (-) SAR0 Vrefhi_out refs SAR_vref1 (1.024V) SAR_vref2 (1.2V) (+) Vp SAR1 (-) Vn Vrefhi_out refs SAR_vref1 (1.024V) SAR_vref2 (1.2V) SAR ADC Vdda Vdda/2 ExVrefL2 ExVrefL1 en_resvda refmux[2:0] 01 23456 7 0123 3210 76543210 Vbat Vssd Ind Vboost * * Vssb Vddio1 GPIO P2[5] GPIO P2[6] GPIO P2[7] SIO P12[4] SIO P12[5] GPIO P6[4] GPIO P6[5] GPIO P6[6] GPIO P6[7] * www.cypress.com * * X- Large ( ~50 Ohms) * * Switch Resistance Small ( ~500 to 700 Ohms ) Large ( ~200 - 350 Ohms) * * Connection * * AMUXBUSL Mux Group Switch Group AGR[3] AGR[2] AGR[1] AGR[0] AMUXBUSR XRES * AGL[1] AGL[0] Notes: * Denotes pins on all packages LCD signals are not shown. Document No. 001-58827 Rev. *E * AGL[3] AGL[2] AGR[0] AMUXBUSR AGR[3] AGR[2] AGR[1] LPF GPIO P5[0] GPIO P5[1] GPIO P5[2] GPIO P5[3] GPIO P1[0] GPIO P1[1] GPIO P1[2] GPIO P1[3] GPIO P1[4] GPIO P1[5] AGL[1] AGL[2] AGL[3] VBE Vss ref * TS ADC AMUXBUSR ANALOG ANALOG BUS GLOBALS * AMUXBUSL AGL[0] ANALOG ANALOG GLOBALS BUS : Vdda Vdda/2 en_resvda refmux[2:0] AMUXBUSL Vssd Vddd * P15[7] VIDAC vcmsel[1:0] Vccd ABUSR0 ABUSR1 ABUSR2 ABUSR3 * * Vddio2 refbuf_vref1 (1.024V) refbuf_vref2 (1.2V) refsel[1:0] sc1 Vin Vref out SC/CT Vin Vref out sc2 out ref in * * Vddd refbufr AGR[4] AMUXBUSR CAPSENSE out ref in refbufl refsel[1:0] GPIO P6[0] GPIO P6[1] GPIO P6[2] GPIO P6[3] GPIO P15[4] GPIO P15[5] GPIO P2[0] GPIO P2[1] GPIO P2[2] GPIO P2[3] * GPIO P2[4] * i1 bg_vda_swabusl0 refbuf_vref1 (1.024V) refbuf_vref2 (1.2V) Vssd + - cmp0_vref (1.024V) cmp1_vref Vdda Vdda/2 Vccd comp3 ExVrefR i3 refbufr_ cmp refbufl_ cmp vref_cmp1 (0.256V) bg_vda_res_en comp1 + - COMPARATOR cmp_muxvn[1:0] abuf_vref_int (1.024V) swin AGR[7] AGR[6] AGR[5] GPIO P4[2] GPIO P4[3] GPIO P4[4] GPIO P4[5] GPIO P4[6] GPIO P4[7] swout out1 comp0 + - cmp1_vref cmp0_vref (1.024V) in1 out0 swin i2 * LPF in0 swout abuf_vref_int (1.024V) cmp1_vref i0 * * opamp2 * * opamp0 * * * * AMUXBUSL * AGL[5] ExVrefL2 swinp GPIO P0[4] GPIO P0[5] GPIO P0[6] GPIO P0[7] * AGR[4] AGL[7] ExVrefL ExVrefL1 * * AMUXBUSR AMUXBUSL AGL[4] * swinp Vddio3 GPIO P3[6] GPIO P3[7] SIO P12[0] SIO P12[1] GPIO P15[2] GPIO P15[3] SIO P12[2] SIO P12[3] GPIO P4[0] GPIO P4[1] GPIO P0[0] GPIO P0[1] GPIO P0[2] GPIO P0[3] Vddio0 swinn Rev #62 26-Mar-2013 8 PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations Document History ® Document Title: PSoC 3 and PSoC 5LP Internal Analog Routing Considerations – AN58827 Document Number: 001-58827 Revision ECN Orig. of Change Submission Date Description of Change ** 2859800 MEH 01/20/2010 New application note *A 2991568 SRIH 07/22/2010 Fixed branding discrepancies *B 3132534 MEH 12/08/2010 Changed title to “Internal Routing Considerations for PSoC® 3 and PSoC 5 Analog Designs”. Updated description of Figure 1. Updated Analog Interconnect Diagram and added caption to diagram. *C 3506342 MEH 01/23/2012 Updated template according to current Cypress standards. Changed the title. Updated Figure 15. Several minor updates. *D 3811873 MEH 11/15/2012 Updated Associated Part Family as “All PSoC 3 and PSoC 5LP parts”. Replaced PSoC 5 with PSoC 5LP in all instances across the document. *E 3956041 www.cypress.com MEH 4/05/2013 Add alternative routing solution and introduce the reader to the PSoC Creator analog editor. Updated the Analog Interconnect Diagram. Document No. 001-58827 Rev. *E 9 PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. www.cypress.com Document No. 001-58827 Rev. *E 10