AN2405 PSoC 1 I/O Power Structure - Determining VOH and VOL at Partial Load.pdf

AN2405
PSoC® 1 I/O Power Structure - Determining VOH and VOL at Partial Load
Author: Dennis Seguine
Associated Project: No
Associated Part Family: CY8C20x34, CY8C21x34, CY8C24x23A, CY8C24x94, CY8C27x43,
CY8C28x45, CY8C29x66
Software Version: PSoC ® Designer™ 5.x
Related Application Notes: None
To get the latest version of this application note, or the associated project file, please visit
http://www.cypress.com/go/AN2405.
AN2405 outlines a means to calculate the output voltages of the PSoC® device digital GPIO, when loaded at less than
the rated maximum current. The internal routing resistances are presented for each of the listed PSoC 1 devices.
Contents
Introduction
Introduction ....................................................................... 1
Bonding Wires ................................................................... 1
Lead Frame ....................................................................... 2
Power (VSS and VDD) Rails ................................................ 2
Output Devices .................................................................. 3
Ohm's Law Manipulation ................................................... 3
Voltage at Unloaded Pin.................................................... 4
Summary ........................................................................... 5
Author's Note..................................................................... 5
Appendix A ........................................................................ 6
Worldwide Sales and Design Support ............................. 14
Most PSoC applications use GPIO connections to drive
resistive loads. Worst case logic level outputs at maximum
rated current are clearly specified in the target device
datasheet. This may be insufficient information when the
absolute value of the output level is important to the
performance of the user's circuit. Examples include using
a PWM as a source to a BPF2 User Module, using a PWM
to implement a DAC, or when the loading device has VIL or
VIH thresholds that are more restrictive than the specified
maximum values for PSoC outputs.
The logic output levels (high and low) are functions of the
output devices and the power routing on the device. A
power distribution model of the PSoC is outlined that
includes the geometric, voltage and temperature
characteristics of the output devices, and routing.
There are four components of the resistance that limit
output current delivery: lead frame, bonding wire, output
devices, and power rail routing.
Bonding Wires
Bonding wires connect the device pads to the lead frame
and have a typical resistance of 100 mΩ. VSS and VDD
connections have multiple pads in some devices and
multiple bonding wires in others.
www.cypress.com
Document No. 001-41447 Rev. *C
1
®
PSoC 1 I/O Power Structure - Determining VOH and VOL at Partial Load
Figure 1. Typical PSoC Power Routing
Lead Frame
GPIO Px.ev3n
GPIO
Px.odd
Vdd
GPIO Px.odd
GPIO Px.odd
The lead-frame resistance varies with the package
selected and each specific pin. Compared to the bonding
wire, the output device, and the on-chip power rail routing,
these values are very small. Smaller packages (QFN and
BGA) have lead resistances in the range of 3 to 15 mΩ.
Larger packages (SSOP, TQFP, SOIC, and PDIP) have
lead resistances in the range of 10 to 70 mΩ. Longer leads
have higher resistance, so pins in the corners have higher
resistance than pins in the center of the part.
GPIO
Px.odd
Vss
Digital
Vdd
GPIO
Px.evn
Vdd
Digital
Vss
Analog Vdd Analog
GPIO Px.odd
GPIO
Px.odd
GPIO Px.even
GPIO
Px.evn
GPIO Px.odd
GPIO
Px.odd
GPIO Px.even
GPIO
Px.evn
SMP
Power (VSS and VDD) Rails
Analog
Digital
Flash
RAM
etc.
SMP
Vss
for
SMP
The VSS and VDD power rails on the PSoC are concentric
rings. Analog power and digital power are routed
separately. An outline of typical PSoC power routing is
shown in Figure 1.
Vss
GPIO
Px.evn
GPIO Px.even
GPIO
Px.evn
GPIO Px.even
GPIO
Px.odd
GPIO Px.odd
GPIO
Px.odd
GPIO Px.odd
Vss Analog
Vdd
Analog
GPIO
Px.evn
GPIO Px.even
Vdd Digital
Vss Digital
GPIO
Px.odd
Vss
GPIO
Px.evn
GPIO
Px.evn
Vdd GPIO
Vss GPIO
GPIO Px.even
GPIO Px.even
Vss
Some devices (generally larger ones) and packages have
multiple VSS connections. This enables lower resistance
VSS connections, reducing noise in the analog section.
Some connections are direct to individual pins. Other
devices have VSS wire-bonded to the main part of the lead
frame (called the “paddle”) to reduce the resistance of the
ground connection. This is seen in the CY8C24x23A
example of Figure 11 in the Appendix A.
GPIO
Px.odd
GPIO Px.odd
GPIO Px.odd
The buses for digital, analog and I/O power systems come
together at the VSS and VDD pad connections. This on-chip
connection method has clear advantages. The interaction
between load, digital, and analog signal currents is only at
the power connection pads. This means that internal
(logic, CPU, analog) currents have minimal effect on the
GPIO output voltages. Correspondingly, the load currents
have a minimal effect on the performance of the precision
analog sections. The PSoC power distribution on-chip
consists of three pairs of power rails for analog, digital,
and I/O structures. The VDD power rails are tied together at
the bonding pad. The bonding pad is connected to the
device's lead frame using a bonding wire.
The resistance of the power rails is identical for both VSS
and VDD. The bonding pads on the device are not
uniformly spaced; other features share the outer ring of
the device with the bonding pads. The metallization on the
device is aluminum, which has a resistance of the form:
R = RREF (1 + α (T − 20°) )

α is the temperature coefficient of resistivity, equal to
0.004308.

RREF is the resistance at 20 °C
The routing resistance of the VSS and VDD rails shown in
Figure 2 and Figure 3 is the worst case value at 25 °C,
calculated from the design and layout detail, and
confirmed by measurements taken during the device
characterization process. The routing resistance at 100 °C
will be about 33 percent higher than the values listed.
The details of the VDD and VSS output rail routing
resistance for PSoC 1 devices is included in the
Appendix A.
www.cypress.com
Document No. 001-41447 Rev. *C
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PSoC 1 I/O Power Structure - Determining VOH and VOL at Partial Load
Output Devices
The output devices on each GPIO port are N-channel
FETs driving (sinking) current to VSS and P-channel FETs
driving (sourcing) current from VDD. Separation of the
threshold voltages of these devices guarantees that they
are never on at the same time.
The temperature dependence of the FET's resistance can
be seen in Figure 3. Again, these values are estimates
based on the design and the characterization data.
Figure 3. FET Resistance vs Temperature
50
Ohms
FETs operating in the linear region (i.e., not turned fully
on) source (or sink) a current that is dependent on the
gate-to-source voltage (VGS) and the device's threshold
voltage (VTH):
45
P-ch Vdd=3.0
P-ch Vdd=5.0
N-ch Vdd=3.0
N-ch Vdd=5.0
40
35
I D = I DD * (VGS − VTH )
2
30
The internal logic levels swing from rail-to-rail, thus the
VGS is equal to VDD for the N-FET and -VDD for the P-FET.
VDD is considerably higher than the VTH, so for the
operating range of VDD for the PSoC and the purposes of
this model, the on-resistance is modeled as a first order
equation with a negative coefficient on the supply voltage
term.
The threshold voltage of a FET has a positive temperature
coefficient. As temperature increases, the difference
between VGS and VTH drops. At a fixed VGS (=VDD) then,
the device conducts less current as the temperature
increases. Thus the output resistance increases with the
temperature.
Based on characterization data for the CY8C24x23A, the
output resistance of the N-channel devices (sinking
current) and the P-channel devices can be modeled as:
RDS − N = 33.2 − 1.8Vdd + 0.04(T − 25)
RDS − P = 63.8 − 6.6Vdd + 0.066(T − 25)
20
-50
-25
0
25
50
Temp
75
(deg C)
100
125
The layout of the PSoC I/O cell is symmetrical; the
N-channel and the P-channel devices are the same size.
For the same size devices, the on-resistance of the
N-channel device is lower than that of the P-channel
device. Typical applications require more sinking current
than sourcing current. This is a design hold-over from the
(good old) days of TTL logic. The use of like-sized devices
for N- and P-output drivers is a reasonable design choice
for almost all applications.
The GPIO cells of all PSoC 1 devices are identical. They
all have the same output resistance. The power
distribution rails are equal width and vary only in length.
Ohm's Law Manipulation
At room temperature, the voltage dependence of the
FET's resistance can be seen in Figure 2.
Figure 2. FET Resistance vs VDD at Room Temperature
50
P-Channel
Ohms
45
25
N-Channel
40
Calculating the output voltage for a given pin with a given
load is a matter of applying Ohm's law, Kirchhoff’s law,
and simple algebra to a large, simple network. The output
voltage on unloaded pins may be of importance. An
example is an LED on one pin and unloaded logic levels
on other pins. You could enter the network into a SPICE
simulation, or have that summer intern build it into a
spreadsheet.
Let us do rough numerical calculation for an example at
the room temperature:
35
Example:
CY8C24423 PDIP 28
30
VDD = 5.0 V, T = 25 °C
25
20 mA load into P1[6]
20
Find
2.5
3
3.5
4
VDD
4.5
5
5.5
6
VOL at P1[6]
VOL at P2[0] unloaded
VOL at P1[0] unloaded
www.cypress.com
Document No. 001-41447 Rev. *C
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PSoC 1 I/O Power Structure - Determining VOH and VOL at Partial Load
We will start with a simplified schematic, reduced from
Figure 11 to summed resistances in Figure 4. The
resistance from the pin to VSS is split, clockwise around
the chip from the pin to VSS (RCW) and counter-clockwise
around the chip from the pin to VSS (RCCW). These values
will vary as a result of the pin location.
Figure 4. Simplified Routing Resistance
24
Let us go back and check the accuracy of the assumption
that we could neglect the resistance of the route between
the two VSS connections.
The voltage at the top end of short-side bond wire is
VBWShort =
0.1
(0.547 − 0.02 A * 24) = 1.34mV
0.1 + 4.89
P1.6
The voltage at the top end of long-side bond wire is
10.05
RCCW
4.89
RCW
20 mA
V BWLong =
4.89
0.1
(0.547 − 0.02 A * 24) = 0.66mV
0.1 + 10.05
RGG
0.10
Bondwire
0.10
Bondwire
The voltage drop between these two points is
= (1.34 mV - 0.66 mV) = 0.68 mV
So, the current between them is
0.018
Leadframe
= 0.68 mV/4.89 Ω
= 0.139 mA
Resistance from P1[6] to VSS pad (the short way clockwise) is summed from the listed values in Figure 11
in the appendix, routing resistance for CY8C24x23.
RCW = 1.35 + 0.27 + 0.27 + 3.0 = 4.89Ω
Resistance from P1[6] to VSS pad (the long way - counter
clockwise), accounted in the same manner, is
RCCW = 0.27 + 0.27 + ... + 0.81 = 10.05Ω
This is small compared to the total current (20 mA) and
means that the earlier estimate that this part of the routing
loop could be neglected is correct.
Voltage at Unloaded Pin
The VSS rail at the source of P1[6]'s output FET is at
3.36 Ω * 20 mA = 67.2 mV. Thus, other output pins in
question, P1[0] and P2[0] will not be at zero volts. We will
use a slightly more complex version of the VSS routing
resistance, shown in Figure 5.
Figure 5. Routing Resistance for Unloaded Pins
Bond wire resistance (RBW) = 0.1 Ω each path
(66.8 mV)
24
P1.6
Lead frame resistance = 0.018 Ω
20 mA
P1[6] N-FET output resistance = 24.0 Ω
Initially let us neglect the resistance between the VSS pads
(RGG), which amounts to about 5.0 ohms.
0.27
24
ROUT = (RCW + R BW ) || (RCCW + R BW ) + R LF
ROUT
1
1
1
+
4.89 + 0.1 10.05 + 0.1
= 3.36Ω
24
P1.0
P2.0
The VSS resistance from P1[6] N-FET source to PCB is the
resistance clockwise around the short side of the loop in
parallel with the resistance counter-clockwise around the
long side of the loop.
ROUT =
3.54
+ 0.018
9.78
R-CCW
1.35
R-CW
4.89
R-GG
0.10
Bondw ire
0.10
Bondw ire
0.018
Leadframe
VOL _ P1.6 = 0.02 A(24 + 3.36 ) = 0.547V
www.cypress.com
Document No. 001-41447 Rev. *C
4
®
PSoC 1 I/O Power Structure - Determining VOH and VOL at Partial Load
P1[0] is between P1[6] and VSS. The voltage at P1[0] for
no load current is the voltage at the source of P1[0]'s
N-FET.
1.
Most of the drop comes from the FET output
resistance . . . NOT the metal routing resistance. For
high current applications, use the multiple pins in
parallel.
2.
It is clear that to deliver high currents without
degrading the VOH and VOL of unloaded outputs, these
unloaded outputs must be placed as close to the VSS
pins as possible.
3.
Calculate your outputs at the full range of temperature
and voltage expected in your product. Add some
margin. While the estimates on routing and output
FET resistance were made in good faith, they are still
estimates.
VOL_P1.0 = (1.35+0.1)/(3.54+1.35+0.1)*67.2 mV = 19.5 mV
P2[0] is very close to P1[6] (... it is a long way around to
loop the VSS terminal next to P2[1]). The voltage at P2[0]
for no load current is the voltage at the source of P2[0]'s
N-FET.
VOL_P2.0 = (9.78+0.1)/(9.78+0.27+0.1)*67.2 mV = 65.4 mV
VOL at both P1[0] and P2[0] is not at zero volts even when
there is no load current into these pins because the
voltage on the bus is non-zero and distributed. More load
currents raise the bus voltage even more. Since there is
no load current on these pins, the 24-Ω N-FET resistance
does not affect the output voltage.
This was obviously a trivial example; distributed loads
beget more complex calculations. This is a simple
exercise for SPICE; it is strictly a matter of data entry.
Author's Note
After years of study and practice, the author is still
messing around with Ohm's law. It is still fundamental;
software has not completely taken over the world.
Summary
Calculation of PSoC logic output voltage under load is a
straight-forward but tedious exercise. The VOH and VOL
values on any pin can be calculated to assure that logic
level and other requirements of external loads can be met.
From the structure of the power routing, we can infer
obvious design steps to drive the unloaded outputs closer
to the rails if this is an issue in the user's application.
www.cypress.com
About the Author
Name:
Dennis Seguine.
Title:
Applications Engrg MTS
Document No. 001-41447 Rev. *C
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®
PSoC 1 I/O Power Structure - Determining VOH and VOL at Partial Load
Appendix A
Figure 6. CY8C20x34 VDD Routing
3.00
P0.7
1.35
0.48
P0.5
33
3.00
0.10
VDD
BondWire
33
33
Figure 7. CY8C20434 VSS Routing
1.06
0.48
VDD
P0.7
33 P-fet RDSon
P0.6
33
24
P0.4
P0.3
0.48
0.48
VSS
P0.2
33
0.48
0.48
33
33
0.48
33
33
0.48
0.48
33
0.48
0.48
33
4.90
0.48
P2.5
P2.2
P2.3
P2.0
P2.1
33
0.48
0.74
0.96
0.80
1.06
0.80
0.80
1.35
4.90
0.48
.48
0.48
2.25
P1.1
33
24
0.48
0.74
XRES
0.96
0.80
1.06
0.80
0.80
1.35
24
P1.6
24
P1.4
24
24
P1.2
0.10
P1.0
24
P4.0
24
P1.2
0.80
24
P1.3
33
P1.1
VSS
0.48
P3.2
24
P1.4
0.48
0.48
P1.5
33
P1.3
24
P2.0
24
P1.6
33
0.48
P1.7
33
P1.5
24
P3.1
XRES
33
0.48
0.48
P1.7
33
0.48
0.10
P4.0
33
0.48
24
P3.3
33
P3.1
0.48
P2.2
0.10
P3.2
.48
0.96
24
P2.4
24
33
P3.3
0.48
P2.6
24
33
P2.1
0.48
24
P0.0
24
P2.4
33
P2.3
0.48
P2.7
33
P2.5
0.48
24
P0.2
24
P2.6
0.48
1.06
P0.1
33
P2.7
0.48
0.10
24
P0.0
0.96
0.48
24 N-fet RDSon
P0.6
P0.4
BondWire
P0.1
1.35
P0.3
33
VSS
0.48
P0.5
0.48
VSS
2.25
0.80
24
P1.0
BondWire
www.cypress.com
Document No. 001-41447 Rev. *C
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PSoC 1 I/O Power Structure - Determining VOH and VOL at Partial Load
Figure 9. CY8C21434 VSS Routing
Figure 8. CY8C21434 VDD Routing
1.70
0.10
1.70
VDD
Bondwire
33
P0.7
33
0.40
0.40
P0.5
33
0.40
0.60
24
33 P-fet RDSon
P0.6
1.07
24
33
0.40
0.40
BondWire
24
33
33
0.54
0.27
0.40
0.40
0.27
0.27
0.40
0.40
0.27
0.81
0.40
0.05
0.27
24
0.27
0.81
24
P3.2
0.40
0.81
24
24
0.48
1.05
XRES
P1.7
XRES
0.40
0.40
2*Bondwire
0.48
P1.7
33
0.40
24
P3.0
P3.0
1.05
0.27
33
VSS
33
0.27
24
P2.0
0.10
SMP
Bondwire
P3.2
0.81
0.40
P2.1
33
SMP
0.40
24
P2.2
24
33
P2.0
0.10
0.27
P2.3
P2.2
33
0.54
24
P2.4
24
33
P2.1
0.40
P2.5
P2.4
33
0.40
24
P2.6
24
33
P2.3
1.07
P2.7
P2.6
33
0.27
P0.0
24
33
P2.5
24
P0.1
P0.0
P2.7
0.40
P0.2
P0.2
P0.1
0.60
24 N-fet RDSon
P0.6
P0.4
0.10
33
VSS
0.40
P0.3
P0.4
0.27
0.40
P0.5
33
P0.3
VDD
24
P0.7
24
33
0.40
0.27
1.06
2.60
0.80
0.27
0.27
0.40
24
P1.6
P1.5
P1.6
P1.5
33
1.06
2.60
24
33
24
P1.4
P1.3
P1.4
P1.3
33
0.80
0.27
24
P1.1
24
P1.1
33
P1.2
P1.2
0.27
VSS
www.cypress.com
1.41
0.40
0.10
33
VSS
P1.0
Document No. 001-41447 Rev. *C
1.41
24
P1.0
BondWire
7
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PSoC 1 I/O Power Structure - Determining VOH and VOL at Partial Load
Figure 11. CY8C24x23A VSS Routing
Figure 10. CY8C24x23A VDD Routing
0.27
0.27
0.10
33
24
VDD
P0.7
0.27
33
1.35
PowerBus
P0.5
0.81
33 Pfet RDSon
P0.6
24
24
P0.4
1.08
33
33
33
33
33
33
0.27
33
24
P2.6
P2.5
P2.4
P2.3
33
0.27
33
24
33
33
0.27
0.27
XRES
SMP
P1.6
P1.7
P1.4
P1.5
33
24
33
P1.5
3.00
24
33
P1.3
33
P1.0
0.81
0.27
24
0.27
0.27
24
0.27
3.00
3.00
0.27
0.27
0.27
24
24
P1.2
P1.1
24
1.35
24
P1.0
0.27
VSS
0.27
P1.3
0.27
33
0.81
24
P1.4
24
P1.2
0.27
0.45
P1.6
0.27
33
0.27
24
XRES
3.00
33
0.45
BondWire
P1.7
0.27
0.27
P2.0
0.27
SMP
24
P2.2
0.10
P2.0
0.81
0.45
P2.1
0.27
VSS
0.27
24
P2.4
24
P2.2
0.81
0.45
P2.6
0.45
P2.1
0.27
24
P0.0
0.45
P2.3
1.50
P2.7
0.45
P2.5
1.08
24
P0.2
24
P0.0
0.27
0.27
P0.1
0.45
P2.7
0.81
24 Nfet RDSon
P0.6
P0.4
24
P0.2
0.27
1.35
P0.3
1.50
P0.1
0.27
P0.5
33
P0.3
33
VDD
0.27
33
P1.1
P0.7
BondWire
0.10
0.27
1.35
VSS
BondWire
www.cypress.com
Document No. 001-41447 Rev. *C
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®
PSoC 1 I/O Power Structure - Determining VOH and VOL at Partial Load
Figure 13. CY8C24x94 VSS Routing
Figure 12. CY8C24x94 VDD Routing
0.27
0.10 Bondwire
VSS
0.35
0.10 Bondwire
Bondwire 0.10
0.27
0.35
0.27
0.27
33
Bondwire 0.10
0.27
0.27
24
0.35
24
0.35
24
1.10
24
0.27
24
0.35
24
0.40
24
0.35
24
1.30
24
VSS
P0.5
P0.3
P0.1
P2.7
P2.5
P2.3
P2.1
P4.7
P4.5
P4.3
P4.1
33
0.27
33
0.54
33
0.81
33
0.81
33
0.27
33
0.40
33
0.40
33
0.40
33
0.40
33
0.35
33
0.35
33
1.10
33
0.27
33
0.35
33
0.40
33
0.35
33
1.30
33
0.35
33
0.54
0.40
0.35
33
0.27
33
0.35
P3.5
P3.3
P3.1
P5.7
P5.5
P5.3
P5.1
P1.7
P1.5
P1.3
P1.1
33
33
33
0.81
33
0.35
33
0.27
33
.035
33
0.27
33
0.35
0.40
33
33
0.27
0.27
33
33
0.35
0.40
33
33
0.27
0.27
33
33
0.35
0.40
33
33
0.27
0.27
33
33
0.35
0.40
33
33
0.27
0.65
33
33
0.35
0.81
33
33
0.27
0.27
33
33
0.35
0.27
33
0.60
0.27
33
VSS
0.27
0.27
33
0.40
0.40
33
VSS
D+
1.0
0.27
0.65
0.27
D0.1
P0.4
P0.7
P0.2
P0.5
P0.0
P0.3
P2.6
P0.1
P2.4
P2.7
P2.2
P2.5
P2.0
P2.3
P4.6
P2.1
P4.4
P4.7
P4.2
P4.5
P4.0
P4.3
XRES
2.85
P3.7
33
P0.6
0.81
0.81
VSS
VDD
0.27
VSS
P0.7
0.27
Bondwire 0.10
VDD
33
P4.1
P3.6
24
VDD
0.27
24
0.54
24
0.81
24
0.81
24
0.27
24
0.40
24
0.40
24
0.40
24
0.40
24
0.40
24
0.27
24
0.35
0.10
0.81
24
0.54
24
0.35
24
P3.0
P3.7
P5.6
24
0.35
24
0.27
24
.035
24
0.27
24
0.35
0.40
24
24
0.27
0.27
24
24
0.35
0.40
24
24
0.27
0.27
24
24
0.35
0.40
24
24
0.27
0.27
24
24
0.35
0.40
24
24
0.27
0.65
24
24
0.35
0.81
24
24
0.27
0.27
24
24
0.35
0.27
24
Bondwire 0.1
0.60
0.27
24
Bondwire 0.1
0.27
0.27
24
P3.3
P5.2
P3.1
P5.0
P5.7
P1.6
P5.5
P1.4
P5.3
P1.2
P5.1
P1.0
P1.7
P7.0
P1.5
P7.1
P1.3
P7.2
P1.1
P7.3
P7.4
VSS
24
24
P3.5
P5.4
0.40
0.40
24
1.0
0.27
24
0.65
0.27
D+
P7.6
D-
P7.7
P0.2
P0.0
P2.6
P2.4
P2.2
P2.0
P4.6
P4.4
P4.2
P4.0
XRES
0.81
2.85
P3.2
P0.4
0.81
P3.4
P7.5
0.35
P0.6
P3.6
P3.4
P3.2
P3.0
P5.6
P5.4
P5.2
P5.0
P1.6
P1.4
P1.2
P1.0
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
VDD
Bondwire
www.cypress.com
Document No. 001-41447 Rev. *C
9
®
PSoC 1 I/O Power Structure - Determining VOH and VOL at Partial Load
Figure 15. CY8C27x43 VSS Routing
Figure 14. CY8C27x43 VDD Routing
BondWire
0.10 BondWire
VSS
0.35
1.35
VSS
33
0.27
0.27
Pow erBus
P0.7
33
0.27
1.08
0.10
0.10 BondWire
VDD
BondWire
24
P0.7
0.27
33 Pfet RDSon
P0.6
0.27
33
P0.5
33
0.10 BondWire
VDD
33
1.08
1.35
33
1.08
0.27
0.27
0.27
0.27
0.27
0.27
1.08
0.27
0.27
0.27
0.27
0.27
0.27
0.27
BondWire
P3.7
33
P3.4
0.35
3.50
0.27
33
P3.1
33
0.27
0.27
0.27
33
0.27
0.27
1.08
33
24
1.62
33
0.27
1.08
0.27
VSS
BondWire
0.27
45
.81
0.27
0.27
0.27
24
0.27
0.27
24
0.27
3.50
0.27
0.27
0.27
0.27
0.27
0.27
24
0.27
0.27
24
0.27
1.08
24
1.35
1.62
24
0.27
0.27
24
P4.0
24
P1.5
P1.4
24
33
P1.3
P1.2
24
P1.1
VSS
P1.0
0.10
1.08
0.27
0.27
0.10
VSS
VSS
BondWire
www.cypress.com
Document No. 001-41447 Rev. *C
P3.0
24
P1.6
24
33
P3.6
24
P1.7
P1.0
0.27
3.24
P5.0
P1.2
P1.1
45
P5.1
P1.6
33
P1.3
0.27
0.27
P5.2
24
P1.4
1.35
0.27
45
P5.3
24
P1.5
33
0.27
P3.1
P5.0
0.27
0.27
P3.2
24
33
P5.1
33
45
P3.3
P3.0
P5.2
0.27
0.27
P3.4
24
33
P5.3
33
45
P3.5
P3.2
0.27
0.27
XRES
24
24
33
P3.3
33
0.27
SMP
33
P3.5
33
24
P4.2
0.10
P3.6
0.27
1.08
0.27
P4.1
33
P3.7
0.27
24
P4.4
45
XRES
33
0.27
P4.3
0.27
0.27
0.27
P4.6
33
SMP
0.27
24
P2.0
45
P4.0
33
0.27
P4.5
VSS
0.81
0.27
45
P4.2
3.24
24
P2.2
24
33
P4.1
VSS
P4.7
P4.4
0.27
0.27
33
P4.3
33
0.27
P2.1
P4.6
0.27
24
P2.4
24
33
P4.5
33
1.75
P2.3
33
P2.0
33
24
1.08
P2.6
24
P2.2
33
0.35
P2.5
P2.4
33
1.08
VDD
P0.0
24
33
P2.1
24 Nfet RDSon
P0.6
P2.7
P2.6
33
0.35
P0.2
24
33
P2.3
0.27
P0.1
P0.0
33
0.35
P0.4
24
33
P2.5
P1.7
24
P0.2
P2.7
VDD
0.27
P0.3
33
P0.1
1.35
P0.5
P0.4
P0.3
P4.7
24
0.27
BondWire
10
®
PSoC 1 I/O Power Structure - Determining VOH and VOL at Partial Load
Figure 16. CY8C28x45 VDD Routing
0.10
0.81
0.35
VDD
VDD
0.05
0.35
1.08
0.45
0.10
33
33 P-fet RDSon
P0.6
P0.5
0.35
33
P0.3
24
P0.4
P0.3
33
1.20
1.08
33
0.27
0.40
0.35
0.35
33
33
0.35
33
0.40
1.08
0.35
0.62
0.35
P4.7
24
33
33
0.35
33
0.27
0.35
0.27
0.27
33
P3.1
33
0.27
0.27
0.35
0.27
0.27
0.35
1.08
1.35
0.27
33
0.35
P1.1
VSS
www.cypress.com
4.00
24
0.35
0.35
24
0.27
0.27
0.35
0.35
0.27
0.27
0.35
0.35
0.27
0.27
0.35
1.08
1.35
0.27
0.35
0.35
24
24
24
24
24
24
P1.5
P1.4
24
33
24
P1.3
P1.2
24
33
P3.0
P1.6
24
24
P1.0
P1.1
P1.0
0.35
0.27
P1.7
P1.2
0.35
0.27
P5.0
24
P1.4
33
3.15
P5.1
33
P1.3
1.48
P5.2
24
P1.6
P1.5
24
P3.2
24
33
P1.7
24
P5.3
P5.0
33
0.27
P3.4
24
33
P5.1
33
0.35
24
P3.1
P3.0
P5.2
33
0.35
P3.3
33
P5.3
0.35
0.27
24
P3.6
24
P3.2
0.35
0.62
P3.5
33
P3.3
0.35
0.35
24
XRES
24
P3.4
33
0.35
P3.7
33
P3.5
33
1.08
P4.2
24
P3.6
33
24
SMP
33
P3.7
0.35
0.40
P4.0
XRES
0.27
0.35
33
SMP
33
24
0.35
P4.0
0.27
0.35
P4.1
3.15
1.48
0.35
24
P4.4
24
P4.2
0.35
0.35
P4.3
33
P4.1
0.35
24
P4.6
24
P4.4
0.35
0.40
P4.5
33
P4.3
0.27
P2.0
24
P4.6
0.27
24
P2.2
P2.0
33
1.08
P2.1
33
P4.5
1.20
P2.4
24
P2.2
33
24
P2.3
33
P2.1
0.35
P2.6
24
P2.4
0.35
1.08
P2.5
33
P2.3
24 Nfet RDSon
P0.6
P0.0
24
P2.6
0.35
1.30
P2.7
P0.0
33
VDD
0.45
P0.2
24
33
P2.5
1.08
P0.1
P0.2
P2.7
0.35
P0.4
24
33
P0.1
P4.7
24
1.30
P0.5
1.08
0.35
VDD
2*BondWire
24
P0.7
P0.7
33
0.81
0.10
VSS
33
Figure 17. CY8C28x45 VSS Routing
0.10
0.35
4.00
VSS
BondWire
Document No. 001-41447 Rev. *C
11
®
PSoC 1 I/O Power Structure - Determining VOH and VOL at Partial Load
Figure 19. CY8C29x66 VSS Routing
Figure 18. CY8C29x66 VDD Routing
Bondwire 0.10
VSS
0.35
1.35
0.01 Bondwire
VSS
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P0.7
P0.5
P0.3
P0.1
P2.7
P2.5
P2.3
P2.1
P4.7
P4.5
P4.3
P4.1
33
33
0.27
0.27
0.27
0.27
33
0.27
0.27
33
0.27
1.08
33
0.27
0.54
33
0.27
0.40
33
0.27
33
0.27
0.40
33
0.27
0.81
33
0.27
0.40
33
1.08
0.27
33
1.08
0.27
33
0.81
0.27
33
0.54
3.00
0.40
0.27
33
0.27
0.81
33
33
0.27
0.27
33
33
33
0.27
0.27
0.27
0.27
0.27
0.27
0.81
0.27
0.81
0.27
SMP
VSS
P3.7
P3.5
P3.3
P3.1
P5.7
P5.5
P5.3
P5.1
P1.7
P1.5
P1.3
P1.1
33
33
1.62
0.27
33
0.27
33
0.27
0.40
1.35
0.27
P6.6
P6.7
P0.7
P0.5
P0.3
P0.1
P2.7
P2.5
XRES
P2.3
P3.6
P2.1
P3.4
P4.7
P3.2
P4.5
P3.0
P4.3
P5.6
P4.1
P5.4
SMP
33
P5.0
33
P1.6
33
P1.4
0.27
33
P1.2
33
33
33
0.27
0.27
33
0.27
0.27
P1.0
P7.0
33
P7.1
33
P7.2
33
0.27
0.27
33
33
1.08
0.27
33
33
0.27
0.27
33
P7.3
P7.4
P7.5
0.27
33
P7.6
0.27
0.27
VDD
0.27
0.27
24
0.27
0.27
24
0.27
0.27
24
0.27
1.08
24
0.27
0.54
24
0.27
0.40
24
0.27
0.40
24
0.27
0.40
24
0.27
0.81
24
0.27
0.40
24
1.08
0.27
24
1.08
0.27
P0.6
24 N-fet RDSon
P0.4
24
P0.2
24
P0.0
24
P2.6
24
P2.4
24
P2.2
24
P2.0
24
P4.6
24
P4.4
0.10 Bondwire
24
0.81
0.27
24
24
0.54
3.00
24
24
1.08
0.27
24
0.27
0.81
24
24
0.27
0.27
24
24
0.27
0.27
24
24
0.27
0.27
24
24
0.27
0.27
24
0.10
Bondwire
24
P3.7
24
P3.5
24
P3.3
24
P3.1
24
P5.7
24
P5.5
24
P5.3
24
P5.1
24
P1.7
24
P1.5
24
P1.3
24
P1.1
P5.2
0.27
0.27
P6.5
33
0.27
Bondwire
VSS
P6.4
33
0.10
VSS
VDD
24
P4.2
P4.0
XRES
P3.6
P3.4
P3.2
P3.0
P5.6
0.81
0.27
24
0.81
0.27
24
1.62
0.40
24
0.27
1.35
24
P5.4
P5.2
P5.0
P1.6
0.27
0.27
24
0.27
0.27
24
P1.4
P1.2
0.27
0.27
24
0.27
0.27
24
P1.0
P7.0
0.27
0.27
24
0.27
0.27
24
0.27
0.27
24
1.08
0.27
24
0.27
0.27
24
0.27
0.27
24
1.62
0.27
24
0.27
0.27
VDD
P7.7
1.35
24
33
0.27
1.62
P6.3
33
0.27
0.10
P6.2
33
33
0.27
P6.1
33
33
33
P6.0
P0.6
33 P-fet RDSon
P0.4
33
P0.2
33
P0.0
33
P2.6
33
P2.4
33
P2.2
33
P2.0
33
P4.6
33
P4.4
0.10
VSS
33
P4.2
33
P4.0
1.08
33
Bondwire
33
33
0.35
0.10
VDD
0.01 Bondwire
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
Bondwire
www.cypress.com
Document No. 001-41447 Rev. *C
12
®
PSoC 1 I/O Power Structure - Determining VOH and VOL at Partial Load
Document History
Document Title: PSoC® 1 I/O Power Structure - Determining VOH and VOL at Partial Load - AN2405
Document Number: 001-41447
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
1541089
SEG
10/03/2007
New Spec.
*A
3247371
SEG
05/03/2011
Update text on lead frame, reformat graphics, add appendix for more chips.
*B
3432728
SEG
11/08/2011
Updated text for clarification and updated template.
*C
4390198
SEG
05/26/2014
Updated in new template.
Completing Sunset Review.
www.cypress.com
Document No. 001-41447 Rev. *C
13
®
PSoC 1 I/O Power Structure - Determining VOH and VOL at Partial Load
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Document No. 001-41447 Rev. *C
14