hm90460-cm44-10120-4e.pdf

FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM44-10120-4E
F2MC-16LX
16-BIT MICROCONTROLLER
MB90460/465 Series
HARDWARE MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90460/465 Series
HARDWARE MANUAL
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Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Objectives and intended reader
Thank you for purchasing Fujitsu Microelectronics products.
The MB90460/465 series was developed as a group of general-purpose models in the F2MC-16LX Family,
which is a family of original 16-bit single-chip microcontrollers that can be used for application specific ICs
(ASICs).
This manual is intended for engineers who design products using the MB90460/465 series of
microcontrollers. The manual describes the functions and operation of the MB90460/465 series.
Note: F2MC is a registered of Fujitsu Microelectronics Limited and stands for FUJITSU Flexible Microcontroller.
■ Trademarks
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
■ Organization of this manual
This manual consists of the following 24 chapters and 1 appendix:
Chapter 1 Overview
This chapter describes the features and basic specifications of the MB90460/465 series.
Chapter 2 Notes on Handling Devices
This chapter describes notes on Handling Devices.
Chapter 3 CPU
This chapter describes the memory space of the MB90460/465 series.
Chapter 4 Reset
This chapter describes the reset function of the MB90460/465 series.
Chapter 5 Clock
This chapter describes the clocks of the MB90460/465 series.
Chapter 6 Low Power Consumption Mode
This chapter describes the energy-saving mode of the MB90460/465 series.
Chapter 7 Interrupt
This chapter describes the interrupts and extended intelligent I/O services of the MB90460/465 series.
Chapter 8 Mode Setting
This chapter describes the operating modes and memory access mode of the MB90460/465 series.
Chapter 9 I/O Port
This chapter describes the functions and operation of the MB90460/465 series I/O ports.
Chapter 10 Time-base Timer
This chapter describes the functions and operation of the MB90460/465 series time-base timer.
Chapter 11 Watchdog Timer
This chapter describes the functions and operation of the MB90460/465 series watchdog timer.
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Chapter 12 16-bit Reload Timer
This chapter describes the functions and operation of the MB90460/465 series 16-bit reload timer.
Chapter 13 16-bit PPG Timer
This chapter describes the functions and operation of the MB90460/465 series 16-bit PPG timer.
Chapter 14 Multi-functional Timer
This chapter describes the functions and operation of the MB90460/465 series multi-functional timer.
Chapter 15 Multi-pulse Generator
This chapter describes the functions and operation of the MB90460/465 series multi-pulse generator.
Chapter 16 PWC Timer
This chapter describes the functions and operation of the MB90460/465 series PWC timer.
Chapter 17 UART
This chapter describes the functions and operation of the MB90460/465 series UART.
Chapter 18 DTP/External Interrupt Circuit
This chapter describes the functions and operation of the MB90460/465 series DTP/external interrupt
circuit.
Chapter 19 Delayed Interrupt Generator Module
This chapter describes the functions and operation of the MB90460/465 series delayed interrupt generator
module.
Chapter 20 8/10-bit A/D Converter
This chapter describes the functions and operation of the MB90460/465 series 8/10-bit A/D Converter.
Chapter 21 ROM Correction Function
This chapter describes the functions and operation of the MB90460/465 series ROM correction function.
Chapter 22 ROM Mirroring Function Selection Module
This chapter describes the functions and operation of the MB90460/465 series ROM mirroring function
selection module.
Chapter 23 512K / 1024K bit Flash Memory
This chapter describes the functions and operation of the MB90460/465 series 512K / 1024K bit flash
memory.
Chapter 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL
WRITING
This chapter describes examples of F2MC-16LX MB90F462/F462A/F463A connections for serial
writing.
Appendix
Appendix A I/O Map
The appendix A contains an I/O map and instruction overview.
Appendix B Instructions
The appendix B contains an instruction overview.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2004-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
MB90460/465 Series Features ........................................................................................................... 2
MB90460/465 Series Product line-up ................................................................................................. 5
Block Diagram of MB90460/465 Series .............................................................................................. 7
Pin Assignment ................................................................................................................................... 8
Package Dimensions ........................................................................................................................ 11
I/O Pins and Pin Functions ............................................................................................................... 14
I/O Circuit Types ............................................................................................................................... 19
CHAPTER 2
2.1
CPU ............................................................................................................ 27
CPU ..................................................................................................................................................
Memory Space ..................................................................................................................................
Memory Maps ...................................................................................................................................
Addressing ........................................................................................................................................
Address Specification by Linear Addressing ...............................................................................
Address Specification by Bank Addressing .................................................................................
Memory Location of Multi-byte Data .................................................................................................
Registers ...........................................................................................................................................
Dedicated Registers .........................................................................................................................
Accumulator (A) ...........................................................................................................................
Stack Pointers (USP, SSP) .........................................................................................................
Processor Status (PS) .................................................................................................................
Condition Code Register (PS: CCR) ..........................................................................................
Register Bank Pointer (PS: RP) ..................................................................................................
Interrupt Level Mask Register (PS: ILM) .....................................................................................
Program Counter (PC) .................................................................................................................
Direct Page Register (DPR) ........................................................................................................
Bank Registers (PCB, DTB, USB, SSB, ADB) ............................................................................
General-purpose Registers ...............................................................................................................
Prefix Codes .....................................................................................................................................
Bank Select Prefix (PCB, DTB, ADB, SPB) .................................................................................
Common Register Bank Prefix (CMR) .........................................................................................
Flag Change Suppression Prefix (NCC) ......................................................................................
Restrictions on Prefix Codes .......................................................................................................
CHAPTER 4
4.1
4.2
4.3
4.4
NOTES ON HANDLING DEVICES ............................................................ 23
Notes on Handling Devices .............................................................................................................. 24
CHAPTER 3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.5
3.6
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.7.7
3.7.8
3.7.9
3.8
3.9
3.9.1
3.9.2
3.9.3
3.9.4
OVERVIEW ................................................................................................... 1
28
29
31
33
34
35
37
39
40
42
45
47
48
50
51
52
53
54
55
57
58
60
61
62
RESET ........................................................................................................ 65
Reset ................................................................................................................................................
Reset Causes and Oscillation Stabilization Wait Intervals ...............................................................
External Reset Pin ............................................................................................................................
Reset Operation ................................................................................................................................
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66
68
69
71
4.5
4.6
Reset Cause Bits .............................................................................................................................. 73
Status of Pins in a Reset .................................................................................................................. 75
CHAPTER 5
5.1
5.2
5.3
5.4
5.5
5.6
CHAPTER 6
6.1
6.2
6.3
6.4
6.5
6.5.1
6.5.2
6.5.3
6.6
6.7
6.8
78
80
82
84
86
87
LOW POWER CONSUMPTION MODE ..................................................... 89
Low Power Consumption Mode ........................................................................................................ 90
Block Diagram of the Low Power Consumption Control Circuit ........................................................ 92
Low Power Consumption Mode Control Register (LPMCR) ............................................................. 94
CPU Intermittent Operation Mode .................................................................................................... 97
Standby Mode ................................................................................................................................... 98
Sleep Mode ................................................................................................................................. 99
Time-base Timer Mode ............................................................................................................. 102
Stop Mode ................................................................................................................................. 104
State Change Diagram ................................................................................................................... 106
State of Pins in Standby Mode and during Reset ........................................................................... 109
Usage Notes on Low Power Consumption Mode ........................................................................... 110
CHAPTER 7
7.1
7.2
7.3
7.3.1
7.3.2
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.5
7.6
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.7
7.8
7.9
CLOCK ....................................................................................................... 77
Clock .................................................................................................................................................
Block Diagram of the Clock Generation Block ..................................................................................
Clock Selection Register (CKSCR) ...................................................................................................
Clock Mode .......................................................................................................................................
Oscillation Stabilization Wait Interval ................................................................................................
Connection of an Oscillator or an External Clock to the Microcontroller ...........................................
INTERRUPT ............................................................................................. 113
Interrupt ..........................................................................................................................................
Interrupt Causes and Interrupt Vectors ...........................................................................................
Interrupt Control Registers and Peripheral Functions .....................................................................
Interrupt Control Registers (ICR00 to ICR15) ...........................................................................
Interrupt Control Register Functions ..........................................................................................
Hardware Interrupt ..........................................................................................................................
Operation of Hardware Interrupt ................................................................................................
Processing for Interrupt Operation ............................................................................................
Procedure for using Hardware Interrupt ....................................................................................
Multiple Interrupts ......................................................................................................................
Hardware Interrupt Processing Time .........................................................................................
Software Interrupt ...........................................................................................................................
Interrupt of Extended Intelligent I/O Service (EI2OS) .....................................................................
Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) ........................................................
Registers of EI2OS Descriptor (ISD) .........................................................................................
Operation of the Extended Intelligent I/O Service (EI2OS) ........................................................
Procedure for using the Extended Intelligent I/O Service (EI2OS) ............................................
Processing Time of the Extended Intelligent I/O Service (EI2OS) .............................................
Exception Processing Interrupt .......................................................................................................
Stack Operations for Interrupt Processing ......................................................................................
Sample Programs for Interrupt Processing .....................................................................................
vi
114
116
119
121
123
126
129
131
132
133
135
137
139
141
142
145
146
147
149
150
152
CHAPTER 8
8.1
8.2
8.3
Mode Setting ................................................................................................................................... 158
Mode Pins (MD2 to MD0) ............................................................................................................... 159
Mode Data ...................................................................................................................................... 160
CHAPTER 9
9.1
9.2
9.3
9.3.1
9.3.2
9.4
9.4.1
9.4.2
9.5
9.5.1
9.5.2
9.6
9.6.1
9.6.2
9.7
9.7.1
9.7.2
9.8
9.8.1
9.8.2
9.9
9.9.1
9.9.2
9.10
MODE SETTING ....................................................................................... 157
I/O PORT .................................................................................................. 163
Overview of I/O Port .......................................................................................................................
Registers of I/O Port .......................................................................................................................
Port 0 ..............................................................................................................................................
Port 0 Registers (PDR0, DDR0 and RDR0) ..............................................................................
Operation of Port 0 ....................................................................................................................
Port 1 ..............................................................................................................................................
Port 1 Registers (PDR1, DDR1 and RDR1) ..............................................................................
Operation of Port 1 ....................................................................................................................
Port 2 ..............................................................................................................................................
Port 2 Registers (PDR2 and DDR2) ..........................................................................................
Operation of Port 2 ....................................................................................................................
Port 3 ..............................................................................................................................................
Port 3 Registers (PDR3 and DDR3) ..........................................................................................
Operation of Port 3 ....................................................................................................................
Port 4 ..............................................................................................................................................
Port 4 Registers (PDR4 and DDR4) ..........................................................................................
Operation of Port 4 ....................................................................................................................
Port 5 ..............................................................................................................................................
Port 5 Registers (PDR5, DDR5 and ADER) ..............................................................................
Operation of Port 5 ....................................................................................................................
Port 6 ..............................................................................................................................................
Port 6 Registers (PDR6 and DDR6) ..........................................................................................
Operation of Port 6 ....................................................................................................................
Sample I/O Port Program ...............................................................................................................
164
166
167
169
171
173
175
176
178
180
181
183
185
186
188
190
191
193
195
196
198
200
201
203
CHAPTER 10 TIME-BASE TIMER .................................................................................. 205
10.1
10.2
10.3
10.4
10.5
10.6
10.7
Overview of the Time-base Timer ...................................................................................................
Configuration of the Time-base Timer ............................................................................................
Time-base Timer Control Register (TBTC) .....................................................................................
Time-base Timer Interrupts ............................................................................................................
Operation of the Time-base Timer ..................................................................................................
Usage Notes on the Time-base Timer ............................................................................................
Sample Program for the Time-base Timer Program .......................................................................
206
208
209
211
212
214
216
CHAPTER 11 WATCHDOG TIMER ................................................................................ 219
11.1
11.2
11.3
11.4
11.5
11.6
Overview of the Watchdog Timer ...................................................................................................
Configuration of the Watchdog Timer .............................................................................................
Watchdog Timer Control Register (WDTC) ....................................................................................
Operation of the Watchdog Timer ...................................................................................................
Usage Notes on the Watchdog Timer .............................................................................................
Sample Program for the Watchdog Timer ......................................................................................
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220
221
222
224
226
227
CHAPTER 12 16-BIT RELOAD TIMER ........................................................................... 229
12.1 Overview of the 16-bit Reload Timer ..............................................................................................
12.2 Block Diagram of the 16-bit Reload Timer ......................................................................................
12.3 16-bit Reload Timer Pins ................................................................................................................
12.4 16-bit Reload Timer Registers ........................................................................................................
12.4.1 Timer Control Status Register, Upper Byte (TMCSRH0/TMCSRH1) ........................................
12.4.2 Timer Control Status Register, Lower Byte (TMCSRL0/TMCSRL1) .........................................
12.4.3 16-bit Timer Register (TMR0/TMR1) .........................................................................................
12.4.4 16-bit Reload Register (TMRD0/TMRD1) ..................................................................................
12.5 16-Bit Reload Timer Interrupts ........................................................................................................
12.6 Operation of the 16-bit Reload Timer .............................................................................................
12.6.1 Internal Clock Mode (reload mode) ...........................................................................................
12.6.2 Internal Clock Mode (single-shot mode) ....................................................................................
12.6.3 Event Count Mode .....................................................................................................................
12.7 Usage Notes on the 16-bit Reload Timer .......................................................................................
12.8 Sample Programs for the 16-bit Reload Timer ...............................................................................
230
233
235
236
237
239
241
242
243
244
246
248
250
252
253
CHAPTER 13 16-BIT PPG TIMER .................................................................................. 257
13.1 Overview of 16-bit PPG Timer ........................................................................................................
13.2 Block Diagram of 16-bit PPG Timer ................................................................................................
13.3 16-bit PPG Timer Pins ....................................................................................................................
13.4 16-bit PPG Timer Registers ............................................................................................................
13.4.1 PPG Down Counter Register (PDCR0 to PDCR2) ....................................................................
13.4.2 PPG Period Setting Buffer Register (PCSR0 to PCSR2) ..........................................................
13.4.3 PPG Duty Setting Buffer Register (PDUT0 to PDUT2) .............................................................
13.4.4 PPG Control Status Register (PCNTL0 to PCNTL2, PCNTH0 to PCNTH2) .............................
13.5 16-bit PPG Timer Interrupts ............................................................................................................
13.6 Operation of 16-bit PPG Timer .......................................................................................................
13.7 Usage Notes on the 16-bit PPG Timer ...........................................................................................
13.8 Sample Programs for the 16-bit PPG Timer ...................................................................................
258
259
260
262
264
265
266
267
271
273
276
277
CHAPTER 14 MULTI-FUNCTIONAL TIMER .................................................................. 279
14.1 Overview of Multi-functional Timer .................................................................................................
14.2 Block Diagram of Multi-functional Timer .........................................................................................
14.3 Multi-functional Timer Pins .............................................................................................................
14.4 Registers of Multi-functional Timer .................................................................................................
14.4.1 Compare Clear Buffer Register (CPCLRB) and Compare Clear Register (CPCLR) .................
14.4.2 Timer Data Register (TCDT) .....................................................................................................
14.4.3 Timer Control Status Register (TCCSH, TCCSL) ......................................................................
14.4.4 Output Compare Buffer Registers (OCCPB0 to OCCPB5) /
Output Compare Registers (OCCP0 to OCCP5) .......................................................................
14.4.5 Compare Control Registers (OCS0 to OCS5) ...........................................................................
14.4.6 Input Capture Register (IPCP0 to IPCP3) .................................................................................
14.4.7 Input Capture Control Status Registers (ICS23, PICS01) .........................................................
14.4.8 16-bit Timer Register (TMRR0/TMRR1/TMRR2) .......................................................................
14.4.9 16-bit Timer Control Register (DTCR0/DTCR1/DTCR2) ...........................................................
14.4.10 Waveform Control Register (SIGCR) ........................................................................................
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280
282
286
289
293
294
295
299
301
305
306
313
314
318
14.5 Multi-functional Timer Interrupts .....................................................................................................
14.6 Operation of Multi-functional Timer .................................................................................................
14.6.1 Operation of 16-bit free-run timer ..............................................................................................
14.6.2 Operation of 16-bit Output Compare .........................................................................................
14.6.3 Operation of 16-bit Input Capture ..............................................................................................
14.6.4 Operation of Waveform Generator ............................................................................................
14.7 Usage Notes on the Multi-functional Timer .....................................................................................
14.8 Sample Programs for the Multi-functional Timer ............................................................................
320
324
325
332
337
339
349
351
CHAPTER 15 MULTI-PULSE GENERATOR .................................................................. 355
15.1 Overview of Multi-pulse Generator .................................................................................................
15.2 Block Diagram of Multi-pulse Generator .........................................................................................
15.3 Multi-pulse Generator Pins .............................................................................................................
15.4 Registers of Multi-pulse Generator .................................................................................................
15.4.1 Output Control Register (OPCR) ...............................................................................................
15.4.2 Output Data Register (OPDR) ...................................................................................................
15.4.3 Output Data Buffer Register (OPDBR) ......................................................................................
15.4.4 Input Control Register (IPCR) ....................................................................................................
15.4.5 Compare Clear Register (CPCR) ..............................................................................................
15.4.6 Timer Buffer Register (TMBR) ...................................................................................................
15.4.7 Timer Control Status Register (TCSR) ......................................................................................
15.4.8 Noise Cancellation Control Register (NCCR) ............................................................................
15.5 Multi-pulse Generator Interrupts .....................................................................................................
15.6 Operation of Multi-pulse Generator ................................................................................................
15.6.1 Operation of Position Detection .................................................................................................
15.6.2 Operation of Data Write Control Unit .........................................................................................
15.6.3 Operation of Output Data Buffer Register .................................................................................
15.6.4 Operation of Data Transfer of Output Data Register .................................................................
15.6.5 Operation of DTTI1 Input Control ..............................................................................................
15.6.6 Operation of Noise Cancellation Function .................................................................................
15.6.7 Operation of 16-bit Timer ...........................................................................................................
15.7 Usage Notes on the Multi-pulse Generator ....................................................................................
15.8 Sample Programs for the Multi-pulse Generator ............................................................................
356
359
367
369
372
376
380
384
388
389
390
392
394
397
399
401
405
407
421
424
425
429
431
CHAPTER 16 PWC Timer ............................................................................................... 433
16.1 Overview of the PWC Timer ...........................................................................................................
16.2 Block Diagram of the PWC Timer ...................................................................................................
16.3 PWC Timer Pins .............................................................................................................................
16.4 PWC Timer Registers .....................................................................................................................
16.4.1 PWC Control Status Register (PWCSH0/PWCSH1, PWCSL0/PWCSL1) ................................
16.4.2 PWC Data Buffer Register (PWC0/PWC1) ...............................................................................
16.4.3 Division Rate Control Register (DIV0/DIV1) ..............................................................................
16.5 PWC Timer Interrupts .....................................................................................................................
16.6 Operation of the PWC Timer ..........................................................................................................
16.6.1 Operation Mode Selection .........................................................................................................
16.6.2 Starting and Stopping the Timer and Pulse-width Measurement and Clearing the Timer .........
16.6.3 Timer Mode Operation ...............................................................................................................
ix
434
435
436
438
439
443
444
445
447
450
451
453
16.6.4 Pulse Width Measurement Mode Operation .............................................................................. 456
16.7 Usage Notes on the PWC Timer .................................................................................................... 461
16.8 Sample Programs for the PWC Timer ............................................................................................ 464
CHAPTER 17 UART ........................................................................................................ 467
17.1 Overview of UART ..........................................................................................................................
17.2 Block Diagram of UART ..................................................................................................................
17.3 UART Pins ......................................................................................................................................
17.4 UART Registers ..............................................................................................................................
17.4.1 Serial Control Register (SCR0/SCR1) .......................................................................................
17.4.2
Serial Mode Register (SMR0/SMR1) .......................................................................................
17.4.3
Serial Status Register (SSR0/SSR1) ........................................................................................
17.4.4 Input Data Register (SIDR0/SIDR1) and Output Data Register (SOR0/SOR1) ........................
17.4.5 Communication Prescaler Control Register (CDCR) .................................................................
17.5 UART Interrupts ..............................................................................................................................
17.5.1 Reception Interrupt Generation and Flag Set Timing ................................................................
17.5.2 Transmission Interrupt Generation and Flag Set Timing ...........................................................
17.6 UART Baud Rates ..........................................................................................................................
17.6.1 Baud Rates Determined Using the Dedicated Baud Rate Generator ........................................
17.6.2 Baud Rates Determined Using the Internal Timer (16-bit Reload Timer 0) ...............................
17.6.3 Baud Rates Determined Using the External Clock ....................................................................
17.7 Operation of UART .........................................................................................................................
17.7.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) .................................................
17.7.2 Operation in Synchronous Mode (Operation Mode 2) ...............................................................
17.7.3 Bidirectional Communication Function (Normal Mode) .............................................................
17.7.4 Master-slave Communication Function (Multiprocessor Mode) .................................................
17.8 Usage Notes on UART ...................................................................................................................
17.9 Sample Program for UART .............................................................................................................
468
470
473
475
476
478
480
482
484
486
488
489
490
492
495
497
498
500
502
504
506
509
510
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT ................................................. 513
18.1 Overview of the DTP/External Interrupt Circuit ...............................................................................
18.2 Block Diagram of the DTP/External Interrupt Circuit ......................................................................
18.3 DTP/External Interrupt Circuit Pins .................................................................................................
18.4 DTP/External Interrupt Circuit Registers .........................................................................................
18.4.1 DTP/interrupt Cause Register (EIRR) .......................................................................................
18.4.2 DTP/interrupt Enable Register (ENIR) .......................................................................................
18.4.3
Request Level Setting Register (ELVR) ..................................................................................
18.5 Operation of the DTP/External Interrupt Circuit ..............................................................................
18.5.1 External Interrupt Function ........................................................................................................
18.5.2 DTP Function .............................................................................................................................
18.6 Usage Notes on the DTP/External Interrupt Circuit ........................................................................
18.7 Sample Programs for the DTP/External Interrupt Circuit ................................................................
514
516
518
520
521
522
524
525
528
529
530
532
CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE ................................... 535
19.1
19.2
19.3
Overview of the Delayed Interrupt Generator Module .................................................................... 536
Delayed Interrupt Generator Module Register ................................................................................ 537
Operation of the Delayed Interrupt Generator Module ................................................................... 538
x
19.4
Usage Notes on the Delayed Interrupt Generator Module ............................................................. 539
CHAPTER 20 8/10-BIT A/D CONVERTER ..................................................................... 541
20.1 Overview of the 8/10-bit A/D Converter ..........................................................................................
20.2 Block Diagram of the 8/10-bit A/D Converter ..................................................................................
20.3 8/10-bit A/D Converter Pins ............................................................................................................
20.4 8/10-bit A/D Converter Registers ....................................................................................................
20.4.1
A/D Control Status Register 1 (ADCS1) ..................................................................................
20.4.2
A/D Control Status Register 0 (ADCS0) ..................................................................................
20.4.3
A/D Data Register (ADCR0/ADCR1) .......................................................................................
20.5 8/10-bit A/D Converter Interrupts ....................................................................................................
20.6 Operation of the 8/10-bit A/D Converter .........................................................................................
20.6.1
Conversion using EI2OS ..........................................................................................................
20.6.2
A/D Conversion Data Protection Function ...............................................................................
20.7 Usage Notes on the 8/10-bit A/D Converter ...................................................................................
20.8 Sample Program 1 for the 8/10-bit A/D Converter (Single Conversion Mode Using EI2OS) ..........
20.9 Sample Program 2 for the 8/10-bit A/D Converter (Continuous Conversion Mode Using EI2OS) ..
20.10 Sample Program 3 for the 8/10-bit A/D Converter (Stop Conversion Mode Using EI2OS) ............
542
544
546
548
549
551
554
556
557
560
561
563
564
566
568
CHAPTER 21 ROM CORRECTION FUNCTION ............................................................. 571
21.1 Overview of the ROM Correction Function .....................................................................................
21.2 Block Diagram of ROM Correction Function ...................................................................................
21.3 ROM Correction Function Registers ...............................................................................................
21.3.1
Program Aaddress Detection Register (PADR0/PADR1) .........................................................
21.3.2 Program Address Detection Control Status Register (PACSR) ................................................
21.4 Operation of the ROM Correction Function ....................................................................................
21.5 Example of Using ROM Correction Function ..................................................................................
572
573
574
575
576
578
579
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE .......................... 583
22.1
22.2
Overview of the ROM Mirroring Function Selection Module ........................................................... 584
ROM Mirroring Function Selection Register (ROMM) .................................................................... 585
CHAPTER 23 512K / 1024K BIT FLASH MEMORY ....................................................... 587
23.1 Overview of the 512K / 1024K Bit Flash Memory ...........................................................................
23.2 512K / 1024K Bit Flash Memory Sector Configuration ...................................................................
23.3 Flash Memory Control Status Register (FMCS) .............................................................................
23.4 Method of Starting the Automatic Algorithm in Flash Memory ........................................................
23.5 Verifying Automatic Algorithm Execution Status .............................................................................
23.5.1 Data Polling Flag (DQ7) ............................................................................................................
23.5.2 Toggle Bit Flag (DQ6) ................................................................................................................
23.5.3
Time limit Exceeded Flag (DQ5) ..............................................................................................
23.5.4 Sector Deletion Timer Flag (DQ3) .............................................................................................
23.6 Detailed Explanation on the Flash Memory Write/Delete ...............................................................
23.6.1 Setting the Read/Reset Status ..................................................................................................
23.6.2 Writing the Data .........................................................................................................................
23.6.3 Deleting the Data (Chip Deletion) ..............................................................................................
23.6.4 Deleting the Data (Sector Deletion) ...........................................................................................
xi
588
589
590
592
593
595
597
598
599
600
601
602
604
605
23.6.5 Temporarily Stopping the Sector Deletion .................................................................................
23.6.6 Restarting the Sector Deletion ...................................................................................................
23.7 Flash Security Feature ....................................................................................................................
23.8 Programming Example of 512K Bit Flash Memory .........................................................................
607
608
609
610
CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION
FOR SERIAL WRITING ............................................................................ 615
24.1
24.2
24.3
24.4
24.5
Standard Configuration for Serial On-board Writing (Fujitsu Standard) .........................................
Example of Connection for Serial Writing (When Power Supplied by User) ...................................
Example of Connection for Serial Writing (When Power Supplied from Writer) .............................
Example of Minimum Connection with Flash Microcontroller Programmer
(When Power Supplied by User) ....................................................................................................
Example of Minimum Connection with Flash Microcontroller Programmer
(When Power Supplied from Writer) ...............................................................................................
616
618
620
622
624
APPENDIX ......................................................................................................................... 627
APPENDIX A I/O MAP ...............................................................................................................................
APPENDIX B Instructions ...........................................................................................................................
B.1 Instruction Types ............................................................................................................................
B.2 Addressing .....................................................................................................................................
B.3 Direct Addressing ...........................................................................................................................
B.4 Indirect Addressing ........................................................................................................................
B.5 Execution Cycle Count ...................................................................................................................
B.6 Effective address field ....................................................................................................................
B.7 How to Read the Instruction List ....................................................................................................
B.8 F2MC-16LX Instruction List ............................................................................................................
B.9 Instruction Map ...............................................................................................................................
628
635
636
637
639
645
653
656
657
660
674
INDEX................................................................................................................................... 697
xii
Main changes in this edition
Page
Section
-
Change Results
The product name is changed to "MB90460/465 series".
83
CHAPTER 5 CLOCK
5.3 Clock Selection Register (CKSCR)
The function column of bit 14 in Table 5.3-1 is changed.
("· Writing has no effect on the operation." is added.)
106
CHAPTER 6
LOW POWER CONSUMPTION MODE
6.6 State Change Diagram
Figure 6.6-1 is changed.
109
CHAPTER 6
LOW POWER CONSUMPTION MODE
"*3" under Table 6.7-1 is changed.
6.7 State of Pins in Standby Mode and during
Reset
123
CHAPTER 7 INTERRUPT
7.3.2 Interrupt Control Register Functions
The summary is changed.
230
CHAPTER 12 16-BIT RELOAD TIMER
12.1 Overview of the 16-bit Reload Timer
"● External trigger operation" is changed.
253
CHAPTER 12 16-BIT RELOAD TIMER
12.8 Sample Programs for the 16-bit Reload
Timer
"● Coding example" is changed.
298
CHAPTER 14
MULTI-FUNCTIONAL TIMER
14.4.3 Timer Control Status Register
(TCCSH, TCCSL)
The function column of bit 3 in Table 14.4-2 is changed.
("· Even after "1" is written, the counter value is not initialized
if "0" is written to this bit before the next count clock." is
added.)
521
CHAPTER 18
DTP/EXTERNAL INTERRUPT CIRCUIT
18.4.1 DTP/interrupt Cause Register (EIRR)
"■ DTP/interrupt Cause Register (EIRR)" is changed.
("Notes:" is added.)
522
CHAPTER 18
"■ DTP/interrupt Enable Register (ENIR)" is changed.
DTP/EXTERNAL INTERRUPT CIRCUIT
("Note:" is added.)
18.4.2 DTP/interrupt Enable Register (ENIR)
525
CHAPTER 18
DTP/EXTERNAL INTERRUPT CIRCUIT
18.5 Operation of the DTP/External Interrupt
Circuit
"■ Setting the DTP/external Interrupt Circuit" is changed.
("1. Set as an input port the general I/O port to be used also as
a pin to input external interrupts." is added.)
530
CHAPTER 18
DTP/EXTERNAL INTERRUPT CIRCUIT
18.6 Usage Notes on the DTP/External
Interrupt Circuit
"● Input polarities of external interrupts" is changed.
("If the request input level is level setting, the pulse width
requires a longer period than the minimum pulse width stated
on the data sheet. Also, as long as the interrupt input pin
retains the active level, interrupt requests continue to be
generated to the interrupt controller, even if the DTP/external
interrupt cause register is cleared." is added.)
552
CHAPTER 20 8/10-BIT A/D CONVERTER The function column of bit5 to bit3 in Table 20.4-2 is changed.
20.4.2 A/D Control Status Register 0 (ADCS0) ("Notes:" is added.)
xiii
Page
Section
Change Results
"■ Temporarily Stopping the Sector Deletion" is changed.
(· up to 15 µs → up to 20 µs
· The sector deletion temporary stop command must be
executed 20 µs or more after the sector deletion command or
sector deletion restart command is issued.)
607
CHAPTER 23
512K / 1024K BIT FLASH MEMORY
23.6.5 Temporarily Stopping the Sector
Deletion
616
CHAPTER 24
EXAMPLE OF F2MC-16LX MB90F462/
F462A/F463A CONNECTION FOR SERIAL
Table 24.1-1 is changed.
WRITING
24.1 Standard Configuration for Serial
On-board Writing (Fujitsu Standard)
The vertical lines marked in the left side of the page show the changes.
xiv
CHAPTER 1
OVERVIEW
This chapter describes the main features and basic
specifications of the MB90460/465 series.
1.1 MB90460/465 Series Features
1.2 MB90460/465 Series Product line-up
1.3 Block Diagram of MB90460/465 Series
1.4 Pin Assignment
1.5 Package Dimensions
1.6 I/O Pins and Pin Functions
1.7 I/O Circuit Types
1
CHAPTER 1 OVERVIEW
1.1
MB90460/465 Series Features
The MB90460/465 series is a line of general-purpose, 16-bit microcontrollers designed
for those applications which require high-speed real-time processing, proving to be
suitable for various industrial machines and motor control (AC induction motor and
brushless DC motor). These microcontrollers consist of a multi-functional timer for AC/
DC motor control and a multi-pulse generator for DC motor control, which can generate
various type of waveform.
The instruction set is designed to be optimized for controller applications which
inheriting the AT architecture of F2MC-16LX family and allow a wide range of control
tasks to be processed efficiently at high speed.
■ MB90460/465 Series Features
● Clock
• Embedded PLL clock multiplication circuit
• Operating clock (PLL clock) can selected from divided-by-2 of oscillation or one to four times the
oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz)
• Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL clock,
operation at Vcc of 5.0 V)
● CPU addressing space of 16 Mbytes
• Internal 24-bit addressing
● Instruction set optimized for controller applications
• Rich data types (bit, byte, word, long word)
• Rich addressing mode (23 types)
• High code efficiency
• Enhanced precision calculation realized by the 32-bit accumulator
● Instruction set designed for high level language (C) and multi-task operations
• Adoption of system stack pointer
• Enhanced pointer indirect instructions
• Barrel shift instructions
● Program patch function (2 address pointer)
● Improved execution speed
• 4-byte instruction queue
2
CHAPTER 1 OVERVIEW
● Powerful interrupt function
• Priority level programmable: 8 levels
• 32 factors of stronger interrupt function
● Automatic data transmission function independent of CPU operation
• Extended intelligent I/O service function (EI2OS)
• Maximum 16 channels
● Low-power consumption (standby) mode
• Sleep mode (mode in which CPU operating clock is stopped)
• Time-base timer mode (mode in which other than oscillation and time-base timer are stopped)
• Stop mode (mode in which oscillation is stopped)
• CPU intermittent operation mode
● Package
• LQFP-64 (FPT-64P-M09: 0.65 mm pitch)
• QFP-64 (FPT-64P-M06: 1.00 mm pitch)
• SDIP-64 (DIP-64P-M01: 1.78 mm pitch)
● Process
• CMOS technology
■ Internal Peripheral Features
● I/O port
•
Maximum of 51 ports
● 18-bit time-base counter/watchdog timer: 1 channel
● Watchdog timer: 1 channel
● PWC: 2 channels (MB90460 series), 1 channel (MB90465 series)
● 16-bit reload timer: 1 channel
● 16-bit PPG timer: 1 channel
● Multi-functional timer (for AC/DC motor control): 1 channel
• 16-bit free-run timer with up or up-down mode selection and buffer: 1 channel
• 16-bit output compare with buffer: 6 channels
• 16-bit input capture: 4 channels
• 16-bit PPG timer: 1 channel
3
CHAPTER 1 OVERVIEW
• Waveform generator (16-bit timer: 3 channels, 3-phase waveform or dead time)
● Multi-pulse generator (for DC motor control): 1 channel (not present in MB90465 series)
• 16-bit reload timer: 1 channel (can be used individually in MB90465 series)
• 16-bit PPG timer: 1 channel (not present in MB90465 series)
• Waveform sequencer (includes16-bit timer with buffer and compare clear function) (not present in
MB90465 series)
● UART: 2 channels
• With full-duplex double buffer (8-bit length)
• Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively
used
● DTP/External interrupt circuit: 8 channels
• A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt
triggered by an external input
● Delayed interrupt generation module
• Generates an interrupt request for switching tasks
● 8/10-bit A/D converter: 8 channels
• Selectable 8/10-bit resolution
4
CHAPTER 1 OVERVIEW
1.2
MB90460/465 Series Product line-up
The MB90460/465 series contains 6 different devices. Table 1.2-1 lists the product lineup.
■ MB90460/465 Series Product Line-up
Table 1.2-1 MB90460/465 Series Product Line-up (1/2)
Part number
MB90V460
MB90F462
MB90F462A
MB90F463A
MB90462
MB90467
Parameter
Classification
ROM size
RAM size
—
Flash type ROM with security
Mask ROM
—
64K Bytes
128K Bytes
64K Bytes
8K Bytes
2K Bytes
Number of instruction: 351
Minimum execution time: 62.5 ns / 4 MHz (PLL x 4)
CPU function
Addressing mode: 23
Data bit length: 1, 8, 16 bits
Maximum memory space: 16 MBytes
I/O port
I/O port (CMOS): 51
PWC
Pulse width counter timer: 2 channels
1 channel
With full-duplex double buffer (8-bit length)
UART
Clock asynchronized or clock synchronized transmission (with start and stop bits) can be
selectively used
Reload timer: 2 channels
16-bit reload
Reload mode, single-shot mode or event count mode selectable
timer
Can be worked with multi-pulse generator (MB90460 series only) or individually
PPG timer: 3 channels
2 channels
16-bit PPG timer PWM mode or single-shot mode selectable
Can be worked with multi-functional timer / multi-pulse generator (MB90460 series only) or
individually
16-bit free-run timer with up or up/down mode selection and buffer: 1 channel
Multi-functional
16-bit output compare: 6 channels
timer
16-bit input capture: 4 channels
(for AC/DC
16-bit PPG timer: 1 channel
motor control)
Waveform generator (16-bit timer: 3 channels, 3-phase waveform or dead time)
16-bit PPG timer: 1 channel
Multi-pulse
16-bit reload timer operation (toggle output, one shot output selectable)
generator
Event counter function, 1 channel built-in
Not present
(for DC motor
Waveform sequencer (includes 16-bit timer with buffer and compare clear
control)
function)
8/10-bit A/D
8/10-bit resolution:8 channels
converter
Conversion time: Min. 6.13 µs (16 MHz internal clock)
External
8 independent channels
interrupt
Selectable causes: Rising edge, falling edge, “L” level or “H” level
Low-power
Stop mode / Sleep mode / CPU intermittent operation mode
consumption
Process
CMOS
5
CHAPTER 1 OVERVIEW
Table 1.2-1 MB90460/465 Series Product Line-up (2/2)
Part number
MB90V460
MB90F462
MB90F462A
MB90F463A
Parameter
6
LQFP-64 (FPT-64P-M09: 0.65 mm pitch)
QFP-64 (FPT-64P-M06: 1.00 mm pitch)
SDIP-64 (DIP-64P-M01: 1.78 mm pitch)
Package
PGA256
Operating
voltage
5V ± 10% @16 MHz
MB90462
MB90467
CHAPTER 1 OVERVIEW
1.3
Block Diagram of MB90460/465 Series
Figure 1.3-1 shows a overall block diagram of the MB90460/465 series.
■ MB90460/465 Series Block Diagram
Figure 1.3-1 MB90460/465 Series Overall Block Diagram
X0
CPU
Clock control
circuit
X1
F2MC-16LX family core
Time-base timer
Reset circuit
(Watchdog timer)
RSTX
Other pins
Vss x 2, Vcc x 1, MD0-2, C
Delayed interrupt generator
Interrupt controller
Multi-functional timer
P13/INT3 to 2
P14/INT4
8
P40/SIN0
P41/SOT0
P42/SCK0
DTP/External interrupt
16-bit input capture
(Ch.0 to Ch.3)
UART
(Ch.0)
P16/INT6/TO0
P15/INT5/TIN0
P01/OPT1*1
P02/OPT2*1
16-bit reload timer
(Ch.0)
3
3
Waveform*2
sequencer
F2MC-16LX bus
16-bit PPG*2
(Ch.1)
P36/PPG1*1
P03/OPT3*1
P46/PPG2
PWC*2
(Ch.0)
16-bit PPG
(Ch.2)
CMOS I/O port 0, 1, 3, 4
P30/RTO0 (U)
P31/RTO1 (X)
P32/RTO2 (V)
P33/RTO3 (Y)
P34/RTO4 (W)
P35/RTO5 (Z)
16-bit output
compare
(Ch.0 to Ch.5)
Waveform
generator
P10/INT0/DTTI0
P20/TIN1
P21/TO1
16-bit reload timer
(Ch.1)
P22/PWI1
P23/PWO1
P60/SIN1
P61/SOT1
P62/SCK1
UART
(Ch.1)
P63/INT7
CMOS I/O port 1, 2, 3, 6
CMOS I/O port 5
RAM
A/D converter
ROM
ROM correction
P24/IN0 to
P27/IN3
P17/FRCK
PWC
(Ch.1)
P04/OPT4*1
P05/OPT5*1
P12/INT2/
P06/PWI0*1
P07/PWO0*1
4
4
16-bit free-run
timer
Multi-pulse generator
P43/SNI0*1 to
P45/SNI2*1
P00/OPT0*1
P37/PPG0
16-bit PPG
(Ch.0)
P11/INT1
(8/10 bit)
8
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
ROM mirroring
Note: P00 to P07 (8 channels): With registers that can be used as input pull-up resistors
P10 to P17 (8 channels): With registers that can be used as input pull-up resistors
AVCC
AVR
AVSS
*1: Resource function for these pins are not applicable to MB90465 series
*2: Not present in MB90465 series
7
CHAPTER 1 OVERVIEW
1.4
Pin Assignment
Figure 1.4-1 to Figure 1.4-3 show the pin assignment diagrams for the MB90460/465
series.
■ FPT-64P-M06 Pin Assignment
64
63
62
61
60
59
58
57
56
55
54
53
52
P43/SNI0*2
P42/SCK0
P41/SOT0
P40/SIN0
P37/PPG0
P36/PPG1*2
C
Vcc
P35*1/RTO5 (Z)
P34*1/RTO4 (W)
P33*1/RTO3 (Y)
P32*1/RTO2 (V)
P31*1/RTO1 (X)
Figure 1.4-1 FPT-64P-M06 Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
QFP-64
(TOP VIEW)
(FPT-64P-M06)
38
37
36
17
18
19
35
34
33
RSTX
MD1
MD2
X0
X1
VSS
P00*1/OPT0*2
P01*1/OPT1*2
P02*1/OPT2*2
P03*1/OPT3*2
P04*1/OPT4*2
P05*1/OPT5*2
P06*1/PWI0*2
*1: Heavy current pins
*2: Resource function for these pins are
not applicable to MB90465 series
8
51
50
49
48
47
46
45
44
43
42
41
40
39
14
15
16
20
21
22
23
24
25
26
27
28
29
30
31
32
P44/SNI1*2
P45/SNI2*2
P46/PPG2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/SIN1
P61/SOT1
P62/SCK1
P63/INT7
MD0
P30*1/RTO0 (U)
VSS
P27/IN3
P26/IN2
P25/IN1
P24/IN0
P23/PWO1
P22/PWI1
P21/TO1
P20/TIN1
P17/FRCK
P16/INT6/TO0
P15/INT5/TIN0
P14/INT4
P13/INT3
P12/INT2/DTTI1*2
P11/INT1
P10/INT0/DTTI0
P07/PWO0*2
CHAPTER 1 OVERVIEW
■ FPT-64P-M09 Pin Assignment
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P44/SNI1*2
P43/SNI0*2
P42/SCK0
P41/SOT0
P40/SIN0
P37/PPG0
P36/PPG1*2
C
Vcc
P35*1/RTO5 (Z)
P34*1/RTO4 (W)
P33*1/RTO3 (Y)
P32*1/RTO2 (V)
P31*1/RTO1 (X)
P30*1/RTO0 (U)
VSS
Figure 1.4-2 FPT-64P-M09 Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LQFP-64
(TOP VIEW)
(FPT-64P-M09)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P27/IN3
P26/IN2
P25/IN1
P24/IN0
P23/PWO1
P22/PWI1
P21/TO1
P20/TIN1
P17/FRCK
P16/INT6/TO0
P15/INT5/TIN0
P14/INT4
P13/INT3
P12/INT2/DTTI1*2
P11/INT1
P10/INT0/DTTI0
P63/INT7
MD0
RSTX
MD1
MD2
X0
X1
VSS
P00*1/OPT0*2
P01*1/OPT1*2
P02*1/OPT2*2
P03*1/OPT3*2
P04*1/OPT4*2
P05*1/OPT5*2
P06/PWI0*2
P07/PWO0*2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P45/SNI2*2
P46/PPG2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/SIN1
P61/SOT1
P62/SCK1
*1: Heavy current pins
*2: Resource function for these pins
are not applicable to MB90465 series
9
CHAPTER 1 OVERVIEW
■ DIP-64P-M01 Pin Assignment
Figure 1.4-3 DIP-64P-M01 Pin Assignment
C
P36/PPG1*2
P37/PPG0
P40/SIN0
P41/SOT0
P42/SCK0
P43/SNI0*2
P44/SNI1*2
P45/SNI2*2
P46/PPG2
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/SIN1
P61/SOT1
P62/SCK1
P63/INT7
MD0
RSTX
MD1
MD2
X0
X1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SDIP-64
(TOP VIEW)
(DIP-64P-M01)
*1: Heavy current pins
*2: Resource function for these pins
are not applicable to MB90465 series
10
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Vcc
P35*1/RTO5 (Z)
P34*1/RTO4 (W)
P33*1/RTO3 (Y)
P32*1/RTO2 (V)
P31*1/RTO1 (X)
P30*1/RTO0 (U)
VSS
P27/IN3
P26/IN2
P25/IN1
P24/IN0
P23/PWO1
P22/PWI1
P21/TO1
P20/TIN1
P17/FRCK
P16/INT6/TO0
P15/INT5/TIN0
P14/INT4
P13/INT3
P12/INT2/DTTI1*2
P11/INT1
P10/INT0/DTTI0
P07/PWO0*2
P06/PWI0*2
P05*1/OPT5*2
P04*1/OPT4*2
P03*1/OPT3*2
P02*1/OPT2*2
P01*1/OPT1*2
P00*1/OPT0*2
CHAPTER 1 OVERVIEW
1.5
Package Dimensions
Three types of packages are available for MB90460/465 series. Figure 1.5-1 to Figure
1.5-3 show the package dimensions.
■ DIP-64P-M01 Package Dimensions
Figure 1.5-1 DIP-64P-M01 Package Dimensions
64-pin plastic SH-DIP
Lead pitch
1.778mm(70mil)
Package width ×
package length
17 × 58 mm
Sealing method
Plastic mold
Mounting height
5.65 mm MAX
(DIP-64P-M01)
64-pin plastic SH-DIP
(DIP-64P-M01)
Note: Pins width and pins thickness include plating thickness.
+0.22
+.009
58.00 –0.55 2.283 –.022
INDEX-1
17.00±0.25
(.669±.010)
INDEX-2
+0.70
4.95 –0.20
+.028
.195 –.008
+0.50
0.70 –0.19
+.020
.028 –.007
0.27±0.10
(.011±.004)
+0.20
3.30 –0.30
+.008
.130 –.012
+0.40
1.378 –0.20
+.016
.0543 –.008
C
1.778(.0700)
0.47±0.10
(.019±.004)
2001-2008 FUJITSU MICROELECTRONICS LIMITED D64001S-c-4-6
19.05(.750)
+0.50
0.25(.010)
M
1.00 –0
+.020
0~15
.039 –.0
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
11
CHAPTER 1 OVERVIEW
■ FPT-64P-M06 Package Dimensions
Figure 1.5-2 FPT-64P-M06 Package Dimensions
64-pin plastic QFP
Lead pitch
1.00 mm
Package width ×
package length
14 × 20 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP64-14×20-1.00
(FPT-64P-M06)
64-pin plastic QFP
(FPT-64P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
24.70±0.40(.972±.016)
* 20.00±0.20(.787±.008)
51
0.17±0.06
(.007±.002)
33
32
52
18.70±0.40
(.736±.016)
Details of "A" part
*14.00±0.20
(.551±.008)
+0.35
3.00 –0.20
INDEX
+.014
.118 –.008
(Mounting height)
20
64
0~8°
1
19
1.00(.039)
0.42±0.08
(.017±.003)
0.20(.008)
+0.15
M
0.25 –0.20
1.20±0.20
(.047±.008)
+.006
.010 –.008
(Stand off)
"A"
0.10(.004)
C
2003-2008 FUJITSU MICROELECTRONICS LIMITED F64013S-c-5-6
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
12
CHAPTER 1 OVERVIEW
■ FPT-64P-M09 Package Dimensions
Figure 1.5-3 FPT-64P-M09 Package Dimensions
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12 × 12 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP64-12×12-0.65
(FPT-64P-M09)
64-pin plastic LQFP
(FPT-64P-M09)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
* 12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.0057±.0022)
33
32
49
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
(Mounting height)
0.25(.010)
INDEX
0~8°
17
64
1
0.65(.026)
C
0.32±0.05
(.013±.002)
2003-2008 FUJITSU MICROELECTRONICS LIMITED F64018S-c-3-6
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
"A"
16
0.13(.005)
0.10±0.10
(.004±.004)
(Stand off)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
13
CHAPTER 1 OVERVIEW
1.6
I/O Pins and Pin Functions
Table 1.6-1 lists the MB90460/465 series I/O pins and their functions. Table 1.7-1 lists the
I/O circuit types.
The letter in the "I/O circuit type" column in Table 1.6-1 refers to the letter in the "Type"
column Table 1.7-1.
■ I/O Pins and Pin Functions
Table 1.6-1 Pin Description (1/5)
Pin no.
Pin name
I/O
circuit
Pin status
during reset
30,31
X0,X1
A
Oscillating
Oscillation input pins.
27
RSTX
B
Reset input
External reset input pin.
QFPM09*1
QFPM06*2
SDIP*3
22,23
23,24
19
20
P00 to P05
25 to 30
26 to 31
33 to 38
31
32
39
OPT0 to
OPT5*4
General-purpose I/O ports.
Output terminals OPT0 to OPT5 of the waveform
sequencer. These pins output the waveforms
specified at the output data buffer register of the
waveform sequencer circuit. Output is generated
when OPE0 to OPE5 of OPCR is enabled.
D
P06
General-purpose I/O ports.
E
PWI0*4
PWC 0 signal input pin.
P07
32
33
40
General-purpose I/O ports.
E
PWO0
PWC 0 signal output pin.
Port input
P10
INT0
33
34 to 35
41 to 42
C
P11
35
42
14
Can be used as interrupt request input channel 0.
Input is enabled when "1" is set in EN0 in standby
mode.
General-purpose I/O ports.
C
INT1
General-purpose I/O ports.
RTO0 to RTO5 pins for fixed-level input. This
function is enabled when the waveform generator
enables its input bits.
DTTI0
34
Function
Can be used as interrupt request input channel 1.
Input is enabled when "1" is set in EN1 in standby
mode.
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Description (2/5)
Pin no.
QFPM09*1
QFPM06*2
Pin name
SDIP*3
I/O
circuit
Pin status
during reset
P12
General-purpose I/O ports.
Can be used as interrupt request input channel 2.
Input is enabled when "1" is set in EN2 in standby
mode.
INT2
35
36
43
Function
C
OPT0 to OPT5 pins for fixed-level input. This
function is enabled when the waveform sequencer
enables its input bits.
DTTI1*4
P13, P14
General-purpose I/O ports.
Port input
36, 37
37, 38
44, 45
INT3,
INT4
Can be used as interrupt request input channels 3 to
4. Input is enabled when "1" is set in EN3 to EN4
in standby mode.
C
P15
38
39
46
INT5
General-purpose I/O ports.
Can be used as interrupt request input channel 5.
Input is enabled when "1" is set in EN5 in standby
mode.
C
TIN0
External clock input pin for reload timer 0.
P16
39
40
47
INT6
General-purpose I/O ports.
Can be used as interrupt request input channel 6.
Input is enabled when "1" is set in EN6 in standby
mode.
C
TO0
Event output pin for reload timer 0.
P17
40
41
48
General-purpose I/O ports.
C
FRCK
External clock input pin for free-run timer.
P20
41
42
49
F
TIN1
43
50
General-purpose I/O ports.
F
TO1
Event output pin for reload timer 1.
P22
43
44
51
General-purpose I/O ports.
F
PWI1
PWC 1 signal input pin.
P23
44
45
General-purpose I/O ports.
External clock input pin for reload timer 1.
P21
42
Port input
52
General-purpose I/O ports.
F
PWO1
PWC 1 signal output pin.
15
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Description (3/5)
Pin no.
QFPM09*1
QFPM06*2
Pin name
SDIP*3
I/O
circuit
Pin status
during reset
P24 to P27
45 to 48
50 to 55
46 to 49
51 to 56
General-purpose I/O ports.
IN0 to IN3
Trigger input pins for input capture channels 0 to 3.
When input capture channels 0 to 3 are used for
input operation, these pins are enabled as required
and must not be used for any other I/P.
P30 to P35
General-purpose I/O ports.
53 to 56
58 to 63
F
RTO0 to
RTO5
Waveform generator output pins. These pins
output the waveforms specified at the waveform
generator. Output is generated when waveform
generator output is enabled.
G
P36, 37
58,59
60
61
59, 60
61
62
2, 3
PPG1*4,
PPG0
General-purpose I/O ports.
H
General-purpose I/O ports.
SIN0
Serial data input pin for UART channel 0. While
UART
channel 0 is operating for input, the input of this
pin is used as required and must not be used for
any other input.
P41
General-purpose I/O ports.
4
F
5
F
P42
63
6
F
P43
64
7
16
1
8
F
P44
Serial data output pin for UART channel 0. This
function is enabled when UART channel 0 enables
data output.
Serial clock I/O pin for UART channel 0. This
function is enabled when UART channel 0 enables
clock output.
General-purpose I/O ports.
SNI0*4
64
Port input
General-purpose I/O ports.
SCK0
63
Output pins for PPG channels 1, 0. This function
is enabled when PPG channels 1, 0 enable output.
P40
SOT0
62
Function
F
Trigger input pins for position detection of the
waveform sequencer. When pins 0 are used for
input operation, these pins are enabled as required
and must not be used for any other I/P.
General-purpose I/O ports.
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Description (4/5)
Pin no.
QFPM09*1
QFPM06*2
Pin name
SDIP*3
I/O
circuit
Pin status
during reset
P45
1
2
9
General-purpose I/O ports.
F
SNI2*4
Port input
P46
2
3
10
F
Output pin for PPG channel 2. This function is
enabled when PPG channel 2 output is enabled.
P50 to P57
General-purpose I/O ports.
3 to 10
4 to 11
11 to 18
AN0 to
AN7
I
11
12
19
AVCC
J
12
13
20
AVR
K
13
14
21
AVSS
J
15
15
16
Analog input A/D converter analog input pins. This function is
enabled when the analog input specification is
enabled (ADER).
Vcc power input pin for analog circuits.
Power input
P60
General-purpose I/O ports.
SIN1
Serial data input pin for UART channel 1. While
UART
channel 1 is operating for input, the input of this
pin is used as required and must not be used for
any other input.
P61
General-purpose I/O ports.
22
F
23
Port input
Serial data output pin for UART channel 1. This
function is enabled when UART channel 1 enables
data output.
F
P62
17
24
General-purpose I/O port.
F
SCK1
P63
17
18
Vref+ input pin for the A/D converter. This
voltage must not exceed AVcc. Vref- is fixed to
AVss.
Vss power input pin for analog circuits.
SOT1
16
Trigger input pin for position detection of the
Multi-pulse generator. When used for input
operation, this pin is
enabled as required and must not be used for any
other I/P.
General-purpose I/O ports.
PPG2
14
Function
25
Serial clock I/O pin for UART channel 1. This
function is enabled when UART channel 1 enables
clock output.
General-purpose I/O port.
F
INT7
Port input
Can be used as interrupt request input channel 7.
Input is enabled when "1" is set in EN7 in standby
mode.
17
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Description (5/5)
Pin no.
QFPM09*1
QFPM06*2
SDIP*3
18
19
26
Pin name
I/O
circuit
MD0
L
Pin status
during reset
Function
Input pin for operation mode specification.
Connect this pin directly to Vcc or Vss.
Mode input
20,21
21,22
28,29
MD1,MD2
L
24,49
25,50
32,57
Vss
–
Input pins for operation mode specification.
Connect these pins directly to Vcc or Vss.
Power (0 V) input pin.
Power input
56
57
64
Vcc
–
*1: FPT-64P-M09
*2: FPT-64P-M06
*3: DIP-64P-M01
*4: Pin names are not applicable to MB90465 series
18
Power (5 V) input pin.
CHAPTER 1 OVERVIEW
1.7
I/O Circuit Types
Table 1.7-1 summarize the I/O circuit types of MB90460/465 series
■ I/O Circuit Types
Table 1.7-1 I/O Circuit Type (1/3)
Classification
A
Type
Remarks
X1
Xout
N-ch P-ch
Main clock(main clock crystal oscillator)
• At an ocillation feedback resistor of
approximately 1MΩ
P-ch
X0
N-ch
Standby mode control
B
• Hysteresis input
• Resistor approximately 50 kΩ
R
C
R
P-ch
Pull-up control
P-ch
Pout
• CMOS output
• Hysteresis input
• Selectable pull-up resistor
approximately 50 kΩ
• IOL = 4 mA
Nout
N-ch
Hysteresis input
Standby mode control
D
R
P-ch
Pull-up control
P-ch
N-ch
Pout
• CMOS output
• CMOS input
• Selectable pull-up resistor
approximately 50 kΩ
• IOL = 12 mA
Nout
CMOS input
Standby mode control
19
CHAPTER 1 OVERVIEW
Table 1.7-1 I/O Circuit Type (2/3)
Classification
Type
Remarks
E
R
P-ch
Pull-up control
P-ch
Pout
• CMOS output
• CMOS input
• Selectable pull-up resistor
approximately 50 kΩ
• IOL = 4 mA
Nout
N-ch
CMOS input
Standby mode control
F
P-ch
Pout
• CMOS output
• Hysteresis input
• IOL = 4 mA
Nout
N-ch
Hysteresis input
Standby mode control
G
P-ch
Pout
• CMOS output
• CMOS input
• IOL = 12 mA
Nout
N-ch
CMOS input
Standby mode control
H
P-ch
Pout
• CMOS output
• CMOS input
• IOL = 4 mA
Nout
N-ch
CMOS input
Analog input control
Analog input
I
P-ch
IN
N-ch
20
•
•
•
•
CMOS output
CMOS input
Analog input
IOL = 4 mA
CHAPTER 1 OVERVIEW
Table 1.7-1 I/O Circuit Type (3/3)
Classification
Type
Remarks
J
• Power supply input protection circuit
P-ch
Analog input enable
IN
N-ch
Analog input enable
K
• A/D converter reference voltage
(AVR) input pin with protection
circuit
L
• Hysteresis input
P-ch
N-ch
Pout
Nout
CMOS input
Analog input control
Analog input
21
CHAPTER 1 OVERVIEW
22
CHAPTER 2
NOTES ON HANDLING
DEVICES
This chapter describes notes on Handling Devices.
2.1 Notes on Handling Devices
23
CHAPTER 2 NOTES ON HANDLING DEVICES
2.1
Notes on Handling Devices
When handling devices, pay special attention to the following eight items or
procedures:
• Strict observation of maximum rated voltage (latch-up prevention)
• Stabilization of supply voltage
• Power-on
• Treatment of unused input pins
• Treatment of A/D converter power pin
• Notes on external clock
• Caution on operation during PLL clock mode
• Power supply pin
• Analog power-on sequence of A/D converter
■ Notes on Handling Devices
● Strict observation of maximum rated voltage
A latch-up may occur on a CMOS IC if a voltage higher than Vcc or lower than Vss is applied to an input
or output pin other than medium-to-high voltage pins. A latch-up may also occur if a voltage higher than
the rating is applied between Vcc and Vss. A latch-up causes a rapid increase in the power supply current,
which can result in thermal damage to an element. Take utmost care that the maximum rated voltage is not
exceeded.
When turning the power on or off to analog circuits, be sure that the analog supply voltages (AVcc and
AVR) and analog input voltage do not exceed the digital supply voltage (Vcc).
● Stabilize of supply voltages
Even within the operation guarantee range of the Vcc supply voltage, a malfunction can be caused if the
supply voltage undergoes a rapid change. For voltage stabilization guidelines, the Vcc ripple fluctuations
(P-P value) at commercial frequencies (50 to 60 Hz) should be suppressed to "10%" or less of the reference
Vcc value. During a momentary change such as when switching a supply voltage, voltage fluctuations
should also be suppressed so that the "transient fluctuation rate" is 0.1 V/ms or less.
● Power-on
To prevent a malfunction in the built-in voltage drop circuit, secure "50 µs (between 0.2 V and 2.7 V)" or
more for the voltage rise time during power-on.
● Treatment of unused input pins
An unused input pin may cause a malfunction if it is left open. Every unused input pin should be pulled up
or down.
● Treatment of A/D converter power pin
When the A/D converter is not used, connect the pins as follows: AVcc = Vcc, AVss = AVR = Vss.
24
CHAPTER 2 NOTES ON HANDLING DEVICES
● Notes on external clock
When an external clock is used, the oscillation stabilization wait time is required at power-on reset or at
cancellation of sub-clock mode or stop mode. As shown in Figure 2.1-1 , when an external clock is used,
connect only the X0 pin and leave the X1 pin open.
Figure 2.1-1 Sample Application of External Clock
X0
MB90460/465 series
Open
X1
● Caution on operation during PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops
while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its
operation at its self-running frequency. However, Fujitsu will not guarantee results of operation if such
failure occurs.
● Power supply pins
When a device has two or more Vcc or Vss pins, the pins that should have equal potential are connected
within the device in order to prevent a latch-up or other malfunction. To reduce extraneous emission, to
prevent a malfunction of the strobe signal due to an increase in the group level, and to maintain the local
output current rating, connect all these power supply pins to an external power supply and ground them.
The current source should be connected to the Vcc and Vss pins of the device with minimum impedance. It
is recommended that a bypass capacitor of about 0.1 µF be connected near the terminals between Vcc and
Vss.
● Analog power-on sequence of A/D converter
The power to the A/D converter (AVcc, AVR) and analog inputs (AN0 to AN7) must be turned on after the
power to the digital circuits (Vcc) is turned on. When turning off the power, turn off the power to the
digital circuits (Vcc) after turning off the power to the A/D converter and analog inputs. When the power
is turned on or off, AVR should not exceed AVcc. Also, when a pin that is used for analog input is also
used as an input port, the input voltage should not exceed AVcc. (The power to the analog circuits and the
power to the digital circuits can be simultaneously turned on or off.)
25
CHAPTER 2 NOTES ON HANDLING DEVICES
26
CHAPTER 3
CPU
This chapter describes memory space for the MB90460/
465 series.
3.1 CPU
3.2 Memory Space
3.3 Memory Maps
3.4 Addressing
3.5 Memory Location of Multi-byte Data
3.6 Registers
3.7 Dedicated Registers
3.8 General-purpose Registers
3.9 Prefix Codes
27
CHAPTER 3 CPU
3.1
CPU
The F2MC-16LX CPU is a 16-bit CPU designed for use in applications, such as welfare
and mobile equipment, which require high-speed real-time processing. The instruction
set of the F2MC-16LX was designed for controllers so that it can perform various types
of control at high speed and efficiency.
The F2MC-16LX CPU process not only 16-bit data but also 32-bit data using a built-in 32bit accumulator. Memory space, which can be extended up to 16M bytes, can be
accessed in either linear or bank access mode. The instruction set inherits the AT
architecture of F2MC-8L, and has additional instructions supporting high-level
languages. In addition, it has an extended addressing mode, enhanced multiply/divide
instructions and reinforced bit manipulation instructions. The features of the F2MC16LX CPU are shown below:
■ CPU
● Minimum instruction execution time: 62.5 ns (when the source oscillation is 4 MHz and the PLL clock is
multiplied by 4)
● Maximum memory address space: 16M bytes. Access in linear or bank addressing mode
● Instruction set optimum for controller applications
Many data types (bit, byte, word and long word)
As many as 23 addressing modes
Enhanced high-precision arithmetic operation by a 32-bit accumulator
Enhanced signed multiply/divide instructions and RETI instruction function
● Enhanced interrupt function
Eight programmable priority levels
● Automatic transfer function independent of CPU
Extended intelligent I/O service using up to 16 channels
● Instruction set supporting high-level language (C) and multitasking
System stack pointer, instruction set symmetry and barrel shift instructions
● Increased execution speed: 4-byte instruction queue
Note:
The MB90460/465 series runs only in single-chip mode so only internal ROM and RAM and internal
peripheral address space can be accessed.
28
CHAPTER 3 CPU
3.2
Memory Space
All I/O, programs and data are located in the 16-megabyte memory space of the F2MC16LX. A part of the memory space is used for special purposes, such as extended
intelligent I/O service (EI2OS) descriptors, general-purpose registers and vector tables.
■ Memory Space
All I/O, programs, and data are located in the 16-megabyte memory space of the F 2MC-16LX CPU. The
CPU is able to access each resource through an address indicated by the 24-bit address bus.
Figure 3.2-1 shows a sample relationship between the F2MC-16LX system and the memory map.
Figure 3.2-1 Sample Relationship between the F2MC-16LX System and the Memory Map
FFFFFFH
⎧⎪ FFC000H
Programs
⎨
⎩⎪ FF0000H*1
100000H
Data
F2MC-16LX
CPU
Internal bus
010000H
004000H*2
EI2OS
003FE0H*2
Program area
ROM
area
External area*4
ROM area
(FF bank image)
Peripheral function
I/O area
control register (cont’)
External area*4
002000H
Interrupts
*3
⎧000D00H
⎪ 000380H
⎪
⎨
⎧ ⎪⎪ 000180H
⎨
⎩ ⎩ 000100H
Peripheral circuits
General-purpose
ports
F2MC-16LX device
Vector table area
⎧⎪ 0000C0H
⎨
⎪
⎩
0000B0H
⎧⎪
⎨
⎪
⎩
000000H
Data area
General-purpose
register
RAM
area
EI2OS descriptor area
External area*4
Interrupt controller
I/O port and
peripheral function
control register
I/O
area
*1: The size of internal ROM differs for each model.
*2: The area accessible by the image differs for each model.
*3: The size of internal RAM differs for each model.
*4: There is no access in single-chip mode.
29
CHAPTER 3 CPU
■ ROM Area
● Vector table area (address: FFFC00H to FFFFFFH)
• This area is used as a vector table for vector call instructions, interrupt vectors and reset vectors.
• This area is allocated at the highest addresses of the ROM area. The start address of the corresponding
processing routine is set as data in each vector table address.
● Program area (address: up to FFFBFFH)
• ROM is built in as an internal program area.
• The size of internal ROM differs for each model.
■ RAM Area
● Data area (address: from 000100H)
• The static RAM is built in as an internal data area.
• The size of internal RAM differs for each model.
● General-purpose register area (address: 000180H to 00037FH)
• Auxiliary registers used for 8-bit, 16-bit and 32-bit arithmetic operations and transfer are allocated in
this area.
• Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM.
• When this area is used as a general-purpose register, general-purpose register addressing enables highspeed access with short instructions.
● Extended intelligent I/O service (EI2OS) descriptor area (address: 000100H to 00017FH)
• This area retains the transfer modes, I/O addresses, transfer count and buffer addresses.
• Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM.
■ I/O Area
● Interrupt control register area (address: 0000B0H to 0000BFHThe interrupt control registers (ICR00 to
ICR15) correspond to all peripheral functions that have an interrupt function. These registers set
interrupt levels and control the extended intelligent I/O service (EI2OS).
● Peripheral function control register area (address: 000008H to 00000FH, 000019H to 0000AFH,
003FE0H to 003FFFHThis register controls the built-in peripheral functions, inputs and outputs data.
Instruction using I/O addressing e.g. MOV A, io, is not supported for registers area 003FE0H to
003FFFH
● I/O port control register area (address: 000000H to 000006H, 000010H to 000017HThis register
controls I/O ports, inputs and outputs data.
30
CHAPTER 3 CPU
3.3
Memory Maps
This section shows the memory map for each MB90460/465 series model.
■ Memory Maps
Figure 3.3-1 shows the memory maps for the MB90460/465 series.
Figure 3.3-1 Memory Maps
Single-chip mode
(with ROM mirroring function)
FFFFFFH
ROM area
Address #1
FC0000H
010000H
ROM area
(FF bank image)
Address #2
004000H
003FE0H
Address #3
Peripheral area
RAM
area
Register
: Internal access memory
000100H
: Access not allowed
0000C0H
000000H
Peripheral area
Model
Address #1
Address #2
Address #3
MB90462
FF0000H
004000H
000900H
MB90467
FF0000H
004000H
000900H
MB90F462
FF0000H
004000H
000900H
MB90F462A
FF0000H
004000H
000900H
MB90F463A
FE0000H
004000H
000900H
MB90V460
FF0000H*
004000H*
002100H
*: The MB90V460 does not contain ROM. Assume that the development tool uses these area
for its ROM decode areas.
31
CHAPTER 3 CPU
Notes:
• If single-chip mode (without ROM mirroring function) is selected, see "CHAPTER 22
MIRRORING FUNCTION SELECTION MODULE".
ROM
• ROM data in the FF bank can be seen as an image in the higher 00 bank to validate the small
model C compiler. Because addresses of the 16 low order bits in the FF bank are the same, the
table in ROM can be referenced without the "far" specification. For example, when 00C000H is
accessed, the contents of ROM at FFC000H are actually accessed. The ROM area in the FF
bank exceeds 48 Kbytes, and all areas cannot be seen as images in the 00 bank. Because ROM
data from FF4000H to FFFFFFH is seen as an image at 004000H to 00FFFFH, the ROM data table
should be stored in the area from FF4000H to FFFFFFH.
32
CHAPTER 3 CPU
3.4
Addressing
The methods for generating addresses are linear addressing and bank addressing.
In linear addressing, the complete 24-bit address is specified directly by an instruction.
In bank addressing, the upper 8 bits of the address are specified by a bank register for
the required purpose, and the lower 16 bits of the address are specified by the
instruction.
The F2MC-16LX family generally uses bank addressing.
■ Linear Addressing and Bank Addressing
In linear addressing, the 16-Mbyte space is accessed as consecutive address spaces. In bank addressing, the
16-Mbyte space is divided into and managed as 256 64-Kbyte banks.
Figure 3.4-1 is an overview of linear addressing and bank addressing memory management.
Figure 3.4-1 Linear Addressing and Bank Addressing Memory Management
Linear addressing
Bank addressing
FF bank
64 Kbytes
FE bank
FD bank
12 bank
04 bank
03 bank
02 bank
01 bank
00 bank
Specified entirely by an instruction
Specified by an instruction
Specified by a bank register for the required purpose
33
CHAPTER 3 CPU
3.4.1
Address Specification by Linear Addressing
The two types of address specification by linear addressing are specification of a 24-bit
address directly in the operand and specification of the lower 24 bits of a 32-bit generalpurpose register.
■ Linear Addressing by 24-bit Operand Specification
Figure 3.4-2 Example of Direct Specification of a 24-bit Physical Address in Linear Addressing
JMPP 123456H
Old program
counter + program
New program
counter + program
17
12
17452DH
JMPP 123456H
123456H
Next instruction
452D
3456
■ Addressing by Indirect Specification with a 32-bit
Figure 3.4-3 Example of Indirect Specification with a 32-bit General-purpose Register
in Linear Addressing
MOV A,@RL1+7
Old AL
090700H
XXXX
3AH
+7
New AL
003A
RL1
(Upper 8 bits are ignored)
RL1: 32-bit (long-word) general-purpose register
34
240906F9H
CHAPTER 3 CPU
3.4.2
Address Specification by Bank Addressing
In address specification by bank addressing, the 16-Mbyte memory space is divided
into 256 64-Kbyte banks. A bank address that corresponds to each space is specified
in the bank register to determine the upper 8 bits of the address. The lower 16 bits of
the address are specified by the instruction.
The five types of bank registers classified by function are as follows:
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
■ Bank Registers and Access Space
Table 3.4-1 lists the access space and main function of each bank register.
Table 3.4-1 Access Space and Main Function of Each Bank Register
Bank register
name
Access space
Main function
Initial value
after a reset
Program bank
register (PCB)
Program (PC) space
Instruction codes, vector tables and immediate-value data
are stored.
FFH
Data bank register
(DTB)
Data (DT) space
Read/write data is stored. Internal or external peripheral
control registers and data registers are accessed.
00H
Stack (SP) space
This area is used for stack accesses such as when PUSH/
POP instructions and interrupt registers are saved. The SSB
is used when the stack flag in the condition register (CCR:
S) is "1". The USB is used when the stack flag in the
condition register (CCR: S) is "0". *
User stack bank
register (USB)
System stack bank
register (SSB) *1
Additional bank
register (ADB)
Additional (AD)
space
Data that overflows from the data (DT) space is stored.
00H
00H
00H
* : The SSB is always used as an interrupt stack.
35
CHAPTER 3 CPU
Figure 3.4-4 shows the relationship between the memory space divisions and each register.
See "3.7.9 Bank Registers (PCB, DTB, USB, SSB, ADB)", for details.
Figure 3.4-4 Sample Bank Addressing
FFFFFFH
Program space
FF0000H
Physical address
0FFFFFH
: ADB (Additional Bank Register)
0DH
: USB (User Stack Bank Register)
0BH
: DTB (Data Bank Register)
07H
: SSB (System Stack Bank Register)
Data space
0B0000H
7FFFFFH
0FH
User stack space
0D0000H
0BFFFFH
: PCB (Program Bank Register)
Additional space
0F0000H
0DFFFFH
FFH
System stack space
070000H
000000H
■ Bank Addressing and Default Space
To improve instruction coding efficiency, each instruction has a defined default space for each addressing
method, as shown in Table 3.4-2. To use a space other than the default space, specify a prefix code for a
bank before the instruction. This enables the bank space that corresponds to the specified prefix code to be
accessed. See "3.9 Prefix Codes", for details about prefix codes.
Table 3.4-2 Addressing and Default Spaces
Default space
36
Addressing
Program space
PC indirect, program access, branching
Data space
Addressing using @RW0, @RW1, @RW4, and @RW5, @A, addr16, dir
Stack space
Addressing using PUSHW, POPW, @RW3, and @RW7
Additional space
Addressing using @RW2 and @RW6
CHAPTER 3 CPU
3.5
Memory Location of Multi-byte Data
Multi-byte data is written to memory sequentially from the lower address. If multi-byte
data is 32-bit data, the lower 16 bits are transferred followed by the upper 16 bits.
If a reset signal is input immediately after the low-order data is written, the high-order
data may not be written.
■ Storage of Multi-byte Data in RAM
Figure 3.5-1 shows the data configuration of multi-byte data in memory. The lower 8 bits of the data is
located at address n, and subsequent data is located at address n + 1, address n + 2, address n + 3 and so on,
in this sequence.
Figure 3.5-1 Storage of Multi-byte Data in RAM
MSB
01010101B
H
LSB
11001100B
11111111B
00010100B
01010101B
11001100B
11111111B
Address ‘n’
00010100B
L
■ Storage of Multi-byte Operand
Figure 3.5-2 shows the configuration of a multi-byte operand in memory.
Figure 3.5-2 Storage of a Multi-byte Operand
JMPP 123456H
H
JMPP 12 34 56H
12H
34H
Address ‘n’
56H
63H
L
37
CHAPTER 3 CPU
■ Storage of Multi-byte Data in a Stack
Figure 3.5-3 shows the configuration of multi-byte data in a stack.
Figure 3.5-3 Storage of Multi-byte Data in a Stack
PUSH RW1,RW3
H
PUSHW RW1, RW3
(35A4H) (6DF0H)
SP
6DH
F0H
Address ‘n’
35H
A4H
L
RW1: 35A4H
RW3: 6DF0H
*: Stack status after execution of the PUSHW instruction
■ Multi-byte Data Access
Accessing is generally performed within a bank. For an instruction that accesses multi-byte data, the
address following "FFFFH" is "0000H" in the same bank. Figure 3.5-4 shows an example of executing an
instruction that accesses multi-byte data on a bank boundary.
Figure 3.5-4 Multi-byte Data Access on a Bank Boundary
H
01H
……..
80FFFFH
800000H
L
38
23H
AL before execution
??
??
AL after execution
23H
01H
CHAPTER 3 CPU
3.6
Registers
F2MC-16LX registers are classified into internal dedicated CPU registers and built-in
RAM general-purpose registers.
■ Dedicated Registers and General-purpose Registers
Dedicated registers are dedicated hardware inside the CPU with limited use in the CPU architecture.
General-purpose registers exist together with RAM in the CPU address space. Just like dedicated registers,
general-purpose registers can be accessed without addressing. Just like ordinary memory, the user can
specify how the register is used. Figure 3.6-1 shows the location of the dedicated registers and generalpurpose registers in the device.
Figure 3.6-1 Dedicated Registers and General-purpose Registers
Dedicated register
General-purpose
register
Accumulator
User stack pointer
Processor status
Program counter
Direct page register
Internal bus
System stack pointer
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
39
CHAPTER 3 CPU
3.7
Dedicated Registers
The following 11 registers are dedicated registers in the CPU.
• Accumulator (A)
• System stack pointer (SSP)
• Program counter (PC)
• Program bank register (PCB)
• User stack pointer (USP)
• User stack bank register (USB)
• Additional data bank register (ADB)
• Processor status (PS)
• Direct page register (DPR)
• Data bank register (DPP)
• System stack bank register (SSB)
■ Configuration of Dedicated Registers
Figure 3.7-1 shows the configuration of dedicated registers; Table 3.7-1 lists the initial values of the
dedicated registers.
Figure 3.7-1 Configuration of Dedicated Registers
AH
AL
Accumulator (A)
USP
User Stack Pointer (USP)
SSP
System Stack Pointer (SSP)
PS
Processor Status (PS)
PC
Program Counter (PC)
DPR
Direct Page Register (DPR)
PCB
Program Bank Register (PBR)
DPB
Data Bank Register (DBR)
USB
User Stack Bank Register (USB)
SSB
System Stack Bank Register (SSB)
ADB
Additional Data Bank Register (ADB)
8 bits
16 bits
32 bits
40
CHAPTER 3 CPU
Table 3.7-1 Initial Values of the Dedicated Registers
Dedicated register
Initial value
Accumulator (A)
Undefined
User stack pointer (USP)
Undefined
System stack pointer (SSP)
Undefined
Processor status (PS)
bit 15
PS
Default value ⇒
13 12
87
0
ILM
RP
CCR
000
00000
-01xxxxx
Program counter (PC)
Value in reset vector (contents of FFFFDCH, FFFFDDH)
Direct page register (DPR)
01H
Program bank register (PCB)
Value in reset vector (contents of FFFFDEH)
Data bank register (DTB)
00H
User stack bank register (USB)
00H
System stack bank register (SSB)
00H
Additional data bank register
(ADB)
00H
-: Not used
x: Undefined
Note:
The above initial values are the initial values for the device.
(emulator, etc.) values.
They are different from the ICE
41
CHAPTER 3 CPU
3.7.1
Accumulator (A)
The accumulator (A) consists of two 16-bit arithmetic operation registers (AH and AL).
The accumulator is used to temporarily store the results of an arithmetic operation and
data.
The A register can be used as a 32-bit, 16-bit or 8-bit register. Various arithmetic
operations can be performed between memory and other registers or between the AH
register and the AL register. The A register has a data retention function that
automatically transfers pre-transfer data from the AL register to the AH register when
data of word length or less is transferred to the AL register. (Data is not retained with
some instructions.)
■ Accumulator (A)
● Data transfer to the accumulator
The accumulator can process 32-bit (long word), 16-bit (word) and 8-bit (byte) data. The 4-bit data transfer
instruction (MOVN) is an exception. The explanation of 8-bit data also applies to 4-bit data.
• For 32-bit data processing, the AH register and AL register are combined.
• For 16-bit data and 8-bit data, only the AL register is used.
• When data of byte length or less is transferred to the AL register, data becomes 16 bits long by sign
extension or zero extension, and is stored in the AL register. Data in the AL register can be handled as
word-length or byte-length data.
Figure 3.7-2 shows data transfer to the accumulator. Figure 3.7-3 to Figure 3.7-6 show specific transfer
examples.
Figure 3.7-2 Data Transfer to the Accumulator
32-bit
32-bit data transfer
Data transfer Data transfer
16-bit data transfer
Data save
Data transfer
8-bit data transfer
Data save
00H or FFH *
Data transfer
(Zero extension or sign extension)
* Becomes 000H or FFFH for a 4-bit transfer instruction.
42
CHAPTER 3 CPU
Figure 3.7-3 Example of AL-AH Transfer in the Accumulator (A) (8-bit Immediate Value, Zero Extension)
MOV A,3000H
(An instruction that zero-extends the contents at address 3000H and
stores the result in the AL register)
MSB
A before execution
XXXXH
2456H
DTB
A after execution
2456H
AH
B53000H
Memory space
77H
LSB
88H
B5H
0088H
AL
Figure 3.7-4 Example of AL-AH Transfer in the Accumulator (A) (8-bit Immediate Value, Sign Extension)
MOVX A,3000H
(An instruction that stores the contents at address 3000H
in the AL register)
MSB
A before execution
XXXXH
2456H
DTB
A after execution
2456H
AH
B53000H
Memory space
77H
LSB
88H
B5H
7788H
AL
Figure 3.7-5 Example of 32-bit Data Transfer to the Accumulator (A) (Register Indirect)
MOVL A,@RW1+6
(Instruction that perform a long-word-length read using the result
of the RW1 contents + an 8-bit offset as the address and stores
the read value in the A register)
Memory space
MSB
A before execution
XXXXH
XXXXH
DTB
A after execution
8F74H
AH
A6H
2B52H
AL
LSB
A61540H
8FH
74H
A6153EH
2BH
52H
RW1
15H
38H
+6
43
CHAPTER 3 CPU
Figure 3.7-6 Example of AL-AH Transfer in the Accumulator (A) (16 Bits, Register Indirect)
MOVW A,@RW1+6
(Instruction that performs a word-length read using the result of
the RW1 contents + an 8-bit offset as the address and stores the
read value in the A register)
Memory space
MSB
A before execution
XXXXH
1234H
DTB
A after execution
1234H
AH
A6H
2B52H
AL
LSB
A61540H
8FH
74H
A6153EH
2BH
52H
RW1
15H
38H
+6
● Accumulator byte-processing arithmetic operation
When a byte-processing arithmetic operation instruction is executed for the AL register, the upper 8 bits of
the AL register before the arithmetic operation is executed are ignored. The upper 8 bits of the arithmetic
operation results are all zeros.
● Initial value of the accumulator
The initial value after a reset is undefined.
44
CHAPTER 3 CPU
3.7.2
Stack Pointers (USP, SSP)
There are two types of stack pointers: a user stack pointer (USP) and a system stack
pointer (SSP). Each stack pointer is a register that indicates the memory address of the
location of the destination for saved data or a return address when PUSH instructions,
POP instructions and subroutines are executed. The upper 8 bits of the stack address
are specified by the user stack bank register (USB) or system stack bank register (SSB).
When the S flag of the condition code register (CCR) is "0", the USP and USB registers
are valid. When the S flag is "1", the SSP and SSB registers are valid.
■ Stack Selection
The F2MC-16LX uses two types of stack: a system stack and a user stack.
The stack address is determined, as shown in Table 3.7-2, by the S flag in the processor status (PS: CCR).
Table 3.7-2 Stack Address Specification
Stack address
S flag
Upper 8 bits
Lower 16 bits
0
User stack bank register (USB)
User stack pointer (USP)
1
System stack bank register (SSB)
System stack pointer (SSP)
: Initial value
Because the S flag is initialized to "1" by a reset, the system stack is used as the default.
Ordinarily, the system stack is used for interrupt routine stack operations, and the user stack is used for all
other types of stack operation. When separation of the stack space is not particularly necessary, only the
system stack should be used.
Note:
Since the S flag is set to "1" when an interrupt is accepted, the system stack is always used for
interrupts.
Figure 3.7-7 shows an example of stack operation with the system stack.
45
CHAPTER 3 CPU
Figure 3.7-7 Stack Operation Instruction and Dtack Pointer
PUSHW A with the S flag set to "0"
Before execution ⇒
AL
A624H
S flag
After execution ⇒
AL
0
A624H
S flag
0
MSB
USB C6H
USP
F328H
SSB 56H
SSP
1234H
USB C6H
USP
F326H
SSB 56H
SSP
1234H
C6F326H
LSB
XXH
XXH
⇐ User stack is used
because S flag is "0"
C6F326H
A6H
24H
PUSHW A with the S flag set to "1"
MSB
Before execution ⇒
AL
A624H
S flag
After execution ⇒
AL
1
A624H
S flag
1
USB C6H
USP
F328H
SSB 56H
SSP
1234H
USB C6H
USP
F328H
SSB 56H
SSP
1232H
LSB
561232H
XXH
XXH
561232H
A6H
24H
⇐
System stack is used
because S flag is "1"
Notes:
• To set a value for the stack pointer, generally use an even-numbered address.
numbered address is used, a word access is split into two parts, lowering efficiency.
If an odd-
• The initial values of the USP register and SSP register after a reset are undefined.
■ System Stack Pointer (SSP)
To use the system stack pointer (SSP), set the S flag in the condition code register (CCR) of the processor
status (PS) to "1". The upper 8 bits of the address that will be used for the stack operation are indicated by
the system stack bank register (SSB).
■ User Stack Pointer (USP)
To use the user stack pointer (USP), set the S flag in the condition code register (CCR) of the processor
status (PS) to "0". The upper 8 bits of the address that will be used for the stack operation are indicated by
the user stack bank register (USB).
46
CHAPTER 3 CPU
3.7.3
Processor Status (PS)
The processor status (PS) consists of CPU control bits and bits that indicate the CPU
status. The PS register consists of the following three registers:
• Interrupt level mask register (ILM)
• Register bank pointer (RP)
• Condition code register (CCR)
■ Processor Status (PS) Configuration
The processor status (PS) consists of CPU control bits and bits that indicate the CPU status. Figure 3.7-8
shows the configuration of the processor status (PS)
Figure 3.7-8 Processor Status (PS) Configuration
bit 15
13 12
PS
Default value ⇒
87
0
ILM
RP
CCR
000
00000
-01xxxxx
bit 7
6
5
4
3
2
1
0
–
I
S
T
N
Z
V
C
– 0 1 x
Default value ⇒
bit 12 11 10 9
x
8
x
x
x
B4 B3 B2 B1 B0
Default value ⇒
bit
Default value ⇒
0 0
15
0 0
14
0
13
ILM2
ILM1
ILM0
0
0
0
: CCR
: RP
: ILM
- : Not used
x : Undefined
● Interrupt level mask register (ILM)
This register indicates the level of the interrupt currently accepted by the CPU. The value is compared with
the value of the interrupt level setting bits (ICR: IL0 to IL2) in the interrupt control register set for the
peripheral resource interrupt request.
● Register bank pointer (RP)
This pointer points to the first address of the memory block (register bank) used as the general-purpose
register in the RAM area.
There are 32 banks for general-purpose registers. Values 0 to 31 are set in the RP to specify a bank.
● Condition code register (CCR)
This register consists of flags that are set to "1" or reset to "0" by instruction execution results and by
interrupts.
47
CHAPTER 3 CPU
3.7.4
Condition Code Register (PS: CCR)
The condition code register (CCR) is an 8-bit register that consists of the bits that
indicate the results of an arithmetic operation and the contents of transfer data and bits
that control interrupt request acceptance.
■ Condition Code Register (CCR) Configuration
Figure 3.7-9 shows the configuration of the CCR register. Refer to the programming manual for details
about the status of the condition code register (CCR) during instruction execution.
Figure 3.7-9 Condition Code Register (CCR) Configuration
bit
Default value ⇒
Interrupt enable flag
Stack flag
Sticky flag
Negative flag
Zero flag
Overflow flag
Carry flag
7
6
5
4
3
2
1
0
–
I
S
T
N
Z
V
C
–
0
1
x
x
x
x
x
: CCR
- : Not used
x : Undefined
● Interrupt enable flag (I)
In response to all interrupt requests other than software interrupts, when the I flag is "1", interrupts are
enabled. When the I flag is "0", interrupts are disabled. Cleared by a reset.
● Stack flag (S)
This flag indicates the pointer used for a stack operation.
When the S flag is "0", the user stack pointer (USP) is valid. When the S flag is "1", the system stack
pointer (SSP) is valid. Set when an interrupt is accepted or when a reset occurs.
● Sticky bit flag (T)
Set to "1" when the data shifted out by the carry contains at least one 1 during execution of a logical right
shift instruction or arithmetic right shift instruction. Otherwise, set to "0". Also set to "0" when the shift
amount is zero.
● Negative flag (N)
Set to "1" when the MSB is ""1 as the result of an arithmetic calculation. Cleared to "0 "when the MSB is
"0".
● Zero flag (Z)
Set to "1" when the result of an arithmetic calculation is all zeros. Otherwise, set to "0".
48
CHAPTER 3 CPU
● Overflow flag (V)
Set to "1" if a signed numeric value overflows because of an arithmetic calculation. Cleared to "0" if no
overflow occurs.
● Carry flag (C)
Set to "1" when there is an overflow from the MSB or an underflow from the LSB because of an arithmetic
calculation. Cleared to "0" when there is no overflow or underflow because of an arithmetic calculation.
49
CHAPTER 3 CPU
3.7.5
Register Bank Pointer (PS: RP)
The register bank pointer (RP) is a register that indicates the first address of the
general-purpose register bank currently being used. The RP is used for real address
conversion when general-purpose register addressing is used.
■ Register Bank Pointer (RP)
Figure 3.7-10 shows the configuration of the register bank pointer (RP) register.
Figure 3.7-10 Configuration of the Register Bank Pointer (RP)
bit 12 11 10 9
8
B4 B3 B2 B1 B0
Default value ⇒
0
0
0
0
: RP
0
■ General-purpose Register Area and Register Bank Pointer
The register bank pointer points to the relationship between the general-purpose register of the F2MC16LX and the address in internal RAM where the general-purpose register exists. Figure 3.7-11 shows the
conversion rules used for the relationship between the contents of the RP and the real address.
Figure 3.7-11 Conversion Rules for Physical Address of General-purpose Register Area
Conversion formula [000180H + (RP) × 10H]
When RP = 10H
000370H
000280H
000180H
Register bank 31
Register bank 16
Register bank 0
• Since the RP takes a value from 00H to 1FH, the first address of the register bank can be set in the range
from 000180H to 00037FH.
• Although an assembler instruction can use an 8-bit immediate value transfer instruction for transfer to
the RP, in actuality only the lower 5 bits of the data are used.
• The initial value of the RP register after a reset is 00H.
50
CHAPTER 3 CPU
3.7.6
Interrupt Level Mask Register (PS: ILM)
The interrupt level mask register (ILM) is a 3-bit register that indicates the level of the
interrupt currently accepted by the CPU.CHAPTER 7 INTERRUPT
■ Interrupt Level Mask Register (ILM)
Figure 3.7-12 shows the configuration of the interrupt level mask register (ILM). See "CHAPTER 7
INTERRUPT", for details about interrupts.
Figure 3.7-12 Configuration of the Interrupt Level Mask Register (ILM)
bit
15
14
13
ILM2
ILM1
ILM0
0
0
0
Default value ⇒
: ILM
The interrupt level mask register (ILM) indicates the level of the interrupt currently accepted by the CPU.
The level is compared with the value of the IL0 to IL2 bits of the interrupt control register (ICR00 to
ICR15) set according to the interrupt request from the peripheral function. If the interrupt enable flag has
been set to enable (CCR: I = 1), the CPU processes the instruction only when the value (interrupt level) of
the interrupt request is smaller than the value indicated by these bits.
• When an interrupt is accepted, the interrupt level value is set in the interrupt level mask register (ILM).
Thereafter, interrupts with the same or lower level are not accepted.
• The interrupt level is set to the highest level, which is the interrupts disabled status, because the interrupt
level mask register (ILM) is initialized to all 0's by a reset.
• Although an assembler instruction can use an 8-bit immediate value transfer instruction for transfer to
the interrupt level mask register (ILM), only the lower 3 bits of the data are used.
• Interrupt level mask register (ILM) and interrupt level priority
Table 3.7-3 Interrupt Level Mask Register (ILM) and Interrupt Level Priority
ILM2
ILM1
ILM0
Interrupt level
Interrupt level priority
0
0
0
0
Highest (interrupts disabled)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Lowest
51
CHAPTER 3 CPU
3.7.7
Program Counter (PC)
The program counter (PC) is a 16-bit counter that indicates the lower 16 bits of the
memory address of the next instruction code to be executed by the CPU.
■ Program Counter (PC)
The program bank register (PCB) specifies the upper 8 bits of the address where the next instruction code
to be executed by the CPU is stored. The PC specifies the lower 16 bits. Before being used, the actual
address is combined to become 24 bits, as shown in Figure 3.7-13.
The contents of the PC are updated by conditional branch instructions, subroutine call instructions,
interrupts and resets.
The PC can be used as a bus pointer for reading operands.
Figure 3.7-13 Program Counter (PC)
Upper 8 bits
Upper 16 bits
PCB
PC ABCDH
FEH
FEABCDH
Next instruction
to be executed
Note:
The PC and PCB cannot be rewritten directly by a program (such as by MOV PC and #FF).
52
CHAPTER 3 CPU
3.7.8
Direct Page Register (DPR)
The direct page register (DPR) is an 8-bit register that specifies bits 8 to 15 (addr8 to
addr15) of the operand address when a short direct addressing instruction is executed.
■ Direct Page Register (DPR)
As shown in Figure 3.7-14, the DPR specifies bits 8 to 15 (addr8 to addr15) of the operand address when a
short direct addressing instruction is executed. The DPR is 8-bits long. The DPR is initialized to 01H by a
reset. The DPR can be read and written using an instruction.
Figure 3.7-14 Physical Address Generation by the Direct Page Register (DPR)
DTB register
DDR register
αααααααα
Direct address in instruction
γγγγγγγγ
ββββββββ
MSB
24-bit physical address
LSB
ααααααααββββββββγγγγγγγγ
Figure 3.7-15 shows an example of direct page register (DPR) setting and data access.
Figure 3.7-15 Example of Direct Page Register (DPR) Setting and Data Access
Instruction execution results
Memory space
MOV S:56H, #5AH
Upper
8 bits
DTB register
12H
123458H
123456H
DPR register
34H
Lower
8 bits
5AH
123454H
MSB
LSB
53
CHAPTER 3 CPU
3.7.9
Bank Registers (PCB, DTB, USB, SSB, ADB)
Bank registers specify the highest 8-bit address by bank addressing. The five bank
registers are as follows:
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
The PCB, DTB, USB, SSB and ADB registers indicate the individual memory banks
where the program space, data space, user stack space, system stack space and
additional space are located.
■ Bank Registers (PCB, DTB, USB, SSB, ADB)
● Program bank register (PCB)
The PCB is a bank register that specifies the program (PC) space.
The PCB is rewritten when a software interrupt instruction is executed, when the JMPP, CALLP, RETP
and RETI instructions that branch anywhere within the 16-megabyte space are executed, or when a
hardware interrupt or exception occurs.
● Data bank register (DTB)
The DTB is a bank register that specifies the data (DT) space.
● User stack bank register (USB), system stack bank register (SSB)
The USB and SSB are bank registers that specify the stack (SP) space. Whether the USB or the SSB is
used depends on the S flag value in the processor status (PS: CCR). See "3.7.2 Stack Pointers (USP, SSP)",
for details.
● Additional bank register (ADB)
The ADB is a bank register that specifies the additional (AD) space.
● Bank setting and data access
All bank registers are byte length. The PCB is initialized to FFH by a reset. The other bank registers are
initialized to 00H by a reset. The PCB can be read, but cannot be written to.
The other bank registers can be read and written to.
Note:
The MB90460/465 series supports up to the memory space contained in the device.
See "3.4.2 Address Specification by Bank Addressing", for the operation of each register.
54
CHAPTER 3 CPU
3.8
General-purpose Registers
The general-purpose registers are a memory block allocated in RAM at 000180H to
00037FH as banks, each of which consists of eight 16-bit segments.
The general-purpose registers can be used as general-purpose 8-bit registers (byte
registers R0 to R7), 16-bit registers (word registers RW0 to RW7) or 32-bit registers
(long-word registers RL0 to RL7).
General-purpose registers can access RAM with a short instruction at high speed.
Since general-purpose registers are blocked into register banks, protection of register
contents and division into function units can readily be performed. When a generalpurpose register is used as a long-word register, it can be used as a linear pointer that
directly accesses the entire space.
■ Configuration of a General-purpose Register
All general-purpose registers exist in RAM at 000180H to 00037FH and are configured as 32 banks. The
register bank pointer (RP) specifies the bank that is to be used for a general-purpose register. The RP
points to the bank currently being used.
The RP determines the first address of each bank with the following formula:
Address of first general-purpose register = 000180H + RP x 10H Figure 3.8-1 shows the location and
configuration of the general-purpose register banks in the memory space.
Figure 3.8-1 Location and Configuration of the General-purpose Register Banks in the Memory Space
Built-in RAM
Register bank 31
Byte address
Byte address
Register bank 30
Register bank 21
Register bank 20
Register bank 19
Register bank 2
Register bank 1
Register bank 0
Conversion formula [000180 H + RP x 10H]
R0 to R7:
RW0 to RW7:
RL0 to RL3:
MSB:
LSB:
Byte registers
Word registers
Long-word registers
Most Significant Bit
Least Significant Bit
Note:
The register bank pointer (RP) is initialized to 00H after a reset.
55
CHAPTER 3 CPU
■ Register Bank
A register bank can be used as general-purpose registers (byte registers R0 to R7, word registers RW0 to
RW7, long-word registers RL0 to RL3) for various arithmetic operations and pointers. A long-word
register can be used as a linear pointer that directly accesses the entire memory space.
The contents of the register bank, like ordinary RAM, are not initialized by a reset. The status before a
reset is retained. At power-on, however, the contents are undefined. Table 3.8-1lists the typical functions
of general-purpose registers.
Table 3.8-1 Typical Functions of General-purpose Registers
Register name
56
Function
R0 to R7
Used as an operand in various instructions
(Note)
R0 is also used as a barrel shift counter and an instruction normalization counter
RW0 to RW7
Used as a pointer
Used as an operand in various instructions
(Note)
RW0 is used also as a string instruction counter
RL0 to RL3
Used as a long pointer
Used as an operand in various instructions
CHAPTER 3 CPU
3.9
Prefix Codes
Prefix codes are placed before an instruction to partially change the operation of the
instruction. The three types of prefix codes are as follows:
• Bank select prefix (PCB, DTB, ADB, SPB)
• Common register bank prefix (CMR)
• Flag change suppression prefix (NCC)
■ Prefix Codes
● Bank select prefix (PCB, DTB, ADB, SPB)
A bank select prefix is placed before an instruction to select the memory space to be accessed by the
instruction regardless of the addressing method.
● Common register bank prefix (CMR)
The common register bank prefix is placed before an instruction that accesses a register bank to change the
register accessed by the instruction to the common bank (register bank selected when RP = 0) at 000180H
to 00018FH regardless of the current register bank pointer (RP) value.
● Flag change suppression prefix (NCC)
The flag change suppression prefix code is placed before an instruction to suppress a flag change
accompanying the execution of the instruction.
57
CHAPTER 3 CPU
3.9.1
Bank Select Prefix (PCB, DTB, ADB, SPB)
A bank select prefix is placed before an instruction to select the memory space
accessed by the instruction regardless of the addressing method.
■ Bank Select Prefixes (PCB, DTB, ADB, SPB)
The memory space used for data access is defined for each addressing method. If a bank select prefix is
placed before an instruction, the memory space accessed by the instruction can be selected regardless of the
addressing method. Table 3.9-1 lists the bank select prefix codes and selected memory spaces.
Table 3.9-1 Bank Select Prefix Codes and selected Memory Spaces
Bank select prefix
Selected space
PCB
Program space
DTB
Data space
ADB
Additional space
SPB
When the value of the S flag in the condition code register (CCR) is "0" and the
user stack space is "1", the system stack space is used.
If a bank select prefix is used, some instructions perform an unexpected operation.
Table 3.9-2 lists the instructions that are not affected by bank select prefix codes. Table 3.9-3 lists
instructions that require caution when they are used.
Table 3.9-2 Instructions not affected by Bank Select Prefix Codes
Instruction type
String instruction
Instruction
MOVS
SCEQ
FIL
MOVSW
SCWEQ
SFILSW
The bank register specified by the
operand is used whether or not a prefix is
used.
When the S flag is "0", the user stack bank
(USB) is used whether or not there is a
prefix. When the S flag is "1", the system
stack bank (SSB) is used regardless of
whether a prefix is used.
Stack
operation
PUSHW
POPW
I/O access instruction
MOV
MOVW
MOV
MOV
MOVB
SETB
BBC
WBTC
A
A, io
io, A
io, #imm8
A, io : bp
io : bp
io : bp, rel
io, bp
Interrupt return
instruction
RETI
58
Effect of bank select prefix
MOVX
A, io
MOVW io, A
MOVW io,#imm16
MOVB io : bp, A
CLRB
io : bp
BBS
io : bp, rel
WBTS
io : bp
The I/O space (000000H to 0000FFH) is
accessed whether or not there is a
prefix.
The system stack bank (SSB) is used
whether or not a prefix is used.
CHAPTER 3 CPU
Table 3.9-3 Instructions whose use requires Caution when Bank Select Prefix Codes are used
Instruction type
Instruction
Explanation
Flag change instruction
AND
OR
CCR, #imm8
CCR, #imm8
The effect of the prefix extends to the next
instruction.
ILM setting instruction
MOV
ILM, #imm8
The effect of the prefix extends to the next
instruction.
PS return instruction
POPW
PS
Do not place a bank select prefix before the PS
return instruction.
59
CHAPTER 3 CPU
3.9.2
Common Register Bank Prefix (CMR)
The common register bank (CMR) prefix is placed before an instruction that accesses a
register bank to change the register accessed by the instruction to the common bank
(register bank selected when RP = 0) at 000180H to 00018FH regardless of the current
register bank pointer (RP) value.
■ Common register bank prefix (CMR)
To facilitate data exchange between multiple tasks, a relatively simple means of accessing a fixed register
bank regardless of the current register bank pointer (RP) value is necessary. This is the reason that the
F2MC-16LX provides a common register bank for tasks, which is called the common bank. The common
bank is located at address 000180H to 00018FH.
If the common register bank prefix (CMR) is placed before an instruction that accesses a register bank,
registers accessed by the instruction can be changed to the common bank (register bank selected when RP =
0) at 000180H to 00018FH regardless of the current register bank pointer (RP) value.
Note that caution is required when this prefix is used with the instructions listed in Table 3.9-4.
Table 3.9-4 Instructions whose use requires Caution when the Common Register Bank Prefix (CMR) is
used
Instruction type
Instruction
Explanation
String
instruction
MOVS
SCEQ
FILS
Flag change instruction
AND
PS return instruction
POPW PS
The effect of the prefix extends to the
next instruction.
ILM setting instruction
MOV
The effect of the prefix extends to the
next instruction.
60
CCR, #imm8
ILM, #imm8
MOVSW
SCWEQ
FILSW
Do not place the CMR prefix before the
string instruction.
OR CCR, #imm8
The effect of the prefix extends to the
next instruction.
CHAPTER 3 CPU
3.9.3
Flag Change Suppression Prefix (NCC)
The flag change suppression prefix (NCC) code is placed before an instruction to
suppress a flag change accompanying the execution of the instruction.
■ Flag Change Suppression Prefix (NCC)
The flag change suppression prefix (NCC) is used to suppress unnecessary flag changes. If a flag change
suppression prefix code is placed before an instruction, a flag change accompanying the execution of the
instruction is suppressed. Changes of the T, N, Z, V and C flags are suppressed.
Note that caution is required when this prefix is used with the instructions listed in Table 3.9-5.
Table 3.9-5 Instructions whose use requires Caution when the Flag Change Suppression Prefix (NCC) is
used
Instruction type
Instruction
Explanation
String
instruction
MOVS
SCEQ
FILS
Flag change
instruction
The condition code register (CCR) changes as defined in
AND CCR, #imm8 OR CCR, #imm8 the instruction specification whether or not a prefix is used.
The effect of prefix extends to the next instruction.
PS return
instruction
POPW
ILM setting
instruction
MOV
Interrupt instruction INT
Interrupt return
INT
RETI
instruction
Context switch
instruction
MOVSW
SCWEQ
FILSW
The condition code register (CCR) changes as defined in
the instruction specification whether or not a prefix is used.
The effect of prefix extends to the next instruction.
PS
ILM, #imm8
#vct8
adder16
JCTX@A
Do not place the NCC prefix before the string instruction.
INT9
INTP
The effect of prefix extends to the next instruction.
addr24
The condition code register (CCR) changes as defined in
the instruction specification whether or not a prefix is used.
The condition code register (CCR) changes as defined in
the instruction specification whether or not a prefix is used.
61
CHAPTER 3 CPU
3.9.4
Restrictions on Prefix Codes
The following three restrictions are imposed on the use of prefix codes:
• Interrupt/hold requests are not accepted during the execution of prefix codes and
interrupt/hold suppression instructions.
• If a prefix code is placed before an interrupt/hold instruction, the effect of the prefix
code is delayed.
• If consecutively placed prefix codes conflict, the last prefix code is valid.
■ Prefix Codes and Interrupt/hold Suppression Instructions
Table 3.9-6 lists the interrupt/hold suppression instructions and prefix codes that have restrictions.
Table 3.9-6 Prefix Codes and Interrupt/hold Suppression Instructions
Prefix codes
Instructions that do not
accept interrupt and
hold requests
Interrupt/hold suppression instructions
(instructions that delay the effect of prefix codes)
PCB
DTB
ADB
SPB
CMR
NCC
MOV
OR
AND
POPW
ILM, #imm8
CCR, #imm8
CCR, #imm8
PS
● Interrupt/hold suppression
As shown in Figure 3.9-1, an interrupt or hold request generated during the execution of prefix codes and
interrupt/hold instructions is not accepted. The interrupt/hold is not processed until the first instruction that
is not governed by a prefix code or that is not an interrupt/hold suppression instruction is executed.
Figure 3.9-1 Interrupt/hold Suppression
Interrupt/hold suppression instruction
⎨
…………
↑
Interrupt request generated
62
(a) Ordinary instruction
……
(a)
↑
Interrupt accepted
CHAPTER 3 CPU
● Delay of the effect of prefix codes
As shown in Figure 3.9-2, if a prefix code is placed before an interrupt/hold suppression instruction, the
prefix code takes effect with the first instruction executed after the interrupt/hold suppression instruction.
Figure 3.9-2 Interrupt/hold Suppression Instructions and Prefix Codes
Interrupt suppression instructions
⎨
MOV A, FFH
NCC
…
MOV ILM, #imm8
CCR: XXX10XXB
ADD A, 01H
CCR: XXX10XXB
CCR is not changed due to NCC prefix
■ Consecutive Prefix Codes
As shown in Figure 3.9-3, when consecutive conflicting prefix codes (PCB, ADB, DTB and SPB) are
specified, the last prefix code is valid.
Figure 3.9-3 Consecutive Prefix Codes
⎨
Prefix codes
……
ADB
DTB
PCB
ADD A, 01H
……
↑ The PCB prefix code is valid
63
CHAPTER 3 CPU
64
CHAPTER 4
RESET
This chapter describes the reset for the MB90460/465
series microcontrollers.
4.1 Reset
4.2 Reset Causes and Oscillation Stabilization Wait Intervals
4.3 External Reset Pin
4.4 Reset Operation
4.5 Reset Cause Bits
4.6 Status of Pins in a Reset
65
CHAPTER 4 RESET
4.1
Reset
If a reset cause is generated, the CPU immediately stops the current execution process
and waits for the reset to be cleared. When the reset is cleared, the CPU begins
processing at the address indicated by the reset vector.
There are four causes of a reset:
Power-on reset
Watchdog timer overflow
External reset request via the RSTX pin
Software reset request
■ Reset Causes
Table 4.1-1 lists the reset causes.
Table 4.1-1 Reset Causes
Type of reset
Cause
Machine clock
Watchdog
timer
Oscillation
stabilization
wait
External pin
Low level input to RSTX pin
Previous state
retained
Previous state
retained
No
Software
A “0” is written to the RST bit
of the low power consumption
mode control register
(LPMCR)
Previous state
retained
Previous state
retained
No
Watchdog
timer
Watchdog timer overflow
MCLK
Stop
Yes
Power-on
When the power is turned on
MCLK
Stop
Yes
MCLK: Main clock (oscillation clock frequency divided by 2)
● External reset
An external reset is generated by the L level input to an external reset pin (RSTX pin). The minimum
required period of the L level input to the RSTX pin is 16 machine cycles (16/φ). The oscillation
stabilization wait interval is not required for external resets.
Reference:
66
For external reset requests via the RSTX pin, if the reset cause is generated during a write operation
(during the execution of a transfer instruction such as MOV), the CPU waits for the reset to be
cleared after the instruction is completed. The normal write operation is therefore completed even
though a reset is input concurrently.
Note, however, that waiting for the reset to be cleared may start before the transfer of the contents of
a counter specified by a string-processing instruction (such as MOVS) is completed.
CHAPTER 4 RESET
● Software reset
A software reset is an internal reset of three machine cycles (3/φ) generated by writing "0" to the RST bit of
the low power consumption mode control register (LPMCR). The oscillation stabilization wait interval is
not required for software resets.
● Watchdog timer reset
A watchdog timer reset is generated by a watchdog timer overflow that occurs when a "0" is not written to
the WTE bit of the watchdog timer control register (WDTC) within a given time after the watchdog timer is
activated. The oscillation stabilization wait interval can be set by the clock selection register (CKSCR).
● Power-on reset
A power-on reset is generated when the power is turned on. The oscillation stabilization wait interval is
fixed at 218 oscillation clock cycles (218/HCLK). After the oscillation stabilization wait interval has
elapsed, the reset is executed.
See also
• Definition of clocks
HCLK:
Oscillation clock frequency
MCLK:
Main clock frequency
φ:
Machine clock (CPU operating clock) frequency
1/φ:
Machine cycle (CPU operating clock cycle)
See "5.1 Clock", for details.
67
CHAPTER 4 RESET
4.2
Reset Causes and Oscillation Stabilization Wait Intervals
The F2MC-16LX has four reset causes. The oscillation stabilization wait interval for a
reset depends on the reset cause.
■ Reset Causes and Oscillation Stabilization Wait Intervals
Table 4.2-1 and Figure 4.2-1 summarize reset causes and oscillation stabilization wait intervals.
Table 4.2-1 Reset Causes and Oscillation Stabilization Wait Intervals
Reset cause
Oscillation stabilization wait interval
The corresponding time interval for an oscillation clock
frequency of 4 MHz is given in parentheses.
Power-on reset
218/HCLK (approximately 65.54 ms)
Watchdog timer
217/HCLK (approximately 32.77 ms)
External reset via the RSTX pin
None. However the WS1 & WS0 bits are initialized to “11”.
Software reset
None. However the WS1 & WS0 bits are initialized to “11”.
HCLK: Oscillation clock frequency, source oscillation.
Figure 4.2-1 shows the oscillation stabilization wait interval of the product at power-on reset.
Figure 4.2-1 Oscillation Stabilization Wait Interval at Power-on Reset
Vcc
2 17 /HCLK
2 17 /HCLK
CLK
CPU operation
Regulator stabilization
wait interval
Oscillation stabilization
wait interval
HCLK: oscillation clock
Note:
Ceramic and crystal oscillators generally require an oscillation stabilization wait interval of a few to
several dozen milliseconds until they stabilize at their natural frequency. Be sure to set a proper
oscillation stabilization wait interval for the specific oscillator used.
See "4.2 Reset Causes and Oscillation Stabilization Wait Intervals" for detail about Oscillation
Stabilization Wait Interval.
■ Oscillation Stabilization Wait and Reset State
A reset operation in response to a power-on reset and other externally activated resets during
stop mode and hardware standby mode is performed after the oscillation stabilization wait interval
has elapsed. This time interval is generated by the time-base timer. If the external reset has not
been cleared after the interval, the reset operation is performed after the external reset is cleared.
68
CHAPTER 4 RESET
4.3
External Reset Pin
The external reset pin (RSTX pin) is a dedicated pin for inputting, with an L level signal,
a reset and generating an internal reset by the L level input.
For MB90460/465 series microcontrollers, resets are generated in synchronization with
the CPU operating clock. Asynchronous resets are generated only for the external
terminals.
■ Block Diagrams of the External Reset Pin
● Block diagram of internal reset
Figure 4.3-1 Block Diagram of Internal Reset
RSTX
P-ch
Pin
N-ch
CPU operating clock
(PLL multiplier circuit with a frequency of HCLK divided by 2)
Synchronization
circuit
Internal reset signal
Input buffer
HCLK: Oscillation clock
Note:
Inputs to the RSTX pin are accepted during cycles in which memory is not affected to prevent
memory from being destroyed by a reset during a write operation.
A clock is required to initialize the internal circuit. In particular, an operation with an external clock
requires clock input together with reset input.
69
CHAPTER 4 RESET
● Block diagram of internal reset for external pin
Figure 4.3-2 Block Diagram of Internal Reset for External Pin
RSTX
P-ch
Pin
N-ch
Internal reset signal
HCLK: Oscillation clock
70
Input buffer
CHAPTER 4 RESET
4.4
Reset Operation
When a reset is cleared, the memory locations from which the mode data and the reset
vector are read are selected according to the setting of the mode pins, and the mode
setting data is fetched. Mode setting data determines the CPU operating mode and the
execution start address after a reset operation ends.
For power-on or recovery from stop mode by a reset, the mode is fetched after the
oscillation stabilization wait time has elapsed.
■ Overview of Reset Operation
Figure 4.4-1 shows the reset operation flow.
Figure 4.4-1 Reset Operation Flow
Power-on reset
Stop mode reset
Watchdog timer reset
External reset
Software reset
During a reset
Oscillation stabilization wait
and reset state
Fetching the mode data
Mode fetch
(Reset operation)
Pin state and function
change associated with
external bus mode
Fetching the reset vector
Normal operation
(Run state)
CPU executes an instruction,
fetching instruction codes from
the address indicates by the
reset vector
■ Mode Pins
Setting the mode pins (MD0 to MD2) specifies how to fetch the reset vector and the mode data. Fetching
the reset vector and the mode data is performed in the reset sequence. See "8.1 Mode Setting", for details
about mode pins.
71
CHAPTER 4 RESET
■ Mode Fetch
When the reset is cleared, the CPU transfers the reset vector and the mode data stored in the hardware
memory to the appropriate registers in the CPU core. The reset vector and mode data are allocated to the
four bytes from FFFFDCH to FFFFDFH. The CPU outputs these addresses to the bus immediately after the
reset is cleared and fetches the reset vector and mode data. Using mode fetching, the CPU can begin
processing at the address indicated by the reset vector.
Figure 4.4-2 shows the transfer of the reset vector and mode data.
Figure 4.4-2 Transfer of Reset Vector and Mode Data
F2MC-16LX CPU
Memory space
FFFFDFH
Mode data
FFFFDEH
Reset vector bit23 to bit16
FFFFDDH
Reset vector bit15 to bit8
FFFFDCH
Reset vector bit7 to bit0
Mode
register
Micro-ROM
Reset sequence
PCB
PC
Reference:
Whether the reset vector and the mode data are read from internal ROM or from external memory is
specified by the setting of the mode pins. If external vector mode is specified by the mode pin
settings, the CPU will always read the reset vector and the mode data from external memory instead
of from internal ROM. If single-chip mode and internal ROM external bus mode are used, setting the
mode pins to specify internal vector mode is recommended.
● Mode data (address: FFFFDFH)
Only the reset operation changes the contents of the mode register. The mode register setting is valid after
a reset operation. See "8.1 Mode Setting", for details about mode data.
● Reset vector (address: FFFFDCH to FFFFDEH)
The execution start address after the reset operation ends is written as the reset vector.
Execution starts at the address contained in the reset vector.
72
CHAPTER 4 RESET
4.5
Reset Cause Bits
A reset cause can be identified by reading the watchdog timer control register (WDTC).
■ Reset Cause Bits
As shown in Figure 4.5-1 , a flip-flop is associated with each reset cause. The contents of the flip-flops are
obtained by reading the watchdog timer control register (WDTC). If it is necessary to identify the cause of
a reset after the reset has been cleared, the value read from the WDTC should be processed by the software
and a branch made to the appropriate program.
Figure 4.5-1 Block Diagram of Reset Cause Bits
RSTX
Pin
RSTX = L
Without periodic clear
Power-on
Power-on
detection circuit
RST bit set
External reset
request detection
circuit
Watchdog timer
reset detection circuit
LPMCR RST bit
write detection circuit
Watchdog timer
control register
(WDTC)
S
R
F/F
Q
S
R
F/F
Q
S
R
F/F
Q
S
R
F/F
Q
WDTC register
Delay
circuit
WDTC register read
F2MC-16LX internal bus
S : Set
R : Reset
:Q : Output
F/F : Flip Flop
73
CHAPTER 4 RESET
■ Correspondence between Reset Cause Bits and Reset Causes
Figure 4.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC).
Table 4.5-1 maps the correspondence between the reset cause bits and reset causes.
Figure 4.5-2 Configuration of Reset Cause Bits (Watchdog Timer Control Register)
Watchdog timer control register
bit
Address : 0000A8H
Read/write ⇒
Default value⇒
7
6
PONR
-
(R)
(X)
(-)
(-)
5
4
3
2
1
0
WDTC
WRSTERST SRST WTE WT1 WT0
(R)
(X)
(R)
(X)
(R)
(X)
(W)
(1)
(W)
(1)
(W)
(1)
Table 4.5-1 Correspondence between Reset Cause Bits and Reset Causes
Reset cause
PONR
WRST
ERST
SRST
Power-on reset
1
X
X
X
Watchdog timer overflow
*
1
*
*
External reset request via RSTX pin
*
*
1
*
Software reset request
*
*
*
1
* : Previous state retained
X: Undefined
■ Notes about Reset Cause Bits
● Multiple reset causes generated at the same time
When multiple reset causes are generated at the same time, the corresponding reset cause bits of the
watchdog timer control register (WDTC) are set to "1".
If, for example, an external reset request via the RSTX pin and the watchdog timer overflow occur at the
same time, both the ERST bit and the WRST bit are set to "1".
● Power-on reset
For a power-on reset, the PONR bit is set to "1", but all other reset cause bits are undefined.
Consequently, program the software so that it will ignore all reset cause bits except the PONR bit if it is
"1".
● Clearing the reset cause bits
The reset cause bits are cleared only when the watchdog timer control register (WDTC) is read. Any bit
that corresponds to a reset cause that has already been generated once is not cleared even though another
reset is generated (its setting of "1" is retained).
74
CHAPTER 4 RESET
4.6
Status of Pins in a Reset
This section describes the status of pins when a reset occurs.
■ Status of Pins during a Reset
The status of pins during a reset depends on the settings of mode pins (MD2 to MD0 = 011B).
● When internal vector mode has been set:
All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM.
■ Status of Pins after Mode Data is read
The status of pins after mode data has been read depends on the mode data (M1 and M0 = 00B).
● When single-chip mode has been selected (M1, M0 = 00B):
All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM.
Note:
For those pins that change to high impedance when a reset cause is generated, take care that
devices connected to them do not malfunction.
See Table 6.7-1 for information about the state of pins during a reset
75
CHAPTER 4 RESET
76
CHAPTER 5
CLOCK
This chapter describes the clock used by MB90460/465
series microcontrollers.
5.1 Clock
5.2 Block Diagram of the Clock Generation Block
5.3 Clock Selection Register (CKSCR)
5.4 Clock Mode
5.5 Oscillation Stabilization Wait Interval
5.6 Connection of an Oscillator or an External Clock to the Microcontroller
77
CHAPTER 5 CLOCK
5.1
Clock
The clock generation block controls the operation of the internal clock that controls
operation of the CPU and peripheral functions. This internal clock is called the machine
clock. One internal clock cycle is regarded as one machine cycle.
Other clocks include a clock generated by source oscillation, called an oscillation clock,
and a clock generated by the internal PLL oscillation, called a PLL clock.
■ Clock
The clock generation block contains the oscillation circuit that generates the oscillation clock. An external
oscillator is attached to this circuit. The oscillation clock can also be supplied by inputting an external
clock to the clock generation block.
The clock generation block also contains the PLL clock multiplier circuit, which generates four clocks that
are multiples of the oscillation clock.
The clock generation block controls the oscillation stabilization wait interval and PLL clock multiplication
as well as controls internal clock operation by changing the clock with a clock selector.
● Oscillation clock (HCLK)
The oscillation clock is generated either from an external oscillator attached to the oscillation circuit or by
input of an external clock.
● Main clock (MCLK)
The main clock, which is the oscillation clock divided by 2, supplies the clock input to the time-base timer
and the clock selector.
● PLL clock (PCLK)
The PLL clock is obtained by multiplying the oscillation clock with the internal PLL clock multiplier
circuit (PLL oscillation circuit). Selection can be made from among four different PLL clocks.
● Machine clock (φ)
The machine clock controls the operation of the CPU and peripheral functions. One clock cycle is regarded
as one machine cycle (1/φ). An operating machine clock can be selected from among the main clock that is
generated from the source clock frequency divided by 2 and the four clocks that are multiples of the source
clock frequency.
Note:
Although an oscillation clock of 3 MHz to 32 MHz can be generated when the operating voltage is
5 V, the maximum operating frequency for the CPU and peripheral functions is 16 MHz. If a
frequency multiplier rate exceeding the operating frequency is specified, devices will not operate
correctly.
If, for example, a source oscillation of 16 MHz is generated, only a multiplier of 1 can be specified.
A PLL oscillation of 3 to 16 MHz is possible, but this range depends on the operating voltage and
multiplier. See "Data Sheet", for details.
78
CHAPTER 5 CLOCK
■ Clock Supply Map
Since the machine clock generated in the clock generation block is supplied as the clock that controls
operation of the CPU and peripheral functions, the operation of the CPU and peripheral functions is
affected by switching of the main clock and the PLL clock (clock mode) and a change in the PLL clock
multiplier.
Since some peripheral functions receive frequency-divided output from the time-base timer, a peripheral
unit can select the clock best suited for its operation. Figure 5.1-1 shows the clock supply map.
Figure 5.1-1 Clock Supply Map
Peripheral function
4
Watchdog timer
16-bit PPG
timer 0
16-bit PPG
timer 1
Time-base timer
16-bit PPG
timer 2
Clock generation block
16-bit reload
timer 0
1 2 3 4
X0
Pin
X1
Pin
PLL multiplier circuit
System
Divide-by-2
clock
generation
HCLK
MCLK
circuit
PPG0
Pin
PPG1
Pin
PPG2
Pin
TIN0
Pin
TO0
Pin
SCK0,SIN0
Pin
PCLK
UART0
Clock selecter
UART1
CPU
16-bit reload
timer 1
Waveform
generator
SOT0
Pin
SCK1,SIN1
Pin
SOT1
Pin
TIN1
Pin
TO1
Pin
DTTI0
Pin
RTO0 to RTO5
Pin
16-bit output compare
(Ch.0 to Ch.5)
16-bit free-run
timer
16-bit input capture
(Ch.0 to Ch.3)
8/10-bit A/D
converter
Machine clock
Waveform
sequencer
FRCK
Pin
IN0 to IN3
Pin
DTTI1
Pin
OPT0 to OPT5
Pin
PWI0, PWI1
Pin
PWC (Ch.0 to Ch.1) PWO0, PWO1
Pin
3
Oscillation stabilization
wait control
79
CHAPTER 5 CLOCK
5.2
Block Diagram of the Clock Generation Block
The clock generation block consists of five blocks:
• System clock generation circuit
• PLL multiplier circuit
• Clock selector
• Clock selection register (CKSCR)
• Oscillation stabilization wait interval selector
■ Block Diagram of the Clock Generation Block
Figure 5.2-1 shows a block diagram of the clock generation block.
Figure 5.2-1 also includes the standby control circuit and time-base timer circuit.
Figure 5.2-1 Block Diagram of the Clock Generation Block
Low power mode control register (LPMCR)
STP
SLP
SPL
RST
TMD
CG1
CG0 RESV
RSTX Pin
Pin high
impedance
control circuit
Pin Hi-z control
Internal reset
generation
circuit
Internal reset
CPU intermittent
operation selecter
Select intermittent cycles
CPU clock
control circuit
Release reset
CPU clock
RST
3
Stop and sleep signals
Standby control
circuit
Cancel interrupt
Stop signal
Machine clock
Peripheral clock
control circuit
Oscillation stabiliz-ation wait is passed
Clock generator
Peripheral clock
Clock selector
Oscillation stabilization
wait interval selector
2
2
x1 x2 x3 x4
PLL multipiler
circuit
RESV MCM WS1 WS0 RESV MCS
CS1
CS0
Clock selection register (CKSCR)
X0
Divideby-2
Pin
Main clock
X1
80
Pin
System clock
generation circuit
Divideby-512
Divideby-2
Divideby-4
Divideby-4
Divideby-4
Time-base timer
CHAPTER 5 CLOCK
● System clock generation circuit
The system clock generation circuit generates an oscillation clock (HCLK) from an external oscillator
attached to it. Alternatively, an external clock can be input to this circuit.
● PLL multiplier circuit
The PLL multiplier circuit multiplies the oscillation clock through PLL oscillation and supplies a clock that
is a multiple of the frequency to the CPU clock selector.
● Clock selector
From among the main clock and four different PLL clocks, the clock selector selects the clock that is
supplied to the CPU and peripheral clock control circuits.
● Clock selection register (CKSCR)
The clock selection register is used to set switching between the oscillation clock and a PLL clock,
selection of an oscillation stabilization wait interval, and selection of a PLL clock multiplier.
● Oscillation stabilization wait interval selector
This selector selects an oscillation stabilization wait interval for the oscillation clock when stop mode is
released or when a watchdog timer reset occurs. Selection is made from among three kinds time-base timer
output. In all other cases, an oscillation stabilization wait interval is not selected.
81
CHAPTER 5 CLOCK
5.3
Clock Selection Register (CKSCR)
The clock selection register (CKSCR) is used to set switching between the main clock
and a PLL clock, selection of an oscillation stabilization wait interval, and selection of a
PLL clock multiplier.
■ Configuration of the Clock Selection Register (CKSCR)
Figure 5.3-1 shows the configuration of the clock selection register (CKSCR). Table 5.3-1 describes the
function of each bit of the clock selection register (CKSCR).
Figure 5.3-1 Configuration of the Clock Selection Register (CKSCR)
Address
0000A1H
bit 15
14
13
12
11
10
9
8
RESV MCM WS1
WS0 RESV MCS
CS1
CS0
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
CS1 CS0
Initial value
11111100B
Multiplier selection bits
The resulting clock frequency is shown in parentheses
0
1
2 x HCLK (8MHz)
1
0
3 x HCLK (12MHz)
1
1
4 x HCLK (16MHz)
1 x HCLK (4MHz)
Machine clock selection bit
0
PLL clock selected.
1
Main clock selected.
Oscillation stabilization wait interval selection bits
The corresponding time interval for an oscillation clock
frequency of 4 MHz is given in parentheses.
0
0
10
2 / HCLK (Approx. 0.256ms)
0
1
13
2 / HCLK (Approx. 2.05ms)
1
0
215/ HCLK (Approx. 8.19ms)
1
1
17
2 / HCLK (Approx. 32.74ms)*
MCM
Machine clock indication bit
0
A PLL clock is used as the machine clock.
1
The main clock is used as the machine clock.
RESV
82
(LPMCR)
0
WS1 WS0
Note:
0
0
MCS
HCLK: Oscillation clock frequency
R/W: Read/write
R:
Read only
-:
Unused
: Initial value
7
Reserved bit
1 must always be written to these bits.
18
* At power-on reset, the oscillation stabilization wait interval is 2 /HCLK.
If the machine clock selection bit is not set, the main clock is used as the machine clock.
CHAPTER 5 CLOCK
Table 5.3-1 Function Description of Each Bit of the Clock Selection Register (CKSCR)
Bit name
bit15,
bit11
bit14
bit13,
bit12
bit10
bit9,
bit8
Function
RESV:
Reserved bit
(Note)
"1" must always be written to these bits.
MCM:
Machine clock indication bit
• This bit indicates whether the main clock or a PLL clock has been selected as
the machine clock.
• When this bit is set to "0", a PLL clock has been selected. When it is set to "1",
the main clock has been selected.
• If MCS = 0 and MCM = 1, the PLL clock oscillation stabilization wait period is
in effect.
• Writing has no effect on the operation.
WS1, WS0:
Oscillation
stabilization wait interval
selection bits
• These bits select an oscillation stabilization wait interval of the oscillation clock
after stop mode has been released.
• These bits are initialized to 11B by all reset causes.
(Note)
The oscillation stabilization wait interval must be set to a value appropriate for
the oscillator used. See "4.2 Reset Causes and Oscillation Stabilization Wait
Intervals".
(Reference)
The oscillation stabilization period for all PLL clocks is fixed at 214/HCLK.
MCS:
Machine clock selection bit
• This bit specifies whether the main clock or a PLL clock is selected as the
machine clock.
• When this bit is "0", a PLL clock is selected. When this bit is "1", the main
clock is selected.
• If this bit has been set to "1" and "0" is written to it, the oscillation stabilization
wait interval for the PLL clock starts. As a result, the time-base timer is automatically cleared, and the TBOF bit of the time-base timer control register
(TBTC) is also cleared.
• For PLL clocks, the oscillation stabilization period is fixed at 214/HCLK
(the oscillation stabilization wait interval is approx. 2 ms for an oscillation clock
frequency of 4 MHz).
• When the main clock has been selected, the operating clock frequency is the frequency of the oscillation clock divided by 2 (e.g., the operating clock is 2 MHz
when the oscillation clock frequency is 4 MHz).
• This bit is initialized to "1" by power-on or watchdog reset.
(Note)
When the MCS bit is "1", write "0" to it only when the time-base timer interrupt
is masked by the TBIE bit of the time-base timer control register (TBTC) or the
interrupt level register (ILM). For 8 machine cycles after "1" is written to the
MCS bit, writing "0" to it may be disabled. Write to the bit after 8 machine
cycles have passed.
CS1, CS0:
Multiplier
selection bits
• These bits select a PLL clock multiplier.
• Selection can be made from among four different multipliers.
• These bits are initialized to 00B by all reset causes.
(Note)
When the MCS bit is "0", writing to these bits is not allowed. Write to the CS1
and CS0 bits only after setting the MCS bit to "1" (main clock mode).
HCLK: Oscillation clock frequency
83
CHAPTER 5 CLOCK
5.4
Clock Mode
Two clock modes are provided: main clock mode and PLL clock mode.
■ Main Clock Mode and PLL Clock Mode
● Main clock mode
In main clock mode, the main clock, whose frequency is the oscillation clock divided by 2, is used as the
operating clock for the CPU and peripheral resources, and the PLL clocks are disabled.
● PLL clock mode
In PLL clock mode, a PLL clock is used as the operating clock for the CPU and peripheral resources. A
PLL clock multiplier is selected with the clock selection register (CKSCR: CS1 and CS0).
■ Clock Mode Transition
Switching between main clock mode and PLL clock mode is done by writing to the MCS bit of the clock
selection register (CKSCR).
● Switching from main clock mode to PLL clock mode
When the MCS bit of CKSCR is "1" and "0" is written to it, the switch from the main clock to a PLL clock
occurs after the PLL clock oscillation stabilization wait period (214/HCLK).
● Switching from PLL clock mode to main clock mode
When the MCS bit of CKSCR is "0" and "1" is written to it, the switch from the PLL clock to the main
clock occurs when the edges of the PLL clock and the main clock coincide (after 1 to 8 PLL clocks).
Note:
Even though the MCS bit of CKSCR is rewritten, machine clock switching does not occur
immediately. When operating a resource that depends on the machine clock, make sure that
machine clock switching has been done by referring to the MCM bit of CKSCR before operating the
resource. If the mode is switched to another clock mode or low-power-consumption mode before
completion of switching, the mode may not be switched.
■ Selection of a PLL Clock Multiplier
Writing a value from “00B” to “11B” to the CS1 and CS0 bits of CKSCR selects one to the four PLL clock
multipliers.
■ Selection of a PLL Clock Multiplier
Writing a value from “00B” to “11B” to the CS1 and CS0 bits of CKSCR selects one to the four PLL clock
multipliers.
■ Machine Clock
The machine clock may be either a PLL clock output from the PLL multiplier circuit or the clock that is the
source oscillation frequency divided by 2. This machine clock is supplied to the CPU and peripheral
functions.
Either the main clock or a PLL clock can be selected by writing to the MCS bit of CKSCR.
84
CHAPTER 5 CLOCK
Figure 5.4-1 shows the status change caused by the machine clock switching.
Figure 5.4-1 Status Dhange Diagram for Machine Dlock Selection
Power-on
(1)
Main
MCS = 1
MCM = 1
CS1, CS0 = xx
(6)
(7)
(7)
(7)
Main
PLLx
MCS = 0
MCM = 1
CS1, CS0 = xx
(2)
(3)
(4)
(5)
PLL1
Main
MCS = 1
MCM = 1
CS1, CS0 = 00
PLL1: Multiplied
by 1
(6) MCS = 0
MCM = 0
CS1, CS0 = 00
PLL2
Main
MCS = 1
MCM = 0
CS1, CS0 = 01
PLL2: Multiplied
by 2
MCS = 0
(6)
MCM = 0
CS1, CS0 = 01
PLL3
Main
MCS = 1
MCM = 0
CS1, CS0 = 11
(6)
PLL3: Multiplied
by 3
MCS = 0
MCM = 0
CS1, CS0 = 10
(6)
PLL4: Multiplied
by 4
MCS = 0
MCM = 0
CS1, CS0 = 11
(7)
PLL4
Main
MCS = 1
MCM = 0
CS1, CS0 = 11
(1) The MCS bit is cleared.
(2) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 00.
(3) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 01.
(4) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 10.
(5) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 11.
(6) The MCS bit is set (including also hardware standby and watchdog timer resets).
(7) PLL clock and main clock synchronization timing.
MCS:
Machine clock selection bit of CKSCR
MCM:
Machine clock indication bit of CKSCR
CS1, CS0: Multiplier selection bits of CKSCR
Note:
The initial value for the machine clock setting is main clock (MCS of CKSCR = 1).
85
CHAPTER 5 CLOCK
5.5
Oscillation Stabilization Wait Interval
When the power is turned on, when stop mode is released, or when a watchdog timer
reset occurs, the oscillation clock starts, oscillation is unstable initially. Therefore, an
oscillation stabilization wait interval is required. When the switch from the main clock to
a PLL clock occurs, an oscillation stabilization wait interval is also required when PLL
oscillation starts.
■ Oscillation Stabilization Wait Interval
Ceramic and crystal oscillators generally require an oscillation stabilization wait interval of a few to several
dozen milliseconds until they stabilize at their natural frequency when oscillation starts.
For this reason, CPU operation is not allowed as soon as oscillation starts and is allowed only after full
stabilization of oscillation. After the oscillation stabilization wait interval has elapsed, the clock is supplied
to the CPU.
Because the oscillation stabilization time depends on the type of the oscillator (crystal, ceramic, etc.), the
proper oscillation stabilization wait interval for the oscillator used must be selected. An oscillation
stabilization wait interval is selected by setting the clock selection register (CKSCR).
In a switch from the main clock to a PLL clock, the CPU continues to operate on the main clock during the
oscillation stabilization wait interval. After this interval, the operating clock switches to the PLL clock.
Figure 5.5-1 shows the operation after oscillation starts.
Figure 5.5-1 Operation when Oscillation Starts
Oscillator-activated Oscillation stabilization Normal operation start
wait interval
oscillation time
or change to PLL clock
Start of oscillation
86
Stable oscillation
CHAPTER 5 CLOCK
5.6
Connection of an Oscillator or an External Clock to the
Microcontroller
The F2MC-16LX microcontroller contains a system clock generation circuit. Connecting
an external oscillator to this circuit generates the system clock.
Alternatively, an externally generated clock can be input to the microcontroller.
■ Connection of an Oscillator or an External Clock to the Microcontroller
● Example of connecting a crystal or ceramic oscillator to the microcontroller
Connect a crystal or ceramic oscillator as shown in the example in Figure 5.6-1 .
Figure 5.6-1 Example of Connecting a Crystal or Ceramic Oscillator to the Microcontroller
X0
MB90460/465 series
X1
● Example of connecting an external clock to the microcontroller
As shown in Figure 5.6-2 , connect an external clock to pin X0. Pin X1 must be open.
Figure 5.6-2 Example of Connecting an External Clock to the Microcontroller
X0
MB90460/465 series
Open
X1
87
CHAPTER 5 CLOCK
88
CHAPTER 6
LOW POWER
CONSUMPTION MODE
This chapter describes the low power consumption
mode of MB90460/465 series microcontrollers.
6.1 Low Power Consumption Mode
6.2 Block Diagram of the Low Power Consumption Control Circuit
6.3 Low Power Consumption Mode Control Register (LPMCR)
6.4 CPU Intermittent Operation Mode
6.5 Standby Mode
6.6 State Change Diagram
6.7 State of Pins in Standby Mode and during Reset
6.8 Usage Notes on Low Power Consumption Mode
89
CHAPTER 6 LOW POWER CONSUMPTION MODE
6.1
Low Power Consumption Mode
F2MC-16LX microcontrollers have the following CPU operating modes, any of which can
be used depending on the operating clock selection and clock operation control:
• Clock mode (PLL clock mode and main clock mode)
• CPU intermittent operation mode (PLL clock intermittent operation mode and main
clock intermittent operation mode)
• Standby mode (sleep, time-base timer and stop modes)
All modes other than PLL clock mode are low power consumption mode.
■ CPU Operating Modes and Current Consumption
Figure 6.1-1 shows the relation between the CPU operating modes and current consumption
Figure 6.1-1 CPU Operating Modes and Current Consumption
Current consumption
Several tens
of mA
CPU operating
mode
Multiplied-by-four
clock
PLL clock mode
Multiplied-by-three
clock
Multiplied-by-two
clock
Multiplied-by-1
clock
PLL clock intermittent operation mode
Multiplied-by-four
clock
Multiplied-by-three
clock
Multiplied-by-two
clock
Multiplied-by-1
clock
Main clock mode (1/2 clock mode)
Main clock intermittent operation mode
Several mA
Standby mode
Sleep mode
Time-base timer mode
Stop mode
Several µA
Low power consumption mode
Note:
This figure is only an indication of the degree of power consumption for each mode. Actual
current consumption values may not agree with those in the figure.
90
CHAPTER 6 LOW POWER CONSUMPTION MODE
■ Clock Mode
● PLL clock mode
A PLL clock that is a multiple of the oscillation clock (HCLK) frequency is used to operate the CPU and
peripheral functions.
● Main clock mode
The main clock, with a frequency one-half that of the oscillation clock (HCLK), is used to operate the CPU
and peripheral functions. In main clock mode, the PLL multiplier circuit is inactive.
Reference:
See "5.1 Clock", for details about clock mode.
■ CPU Intermittent Operation Mode
CPU intermittent operation mode causes the CPU to operate intermittently, while high-speed clock pulses
are supplied to peripheral functions, reducing power consumption. In CPU intermittent operation mode,
intermittent clock pulses are only applied to the CPU when it is accessing a register, internal memory, a
peripheral function, or an external unit.
■ Standby Mode
In standby mode, the low power consumption control circuit stops supplying the clock to the CPU (sleep
mode) or the CPU and peripheral functions (time-base timer mode), or stops the oscillation clock itself
(stop mode), reducing power consumption.
● PLL sleep mode
PLL sleep mode is activated to stop the CPU operating clock when the microcontroller enters PLL clock
mode; other components continue to operate on the PLL clock.
● Main sleep mode
Main sleep mode is activated to stop the CPU operating clock when the microcontroller enters main clock
mode; other components continue to operate on the main clock.
● PLL time-base timer mode
PLL time-base timer mode causes microcontroller operation, with the exception of the oscillation clock,
PLL clock and time-base timer, to stop. All functions other than the time-base timer are deactivated.
● Main time-base timer mode
Main time-base timer mode causes microcontroller operation, with the exception of the oscillation clock,
main clock and the time-base timer, to stop. All functions other than the time-base timer are deactivated.
● Stop mode
Stop mode causes the source oscillation to stop. All functions are deactivated.
Note:
Because stop mode turns the oscillation clock off, this mode saves most power while data is being
retained.
If the mode is switched to another clock mode or low-power-consumption mode before completion of
switching, the mode may not be switched.
91
CHAPTER 6 LOW POWER CONSUMPTION MODE
6.2
Block Diagram of the Low Power Consumption Control
Circuit
The low power consumption control circuit consists of the following seven blocks:
• CPU intermittent operation selector
• Standby clock control circuit
• CPU clock control circuit
• Peripheral clock control circuit
• Pin high-impedance control circuit
• Internal reset generation circuit
• Low power consumption mode control register (LPMCR)
■ Block Diagram of the Low Power Consumption Control Circuit
Figure 6.2-1 shows the block diagram of the low power consumption control circuit.
Figure 6.2-1 Block diagram of the low power consumption control circuit
Low power mode control register (LPMCR)
STP
SLP
SPL
RST
TMD
CG1
CG0 RESV
RSTX Pin
Pin high
impedance
control circuit
Pin Hi-z control
Internal reset
generation
circuit
Internal reset
CPU intermittent
operation selecter
Select intermittent cycles
CPU clock
control circuit
Release reset
CPU clock
RST
3
Stop and sleep signals
Standby control
circuit
Cancel interrupt
Stop signal
Machine clock
Peripheral clock
Oscillation stabiliz- control circuit
-ation wait is passed
Clock generator
Peripheral clock
Clock selector
Oscillation stabilization
wait interval selector
2
2
x1 x2 x3 x4
PLL multipiler
circuit
RESV MCM WS1 WS0 RESV MCS CS1
CS0
Clock selection register (CKSCR)
X0
Divideby-2
Pin
Main clock
X1
92
Pin
System clock
generation circuit
Divideby-512
Divideby-2
Divideby-4
Divideby-4
Divideby-4
Time-base timer
CHAPTER 6 LOW POWER CONSUMPTION MODE
● CPU intermittent operation selector
This selector selects the number of clock pulses the CPU is to be halted during CPU intermittent operation
mode.
● Standby control circuit
The standby control circuit controls the CPU clock control circuit and the peripheral clock control circuit,
and turns the low power consumption mode on and off.
● CPU clock control circuit
This circuit controls the clocks supplied to the CPU. This circuit controls the clocks supplied to peripheral
functions for the peripheral clock control.
● Peripheral clock control circuit
This circuit controls the clocks supplied to peripheral functions.
● Pin high-impedance control circuit
This circuit makes the external pins high-impedance when the microcontroller enters time-base timer mode
and stop mode.
For the pins with the pull-up option, this circuit disconnects the pull-up resistor when the microcontroller
enters stop mode.
● Internal reset generation circuit
This circuit generates an internal reset signal.
● Low power consumption mode control register (LPMCR)
This register is used to switch to and release standby mode and to set the CPU intermittent operation
function.
93
CHAPTER 6 LOW POWER CONSUMPTION MODE
6.3
Low Power Consumption Mode Control Register (LPMCR)
The low power consumption mode control register (LPMCR) switches to or releases low
power consumption mode. It is also used to set the number of CPU clock pulses the
CPU is to be halted during CPU intermittent mode.
■ Low Power Consumption Mode Control Register (LPMCR)
Figure 6.3-1 shows the configuration of the low power consumption mode control register (LPMCR).
Figure 6.3-1 Configuration of the Low Power Consumption Mode Control Register (LPMCR)
bit 15
Address
0000A0H
(CKSCR)
7
6
5
4
STP
SLP
SPL
W
W
R/W
3
2
RST TMDX CG1
W
W
0
1
R/W
CG0 RESV
R/W
RESV
Initial value
00011000B
R/W
Reserved bit
1 must always be written to these bits.
CPU halt clock pulses selection bits
CG1 CG0
0
0
0 clock pulse (CPU clock = Peripheral clock)
0
1
9 clock pulses (CPU clock: Peripheral clock = 1: 3 to 4 approx.)
1
0
17 clock pulses (CPU clock: Peripheral clock = 1: 5 to 6 approx.)
1
1
33 clock pulses (CPU clock: Peripheral clock = 1: 9 to 10 approx.)
TMDX
Time-base timer bit
0
Switch to time-base timer mode
1
No change, no effect on operation
RST
Internal reset signal generation bit
0
Generates an internal reset signal of 3 machine cycles.
1
No change, no effect on operation
SPL
Pin state setting bit (for time-base timer mode and stop mode)
0
Retained
1
High-impedance
SLP
R/W:
W:
94
Read/write
Write-only
: Initial value
Sleep bit
0
No change, no effect on operation
1
Switch to sleep mode
STP
Stop bit
0
No change, no effect on operation
1
Switch to stop mode
CHAPTER 6 LOW POWER CONSUMPTION MODE
Table 6.3-1 Function Description of Each Bit of the Low Power Consumption Mode Control Register
(LPMCR)
Bit name
Function
STP:
Stop bit
•
•
•
•
•
This bit indicates switching to stop mode.
When "1" is written to this bit, a switch to stop mode.
Writing "0" to this bit has no effect on operation.
This bit is cleared to "0" by a reset or by release of stop state.
The read value of this bit is always "0".
bit6
SLP:
Sleep bit
•
•
•
•
•
This bit indicates switching to sleep mode.
When "1" is written to this bit, the mode switches to sleep mode.
Writing "0" to this bit has no effect on operation.
This bit is cleared to "0" by a reset or by release of sleep mode.
The read value of this bit is always "0".
bit5
SPL:
Pin state setting bit (for
time-base timer mode and
stop mode)
•
•
•
•
This bit is enabled while either time-base timer mode or stop mode is in effect.
When this bit is "0", the level of the external pins is retained.
When this bit is "1", the status of the external pins changes to high- impedance.
This bit is initialized to "0" by a reset.
bit4
RST:
Internal reset signal
generation bit
• When "0" is written to this bit, an internal reset signal of 3 machine cycles is
generated.
• Writing "1" to this bit has no effect on operation.
• The read value of this bit is always "1".
TMDX:
Time-base timer bit
•
•
•
•
•
bit2,
bit1
CG1, CG0:
CPU halt clock pulses
selection bits
• These bits set the number of CPU halt clock pulses for the CPU intermittent
operation function.
• The clock supplied to the CPU is stopped after the execution of every instruction
for the specified number of clock pulses.
• Selection can be made from among four different clock pulses.
• These bits are initialized to 00B by a power-on or watchdog timer reset. Other
resets do not initialize these bits.
bit0
RESV:
Reserved bit
(Note)
"1" must always be written to this bit.
bit7
bit3
This bit indicates switching to time-base timer mode.
When "0" is written to this bit, the mode switches to time-base timer mode.
Writing "1" to this bit has no effect on operation.
This bit is set to "1" by a reset or by release of time-base timer mode.
The read value of this bit is always "1".
Note:
If "1" is written to the STP bit, SLP bit and "0" is written to TMDX bit at the same time, switching to
stop mode takes the highest priority, then time-base timer mode and sleep mode has the lowest
priority.
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CHAPTER 6 LOW POWER CONSUMPTION MODE
■ Access to the Low Power Consumption Mode Control Register
Switching to low power consumption mode (including stop mode and sleep mode) is performed by writing
to the low power consumption mode control register. Only the instructions listed in Table 6.3-2 should be
used for this purpose. If other instructions are used for switching to low power consumption mode,
operation cannot be assured. To control functions not listed in Table 6.3-2, any instruction can be used.
When word-length is used for writing to the low power consumption mode control register, even addresses
must be used. Writing with odd addresses to switch to low power consumption mode may cause a
malfunction.
Table 6.3-2 Instructions to be used for switching to Low Power Consumption Mode
96
MOV io, #imm8
MOV io, A
MOV @RLi+disp8, A
MOVW io, #imm16
MOVW io, A
MOVW @RLi+disp8, A
MOV dir, #imm8
MOV dir, A
MOV eam, #imm8
MOV addr, 16A
MOV
MOV
MOVW
MOVW
MOVW eam, #imm16
MOVW addr16, A
MOVW eam, RWi
MOVW eam, A
SETB io:bp
CLRB io:bp
SETB dir:bp
CLRB dir:bp
dir, #imm16
dir, A
SETB addr16:bp
CLRB addr16:bp
eam, Ri
eam, A
CHAPTER 6 LOW POWER CONSUMPTION MODE
6.4
CPU Intermittent Operation Mode
CPU intermittent operation mode is used for intermittent operation of the CPU while
external buses and peripheral functions continue to operate at high speed. Its purpose
is to reduce power consumption.
■ CPU Intermittent Operation Mode
CPU intermittent operation mode halts the supply of the clock to the CPU for a certain period. The halt
occurs after the execution of every instruction that accesses a register, internal memory (ROM and RAM),
I/O, peripheral functions and the external bus. Internal bus cycle activation is therefore delayed. While a
steady rate of peripheral clock pulses are supplied to the peripheral functions, the rate of CPU execution is
reduced, enabling processing with low power consumption.
• The CG1 and CG0 bits of the low power consumption mode control register (LPMCR) are used to select
the number of clock pulses per halt cycle of the clock supplied to the CPU.
• External bus operation uses the same clock as that used for peripheral functions.
• Instruction execution time in CPU intermittent mode can be calculated. A correction value should be
obtained by multiplying the number of times instructions that access a register, internal memory,
internal peripheral functions, and the external bus are executed by the number of clock pulses per halt
cycle. Add this correction value to the normal execution time.
Figure 6.4-1 shows the operating clock pulses during CPU intermittent operation mode.
Figure 6.4-1 Clock Pulses during CPU Intermittent Operation
Peripheral clock
CPU clock
Intermittent operation halt cycle
One instruction
execution cycle
Internal bus activation cycle
97
CHAPTER 6 LOW POWER CONSUMPTION MODE
6.5
Standby Mode
Standby mode includes the sleep (PLL sleep and main sleep), time-base timer and stop
modes.
■ Operating Status during Standby Mode
Table 6.5-1 summarizes the operating statuses during standby mode.
Table 6.5-1 Operation Statuses during Standby Mode
Standby mode
Sleep
mode
PLL sleep
mode
MCS = 0
SLP = 1
Main sleep
mode
MCS = 1
SLP = 1
PLL time-base
timer mode
(SPL = 1)
Main timebase timer
mode (SPL =
0)
Main timebase timer
mode (SPL =
1)
Stop
mode
Oscillation
Clock
CPU
Peripheral
Active
PLL time-base
timer mode
(SPL = 0)
Timebase
timer
mode
Condition
for switch
Main/PLL stop
mode
(SPL = 0)
Main/PLL stop
mode
(SPL = 1)
Release
event
Active
Hold
MCS = 0
TMDX = 0
Active
Hi-Z
Active
Inactive *
In-active
Hold
MCS = 1
STP = 1
Hi-Z
Hold
MCS = x
STP = 1
Inactive
Inactive
Inactive
*:
Only the time-base timer is active.
SPL:
Pin state setting bit of low power consumption mode control register (LPMCR)
SLP:
Sleep bit of LPMCR
STP:
Stop bit of LPMCR
TMDX: Time-base timer bit of LPMCR
MCS: Machine clock selection bit of clock selection register (CKSCR)
Hi-Z: High-impedance
98
Pin
Hi-Z
Reset or
Interrupt
CHAPTER 6 LOW POWER CONSUMPTION MODE
6.5.1
Sleep Mode
Sleep mode causes the CPU operating clock to stop while other components continue
to operate.
When the low power consumption mode control register (LPMCR) indicates a switch to
sleep mode, a switch to PLL sleep mode occurs if PLL clock mode has been set.
Alternatively, a switch to main sleep mode occurs if main clock mode has been set.
■ Switching to Sleep Mode
Writing "1" to the SLP and TMDX bit of LPMCR and 0 to the STP bit of LPMCR triggers a switch to sleep
mode.
At this time, if the MCS bit of the clock selection register (CKSCR) is "0", the microcontroller enters PLL
sleep mode. If the MCS bit of CKSCR is "1", the microcontroller enters main sleep mode.
Note:
Since the STP/TMDX bit setting overrides the SLP bit setting when "1" is written to the SLP, STP
and "0" to TMDX bit at the same time, the mode switches to stop/time-base timer mode.
● Data retention function
In sleep mode, the contents of dedicated registers, such as accumulators and internal RAM, are retained.
● Operation during an interrupt request
Writing "1" to the SLP bit of LPMCR during an interrupt request does not trigger a switch to sleep mode.
If the CPU does not accept the interrupt, the CPU executes the next instruction. If the CPU accepts the
interrupt, CPU operation immediately branches to the interrupt processing routine.
● Status of pins
During sleep mode, all pins retain the state they had immediately before the switch to sleep mode. The
once exceptions are the pins used for bus input/output or bus control.
■ Release of Sleep Mode
The low power consumption control circuit releases sleep mode. Releasing is caused by the input of a reset
or by an interrupt.
● Return to normal mode by a reset
When sleep mode is released by a reset, the microcontroller is placed in the reset state on release from sleep
mode.
99
CHAPTER 6 LOW POWER CONSUMPTION MODE
● Return to normal mode by an interrupt
If an interrupt request higher than level 7 is issued from a peripheral circuit during sleep mode, sleep mode
is released. After release, the CPU handles the interrupt as it would any other interrupt. The CPU executes
processing according to the settings of the I flag of the condition code register (CCR), interrupt level mask
register (ILM), and interrupt control register (ICR). If that interrupt is accepted, the CPU executes interrupt
processing. If the interrupt is not accepted, the CPU resumes execution with the instruction that follows the
instruction in which switching to sleep mode was specified.
Figure 6.5-1 shows the release of sleep mode for an interrupt.
Figure 6.5-1 Release of Sleep Mode for an Interrupt
Interrupt from a peripheral circuit
Enable flag is set
INT occurs
(IL < 7)
NO
Sleep mode is not
released
YES
Execution of the
next instruction
Sleep mode is not
released
YES
I=0
Sleep mode is
released
NO
YES
ILM < IL
Execution of the
next instruction
NO
Interrupt execution
Note:
When interrupt processing is executed normally, the CPU first executes the instruction that follows
the instruction in which switching to sleep mode was specified. The CPU then proceeds to interrupt
processing.
● Return to normal mode from PLL sleep mode by an external reset
During PLL sleep mode, the main clock and the PLL clock generate clock pulses. Since an external reset
does not initialize the MCS bit in the clock selection register (CKSCR) to "1", PLL clock mode remains
selected (MCS of CKSCR = 0). On return from PLL sleep mode by an external reset, the CPU starts
operation using the PLL clock immediately after PLL sleep mode is released as shown in Figure 6.5-2.
100
CHAPTER 6 LOW POWER CONSUMPTION MODE
Figure 6.5-2 Release of PLL Sleep Mode (by External Reset)
RSTX pin
Sleep mode
Main clock
Oscillating
PLL clock
Oscillating
PLL clock
CPU clock
CPU operation
Inactive
Sleep mode released.
Reset sequence
Execution
Reset cleared.
101
CHAPTER 6 LOW POWER CONSUMPTION MODE
6.5.2
Time-base Timer Mode
Time-base timer mode causes the microcontroller operation to stop with the exception
of the source oscillation and the time-base timer. All functions other than time-base
timer are deactivated.
■ Switching to Time-base Timer Mode
Writing "0" to the TMDX and STP bit of LPMCR triggers a switch to time-base timer mode.
At this time, if the MCS bit of the clock selection register (CKSCR) is "0", the microcontroller enters PLL
time-base timer mode. If the MCS bit of CKSCR is "1", the microcontroller enters main time-base timer
mode.
Note:
Since the STP bit setting overrides the TMDX bit setting when "0" is written to the TMDX and STP
bits at the same time, the mode switches to stop mode.
● Data retention function
In time-base timer mode, the contents of dedicated registers, such as accumulators and internal RAM, are
retained.
● Operation during an interrupt request
Writing "0" to the TMDX bit of LPMCR during an interrupt request does not trigger switching to time-base
timer mode.
● Status of pins
Selection of whether the external pins retain the state they had immediately before switching to time-base
timer mode or go to high-impedance with switching to this mode can be controlled by the SPL bit of
LPMCR.
■ Release of Time-base Timer Mode
The low power consumption control circuit releases time-base timer mode. Release is caused by input of a
reset or an interrupt. If time-base timer mode is released by a reset, the microcontroller is placed in the
reset state after its release from time-base timer mode.
● Return to normal mode by a reset
If time-base timer mode is released by a reset, the microcontroller is placed in the reset state after release
from time-base timer mode.
● Return to normal mode by an external reset
Since an external reset does not initialize the MCS bit of the clock selection register (CKSCR) to "1", PLL
clock mode remains selected (MCS of CKSCR = 0) or main clock mode remains selected (MCS of CKSCR =
1). On return from time-base timer mode by an external reset, the CPU starts operation using PLL/Main
clock immediately after time-base timer mode is released.
102
CHAPTER 6 LOW POWER CONSUMPTION MODE
Figure 6.5-3 shows the operation for return to normal mode from time-base timer mode triggered by an
external reset.
Figure 6.5-3 Release of Time-base Timer Mode (by an External Reset)
RSTX pin
Time-base timer mode
Main clock
Oscillating
PLL clock
Oscillating
Main/PLL clock
CPU clock
CPU operation
Inactive
Time-base timer mode released.
Reset sequence
Execution
Reset cleared.
● Return to normal mode by an interrupt
If an interrupt request higher than level 7 is issued from a peripheral circuit in time-base timer mode (when
IL2, IL1 and IL0 of the interrupt control register (ICR) are set to a value other than "111B"), the low power
consumption control circuit releases time-base timer mode. After the release, the CPU handles the interrupt
as it would any other interrupt. The CPU executes processing according to the settings of the I flag of the
condition code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR). If
the interrupt is accepted, the CPU executes interrupt processing. If the interrupt is not accepted, the CPU
resumes execution with the instruction that follows the instruction in which switching to time-base timer
mode was specified.
Note:
When interrupt processing is executed normally, the CPU first executes the instruction that follows
the instruction in which switching to time-base timer mode was specified. The CPU then proceeds to
interrupt processing.
103
CHAPTER 6 LOW POWER CONSUMPTION MODE
6.5.3
Stop Mode
Stop mode causes the source oscillation to stop and deactivates all functions. It
therefore saves the most power saving while data is being retained.
■ Switching to Stop Mode
Writing "1" to the STP bit of LPMCR triggers a switch to stop mode.
At this time, if the MCS bit of the clock selection register (CKSCR) is "0", the microcontroller enters PLL
stop mode. If the MCS bit of CKSCR is "1", the microcontroller enters main stop mode.
● Data retention function
In stop mode, the contents of dedicated registers, such as accumulators and internal RAM, are retained.
● Operation during an interrupt
Writing "1" to the STP bit of LPMCR during an interrupt request does not trigger switching to stop mode.
● Pin state setting
Selection of whether the external pins retain the state they had immediately before switching to stop mode
or go to high-impedance with switching to stop mode can be controlled by the SPL bit of LPMCR.
■ Release of Stop Mode
The low power consumption control circuit releases stop mode. The release is caused by input of a reset or
by an interrupt.
Because the oscillation of the operating clock is halted before return to normal mode from stop mode, the
low power consumption control circuit puts the microcontroller into the oscillation stabilization wait state,
then releases stop mode.
● Return to normal mode by a reset
When stop mode is released by a reset cause, the microcontroller is placed in the oscillation stabilization
wait and reset state after release from stop mode. The reset sequence proceeds after the oscillation
stabilization wait interval has elapsed.
● Return to normal mode by a interrupt
If an interrupt request higher than level 7 is issued from a peripheral circuit during stop mode (when IL2,
IL1 and IL0 of the interrupt control register (ICR) are set to a value other than "111B"), the low power
consumption control circuit releases stop mode. After release, the CPU handles the interrupt as it would
any other interrupts. However, the CPU starts after the main clock oscillation stabilization wait interval
specified by the WS1 and WS0 bits of the clock selection register (CKSCR) has elapsed. The CPU
executes processing according to the settings of the I flag of the condition code register (CCR), interrupt
level mask register (ILM), and interrupt control register (ICR). If the interrupt is accepted, the CPU
executes interrupt processing. If the interrupt is not accepted, the CPU resumes the execution with the
instruction that follows the instruction in which switching to stop mode was specified.
104
CHAPTER 6 LOW POWER CONSUMPTION MODE
Note:
When interrupt processing is executed normally, the CPU first executes the instruction that follows
the instruction in which switching to stop mode was specified. The CPU then proceeds to interrupt
processing.
Figure 6.5-4 shows the operation of return to normal mode from stop mode.
Figure 6.5-4 Release of Main Stop Mode (by External Reset)
RSTX pin
Stop mode
Main clock
Oscillation stabilization wait time
Oscillating
PLL clock
Oscillation stabilization wait time
Oscillating
CPU clock
Main/PLL clock
CPU operation
Inactive
Stop mode released
Reset
sequence
Execution
Reset cleared
105
CHAPTER 6 LOW POWER CONSUMPTION MODE
6.6
State Change Diagram
Figure 6.6-1 shows the state change diagram of F2MC-16LX operation and gives change
conditions.
■ State Change Diagram
Figure 6.6-1 State Change Diagram
Power-on
Main clock mode
Source Osc.
stabilization wait and
reset state
[9]
Main clock
reset state
[1]
Main time-base
timer state
[4]
[13]
Source clock osc.
stabilization wait
state
[8]
[2]
Main Stop
state
PLL stop
state
[16]
[18]
[6]
[11]
[5]
Main run
state
[19]
[14]
[3]
[10]
[7]
Source clock osc.
stabilization wait
state
[12]
Source Osc.
stabilization wait
and reset state
[15]
[23]
[6]
Main sleep
state
[22]
[20]
PLL run
state
<10>
[21]
[7]
<1>
<3>
PLL sleep
state
<7>
<4>
<5>
PLL clock
reset state
<8>
PLL time-base
timer state
[17]
Main clock
reset state
PLL clock mode
Note:
106
When the clock mode is switched, do not switch to low power consumption mode and other clock
mode before this switching is completed. Confirm the completion of clock mode switching by
referring to the MCM and SCM bits of the clock selection register (CKSCR). If the mode is switched
to another clock mode or low-power-consumption mode before completion of switching, the mode
may not be switched.
CHAPTER 6 LOW POWER CONSUMPTION MODE
■ Low Power Consumption Mode Operating States
Table 6.6-1 lists the operating states of low power consumption mode.
Table 6.6-1 Low Power Consumption Mode Operating States
Low power
consumption
mode
Condition
for transition
Oscillation
Clock
CPU
Peripheral
Pin
Release
event
Main sleep
MCS = 1
SLP = 1
Active
Active
Inactive
Active
Active
Reset or
interrupt
PLL sleep
MCS = 0
SLP = 1
Active
Active
Inactive
Active
Active
Reset or
interrupt
Main/PLL
time-base timer
(SPL = 0)
MCS = x
TMDX = 0
Active
Active
Inactive
Inactive
Hold
Reset or
interrupt
Main/PLL
time-base timer
(SPL = 1)
MCS = x
TMDX = 0
Active
Active
Inactive
Inactive
Hi-Z
Reset or
interrupt
Main/PLL stop
(SPL = 0)
MCS = x
STP = 1
Inactive
Inactive
Inactive
Inactive
Hold
Reset or
interrupt
Main/PLL stop
(SPL = 1)
MCS = x
STP = 1
Inactive
Inactive
Inactive
Inactive
Hi-Z
Reset or
interrupt
● Clock mode switching and release (excluding standby mode)
Table 6.6-2 lists clock mode switching and release.
Table 6.6-2 Clock Mode Wwitching and Release
Transition
Conditions
After power-on, transition to
the main run state
[1] Source clock oscillation stabilization wait interval ends. (Time-base timer output)
[2] Reset input has been cleared.
Reset during main run state
[3] External reset, software reset, or watchdog timer reset
Transition from main run
state to PLL run state
[19] MCS = 0 (After PLL clock oscillation stabilization wait, switch to PLL clock) *
Return to main run state
from PLL run state
[20] MCS = 1 (PLL clock deactivated)
Reset during PLL run state
[6] External reset or software reset ([7] After reset, return to PLL run state)
[13] Watch dog reset ([2] After reset, return to main run state)
*:The microcontroller operates using the main clock during the PLL clock oscillation stabilization wait state.
107
CHAPTER 6 LOW POWER CONSUMPTION MODE
● Switching to and release of standby mode
Table 6.6-3 lists switching to and release of standby mode.
Table 6.6-3 Switching to and Release of Standby Mode
Transition
Conditions
Transition to main sleep
mode
[21] SLP = 1, MCS = 1 (Transition from main run state)
[2] SLP =1, MCS = 1 (Transition from PLL run state)
Release of main sleep mode
[22] Interrupt input
[4] External reset
Transition to main stop mode
[5] STP =1, MCS = 1 (Transition from main run state)
Transition to PLL stop mode
<10>STP =1, MCS = 0 (Transition from PLL run state)
Release of main stop mode
[7] Interrupt input ([10] indicates return to main run state after oscillation stabilization
wait)
[8] External reset ([9] indicates external reset during oscillation stabilization wait state)
Release of PLL stop mode
[14] Interrupt input ([15] indicates return to PLL run state after oscillation stabilization
wait)
[16] External reset ([18] indicates external reset during oscillation stabilization wait
state)
Transition to PLL sleep
mode
<1> SLP = 1, MCS = 0 (Transition from PLL run state)
<2> SLP = 1, MCS = 0 (Transition from main run state, switch to PLL clock after PLL
clock oscillation stabilization wait) *
Release of PLL sleep mode
<3> Interrupt input
<4> External reset
Transition to main time-base
timer mode
[6] STP = 1, MCS = 1 (Transition from main run state)
Transition to PLL time-base
timer mode
<5> STP = 1, MCS = 0 (Transition from PLL run state)
Release of main time-base
timer mode
[11] Interrupt input
[12] External reset ([2] After reset, return to main run state)
Release of PLL time-base
timer mode
<7> Interrupt input
<8> External reset ([7] After reset, return to PLL run state)
*The microcontroller operates using the main clock during the PLL clock oscillation stabilization wait state.
108
CHAPTER 6 LOW POWER CONSUMPTION MODE
6.7
State of Pins in Standby Mode and during Reset
The state of pins in standby mode and during reset are summarized below for each
memory access mode.
■ Software Pull-up Resistor
For pins with a pull-up resistor selected by software, the pull-up resistor is disconnected during L level
output.
■ State of Pins in Single-chip Mode
Table 6.7-1 lists the state of pins in single-chip mode.
Table 6.7-1 State of Pins in Single-chip Mode
Standby mode
Pin name
Stop
Reset
Sleep
SPL = 0
P00 to P07
P17
P20 to P27
P30 to P37
P40
P42 to P47
P50 to P57
P60 to P63
P10 to P16
P63
The preceding state is
retained*2
The preceding state is
retained*2
SPL = 1
Input shut off*3 /
output Hi-Z
Input disabled /
output Hi-Z
Input enabled*1
*1: "Input enabled" means that the input function is enabled when corresponding external interrupt pin is enable. Select
either the pull-up or the pull-down option. Alternatively, an external input is required. Pins used as output ports are the
same as other ports.
*2: "The preceding state is retained" means that the state of the pin output existing immediately before switching to this
mode is retained. Note that input is disabled if the preceding state was input.
• "State of the pin output is retained" means that the pin retains the value output from an operating internal
peripheral unit or the value output from the port if the pin is used as a port.
• "Input disabled" means that the input to the pin is not accepted because the internal circuit is inactive,
although operation of the input gate adjacent to the pin is enabled.
*3: In the "Input shut off" state, input is masked and the "L" level is transmitted internally. "Output Hi-Z" means that the
pin state is high-impedance because driving of the pin driving transistor is disabled.
109
CHAPTER 6 LOW POWER CONSUMPTION MODE
6.8
Usage Notes on Low Power Consumption Mode
Note the following six items to use low power consumption mode:
• Switching to standby mode and interrupts
• Release of standby mode by an interrupt
• Setting of standby mode
• Release of stop mode
• Release of time-base timer mode
• Oscillation stabilization wait time
■ Notes on Standby Mode
● Switching to standby mode and interrupts
During an interrupt request to the CPU from a peripheral function, the CPU ignores the STP and SLP bits
of the low power consumption mode control register (LPMCR) even though 1 has been written to these
bits. Thus, switching to any standby mode is disabled (even after processing the interrupt is completed,
there is no switch to standby mode). If the interrupt level is higher than 7, this action does not depend on
whether the interrupt request is accepted by the CPU.
However, during execution of interrupt processing by the CPU, if the interrupt request flag for the interrupt
is cleared and no other interrupt requests have been issued, switching to standby mode can be done.
● Release of standby mode caused by an interrupt
If an interrupt request higher than level 7 is issued from a peripheral function during the sleep, time-base
timer, or stop modes, the standby mode is released. This action does not depend on whether the CPU
accepts that interrupt.
After the release of standby mode, normal interrupt processing is performed. The CPU branches to the
interrupt handling routine provided that the priority of the interrupt request indicated by the interrupt level
setting bits (IL2, IL1 and IL0 of ICR) is higher than the interrupt level mask register (ILM); and the
interrupt enable flag (I) of the condition code register (CCR) is set to "1" (enabled). If the interrupt is not
accepted, the CPU starts the execution with the instruction that follows the instruction in which switching
to standby mode was specified.
When interrupt processing is executed normally, the CPU first executes the instruction that follows the
instruction in which switching to standby mode was specified. The CPU then proceeds to interrupt
processing. Depending on the condition when switching to standby mode was performed, however, the
CPU may proceed to interrupt processing before executing the next instruction.
If the CPU should not branch to the interrupt processing routine immediately on return to normal mode
from standby mode, action must be taken to disable interrupts before standby mode is set.
● Setting of standby mode
When "1" is written to the STP bit and SLP bit of LPMCR at the same time, switching to standby mode is
performed. If the MCS bit of the clock selection register (CKSCR) is "0", switching to time-base timer
mode is performed; if this bit is "1", switching to stop mode is performed.
110
CHAPTER 6 LOW POWER CONSUMPTION MODE
■ Release of Stop Mode
To use an external interrupt for releasing stop mode, use an input that has been set as an interrupt input
cause before the system enters stop mode. As an input cause, H level, L level, rising edge or falling edge
can be selected.
■ Release of Time-base Timer Mode
When time-base timer mode is released, the microcontroller is placed in the PLL clock oscillation
stabilization wait state. If the PLL clock is not used, change the MCS bit of the clock selection register
(CKSCR) to "1" with the instruction that is to be executed immediately after a reset or on return from an
interrupt.
If an external interrupt is used to release time-base timer mode, the input cause can be selected as H level,
L level, rising edge or falling edge.
■ Oscillation Stabilization Wait Interval
● Source clock oscillation stabilization wait interval
Because the oscillator for source oscillation is halted in stop mode, an oscillation stabilization wait interval
is required. A time period selected by the WS1 and WS0 bits of CKSCR is used as the oscillation
stabilization wait interval.
● PLL clock oscillation stabilization wait interval
The CPU may be working with the main clock and the PLL clock may be stopped. If the microcontroller
will enter a mode in which the CPU and peripheral functions work with the PLL clock, the PLL clock
initially enters the oscillation stabilization wait state. In this state, the CPU still operates using the main
clock.
The PLL clock oscillation stabilization wait interval is fixed at 214/HCLK (HCLK: oscillation clock
frequency).
However, this interval may range from 214/HCLK to 2 x 214/HCLK depending on the status of the timebase timer, if the time-base timer is not cleared before the PLL clock oscillation stabilization wait state is
entered. (For example, return to the PLL run state from time-base timer mode occurs because of an
external reset.)
■ Switching the Clock Mode
When the clock mode is switched, do not switch to low power consumption mode and other clock mode
before this switching is completed. Confirm the completion of clock mode switching by referring to the
MCM and SCM bits of the clock selection register (CKSCR). If the mode is switched to another clock
mode or low-power-consumption mode before completion of switching, the mode may not be switched.
111
CHAPTER 6 LOW POWER CONSUMPTION MODE
112
CHAPTER 7
INTERRUPT
This chapter explains the interrupt and extended
intelligent I/O service (EI2OS) in the MB90460/465 series.
7.1 Interrupt
7.2 Interrupt Causes and Interrupt Vectors
7.3 Interrupt Control Registers and Peripheral Functions
7.4 Hardware Interrupt
7.5 Software Interrupt
7.6 Interrupt of Extended Intelligent I/O Service (EI2OS)
7.7 Exception Processing Interrupt
7.8 Stack Operations for Interrupt Processing
7.9 Sample Programs for Interrupt Processing
113
CHAPTER 7 INTERRUPT
7.1
Interrupt
This chapter explains the interrupt and extended intelligent I/O service (EI2OS) in the
MB90460/465 series.
• Hardware interrupt
• Software interrupt
• Interrupt from extended intelligent I/O service (EI2OS)
• Exception processing
■ Interrupt Types and Functions
● Hardware interrupt
A hardware interrupt transfers control to a user-defined interrupt processing program in response to an
interrupt request from a peripheral function.
● Software interrupt
A software interrupt transfers control to a user-defined interrupt processing program triggered by the
execution of a dedicated software interrupt instruction (such as the INT instruction).
● Interrupt from extended intelligent I/O service (EI2OS)
The EI2OS function automatically transfers data between a peripheral function and memory. Data transfer,
which has ordinarily been executed by an interrupt processing program, can be handled like a direct
memory access (DMA). When the specified number of data transfers has been terminated, the interrupt
processing program is automatically executed.
An instruction from EI2OS is a type of hardware interrupt.
● Exception processingException processing is basically the same as an interrupt. When an exception
event (execution of an undefined instruction) is detected on the instruction boundary, ordinary
processing is interrupted and exception processing is performed. This is equivalent to software
interrupt instruction INT10.
114
CHAPTER 7 INTERRUPT
■ Interrupt Operation
Figure 7.1-1 shows the activation and return processing for the four types of interrupt functions.
Figure 7.1-1 Overall Flow of Interrupt Operation
Main program
Is there
a valid hardware
interrupt
request?
String type *
instruction being
executed
Interrupt activation/return
processing
EI2OS?
Fetch the next instruction and decode
INT instruction?
EI2OS
EI²OS processing
Software
interrupt/
exception
processing
Save the dedicated
register on the system
stack
Disable acceptance of
hardware interrupts
(I = 0)
Hardware
Interrupt
Specified
count terminated?
Alternatively, is there
an end request from the
peripheral
function?
Save the dedicated
register on the system
stack
Update the CPU interrupt processing level
(ILM)
RETI instruction?
Execute ordinary
instruction
Return
processing
Return the dedicated
register from the system
stack, call the interrupt
routine, and return to
the previous routine
Read the interrupt
vector, update PC and
PCB, and branch to
the interrupt routine
Repetition
of string type* instruction
completed?
Move the pointer to the
next instruction by PC
update
*: When a string type instruction is being executed, the interrupt is evaluated in each step.
115
CHAPTER 7 INTERRUPT
7.2
Interrupt Causes and Interrupt Vectors
The F2MC-16LX has functions for handling 256 types of interrupt causes. The 256
interrupt vector tables are allocated to the memory at the highest addresses. These
interrupt vectors are shared by all interrupts.
Software interrupt can use all these interrupt vectors (INT0 to INT256). Software
interrupt shares same interrupt vectors with the hardware interrupt and exception
processing interrupt. Hardware interrupt uses a fixed interrupt vector and interrupt
control register (ICR) for each peripheral function.
■ Interrupt Vectors
Interrupt vector tables referenced during interrupt processing are allocated to the highest addresses in the
memory area (FFFC00H to FFFFFFH). Interrupt vectors share the same area with EI2OS, exception
processing, hardware and software interrupt.
Table 7.2-1 shows the assignment of interrupt numbers and interrupt vectors.
Table 7.2-1 Interrupt Vectors
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Interrupt
no.
Mode data
Hardware interrupt
INT0
FFFFFCH
FFFFFDH
FFFFFEH
Not used
#0
None
:
:
:
:
:
:
:
INT7
FFFFE0H
FFFFE1H
FFFFE2H
Not used
#7
None
INT8
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
#8
(RESET vector)
INT9
FFFFD8H
FFFFD9H
FFFFDAH
Not used
#9
None
INT10
FFFFD4H
FFFFD5H
FFFFD6H
Not used
#10
<Exception processing>
INT11
FFFFD0H
FFFFD1H
FFFFD2H
Not used
#11
Hardware interrupt #0
INT12
FFFFCCH
FFFFCDH
FFFFCEH
Not used
#12
Hardware interrupt #1
INT13
FFFFC8H
FFFFC9H
FFFFCAH
Not used
#13
Hardware interrupt #2
INT14
FFFFC4H
FFFFC5H
FFFFC6H
Not used
#14
Hardware interrupt #3
:
:
:
:
:
:
:
INT254
FFFC04H
FFFC05H
FFFC06H
Not used
#254
None
INT255
FFFC00H
FFFC01H
FFFC02H
Not used
#255
None
(Reference)
Unused interrupt vectors should be set as the exception processing address.
116
CHAPTER 7 INTERRUPT
■ Interrupt Causes and Interrupt Vectors/interrupt Control Registers
Table 7.2-2 shows the relationship among interrupt causes (excluding software interrupt), interrupt vectors,
and interrupt control registers.
Table 7.2-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers
Interrupt cause
Reset
Interrupt vector
EI2OS
support
X
Priority *2
Number
Address
ICR
Address
#08
08H
FFFFDCH
-
-
FFFFD8H
-
-
FFFFD4H
-
-
ICR00
0000B0H*1
ICR01
0000B1H*1
ICR02
0000B2H*1
ICR03
0000B3H*1
ICR04
0000B4H*1
ICR05
0000B5H*1
ICR06
0000B6H*1
ICR07
0000B7H*1
ICR08
0000B8H*1
ICR09
0000B9H*1
ICR10
0000BAH*1
ICR11
0000BBH*1
ICR12
0000BCH*1
ICR13
0000BDH*1
ICR14
0000BEH*1
ICR15
0000BFH*1
INT9 instruction
X
#09
09H
Exception processing
X
#10
0AH
A/D converter conversion termination
O
#11
0BH
FFFFD0H
Output compare channel 0 match
O
#12
0CH
FFFFCCH
End of measurement by PWC0 timer / PWC0 timer overflow*
O
#13
0DH
FFFFC8H
16-bit PPG timer 0
O
#14
0EH
FFFFC4H
Output compare channel 1 match
O
#15
0FH
FFFFC0H
16-bit PPG timer 1*
O
#16
10H
FFFFBCH
Output compare channel 2 match
O
#17
11H
FFFFB8H
16-bit reload timer 1 underflow
O
#18
12H
FFFFB4H
Output compare channel 3 match
O
#19
13H
FFFFB0H
DTP/ext. interrupt channels 0/1 detection
O
#20
14H
FFFFACH
#21
15H
FFFFA8H
#22
16H
FFFFA4H
DTTI0
∆
Output compare channel 4 match
O
DTP/ext. interrupt channels 2/3 detection
O
DTTI1*
∆
Output compare channel 5 match
O
#23
17H
FFFFA0H
End of measurement by PWC1 timer / PWC1 timer overflow
O
#24
18H
FFFF9CH
DTP/ext. interrupt channels 4/5 detection
O
#25
19H
FFFF98H
Waveform sequencer timer compare match / write timing*
O
#26
1AH
FFFF94H
DTP/ext. interrupt channels 6/7 detection
O
#27
1BH
FFFF90H
Waveform sequencer position detect / compare interrupt*
O
#28
1CH
FFFF8CH
Waveform generator 16-bit timer 0/1/2 underflow
∆
#29
1DH
FFFF88H
16-bit reload timer 0 underflow
O
#30
1EH
FFFF84H
16-bit free-run timer zero detect
∆
#31
1FH
FFFF80H
16-bit PPG timer 2
O
#32
20H
FFFF7CH
Input capture channels 0/1
O
#33
21H
FFFF78H
16-bit free-run timer compare clear
∆
#34
22H
FFFF74H
Input capture channels 2/3
O
#35
23H
FFFF70H
Time-base timer
∆
#36
24H
FFFF6CH
#37
25H
FFFF68H
#38
26H
FFFF64H
UART1 receive
UART1 send
∆
#39
27H
FFFF60H
UART0 send
∆
#40
28H
FFFF5CH
Flash memory status
∆
#41
29H
FFFF58H
Delayed interrupt generator module
∆
#42
2AH
FFFF54H
UART0 receive
Interrupt control register
High
Low
117
CHAPTER 7 INTERRUPT
O:Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal.
X:Cannot be used.
:Can be used and support the EI2OS stop request.
∆:Usable when an interrupt cause that shares the ICR is not used.
*1:- For peripheral functions that share the ICR register, the interrupt level will be the same.
- If the extended intelligent I/O service is to be used with a peripheral function that shares the ICR
register with another peripheral function, the service can be started by either of the function. And if
EI2OS clear is supported, both interrupt request flags for the two interrupt causes are cleared by
EI2OS interrupt clear signal. It is recommended to mask either of the interrupt request during the
use of EI2OS.
- EI2OS service cannot be started multiple times simultaneously. Interrupt other than the operating
interrupt is masked during EI2OS operation. It is recommended to mask either of the interrupt
requests during the use of EI2OS.
*2:This priority is applied when interrupts of the same level occur simultaneously.
*:In MB90465 series, these resources are not present, and therefore the interrupts are not available.
118
CHAPTER 7 INTERRUPT
7.3
Interrupt Control Registers and Peripheral Functions
Interrupt control registers (ICR00 to ICR15) are located inside the interrupt controller.
The interrupt control registers correspond to all peripheral functions that have the
interrupt function. These registers control interrupts and the extended intelligent I/O
service (EI2OS).
■ Interrupt Control Registers
Table 7.3-1 lists the interrupt control registers and corresponding peripheral functions.
Table 7.3-1 Interrupt Control Registers
Address
Register
Abbreviation
0000B0H
Interrupt control register 00
ICR00
A/D converter, output compare 0
0000B1H
Interrupt control register 01
ICR01
PWC 0*, 16-bit PPG timer 0
0000B2H
Interrupt control register 02
ICR02
Output compare 1, 16-bit PPG timer 1*
0000B3H
Interrupt control register 03
ICR03
Output compare 2, 16-bit reload timer 1
0000B4H
Interrupt control register 04
ICR04
Output compare 3, DTP/external interrupt 0/1, DTTI0
0000B5H
Interrupt control register 05
ICR05
Output compare 4, DTP/external interrupt 2/3, DTTI1*
0000B6H
Interrupt control register 06
ICR06
Output compare 5, PWC timer 1
0000B7H
Interrupt control register 07
ICR07
DTP/external interrupt 4/5, waveform sequencer*
0000B8H
Interrupt control register 08
ICR08
DTP/external interrupt 6/7, waveform sequencer*
0000B9H
Interrupt control register 09
ICR09
Waveform generator, 16-bit reload timer 0
0000BAH
Interrupt control register 10
ICR10
16-bit free-run timer zero detect, 16-bit PPG timer 2
0000BBH
Interrupt control register 11
ICR11
Input capture 0/1, 16-bit free-run timer compare clear
0000BCH
Interrupt control register 12
ICR12
Input capture 2/3, time-base timer
0000BDH
Interrupt control register 13
ICR13
UART1
0000BEH
Interrupt control register 14
ICR14
UART0
0000BFH
Interrupt control register 15
ICR15
Flash memory, delayed interrupt generator module
*:
Corresponding peripheral function
In MB90465 series, these resources are not present, therefore, interrupt is not available.
119
CHAPTER 7 INTERRUPT
■ Interrupt Control Register Functions
All interrupt control registers (ICR) do the following
• Set the interrupt level of the corresponding peripheral function
• Select ordinary interrupt or the extended intelligent I/O service as interrupt of the corresponding
peripheral function
• Select an extended intelligent I/O service (EI2OS) channel
• Display the status of the extended intelligent I/O service (EI2OS)
Some of the functions of the interrupt control registers (ICR) differ during writing and reading, as shown in
Figure 7.3-1 and Figure 7.3-2.
Note:
120
Do not use a read-modify-write instruction to access the interrupt control registers (ICR), since
operation will not be correct.
CHAPTER 7 INTERRUPT
7.3.1
Interrupt Control Registers (ICR00 to ICR15)
Interrupt control registers correspond to all peripheral functions that have the interrupt
function. The interrupt control registers control the processing when an interrupt
request occurs. The functions of these registers partially differ at writing and reading.
■ Interrupt Control Registers (ICR00 to ICR15)
Figure 7.3-1 Interrupt Control Registers (ICR00 to ICR15) during writing
Writing
bit
Address
0000B0H
to
0000BFH
7
6
5
4
3
2
1
0
ICS3
ICS2
ICS1
ICS0
ISE
IL2
IL1
IL0
W
W
W
R/W
R/W
R/W
R/W
W
Initial value
00000111B
IL1
IL0
Interrupt level setting bit
0
0
0
Interrupt level 0 (highest)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
IL2
Interrupt level 7 (no interrupt)
EI2OS enable bit
ISE
0
Activates the interrupt sequence when an interrupt occurs
1
Activates EI2OS when an interrupt occurs
EI2OS channel selection bit
ICS3 ICS2 ICS1 ICS0
R/W:
W:
Read/write
Write-only
: Initial value
Channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
121
CHAPTER 7 INTERRUPT
Figure 7.3-2 Interrupt Control Registers (ICR00 to ICR15) during reading
Reading
bit
Address
0000B0H
to
0000BFH
7
6
5
4
3
2
1
0
-
-
S1
S0
ISE
IL2
IL1
IL0
R
R
R/W
R/W
R/W
R/W
IL2
Initial value
XX000111B
IL1
IL0
Interrupt level setting bit
0
0
0
Interrupt level 0 (highest)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
EI2OS enable bit
ISE
0
Activates the interrupt sequence when an interrupt occurs
1
Activates EI2OS when an interrupt occurs
S0
EI2OS status
0
0
EI2OS operation in progress or EI2OS not activated
0
1
Stopped status due to count termination
1
0
Reserved
1
1
Stopped status due to a request from the peripheral function
S1
R/W: Read/write
R: Write-only
- : Not used
X:
Undefined
: Initial value
122
Interrupt level 7 (no interrupt)
CHAPTER 7 INTERRUPT
7.3.2
Interrupt Control Register Functions
The interrupt control registers (ICR00 to ICR15) consist of the following four functional
bits:
• Interrupt level setting bits (IL2 to IL0)
• Extended intelligent I/O service (EI2OS) enable bit (ISE)
• Extended intelligent I/O service (EI2OS) channel selection bits (ICS3 to ICS0)
• Extended intelligent I/O service (EI2OS) status (S1 and S0)
■ Configuration of Interrupt Control Registers (ICR)
Figure 7.3-3 shows the configuration of the interrupt control register (ICR) bits.
Figure 7.3-3 Configuration of Interrupt Control Registers (ICR)
Writing to interrupt control register (ICR)
Address
0000B0H
to
0000BFH
Reading of interrupt control register (ICR)
Address
0000B0H
to
0000BFH
Initial value
Initial value
R: Read-only
W: Write-only
- : Not used
References:
• The ICS3 to ICS0 bits are valid only when the extended intelligent I/O service (EI2OS) has been
activated. To activate EI2OS, set the ISE bit to "1". To not activate EI2OS, set the ISE bit to "0".
When EI2OS is not activated, setting ICS3 to ICS0 is optional.
• ICS1 and ICS0 are valid only for writing. S1 and S0 are valid only for reading.
■ Interrupt Control Register Functions
● Interrupt level setting bits (IL2 to IL0)
These bits set the interrupt level of the corresponding peripheral function. These bits are initialized to level
7 (no interrupt) by a reset.
Table 7.3-2 shows the correspondence between the interrupt level setting bits and interrupt levels.
123
CHAPTER 7 INTERRUPT
Table 7.3-2 Correspondence between the Interrupt Level Setting Bits and Interrupt Levels
IL2
IL1
IL0
Interrupt level
0
0
0
0 (highest priority)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
6 (lowest priority)
1
1
1
7 (no interrupt)
● Extended intelligent I/O service (EI2OS) enable bit (ISE)
If this bit is "1" when an interrupt request is generated, EI2OS is activated. If this bit is "0" at when an
interrupt request is generated, the interrupt sequence is activated. When the EI2OS termination condition is
met (when the S1 and S0 bits are not 00B), the ISE bit is cleared. If the corresponding peripheral function
does not have the EI2OS function, the ISE bit must be set to "0" by software. The ISE bit is initialized to
"0" by a reset.
● Extended intelligent I/O service (EI2OS) channel selection bits (ICS3 to ICS0)
These write-only bits specify the EI2OS channel. The EI2OS descriptor address is determined based on the
value set here. The ICS bit is initialized to 0000B by a reset.
Table 7.3-3 shows the correspondence between the EI2OS channel selection bits and descriptor addresses.
Table 7.3-3 Correspondence between the EI2OS Channel Selection Bits and Eescriptor
Addresses (1 / 2)
124
ICS3
ICS2
ICS1
ICS0
Selected channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
CHAPTER 7 INTERRUPT
Table 7.3-3 Correspondence between the EI2OS Channel Selection Bits and Eescriptor
Addresses (2 / 2)
ICS3
ICS2
ICS1
ICS0
Selected channel
Descriptor address
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
● Extended intelligent I/O service (EI2OS) status bits (S1, S0)
These are read-only bits. When this value is checked at EI2OS termination, the operating status and
termination status can be distinguished. These bits are initialized to 00B by a reset.
Table 7.3-4 shows the relationship between the S0 and S1 bits and the EI2OS status.
Table 7.3-4 Relationship between EI2OS Status Bits and the EI2OS Status
S1
S0
0
0
EI2OS operation in progress or EI2OS not activated
0
1
Stopped status due to count termination
1
0
Reserved
1
1
Stopped status due to a request from the peripheral function
EI2OS status
125
CHAPTER 7 INTERRUPT
7.4
Hardware Interrupt
The hardware interrupt function temporarily interrupts the program being executed by
the CPU and transfers control to a user-defined interrupt processing program in
response to an interrupt signal from a peripheral function.
The extended intelligent I/O service (EI2OS) and external interrupt are executed as a
type of hardware interrupt.
■ Hardware Interrupt
● Hardware interrupt function
The hardware interrupt function compares the interrupt level of the interrupt request signal output by a
peripheral function with the interrupt level mask register (ILM) in the CPU processor status (PS). The
function then references the contents of the I flag in the processor status (PS) through the hardware and
decides if the interrupt can be accepted.
When the hardware interrupt is accepted, the CPU internal registers are automatically saved on the system
stack. The currently requested interrupt level is stored in the interrupt level mask register (ILM), and the
function branches to the corresponding interrupt vector.
● Multiple interrupts
Multiple hardware interrupts can be activated.
● Extended intelligent I/O service (EI2OS)
EI2OS is an automatic transfer function between memory and I/O. When the specified transfer count has
been completed, a hardware interrupt is activated. Multiple EI2OS activation does not occur. During
EI2OS processing, all other interrupt requests and EI2OS requests are held.
● External interrupt
An external interrupt (including wake-up interrupt) is accepted from a peripheral function (interrupt request
detection circuit) as a hardware interrupt.
● Interrupt vector
Interrupt vector tables referenced during interrupt processing are allocated to memory at FFFC00H to
FFFFFFH. These tables are shared by software interrupts.
See "7.2 Interrupt Causes and Interrupt Vectors", for more information about the allocation of interrupt
numbers and interrupt vectors.
126
CHAPTER 7 INTERRUPT
■ Hardware Interrupt Structure
Table 7.4-1 lists four mechanisms used for hardware interrupt. These four mechanisms must be included in
the program before hardware interrupt can be used.
Table 7.4-1 Mechanisms used for Hardware Interrupt
Mechanism
Function
Peripheral function
Interrupt enable bit, interrupt
request bit
Controls interrupt requests from a peripheral
function
Interrupt controller
Interrupt control register (ICR)
Sets the interrupt level and controls EI2OS
Interrupt enable flag (I)
Identifies the interrupt enable status
Interrupt level mask register
(ILM)
Compares the request interrupt level and
current interrupt level
Microcode
Executes the interrupt processing routine
Interrupt vector table
Stores the branch destination address for
interrupt processing
CPU
FFFC00H to
FFFFFFH in memory
These four mechanisms must be included in the program before hardware interrupt can be used.
■ Hardware Interrupt Suppression
Acceptance of hardware interrupt requests is suppressed under the following conditions.
● Hardware interrupt suppression during writing to the peripheral function control register area
When data is being written to the peripheral function control register area, hardware interrupt requests are
not accepted. This prevents the CPU from making operational mistakes. The mistakes may be caused if an
interrupt request is generated during data is written to the interrupt control registers for a resource. The
peripheral function control register area is not the I/O addressing area at 000000H to 0000FFH, but the area
allocated to the control register of the peripheral function control register and data register.
Figure 7.4-1 shows hardware interrupt operation during writing to the built-in resource area.
Figure 7.4-1 Hardware Interrupt Request while writing to the Peripheral Function Control Register Area
Instruction that writes to the peripheral function control register area
MOV A, #08
MOV io, A
An interrupt request
is generated here
MOV A, 2000H
Does not branch
to the interrupt
Interrupt processing
Branches to
the interrupt
127
CHAPTER 7 INTERRUPT
● Hardware interrupt suppression by interrupt suppression instruction
The ten types of hardware interrupt suppression instructions listed in Table 7.4-2 ignore interrupt requests
without detecting whether a hardware interrupt request exists.
Table 7.4-2 Hardware Interrupt Suppression Instruction
Prefix code
Instructions that do not
accept interrupt and hold
requests
PCB
DTB
ADB
SPB
CMR
NCC
Interrupt/hold suppression instructions
(instructions that delay the effect of the prefix code)
MOV
OR
AND
POPW
ILM, #imm8
CCR, #imm8
CCR, #imm8
PS
Even if a valid hardware interrupt request is generated during execution of one of these instructions, the
interrupt is not processed until the first time an instruction of a different type is executed.
● Hardware interrupt suppression during execution of software interrupt
When a software interrupt is activated, the I flag is cleared to "0". In this state, other interrupt requests
cannot be accepted.
128
CHAPTER 7 INTERRUPT
7.4.1
Operation of Hardware Interrupt
This section explains hardware interrupt operation from generation of a hardware
interrupt request to the completion of interrupt processing.
■ Hardware Interrupt Activation
● Peripheral function operation (generation of an interrupt request)
A peripheral function that has a hardware interrupt request function also has an interrupt request flag that
indicates the presence of interrupt requests and an interrupt enable flag that determines whether CPU
interrupt requests are enabled or disabled. The interrupt request flag is set when an event specific to the
peripheral function occurs.
● Interrupt controller operation (interrupt request control)
The interrupt controller compares the interrupt levels (IL) of interrupt requests received at the same time.
The interrupt controller selects the request with the highest level (with the smallest IL value) and posts it to
the CPU. When multiple requests have the same level, the request with the smallest interrupt number has
the highest priority.
● CPU operation (interrupt request acceptance and interrupt processing)
The CPU compares the received interrupt level (ICR: IL2 to IL0) and the interrupt level mask register
(ILM). If IL < ILM and interrupts are enabled (PS: CCR: I = 1), the CPU activates the interrupt
processing microcode after the instruction currently being executed terminates.
At the beginning of the interrupt processing microcode, the CPU references the ISE bit in the interrupt
control register (ICR). If ISE = 0, the CPU continues the execution of interrupt processing. (If ISE = 1,
EI2OS is activated.)
Interrupt processing saves the contents of the dedicated registers (12 bytes including A, DPR, ADB, DTB,
PCB, PC and PS) on the system stack (the system stack space indicated by the SSB and SSP).
The CPU then loads data into the interrupt vector program counters (PCB and PC), updates the ILM, and
sets the stack flag (S) (sets CCR: S = 1 and activates the system stack).
■ Returning from a Hardware Interrupt
In an interrupt processing program, when the interrupt request flag of the peripheral function that generated
the interrupt cause is cleared and the RETI instruction is executed, 12-byte data saved on the system stack
is restored to the dedicated registers and the processing that was being executed before branching for the
interrupt is resumed.
When the interrupt request flag is cleared, interrupt requests output by the peripheral function to the
interrupt controller are automatically canceled.
129
CHAPTER 7 INTERRUPT
■ Hardware Interrupt Operation
Figure 7.4-2 shows hardware interrupt operation from generation of a hardware interrupt to the completion
of interrupt processing.
Figure 7.4-2 Hardware Interrupt Operation
Internal bus
Microcode
Check
Comparator
X
Other peripheral
functions
Peripheral function that generated
the interrupt request
Enable FF
Level
comparator
Interrupt
level IL
Factor FF
Interrupt controller
IL:
PS:
I:
ILM:
IR:
FF:
Interrupt level setting bit in the interrupt control register (ICR)
Processor status
Interrupt enable flag
Interrupt level mask register
Instruction register
Flip-flop
(1) An interrupt cause is generated within the peripheral function.
(2) The interrupt enable bit of the peripheral function is referenced. If the interrupt is enabled, the
interrupt request is output from the peripheral function to the interrupt controller.
(3) The interrupt controller that receives the interrupt request determines the priority of simultaneous
interrupt requests, then transfers the interrupt level (IL) that matches the corresponding interrupt
request to the CPU.
(4) The CPU compares the interrupt level (IL) requested by the interrupt controller with the interrupt level
mask register (ILM).
(5) If the comparison indicates a higher priority than the current interrupt processing level, the CPU checks
the contents of the I flag in the condition code register (CCR).
(6) If in the check in (5) the I flag is interrupt enabled (I = 1), the CPU waits until the execution of the
instruction currently being executed terminates. At termination, the CPU sets the requested level (IL)
in the ILM.
(7) Registers are saved, and processing branches to the interrupt processing routine.
(8) The interrupt cause that was generated in (1) is cleared by software in the interrupt processing routine.
Execution of the RETI instruction terminates the interrupt processing.
130
CHAPTER 7 INTERRUPT
7.4.2
Processing for Interrupt Operation
When an interrupt request is generated by the peripheral function, the interrupt
controller transmits the interrupt level to the CPU. If the CPU is able to accept interrupt,
the interrupt controller temporarily interrupts the instruction currently being executed.
The interrupt controller then executes the interrupt processing routine or activates the
extended intelligent I/O service (EI2OS).
If a software interrupt is generated by the INT instruction, the interrupt processing
routine is executed regardless of the CPU status. In this case, hardware interrupt is not
allowed.
■ Processing for Interrupt Operation
Figure 7.4-3 shows the flow of processing for interrupt operation.
Figure 7.4-3 Flow of Interrupt Processing
START
Main program
YES
String type*
instruction in
progress
I&IF&IF=1
AND
LM>IL
Interrupt activation/return processing
YES
ISE = 1
Fetch the next instruction
and deode
YES
EI2OS
NO
EI2OS processing
Software interrupt/exception
processing
INT
instruction?
NO
Save the dedicated registers
to the system stack
I <- 0 (Disable hardware
interrupts)
Hardware
instruction
YES
Specified
count terminated? Alternatively, is there a termination
request from the peripheral
function?
Save the dedicated
registers to the system stack
NO
ILM <- IL (Transfer the
interrupt level of the accepted
interrupt request to the ILM)
RETI
instruction?
YES
NO
Execute ordinary instruction
(including interrupt processing)
NO
Return
processing
Return the dedicated
registers from the system
stack, call the interrupt
routine, and return to the
previous routine
S <- 1 (Activates the
system stack)
PCB, PC <- interrupt
vector (Branch to the
interrupt processing routine)
Repetition
of string type* instruction
completed?
YES
Move the pointer to the next
instruction by PC update
*: When a string type instruction is being executed, the interrupt is evaluated in each step.
I:
Interrupt enable flag of the condition code register (CCR)
S:
Stack flag of the condition code register (CCR)
IF:
Interrupt request flag of the peripheral function
PCB: Program bank register
IE:
Interrupt enable flag of the peripheral function
PC: Program counter:
ILM: Interrupt level mask register (in the PS)
ISE: EI²OS enbale flag ofthe interruptor control register (ICR)
IL:
Interrupt level setting bit of the interrupt control register (ICR)
131
CHAPTER 7 INTERRUPT
7.4.3
Procedure for using Hardware Interrupt
Before hardware interrupt can be used, the system stack area, peripheral function, and
interrupt control register (ICR) must be set.
■ Procedure for using Hardware Interrupt
Figure 7.4-4 shows an example of the procedure for using hardware interrupt.
Figure 7.4-4 Procedure for using Hardware Interrupt
Start
(1)
Set the system stack area
(2)
Initialize the peripheral function
(3)
Set the ICR in the interrupt
controller
Interrupt processing program
Stack processing branches to
the interrupt vector
(8) Processing for interrupt to the
peripheral function (execute the
interrupt processing routine)
(7)
(4)
(5)
Set operation start for the
peripheral function. Set the
interrupt enable bit to enable
Hardware
processing
Set the ILM and I in the PS
(9)
Clear the interrupt cause
(10)
Interrupt return instruction
(RETI)
Main program
(6)
Interrupt request
generated
Main program
(1) Set the system stack area.
(2) Initialize a peripheral function that can generate interrupt requests.
(3) Set the interrupt control register (ICR) in the interrupt controller.
(4) Set the peripheral function to the operation start status, and set the interrupt enable bit to enable.
(5) Set the interrupt level mask register (ILM) and interrupt enable flag (I) to interrupt acceptable.
(6) An interrupt generated in the peripheral function causes a hardware interrupt request.
(7) The interrupt processing hardware saves the registers and branches to the interrupt processing program.
(8) The interrupt processing program processes the peripheral function in response to the generated
interrupt.
(9) Clear the peripheral function interrupt request.
(10) Execute the interrupt return instruction, and return to the program before branching.
132
CHAPTER 7 INTERRUPT
7.4.4
Multiple Interrupts
Multiple hardware interrupts can be implemented by setting different interrupt levels in
the interrupt level setting bits (IL0, IL1, IL2) of the interrupt control register (ICR) in
response to multiple interrupt requests from peripheral functions. Use of multiple
interrupts, however, is not possible with the extended intelligent I/O service.
■ Multiple Interrupts
● Operation of multiple interrupts
During execution of an interrupt processing routine, if an interrupt request with a higher-priority interrupt
level is generated, the current interrupt processing is interrupted and the interrupt request with the higherpriority interrupt level is accepted. When the interrupt request with the higher-priority interrupt level
terminates, the CPU returns to the previous interrupt processing.
0 to 7 can be set as the interrupt level. If level 7 is set, the CPU does not accept interrupt requests.
During execution of interrupt processing, if an interrupt request with the same or lower-priority interrupt
level is generated, the new interrupt request is held until the current interrupt terminates unless the I flag or
ILM is changed.
Other multiple interrupts to be activated during an interrupt can be temporarily disabled by setting the I flag
in the condition code register (CCR) in the interrupt processing routine to interrupts not allowed (CCR: I =
0) or the interrupt level mask register (ILM) to interrupts not allowed (ILM = 000B).
Note:
The extended intelligent I/O service (EI2OS) cannot be used for the activation of multiple interrupts.
During processing of the extended intelligent I/O service (EI2OS), all other interrupt requests and
extended intelligent I/O service requests are held.
● Example of multiple interrupts
This example of multiple interrupt processing assumes that a timer interrupt is given a higher priority than
an A/D converter interrupt. In this example, the A/D converter interrupt level is set to "2", and the timer
interrupt level is set to "1". If a timer interrupt is generated during processing of the A/D converter
interrupt, the processing shown in Figure 7.4-5 is performed.
133
CHAPTER 7 INTERRUPT
Figure 7.4-5 Example of Multiple Interrupts
Main program
A/D interrupt processing
Interrupt level 2
(ILM = 010)
Interrupt level 1
(ILM = 001)
Peripheral initialization
A/D interrupt generated
Interrupted
Timer interrupt processing
Timer interrupt
generated
Timer interrupt processing
Restart
Main processing restarts
A/D interrupt
processing
Timer interrupt return
A/D interrupt return
(1) A/D interrupt generated
When the A/D converter interrupt processing starts, the interrupt level mask register (ILM)
automatically has the same value (2 in the example) as the A/D converter interrupt level (ICR: IL2 to
IL0).
If a level-1 or level-0 interrupt request is generated, this interrupt processing has priority.
(2) Interrupt processing terminated
When the interrupt processing terminates and the return instruction (RETI) is executed, the values of the
dedicated registers (A, DPR, ADB, DTB, PCB, PC and PS) are returned from the stack, and the interrupt
level mask register (ILM) has the value that it had before the interrupt.
134
CHAPTER 7 INTERRUPT
7.4.5
Hardware Interrupt Processing Time
From the generation of a hardware interrupt request to the execution of an interrupt
processing routine, the time for the instruction currently being executed to terminate
and the time required to handle an interrupt are necessary.
■ Hardware Interrupt Processing Time
From the generation of a hardware interrupt request to the acceptance of the interrupt and to the execution
of an interrupt processing routine, the time to wait for sampling for an interrupt request and the time
required to handle an interrupt (time to prepare for interrupt processing) are necessary. Figure 7.4-6 shows
the interrupt processing time.
Figure 7.4-6 Interrupt Processing Time
CPU operation
Ordinary instruction
execution
Interrupt handling
Interrupt wait time
Interrupt request
sampling wait time
Interrupt handling time
( machine cycle) (*)
Interrupt processing
routine
Interrupt request generation
: The final instruction cycle samples the interrupt request here.
: One machine cycle corresponds to one machine clock ( ).
● Interrupt request sampling wait time
The interrupt request sampling wait time is the time from the generation of and interrupt request to the
termination of the instruction currently being executed.
Whether an interrupt request has been generated is determined by sampling the instruction for an interrupt
request in the final cycle of the instruction. Consequently, the CPU cannot identify an interrupt request
during execution of each instruction creating a delay.
The interrupt request sampling wait time is the maximum when an interrupt request is generated as soon as
the POPW RW0, ... RW7 instruction (45 machine cycles), which takes the longest to execute, starts.
135
CHAPTER 7 INTERRUPT
● Interrupt handling time (φ machine cycle)
The CPU saves dedicated registers to the system stack and fetches interrupt vectors after it receives an
interrupt request. The required handling time for this processing is f machine cycles. The interrupt
handling time is calculated with the following formula:
When an interrupt is activated: θ = 24 + 6 + Z machine cycles
When control is returned from an interrupt: θ = 11 + 6 + Z machine cycles (RETI instruction)
The interrupt handling time is different for each address pointed to by the stack pointer.
Table 7.4-3 shows the interpolation values (Z) for the interrupt handling time.
Table 7.4-3 Interpolation Values (Z) for the Interrupt Handling Time
Address pointed to by the stack pointer
Interpolation value (Z)
External 8-bit
+4
External even-numbered address
+1
External odd-numbered address
+4
Internal even-numbered address
0
Internal odd-numbered address
+2
Reference:
One machine cycle corresponds to one clock cycle of the machine clock (φ).
136
CHAPTER 7 INTERRUPT
7.5
Software Interrupt
When the software interrupt instruction (INT instruction) is executed, the software
interrupt function transfers control from the program being executed by the CPU to the
user-defined interrupt processing program. Hardware interrupt is disabled during
execution of a software interrupt.
■ Software Interrupt Activation
● Software interrupt activation
The INT instruction is used to activate a software interrupt. There is no interrupt request flag or enable flag
for software interrupt requests. When the INT instruction is executed, an interrupt request is always
generated.
● Hardware interrupt suppression
Since the INT instruction does not have interrupt levels, the interrupt level mask register (ILM) is not
updated. During the execution of the INT instruction, the I flag of the condition code register (CCR) is set
to "0", and hardware interrupts are masked.
To enable hardware interrupts during software interrupt processing, set the I flag to "1" in the software
interrupt processing routine.
● Software interrupt operation
When the CPU fetches the INT instruction, the software interrupt processing microcode is activated. This
microcode saves the internal CPU registers on the system stack, masks hardware interrupts (CCR: I = 0),
and branches to the corresponding interrupt vector.
See "7.2 Interrupt Causes and Interrupt Vectors", in Chapter 7 for more information about the allocation of
interrupt numbers and interrupt vectors.
■ Returning from a Software Interrupt
In the interrupt processing program, when the interrupt return instruction (RETI instruction) is executed,
the 12-byte data saved to the system stack is restored to the dedicated registers and the processing that was
being executed before branching for the interrupt is resumed.
137
CHAPTER 7 INTERRUPT
■ Software Interrupt Operation
Figure 7.5-1 shows software interrupt operation from the generation of a software interrupt to the
completion of interrupt processing.
Figure 7.5-1 Software Interrupt Operation
(1)
PS
Register file
(2)
Microcode
I
S
B unit
IR
Queue
F2 MC-16LX CPU
(3)
Save
Instruction bus
F2MC-16LX bus
PS :
I
:
S
:
IR
:
B unit:
Fetch
RAM
Processor status
Interrupt enable flag
Stack flag
Instruction register
Bus interface unit
(1) A software interrupt instruction is executed.
(2) The dedicated registers are saved according to the microcode that corresponds to the software
interrupt instruction, and other necessary processing is performed. Branch processing is then executed.
(3) The RETI instruction in the user interrupt processing routine terminates the interrupt processing.
Note:
138
When the program bank register (PCB) is FFH, the vector area of the CALLV instruction overlaps the
INT #vct8 instruction table. When creating the software, be careful of the duplicated address of the
CALLV instruction and INT #vct8 instruction.
CHAPTER 7 INTERRUPT
7.6
Interrupt of Extended Intelligent I/O Service (EI2OS)
The extended intelligent I/O service (EI2OS) automatically transfers data between a
peripheral function (I/O) and memory. When the data transfer terminates, a hardware
interrupt is generated.
■ Extended Intelligent I/O Service (EI2OS)
The extended intelligent I/O service is a type of hardware interrupt. It automatically transfers data between
a peripheral function (I/O) and a memory. Traditionally, data transfer with a peripheral function (I/O) has
been performed by the interrupt processing program. EI2OS performs this data transfer in the same way as
direct memory access (DMA). At termination, EI2OS sets the termination condition and automatically
branches to the interrupt processing routine. The user creates programs only for EI2OS activation and
termination. Data transfer programs in between are not required.
● Advantages of extended intelligent I/O service (EI2OS)
Compared to data transfer performed by the interrupt processing routine, EI2OS has the following
advantages.
• Coding a transfer program is not necessary, reducing program size.
• Because transfer can be stopped depending on the peripheral function (I/O) status, unnecessary data
transfer can be eliminated.
• Incrementing or no update can be selected for the buffer address.
• Incrementing or no update can be selected for the I/O register address.
● Extended intelligent I/O service (EI2OS) termination interrupt
When data transfer by EI2OS terminates, a termination condition is set in the S1 and S0 bits in the interrupt
control register (ICR). Processing then automatically branches to the interrupt processing routine.
The EI2OS termination factor can be determined by checking the EI2OS status (ICR: S1, S0) with the
interrupt processing program.
Interrupt numbers and interrupt vectors are permanently set for each peripheral. See "7.2 Interrupt Causes
and Interrupt Vectors", in Chapter 7 for more information.
● Interrupt control register (ICR)
This register, which is located in the interrupt controller, activates EI2OS, specifies the EI2OS channel, and
displays the EI2OS termination status.
● Extended intelligent I/O service (EI2OS) descriptor (ISD)
This descriptor, which is located in RAM at 000100H to 00017FH, is an eight-byte data that retains the
transfer mode, I/O address, transfer count, and buffer address. The descriptor handles 16 channels. The
channel is specified by the interrupt control register (ICR).
139
CHAPTER 7 INTERRUPT
Note:
When the extended intelligent I/O service (EI2OS) is operating, execution of the CPU program stops.
■ Operation of the Extended Intelligent I/O Service (EI2OS)
Figure 7.6-1 shows EI2OS operation.
Figure 7.6-1 Extended Intelligent I/O Service (EI2OS) Operation
Memory space
by IOA
I/O register
2
F MC-16LX
CPU
••• ••• ••• ••• •••
Peripheral
function (I/O)
(5)
Interrupt request (1)
I/O register
(3)
ISD
by ICS
(2)
(3)
Interrupt control register (ICR)
Interrupt controller
by BAP
(4)
Buffer
ISD:
IOA:
BAP:
ICS:
DCT:
by
DCT
EI2OS descriptor
I/O address pointer
Buffer address pointer
EI2OS channel selection bit in ICR
Data counter
(1) I/O requests transfer.
(2) The interrupt controller selects the descriptor.
(3) The transfer source and transfer destination are read from the descriptor.
(4) Transfer is performed between I/O and memory.
(5) The interrupt cause is automatically cleared.
140
CHAPTER 7 INTERRUPT
7.6.1
Extended Intelligent I/O Service (EI2OS) Descriptor (ISD)
The extended intelligent I/O service (EI2OS) descriptor (ISD) resides in internal RAM at
000100H to 00017FH. The ISD consists of 8 bytes x 16 channels.
■ Configuration of the Extended Intelligent I/O Service (EI2OS) Descriptor (ISD)
The ISD consists of 8 bytes x 16 channels. Each ISD has the structure shown in Figure 7.6-2. Table 7.6-1
shows the correspondence between channel numbers and ISD addresses.
Figure 7.6-2 Configuration of EI2OS Descriptor (ISD)
H
High-order 8 bits of data counter (DCTH)
Low-order 8 bits of data counter (DCTL)
High-order 8 bits of I/O address pointer (IOAH)
Low-order 8 bits of I/O address pointer (IOAL)
EI2OS status register (ISCS)
High-order 8 bits of buffer address pointer (BAPH)
000100H + 8 × ICS
Medium-order 8 bits of buffer address pointer (BAPM)
ISD start address
Low-order 8 bits of buffer address pointer (BAPL)
L
Table 7.6-1 Correspondence between Channel Numbers and Descriptor Addresses
Channel
Descriptor address
0
000100H
1
000108H
2
000110H
3
000118H
4
000120H
5
000128H
6
000130H
7
000138H
8
000140H
9
000148H
10
000150H
11
000158H
12
000160H
13
000168H
14
000170H
15
000178H
Registers of the extended intelligent I/O service (EI2OS) descriptor (ISD)
141
CHAPTER 7 INTERRUPT
7.6.2
Registers of EI2OS Descriptor (ISD)
• Data counter (DCT)
• I/O register address pointer (IOA)
• EI2OS status register (ISCS)
• Buffer address pointer (BAP)
Note: that the initial value of each register is undefined after a reset.
■ Data Counter (DCT)
The DCT is a 16-bit register that serves as a counter for the data transfer count. After each data transfer,
the counter is decremented by "1". When the counter reaches zero, EI2OS terminates.
Figure 7.6-3 shows the configuration of the DCT.
Figure 7.6-3 Configuration of DCT
15
14
13
12
11
10
9
8
B15
B14
B13
B12
B11
B10
B09
B08
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
3
2
1
0
B07
B06
B05
B04
B03
B02
B01
B00
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit
Upper byte of data counter
Initial value
bit
Lower byte of data counter
Initial value
DCTH
DCTL
■ I/O Register Address Pointer (IOA)
The IOA is a 16-bit register that indicates the lower address (A15 to A00) of the I/O register used to
transfer data to and from the buffer. The upper address (A23 to A16) is all zeros. Any I/O from 000000H
to 00FFFFH can be specified by address. Figure 7.6-4 shows the configuration of the IOA.
Figure 7.6-4 Configuration of I/O Register Address Pointer (IOA)
bit
Upper address pointer
Initial value
bit
Lower address pointer
Initial value
142
15
14
13
12
11
10
9
8
A15
A14
A13
A12
A11
A10
A09
A08
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
3
2
1
0
A07
A06
A05
A04
A03
A02
A01
A00
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
IOAH
IOAL
CHAPTER 7 INTERRUPT
■ Extended Intelligent I/O Service (EI2OS) Status Register (ISCS)
The ISCS is an 8-bit register. The ISCS indicates the update/fixed for the buffer address pointer and I/O
register address pointer, transfer data format (byte or word), and transfer direction. Figure 7.6-5 shows the
configuration of the ISCS.
Figure 7.6-5 Configuration of EI2OS Status Register (ISCS)
bit
7
6
5
4
3
2
1
0
Initial value
EI2OS termination control bit
Not terminated by a request from the peripheral function.
Terminated by a request from the peripheral function
Data transfer direction specification bit
I/O register address pointer → buffer address pointer.
Buffer address pointer → I/O register address pointer
BAP update/fixed selection bit
After data transfer, the buffer address pointer is updated. (*1)
After data transfer, the buffer address pointer is not updated.
Transfer data length specification bit
Byte
Word
IOA update/fixed selection bit
After data transfer, the I/O register address pointer is updated. (*2)
After data transfer, the buffer address pointer is not updated.
Reserved bits
0 must be written to these bits.
R/W: Read-write
X:
Undefined
*1 Only the lower 16 bits of the buffer address pointer change. The buffer address pointer
can only be incremented.
*2 The address pointer can only be incremented.
■ Buffer Address Pointer (BAP)
The BAP is a 24-bit register that retains the address used by EI2OS for the next transfer. Since one
independent BAP exists for each EI2OS channel, each EI2OS channel can transfer data between any
address in the 16-megabyte space and the I/O. If the BF bit (BAP update/fixed selection bit in the EI2OS
status register) in the EI2OS status register (ISCS) is set to "update yes", only the lower 16 bits (BAPM,
BAPL) of the BAP change; the upper 8 bits (BAPH) do not change. Figure 7.6-6 shows the configuration
of the BAP.
143
CHAPTER 7 INTERRUPT
Figure 7.6-6 Configuration of Buffer Address Pointer (BAP)
bit 23
BAP
~
16 15
~
BAPH
BAPM
(R/W)
(R/W)
87
~
BAPL
(R/W)
0
Initial value
xxxxxxB
R/W: Read-write
x: Undefined
References:
• The area that can be specified by the I/O address pointer (IOA) extends from 000000H to
00FFFFH.
• The area that can be specified with the buffer address pointer (BAP) extends from 000000H to
FFFFFFH.
• The maximum transfer count that can be specified by the data counter (DCT) is 65,536 (64 Kbytes).
144
CHAPTER 7 INTERRUPT
7.6.3
Operation of the Extended Intelligent I/O Service (EI2OS)
If an interrupt request is generated by a peripheral function, EI2OS activation is set in
the corresponding interrupt control register (ICR) that the CPU uses EI2OS to transfer
data. When the specified data transfer count terminates, the hardware interrupt is
automatically processed.
■ Operation flow of the Extended Intelligent I/O Service (EI2OS)
Figure 7.6-7 shows the flow of EI2OS operation based on the internal microcode of the CPU.
Figure 7.6-7 Flow of Extended Intelligent I/O Service (EI2OS) Operation
Interrupt request generated
by peripheral function
NO
ISE = 1
YES
Interrupt sequence
Read ISD/ISCS
Termination
request from peripheral
function
YES
YES
SE = 1
NO
NO
YES
DIR = 1
NO
Data indicated by IOA
(data transfer)
memory indicated by BAP
Data indicated by BAP
(data transfer)
memory indicated by IOA
YES
IF = 0
NO
Updage value
by BW
Update IOA
Updage value
by BW
Update BAP
YES
BF = 0
NO
Decrement DCT
(-1)
YES
DCT = 00
EI2OS termination processing
NO
Set S1 and S0 to 00
Clear interrupt request from
the peripheral function
Return to CPU operation
ISD:
ISCS:
IF:
BW:
BF:
DIR:
SE:
Set S1 and S0 to 11
Set S1 and S0 to 01
EI²OS descriptor
EI²OS status register
IOA update/fixed selection bit inte EI²OS status register (ISCS)
Transfer data length specification bit in the EI²OS status register (ISCS)
BAP update/fixed selection bit in the EI²OS status register (ISCS)
Data transfer direction specification bit in the EI²OS status register (ISCS)
EI²OS termination control bit in the EI²OS status register (ISCS)
Clear ISE to 0
Interrupt sequence
DCT:
IOA:
BAP:
ISE:
Data counter
I/O register address pointer
Buffer address pointer
EI²OS enable bit in the interrupt control
register
S1, S0: EI²OS status in the interrupt control
register (ICR)
145
CHAPTER 7 INTERRUPT
7.6.4
Procedure for using the Extended Intelligent I/O Service
(EI2OS)
Before the extended intelligent I/O service (EI2OS) an be used, the system stack area,
extended intelligent I/O service (EI2OS) descriptor, interrupt function, and interrupt
control register (ICR) must be set.
■ Procedure for using the Extended Intelligent I/O Service (EI2OS)
Figure 7.6-8 shows the EI2OS software and hardware processing.
Figure 7.6-8 Procedure for using the Extended Intelligent I/O Service (EI2OS)
Software processing
Hardware processing
Start
Set the system stack area
Set the EI2OS descriptor
Initialization
Initialize the peripheral
function
Set the interrupt control
register (ICR)
Set the built-in resource to
start operation. Set the
interrupt enable bit
Set the ILM and I in the PS
(Interrupt request)
and (ISE = 1)
Execute the user program
S1, S0 = 00
Transfer data
(Branch to interrupt vector)
Decide whether to end
counting or to branch to an
interrupt requested by the
resource
YES
Set the extended intelligent
I/O service again (switch
channels)
Process data in the buffer
RETI
ISE: EI2OS enable bit in the interrupt control register (ICR)
S1, S0: EI2OS status of the interrupt control register (ICR)
146
S1, S0 = 01 or
S1, S0 = 11
NO
CHAPTER 7 INTERRUPT
7.6.5
Processing Time of the Extended Intelligent I/O Service
(EI2OS)
The time required for processing the extended intelligent I/O service (EI2OS) changes
according to the following factors:
•
•
•
•
•
EI2OS status register (ISCS) setting
Address (area) pointed to by the I/O register address pointer (IOA)
Address (area) pointed to by the buffer address pointer (BAP)
External data bus length for external access
Transfer data length
Because the hardware interrupt is activated when data transfer by EI2OS terminates, the
interrupt handling time is added.
■ Processing Time (one transfer time) of the Extended Intelligent I/O Service (EI2OS)
● When data transfer continues
The EI2OS processing time for data transfer continuation is shown in Table 7.6-2 based on the EI2OS status
register (ISCS) setting.
Table 7.6-2 Extended Intelligent I/O Service Execution Time
EI2OS termination control bit (SE) setting
IOA update/fixed selection bit (IF) setting
BAP address update/fixed selection bit (BF) setting
Terminates due to termination
request from the peripheral
Ignores termination request
from the peripheral
Fixed
Update
Fixed
Update
Fixed
32
34
33
35
Update
34
36
35
37
Unit:Machine cycle (One machine cycle corresponds to one clock cycle of the machine clock, φ).
As shown in Table 7.6-3, interpolation is necessary depending on the EI2OS execution condition.
Table 7.6-3 Data Transfer Interpolation Value for EI2OS Execution Time
Internal access
External access
I/O register address pointer
Internal access
Buffer address
pointer
External access
B/Even
Odd
B/Even
8/Odd
B/Even
0
+2
+1
+4
Odd
+2
+4
+3
+6
B/Even
+1
+3
+2
+5
8/Odd
+4
+6
+5
+8
B:
Byte data transfer
8:
External bus using the 8-bit word transfer
Even: Even-numbered address word transfer
Odd: Odd-numbered address word transfer
147
CHAPTER 7 INTERRUPT
● When the data counter (DCT) count terminates (final data transfer)
Because the hardware interrupt is activated when data transfer by EI2OS terminates, the interrupt handling
time is added. The EI2OS processing time when counting terminates is calculated with the following
formula:
EI2OS processing time when counting terminates = EI2OS processing time when data is transferred +
(21 + 6 × Z) Machine cycles
Interrupt handling time
The interrupt handling time is different for each address pointed to by the stack pointer. Table 7.6-4 shows
the interpolation value (Z) for the interrupt handling time.
Table 7.6-4 Interpolation Value (Z) for the Interrupt Handling Time
Address pointed to by the stack pointer
Interpolation value (Z)
External 8-bit
+4
External even-numbered address
+1
External odd-numbered address
+4
Internal even-numbered address
0
Internal odd-numbered address
+2
● For termination by a termination request from the peripheral function (I/O)
When data transfer by EI2OS is terminated before completion due to a termination request from the
peripheral function (I/O) (ICR: S1, S0 = 11B), the data transfer is not performed and a hardware interrupt
is activated. The EI2OS processing time is calculated with the following formula. Z in the formula
indicates the interpolation value for the interrupt handling time (Table 7.6-4).
EI2OS processing time for termination before completion = 36 + 6 × Z Machine cycle
Reference:
One machine cycle corresponds to one clock cycle of the machine clock (φ).
148
CHAPTER 7 INTERRUPT
7.7
Exception Processing Interrupt
In the F2MC-16LX, the execution of an undefined instruction results in exception
processing.
Exception processing is basically the same as an interrupt. When the generation of an
exception processing is detected on the instruction boundary, ordinary processing is
interrupted and exception processing is executed.
Generally, exception processing occurs as the result of an unexpected operation.
Exception processing should be used only to activate recovery software required for
debugging or an emergency.
■ Exception Processing
● Exception processing operation
The F2MC-16LX handles all codes that are not defined in the instruction map as undefined instructions.
When an undefined instruction is executed, processing equivalent to the INT #10 software interrupt
instruction is executed.
● The following processing is executed before exception processing branches to the interrupt routine:
• The A, DPR, ADB, DTB, PCB, PC and PS registers are saved to the system stack.
• The I flag of the condition code register (CCR) is cleared to "0", and hardware interrupts are masked.
• The S flag of the condition code register (CCR) is set to "1", and the system stack is activated.
The program counter (PC) value saved to the stack is the exact address where the undefined instruction is
stored. For 2-byte or longer instruction codes, the code identified as undefined is stored at this address.
When the exception factor type must be determined within the exception processing routine, use this PC
value.
● Return from exception processing
When the RETI instruction returns control from exception processing, exception processing restarts
because the PC is pointing to the undefined instruction. Provide a solution such as resetting the software.
149
CHAPTER 7 INTERRUPT
7.8
Stack Operations for Interrupt Processing
Once an interrupt is accepted, the contents of the dedicated registers are automatically
saved to the system stack before a branch to interrupt processing. When the interrupt
processing terminates, the previous processing is automatically restored from the
stack.
■ Stack Operations at the Start of Interrupt Processing
Once an interrupt is accepted, the CPU automatically saves the contents of the current dedicated registers to
the system stack in the order given below:
• Accumulator (A)
• Direct page register (DPR)
• Additional data bank register (ADB)
• Data bank register (DTB)
• Program bank register (PCB)
• Program counter (PC)
• Processor status (PS)
Figure 7.8-1 shows the stack operations at the start of interrupt processing.
Figure 7.8-1 Stack Operations at the Start of Interrupt Processing
Immediately before interrupt
Immediately after interrupt
Memory
Address
Memory
Address
before update
SP after update
Byte
Byte
■ Stack Operations on Return from Interrupt Processing
When the interrupt return instruction (RETI) is executed at the termination of interrupt processing, the PS,
PC, PCB, DTB, ADB, DPR and A values are returned from the stack in reverse order from the order they
were placed on the stack. The dedicated registers are restored to the status they had immediately before the
start of interrupt processing.
150
CHAPTER 7 INTERRUPT
■ Stack Area
● Stack area allocation
The stack area is used for saving and restoring the program counter (PC) when the subroutine call
instruction (CALL) and vector call instruction (CALLV) are executed in addition to interrupt processing.
The stack area is used for temporary saving and restoring of registers by the PUSHW and POPW
instructions.
The stack area is allocated together with the data area in RAM.
Figure 7.8-2 shows the stack area.
Figure 7.8-2 Stack Area
Vector table
(interrupt vector call
instruction for a reset)
FFFFFFH
FFFC00H
ROM area
FF0000H*1
000900H*2
Built-in
RAM area
Stack
area 000380H
General-purpose
register bank area
000180H
000100H
0000C0H
Built-in I/O area
000000H
*1
*2
Notes:
The internal ROM is different for each model.
The internal RAM is different for each model.
• Generally set an even-numbered address in the stack pointers (SSP and USP).
• Allocate the system stack area, user stack area, and data area so that they do not overlap.
● System stack and user stack
The system stack area is used for interrupt processing. When an interrupt occurs, the user stack area being
used is forcibly switched to the system stack. The system stack area must be set correctly even in a system
that mainly uses the user stack area.
If division of the stack space is not particularly necessary, use only the system stack.
151
CHAPTER 7 INTERRUPT
7.9
Sample Programs for Interrupt Processing
This section contains sample programs for interrupt processing.
■ Sample Programs for Interrupt Processing
● Processing specifications
The following is a sample program for an interrupt that uses external interrupt 0 (INT0).
● Sample coding
DDR1
EQU
000011H
;Port 1 direction register
ENIR
EQU
030H
;Interrupt/DTP enable register
EIR
EQU
031H
;Interrupt/DTP flag
ELVR
EQU
032H
;Request level setting register
ICR04
EQU
0B4H
;Interrupt control register
STACK
SSEG
;Stack
RW
100
STACK_T
RW
1
STACK
ENDS
;---------Main program --------------------------------------------------------------------------------------------------CODE
CSEG
START:
MOV
RP,#0
;General-purpose registers use the first bank
MOV
ILM, #07H
;Sets ILM in PS to level 7
MOV
A, #!STACK_T
;Sets system stack
MOV
SSB, A
MOVW
A, #STACK_T
;Sets stack pointer, then
MOVW
SP, A
;Sets SSP because S flag = 1
MOV
DDR1, #00000000B
;Sets P10/INT0 pin to input
OR
CCR, #40H
;Sets I flag of CCR in PS, enables interrupts
MOV
I:ICR04, #00H
;Sets interrupt level to "0" (highest priority)
MOV
I:ELVR, #00000001B ;Requests that INT0 be made level H
MOV
I:EIRR, #00H
;Clears INT0 interrupt cause
MOV
I:EIRR, #01H
;Enables INT0 input
:
LOOP:
NOP
NOP
NOP
152
;Dummy loop
CHAPTER 7 INTERRUPT
NOP
BRA
LOP
;Unconditional jump
;---------Interrupt program ---------------------------------------------------------------------------------------------ED_INT1:
MOV
I:EIRR, #00H
;Acceptance of new INT0 not allowed
NOP
NOP
NOP
NOP
NOP
NOP
RETI
CODE
;Return from interrupt
ENDS
;--------Vector setting----------------------------------------------------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFACH
;Sets vector for interrupt #20 (14H)
ORG
0FFDCH
;Sets reset vector
DSL
START
DB
00H
DSLED_INT1
VECT
;Sets single-chip mode
ENDS
END
START
■ Processing Specifications of Sample Program for Extended Intelligent I/O Service
(EI2OS)
1. This program detects the H level signal input to the INT0 pin and activates the extended intelligent I/O
service (EI2OS).
2. When the H level is input to the INT0 pin, EI2OS is activated. Data is transferred from port 0 to the
memory at the 3000H address.
3. The number of transfer data bytes is 100 bytes. After 100 bytes are transferred, an interrupt is generated
because EI2OS transfer has terminated.
● Sample coding
DDR1
EQU
000011H
;Port 1-direction register
ENIR
EQU
000030H
;Interrupt/DTP enable register
EIRR
EQU
000031H
;Interrupt/DTP factor register
ELVR
EQU
000032H
;Request level setting register
ICR04
EQU
0000B4H
;Interrupt control register
BAPL
EQU
000100H
;Lower buffer address pointer
BAPM
EQU
000101H
;Middle buffer address pointer
153
CHAPTER 7 INTERRUPT
BAPH
EQU
000102H
;Upper buffer address pointer
ISCS
EQU
000103H
;EI2OS status
IOAL
EQU
000104H
;Lower I/O address pointer
IOAH
EQU
000105H
;Upper I/O address pointer
DCTL
EQU
000106H
;Low-order data counter
DCTH
EQU
000107H
;High-order data counter
ER0
EQU
EIRR:0
;Definition of external interrupt request flag bit
STACK
SSEG;Stack
RW100
STACK_T
RW1
STAC
KENDS
-------------------Main program-----------------------------------------------------------------------------------------CODE
CSEG
START:
AND
CCR, #0BFH
;Clears the I flag of the CCR in the PS and
prohibits interrupts
MOV
RP, #00
;Sets the register bank pointer
MOV
A, #STACK_T
;Sets the system stack
MOV
SSB, A
MOVW
A, #STACK_T
;Sets the stack pointer, then
MOVW
SP, A
;Sets SSP because the S flag = 1
MOV
I:DDR1, #00000000B ; Sets the P10/INT0 pin to input
MOV
BAPL, #00H
MOV
BAPM, #30H
MOV
BAPH, #00H
MOV
ISCS, #00010001B
;Sets the buffer address (003000H)
;No I/O address update, byte transfer,
buffer address updated
I/O -> buffer transfer, terminated by the
peripheral function
MOV
IOAL, #00H
;Sets the transfer source address
(port 0: 000000H)
MOV
IOAH, #00H
MOV
DCTL, #64H
;Sets the number of transfer bytes
(100 bytes)
MOV
DCTH, #00H
MOV
I:ICR04, #00001000B ;EI2OS channel 0, EI2OS enable,
interrupt level 0 (highest priority)
154
MOV
I:ELVR, #00000001B ;Requests that INT0 be made H level
MOV
I:EIRR, #00H
;Clears the INT0 interrupt cause
CHAPTER 7 INTERRUPT
MOV
I:ENIR, #01H
;Enables INT0 interrupts
MOV
ILM, #07H
;Sets the ILM in the PS to level 7
OR
CCR, #40H
;Sets the I flag of the CCR in the PS
and enables interrupts
:
LOOP
BRA
LOOP
;Infinite loop
;---------------Interrupt program----------------------------------------------------------------------------------------WARI
CLRB
ER0
;Clears interrupt/DTP request flag
:
User processing
:
;Checks EI2OS termination factor,
;processes data in buffer, sets EI2OS
again
RETI
CODE
ENDS
;---------------Vector processing---------------------------------------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFACH
; Sets vector for interrupt #20 (14H)
DSL
WARI
ORG
0FFDCH
;Sets reset vector
DSL
START
DB
00H
;Sets single-chip mode
VECT
ENDS
END
START
155
CHAPTER 7 INTERRUPT
156
CHAPTER 8
MODE SETTING
This chapter describes the operating modes and
memory access modes supported by the MB90460/465
series.
8.1 Mode Setting
8.2 Mode Pins (MD2 to MD0)
8.3 Mode Data
157
CHAPTER 8 MODE SETTING
8.1
Mode Setting
The F2MC-16LX supports the modes for access method, and access areas. A mode is
determined based on the settings by the mode pin at a reset as well as the mode data
fetched.
■ Mode Setting
The F2MC-16LX supports the modes for access method, and access areas, classified as shown in Figure
8.1-1 in this module.
Figure 8.1-1 Mode Classification
Operating mode
RUN mode
FLASH WRITE mode
Bus mode
Single-chip mode
■ Operating Modes
The operating modes control the operating state of the device, and are specified by the mode setting pin
(MDx) and Mx bit contents in mode data.
Note:
Because the MB90460/465 series is only used in single-chip mode, set MD2, MD1, MD0 to 011B and
set M1, M0 to 00B.
■ Bus Mode
The bus mode controls the operation of internal ROM and external access functions, and is specified by the
mode setting pin (MDx) and Mx bit contents in mode data. The mode setting pin (MDx) specifies bus
mode when reset vector and mode data are read. The Mx bit in mode data specifies bus mode during
normal operation.
■ RUN Mode
The RUN mode means CPU operating mode. The RUN mode includes main clock mode, PLL clock mode,
and various low power consumption modes. See "CHAPTER 6 LOW POWER CONSUMPTION
MODE", for details.
Note:
158
Because the MB90460/465 series is only used in single-chip mode, set MD2, MD1, MD0 to 011B and
set M1, M0 to 00B.
CHAPTER 8 MODE SETTING
8.2
Mode Pins (MD2 to MD0)
Three external pins, MD2 to MD0, are supported as the mode pins. These are used to
specify how the reset vector and mode data are fetched.
■ Mode Pins (MD2 to MD0)
The mode pins are used to select the data bus (external or internal) used for reading the reset vector and to
specify the bus width when the external data bus is selected.
For a built-in FLASH version, the mode pins are also used to specify FLASH programming mode, which is
used to write programs and other data to internal FLASH.
Table 8.2-1 shows the mode pin settings.
Table 8.2-1 Mode Pin Settings
MD2
MD1
MD0
0
0
0
0
0
1
0
1
0
Mode name
Reset vector
access area
External data
bus width
Remarks
Setting not allowed
Internal vector mode
Internal
Mode data
The reset
sequence and
subsequent
sequences are
controlled by
mode data.
0
1
1
1
0
0
1
0
1
1
1
0
FLASH serial write
mode
-
-
-
1
1
1
FLASH memory
mode
-
-
Mode when the
parallel writer
is used.
Setting not allowed
MD2 to MD0: Connect the pins to Vss for 0 and to Vcc for 1.
*: The flash serial write mode cannot be executed by just setting the mode pins. Other terminal also need
to be set. For details, see "CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A
CONNECTION FOR SERIAL WRITING".
Note:
Because the MB90460/465 series is only used in single-chip mode, set MD2, MD1, MD0 to 011B and
set M1, M0 to 00B.
159
CHAPTER 8 MODE SETTING
8.3
Mode Data
The mode data is at memory location FFFFDFH, and is used to specify the operation
after a reset sequence. The mode data is automatically fetched to the CPU.
■ Mode Data
During a reset sequence, the mode data at address FFFFDFH is fetched to the mode register in the CPU.
The CPU uses the mode data to set the memory access mode.
The contents of the mode register can only be changed during the reset sequence. The settings in the
register take effect after the reset sequence.
Figure 8.3-1 shows the mode data configuration.
Figure 8.3-1 Mode Data Configuration
bit
Mode data
7
6
5
4
3
2
1
0
M1
M0
0
0
0
0
0
0
Function extension bits (reserved area)
Bus mode setting bits
■ Bus Mode Setting Bits
The bus mode setting bits specify operating mode after a reset sequence. Table 8.3-1 lists the relationship
between the bits and functions.
Table 8.3-1 Bus Mode Setting Bits and Functions
Note:
160
M1
M0
Function
0
0
Single-chip mode
0
1
1
0
1
1
(Setting not allowed)
Because the MB90460/465 series is only used in single-chip mode, set MD2, MD1, MD0 to 011B and
set M1, M0 to 00B.
CHAPTER 8 MODE SETTING
Figure 8.3-2 shows the correspondence between access areas and physical addresses in single-chip mode.
Figure 8.3-2 Correspondence between Access Areas and Physical Addresses in Single-chip Mode
FFFFFFH
ROM
Model #1
FF0000H
00FFFFH
ROM
When ROM mirroring function is selected
Model #2
Model #3
RAM
000100H
0000C0H
000000H
: No access
: Internal access
I/O
(Note) Model #x becomes the model-dependent address.
■ Relationship between Mode Pins and Mode Data
Table 8.3-2 lists the relationship between mode pins and mode data.
Table 8.3-2 Relationship between Mode Pins and Mode Data
Note:
Mode
MD2
MD1
MD0
M1
M0
Single-chip mode
0
1
1
0
0
The MB90460/465 series is only used in single-chip mode.
161
CHAPTER 8 MODE SETTING
162
CHAPTER 9
I/O PORT
This chapter describes the functions and operation of
the I/O port.
9.1 Overview of I/O Port
9.2 Registers of I/O Port
9.3 Port 0
9.4 Port 1
9.5 Port 2
9.6 Port 3
9.7 Port 4
9.8 Port 5
9.9 Port 6
9.10 Sample I/O Port Program
163
CHAPTER 9 I/O PORT
9.1
Overview of I/O Port
An I/O port can be used as a general-purpose I/O port (parallel I/O port). The MB90460/
465 series has 7 ports (51 lines). The ports are also used for resource I/O pins
(peripheral function I/O pins).
■ I/O Port Functions
Each I/O port outputs data from the CPU to the I/O pins or inputs signals from the I/O pins to the CPU as
directed by the port data register (PDR). Each I/O port can also designate the direction of a data flow
(input or output) at the I/O pins in bit units using the port data direction register (DDR). The function of
each port and the resources using it are described below:
• Port 0: General-purpose I/O port/resource (Waveform sequencer*/PWC0*)
• Port1: General-purpose I/O port/resource (External interrupt/Waveform
sequencer*/Waveform generator/16-bit reload timer 0)
• Port 2: General-purpose I/O port/resource (16-bit reload timer/PWC1/Input capture)
• Port 3: General-purpose I/O port/resource (Waveform generator/PPG1*/PPG0)
• Port 4: General-purpose I/O port/resource (UART0/Waveform sequencer*/PPG2)
• Port 5: General-purpose I/O port/resource (A/D converter)
• Port6: General-purpose I/O port/resource (UART1/External interrupt)
Table 9.1-1 summarizes the functions of individual port.
Table 9.1-1 Functions of Individual Port
Port
Pin
Input form
Port 0
P00/OPT0
to P07/
PWO0
CMOS
Port 1
Port 2
Port 3
P10/INT0/
DTT0 to
P17/FRCK
Output
Function
form
General
I/O port
CMOS Resource
pull-up
resistor General
selectable I/O port
CMOS
bit
14
bit
13
bit
12
bit
11
bit
10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
–
–
–
–
–
–
–
–
P07
P06
P05
P04
P03
P02
P01
P00
–
–
–
–
–
–
–
–
P17
P16
P15
P14
P13
P12
P11
P10
INT6/
TO0
INT5/
TIN0
INT4
INT3
Resource FRCK
CMOS
(hysteresis)
P20/TIN1
to P27/IN3
P30/RT00
to P37/PPG0
bit
15
CMOS
Port 5
Port 6
P40/SIN
CMOS
to P46/PPG2 (hysteresis)
P50/AN0
to P57/AN7
Analog/
CMOS
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P23
P22
P21
P20
TO1
TIN1
–
–
–
–
–
–
–
–
P27
P26
P25
P24
Resource
–
–
–
–
–
–
–
–
IN3
IN2
IN1
IN0
General
I/O port
P37
P36
P35
P34
P33
P32
P31
P30
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P46
P45
P44
P43
P42
P41
P40
RTO2
RTO1 RTO0
PWO1 PWI1
General
I/O port
–
–
–
–
–
–
–
–
–
Resource
–
–
–
–
–
–
–
–
–
General
I/O port
P57
P56
P55
P54
P53
P52
P51
P50
–
–
–
–
–
–
–
–
Analog
input
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
–
–
–
–
–
–
–
–
General
I/O port
–
–
–
–
–
–
–
–
–
–
–
–
P63
P62
P61
P60
Resource
–
–
–
–
–
–
–
–
–
–
–
–
PPG2 SNI2* SNI1* SNI0* SCK0 SOT0 SIN0
CMOS
P60/SIN1
CMOS
CMOS
to P63/INT7 (hysteresis)
*: Pin names not applicable to MB90465 series
164
–
General
I/O port
Resource PPG0 PPG1* RTO5 RTO4 RTO3
Port 4
INT2/
INT0/
INT1
DTTI1*
DTTI0
PWO0* PWI0* OPT5* OPT4* OPT3* OPT2* OPT1* OPT0*
INT7 SCK1 SOT1 SIN1
CHAPTER 9 I/O PORT
Note:
Port 5 is also used as analog input pins. To use the port as a general-purpose port, be sure to reset
the corresponding bit of the analog data input enable register (ADER) to "0". Resetting the CPU sets
the ADER register bits to "1".
165
CHAPTER 9 I/O PORT
9.2
Registers of I/O Port
This section provides a list of the registers related to the I/O port settings.
■ Registers for I/O Ports
Table 9.2-1 is a list of the registers corresponding to individual port.
Table 9.2-1 Registers and Corresponding port
Register
Read/Write
Address
Initial value
Port 0 data register (PDR0)
R/W
000000H
XXXXXXXXB
Port 1 data register (PDR1)
R/W
000001H
XXXXXXXXB
Port 2 data register (PDR2)
R/W
000002H
XXXXXXXXB
Port 3 data register (PDR3)
R/W
000003H
XXXXXXXXB
Port 4 data register (PDR4)
R/W
000004H
-XXXXXXXB
Port 5 data register (PDR5)
R/W
000005H
XXXXXXXXB
Port 6 data register (PDR6)
R/W
000006H
----XXXXB
Port 0 data direction register (DDR0)
R/W
000010H
00000000B
Port 1 data direction register (DDR1)
R/W
000011H
00000000B
Port 2 data direction register (DDR2)
R/W
000012H
00000000B
Port 3 data direction register (DDR3)
R/W
000013H
00000000B
Port 4 data direction register (DDR4)
R/W
000014H
–0000000B
Port 5 data direction register (DDR5)
R/W
000015H
00000000B
Port 6 data direction register (DDR6)
R/W
000016H
----0000B
Analog data input enable register (ADER)
R/W
000017H
11111111B
Port 0 pull-up resistor setting register (RDR0)
R/W
00001CH
00000000B
Port 1 pull-up resistor setting register (RDR1)
R/W
00001DH
00000000B
R/W: Read/write enabled
R: Read-only
X: Undefined
–: Not used
Note:
166
For port (other than Port 0,1,2 and 3) that is multiplexed with resource, use Read-modify-write
instruction (such as an instruction that sets bits) may accidentally write unexpected value to the DDR
and PDR register when resource is enabled.
CHAPTER 9 I/O PORT
9.3
Port 0
Port 0 is a general-purpose I/O port. It can also be used for resource I/O. The port pins
can be switched in units of bits between the I/O port and resource. This section
focuses on the general I/O port function. This section also provides the configuration
of port 0, lists of pins, shows a block diagram of the pins, and describes the
corresponding registers.
■ Port 0 Configuration
Port 0 consists of the following:
• General-purpose I/O pins/waveform sequencer output/PWC0 input, output (P00/OPT0 to P07/PWO0)
(waveform sequencer output and PWC0 not present in MB90465 series)
• Port 0 data register (PDR0)
• Port 0 data direction register (DDR0)
• Port 0 pull-up resistor setting register (RDR0)
■ Port 0 Pins
The port 0 I/O pins are also used as resource I/O pins. Therefore, the pins cannot be used as generalpurpose I/O port pins when they are used as resource I/O pins. Table 9.3-1 lists the port 0 pins.
Table 9.3-1 Port 0 Pins
Port
Pin
Port function
(single-chip mode)
I/O form
Resource function
Input
P00/OPT0*
P00
OPT0*
Waveform
sequencer output
P01/OPT1*
P01
OPT1*
Waveform
sequencer output
P02/OPT2*
P02
OPT2*
Waveform
sequencer output
OPT3*
Waveform
sequencer output
Output
Circuit
type
D
Port 0
Generalpurpose I/O
P03/OPT3*
P03
P04/OPT4*
P04
OPT4*
Waveform
sequencer output
P05/OPT5*
P05
OPT5*
Waveform
sequencer output
P06/PWI0*
P06
PWI0*
PWC0 input
P07/PWO0*
P07
PWO0*
PWC0 output
CMOS
CMOS
E
*: Pin names not applicable to MB90465 series
See "1.7 I/O Circuit Types", for information on the circuit types.
167
CHAPTER 9 I/O PORT
■ Block Diagram of Port 0 Pins
Figure 9.3-1 is a block diagram of the port 0pins.
Figure 9.3-1 Block Diagram of port 0 Pins
RDR
Resource output
Port data register (PDR)
Direct resource input
Resource output enable
Pull-up resistor
Internal data bus
About 50k
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
When the resource output enable bit is set, the port is forcibly caused to function as resource output pins
regardless of the value in the DDR0 register.
■ Port 0 Registers
Port 0 registers are PDR0, DDR0 and RDR0. The bits making up each register correspond to the port 0
pins on a one-to-one basis. Table 9.3-2 lists the port 0 pins and their corresponding register bits.
Table 9.3-2 Port 0 Pins and their Corresponding Register Bits
Port
Register bits and corresponding port pins
PDR0, DDR0, RDR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P07
P06
P05
P04
P03
P02
P01
P00
Port 0
See "1.7 I/O Circuit Types", for information on the circuit types.
168
CHAPTER 9 I/O PORT
9.3.1
Port 0 Registers (PDR0, DDR0 and RDR0)
This section describes the port 0 registers.
■ Functions of Port 0 Registers
● Port 0 data register (PDR0)
The PDR0 register indicates the state of each pin of port 0.
● Port 0 data direction register (DDR0)
The DDR0 register specifies the direction of a data flow (input or output) at each pin (bit) of port 0. When
a DDR0 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the
port (pin) is set as an input port.
● Port 0 pull-up resistor setting register (RDR0)
The RDR0 register specifies the selection of a pull-up resistor at each pin (bit) of port 0. When a RDR0
register bit is "1", a pull-up resistor is selected for the corresponding port (pin). When the bit is "0", the
pull-up resistor is deselected.
Notes:
• When a resource having output pins is used, the port functions as resource output pins regardless
of the value in the DDR0 register as long as the resource output enable bit corresponding to the
pins is set.
• To use a resource having input pins, reset the port direction register bit corresponding to each
resource input pin to "0" to place the port in input mode.
169
CHAPTER 9 I/O PORT
Table 9.3-3 lists the functions of the port 0 registers.
Table 9.3-3 Port 0 Register Functions
Register
Data During reading
During writing
The output latch is loaded with 0. When
The pin is at the
the pin functions as an output port, the
low level.
pin is set to the low level.
Port 0 data
register (PDR0)
The output latch is loaded with 1. When
The pin is at the
1
the pin functions as an output port, the
high level.
pin is set to the high level.
The direction
The output buffer is turned off to place
0
Port 0 data
latch is "0".
the port in input mode.
direction register
The direction
The output buffer is turned on to place
(DDR0)
1
latch is "1".
the port in output mode.
The setting
The pull-up resistor is cut and the port is
0
latch is "0".
placed in the Hi-Z state in input mode.
Port 0 pull-up
resistor setting
The pull-up resistor is selected and the
The setting
register (RDR0)
1
port is held at the high level in input
latch is "1".
mode.
R/W: Read/write enabled
X : Undefined
Read/
Write
Address
Initial value
0
170
R/W
000000H XXXXXXXXB
R/W
000010H
00000000B
R/W
00001CH
00000000B
CHAPTER 9 I/O PORT
9.3.2
Operation of Port 0
This section describes the operation of port 0.
■ Operation of Port 0
● Port operation in output mode
• Setting a bit of the DDR0 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR0 register in output mode is held in the output latch of the PDR and output to the
port pins as is.
• The PDR0 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR).
Note:
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as is. Before switching
the mode for the bits from input to output, therefore, write the output data to the PDR register, then
specify output mode in the DDR register.
● Port operation in input mode
• Resetting a bit of the DDR0 register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pins are placed in a high impedance state.
• However, when the RDR0 register is set to "1" to select a pull-up resistor, the pins are held at the high
level.
• Data written to the PDR0 register in input mode is held in the output latch of the PDR but is not output
to the port pins.
• The PDR0 register can be accessed in read mode to read the level value (0 or 1) at the port pins.
● Port operation for resource output
• The resource output enable bit is set to enable the port to be used for resource output. The state of the
resource enable bit takes precedence when specifying a switch between input and output. Even if a
DDR0 register bit is "0", the corresponding port pin is used for resource output if the resource has been
enabled for output. Because the value at the pins can be read even if resource output is enabled, the
resource output value can be read.
● Port operation for resource input
• When the port is also used for resource input, the value at the pins is always supplied as resource inputs.
To use an external signal for the resource, reset the DDR0 register to "0" to place the port in input mode.
171
CHAPTER 9 I/O PORT
● Port operation after a reset
• When the CPU is reset, the DDR0 and RDR registers are initialized to "0". As a result, the output buffer
is turned off (I/O mode changes to input), the pull-up resistor is cut, and the pins are placed in a high
impedance state.
• The PDR0 register is not initialized when the CPU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR0 register after the output data is set in the PDR0 register.
● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR0 register. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit.
Note also that when a pull-up resistor is selected, the port pins are held at the high level and not placed in a
high-impedance state even when the SPL bit is set to "1". Table 9.3-4 lists the states of the port 0 pins.
Table 9.3-4 States of Port 0 Pins
Pin
Normal operation
Sleep mode
GeneralP00/OPT0 to General-purpose
purpose
P07/PWO0
I/O port
I/O port
Stop mode or time-base
timer mode (SPL = 0)
Stop mode or time-base Stop mode or time-base
timer mode
timer mode
(SPL = 1, RDR = 0)
(SPL = 1, RDR = 1)
General-purpose I/O
port
Input shut down/output Input shut down/
in Hi-Z
held at H level
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z: High impedance
172
CHAPTER 9 I/O PORT
9.4
Port 1
Port 1 is a general-purpose I/O port. It can also be used for resource I/O. The port pins
can be switched in units of bits between the I/O port and resource. This section
focuses on the general I/O port function. The section provides the configuration of port
1, lists its pins, shows a block diagram of the pins, and describes the corresponding
registers.
■ Port 1 Configuration
Port 1 consists of the following:
• General-purpose I/O pins/external interrupt input pins (P10/INT0/DTT0 to P17/FRCK)
• Port 1 data register (PDR1)
• Port 1 data direction register (DDR1)
• Port 1 pull-up resistor setting register (RDR1)
■ Port 1 Pins
The port 1 pins are also used as resource input pins. The pins cannot be used as output port pins when they
are used as resource input pins. Table 9.4-1 lists the port 1 pins.
Table 9.4-1 Port 1 Pins
I/O form
Port
Port 1
Pin
Port function
Resource function
P10/INT0/
DTTI0
P10
INT0/
DTTI0
External interrupt
input/waveform
generator input
P11/INT1
P11
INT1
External interrupt
input
P12/INT2/
DTTI1*
P12
INT2/
DTTI1*
External interrupt
input/waveform
sequencer input
P13/INT3
P13
P14/INT4
P14
P15/INT5/
TIN0
P15
INT5/
TIN0
External interrupt
input/reload timer
input
P16/INT6/
TO0
P16
INT6/
TO0
External interrupt
input/reload timer
output
P17/FRCK
P17
FRCK
Free-run timer
clock input
Generalpurpose I/O
INT3
INT4
External interrupt
input
Circuit type
Input
Output
CMOS
(hysteresis)
CMOS
C
*: Pin names not applicable to MB90465 series
See "1.7 I/O Circuit Types", for information on the circuit types.
173
CHAPTER 9 I/O PORT
■ Block Diagram of Port 1 Pins
Figure 9.4-1 is a block diagram of port 1 pins.
Figure 9.4-1 Block Diagram of Port 1 Pins
RDR
Resource input
Resource output
Port data register (PDR)
Resource output enable
Pull-up resistor
About 50k
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
When the resource output enable bit is set, the port is forcibly caused to function as resource output pins
regardless of the value in the DDR1 register.
■ Port 1 Registers
Port 1 registers are PDR1, DDR1 and RDR1. The bits making up each register correspond to the port 1
pins on a one-to-one basis. Table 9.4-2 lists the port 1 pins and their corresponding register bits.
Table 9.4-2 Port 1 Pins and their Corresponding Register Bits
Port
Register bits and corresponding port pins
PDR1, DDR1, RDR1
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Corresponding pin
P17
P16
P15
P14
P13
P12
P11
P10
Port 1
174
CHAPTER 9 I/O PORT
9.4.1
Port 1 Registers (PDR1, DDR1 and RDR1)
This section describes the port 1 registers.
■ Functions of Port 1 Registers
● Port 1 data register (PDR1)
The PDR1 register indicates the state of each pin of port 1.
● Port 1 data direction register (DDR1)
The DDR1 register specifies the direction of a data flow (input or output) at each pin (bit) of port 1. When
a DDR1 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the
port (pin) is set as an input port.
● Port 1 pull-up resistor setting register (RDR1)
The RDR1 register specifies the selection of a pull-up resistor at each pin (bit) of port 1. When a RDR1
register bit is "1", a pull-up resistor is selected for the corresponding port (pin). When the bit is "0", the
pull-up resistor is deselected.
Notes:
• When a resource having output pins is used, the port functions as resource output pins regardless
of the value in the DDR1 register as long as the resource output enable bit corresponding to the
pins is set.
• To use a resource having input pins, reset the port direction register bit corresponding to each
resource input pin to "0" to place the port in input mode.
Table 9.4-3 lists the functions of the port 1 registers.
Table 9.4-3 Port 1 Register Functions
Register
Data During reading
0
Port 1 data register
(PDR1)
1
Port 1 data
direction register
(DDR1)
Port 1 pull-up
resistor setting
register (RDR1)
0
1
0
1
During writing
The output latch is loaded with 0. When
The pin is at the
the pin functions as an output port, the pin
low level.
is set to the low level.
The output latch is loaded with 1. When
The pin is at the
the pin functions as an output port, the pin
high level.
is set to the high level.
The direction
The output buffer is turned off to place the
latch is "0".
port in input mode.
The direction
The output buffer is turned on to place the
latch is "1".
port in output mode.
The setting latch The pull-up resistor is cut and the port is
is "0".
placed in the Hi-Z state in input mode.
The setting latch The pull-up resistor is selected and the port
is "1".
is held at the high level in input mode.
Read/Write
Address
Initial value
R/W
000001H
XXXXXXXXB
R/W
000011H
00000000B
R/W
00001DH
00000000B
R/W: Read/write enabled
X : Undefined
175
CHAPTER 9 I/O PORT
9.4.2
Operation of Port 1
This section describes the operation of port 1.
■ Operation of Port 1
● Port operation in output mode
• Setting a bit of the DDR1 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR1 register in output mode is held in the output latch of the PDR and output to the
port pins.
• The PDR1 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR).
Note:
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as is. Before switching
the mode for the bits from input to output, therefore, write the output data to the PDR register, then
specify output mode in the DDR register.
● Port operation in input mode
• Resetting a bit of the DDR1 register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pins are placed in a high impedance state.
• However, when the RDR1 register is set to "1" to select a pull-up resistor, the pins are held at the high
level.
• Data written to the PDR1 register in input mode is held in the output latch of the PDR but not output to
the port pins.
• The PDR1 register can be accessed in read mode to read the level value (0 or 1) at the port pins.
● Port operation for resource output
• The resource output enable bit is set to enable the port to be used for resource output. The state of the
resource enable bit takes precedence when specifying a switch between input and output. Even if a
DDR1 register bit is "0", the corresponding port pin is used for resource output if the resource has been
enabled for output. Because the value at the pins can be read even if resource output is enabled, the
resource output value can be read.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as resource inputs.
To use an external signal for the resource, reset the DDR1 register to "0" to place the port in input mode.
176
CHAPTER 9 I/O PORT
● Port operation after a reset
• When the CPU is reset, the DDR1 and RDR registers are initialized to "0". As a result, the output buffer
is turned off (I/O mode changes to input), the pull-up resistor is cut, and the pins are placed in a high
impedance state.
• The PDR1 register is not initialized when the CPU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR1 register after the output data is set in the PDR1 register.
● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR1 register. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit.
Note also that when a pull-up resistor is selected, the port pins are held at the high level and not placed in a
high-impedance state even when the SPL bit is set to "1". Table 9.4-4 lists the states of the port 1 pins.
Table 9.4-4 States of Port 1 Pins
Pin
Normal operation
P10/INT0/
General-purpose
DTTI0 to P17/
I/O port
FRCK
Sleep mode
Stop mode or time-base Stop mode or time-base Stop mode or time-base
timer mode
timer mode
timer mode
(SPL = 0)
(SPL = 1, RDR = 0)
(SPL = 1, RDR = 1)
General-purpose
Input enabled*/output in
General-purpose I/O port
I/O port
Hi-Z
Input shut down/held at H
level
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z : High impedance
*
: Only when P10/INT0 to P16/INT6 is configured as external interrupt pins, otherwise input shutdown
177
CHAPTER 9 I/O PORT
9.5
Port 2
Port 2 is a general-purpose I/O port. It can also be used for resource I/O. The port pins
can be switched in units of bits between the I/O port and the resource. This section
focuses on the general I/O port function. This section also provides the configuration of
port 2, lists its pins, shows a block diagram of the pins, and describes the
corresponding registers.
■ Port 2 Configuration
Port 2 consists of the following:
• General-purpose I/O pins/resource I/O pins (P20/TIN1 to P27/IN3)
• Port 2 data register (PDR2)
• Port 2 data direction register (DDR2)
■ Port 2 Pins
The port 2 I/O pins are also used as resource I/O pins. The pins cannot be used as general-purpose I/O port
pins when they are used as resource I/O pins. Table 9.5-1 lists the port 2 pins.
Table 9.5-1 Port 2 Pins
I/O form
Port
Pin
Port function
Resource function
P20/TIN1
P20
TIN1
16-bit reload timer 1input
P21/TO1
P21
TO1
16-bit reload timer 1 output
P22/PWI1
P22
PWI1
PWC1 input
P23/PWO1
P23
PWO1
PWC1 output
P24/IN0
P24
P25/IN1
Port 2
Generalpurpose I/O
IN0
Input capture channel 0 input
P25
IN1
Input capture channel 1 input
P26/IN2
P26
IN2
Input capture channel 2 input
P27/IN3
P27
IN3
Input capture channel 3 input
See "1.7 I/O Circuit Types", for information on the circuit types.
178
Input
Output
CMOS
(hysteresis)
CMOS
Circuit
type
F
CHAPTER 9 I/O PORT
■ Block Diagram of Port 2 Pins
Figure 9.5-1 is a block diagram of port 2 pins.
Figure 9.5-1 Block Diagram of Port 2 Pins
Resource output
Resource input
Resource output enable
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
When the resource output enable bit is set, the port is forcibly caused to function as resource
output pins regardless of the value in the DDR2 register.
■ Port 2 Registers
Port 2 registers are PDR2 and DDR2. The bits making up each register correspond to the port 2 pins on a
one-to-one basis. Table 9.5-2 lists the port 2 pins and their corresponding register bits.
Table 9.5-2 Port 2 Pins and their Corresponding Register Bits
Port
Register bits and corresponding port pins
PDR2, DDR2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P27
P26
P25
P24
P23
P22
P21
P20
Port 2
179
CHAPTER 9 I/O PORT
9.5.1
Port 2 Registers (PDR2 and DDR2)
This section describes the port 2 registers.
■ Functions of Port 2 Registers
● Port 2 data register (PDR2)
The PDR2 register indicates the state of each pin of port 2.
● Port 2 data direction register (DDR2)
The DDR2 register specifies the direction of a data flow (input or output) at each pin (bit) of port 2. When
a DDR2 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the
port (pin) is set as an input port.
References:
• When a resource having output pins is used, the port functions as resource output pins regardless
of the value in the DDR2 register as long as the resource output enable bit corresponding to the
pins is set.
• To use a resource having input pins, reset the DDR2 register bit corresponding to each resource
input pin to "0" to place the port in input mode.
Table 9.5-3 lists the functions of the port 2 registers.
Table 9.5-3 Port 2 Register Functions
Register
Data
During writing
0
The pin is
at the low
level.
The output latch is loaded with 0.
When the pin functions as an output
port, the pin is set to the low level.
1
The pin is
at the high
level.
The output latch is loaded with 1.
When the pin functions as an output
port, the pin is set to the high level.
0
The
direction
latch is "0".
The output buffer is turned off to
place the port in input mode.
1
The
direction
latch is "1".
Port 2 data
register (PDR2)
Port 2 data
direction
register (DDR2)
R/W: Read/write enabled
X : Undefined
180
During
reading
The output buffer is turned on to
place the port in output mode.
Read/
Write
Address
Initial value
R/W
000002H
XXXXXXXXB
R/W
000012H
00000000B
CHAPTER 9 I/O PORT
9.5.2
Operation of Port 2
This section describes the operation of port 2.
■ Operation of Port 2
● Port operation in output mode
• Setting a bit of the DDR2 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR2 register in output mode is held in the output latch of the PDR and output to the
port pins.
• he PDR2 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR).
Note:
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as is. Before switching
the mode for the bits from input to output, therefore, write the output data to the PDR register, then
specify output mode in the DDR register.
● Port operation in input mode
• Resetting a bit of the DDR2 register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pins are placed in a high impedance state.
• Data written to the PDR2 register in input mode is held in the output latch of the PDR but not output to
the port pins.
• The PDR2 register can be accessed in read mode to read the level value (0 or 1) at the port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state of the
resource enable bit takes precedence when specifying a switch between input and output. Even if a DDR2
register bit is "0", the corresponding port pin is used for resource output if the resource has been enabled for
output. Because the value at the pins can be read even if resource output is enabled, the resource output
value can be read.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as resource inputs.
To use an external signal for the resource, reset the DDR2 register to "0" to place the port in input mode.
181
CHAPTER 9 I/O PORT
● Port operation after a reset
• When the CPU is reset, the DDR2 register is initialized to "0". As a result, the output buffer is turned
off (I/O mode changes to input), and the pins are placed in a high impedance state.
• The PDR2 register is not initialized when the CPU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR2 register after the output data is set in the PDR2 register.
● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR2 register. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit.
Table 9.5-4 lists the states of the port 2 pins.
Table 9.5-4 States of Port 2 Pins
Pin
P20/TIN1 to
P27/IN3
Normal operation
Sleep mode
Stop mode or time-base timer
mode (SPL = 0)
General-purpose I/O port General-purpose I/O port General-purpose I/O port
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z: High impedance
182
Stop mode or time-base
timer mode (SPL = 1)
Input shut down/output in Hi-Z
CHAPTER 9 I/O PORT
9.6
Port 3
Port 3 is a general-purpose I/O port. It can also be used for resource output. The port
pins can be switched in units of bits between the I/O port and resource. This section
focuses on the general I/O port function. It provides the configuration of port 3, lists its
pins, shows a block diagram of the pins, and describes the corresponding registers.
■ Port 3 Configuration
Port 3 consists of the following:
• General-purpose I/O pins/resource I/O pins (P30/RTO0 to P37/PPG0)
• Port 3 data register (PDR3)
• Port 3 data direction register (DDR3)
■ Port 3 Pins
The port 3 I/O pins are also used as resource output pins. Therefore, the pins cannot be used as generalpurpose I/O port pins when they are used as resource I/O pins. Table 9.6-1 lists the port 3 pins.
Table 9.6-1 Port 3 Pins
Port
Pin
I/O form
Port function
(single-chip mode)
Resource function
Input
P30/RTO0*
P30
RTO0*
Waveform generator
output 0
P31/RTO1*
P31
RTO1*
Waveform generator
output 1
P32/RTO2*
P32
RTO2*
Waveform generator
output 2
RTO3*
Waveform generator
output 3
Output
Circuit
type
G
Port 3
Generalpurpose I/O
P33/RTO3*
P33
P34/RTO4*
P34
RTO4*
Waveform generator
output 4
P35/RTO5*
P35
RTO5*
Waveform generator
output 5
P36/PPG1*
P36
PPG1*
PPG1 output
P37/PPG0
P37
PPG0
PPG0 output
CMOS
CMOS
H
*: Pin names not applicable to MB90465 series
See "1.7 I/O Circuit Types", for information on the circuit types.
183
CHAPTER 9 I/O PORT
■ Block Diagram of Port 3 Pins
Figure 9.6-1 is a block diagram of port 3 pins.
Figure 9.6-1 Block Diagram of Port 3 Pins
Resource output
Resource output enable
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
When the resource output enable bit is set, the port is forcibly caused to function as resource output pins
regardless of the value in the DDR3 register.
■ Port 3 Registers
Port 3 registers are PDR3 and DDR3. The bits making up each register correspond to the port 3 pins on a
one-to-one basis. Table 9.6-2 lists the port 3 pins and their corresponding register bits.
Table 9.6-2 Port 3 pins and their Corresponding Register Bits
Port
Register bits and corresponding port pins
PDR3, DDR3
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Corresponding pin
P37
P36
P35
P34
P33
P32
P31
P30
Port 3
184
CHAPTER 9 I/O PORT
9.6.1
Port 3 Registers (PDR3 and DDR3)
This section describes the port 3 registers.
■ Functions of Port 3 Registers
● Port 3 data register (PDR3)
The PDR3 register indicates the state of each pin of port 3.
● Port 3 data direction register (DDR3)
The DDR3 register specifies the direction of a data flow (input or output) at each pin (bit) of port 3. When
a DDR3 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the
port (pin) is set as an input port.
Note:
When a resource having output pins is used, the port functions as resource output pins regardless of
the value in the DDR3 register as long as the resource output enable bit corresponding to the pins is
set.
Table 9.6-3 lists the functions of the port 3 registers.
Table 9.6-3 Port 3 Register Functions
Register
Data
During
reading
During writing
0
The pin is
at the low
level.
The output latch is loaded with "0".
When the pin functions as an output
port, the pin is set to the low level.
1
The pin is
at the high
level.
The output latch is loaded with "1".
When the pin functions as an output
port, the pin is set to the high level.
0
The
direction
latch is "0".
The output buffer is turned off to
place the port in input mode.
1
The
direction
latch is "1".
Port 3 data
register (PDR3)
Port 3 data
direction
register (DDR3)
Read/
Write
Address
Initial value
R/W
000003H
XXXXXXXXB
R/W
000013H
00000000B
The output buffer is turned on to
place the port in output mode.
R/W: Read/write enabled
X : Undefined
185
CHAPTER 9 I/O PORT
9.6.2
Operation of Port 3
This section describes the operation of port 3.
■ Operation of Port 3
● Port operation in output mode
• Setting a bit of the DDR3 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR3 register in output mode is held in the output latch of the PDR and output to the
port pins.
• The PDR3 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR).
Note:
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as is. Before switching
the mode for the bits from input to output, therefore, write output data to the PDR register, then
specify output mode in the DDR register.
● Port operation in input mode
• Resetting a bit of the DDR3 register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pins are placed in a high impedance state.
• Data written to the PDR3 register in input mode is held in the output latch of the PDR but not output to
the port pins.
• The PDR3 register can be accessed in read mode to read the level value (0 or 1) at the port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state of the
resource enable bit takes precedence when specifying a switch between input and output. Even if a DDR3
register bit is "0", the corresponding port pin is used for resource output if the resource has been enabled for
output. Because the value at the pins can be read even if resource output is enabled, the resource output
value can be read.
● Port operation after a reset
• When the CPU is reset, the DDR3 register is initialized to "0". As a result, the output buffer is turned
off (I/O mode changes to input), and the pins are placed in a high impedance state.
• The PDR3 register is not initialized when the CPU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR3 register after the output data is set in the PDR3 register.
186
CHAPTER 9 I/O PORT
● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR3 register. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit.
Table 9.6-4 lists the states of the port 3 pins.
Table 9.6-4 States of Port 3 Pins
Pin
Normal operation
Sleep mode
P30/RTO0
General-purpose I/O port General-purpose I/O port
to P37/PPG0
Stop mode or time-base Stop mode or time-base
timer mode (SPL = 0)
timer mode (SPL = 1)
General-purpose I/O port
Input shut down/output in
Hi-Z
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z: High impedance
187
CHAPTER 9 I/O PORT
9.7
Port 4
Port 4 is a general-purpose I/O port. It can also be used for resource I/O. The port pins
can be switched in units of bits between the I/O port and resource. This section
focuses on the general I/O port function. It provides the configuration of port 4, lists its
pins, shows a block diagram of the pins, and describes the corresponding registers.
■ Port 4 Configuration
Port 4 consists of the following:
• General-purpose I/O pins/resource I/O pins (P40/SIN0 to P46/PPG2)
• Port 4 data register (PDR4)
• Port 4 data direction register (DDR4)
■ Port 4 Pins
The port 4 I/O pins are also used as resource I/O pins. The pins cannot be used as general-purpose I/O port
pins when they are used as resource I/O pins. Table 9.7-1 lists the port 4 pins.
Table 9.7-1 Port 4 Pins
Port
Pin
I/O form
Port function
(single-chip mode)
Resource function
P40/SIN0
P40
SIN0
UART 0 data input
P41/SOT0
P41
SOT0
UART 0 data output
P42/SCK0
P42
SCK0
UART 0 serial clock I/O
P43/SNI0*
P43
SNI0*
Waveform sequencer
input 0
Port 4
Generalpurpose I/O
P44/SNI1*
P44
SNI1*
Waveform sequencer
input 1
P45/SNI2*
P45
SNI2*
Waveform sequencer
input 2
P46/PPG2
P46
PPG2
PPG2 output
*: Pin names not applicable to MB90465 series
See "1.7 I/O Circuit Types", for information on the circuit types.
188
Input
Output
CMOS
(hysteresis)
CMOS
Circuit
type
F
CHAPTER 9 I/O PORT
■ Block Diagram of Port 4 Pins
Figure 9.7-1 is a block diagram of port 4 pins.
Figure 9.7-1 Block Diagram of Port 4 Pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
When the resource output enable bit is set, the port is forcibly caused to function as resource output pins
regardless of the value in the DDR4 register.
■ Port 4 Registers
Port 4 registers are PDR4 and DDR4. The bits making up each register correspond to the port 4 pins on a
one-to-one basis. Table 9.7-2 lists the port 4 pins and their corresponding register bits.
Table 9.7-2 Port 4 Pins and their Corresponding Register Bits
Port
Register bits and corresponding port pins
PDR4, DDR4
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
–
P46
P45
P44
P43
P42
P41
P40
Port 4
Corresponding pin
189
CHAPTER 9 I/O PORT
9.7.1
Port 4 Registers (PDR4 and DDR4)
This section describes the port 4 registers.
■ Functions of Port 4 Registers
● Port 4 data register (PDR4)
The PDR4 register indicates the state of each pin of port 4.
● Port 4 data direction register (DDR4)
The DDR4 register specifies the direction of a data flow (input or output) at each pin (bit) of port 4. When
a DDR4 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the
port (pin) is set as an input port.
References:
• When a resource having output pins is used, the port functions as resource output pins regardless
of the value in the DDR4 register as long as the resource output enable bit corresponding to the
pins is set.
• To use a resource having input pins, reset the DDR4 register bit corresponding to each resource
input pin to "0" to place the port in input mode.
Table 9.7-3 lists the functions of the port 4 registers.
Table 9.7-3 Port 4 Register Functions
Register
Data
0
1
Setting an DDR5 bit to "0" enables the
The pin is at pin for a high-impedance.
Setting an DDR5 bit to "1" enables the
the high
pin functions as an output port, and the
level.
pin is set to the high level.
0
The
The output buffer is turned off to place
direction
the port in input mode.
latch is "0".
1
The
The output buffer is turned on to place
direction
the port in output mode.
latch is "1".
R/W: Read/write enabled
X : Undefined
: Empty bit
190
During writing
Setting an DDR5 bit to "0" enables the
The pin is at pin for a high-impedance.
Setting an DDR5 bit to "1" enables the
the low
pin functions as an output port, and the
level.
pin is set to the low level.
Port 4 data
register (PDR4)
Port 4 data
direction register
(DDR4)
During
reading
Read/
Write
Address
Initial value
R/W
000004H
–XXXXXXXB
R/W
000014H
–0000000B
CHAPTER 9 I/O PORT
9.7.2
Operation of Port 4
This section describes the operation of port 4.
■ Operation of Port 4
● Port operation in output mode
• Setting a bit of the DDR4 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR4 register in output mode is held in the output latch of the PDR and output to the
port pins.
• The PDR4 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR).
Note:
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as is. Before switching
the mode for the bits from input to output, therefore, write output data to the PDR register, then
specify output mode in the DDR register.
● Port operation in input mode
• Resetting a bit of the DDR4 register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pins are placed in a high impedance state.
• Data written to the PDR4 register in input mode is held in the output latch of the PDR but not output to
the port pins.
• The PDR4 register can be accessed in read mode to read the level value (0 or 1) at the port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state of the
resource enable bit takes precedence when specifying a switch between input and output. Even if a DDR4
register bit is "0", the corresponding port pin is used for resource output if the resource has been enabled for
output. Because the value at the pins can be read even if resource output is enabled, the resource output
value can be read.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as resource inputs.
To use an external signal for the resource, reset the DDR4 register to "0" to place the port in input mode.
191
CHAPTER 9 I/O PORT
● Port operation after a reset
• When the CPU is reset, the DDR4 register is initialized to "0". As a result, the output buffer is turned
off (I/O mode changes to input), and the pins are placed in a high impedance state.
• The PDR4 register is not initialized when the CPU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR4 register after the output data is set in the PDR4 register.
● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR4 register. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit.
Table 9.7-4 lists the states of the port 4 pins.
Table 9.7-4 States of Port 4 Pins
Pin
P40/SIN0 to
P46/PPG2
Normal operation
Sleep mode
Stop mode or time-base
timer mode (SPL = 0)
Stop mode or time-base
timer mode (SPL = 1)
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O port
Input shut down/output in
Hi-Z
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z: High impedance
192
CHAPTER 9 I/O PORT
9.8
Port 5
Port 5 is a general-purpose I/O port. It can also be used for A/D converter analog input.
The port pins can be switched in units of bits between the I/O port and analog input.
This section focuses on the general I/O port function. It provides the configuration of
port 5, lists its pins, shows a block diagram of the pins, and describes the
corresponding registers.
■ Port 5 Configuration
Port 5 consists of the following:
• General-purpose I/O pins/analog input pins (P50/AN0 to P57/AN7)
• Port 5 data register (PDR5)
• Port 5 data direction register (DDR5)
• Analog input enable register (ADER)
■ Port 5 Pins
The port 5 I/O pins are also used as analog input pins. The pins cannot be used as general-purpose I/O port
pins when they are used for analog input. Similarly, the port 5 I/O pins cannot be used for analog input
when they are used as a general-purpose I/O port. Table 9.8-1 lists the port 5 pins.
Table 9.8-1 Port 5 Pins
Port
Pin
I/O form
Port function
(single-chip mode)
Resource function
P50/AN0
P50
AN0
Analog input 0
P51/AN1
P51
AN1
Analog input 1
P52/AN2
P52
AN2
Analog input 2
P53/AN3
P53
AN3
Analog input 3
P54/AN4
P54
AN4
Analog input 4
P55/AN5
P55
AN5
Analog input 5
P56/AN6
P56
AN6
Analog input 6
P57/AN7
P57
AN7
Analog input 7
Port 5
Generalpurpose I/O
Input
Output
Analog/
CMOS
CMOS
Circuit
type
I
See "1.7 I/O Circuit Types", for information on the circuit types.
193
CHAPTER 9 I/O PORT
■ Block Diagram of Port 5 Pins
Figure 9.8-1 is a block diagram of port 5 pins.
Figure 9.8-1 Block Diagram of Port 5 Pins
ADER
Analog input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
For a pin used as an input port, reset the corresponding DDR5 register bit to "0", and also reset the
corresponding ADER register bit to "0".
For an pin used as an analog input pin, reset the corresponding DDR5 register bit to "0" and set the
corresponding ADER register bit to "1". In this case, the value read from the PDR5 register is "0".
■ Port 5 Registers
Port 5 registers are PDR5, DDR5 and ADER. The bits making up each register correspond to the port 5
pins on a one-to-one basis. Table 9.8-2 lists the port 5 pins and their corresponding register bits.
Table 9.8-2 Port 5 Pins and their Corresponding Register Bits
Port
Register bits and corresponding port pins
PDR5, DDR5, ADER
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Corresponding pin
P57
P56
P55
P54
P53
P52
P51
P50
Port 5
194
CHAPTER 9 I/O PORT
9.8.1
Port 5 Registers (PDR5, DDR5 and ADER)
This section describes the port 5 registers.
■ Functions of Port 5 Registers
● Port 5 data register (PDR5)
The PDR5 register indicates the state of each pin of port 5.
● Port 5 data direction register (DDR5)
The DDR5 register specifies the direction of a data flow (input or output) at each pin (bit) of port 5. When
a DDR5 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the
port (pin) is set as an input port.
● Analog input enable register (ADER)
Each bit of the ADER register specifies whether the corresponding port 5 pin is to be used as a generalpurpose I/O port or an analog input pin. Setting an ADER bit to "1" enables the corresponding pin for
analog input. Setting the bit to "0" enables the pin for general-purpose I/O.
Note:
Reference:
If a signal at an intermediate level is input in port I/O mode, input leak current flows. Therefore, for a
pin used for analog input, be sure to set the corresponding ADER bit to "1" for analog input.
When the CPU is reset, the DDR5 register is reset to "0" and the ADER register is set to "1" for
analog input.
Table 9.8-3 lists the functions of the port 5 registers.
Table 9.8-3 Port 5 Register Functions
Register
Port 5 data
register (PDR5)
Port 5 data
direction
register (DDR5)
Data
0
1
0
1
Analog input
0
enable register
1
(ADER)
R/W: Read/write enabled
X : Undefined
During
reading
The pin is at
the low level.
The pin is at
the high level.
The direction
latch is "0".
The direction
latch is "1".
Port I/O mode
During writing
The output buffer is turned off to
place the port in input mode.
The output buffer is turned on to
place the port in output mode.
Analog input mode
Read/
Write
Address
Initial value
R/W
000005H
XXXXXXXB
R/W
000015H
00000000B
R/W
000017H
11111111B
195
CHAPTER 9 I/O PORT
9.8.2
Operation of Port 5
This section describes the operation of port 5.
■ Operation of Port 5
● Port operation in output mode
• Setting a bit of the DDR5 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR5 register in output mode is held in the output latch of the PDR and output to the
port pins.
• The PDR5 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR).
Note:
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as is. Before switching
the mode for the bits from input to output, therefore, write the output data to the PDR register, then
specify output mode in the DDR register.
● Port operation in input mode
• Resetting a bit of the DDR5 and ADER register to "0" places the corresponding port pin in input mode.
• In input mode, the output buffer is turned off, and the pins are placed in a high impedance state.
• Data written to the PDR5 register in input mode is held in the output latch of the PDR but not output to
the port pins.
• The PDR5 register can be accessed in read mode to read the level value (0 or 1) at the port pins.
● Port operation for analog input
To use a port pin for analog input, write "1" to the corresponding ADER bit. Doing so disables the port
from operating as a general-purpose port pin and enables it to function as an analog input pin. When PDR5
is accessed in read mode in this situation, a value of "0" is read.
● Port operation after a reset
When the CPU is reset, the DDR5 register is initialized to "0" and the ADER register is initialized to "1" to
place the port in analog input mode. To use the port as a general-purpose port, write "0" to the ADER
register in advance to place the port in port I/O mode.
196
CHAPTER 9 I/O PORT
● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly. Note that the inputs are fixed at a
certain level to prevent leakage due to an open circuit.
Table 9.8-4 lists the states of the port 5 pins.
Table 9.8-4 States of Port 5 Pins
Pin
Normal operation
Sleep mode
Stop mode or time-base Stop mode or time-base
timer mode
timer mode
(SPL = 0)
(SPL = 1)
P50/AN0 to
Input shut down/output in
General-purpose I/O port General-purpose I/O port General-purpose I/O port
P57/AN7
Hi-Z
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z: High impedance
197
CHAPTER 9 I/O PORT
9.9
Port 6
Port 6 is a general-purpose I/O port. It can also be used for resource input and output.
The port pins can be switched in units of bits between the I/O port and resource. This
section focuses on the general I/O port function. It provides the configuration of port 6,
lists its pins, shows a block diagram of the pins, and describes the corresponding
registers.
■ Port 6 Configuration
Port 6 consists of the following:
• General-purpose I/O pins/resource I/O pins (P60/SIN1 to P63/INT7)
• Port 6 data register (PDR6)
• Port 6 data direction register (DDR6)
■ Port 6 Pins
The port 6 I/O pins are also used as resource I/O pins. The pins cannot be used as general-purpose I/O port
pins when they are used as resource I/O pins. Table 9.9-1 lists the port 6 pins.
Table 9.9-1 Port 6 Pins
Port
Pin
I/O form
Port function
(single-chip mode)
P60/SIN1
P60
P61/SOT1
P61
P62/SCK1
P62
P63/INT7
P63
Port 6
Generalpurpose I/O
Resource function
SIN1
UART1 data input
SOT1
UART1 data output
SCK1
UART1 serial clock I/O
INT7
External interrupt input
See "1.7 I/O Circuit Types", for information on the circuit types.
198
Input
Output
CMOS
(hysteresis)
CMOS
Circuit
type
F
CHAPTER 9 I/O PORT
■ Block Diagram of Port 6 Pins
Figure 9.9-1 is a block diagram of port 6 pins.
Figure 9.9-1 Block Diagram of Port 6 Pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
External interrupt enable
■ Port 6 Registers
Port 6 registers are PDR6 and DDR6. The bits making up each register correspond to the port 6 pins on a
one-to-one basis. Table 9.9-2 lists the port 6 pins and their corresponding register bits.
Table 9.9-2 Port 6 Pins and their Corresponding Register Bits
Port
Register bits and corresponding port pins
PDR6, DDR6
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
–
–
–
–
P63
P62
P61
P60
Port 6
Corresponding pin
199
CHAPTER 9 I/O PORT
9.9.1
Port 6 Registers (PDR6 and DDR6)
This section describes the port 6 registers.
■ Functions of Port 6 Registers
● Port 6 data register (PDR6)
The PDR6 register indicates the state of each pin of port 6.
● Port 6 data direction register (DDR6)
The DDR6 register specifies the direction of a data flow (input or output) at each pin (bit) of port 6. When
a DDR6 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the
port (pin) is set as an input port.
Notes:
• When a resource having output pins is used, the port functions as resource output pins regardless
of the value in the DDR6 register as long as the resource output enable bit corresponding to the
pins is set.
• To use a resource having input pins, reset the DDR6 register bit corresponding to each resource
input pin to "0" to place the port in input mode.Table 9.9-3 lists the functions of the port 6
registers.
Table 9.9-3 Port 6 Register Functions
Register
Data
During
reading
During writing
0
The pin is at
the low level.
The output latch is loaded with "0".
When the pin functions as an
output port, the pin is set to the low
level.
1
The pin is at
the high level.
The output latch is loaded with "1".
When the pin functions as an
output port, the pin is set to the
high level.
0
The direction
latch is "0".
The output buffer is turned off to
place the port in input mode.
1
The direction
latch is "1".
The output buffer is turned on to
place the port in output mode.
Port 6 data
register (PDR6)
Port 6 data
direction
register
(DDR6)
R/W: Read/write enabled
X : Undefined
: Empty bit
200
Read/
Write
Address
Initial value
R/W
000006H
----XXXXB
R/W
000016H
----0000B
CHAPTER 9 I/O PORT
9.9.2
Operation of Port 6
This section describes the operation of port 6.
■ Operation of Port 6
● Port operation in output mode
• Setting a bit of the DDR6 register to "1" places the corresponding port pin in output mode.
• Data written to the PDR6 register in output mode is held in the output latch of the PDR and output to the
port pins.
• The PDR6 register can be accessed in read mode to read the value at the port pins (the same value as in
the output latch of the PDR).
Note:
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been specified
for input, a value input from the pins is written to the output latch and output as is. Before switching
the mode for the bits from input to output, therefore, write the output data to the PDR register, then
specify output mode in the DDR register.
● Port operation in input mode
• Resetting a bit of the DDR6 register to "0" places the corresponding port pin in input mode.
•
In input mode, the output buffer is turned off, and the pins are placed in a high impedance state.
• Data written to the PDR6 register in input mode is held in the output latch of the PDR but not output to
the port pins.
• The PDR6 register can be accessed in read mode to read the level value (0 or 1) at the port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state of the
resource enable bit takes precedence when specifying a switch between input and output. Even if a DDR6
register bit is "0", the corresponding port pin is used for resource output if the resource has been enabled for
output. Because the value at the pins can be read even if resource output is enabled, the resource output
value can be read.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as resource inputs.
To use an external signal for the resource, reset the DDR6 register to "0" to place the port in input mode.
201
CHAPTER 9 I/O PORT
● Port operation after a reset
• When the CPU is reset, the DDR6 register is initialized to "0". As a result, the output buffer is turned
off (I/O mode changes to input), and the pins are placed in a high impedance state.
• The PDR6 register is not initialized when the CPU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR6 register after output data is set in the PDR6 register.
● Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR6 register. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit.
Table 9.9-4 lists the states of the port 6 pins.
Table 9.9-4 States of Port 6 Pins
Pin
P60/SIN1 to
P63/INT7
Normal operation
Sleep mode
Stop mode or time-base Stop mode or time-base
timer mode
timer mode
(SPL = 0)
(SPL = 1)
General-purpose I/O port General-purpose I/O port General-purpose I/O port
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z: High impedance
202
Input shut down/output in
Hi-Z
CHAPTER 9 I/O PORT
9.10
Sample I/O Port Program
This section provides a sample program using I/O port pins.
■ Sample I/O Port Program
● Processing specifications
• Ports 0 and 1 are used to turn on all segments of a seven-segment (eight-segment if the decimal point is
included) LED.
• Pin P00 corresponds to the anode common pin of the LED and pins P10 to P17 correspond to the
segment pins.
Figure 9.10-1 is an example of connecting the eight-segment LED to the MB90460/465 series ports.
Figure 9.10-1 Example of Eight-segment LED Connection
MB90460/465 series
P00
P17
P16
P15
P14
P13
P12
P11
P10
● Coding example
PDR
EQU
000000H
PDR1
EQU
000001H
DDR0
EQU
000010H
DDR1
EQU
000011H
;-----------------------------Main program---------------------------------------------------------------------------------CODE
CSEG
START:
; Initialization
MOV
I :PDR0, #00000000B
; Puts P00 at a low level (#XXXXXXX0B)
MOV
I:DDR0, #11111111B
; Puts all port 0 bits in output mode
MOV
I:PDR1, #11111111B
; Sets all port 1 bits to "1"
MOV
I:DDR1, #11111111B
; Puts all port 1 bits in output mode
CODE
ENDS
;-------------------------------------------------------------------------------------------------------------------------------END
START
203
CHAPTER 9 I/O PORT
204
CHAPTER 10
TIME-BASE TIMER
This chapter describes the functions and operation of
the time-base timer.
10.1 Overview of the Time-base Timer
10.2 Configuration of the Time-base Timer
10.3 Time-base Timer Control Register (TBTC)
10.4 Time-base Timer Interrupts
10.5 Operation of the Time-base Timer
10.6 Usage Notes on the Time-base Timer
10.7 Sample Program for the Time-base Timer Program
205
CHAPTER 10 TIME-BASE TIMER
10.1
Overview of the Time-base Timer
The time-base timer is an 18-bit free-run counter (time-base counter) that counts up in
synchronization with the internal count clock (one-half of the source oscillation). The
timer has an interval timer function that can select four intervals.
The time-base timer also has functions for timer output of the oscillation stabilization
time and for supplying the clocks for the watchdog timer.
■ Interval Timer Function
The interval timer function repeatedly generates an interrupt request at a given interval.
• An interrupt request is generated when the interval timer bit for the time-base counter overflows.
• The interval timer bit (interval) can be selected from four types. Table 10.1-1 lists the intervals for the
time-base timer.
Table 10.1-1 Intervals for the Time-base Timer
Internal count clock cycle
Interval cycle
212 / HCLK (Approx. 1.0 ms)
214 / HCLK (Approx. 4.1 ms)
2 / HCLK (0.5 µs)
216 / HCLK (Approx. 16.4 ms)
219 / HCLK (Approx. 131.1 ms)
HCLK: Oscillation clock
Values in parentheses are for a 4 MHz oscillation clock.
206
CHAPTER 10 TIME-BASE TIMER
■ Clock Supply Function
The clock supply function supplies clocks to the oscillation stabilization time timer and to some peripheral
functions.
Table 10.1-2 lists the cycle times of clocks supplied from the time-base timer to each peripheral.
Table 10.1-2 Clock Cycle Time supplied from the Time-base Timer
Clock destination
Clock cycle time
213 / HCLK (Approx. 2.0 ms)
Oscillation
stabilization time
Remarks
Oscillation stabilization time for ceramic vibrator
215 / HCLK (Approx. 8.2 ms)
Oscillation stabilization time for crystal vibrator
218 / HCLK (Approx. 65.4 ms)
212 / HCLK (Approx. 1.0 ms)
214 / HCLK (Approx. 4.1 ms)
Count-up clock for watchdog timer
Watchdog timer
216 / HCLK (Approx. 16.4 ms)
219 / HCLK (Approx. 131.1 ms)
HCLK: Oscillation clock
Values in parentheses occurs during operation of the 4 MHz oscillation clock.
Reference:
The oscillation stabilization time is the yardstick because the oscillation cycle time is unstable as
soon as oscillation starts.
207
CHAPTER 10 TIME-BASE TIMER
10.2
Configuration of the Time-base Timer
The time-base timer consists of the following four blocks:
• Time-base timer counter
• Counter clear circuit
• Interval timer selector
• Time-base timer control register (TBTC)
■ Block Diagram of the Time-base Timer
Figure 10.2-1 shows the block diagram of the time-base timer.
Figure 10.2-1 Block Diagram of the Time-base Timer
To watchdog timer
Time-base
timer counter
Divide-by
-two HCLK
× 21 × 2 2 × 23
...
. . . × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
OF
OF
OF
OF
To the oscillation
setting time selector
in the clock control
section
Counter clear
Power-on reset
Stop mode start
CKSCR: MCS = 1 to 0(*1)
Counter
clear circuit
TBOF clear
OF
Interval
timer selector
TBOF set
Time-base timer
interrupt signal
#36 (24H)(*2)
—
—
—
TBIE TBOF
OF:Overflow
HCLK: Oscillation clock
*1 :Switching of the machine clock from the oscillation clock to the PLL clock
*2 :Interrupt number
TBR TBC1 TBC0
Time-base timer
interrpt register (TBTC)
● Time-base timer counter
This 18-bit up counter uses the divide-by-two clock of the oscillation clock (HCLK) as the count clock.
● Counter clear circuit
Used to clear the counter by writing "0" to the TBTC:TBR bit, by a power-on reset or by transition to stop
mode (LPMCR: STP = 1).
● Interval timer selector
Selects one of four outputs of the time-base timer counter. An overflow of the selected bit becomes an
interrupt cause.
● Time-base timer control register (TBTC)
Selects the interval, clears the counter, controls an interrupt request, and checks the status.
208
CHAPTER 10 TIME-BASE TIMER
10.3
Time-base Timer Control Register (TBTC)
The time-base timer control register (TBTC) selects the interval, clears the counter,
controls interrupts, and checks the status.
■ Time-base Timer Control Register (TBTC)
Figure 10.3-1 Time-base Timer Control Register (TBTC)
bit 15
Address
0000A9H RESV
R/W
14
13
-
-
12
11
10
9
8
7
0
TBIE TBOF TBR TBC1 TBC0
R/W
R/W
W
R/W
Initial value
(WDTC)
1XX00100B
R/W
TBC1 TBC0
Interval selection bit
0
0
212/HCLK (Approx. 1.0 ms)
0
1
214/HCLK (Approx. 4.1 ms)
1
0
216/HCLK (Approx. 16.4 ms)
1
1
219/HCLK (Approx. 131 ms)
Values in parentheses are for a 4 MHz oscillation clock.
Time-base timer initialization bit
TBR
During reading
During writing
Clearing of the time-base timer
counter and TBOF bit
0
-
1
The read value is always "1".
TBOF
No change, no effect on other bits.
Interrupt request flag bit
During reading
0
No overflow from the
specified bit
Clearing of this bit
1
Overflow from the specified
bit
No change, no effect on other bits.
TBIE
Interrupt request enable bit
0
Interrupt request output disabled
1
Interrupt request output enabled
RESV
R/W:
W:
-:
x:
Read/write
Write only
Not used
Undefined
Initial value
During writing
Reserved bit
Always write "1" to this bit.
209
CHAPTER 10 TIME-BASE TIMER
Table 10.3-1 Function Description of Each Bit in the Time-base Timer Control Register (TBTC)
Bit name
Function
bit15
RESV:
Reserved bit
(Note)
Always write "1" to this bit.
bit14,
bit13
Not used
• When read, the value is undefined.
• Writing has no effect on operation.
bit12
TBIE:
Interrupt request
enable bit
• Used to enable or disable the output of an interrupt request to the CPU.
• When this bit and the interrupt request flag bit (TBOF) are "1", an interrupt request is
output.
bit11
TBOF:
Interrupt request
flag bit
• This bit is set to "1" when the bit specifying the time-base timer counter overflows.
• When this bit and the interrupt request enable bit (TBIE) are 1, an interrupt request is
output.
• During writing, this bit is cleared with "0". If "1" is written, the bit does not change and
there is no effect.
(Note)
• To clear the TBOF bit, disable the time-base timer
interrupt by specifying the TBIE
bit or processor status (PS) ILM bit.
• The TBOF bit is cleared by writing "0", by a transition to stop mode, by clearing of the
time-base timer with the TBR bit or by a reset.
bit10
TBR:
Time-base timer
initialization bit
• Used to clear the time-base timer counter.
• When "0" is written to this bit, the counter is cleared and the TBOF bit is cleared. If "1" is
written, the bit does not change and there is no effect.
(Reference)
The read value is always "1".
bit9,
bit8
TBC1, TBC0:
Interval
selection bit
• Used to select an interval timer cycle.
• The bit for the interval timer of the time-base timer counter is specified.
• Four types of interval can be selected.
210
CHAPTER 10 TIME-BASE TIMER
10.4
Time-base Timer Interrupts
The time-base timer can generate an interrupt request when the bit specifying the timebase timer counter overflows.
■ Time-base Timer Interrupts
The interrupt request flag bit (TBTC: TBOF) is set to "1" when the time-base timer counter counts up with
the internal count clock and when the bit for the selected interval timer bit overflows. If the interrupt
request enable bit has been enabled (TBTC: TBIE = 1), an interrupt request (#36) is generated in the CPU.
Write "0" to the TBOF bit in the interrupt handling routine to clear the interrupt request. When the
specified bit overflows, the TBOF bit is set regardless of the TBIE bit value.
Note:
Clear the interrupt request flag bit (TBTC: TBOF) while a time-base timer interrupt is disabled by
setting the TBIE bit or the processor status (PS) ILM bit.
Reference:
When the TBOF bit is "1", if the TBIE bit status is switched from disable to enable (0 -> 1), an
interrupt request occurs immediately.
■ Time-base Timer Interrupts and EI2OS
Table 10.4-1 lists the time-base timer interrupt and EI2OS.
Table 10.4-1 Time-base Interrupts and EI2OS
Interrupt level setting register
Vector table address
EI2OS
Interrupt number
#36 (24H)
Register name
Address
Lower
Upper
Bank
ICR12
0000BCH
FFFF6CH
FFFF6DH
FFFF6EH
∆
∆: Usable when an interrupt cause that shares the ICR is not used.
Note:
ICR12 is common to the time-base timer interrupt and input capture channels 2/3 interrupt.
Interrupts can be used for two applications, but the interrupt level is the same.
211
CHAPTER 10 TIME-BASE TIMER
10.5
Operation of the Time-base Timer
The time-base timer provides the interval timer function and the clock supply function
that supplies clocks to some peripheral functions.
■ Operation of the Interval Timer Function (Time-base Timer)
The interval timer function generates an interrupt request for each interval
The setting in Figure 10.5-1 is required to all the timer to operate as an interval timer.
Figure 10.5-1 Setting of the Time-base Timer
bit
TBTC
15
14
13
RESV
-
-
1
12
11
10
9
8
TBIE TBOF TBR TBC1 TBC0
0
7
0
WDTC
0
: Used
0 : Set "0"
1 : Set "1"
• The time-base timer counter continues counting up in synchronization with the internal count clock
(one-half of the oscillation clock) as long as the clock is being oscillated.
• When the counter is cleared (TBR = 0), it counts up from "0". When the interval timer bit overflows,
the interrupt request flag bit (TBOF) is set to "1". If interrupt request output has been enabled (TBIE =
1), an interrupt is generated for each selected interval based on the cleared time.
• The interval may become longer than the time set because of time-base timer clearing.
212
CHAPTER 10 TIME-BASE TIMER
■ Oscillation Stabilization Time Timer Function
The time-base timer is also used as the oscillation stabilization time timer for oscillation and the PLL
clocks.
The oscillation stabilization time is set for the interval from the time the counter counts up from "0" (count
clear) until the oscillation stabilization time bit overflows. When control returns from time-base timer
mode to PLL clock mode, the oscillation stabilization time starts from the middle of counting because the
time-base timer counter has been not cleared. Table 10.5-1 shows the clearing of the time-base counter and
the oscillation stabilization times.
Table 10.5-1 Time-base Timer Counter Clearing and Oscillation Settling Times
Operation
Counter clear
TBOF clear
O
O
O
O
Oscillation clock oscillation stabilization time
Releasing of stop mode
O
O
Oscillation clock oscillation stabilization time
(at return to main clock mode)
Transition from oscillation clock mode
to PLL clock mode (MCS = 1 → 0)
O
O
PLL clock oscillation stabilization time
Releasing of time-base timer mode
X
X
PLL clock oscillation stabilization time (at
return to PLL clock mode)
Releasing of sleep mode
X
X
TBTC: Writing of 0 to TBR
Oscillation settling time
Power-on reset
Watchdog reset
O: Available
X: Not available
■ Clock Supply Function
The time-base timer supplies clocks to the watchdog timer. Clearing of the time-base counter affects
operation of the watchdog timer.
213
CHAPTER 10 TIME-BASE TIMER
10.6
Usage Notes on the Time-base Timer
Notes about the effects on peripheral functions of clearing interrupt requests and the
time-base timer are given below.
■ Time-base Timer Usage Notes
● Clearing interrupt requests
The TBOF bit of the time-base timer control register must be cleared while a time-base timer interrupt is
masked by the TBIE bit or the interrupt level mask register (ILM) of the processor status (PS).
● Effects of time-base timer clearing
Clearing of the time-base timer counter affects the following operations:
• When the time-base timer is using the interval timer function (interval interrupt)
• When the watchdog timer is being used
● Use of the time-base timer as the oscillation stabilization time timer
At power-on, the source oscillation of the main clock stops in main stop mode. After oscillator operation
starts, the operating clock supplied by the time-base timer is used to take the oscillation stabilization wait
time of the main clock. An appropriate oscillation stabilization wait time must be selected based on the
type of oscillating element connected to the main clock oscillator (clock generation section). See "5.5
Oscillation Stabilization Wait Interval", for details.
● Notes on peripheral functions to which clocks are supplied from the time-base timer
In the mode in which the main clock source oscillation stops, the counter is cleared and time-base timer
operation stops. When the time-base timer counter is cleared, the clock supplied from the time-base timer
is supplied from its initial state. As a result, the H level is shortened and the L level lengthened 1/2 cycle.
Although the clock for the watchdog timer is also supplied from its initial state; the watchdog timer
operates in normal cycles because the watchdog timer counter is cleared at the same time.
214
CHAPTER 10 TIME-BASE TIMER
■ Operation of the Time-base Timer
The following operations are shown in Figure 10.6-1:
• A power-on reset occurs.
• Sleep mode is entered during operation of the interval timer function.
• A counter clear request is issued.
When stop mode is entered, the time-base timer is cleared and its operation stops. On return from stop
mode, the time-base timer counts the oscillation stabilization time.
Figure 10.6-1 Time-base Timer Operations
Counter value
3FFFFH
Cleared by transition to
stop mode.
Oscillation stabilization
delay overflow
0000H
CPU operation starts
Power-on reset
(optional)
Counter clear
(TBTC: TBR = 0)
Interval cycle
(TBTC: TBC1, TBC0 = 11B)
Cleared by the interrupt
handling routine.
TBOF bit
Sleep mode
TBIE bit
SLP bit
(STBC register)
STP bit
(STBC register)
Stop
Releasing of interval interrupt sleep
Releasing of Stop by an external interrupt
When 11B has been set in the interval selection bit
(TBTC:TBC1,TBC0) of the time-base timer control register
: Indicates the oscillation stabilization time.
215
CHAPTER 10 TIME-BASE TIMER
10.7
Sample Program for the Time-base Timer Program
This section contains a sample program for the time-base timer.
■ Sample Program for the Time-base Timer
● Processing
An interval interrupt of 212 / HCLK (HCLK: oscillation clock) is repeatedly generated. The interval
becomes approx. 1.0 ms (during 4 MHz operation).
● Coding example
ICR12
EQU
0000BCH
;Time-base timer interrupt control register
TBTC
EQU
0000A9H
;Time-base timer control register
TBOF
EQU
TBTC:3
;Interrupt request flag bit
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
;Assumes that stack pointer (SP) has already
been initialized
AND
CCR,#0BFH
;Disables interrupts
MOV
I:ICR12 #00H
;Interrupt level 0 (highest)
MOV
I:TBTC,#10010000B
;Fixes upper 3 bits
;Enables interrupts and clears TBOF
;Clears counter
;Selects interval 212/HCLK
LOOP:
MOV
ILM,#07H
;Sets PS ILM to level 7
OR
CCR,#40H
;Enables interrupts
MOV
A,#00H
;Endless loop
MOV
A,#01H
BRA
LOOP
;-------Interrupt program--------------------------------------------------------------------------------------------WARI:
CLRB
;
:
;
User handling
;
:
RETI
CODE
216
ENDS
I:TBOF
;Clears interrupt request flag
;Returns from interrupt
CHAPTER 10 TIME-BASE TIMER
;-------Vector setting-------------------------------------------------------------------------------------------------VECT
VECT
CSEG
ABS=0FFH
ORG
0FF6CH
DSL
WARI
ORG
0FFDCH
DSL
START
DB
00H
;Sets vector for interrupt #36 (24H)
;Sets reset vector
;Sets single-chip mode
ENDS
END
START
217
CHAPTER 10 TIME-BASE TIMER
218
CHAPTER 11
WATCHDOG TIMER
This chapter describes the functions and operation of
the watchdog timer.
11.1 Overview of the Watchdog Timer
11.2 Configuration of the Watchdog Timer
11.3 Watchdog Timer Control Register (WDTC)
11.4 Operation of the Watchdog Timer
11.5 Usage Notes on the Watchdog Timer
11.6 Sample Program for the Watchdog Timer
219
CHAPTER 11 WATCHDOG TIMER
11.1
Overview of the Watchdog Timer
The watchdog timer is a 2-bit counter that uses the time-base timer supply clock as the
count clock. After activation, if the watchdog timer is not cleared within a given time,
the CPU is reset.
■ Watchdog Timer Function
The watchdog timer is a counter for handling program crashes. Once the watchdog timer is activated, it
must be regularly cleared within a given time. If the program results in an endless loop and the watchdog
timer is not cleared over a given time, a watchdog reset is generated for the CPU.
Table 11.1-1 lists the watchdog timer intervals. If the watchdog timer is not cleared, a watchdog reset is
generated between the minimum time and maximum time. Clear the counter within the minimum time
listed in this table.
Table 11.1-1 Intervals for the Watchdog Timer
Interval
Minimum*
Maximum*
Oscillation clock cycle count
Approx. 3.58 ms
Approx. 4.61 ms
214 ±211 cycle
Approx. 14.33 ms
Approx. 18.3 ms
216 ±213 cycle
Approx. 57.23 ms
Approx. 73.73 ms
218 ±215 cycle
Approx. 458.75 ms
Approx. 589.82 ms
221 ±218 cycle
* Value during operation of the 4 MHz oscillation clock
The maximum and minimum watchdog timer intervals and the oscillation clock cycle count depend on the
clear timing.
The interval is 3.5 to 4.5 times longer than the cycle of the count clock (time-base timer supply clock).
See "11.4 Operation of the Watchdog Timer".
Note:
The watchdog counter consists of a 2-bit counter that uses the carry signals of the time-base timer
as count clocks. Therefore, if the time-base timer is cleared, the watchdog reset generation time
may become longer than the time set.
Reference:
At activation, the watchdog timer is initialized by a power-on or watchdog reset, and is placed in
stopped status. The watchdog timer is cleared by an external pin reset, software reset, writing to the
WTE bit (watchdog timer control register), sleep mode or transition to stop mode. However, It is not
stopped.
220
CHAPTER 11 WATCHDOG TIMER
11.2
Configuration of the Watchdog Timer
The watchdog timer consists of the following five blocks:
• Count clock selector
• Watchdog counter (2-bit counter)
• Watchdog reset generator
• Counter clear control circuit
• Watchdog timer control register (WDTC)
■ Block Diagram of the Watchdog Timer
Figure 11.2-1 shows the block diagram of the watchdog timer.
Figure 11.2-1 Block diagram of the watchdog timer
Watchdog timer control register (WDTC)
Watchdog timer
Activation
with CLR
Start of sleep mode
Start of hold status mode
Start of stop mode
Counter
clear control
circuit
Count
clock
selector
2-bit
counter
OverWatchdog
flow
reset generator
To the internal
reset generator
Clear
(Time-base timer counter)
One-half of HCLK
HCLK: Oscillation clock
● Count clock selector
This circuit is used to select the count clock of the watchdog timer from four types of time-base timer
outputs. This determines the watchdog reset generation time.
● Watchdog counter (2-bit counter)
This 2-bit up counter uses the time-base timer output as the count clock.
● Watchdog reset generator
Used to generate the reset signal by an overflow of the watchdog counter.
● Counter clear circuit
Used to clear the watchdog counter and to control the operation or stopping of the counter.
● Watchdog timer control register (WDTC)
Used to activate or clear the watchdog timer; holds the reset generation cause.
221
CHAPTER 11 WATCHDOG TIMER
11.3
Watchdog Timer Control Register (WDTC)
The watchdog timer control register (WDTC) activates and clears the watchdog timer,
and displays the reset cause.
■ Watchdog Timer Control Register (WDTC)
Figure 11.3-1 shows the watchdog timer control register (WDTC). Table 11.3-1 describes the function of
each bit of the watchdog timer control register (WDTC).
Figure 11.3-1 Watchdog Timer Control Register (WDTC)
8
bit 15
Address
0000A8H
(TBTC)
7
6
PONR
-
R
5
4
3
2
WRST ERST SRST WTE
R
R
R
W
1
0
WT1
WT0
W
W
Initial value
X-XXX111B
Interval selection bit (for 4 MHz HCLK)
WT1
Interval
WT0
Minimum
Maximum
Oscillation clock
cycle count
0
0
Approx. 3.58 ms
Approx. 4.61 ms
214 ±211 cycle
0
1
Approx. 14.33 ms
Approx. 18.3 ms
216 ±213 cycle
1
0
Approx. 57.23 ms
Approx. 73.73 ms
218 ±215 cycle
1
1
Approx. 458.75 ms Approx. 589.82 ms
221 ±218 cycle
HCLK: Oscillation clock
Watchdog control bit
WTE
0
- Activation of the watchdog timer
(At first write after reset)
- Clearing of the watchdog timer
(At second or subsequent write after reset)
1
No operation
Reset cause bit
Reset cause
PONR WRST ERST SRST
R: Read only
W: Write only
X: Undefined
*: Retains the previous status.
: Initial value
1
X
X
X
Power-on
*
1
*
*
Watchdog timer
*
*
1
*
External pin (RSTX input)
*
*
*
1
RST bit (software reset)
The interval becomes 3.5 to 4.5 times longer than the count clock (time-base timer output value) cycle. For
details, see "11.4 Operation of the Watchdog Timer".
222
CHAPTER 11 WATCHDOG TIMER
Table 11.3-1 Function Description of Each bit of the Watchdog Timer Control Register (WDTC)
Bit name
bit7,
PONR, WRST,
bit5
ERST, SRST:
to
Reset cause bits
bit3
bit2
WTE:
Watchdog timer
control bit
bit1, WT1, WT0:
bit0 Interval selection bit
Function
• Read-only bits for indicating the reset cause. If more than one reset cause occurs, the bit
for each reset cause occurring is set to "1".
• These bits are all cleared to "0" after the watchdog timer control register (WDTC) is read.
• At power-on, the contents of the bits other than the PONR bit are not guaranteed.
Therefore, when the PONR bit is "1", ignore the contents of the bits other than the PONR
bit.
• When "0" is written to this bit, the watchdog timer is activated (first write after reset) or
the 2-bit counter is cleared (second or subsequent write after reset).
• Writing "1" does not affect operation.
• Used to select the watchdog timer interval.
• Only data at watchdog timer activation is valid.
Data written after watchdog timer activation is ignored.
• These bits are write-only.
223
CHAPTER 11 WATCHDOG TIMER
11.4
Operation of the Watchdog Timer
The watchdog timer generates a watchdog reset by an overflow of the watchdog
counter.
■ Watchdog Timer Operation
Operation of the watchdog timer requires the setting in Figure 11.4-1.
Figure 11.4-1 Setting of the Watchdog Timer
8
bit 15
WDTC
TBTC
: Used
0 : Set "0"
7
6
PONR
-
5
4
3
2
1
0
WRST ERST SRST WTE WT1 WT0
0
● Activating the watchdog timer
• The watchdog timer is activated when the first 0 after reset is written to the WTE bit of the watchdog
timer control register (WDTC). Specify the interval by specifying the WT1 and WT0 bits of the
watchdog timer control register at the same time.
• When watchdog timer activation starts, it can be stopped only by a power-on or its own reset.
● Clearing the watchdog timer
• When a second or subsequent "0" is written to the WTE bit, the 2-bit counter of the watchdog timer is
cleared. If the counter is not cleared within the time interval, it overflows and a watchdog reset occurs.
• The watchdog counter is cleared by reset generation, sleep mode or stop mode, transition to clock mode.
● Intervals for the watchdog timer
Figure 11.4-2 shows the relationship between the clear timing of the watchdog timer and intervals. The
interval changes according to the clear timing of the watchdog timer and requires 3.5 to 4.5 times longer
than the count clock cycle.
● Checking a reset cause
A reset cause can be determined by checking the PONR, WRST, ERST and SRST bits of the watchdog
timer control register (WDTC) after a reset.
224
CHAPTER 11 WATCHDOG TIMER
Figure 11.4-2 Clear Timing and Watchdog Timer Intervals
[WDG timer block diagram]
2-bit counter
Clock
selector
Divide-bytwo circuit
Divide-bytwo circuit
Reset
circuit
Reset signal
Count enabling and clearing
WTE bit
Count enable
output circuit
[Minimum interval] When the WTE bit is cleared immediately before the count clock rises:
Counter clearing
Count start
Count clock a
Divide-by-two
value b
Divide-by-two
value c
Count enabling
Reset signal d
7 x (count clock cycle/2)
WTE bit clearing
Watchdog reset generation
[Maximum interval] When the WTE bit is cleared immediately after the count clock rises:
Counter clearing
Count start
Count clock a
Divide-by-two
value b
Divide-by-two
value c
Count enabling
Reset signal d
9 x (count clock cycle/2)
WTE bit clearing
Watchdog reset generation
225
CHAPTER 11 WATCHDOG TIMER
11.5
Usage Notes on the Watchdog Timer
Notes on using the watchdog timer are given below.
■ Usage Notes on the Watchdog Timer
● Stopping the watchdog timer
Once the watchdog timer is activated, it cannot stop until a power-on or watchdog reset occurs. The
watchdog timer counter is cleared by an external reset or software reset; however, the watchdog timer does
not stop.
● Intervals
Since a carry signal of the time-base timer is used as the count clock for the interval, the watchdog timer
interval may become longer than the setting time when the time-base timer is cleared.
● Selecting the interval
The interval can be set when the watchdog timer is activated. Data written during operations other than
activation is ignored.
● Notes on program creation
When a program that repeatedly clears the watchdog timer in the main loop is created, the processing time
of the main loop including the interrupt processing must be equal to or less than the minimum watchdog
timer interval.
● Watchdog timer operation in time-base timer mode
The time-base timer operates while the time-base timer mode is set. The watchdog timer, however, is
temporarily stopped.
226
CHAPTER 11 WATCHDOG TIMER
11.6
Sample Program for the Watchdog Timer
This section contains a sample program for the watchdog timer.
■ Sample Program for the Watchdog Timer
● Processing
• The watchdog timer is cleared every time in the main program loop.
• The main loop must make one iteration within the minimum watchdog timer interval.
● Coding example
WDTC
EQU
0000A8H
;Watchdog timer control register
WTE
EQU
WDTC:2
;Watchdog control bit
;-------Main program-----------------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
;Assumes that stack pointer (SP) has already
been initialized
WDG_START:
MOV
WDTC,#00000011B ;Activates watchdog timer
;Selects the interval 221
218 cycle
;--------Main loop---------------------------------------------------------------------------------------------------------MAIN:
CLRB
;
:
;
User processing
;
:
JMP
CODE
I:WTE
;Clears watchdog timer
Clears this bit regularly
MAIN
;Loops in less time than the watchdog
timer interval
ENDS
;--------Vector setting----------------------------------------------------------------------------------------------------VECT
VECT
CSEG
ABS=0FFH
ORG
0FFDCH
DSL
START
DB
00H
;Sets reset vector
;Sets single-chip mode
ENDS
END
START
227
CHAPTER 11 WATCHDOG TIMER
228
CHAPTER 12
16-BIT RELOAD TIMER
The chapter describes the functions and operation of
the 16-bit reload timer.
12.1 Overview of the 16-bit Reload Timer
12.2 Block Diagram of the 16-bit Reload Timer
12.3 16-bit Reload Timer Pins
12.4 16-bit Reload Timer Registers
12.5 16-Bit Reload Timer Interrupts
12.6 Operation of the 16-bit Reload Timer
12.7 Usage Notes on the 16-bit Reload Timer
12.8 Sample Programs for the 16-bit Reload Timer
229
CHAPTER 12 16-BIT RELOAD TIMER
12.1
Overview of the 16-bit Reload Timer
The 16-bit reload timer functions in the two modes shown below, either of which can be
selected. It is synchronized with three types of internal clocks for counting down in
internal clock mode, and it counts down by detecting an optional edge input to the
external pin in event counter mode.
This timer defines that an underflow condition results when the counter value changes
from 0000H to FFFFH. Thus, an underflow will occur after an interval of [reload register
setting value + 1] counts.
Either of two modes can be selected for counting. In load mode, the value set for the
count is reloaded to repeat counting for an underflow. In single-shot mode, the
counting is stopped with an underflow.
The counter underflow allows the occurrence of an interrupt and coordination with the
extended intelligent I/O service (EI2OS).
The MB90460/465 series 16-bit reload timer has two built-in channels.
■ Overview of the 16-bit Reload Timer
● 16-bit reload timer operating modes
Table 12.1-1 lists the operating modes of the 16-bit reload timer.
Table 12.1-1 16-bit Reload Timer Operating Modes
Clock mode
Counter operation
Reload mode
Internal clock mode
Event count mode
(external clock mode)
One-shot mode
Reload mode
One-shot mode
Operation of 16-bit reload timer
Software trigger operation
External trigger operation
External gate input operation
Software trigger operation
■ Internal Clock Mode
Internal clock mode allows selection of one of three types of internal clock for the following operations:
● Software trigger operation
When "1" is written to the TRG bit of the timer control status register (TMCSRL0/TMCSRL1), counting
starts. Trigger input by the TRG bit is always valid for external trigger input as well as for external gate
input.
● External trigger operation
When selected edges (rising, falling, and both edges) are input to the TIN0 and TIN1 pins, counting starts
in channel 0 and 1 respectively.
● External gate input operation
While the selected signal level (L or H) is being input to TIN0 and TIN1 pins, counting continues in
channel 0 and 1 respectively.
230
CHAPTER 12 16-BIT RELOAD TIMER
■ Event Count Mode (External Clock Mode)
When selected valid edges (rising, falling and both edges) are input to TIN0 and TIN1 pins, the
timer counts down at these edges in channel 0 and 1 respectively.
When an external clock with a constant period is used, this timer can also be used as an interval
timer.
■ Counter Operation
● Reload mode
When an underflow (from 0000H to FFFFH) occurs during counting down, the count setting value is
reloaded to continue counting. Since the 16-bit reload timer causes an interrupt request to occur for an
underflow condition, it can be used as an interval timer.
A toggle waveform inverted at each underflow cab also be output from TO0 and TO1 pins.
Table 12.1-2 lists the intervals for the 16-bit reload timer.
Table 12.1-2 Intervals for the 16-bit Reload Timer
Count clock
Count clock period
Interval
21/φ (0.125 µs)
0.125 µs to 8.192 ms
23/φ (0.5 µs)
0.5 µs to 32.768 ms
25/φ (2.0 µs)
2.0 µs to 131.1 ms
23/φ or more (0.5 µs)
0.5 µs or more
Internal clock
External clock
φ: Machine clock
Values in parentheses are for a 16 MHz machine clock.
● Single-shot mode
When an underflow (from 0000H to FFFFH) occurs during counting down, counting stops, causing an
interrupt to occur for the underflow condition.
During counter operation, a rectangular waveform that indicates when the count is in progress can be
output from the TO0 and TO1 pins.
References:
• 16-bit reload timer 0 can be used to create the baud rate of UART0 or enable data transfer in
waveform sequencer.
• 16-bit reload timer 1 can be used as the start trigger of the A/D converter or the baud rate of
UART1.
231
CHAPTER 12 16-BIT RELOAD TIMER
■ 16-bit Reload Timer Interrupts and EI2OS
Table 12.1-3 lists 16-bit reload timer interrupts and EI2OS.
Table 12.1-3 16-bit Reload Timer Interrupts and EI2OS
Channel
Interrupt
number
Interrupt control register
Vector table address
EI2OS
Register name
Address
Lower
Middle
Upper
16-bit reload timer 0*1
#30 (1EH)
ICR09
0000B9H
FFFF84H
FFFF85H
FFFF86H
16-bit reload timer 1*2
#18 (12H)
ICR03
0000BAH
FFFFB4H
FFFFB5H
FFFB6H
O
O: Can be used.
*1: The same interrupt number as that for 16-bit reload timer 0 underflow is assigned to 16-bit timer 0/1/2 counter borrow.
*2: The same interrupt number as that for 16-bit reload timer 1 underflow is assigned to 16-bit output compare channel 2.
232
CHAPTER 12 16-BIT RELOAD TIMER
12.2
Block Diagram of the 16-bit Reload Timer
There are two 16-bit reload timers in MB90460/465 series. Each of them consists of the
seven blocks as shown in the block diagram below.
■ Block Diagram of the 16-bit Reload Timer
Figure 12.2-1 shows the block diagram of the 16-bit reload timer
Figure 12.2-1 Block Diagram of the 16-bit Reload Timer
F2MC-16LX bus
TMRD0*1
<TMRD1>
16-bit reload register
Reload signal
Reload
control circuit
16-bit timer register
Count clock generation
circuit
Machine
clock
Gate
input
Prescaler
Valid
clock
judgment
circuit
Wait signal
Clear
Internal
clock
Clock
selector
Input
control
circuit
Pin
P15
P20
Output control circuit
Invert
To UART0 and
UART1 (*1)
<To the A/D
converter>
Output signal
generation
circuit
Pin
P16/TO0(*1)
<P21/TO1>
External clock
Select
signal
Function selection
Timer control status register (TMCSR0)(*1) <TMCSR1>
Operation
control
circuit
Interrupt request signal
#30 (1EH)(*2)
<#18 (12H)>
*1 This register includes channel 0 and channel 1. The register enclosed in < and > indicates the
channel 1 register.
*2 Interrupt number
● Count clock generation circuit
This circuit generates the count clock for the 16-bit reload timer from the machine clock or external input
clock.
● Reload control circuit
This circuit controls the reload operation when the timer is started and when an underflow occurs.
233
CHAPTER 12 16-BIT RELOAD TIMER
● Output control circuit
This circuit controls the inversion of the TO pin output by an underflow of the 16-bit timer register and
enabling and disabling of TO pin output.
● Operation control circuit
This circuit controls starting and stopping of the 16-bit reload timer.
● 16-bit timer register (TMR0/TMR1)
This register is a 16-bit down counter. The current counter value is read from this register during a read
operation.
● 16-bit reload register (TMRD0/TMRD1)
The interval for the 16-bit reload timer is set in this register. The setting value of this register is loaded into
the 16-bit timer register and decremented.
● Timer control status register (TMCSR0/TMCSR1)
This register selects the count clock of the 16-bit reload timer and the operating mode, sets operating
conditions, starts a trigger with software, enables or disables counting, selects reload or single-shot mode
and the pin output level, enables or disables timer output, controls interrupts, and controls the status.
234
CHAPTER 12 16-BIT RELOAD TIMER
12.3
16-bit Reload Timer Pins
This section describes the pins of the 16-bit reload timer and provides a pin block
diagram.
■ 16-bit Reload Timer Pins
The pins of the 16-bit reload timer are shared with the general-purpose ports. Table 12.3-1 lists the
functions of the pins, I/O format, and settings required to use the 16-bit reload timer.
Table 12.3-1 16-bit reload timer pins
Pin name
Pin function
P15/INT5/TIN0
Port 1 input-output / external
interrupt input /timer input
P16/INT6/TO0
Port 1 input-output / external
interrupt input /timer output
Pull-up
option
I/O format
P20/TIN1
Port 2 input-output / timer
input
P21/TO1
Port 2 input-output / timer
output
Standby
control
Settings required for pins
Setting for the input port
(DDR1: bit15 = 0)
CMOS output /
CMOS hysteresis
input
Setting for timer output enable
(TMCSRL0: OUTE = 1)
Selection
Available
allowed
Setting for the input port
(DDR2: bit0 = 0)
Setting for timer output enable
(TMCSRL1: OUTE = 1)
■ Block Diagram of the 16-bit Reload Timer Pins
Figure 12.3-1 shows the block diagram of the16-bit reload timer pins.
Figure 12.3-1 Block Diagram of the 16-bit Reload Timer Pins
Resource input (*1)
Internal data bus
PDR (port data register)
Resource output (*1)
Resource output enabled (*1)
PDR read
Output latch
PDR write
Pins
DDR (port direction register)
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Standby control: Stop, clock mode with SPL = 1
*1: Only pins with peripheral functions are used for resource I/O.
235
CHAPTER 12 16-BIT RELOAD TIMER
12.4
16-bit Reload Timer Registers
The 16-bit reload timer registers are as follows.
■ 16-bit Reload Timer Registers
Figure 12.4-1 shows 16-bit reload timer registers.
Figure 12.4-1 16-bit Reload Timer Registers
Timer Control Status Register (Upper)
bit
15
14
13
12
11
10
9
8
Address: ch.0 000083H
ch.1 000087H
CSL1
CSL0 MOD2
Read/write
Initial value
R/W
0
R/W
0
MOD1
R/W
0
R/W
0
0
TMCSRH0/
TMCSRH1
Timer Control Status Register (Lower)
bit
Address: ch.0 000082H
ch.1 000086H
Read/write
Initial value
7
6
5
4
3
2
1
CNTE
TRG
R/W
0
R/W
0
MOD0 OUTE OUTL
RELD
INTE
UF
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
TMCSRL0/
TMCSRL1
16-bit Timer Register / 16-bit Reload Register (Upper)
15
14
13
12
11
10
9
8
Address: ch.0 000085H
ch.1000089H
D15
D14
D13
D12
D11
D10
D09
D08
Read/write
Initial value
R/W
X
R/W
X
bit
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
3
2
1
0
D01
D00
TMR0/TMRD0
16-bit Timer Register / 16-bit Reload Register (Lower)
bit
Address: ch.0 000084H
ch.1000088H
Read/write
Initial value
236
7
6
5
4
D07
D06
D05
D04
D03
D02
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
TMR0/TMRD0
CHAPTER 12 16-BIT RELOAD TIMER
12.4.1
Timer Control Status Register, Upper Byte (TMCSRH0/
TMCSRH1)
High-order bit11 to bit8 and low-order bit7 of the timer control status registers
(TMCSR0/TMCSR1) are used to select the operating mode of the 16-bit reload timer and
set the operating conditions. This section describes low-order bit7: the MOD0 bit.
■ Timer Control Status Register, Upper Byte (TMCSRH0/TMCSRH1)
Figure 12.4-2 Timer Control Status Register, Upper Byte (TMCSRH0/TMCSRH1)
Address
bit
TMCSRH0
000083 H
TMCSRH1
15
14
13
12
11
10
9
8
7
6
CSL1 CSL0 MOD2 MOD1 MOD0
R/W
0
Initial value
----00000 B
(TMCSR:L)
R/W R/W R/W R/W
000087 H
MOD2 MOD1 MOD0
Operating mode selection bit
(Internal clock mode)
Input pin function
0
0
0
0
0
1
0
1
0
0
1
1
1
X
0
1
X
1
Valid edge and level
Trigger disabled
Rising edge
Falling edge
Both edges
Trigger input
"L" level
Gate input
"H" level
Operating mode selection bit
(Event count mode)
MOD2 MOD1 MOD0
Input pin function
X
0
0
X
0
1
X
1
0
X
1
1
CSL1 CSL0
R/W
X
0
0
0
1
Valid edge
Rising edge
Falling edge
Both edges
Trigger input
Count clock selection bit
Function
Count clock
1
Internal clock mode
2
23
(0.125 s)
(0.5 s)
25
0
1
(2.0 s)
Read/Write
1
1
External event input
Event count mode
Not used
Undefined
Initial value
Machine cycle. Value in parentheres ( ) indicates the value when machine clock is 16MHz
237
CHAPTER 12 16-BIT RELOAD TIMER
Table 12.4-1 Timer Control Status Register (TMCSRH0/TMCSRH1)
Bit name
bit15
to
bit12
bit11,
bit10
bit9
to
bit7
238
Function
Not used
• When these bits are read, their values are undefined.
• Writing to these bits has no effect on operation.
CSL1, CSL0:
Count clock selection
bits
• Selects the count clock.
• When these bits are not set to "11B", internal clock mode is set. The internal
clock is counted in this mode.
• When these bits are set to "11B", event count mode is set. The external clock
edges are counted in this mode.
MOD2 to MOD0:
Operating mode
selection bits
<In internal clock mode>
• The MOD2 bit is used to select input pin functions.
• When the MOD2 bit is "0", the input pin is used as a trigger input pin, so that
whenever a valid edge is input, the contents of the reload register are loaded into
the counter and counting continues. The MOD1 and MOD0 bits are used to
select the type of valid edge.
• When the MOD2 bit is "1", the input pin becomes a gate, meaning that counting
will continue only as long as a valid level signal is input. The MOD1 bit is an
unused bit, and the MOD0 bit is used to select the valid level.
<In event count mode>
• The MOD2 bit is not used. Set any value ("0" or "1").
• The input pin is used as a trigger input pin for event input, and the valid edge is
selected with MOD1 and MOD0 bits.
CHAPTER 12 16-BIT RELOAD TIMER
12.4.2
Timer Control Status Register, Lower Byte (TMCSRL0/
TMCSRL1)
The lower seven bits of the timer control status registers (TMCSR0/TMCSR1) are used
to set operating conditions for the 16-bit reload timer, enable and disable operation,
control interrupts, and check the status.
■ Timer Control Status Register, Lower Byte (TMCSRL0/TMCSRL1)
Figure 12.4-3 Timer Control Status Register, Lower Byte (TMCSRL0/TMCSRL1)
bit 15
Address
(TMCSR:H)
TMCSRL0
000082H
TMCSRL1
000086H
8
7
6
5
4
3
2
MOD0* OUTE OUTL RELD INTE
R/W
R/W
R/W
R/W
1
UF
R/W
0
Initial value
00000000B
CNTE TRG
R/W
R/W
R/W
Software trigger bit
TRG
During reading
During writing
0
No effect
1
After reloading, counting starts.
Always read "0"
Count enable bit
CNTE
0
Counting stopped
1
Counting enabled (wait for the start trigger)
Underflow interrupt request flag bit
UF
During writing
During reading
0
Without counter underflow
This bit is cleared.
1
With counter underflow
No effect
Underflow interrupt enable bit
INTE
0
Disable underflow interrupt
1
Enable underflow interrupt
Reload selection bit
RELD
0
Single-shot mode
1
Reload mode
Pin output level selection bit
OUTL
In single-shot mode (RELD = 0)
In reload mode (RELD = 1)
0
Square wave of H during counting Toggle output of L when counting is started.
1
Square wave of L during counting
Toggle output of H when counting is started.
Timer output enable bit
OUTE
Registers and pins corresponding to each channel
Pin functions
R/W: Read/write
: Initial value
TMCSR0
TMCSR1
0
General-purpose port
P16
P21
1
Timer output
TO0
TO1
* : See Section 12.4.1, "Timer control status register, upper byte", for MOD0 (bit 7)
239
CHAPTER 12 16-BIT RELOAD TIMER
Table 12.4-2 Timer Control Status Register (TMCSRL0/TMCSRL1)
Bit name
Function
bit6
OUTE:
Timer output enable bit
• This bit enables or disables output from the timer output pin.
• When this bit is "0", the pin functions as a general-purpose port. When this bit is
"1", the pin functions as a timer output pin.
• In reload mode, the output waveform of this timer output pin
toggles. In single-shot mode, the timer outputs a rectangular
waveform that indicates that counting is in progress is output.
bit5
OUTL:
Pin output level
selection bit
• This register is used to select the output level of the timer output pin.
• The output level of the pin is inverted depending on whether this bit is "0" or "1".
bit4
RELD:
Reload selection bit
• This bit enables reloading.
• When this bit is "1", the timer is in reload mode. At the same time an underflow
occurs, the contents of the reload register are loaded into the counter, and counting
continues.
• When this bit is "0", the timer is in single-shot mode. Counting stops when an
underflow occurs.
bit3
INTE:
Interrupt request
enable bit
• This bit enables or disables underflow interrupt request to the CPU.
• When this bit and the underflow interrupt request flag (UF) bit are "1", the timer
outputs an interrupt request.
bit2
UF:
Underflow interrupt
request flag bit
• This bit is set to "1" when a counter underflow occurs.
• Writing "0" to this bit clears it. Writing "1" to this bit does not change the bit value
and has no effect on other bits.
• This bit is also cleared when EI2OS is activated.
bit1
CNTE:
Count enable bit
• The bit enables or disables counting.
• When this bit is set to "1", the counter is placed in trigger standby mode. When a
trigger occurs, actual counting starts.
TRG:
Software trigger bit
• This bit starts the interval timer function or counter function with software.
• Writing "1" to this bit applies a software trigger, causing the contents of the reload
register to be loaded into the counter and starting counter operation. Writing "0" to
this bit has no effect.
• Trigger input from this trigger is always valid when the CNTE bit is set to "1"
regardless of the operating mode.
bit0
240
CHAPTER 12 16-BIT RELOAD TIMER
12.4.3
16-bit Timer Register (TMR0/TMR1)
The 16-bit timer register (TMR0/TMR1) is always able to read the count value from the
16-bit down counter.
■ 16-bit Timer Register (TMR0/TMR1)
Figure 12.4-4 shows the 16-bit timer registers (TMR0/TMR1).
Figure 12.4-4 16-bit Timer Register (TMR0/TMR1)
16-bit Timer Register (Upper)
bit
15
Address: ch.0 000085H
D15
ch.1 000089
H
Read/write
Initial value
R
X
14
13
12
11
10
9
8
D14
D13
D12
D11
D10
D09
D08
R
X
R
X
R
X
R
X
R
X
3
R
X
R
X
2
1
0
D02
D01
D00
R
X
R
X
R
X
TMR0/TMR1
16-bit Timer Register (Lower)
bit
Address: ch.0 000084H
ch.1 000088H
Read/write
Initial value
7
6
5
4
D07
D06
D05
D04
D03
R
X
R
X
R
X
R
X
R
X
TMR0/TMR1
The 16-bit timer register is able to read the counter value from the 16-bit down counter.
When counting is enabled (TMCSRL0/TMCSRL1:CNTE = 1) to start counting, the value written to the 16bit reload register is loaded into this register, and counting down starts. This register value is stored in the
counter stop status (TMCSRL0/TMCSRL1:CNTE = 0).
Notes:
• This register is able to read the count value even during counting. It should always be read with a
word transfer instruction (MOVW A, 003AH, etc.).
• Although the 16-bit timer register (TMR0/TMR1) is a read-only register, it is allocated to the same
address as the address of the write-only 16-bit reload register (TMRD0/TMRD1). Accordingly,
writing to this register has no effect on the TMR0/TMR1 value, although writing to TMRD0/TMRD1
is done.
241
CHAPTER 12 16-BIT RELOAD TIMER
12.4.4
16-bit Reload Register (TMRD0/TMRD1)
The 16-bit reload register (TMRD0/TMRD1) sets a reload value in the 16-bit down
counter. The value written to this register is loaded into the down counter, and the
value is counted down.
■ 16-bit Reload Register (TMRD0/TMRD1)
Figure 12.4-5 shows the 16-bit reload registers (TMRD0/TMRD1).
Figure 12.4-5 16-bit Reload Register (TMRD0/TMRD1)
16-bit Reload Register (Upper)
bit
15
Address: ch.0 000085H
D15
ch.1 000089H
Read/write
Initial value
14
13
12
11
10
9
8
D14
D13
D12
D11
D10
D09
D08
W
X
W
X
W
X
W
X
W
X
W
X
W
X
3
2
1
0
W
X
TMRD0/TMRD1
16-bit Reload Register (Lower)
bit
Address: ch.0 000084H
ch.1 000088H
Read/write
Initial value
7
6
5
4
D07
D06
D05
D04
D03
D02
D01
D00
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
TMRD0/TMRD1
The initial value of the counter is set in this register when counting is disabled (TMCSRL0/
TMCSRL1:CNTE = 0), regardless of the operating mode of the 16-bit reload timer. When counting is
enabled (TMCSRL0/TMCSRL1:CNTE = 1) and the counter is started, counting down starts from the value
written to this register.
In reload mode, the value set in the 16-bit reload register (TMRD0/TMRD1) is reloaded into the counter
when an underflow occurs, and counting down continues. In single-shot mode, the counter stops at FFFFH
when an underflow occurs.
Notes:
242
• Write a value to this register in the counter stop (TMCSRL0/TMCSRL1:CNTE = 0) state. Also,
always use a word transfer instruction (MOVW 003AH, A etc.) to write a value to this register.
• Although the 16-bit reload register (TMRD0/TMRD1) is functionally a write-only register, it is
allocated to the same address as the read-only 16-bit timer registers (TMR0/TMR1). Accordingly,
since the read value is used as the TMR0/TMR1 value, the INC/DEC instruction and other
instructions for read-modify-write (RMW) operations cannot be used.
CHAPTER 12 16-BIT RELOAD TIMER
12.5
16-Bit Reload Timer Interrupts
The 16-bit reload timer is enabled to generate an interrupt request in an underflow of
the counter. It is also coordinated with the extended intelligent I/O service (EI2OS).
■ 16-bit Reload Timer Interrupts
Table 12.5-1 lists the interrupt control bits and interrupt causes of the 16-bit reload timer.
Table 12.5-1 Interrupt Control Bits and Interrupt Causes of the 16-bit Reload Timer
16-bit reload timer 0
Interrupt request flag bit
16-bit reload timer 1
TMCSRL0: UF
TMCSRL1: UF
Interrupt request enable bit TMCSRL0: INTE
Interrupt cause
TMCSRL1: INTE
Underflow of the 16-bit down counter (TMR0) Underflow of the 16-bit down counter (TMR1)
In the 16-bit reload timer, the UF bit of the timer control status register (TMCSRL0/TMCSRL1) is set to
"1" by an underflow (from 0000H to FFFFH) of the down counter. If an interrupt request is enabled
(TMCSRL0/TMCSRL1:INTE = 1) in this operation, the interrupt request is output to the interrupt
controller.
■ 16-bit Reload Timer Interrupts and EI2OS
Table 12.5-2 lists the 16-bit reload timer interrupts and EI2OS.
Table 12.5-2 16-bit Reload Timer Interrupts and EI2OS
Interrupt
number
Channel
Interrupt control register
Vector table address
EI2OS
Register name
Address
Lower
Middle
Upper
16-bit reload timer 0*1
#30 (1EH)
ICR09
0000B9H
FFFF84H
FFFF85H
FFFF86H
16-bit reload timer 1*2
#18 (12H)
ICR03
0000B3H
FFFFB4H
FFFFB5H
FFFFB6H
O
*1: The same interrupt number as that for waveform sequencer 16-bit timer counter borrow is assigned to 16-bit reload timer 0.
*2: The same interrupt number as that for output compare ch 2 match is assigned to 16-bit reload timer 1.
■ EI2OS Function of the 16-bit Reload Timer
Since the 16-bit reload timer has a circuit that coordinates with EI2OS, the counter can start EI2OS when an
underflow occurs.
However, EI2OS is available only when other peripheral functions sharing the interrupt control register
(ICR) do not use interrupts. For example, when 16-bit reload timer 0 uses EI2OS, interrupts of the
waveform generator 16-bit timer 0/1/2 counter borrow must be disabled.
243
CHAPTER 12 16-BIT RELOAD TIMER
12.6
Operation of the 16-bit Reload Timer
This section describes the 16-bit reload timer settings and counter operating status.
■ 16-bit Reload Timer Settings
● Internal clock mode setting
The setting shown in Figure 12.6-1 is required to operate this timer as an interval timer.
Figure 12.6-1 Internal Clock Mode Setting
TMCSR0/
TMCSR1
CSL1 CSL0 MOD2 MOD1MOD0 OUTE OUTL RELD INTE
Other than 11
TMRD0/
TMRD1
O
1
O
O
O
O
O
O
O
UF CNTE TRG
O
1
O
Set the initial value (reload value) of the counter
: Used
: Set to "1"
● Event count mode setting
The setting shown in Figure 12.6-2 is required to operate this timer as an event counter.
Figure 12.6-2 Event Counter Mode Setting
TMCSR0/
TMCSR1
CSL1 CSL0 MOD2 MOD1MOD0 OUTE OUTL RELD INTE
1
TMRD0/
TMRD1
DDR1
(for PWC0)
1
O
O
O
244
O
O
O
O
1
O
Set the initial value (reload value) of the counter
∆
DDR2
(for PWC1)
O
1
∆
O
UF CNTE TRG
: Used
: Set to "1"
: Set the bit corresponding to the pin used to "0"
∆
CHAPTER 12 16-BIT RELOAD TIMER
■ Counter Operating State
The counter status is determined by the CNTE bit of the timer control status register (TMCSRL0/
TMCSRL1) and the internal WAIT signal. Possible settings include the stop status (STOP state), trigger
wait state (WAIT state), and running state (RUN state).
Figure 12.6-3 shows the transitions of the counter state.
Figure 12.6-3 Counter State Transition
Reset
STOP
CNTE = 0, WAIT = 1
TIN: Input disabled
TO: General-purpose port
Counter: The counter value is
retained when the counter
stops. Immediately after a
reset it is undefined.
CNTE = 0
CNTE = 1
TRG = 1
CNTE = 1
TRG = 0
WAIT
RUN
CNTE = 1, WAIT = 1
CNTE = 1, WAIT = 0
TIN: Functions as TIN
TIN: Only trigger input enabled
TO: Functions as TO
TO: Output initial value
Counter: The counter value is
retained when the counter
stops. Immediately after a
reset, it is undefined and
remains so until a value is
loaded.
UF = 1 &
RELD = 0
(Single-shot mode)
Counter: Running
UF = 1 &
RELD = 1
(Reload mode)
TRG = 1
(Software trigger)
External trigger from TIN
CNTE = 0
LOAD
TRG = 1
(Software trigger)
CNTE = 1, WAIT = 0
Load complete
Load contents of the reload
register into the counter.
: State transitions by hardware
: State transitions by register access
WAIT: Wait signal (internal signal)
TRG: Software trigger bit of timer control status register (TMCSRL0/TMCSRL1)
CNTE: Count enable bit of timer control status register (TMCSRL0/TMCSRL1)
Underflow interrupt flag bit of timer control status register (TMCSRL0/TMCSRL1)
UF:
RELD: Reload selection bit of timer control status register (TMCSRL0/TMCSRL1)
245
CHAPTER 12 16-BIT RELOAD TIMER
12.6.1
Internal Clock Mode (reload mode)
Synchronized with the internal count clock, the 16-bit reload timer is used for counting
down of the 16-bit counter, generating an interrupt request to the CPU for a counter
underflow. It can also output a toggle waveform from the timer output pin.
■ Operation in Internal Clock Mode (reload mode)
When counting is enabled (TMCSRL0/TMCSRL1:CNTE = 1) and the timer is started by the software
trigger bit (TMCSRL0/TMCSRL1:TRG) or external trigger, the value of the reload register (TMRD0/
TMRD1) is loaded into the counter, and counting starts. If the count enable bit and software trigger bit are
set to "1" simultaneously, counting starts simultaneously with the enabling of counting.
When an underflow of the counter value (from 0000H to FFFFH) occurs, the value of the 16-bit reload
register (TMRD0/TMRD1) is loaded into the counter, and counting continues. If the underflow interrupt
flag (TMCSRL0/TMCSRL1:UF) bit is set to "1" and the underflow interrupt enable (TMCSRL0/
TMCSRL1:INTE) bit is "1", an interrupt request is generated.
The timer can also output from the TO0/TO1 pin a toggle waveform, which is inverted for each underflow.
● Software trigger operation
When "1" is written to the TRG bit of the timer control status register (TMCSRL0/TMCSRL1), the counter
is started. Figure 12.6-4 shows software trigger operation in reload mode.
Figure 12.6-4 Count Operation in Teload Mode (Software Trigger Operation)
Count clock
Counter
Reload data
Reload data
Reload data
Reload data
Data load signal
UF bit
CNTE bit
TRG bit
TO pin
T: Machine cycle
* It takes 1T time from trigger input to loading of the reload data.
246
CHAPTER 12 16-BIT RELOAD TIMER
● External trigger operation
When a valid edge (rising, falling and both edges can be selected) is input to the TIN pin, the counter is
started. Figure 12.6-5 shows external trigger operation in reload mode.
Figure 12.6-5 Counting in Reload Mode (External Trigger Operation)
Count clock
Reload data
Counter
Reload data
Reload data
Reload data
Data load signal
UF bit
CNTE bit
TIN pin
TO pin
T: Machine cycle
* It takes 2T to 2.5T time from trigger input to loading of the reload data.
Note:
Specify 2/φ or more for the width of the trigger pulse input to the TIN0/TIN1 pin.
● Gate input operation
While a valid level (H and L levels can be selected) is input to the TIN0/TIN1 pin, counting is done.
Figure 12.6-6 shows gate input in reload mode.
Figure 12.6-6 Count Operation in Reload Mode (Software Trigger and Gate Input Operation)
Count clock
Counter
Reload data
Reload data
Data load signal
CNTE bit
TRG bit
TIN pin
TO pin
T: Machine cycle
* It takes 1T time from trigger input to loading of the reload data.
Note:
Specify 2/φ or more for the width of the trigger pulse input to the TIN0/TIN1 pin.
247
CHAPTER 12 16-BIT RELOAD TIMER
12.6.2
Internal Clock Mode (single-shot mode)
Synchronized with the internal count clock, the 16-bit reload timer is used for counting
down of the 16-bit counter, generating an interrupt request to the CPU for a counter
underflow. It can also output from the TO pin a rectangular waveform indicating that
counting is in progress.
■ Internal Clock Mode (Single-shot Mode)
When counting is enabled (TMCSRL0/TMCSRL1:CNTE = 1) and the timer is started with the software
trigger bit (TMCSRL0/TMCSRL1:TRG) or external trigger, counting starts. If the count enable bit and
software trigger bit are set to "1" simultaneously, counting starts simultaneously with the enabling of
counting. When an underflow of the counter value (from 0000H to FFFFH) occurs, the counter stops in the
FFFFH state. If the underflow interrupt flag (TMCSRL0/TMCSRL1:UF) bit is set to "1" and the underflow
interrupt enable (TMCSRL0/TMCSRL1:INTE) bit is "1", an interrupt request is generated.
The timer can also output from the TO0/TO1 pin a rectangular waveform indicating that counting is in
progress.
● Software trigger operation
When "1" is written to the TRG bit of the timer control status register (TMCSRL0/TMCSRL1), the counter
is started. Figure 12.6-7 shows the software trigger operation in single-shot mode.
Figure 12.6-7 Count Operation in Single-shot Mode (Software Trigger Operation)
Count clock
Reload data
Reload data
Counter
Data load signal
UF bit
CNTE bit
TRG bit
TO pin
Wait for trigger input
T: Machine cycle
* It takes 1T time from trigger input to loading of the reload data.
248
CHAPTER 12 16-BIT RELOAD TIMER
● External trigger operation
When a valid edge (rising, falling, and both edges can be selected) is input to the TIN0/TIN1 pin, the
counter is started. Figure 12.6-8 shows external trigger operation in single-shot mode
Figure 12.6-8 Specify 2/f or more for the Width of the Trigger Pulse Input to the TIN0/TIN1 Pin.
Count clock
Reload data
Reload data
Counter
Data load signal
UF bit
CNTE bit
TIN bit
TO pin
Wait for trigger input
T: Machine cycle
* It takes 2T to 2.5T time from external trigger input to loading of the reload data.
Note:
Specify 2/φ or more for the width of the trigger pulse input to the TIN0/TIN1 pin.
● Gate input operation
While a valid level (H and L levels can be selected) is input to the TIN0/TIN1 pin, counting is done.
Figure 12.6-9 shows gate input operation in single-shot mode
Figure 12.6-9 Count Operation in Single-shot Mode (Software Trigger and Gate Input Operation)
Count clock
Reload data
Reload data
Counter
Data load signal
UF bit
CNTE bit
TRG bit
T*
TO pin
Wait for trigger input
T: Machine cycle
* It takes 1T time from trigger input to loading of the reload data.
Note:
Specify 2/φ or more for the width of the trigger pulse input to the TIN0/TIN1 pin.
249
CHAPTER 12 16-BIT RELOAD TIMER
12.6.3
Event Count Mode
The 16-bit reload timer counts an input edge from the TIN0/TIN1 pin, counts down the
16-bit counter, and generates an interrupt request to the CPU for a counter underflow. It
can also output a toggle waveform or rectangular waveform from the TO0/TO1 pin.
■ Event Count Mode
When counting is enabled (TMCSRL0/TMCSRL1:CNTE = 1) and the counter is started (TMCSRL0/
TMCSRL1:TRG = 1), the value of the reload register is loaded into the counter. Counting down is then
done every time a valid edge (rising, falling, and both edges can be selected) of the pulse input to the TIN
pin (external count clock) is detected.
When the count enable bit and software trigger bit are set to "1" simultaneously, counting is started
simultaneously with the enabling of counting.
● Operation in reload mode
When an underflow of the counter value (from 0000H to FFFFH) occurs, the value of the reload register
(TMRD0/TMRD1) is loaded into the counter, and counting continues. If the underflow interrupt flag
(TMCSRL0/TMCSRL1:UF) bit is set to "1" and the underflow interrupt enable bit (TMCSRL0/
TMCSRL1:INTE) is "1", an interrupt request is generated.
The timer can also output from the TO0/TO1 pin a toggle waveform, which is inverted for each underflow.
Figure 12.6-10 shows counting in reload mode.
Figure 12.6-10 Count Operation in Reload Mode (Event Count Mode)
TIN pin
Counter
Reload data
Reload data
Reload data
Reload data
Data load signal
UF bit
CNTE bit
TRG bit
TO pin
T: Machine cycle
* It takes 1T time from trigger input to loading of the reload data.
Note:
250
Specify 4/φ or more for the H and L widths of the clock input to the TIN0/TIN1 pin.
CHAPTER 12 16-BIT RELOAD TIMER
● Operation in single-shot mode
When an underflow of the counter value (from 0000H to FFFFH) occurs, the counter stops in the FFFFH
state. If the underflow interrupt flag (TMCSRL0/TMCSRL1:UF) bit is set to "1" and the underflow
interrupt enable (TMCSRL0/TMCSRL1:INTE) bit is "1", an interrupt request is generated.
The timer can also output from the TO0/TO1 pin a rectangular waveform indicating that counting is in
progress.
Figure 12.6-11 shows counting in single-shot mode.
Figure 12.6-11 Counter Operation in Single-shot Mode (Event Count Mode)
TIN pin
Counter
Reload data
Reload data
Data load signal
UF bit
CNTE bit
TRG bit
TO pin
Wait for trigger input
T: Machine cycle
* It takes 1T time from trigger input to loading of the reload data.
Note:
Specify 4/φ or more for the H and L widths of the clock input to the TIN0/TIN1 pin.
251
CHAPTER 12 16-BIT RELOAD TIMER
12.7
Usage Notes on the 16-bit Reload Timer
Notes on using the 16-bit reload timer are given below.
■ Usage Notes on the 16-bit Reload Timer
● Notes on using a program for setting
• Write a value to the 16-bit reload register (TMRD0/TMRD1) when counting stops (TMCSRL0/
TMCSRL1:CNTE = 0). Also, a value can be read from the 16-bit timer register (TMR0/TMR1) even
during counting, but always be sure to use a word transfer instruction (MOVW A, dir, etc.).
• Change the CSL1 and CSL0 bits of the timer control status register (TMCSRH0/TMCSRH1) when the
counter has stopped (TMCSRL0/TMCSRL1:CNTE = 0).
● Notes about interrupts
• When the UF bit of the timer control status register (TMCSRL0/TMCSRL1) is set to "1" and an
interrupt request is enabled (TMCSRL0/TMCSRL1:INTE = 1), control cannot be returned from
interrupt processing. Always clear the UF bit.
• Since the 16-bit reload timer shares an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the 16-bit reload timer, shared resource interrupts must be disabled.
252
CHAPTER 12 16-BIT RELOAD TIMER
12.8
Sample Programs for the 16-bit Reload Timer
This section contains sample programs for the 16-bit reload timer in internal clock
mode and event count mode.
■ Sample Program in Internal Clock Mode
● Processing
• A 25 ms interval timer interrupt is generated with 16-bit reload timer 0.
• The timer is used in reload mode to repeatedly generate an interrupt.
• The timer is started with a software trigger. External trigger input is not used.
• EI2OS is not used.
• 16 MHz is used for the machine clock, and 2 µs is used for the count clock.
● Coding example
ICR09
EQU
0000B9H
;Interrupt control register for the 16-bit reload timer
TMCSR
EQU
000082H
;Timer control status register
TMR
EQU
000084H
;16-bit timer register
TMRD
EQU
000084H
;16-bit reload register
UF
EQU
TMCSR:2
;Interrupt request flag bit
CNTE
EQU
TMCSR:1
;Counter operation enable bit
TRG
EQU
TMCSR:
;Software trigger bit
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
;Assumes that stack pointer (SP) has already been
initialized
AND
CCR,#0BFH
;Interrupt disable
MOV
I:ICR09,#00H
;Interrupt level 0 (strongest)
CLRB
I:CNTE
;Temporary stopping of counter
MOVW
I:TMRD,#30D3H
;Sets data for 25-ms timer
MOVW
I:TMCSR,#00001000000011011B
;Interval timer operation, 2 µs clock
;Disables external trigger and external output
;Selects reload mode, and enables interrupts
;Clears interrupt flag, and starts counter
MOV
ILM,#07H
;Sets ILM in PS to level 7
OR
CCR,#40H
; Interrupt enable
253
CHAPTER 12 16-BIT RELOAD TIMER
LOOP:
MOV
A,#00H
;Endless loop
MOV
A,#01H
;
BRA
LOOP
;
;-------Interrupt program-------------------------------------------------------------------------------------------WARI:
CLRB
I:UF
;
:
;
User processing
;
:
RETI
CODE
;Clears interrupt request flag
;Returns from interrupt
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------VECT
VECT
CSEG
ABS=0FFH
ORG
0FF84H
DSL
WARI
ORG
0FFDCH
DSL
START
DB
00H
;Sets vector for interrupt #30 (1EH)
;Sets reset vector
;Sets single-chip mode
ENDS
END
START
■ Sample Program in Event Count Mode
● Processing
• When the rising edge of the pulse input to the external event input pin is counted 10,000 times with 16bit reload timer/counter 0, an interrupt is generated.
• The timer operates in single-shot mode.
• External trigger input selects the rising edge.
• EI2OS is not used.
● Coding example
254
ICR09
EQU
0000B9H
;Interrupt control register for the 16-bit reload timer
TMCSR
EQU
000082H
;Timer control status register
TMR
EQU
000084H
;16-bit timer register
TMRD
EQU
000084H
;16-bit reload register
DDR1
EQU
000011H
;Port data register
UF
EQU
TMCSR:2
;Interrupt request flag bit
CNTE
EQU
TMCSR:1
;Counter operation enable bit
TRG
EQU
TMCSR:0
;Software trigger bit
CHAPTER 12 16-BIT RELOAD TIMER
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
;Assumes that stack pointer (SP) has already been
initialized
AND
CCR,#0BFH
;Interrupt disable
MOV
I:ICR09,#00H
;Interrupt level 0 (strongest)
MOV
I:DDR1,#00H
;Sets P15/INT5/TIN0 pin to input
CLRB
I:CNTE
;Temporary stopping of counter
MOVW
I:TMRD,#2710H
;Sets reload value to 10,000
MOVW
I:TMCSR,#0000110010001011B
;Counter operation, external event input, rising
;Disables external output
;Selects single-shot mode and enables interrupts
;Clears interrupt flag, starts counter
LOOP:
MOV
ILM,#07H
;Sets ILM in PS to level 7
OR
CCR,#40H
;Interrupt enable
MOV
A,#00H
;Endless loop
MOV
A,#01H
;
BRA
LOOP
;
;-------Interrupt program-------------------------------------------------------------------------------------------WARI:
CLRB
I:UF
;
:
;
User processing
;Clears interrupt request flag
;
RETI
CODE
;Returns from interrupt
ENDS
;-------Vector setting------------------------------------------------------------------------------------------------VECT
VECT
CSEG
ABS=0FFH
ORG
0FF84H
DSL
WARI
ORG
0FFDCH
DSL
START
DB
00H
;Sets vector for interrupt #30 (1EH)
;Sets reset vector
;Sets single-chip mode
ENDS
END
START
255
CHAPTER 12 16-BIT RELOAD TIMER
256
CHAPTER 13
16-BIT PPG TIMER
This chapter describes the functions and operation of
the 16-bit PPG Timer.
13.1 Overview of 16-bit PPG Timer
13.2 Block Diagram of 16-bit PPG Timer
13.3 16-bit PPG Timer Pins
13.4 16-bit PPG Timer Registers
13.5 16-bit PPG Timer Interrupts
13.6 Operation of 16-bit PPG Timer
13.7 Usage Notes on the 16-bit PPG Timer
13.8 Sample Programs for the 16-bit PPG Timer
257
CHAPTER 13 16-BIT PPG TIMER
13.1
Overview of 16-bit PPG Timer
The 16-bit PPG timer consists of a 16-bit down counter, prescaler, 16-bit period setting
register, 16-bit duty setting register, 16-bit control register and a PPG output pin.
■ 16-bit PPG Timer (× 3, PPG1 is not present in MB90465 Series)
The 16-bit PPG timer consists of a 16-bit down counter, prescaler, 16-bit period setting register, 16-bit duty
setting register, 16-bit control register and a PPG output pin. This module can be used to output pulses
synchronized by software trigger or GATE signal from Multi-functional timer, refer to "Multi-functional
Timer" in chapter 14.
• 8 types of counter operation clock (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128) can be selected
(φ is the machine clock).
• An interrupt is generated when there is a trigger or an counter borrow or when PPG rising (normal
polarity) / PPG falling (inverted polarity).
• PPG output operation
The 16-bit PPG timer can output pulse waveforms with variable period and duty ratio. Also, it can be
used as D/A converter in conjunction with an external circuit.
258
CHAPTER 13 16-BIT PPG TIMER
13.2
Block Diagram of 16-bit PPG Timer
This section shows the block diagram of 16-bit PPG timer.
■ Block Diagram of 16-bit PPG Timer
Figure 13.2-1 Block Diagram of 16-bit PPG Timer
Period Setting Buffer Register 0/1/2
Duty Setting Buffer Register 0/1/2
Prescaler
CKS1
CKS0
Period Setting Register 0/1/2
1/1
1/2
1/4
1/8
1/16
1/32
1/64
1/128
Duty Setting Register 0/1/2
Comparator
CLK
LOAD
16-bit down counter
MDSE PGMS OSEL POEN
STOP
START
BORROW
P37/PPG0
or
P36/PPG1
or
P46/PPG2
Machine clock φ
Pin
S
Down Counter Register 0/1/2
F2MC-16LX bus
CKS2
Q
PPG0 (multi-functional timer)
or
PPG1 (multi-pulse generator)
or
PPG2
R
Interrupt
selection
Interrupt
#14/#16/#32
GATE - from multi-functional
timer (for PPG ch. 0 only)
IRS1
Edge detection
IRS0
IRQF
IREN
(for PPG ch. 1 & 2)
STGR CNTE RTRG
259
CHAPTER 13 16-BIT PPG TIMER
13.3
16-bit PPG Timer Pins
This section describes the pins of the 16-bit PPG timer and provides a pin block
diagram.
■ 16-bit PPG Timer Pins
The pins of the 16-bit PPG timer are shared with the general-purpose ports. Table 13.3-1 lists the functions
of the pins, I/O format, and settings required to use the 16-bit PPG timer.
Table 13.3-1 16-bit PPG Timer Pins
Pin name
Pin function
I/O format
P37/PPG0
Port 3 input-output /
PPG0 output
P36/PPG1
Port 3 input-output /
PPG1 output
P46/PPG2
Port 4 input-output /
PPG2 output
Standby control
Settings required for pins
Setting for the PPG timer 0 output
(PNCTL0:POEN=1)
CMOS output /
CMOS input
Available
CMOS output /
CMOS hysteresis
input
Setting for PPG timer 1 output enable
(PNCTL1:POEN=1)
Setting for PPG timer 2 output enable
(PNCTL2:POEN=1)
■ Block Diagram of the 16-bit PPG Timer Pins
Figure 13.3-1 Block Diagram of the 16-bit PPG Timer 0 & 1 Pins
Resource output
Resource output enable
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
260
Standby control (SPL = 1)
CHAPTER 13 16-BIT PPG TIMER
Figure 13.3-2 Block Diagram of the 16-bit PPG Timer 2 Pin
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
261
CHAPTER 13 16-BIT PPG TIMER
13.4
16-bit PPG Timer Registers
■ 16-bit PPG Timer Registers
Figure 13.4-1 Registers of 16-bit PPG Timer
PPG Down Counter Register (Upper)
bit 15
14
13
12
11
10
9
8
Address: ch.0 000039H
ch.1 000041H
ch.2 000049H DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08
Read/write
Initial value
R
1
PPG Down Counter Register (Lower)
Address: ch.0 000038H
ch.1 000040H
ch.2 000048H
bit
R
1
R
1
R
1
R
1
R
1
R
1
R
1
7
6
5
4
3
2
1
PDCR0 to
PDCR2
0
PDCR0 to
PDCR2
DC07 DC06 DC05 DC04 DC03 DC02 DC01 DC00
Read/write
Initial value
R
1
R
1
R
1
R
1
R
1
R
1
R
1
R
1
PPG Period Setting Buffer Register (Upper)
bit 15
14
13
12
11
10
9
8
Address: ch.0 00003BH
ch.1 000043H
ch.2 00004BH CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08
Read/write
W
W
W
W
W
Initial value
X
X
X
X
X
PPG Period Setting Buffer Register (Lower)
7
6
5
4
bit
Address: ch.0 00003AH
ch.1 000042H
CS07 CS06 CS05 CS04 CS03
ch.2 00004AH
Read/write
Initial value
W
X
W
X
W
X
W
X
W
X
W
X
W
X
3
2
1
PCSR0 to
PCSR2
0
CS02 CS01 CS00
W
X
W
X
W
X
W
X
PPG Duty Setting Buffer Register (Upper)
14
13
12
11
10
9
8
bit 15
Address: ch.0 00003DH
ch.1 000045H
ch.2 00004DH DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08
Read/write
Initial value
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
PDUT0 to
PDUT2
W
X
PPG Duty Setting Buffer Register (Lower)
7
6
5
4
3
2
1
0
bit
Address: ch.0 00003CH
ch.1 000044H
DU07 DU06 DU05 DU04 DU03 DU02 DU01 DU00
ch.2 00004CH
Read/write
Initial value
PCSR0 to
PCSR2
W
X
PDUT0 to
PDUT2
W
X
(Continued)
262
CHAPTER 13 16-BIT PPG TIMER
(Continued)
PPG Control Status Register (Upper)
bit
15
14
13
12
Address: ch.0 00003FH
ch.1 000047H
CNTE STGR MDSE RTRG CKS2
ch.2 00004FH
Read/write
Initial value
R/W
0
R/W
0
11
10
9
8
CKS1 CKS0 PGMS
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
3
2
IREN
IRQF
IRS1
IRS0
POEN OSEL
R/W
0
R/W
0
R/W
0
R/W
0
PCNTH0 to
PCNTH2
R/W
0
PPG Control Status Register (Lower)
bit
7
Address: ch.0 00003EH
ch.1 000046H
ch.2 00004EH
Read/write
Initial value
-
-
1
R/W
0
0
PCNTL0 to
PCNTL2
R/W
0
263
CHAPTER 13 16-BIT PPG TIMER
13.4.1
PPG Down Counter Register (PDCR0 to PDCR2)
PPG down counter registers (PDCR0 to PDCR2) are 16-bit registers, which are used to
read the count value of the 16-bit PPG down counter.
■ PPG Down Counter Register (PDCR0 to PDCR2)
Figure 13.4-2 PPG Down Counter Register (PDCR0 to PDCR2)
PPG Down Counter Register (Upper)
Address: ch.0 000039H
ch.1 000041H
ch.3 000049H
Read/write
Initial value
bit
15
DC15
14
DC14
R
1
13
12
DC13 DC12
R
1
R
1
11
10
9
8
DC11
DC10
DC09
DC08
R
1
R
1
R
1
R
1
R
1
PDCR0 to
PDCR2
PPG Down Counter Register (Lower)
Address: ch.0 000038H
ch.1 000040H
ch.3 000048H
Read/write
Initial value
bit
7
6
5
DC07
DC06
DC05 DC04
R
1
R
1
R
1
R
1
4
3
2
1
DC03
DC02
DC01
DC00
R
1
R
1
R
1
0
PDCR0 to
PDCR2
R
1
These are 16-bit registers that are used to store the values of the 16-bit down counter. The initial value of
them are all 1. Word access to these register are recommended. These registers are read-only.
264
CHAPTER 13 16-BIT PPG TIMER
13.4.2
PPG Period Setting Buffer Register (PCSR0 to PCSR2)
PPG period setting buffer register is used to set the period of the output pulses
generated by PPG.
■ PPG Period Setting Buffer Register (PCSR0 to PCSR2)
Figure 13.4-3 PPG Period Setting Buffer Register (PCSR0 to PCSR2)
PPG Period Setting Buffer Register (Upper)
Address: ch.0 00003BH
ch.1 000043H
ch.3 00004BH
Read/write
Initial value
bit
15
CS15
14
CS14
W
X
13
12
CS13 CS12
W
X
W
X
11
10
9
8
CS11
CS10
CS09
CS08
W
X
W
X
W
X
W
X
W
X
PCSR0 to
PCSR2
PPG Period Setting Buffer Register (Lower)
Address: ch.0 00003AH
ch.1 000042H
ch.3 00004AH
Read/write
Initial value
7
6
CS07
CS06
CS05 CS04
W
X
W
X
bit
5
W
X
W
X
4
3
2
1
0
CS03
CS02
CS01
CS00
W
X
W
X
W
X
PCSR0 to
PCSR2
W
X
These are 16-bit registers that are used to set the period of the output pulses generated by PPG. The initial
value of them are undetermined, so that these registers must be written before starting an operation. Word
access to these registers are recommended. These registers are write-only.
Data transfer from period setting buffer register to period setting register will be at counter borrow or
trigger or retrigger if enabled.
Note:
In case of updating period setting buffer register, duty setting buffer register must be written after
writing to period setting buffer register. Only updating period setting buffer register is prohibited.
265
CHAPTER 13 16-BIT PPG TIMER
13.4.3
PPG Duty Setting Buffer Register (PDUT0 to PDUT2)
PPG duty setting buffer register is used to control the duty ratio of the output pulses
generated by PPG.
■ PPG Duty Setting Buffer Register (PDUT0 to PDUT2)
Figure 13.4-4 PPG Duty Setting Buffer Register (PDUT0 to PDUT2)
PPG Duty Setting Buffer Register (Upper)
Address: ch.0 00003DH
ch.1 000045H
ch.3 00004DH
Read/write
Initial value
bit
15
DU15
14
DU14
W
X
13
12
DU13 DU12
W
X
11
10
9
8
DU11
DU10
DU09
DU08
W
X
W
X
W
X
W
X
4
3
2
1
DU11
DU10
DU09
DU08
W
X
W
X
W
X
W
X
7
6
5
DU14
DU13 DU12
PDUT0 to
PDUT2
PPG Duty Setting Buffer Register (Lower)
Address: ch.0 00003CH
ch.1 000044H
ch.3 00004CH
Read/write
Initial value
bit
DU15
W
X
W
X
W
X
W
X
W
X
0
PDUT0 to
PDUT2
W
X
These are 16-bit registers that are used to control the duty ratio of the output pulses generated by PPG. The
initial value of them are undetermined, so that these registers must be set a value before starting an
operation. Word access instruction to these registers are recommended. These registers are write-only.
Data transfer from duty setting buffer register to duty setting register is at counter borrow or trigger or
retrigger if enabled.
Setting the same value in both the period setting register and duty setting register outputs all "H"s for
normal polarity and all "L"s for inverted polarity.
The output of the PPG is indeterminate if PCSR < PDUT.
Note:
266
Duty setting buffer register can be written in the case of not updating period setting buffer register.
CHAPTER 13 16-BIT PPG TIMER
13.4.4
PPG Control Status Register (PCNTL0 to PCNTL2,
PCNTH0 to PCNTH2)
PPG control status register is used to set operating conditions for 16-bit PPG timer
enable or disable operation, software trigger, retrigger control interrupt, output polarity
and check the status
■ PPG Control Status Register, Upper Byte (PCNTH0 to PCNTH2)
Figure 13.4-5 PPG0 to PPG2 Control Register (PCNTH0 to PCNTH2)
Address bit
ch.0 : 00003FH
ch.1: 000047H
ch.2 : 00004FH
15
14
13
12
11
10
9
8
Initial value
CNTE
STGR
MDSE
RTRG
CKS2
CKS1
CKS0
PGMS
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PGMS
PPG output mask enable bit
0
PPG output masking disabled
1
PPG output masking enabled
CKS2 CKS1 CKS0
Counter clock selection bits
0
0
0
φ (62.5 ns, φ = 16 MHz)
0
0
1
φ/2 (125 ns, φ = 16 MHz)
0
1
0
φ/4 (250 ns, φ = 16 MHz)
0
1
1
φ/8 (500 ns, φ = 16 MHz)
1
0
0
φ/16 (1 µs, φ = 16 MHz)
1
0
1
φ/32 (2 µs, φ = 16 MHz)
1
1
0
φ/64 (4 µs, φ = 16 MHz)
1
1
1
φ/128 (8 µs, φ = 16 MHz)
φ: Machine clock
RTRG
Retrigger enable bit
0
Retriggering disabled
1
Retriggering enabled
MDSE
Mode selection bit
0
PWM mode
1
Single-shot mode
Software trigger bit
STGR
write
0
No software trigger
1
Trigger the PPG by software
read
Always read “0”
CNTE
R/W : Read and Write
: Initial value
Timer enable bit
0
Stop the PPG timer
1
Enable the PPG timer
267
CHAPTER 13 16-BIT PPG TIMER
Table 13.4-1 PPG Control Register (PCNTH0 to PCNTH2) Bit
Bit name
Function
bit15
CNTE:
Timer enable
bit
• This bit is used to enable the PPG timer operation.
• Writing “1” will enable the PPG operation and wait for trigger to start PPG
operation.
• Writing “0” will stop the operation.
bit14
STGR:
Software trigger
bit
• This bit is the software trigger bit for PPG.
• Writing “1” to this bit triggers the PPG by software.
• This bit is always read as “0”.
bit13
MDSE:
Mode selection bit
• When this bit is “0”, PPG operates in PWM mode.
• When this bit is “1”, PPG operates in single-shot mode.
bit12
RTRG:
Retrigger enable
bit
• This bit is used to enable retriggering function of PPG during operation.
• When this bit is “0”, retriggering function is disabled.
• When this bit is “1”, retriggering function is enabled.
bit11
to
bit9
CKS2 to CKS0:
Counter clock
selection bits
• This bit are used to select the operation clock for 16-bit PPG timer.
PGMS:
PPG output mask
enable bit
• This bit is used to mask the PPG output to specific level regardless of the mode
setting (PCNTH:MDSE), period setting (PCSR) or duty setting (PDUT).
• Write “0” will disable PPG output masking function.
• Writing “1” to this bit masks the PPG output to always “L” when polarity
setting is “Normal” (PCNTL:OSEL=0).
• Writing “1” to this bit masks the PPG output to always “H” when polarity
setting is “Inverted” (PCNTL:OSEL=1).
(Note)
By setting period setting register (PCSR) and duty setting register (PDUT) with
same value, all “H” in normal polarity or all “L” in inverted polarity can be
outputted when this bit is “1”.
bit8
268
CHAPTER 13 16-BIT PPG TIMER
■ PPG Control Status Register, Lower Byte (PCNTL0 to PCNTL2)
Figure 13.4-6 PPG Control Register (PCNTL0 to PCNTL2)
Address
bit
7
ch.0: 00003EH
ch.1: 000046H
ch.2: 00004EH
6
5
4
3
2
1
0
Initial value
IREN
IRQF
IRS1
IRS0
POEN
OSEL
--000000B
R/W
R/W
R/W
R/W
R/W
R/W
OSEL
Output inversion bit
0
Normal polarity
1
Inverted polarity
POEN
Output enable bit
0
General-purpose I/O pin (P37/P36/P46)
1
PPG output pin (PPG0/PPG1/PPG2)
IRS1
IRS0
Interrupt type
0
0
Gate trigger (channel 0 only) / Software trigger /
Retigger
0
1
Counter borrow
1
0
PPG output rising in normal polarity or PPG output
falling in inverted polarity (duty match)
1
1
Counter borrow or PPG output rising in normal
polarity or PPG output falling in inverted polarity
PPG interrupt request flag
IRQF
R/W : Read and Write
-
: Not used
: Initial value
Read
Write
0
No PPG interrupt generated
Clear this bit
1
PPG interrupt generated
No effect
IREN
PPG interrupt request enable bit
0
Interrupt request disabled
1
Interrupt request enabled
269
CHAPTER 13 16-BIT PPG TIMER
Table 13.4-2 PPG Control Register (PCNTL0 to PCNTL2)
Bit name
Function
bit7,
bit6
Unused bit
• This read value is indeterminate.
• Writing to this bit has no effect on the operation.
bit5
IREN:
PPG interrupt
request enable bit
• This bit enable or disables PPG interrupt request to the CPU.
• When this bit and the interrupt flag (IRQF) bit are “1”, PPG outputs an interrupt
request.
bit4
IRQF:
PPG interrupt flag bit
•
•
•
•
•
bit3,
bit2
IRS1, IRS0:
Interrupt selection bit
• These bits are used to select interrupt condition of the PPG timer.
bit1
POEN:
Output enable bit
• This bit enables or disables output from the PPG output pin.
• When this bit is “0”, the pin functions as a general purpose port.
• When this bit is “1”, the pin functions as a PPG timer output pin.
OSEL:
Output inversion bit
• This bit selects the polarity of PPG output pin.
• When this bit is “0”, normal polarity is selected. PPG outputs “L” when 16-bit down
count value is greater than PDUT, and outputs “H” when smaller than or equals to
PDUT.
• When this bit is “1”, the PPG output is inverted.
bit0
270
This bit is set to "1" when PPG interrupt occurs.
Writing "0" will clear this bit.
Writing "1" has no effect.
In read-modify-write operation, “1” is always read.
This bit is also cleared when EI2OS is activated.
CHAPTER 13 16-BIT PPG TIMER
13.5
16-bit PPG Timer Interrupts
The 16-bit PPG timer is enabled to generate an interrupt request when trigger or counter
borrow or PPG rising in normal polarity or PPG falling in inverted polarity depending on
PCNTL=IRS1, IRS0 setting. It is also coordinated with the extended intelligent I/O
service (EI2OS).
■ 16-bit PPG Timer Interrupts
Table 13.5-1 list the interrupt control bits and interrupt causes of the 16-bit PPG timer.
Table 13.5-1 Interrupt Control Bits and Interrupt Causes of the 16-bit PPG Timer
16-bit PPG timer 0
16-bit PPG timer 1
16-bit PPG timer 2
Interrupt flag bit
PCNTL0:IRQF
PCNTL1:IRQF
PCNTL2:IRQF
Interrupt request enable bit
PCNTL0:IREN
PCNTL1:IREN
PCNTL2:IREN
Interrupt type selection bit
PCNTL0:IRS1,IRS0
PCNTL1:IRS1,IRS0
PCNTL2:IRS1,IRS0
PCNTL0:IRS1,IRS0=00
gate trigger/software trigger/
retrigger of 16-bit down
counter (ch.0)
PCNTL1:IRS1,IRS0=00
software trigger/retrigger of
16-bit down counter (ch.1)
PCNTL2:IRS1,IRS0=00
software trigger/retrigger of
16-bit down counter (ch.2)
PCNTL2:IRS1,IRS0=01
PCNTL0:IRS1,IRS0=01
PCNTL1:IRS1,IRS0=01
counter borrow of 16-bit down counter borrow of 16-bit down counter borrow of 16-bit down
counter (ch.1)
counter (ch.2)
counter (ch.0)
Interrupt cause
PCNTL0:IRS1,IRS0=10
PPG0 output rising in normal
polarity or PPG0 output falling
in inverted polarity
PCNTL1:IRS1,IRS0=10
PPG1 output rising in normal
polarity or PPG1 output falling
in inverted polarity
PCNTL2:IRS1,IRS0=10
PPG2 output rising in normal
polarity or PPG2 output
falling in inverted polarity
PCNTL0:IRS1,IRS0=11
Counter borrow of 16-bit down
counter (ch.0) or PPG0 output
rising in normal polarity or
PPG0 output falling in inverted
polarity
PCNTL0:IRS1,IRS0=11
Counter borrow of 16-bit down
counter (ch.1) or PPG1 output
rising in normal polarity or
PPG1 output falling in inverted
polarity
PCNTL0:IRS1,IRS0=11
Counter borrow of 16-bit
down counter (ch.2) or PPG2
output rising in normal
polarity or PPG2 output
falling in inverted polarity
In the 16-bit PPG timer, the IRQF bit of the PPG control status register (PCNTL) is set to "1" and an
interrupt request is enabled (PCNTL: IREN=1), the interrupt request is outputted to the interrupt controller.
271
CHAPTER 13 16-BIT PPG TIMER
■ 16-bit PPG Timer Interrupts and EI2OS
Table 13.5-2 lists the 16-bit PPG timer interrupts and EI2OS.
Table 13.5-2 16-bit PPG Timer Interrupts and EI2OS
Interrupt
number
Channel
Interrupt control register
Vector table address
EI2OS
Register name
Address
Lower
Middle
Upper
16-bit PPG timer 0*1
#14 (0EH)
ICR01
0000B1H
FFFFC4H
FFFFC5H
FFFFC6H
16-bit PPG timer 1*2
#16 (10H)
ICR02
0000B2H
FFFFBCH
FFFFBDH
FFFFBEH
16-bit PPG timer 2*3
#32 (20H)
ICR10
0000BAH
FFFF7CH
FFFF7DH
FFFF7EH
O
*1: The same interrupt control register as that for 16-bit PPG timer 0 is assigned to PWC timer 0.
*2: The same interrupt control register as that for 16-bit PPG timer 1 is assigned to 16-bit output compare channel 1 match.
*3: The same interrupt control register as that for 16-bit PPG timer 2 is assigned to 16-bit free-run timer zero detect.
■ EI2OS Function of the 16-bit PPG Timer
Since the 16-bit PPG timer has a circuit that coordinates with EI2OS, the counter can start EI2OS when
PPG interrupt occurs.
However, EI2OS is available only when other peripheral functions sharing the interrupt control register
(ICR) do not use interrupts. For example, when 16-bit PPG timer 0 uses EI2OS, interrupts of the output
compare channel 0 match must be disabled.
272
CHAPTER 13 16-BIT PPG TIMER
13.6
Operation of 16-bit PPG Timer
The 16-bit PPG Timer operate in either PWM mode or single shot mode. And
Retriggering can be enabled.
■ PWM Mode (PCNTL: MDSE = 0)
For PWM operation, the 16-bit down counter will be loaded with PCSR value, starts counting after a valid
trigger is detected. And once the 16-bit down counter reached zero, it is reloaded with PCSR value and
repeat counting again. PPG output is toggled when 16-bit down counter is reloaded. The period of the
output pulses can be controlled by setting PCSR and the duty ratio controlled by setting PDUT.
a) Retriggering is disabled (PCNTH: RTRG = 0)
Figure 13.6-1 Retriggering is disabled in PWM Mode
Counter value
m
n
0
Time
Rising edge detected
Trigger is ignored
Software trigger
PPG
(normal polarity)
(inverted polarity)
(1)
T: Count clock period
m: PCSR value
n: PDUT value
(2)
(1) = (n+1)*T ns
(2) = (m+1)*T ns
b) Retriggering is enabled (PCNTH: RTRG = 1)
Figure 13.6-2 Retriggering is enabled in PWM Mode
Counter value
m
n
Time
0
Rising edge detected
Restarted by trigger
Software trigger
PPG
(normal polarity)
PPG
(inverted polarity)
(1)
(2) = (m+1)*T ns
(1) = (n+1)*T ns
(2)
m: PCSR value
n: PDUT value
T: Count clock period
273
CHAPTER 13 16-BIT PPG TIMER
■ Single-shot Mode (PCNTL: MDSE = 1)
For single-shot operation, a single pulse of specified width can be output by a valid trigger. When
retriggering is enabled, the counter is reloaded if an edge is detected during operation.
a) Retriggering is disabled (PCNTH: RTRG = 0)
Figure 13.6-3 Retriggering is disabled in Single-shot Mode
Counter value
m
n
Time
0
Rising edge detected
Trigger is ignored
Software trigger
PPG
(normal polarity)
PPG
(inverted polarity)
(1)
(2)
T: Count clock period
m: PCSR value
n: PDUT value
(1) = (n+1)*T ns
(2) = (m+1)*T ns
b) Retriggering is enabled (PCNTH: RTRG = 1)
Figure 13.6-4 Retriggering is enabled in Single-shot Mode
Counter value
m
n
Time
0
Software trigger
Rising edge detected
Restarted by trigger
PPG
(normal polarity)
PPG
(inverted polarity)
(1)
(2)
(1) = (n+1)*T ns
(2) = (m+1)*T ns
274
T: Count clock period
m: PCSR value
n: PDUT value
CHAPTER 13 16-BIT PPG TIMER
■ Gate Trigger (PPG channel 0 only)
When gate trigger is used, PPG starts operation when rising edge of gate trigger is detected and stops when
falling is detected. In next rising edge, PPG restarts operation again.
Figure 13.6-5 Gate Trigger in PWM Mode when retriggering is enable
Counter value
m
n
0
Time
Rising edge detected
Falling edge detected
Gate trigger
PPG
(normal polarity)
(inverted polarity)
(1)
(2)
T: Count clock period
m: PCSR value
n: PDUT value
(1) = (n+1)*T ns
(2) = (m+1)*T ns
■ PPG Interrupts
There are four types of interrupts sharing one interrupt flag (PCNTL:IRQF) selected by interrupt type bits
(PCNTL:IRS1,IRS0).
• Gate trigger (for PPG channel 0 only) or software trigger or retrigger
• Counter borrow
• Duty match occurs when PPG output rising in normal polarity or PPG output falling in inverted polarity
• Counter borrow or duty match
Figure 13.6-6 PPG Interrupt Timing
Software trigger
Load
Count clock
Counter value
0002H
0001H
0000H
0002H
PPG output
(normal polarity)
Interrupt
(by software trigger)
Interrupt
(by duty match)
Interrupt
(by counter borrow)
275
CHAPTER 13 16-BIT PPG TIMER
13.7
Usage Notes on the 16-bit PPG Timer
Notes on using the 16-bit PPG timer are given below.
■ Usage Notes on the 16-bit PPG Timer
● Notes on using a program for setting
• Write a value to the period setting buffer register (PCSR), duty setting buffer register (PDUT) must be
written after writing to PCSR. Only updating PCSR is prohibited. Be sure to use a word transfer
instruction (MOVW A, dir, etc.) to access PCSR and PDUT.
• Always set the value of duty setting buffer register (PDUT) not greater than period setting buffer
register (PCSR), otherwise the output of PPG is indeterminate.
• Change the CKS2, CKS1 and CKS0 bits of the control status register (PCNTH) when the PPG is
stopped (PCNTH: CNTE=0).
● Notes about interrupts
• When the IRQF bit of the PPG control status register (PCNTL) is set to "1" and an interrupt request is
enabled (PCNTL: IREN = 1), control cannot be returned from interrupt processing. Always clear the
IRQF bit.
• Since the 16-bit PPG timer shares an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the 16-bit PPG timer, shared resource interrupts must be disabled.
276
CHAPTER 13 16-BIT PPG TIMER
13.8
Sample Programs for the 16-bit PPG Timer
This section contains sample programs for the 16-bit PPG timer.
■ Sample Program for the 16-bit PPG Timer
● Processing
• An output in 160 kHz with 60% duty is generated with 16-bit PPG timer 0.
• The timer is used in PWM mode to repeatedly generate an interrupt.
• The timer is started with a software trigger.
• EI2OS is not used.
• 16 MHz is used for the machine clock, and 62.5 ns is used for the count clock.
● Coding example
ICR01
EQU
0000B1H
;Interrupt control register for the 16-bit PPG timer
PCSR0
EQU
00003AH
;PPG period setting register
PDUT0
EQU
00003CH
;PPG duty setting register
PCNT0
EQU
00003EH
;PPG control status register
IRQF
EQU
PCNT0:4
;Interrupt request flag bit
;-------Main program---------------------------------------------------------------------------------CODE
CSEG
START:
;
:
;Assumes that stack pointer (SP) has already been
initialized
AND
CCR,#0BFH
;Interrupt disable
MOV
I:ICR01,#00H
;Interrupt level 0 (strongest)
MOVW
I:PCSR0,#0063H
;Sets the period of the PPG output
MOVW
I:PDUT0,#003BH
;Sets the duty ratio of the PPG output
MOVW
I:PCNT0,#01100000000100110B
;Enables PPG output in normal polarity
;Enables 16-bit PPG timer, and 62.5 ns clock
;Software triggers PPG
;Select PWM mode and enable interrupt
;Clears interrupt flag, and starts counter
LOOP:
MOV
ILM,#07H
;Sets ILM in PS to level 7
OR
CCR,#40H
;Interrupt enable
MOV
A,#00H
;Endless loop
MOV
A,#01H
;
BRA
LOOP
;
277
CHAPTER 13 16-BIT PPG TIMER
;-------Interrupt program----------------------------------------------------------------------------WARI:
CLRB
I:IRQF
;
:
;
User processing
;
:
RETI
CODE
;Clears interrupt request flag
;Returns from interrupt
ENDS
;-------Vector setting---------------------------------------------------------------------------------VECT
VECT
CSEG
ABS=0FFH
ORG
0FFC4H
DSL
WARI
ORG
0FFDCH
DSL
START
DB
00H
ENDS
END
278
START
;Sets vector for interrupt #14 (0EH)
;Sets reset vector
;Sets single-chip mode
CHAPTER 14
MULTI-FUNCTIONAL TIMER
This chapter describes the functions and operation of
the multi-functional timer.
14.1 Overview of Multi-functional Timer
14.2 Block Diagram of Multi-functional Timer
14.3 Multi-functional Timer Pins
14.4 Registers of Multi-functional Timer
14.5 Multi-functional Timer Interrupts
14.6 Operation of Multi-functional Timer
14.7 Usage Notes on the Multi-functional Timer
14.8 Sample Programs for the Multi-functional Timer
279
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.1
Overview of Multi-functional Timer
The multi-functional timer consists of a 16-bit free-run timer, six 16-bit output compare,
four 16-bit input capture, 1 channel of 16-bit PPG timer and a waveform generator. By
using this waveform generator, 12 independent waveform can be outputted through 16bit free-run timer. Furthermore input pulse width measurement and external clock cycle
measurement can be done.
■ 16-bit Free-run Timer (× 1)
• The 16-bit free-run timer consists of a 16-bit up/up-down counter, control register, 16-bit compare clear
register (with buffer register) and a prescaler.
• 8 types of counter operation clock (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128) can be selected (φ is the
machine clock).
• Compare clear interrupt is generated when there is a compare match with compare clear register and 16bit free-run timer. Zero detection interrupt is generated while 16-bit free-run timer is detected as zero in
count value.
• The compare clear register has a selectable buffer register, into which data is written for transfer to the
compare clear register. When the timer is stopped, transfer occurs immediately when the data is written
to the buffer. When the timer is operation, data transfer from the buffer occurs when the timer value is
detected to be zero.
• Reset, software clear, compare match with compare clear register in up-count mode will reset the
counter value to "0000H".
• The output value of this counter can be used as the count clock of the output compares and input
captures in multi-functional timer.
■ 16-bit Output Compare (× 6)
• The output compare consists of six 16-bit compare registers (with selectable buffer register), compare
output latch and compare control registers. An interrupt is generated and output level is inverted when
the value of 16-bit free-run timer and compare register are matched.
• 6 compare registers can be operated independently.
Output pins and interrupt flag are corresponding to each compare register.
• 2 compare registers can be paired to control the output pins.
Inverts output pins by using 2 compare registers together.
• Setting the initial value for each output pin is possible.
• An interrupt is generated when output compare register is matched with 16-bit free-run timer.
280
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ 16-bit Input Capture (× 4)
Input capture consists of 4 independent external input pins, the corresponding capture register and capture
control register. By detecting any edge of the input signal from the external pin, the value of the 16-bit freerun timer can be stored in the capture register and an interrupt is generated simultaneously.
• 3 types of trigger edge (rising edge, falling edge and both edge) of the external input signal can be
selected and there is indication bit to show the trigger edge is rising or falling.
• 4 input captures can be operated independently.
• An interrupt is generated by detecting a valid edge from external input.
• Channel 0 and 1 share interrupt #33.
• Channel 2 and 3 share interrupt #35.
■ 16-bit PPG Timer (× 1)
The 16-bit PPG timer 0 is used to provide a PPG signal for waveform generator. The detail of 16-bit PPG
timer 0 is described in Chapter 13.
■ Waveform Generator
The waveform generator consists of three 16-bit timer registers, three timer control registers and 16-bit
waveform control register.
With waveform generator, it is possible to generate real-time output, 16-bit PPG waveform output, nonoverlap 3-phase waveform output for inverter control and DC chopper waveform output.
• It is possible to generate a non-overlap waveform output based on dead-time of 16-bit timer. (Dead-time
timer function)
• It is possible to generate a non-overlap waveform output when real-time output is operated in 2-channel
mode. (Dead-time timer function)
• By detecting real-time output compare match, GATE signal of the PPG timer operation will be
generated to start or stop PPG timer operation. (GATE function)
• When a match is detected by real-time output compare, the 16-bit timer is activated. The PPG timer can
be started or stopped easily by generating a GATE signal for PPG operation until the 16-bit timer stops.
(GATE function)
• Forced stop control using DTTI0 pin input
281
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.2
Block Diagram of Multi-functional Timer
The block diagram of the multi-functional timer will be described in the following
sections.
■ Block Diagram of Multi-functional Timer
Figure 14.2-1 Block Diagram of Multi-functional Timer
Real time I/O
16-bit output
compare
Interrupt #12
Interrupt #15
Interrupt #17
Interrupt #19
Interrupt #21
Interrupt #23
Output compare 0
Output compare 1
Output compare 2
Output compare 3
Output compare 4
Output compare 5
RT0 to RT5
F2MC-16LX bus
A/D trigger
16-bit freerun timer
Zero detect
Compare clear
RTO1
Pin
P31/RTO1 (X)
RTO2
Pin
P32/RTO2 (V)
RTO3
Pin
P33/RTO3 (Y)
RTO4
Pin
P34/RTO4 (W)
RTO5
Pin
P35/RTO5 (Z)
DTTI
Pin
P10/INT0/DTTI0
16-bit timer 0/1/2
underflow
Interrupt #20
DTTI0 falling edge detect
PPG0
PPG0
GATE
GATE
Pin
P17/FRCK
IN0
Pin
P24/IN0
IN1
Pin
P25/IN1
IN2
Pin
P26/IN2
IN3
Pin
P27/IN3
Interrupt #33
Interrupt #35
16-bit input
capture
Interrupt #29
A/D trigger
EXCK
282
P30/RTO0 (U)
Counter value
Interrupt #31
Interrupt #34
Counter value
Pin
RT0 to RT5
Waveform
generator
Buffer transfer
RTO0
Input capture 0/1
Input capture 2/3
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Block Diagram of 16-bit Free-run TImer
Figure 14.2-2 Block Diagram of 16-bit Free-run Timer
φ
STOP
STOP
MODE
SCLR
UP/UP-DOWN
CLK2
CLK1
CLK0
Prescaler
CLR
Zero detect
circuit
16-bit free-run
timer
Zero detect (to output compare)
CK
To input capture &
output compare
transfer
Compare circuit
Compare clear match (to output compare)
16-bit compare clear
buffer register
I0
I1
O
Interrupt #31 (1FH)
I1
I0
Selector
O
Selector
F2MC-16LX bus
16-bit compare
clear register
I0
I1
O
Interrupt #34 (22H)
Selector
Mask circuit
A/D trigger
MSI2
MSI1
MSI0
ICLR
ICRE
IRQZF
IRQZE
I0
I1
O
Selector
283
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Block Diagram of 16-bit Output Compare
Figure 14.2-3 Block Diagram of 16-bit Output Compare
Count value from free-run timer
BTS0
BUF0
Compare buffer register 0/2/4
O
Compare register 0/2/4
F2MC-16LX bus
Zero detect from
free-run timer
Compare clear match from
free-run timer
I0
transfer
I1
Selector
BTS1
BUF1
Compare circuit
I0
O
Compare buffer register 1/3/5
Selector
transfer
Compare register 1/3/5
I1
CMOD
Compare circuit
IOP1
IOP0
IOE1
T
Q
RT0/RT2/RT4
(Waveform
generator)
T
Q
RT1/RT3/RT5
(Waveform
generator)
IOE0
Interrupt
#12, #17, #21
#15, #19, #23
■ Block Diagram of 16-bit Input Capture
Figure 14.2-4 Block Diagram of 16-bit Input Capture
Count value from free-run timer
Edge detect
F2MC-16LX bus
Capture register 0/2
EG11 EG10 EG01 EG00
Edge detect
Capture register 1/3
ICP0
ICP1
ICE0
IN0/IN2
IEI1
IEI0
IN1/IN3
ICE1
Interrupt
#33, #35
#33, #35
284
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Block Diagram of Waveform Generator
Figure 14.2-5 Waveform Generator Block Diagram
DCK2 DCK1 DCK0 NRSL DTIF DTIE NWS1 NWS0
φ
DTTI0 control circuit
Divider
PICSH01
DTCR0 TMD2
TMD1
TMD0
SIGCR
Noise cancellation
DTTI0
PGEN1 PGEN0
GTEN1 GTEN0
GATE 0/1
GATE
(to PPG0)
TO0
Waveform control
RT0
Selector
16-bit timer 0
Compare circuit
Selector
Output control
TO1
RT1
RTO1 (X)
U
16-bit timer register 0
RTO0 (U)
Dead time generator
X
DTCR1 TMD2
TMD1
TMD0
GATE 2/3
PGEN3 PGEN2
TO2
Waveform control
RT2
TO3
RT3
Selector
16-bit timer 1
Compare circuit
Selector
Output control
F2MC-16LX bus
PICSH01
GTEN1 GTEN0
RTO3 (Y)
V
16-bit timer register 1
RTO2 (V)
Dead time generator
Y
DTCR2 TMD2
TMD1
TMD0
GTEN1 GTEN0
GATE 4/5
PICSH01 PGEN5 PGEN4
TO4
Waveform control
RT4
Selector
16-bit timer 2
Compare circuit
Selector
W
16-bit timer register 2
Output control
TO5
RT5
RTO4 (W)
RTO5 (Z)
Dead time generator
PPG0
Z
285
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.3
Multi-functional Timer Pins
This section describes the pins of the multi-functional timer and provides a pin block
diagram.
■ Multi-functional Timer Pins
Table 14.3-1 Multi-functional Timer Pins
Pin Name
Pin function
P10/INT0/
DTTI0
Port 1 input-output/
external interrupt input/
DTTI0
I/O format
Pull-up option
Standby
control
Setting required for pins
Set the pin as an input port
(DDR1:bit8 = 0)
Selectable
P17/FRCK
Port 1 input-output/
external clock
Set the pin as an input port
(DDR1:bit15 = 0)
P24/IN0
Port 2 input-output/
input capture 0
P25/IN1
Port 2 input-output/
input capture 1
P26/IN2
Port 2 input-output/
input capture 2
Set the pin as an input port
(DDR2:bit6 = 0)
P27/IN3
Port 2 input-output/
input capture 3
Set the pin as an input port
(DDR2:bit7 = 0)
Set the pin as an input port
(DDR2:bit4 = 0)
CMOS output/
CMOS hysteresis
input
Set the pin as an input port
(DDR2:bit5 = 0)
Provided
P30/RTO0 (U)
Port 3 input-output/
RTO0
Set RTO0 output
(OCS1:OTE0 = 1)
P31/RTO1 (X)
Port 3 input-output/
RTO1
Set RTO1 output
(OCS1:OTE1 = 1)
P32/RTO2 (V)
Port 3 input-output/
RTO2
Set RTO2 output
(OCS3:OTE0 = 1)
Not provided
CMOS output/
CMOS input
P33/RTO3 (Y)
Port 3 input-output/
RTO3
P34/RTO4 (W)
Port 3 input-output/
RTO4
Set RTO4 output
(OCS5:OTE0 = 1)
P35/RTO5 (Z)
Port 3 input-output/
RTO5
Set RTO5 output
(OCS5:OTE1 = 1)
286
Set RTO3 output
(OCS3:OTE1 = 1)
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Block Diagram of Multi-functional Timer Pins
Figure 14.3-1 Block Diagram of P10/INT0/DTTI0, P17/FRCK
RDR
Resource input
Resource output
Port data register (PDR)
Resource output enable
Pull-up resistor
About 50k
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
Figure 14.3-2 Block Diagram of P24/IN0 to P27/IN3
Resource output
Resource input
Resource output enable
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
287
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Figure 14.3-3 Block Diagram of P30/RTO0 to P35/RTO5
Resource output
Resource output enable
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
288
Standby control (SPL = 1)
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.4
Registers of Multi-functional Timer
This section describes registers of multi-functional timer.
■ 16-bit Free-run Timer Registers
Figure 14.4-1 Registers of 16-bit Free-run Timer
Compare Clear Buffer Register / Compare Clear Register (Upper)
bit 15
Address: 00005BH
Read/write
Initial value
14
13
12
11
10
9
8
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
1
0
CPCLRB/CPCLR
Compare Clear Buffer Register / Compare Clear Register (Lower)
7
6
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
Address: 00005DH
T15
T14
T13
T12
T11
T10
Read/write
Initial value
R/W
0
R/W
0
bit
Address: 00005AH
Read/write
Initial value
5
4
3
2
CPCLRB/CPCLR
Timer Data Register (Upper)
bit
9
8
T09
T08
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
T01
T00
TCDT
Timer Data Register (Lower)
7
6
5
4
Address: 00005CH
T07
T06
T05
T04
T03
T02
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
12
11
10
ECKE IRQZF IRQZE
MSI2
MSI1
MSI0
ICLR
ICRE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
3
2
1
0
BFE
STOP
CLK2
CLK1
CLK0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
bit
R/W
0
R/W
0
TCDT
R/W
0
Timer Control Status Register (Upper)
bit
Address: 00005FH
Read/write
Initial value
15
R/W
0
14
13
9
8
TCCSH
Timer Control Status Register (Lower)
bit
7
Address: 00005EH
Read/write
Initial value
-
MODE SCLR
R/W
0
R/W
0
TCCSL
289
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ 16-bit Output Compare Registers
Figure 14.4-2 Registers of Output Compare
Output Compare Buffer Register / Output Compare Register (Upper)
Address: ch.0 000071H
ch.1 000073H
ch.2 000075H
ch.3 000077H
ch.4 000079H
ch.5 00007BH
Read/write
Initial value
bit
15
OP15
R/W
X
14
13
12
11
10
OP14
OP13
OP12
OP11 OP10
R/W
X
R/W
X
R/W
X
R/W
X
9
8
OCCPB0 to
OCCPB5/
OCCP0 to
OCCP5
OP09 OP08
R/W
X
R/W
X
R/W
X
Output Compare Buffer Register / Output Compare Register (Lower)
Address: ch.0 000070H
ch.1 000072H
ch.2 000074H
ch.3 000076H
ch.4 000078H
ch.5 00007AH
7
bit
OP07
Read/write
Initial value
6
5
OP06 OP05
R/W
X
R/W
X
4
OP04
R/W
X
R/W
X
3
2
OP03 OP02
R/W
X
1
OP01
R/W
X
0
OCCPB0 to
OCCPB5/
OCCP0 to
OCCP5
OP00
R/W
X
R/W
X
9
8
Compare Control Register (Upper)
bit 15
Address: ch.1 00007DH
ch.3 00007FH
ch.5 000081H
Read/write
Initial value
14
13
12
11
10
BTS1 BTS0 CMOD OTE1 OTE0
R/W
1
-
R/W
1
R/W
0
R/W
0
OCS1/OCS3/
OCS5
OTD1 OTD0
R/W
0
R/W
0
R/W
0
Compare Control Register (Lower)
bit
Address: ch.0 00007CH
ch.2 00007EH
ch.4 000080H
Read/write
Initial value
290
IOP1
R/W
0
7
6
5
4
3
IOP0
IOE1
IOE0
BUF1
BUF0 CST1 CST0
R/W
0
R/W
0
R/W
0
R/W
1
2
R/W
1
1
R/W
0
0
R/W
0
OCS0/OCS2/
OCS4
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Input Capture Registers
Figure 14.4-3 Registers of 16-bit Input Capture
Input Capture Data Register (Upper)
Address: ch.0 000061H
ch.1 000063H
ch.2 000065H
ch.3 000067H
bit 15
CP15
Read/write
Initial value
14
CP14
12
CP13
CP12
R
X
R
X
R
X
R
X
13
11
10
CP11 CP10
8
IPCP0 to
IPCP3
CP09
CP08
R
X
R
X
2
1
CP01
CP00
R
X
R
X
R
X
R
X
9
Input Capture Data Register (Lower)
Address: ch.0 000060H
ch.1 000062H
ch.2 000064H
ch.3 000066H
bit
7
6
5
4
CP07
CP06
CP05
CP04
CP03 CP02
R
X
R
X
R
X
Read/write
Initial value
3
R
X
R
X
R
X
12
11
10
0
IPCP0 to
IPCP3
Input Capture Control Status Register (2/3) (Upper)
bit
15
14
13
Address: 00006BH
Read/write
Initial value
8
IEI3
IEI2
-
-
-
R
0
R
0
5
4
3
2
1
0
ICP2
ICE3
ICE2
EG31
EG30
EG21
EG20
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
9
8
-
-
9
-
ICSH23
Input Capture Control Status Register (2/3) (Lower)
bit
7
ICP3
Address: 00006AH
Read/write
Initial value
R/W
0
6
PPG output control/ Input Capture Control Status Register (0/1) (Upper)
14
13
12
11
10
bit 15
Address: 000069H
PGEN5 PGEN4 PGEN3 PGEN2 PGEN1 PGEN0
Read/write
Initial value
R/W
0
R/W
0
IEI1
IEI0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
5
4
3
2
1
0
ICSL23
PICSH01
Input Capture Control Register (0/1)
bit
Address: 000068H
Read/write
Initial value
7
6
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PICSL01
291
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Waveform Generator Registers
Figure 14.4-4 Registers of Waveform Generator
16-bit Timer Register (Upper)
15
14
13
12
11
10
9
TR15
TR14
TR13
TR12
TR11
TR10
TR09
TR08
R/W
X
R/W
X
bit
Address: ch.0 000051H
ch.1 000053H
ch.2 000055H
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
8
TMRR0/TMRR1/
TMRR2
R/W
X
16-bit Timer Register (Lower)
7
6
5
4
3
2
1
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
14
13
12
11
10
bit
Address: ch.0 000050H
ch.1 000052H
ch.2 000054H
Read/write
Initial value
0
R/W
X
R/W
X
9
8
TMRR0/TMRR1/
TMRR2
16-bit Timer Control Register
bit
Address: ch.1 000057H
Read/write
Initial value
15
DTCR1
DMOD GTEN1 GTEN0 TMIF
R/W
0
R/W
0
R/W
0
TMIE
TMD2 TMD1 TMD0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
5
4
3
TMIE
TMD2 TMD1 TMD0
16-bit Timer Control Register
bit
Address: ch.0 000056H
ch.2 000058H
Read/write
Initial value
7
6
DMOD GTEN1 GTEN0 TMIF
R/W
0
2
R/W
0
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
DTIE
DTIF
NRSL
DCK2
DCK1
DCK0 NWS1 NWS0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
DTCR0/DTCR2
R/W
0
Waveform Control Register
bit
Address: 000059H
Read/write
Initial value
292
10
9
R/W
0
8
R/W
0
SIGCR
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.4.1
Compare Clear Buffer Register (CPCLRB) and Compare
Clear Register (CPCLR)
Compare clear buffer register (CPCLRB) is a 16-bit buffer register of compare clear
register (CPCLR). Both CPCLRB and CPCLR registers are located in the same address.
■ Compare Clear Buffer Register (CPCLRB)
Figure 14.4-5 Compare Clear Buffer Register (CPCLRB)
Compare Clear Buffer Register (Upper)
bit
15
14
Address: 00005BH
CL15
CL14
Read/write
Initial value
W
W
1
1
Compare Clear Buffer Register (Lower)
7
6
bit
Address: 00005AH
Read/write
Initial value
13
12
11
10
9
8
CL13
CL12
CL11
CL10
CL09
CL08
W
1
W
1
W
1
W
1
W
1
W
1
5
4
3
2
1
0
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
W
1
W
1
W
1
W
1
W
1
W
1
W
1
W
1
CPCLRB
CPCLRB
Compare Clear Buffer Register is the buffer register for Compare Clear Register. When buffer function is
disabled (TCCSL:BFE=0) or when free-run timer is stopped, value in Compare clear buffer register is
transferred to Compare clear register immediately. When buffer function is enabled, value is transferred
when the count value of 16-bit free-run timer is detected as zero.
Word access to this register is recommended.
■ Compare Clear Register (CPCLR)
Figure 14.4-6 Compare Clear Register (CPCLR)
Compare Clear Register (Upper)
bit
Address: 00005BH
Read/write
Initial value
15
14
13
12
11
10
9
8
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
R
1
R
1
R
1
R
1
R
1
R
1
R
1
R
1
4
3
CPCLR
Compare Clear Register (Lower)
bit
Address: 00005AH
Read/write
Initial value
7
6
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
R
1
R
1
R
1
R
1
R
1
R
1
R
1
R
1
5
2
1
0
CPCLR
The Compare Clear Register is used to compare with the count value of the 16-bit free-run timer. In upcount mode, when this register is matched with the count value of 16-bit free-run timer, timer will be reset
to "0000H". In up-down count mode, when this register is matched with the count value of the 16-bit freerun timer, the timer changes from up-count to down-count and changes from down-count to up-count at
zero detect.
Word access to this register is recommended.
293
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.4.2
Timer Data Register (TCDT)
The timer data register (TCDT) is used to read the count value of 16-bit free-run timer.
■ Timer Data Register (TCDT)
Figure 14.4-7 Timer Data Register
Timer Data Register (Upper)
bit
15
14
13
12
11
10
Address: 00005DH
T15
T14
T13
T12
T11
T10
Read/write
Initial value
R/W
0
R/W
0
9
8
T09
T08
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
T01
T00
Timer Data Register (Lower)
bit
7
6
5
4
Address: 00005CH
T07
T06
T05
T04
T03
T02
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
TCDT
TCDT
R/W
0
The timer data register is used to read the count value of the 16-bit free-run timer. The counter value is
cleared to "0000H" upon a reset. The timer value can be set by writing a value to this register. However,
ensure that the value is written while the operation is stopped (STOP = 1). Word access instruction to the
timer data register is recommended.
The 16-bit free-run timer is initialized upon the following factors:
• Reset
• Clear bit (SCLR) of control status register
• A match between compare clear register and the timer counter value in up-count mode
(TCCSL:MODE=0)
294
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.4.3
Timer Control Status Register (TCCSH, TCCSL)
The timer control status register (TCCS) is a 16-bit register and used to control the
operation of 16-bit free-run timer.
■ Timer Control Status Register, Upper Byte (TCCSH)
Figure 14.4-8 Timer Control Status Register (TCCSH)
Address bit15
14
13
12
11
10
9
8
Initial value
00005FH ECKE IRQZFIRQZE MSI2 MSI1 MSI0 ICLR ICRE 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICRE
Compare clear interrupt request enable bit
0
Disable interrupt request
1
Enable interrupt request
Compare clear interrupt flag bit
ICLR
Read
Write
0
No compare-clear match
Clear this bit
1
Compare-clear match
No effect
MSI2 MSI1 MSI0
Interrupt masking selection bits
0
0
0
Interrupt is generated when 1st match
0
0
1
Interrupt is generated when 2nd match
0
1
0
Interrupt is generated when 3rd match
0
1
1
Interrupt is generated when 4th match
1
0
0
Interrupt is generated when 5th match
1
0
1
Interrupt is generated when 6th match
1
1
0
Interrupt is generated when 7th match
1
1
1
Interrupt is generated when 8th match
IRQZE
Zero detect interrupt request enable bit
0
Disable interrupt request
1
Enable interrupt request
Zero detect interrupt flag bit
IRQZF
R/W : Read and Write
: Initial value
Read
Write
0
No zero detect
Clear this bit
1
Zero detect
No effect
ECKE
Clock selection bit
0
Internal clock
1
External clock
295
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-1 Timer Control Status Register (TCCSH)
Bit name
Function
ECKE:
Clock selection bit
• This bit is used to select internal or external clock as count clock for 16-bit free-run
timer.
• Writing “0” selects internal clock. The clock frequency selection bits (CK2 to CK0)
should also be set to select the count clock frequency.
• Writing “1” selects external clock. External clock is input from pin “P17/FRCK”, so
DDR1:7 should be set as “0” to enable external clock input.
(Note)
The count clock is changed immediately after this bit is set. So change this bit while the
output compare and input capture units are stopped.
bit14
IRQZF:
Zero detect
interrupt flag bit
• This bit is an interrupt flag for zero detect.
• When the count value of 16-bit free-run timer is “0000H”, this bit is set to “1”.
• Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
(Note)
• In software clear, (writing TCCSL:SCLR “1”) will not set this bit.
• In up-down count mode (MODE=1) and interrupt mask function is selected (MSI2
to MSI0 not equals 000B), this bit will only be set after the number of zero detect is
masked.
• In up-count mode (MODE=0), this bit is set at every zero detect disregarding the
value of MSI2 to MSI0.
bit13
IRQZE:
Zero detect
interrupt request
enable bit
• This is the interrupt request enable bit for the zero detect.
• When this bit is “1” and the interrupt flag (bit14: IRQZF) is set to “1”, an interrupt
request will be generated to CPU.
MSI2 to MSI0:
Interrupt mask
selection bits
• These bits are used to set the number of times of masking the compare clear interrupt in
up-count mode (MODE=0) or zero detect interrupt in up-down count mode
(MODE=1).
• No interrupt cause is masked when MSI2 to MSI0 equals zero.
(Note)
To mask the interrupt cause twice and perform interrupt processing at the third time,
MSI2 to MSI0 should be set as 010B.
bit9
ICLR:
Compare clear
interrupt flag bit
• This bit is an interrupt flag for compare clear.
• When the compare clear value and 16-bit free-run timer value are matched, this bit is
set to "1".
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
(Note)
• In up-count mode (MODE=0) and interrupt mask function is selected (MSI2 to
MSI0 not equals 000B), this bit will only be set after the number of compare clear is
masked.
• In up-down count mode (MODE=1), this bit is set at every compare clear
disregarding the value of MSI2 to MSI0.
bit8
ICRE:
Compare clear
interrupt request
enable bit
• This is the interrupt request enable bit for the compare clear.
• When this bit is “1” and the interrupt flag (bit9: ICLR) is set to “1”, an interrupt request
will be generated to CPU.
bit15
bit12
to
bit10
296
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ TImer Control Ctatus Register, Lower Byte (TCCSL)
Figure 14.4-9 Timer Control Status Register (TCCSL)
Address bit7
00005EH
6
5
4
3
2
1
0
Initial value
BFE STOP MODE SCLR CLK2 CLK1 CLK0 -0100000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock frequency selection bit
CLK2 CLK1 CLK0
0
0
Count
clock
φ = 16 MHz
φ = 8 MHz
φ = 4 MHz
φ = 1 MHz
0
φ
62.5 ns
125 ns
0.25 µs
1 µs
0
0
1
φ/2
125 ns
0.25 µs
0.5 µs
2 µs
0
1
0
φ/4
0.25 µs
0.5 µs
1 µs
4 µs
0
1
1
φ/8
0.5 µs
1 µs
2 µs
8 µs
1
0
0
φ/16
1 µs
2 µs
4 µs
16 µs
1
0
1
φ/32
2 µs
4 µs
8 µs
32 µs
1
1
0
φ/64
4 µs
8 µs
16 µs
64 µs
1
1
1
φ/128
8 µs
16 µs
32 µs
128 µs
φ: Machine cycle
Timer clear bit
SCLR
Write
R/W : Read and write
: Initial value
—
: Not used
Read
0
Clear SCLR bit
1
Initialize counter to “0000H”
Always read as ”0”
MODE
Timer counting mode
0
up-count mode
1
up-down count mode
STOP
Timer enable bit
0
Counting is enabled (operation)
1
Counting is disabled (stop)
BFE
Compare clear buffer enable bit
0
Disable compare clear buffer
1
Enable compare clear buffer
297
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-2 Timer control status register (TCCSL)
Bit name
bit7
bit6
bit5
bit4
bit3
Function
Unused bit
• The read value is indeterminate.
• Writing to this bit has no effect on the operation.
BFE:
Compare clear
buffer enable bit
• This bit is used to enable compare clear buffer.
• Writing “0” disables compare clear buffer. Directly write in compare clear register is
possible.
• Writing “1” enables compare clear buffer. Data written in compare clear buffer register
will be held and transfer to compare clear register when the count value of 16-bit freerun timer is detected as zero.
STOP:
Timer enable bit
• This bit is used to stop/start the counting of the 16-bit free-run timer.
• Writing “1” stops the counting of the 16-bit free-run timer.
• Writing “0” starts the counting of the 16-bit free-run timer.
(Note)
When the 16-bit free-run timer is stopped, the output compare operation will also be
stopped.
MODE:
Timer counting
mode bit
• This bit is used to select the count mode of the 16-bit free-run timer.
• Writing “0” selects up-count mode. Timer counts up until counter value matches with
compare clear register and reset to “0000H” and then counts up again.
• Writing “1” selects up-down count mode.
In up-down count mode, whenever zero in the timer data register is detected, the timer
counting direction will always be reseted to up-counting.
The timer will reverse its counting direction whenever the timer value matches with
compare clear register.
• This bit can be written at any time whether the timer is operating or stopped. The value
written to this bit is buffered and the count mode will be changed when timer value is
“0000H”.
(Note)
Because the timer will reverse its counting direction when compare-match is detected in
up-down count mode (MODE = 1), it should be careful to set the compare clear register
and timer data register when the timer is being counted down.
SCLR:
Timer clear bit
• This bit is used to initialize the 16-bit free-run timer to “0000H”.
• Writing “1” initializes 16-bit free-run timer to “0000H” at the next count clock.
• Writing “0” will clear the bit SCLR if it is “1”.
• Read value is always “0”.
(Note)
• This bit cannot be used to initialize the timer when timer stops (STOP=1). Writing
“0000H” to timer data register (TCDT) can initialize the timer.
• Writing “1” will not generate zero detect interrupt.
• This bit will be cleared by hardware after the timer is initialized to “0000”. If “0” is written to
the bit before timer initialization, the bit is cleared and the timer did not initi
• Even after "1" is written, the counter value is not initialized if "0" is written to this bit
before the next count clock.
bit2
to
bit0
298
CLK2 to CLK0:
Clock frequency
selection bit
• This bit is used to select count clock for the 16-bit free-run timer.
• The count clock is changed immediately after these bits are set. So change them while
the output compare and input capture units are stopped.
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.4.4
Output Compare Buffer Registers (OCCPB0 to OCCPB5) /
Output Compare Registers (OCCP0 to OCCP5)
Output compare buffer register (OCCPB) is a 16-bit buffer register of output compare
register (OCCP). Both OCCPB and OCCP registers are located in the same address.
■ Output Compare Buffer Registers (OCCPB0 to OCCPB5)
Figure 14.4-10 Output Compare Buffer Registers (OCCPB0 to OCCPB5)
Output Compare Buffer Register (Upper)
Address: ch.0 000071H
ch.1 000073H
ch.2 000075H
ch.3 000077H
ch.4 000079H
ch.5 00007BH
Read/write
Initial value
bit
15
OP15
14
OP14
W
X
W
X
13
12
OP13
OP12
W
X
W
X
11
10
OP11 OP10
9
8
OCCPB0 to
OCCPB5
OP09 OP08
W
X
W
X
W
X
W
X
5
4
3
2
1
OP04
OP03 OP02
OP01
OP00
Output Compare Buffer Register (Lower)
Address: ch.0 000070H
ch.1 000072H
ch.2 000074H
ch.3 000076H
ch.4 000078H
ch.5 00007AH
Read/write
Initial value
bit
7
OP07
W
X
6
OP06 OP05
W
X
W
X
W
X
W
X
W
X
W
X
0
OCCPB0 to
OCCPB5
W
X
Output compare buffer register is the buffer register of output compare register (OCCP). When buffer
function is disabled (OCS0/OCS2/OCS4:BUF0/BUF1=1) or when free-run timer is stopped, value in
output compare buffer register is transferred to output compare register immediately. When buffer function
is enabled (OCS0/OCS2/OCS4:BUF0/BUF1=0), value is transferred at compare clear match or zero
detection depending on transfer selection bit BTS in compare control register (OCS1/OCS3/OCS5).
Word access to this register is recommended.
299
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Output Compare Registers (OCCP0 to OCCP5)
Figure 14.4-11 Output Compare Registers (OCCP0 to OCCP5)
Output Compare Register (Upper)
Address: ch.0 000071H
ch.1 000073H
ch.2 000075H
ch.3 000077H
ch.4 000079H
ch.5 00007BH
Read/write
Initial value
bit
15
OP15
14
13
OP14 OP13
R
X
R
X
12
OP12
R
X
11
10
OP11 OP10
R
X
R
X
9
8
OCCP0 to
OCCP5
OP09 OP08
R
X
R
X
R
X
2
1
OP01
OP00
R
X
R
X
Output Compare Register (Lower)
Address: ch.0 000070H
ch.1 000072H
ch.2 000074H
ch.3 000076H
ch.4 000078H
ch.5 00007AH
Read/write
Initial value
bit
7
OP07
OP06 OP05
R
X
6
R
X
R
X
5
4
OP04
OP03 OP02
R
X
3
R
X
R
X
0
OCCP0 to
OCCP5
The output compare register is a 16-bit register which is used to compare the count value of 16-bit free-run
timer. The initial value of the output compare register is undetermined, so output compare buffer register
(OCCPB) must be set with a value before enabling the operation.
When the value of the output compare register matches the count value of 16-bit free-run timer, a compare
signal is generated to set the output compare interrupt flag (OCS0/OCS2/OCS4:IOP0/IOP1). If output level
is set (OCS1/OCS3/OCS5:OTD0/OTD1), the output level of RT0 to RT5 corresponding to the output
compare register (OCCP0 to OCCP5) can be reversed.
Word access to this register is recommended.
300
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.4.5
Compare Control Registers (OCS0 to OCS5)
Compare control register is used to control the output level, output enable, output
reverse mode, compare operation enable, compare match interrupt enable and compare
match interrupt flag for RTO0 to RTO5.
■ Compare Control Register, Upper Byte (OCS1/OCS3/OCS5)
Figure 14.4-12 Compare Control Register (OCS1/OCS3/OCS5)
Address
bit15
ch.1: 00007DH
ch.3: 00007FH
ch.5: 000081H
—
—
14
13
12
11
10
9
8
Initial value
BTS1 BTS0 CMOD OTE1 OTE0 OTD1 OTD0 -1100000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output level bit
OTD0
Write
Read
0
Output “0” for RT0/RT2/RT4
1
Output “1” for RT0/RT2/RT4
Current output value of RT0/
RT2/RT4
Output level bit
OTD1
R/W : Read and write
: Initial value
—
: Not used
Write
Read
0
Output “0” for RT1/RT3/RT5
1
Output “1” for RT1/RT3/RT5
Current output value of RT1/
RT3/RT5
OTE0
Output enable bit
0
General-purpose port (P30/P32/P34)
1
Output compare output pin (RTO0/RTO2/RTO4)
OTE1
Output enable bit
0
General-purpose port (P31/P33/P35)
1
Output compare output pin (RTO1/RTO3/RTO5)
CMOD
Output level reverse mode bit
0
RT0/RT2/RT4: The level is reversed upon a match with compare register 0/2/4
RT1/RT3/RT5: The level is reversed upon a match with compare register 1/3/5 respectively
1
RT0/RT2/RT4: The level is reversed upon a match with compare register 0/2/4
RT1/RT3/RT5: The level is reversed upon a match with compare register (0or1)/(2or3)/(4or5)
BTS0
Buffer transfer select bit
0
Transfer at zero detect ( channel 0/2/4)
1
Transfer at compare clear match (channel 0/2/4)
BTS1
Buffer transfer select bit
0
Transfer at zero detect (channel 1/3/5)
1
Transfer at compare clear match (channel 1/3/5)
301
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-3 Compare Control Register (OCS1/OCS3/OCS5) bit
Bit name
Function
Unused bit
• The read value is indeterminate.
• Writing to this bit has no effect on the operation.
BTS1
• This bit is used to select when data transfer from output compare buffer register (OCCPB1/
OCCPB3/OCCPB5) to output compare register (OCCP1/OCCP3/OCCP5).
• When BTS1=0, buffer transfer is occurred when count value of 16-bit free-run timer is
detected as zero.
• When BTS1=1, buffer transfer is occurred when compare clear match is occurred in 16-bit
free-run timer.
bit13
BTS0
• This bit is used to select when data transfer from output compare buffer register (OCCPB0/
OCCPB2/OCCPB4) to output compare register (OCCP0/OCCP2/OCCP4).
• When BTS0=0, buffer transfer is occurred when count value of 16-bit free-run timer is
detected as zero.
• When BTS0=1, buffer transfer is occurred when compare clear match is occurred in 16-bit
free-run timer.
bit12
• CMOD is used to switch the pin output level reverse mode upon a match while pin output is
enabled (OTE1 = 1 or OTE0 = 1).
• When CMOD = 0, the output level of the pin is reversed upon a match with corresponding
compare register.
RT0/RT2/RT4: The level is reversed upon a match between the 16-bit free-run timer and compare
register 0/2/4.
RT1/RT3/RT5: The level is reversed upon a match between the 16-bit free-run timer and compare
register 1/3/5.
CMOD:
Output level
• When CMOD = 1, the output level of the pin RT0/RT2/RT4 corresponding to compare register
reverse mode bit
is reversed as same as when CMOD = 0. However, the output level of the pin (RT1/RT3/RT5)
corresponding to compare register 1/3/5 is reversed when a match is detected in compare
register 0/2/4 or 1/3/5. If compare registers 0/2/4 and 1/3/5 have the same value, the same
operation as when only one compare register is used.
RT0/RT2/RT4: The level is reversed upon a match between the 16-bit free-run timer and compare
register 0/2/4.
RT1/RT3/RT5: The level is reversed upon a match between the 16-bit free-run timer and compare
register (0 or 1)/(2 or 3)/(4 or 5).
bit11
OTE1:
Output enable
bit
• This bit is used to enable waveform generator output RTO1/RTO3/RTO5 to P31/P33/P35.
• The initial value for these bits is “0”.
(Note)
If waveform generator is disabled (DTCR:TMD2 to TMD0=000B) RTO1/RTO3/RTO5 output the
same value in output compare RT1/RT3/RT5.
bit10
OTE0:
Output enable
bit
• This bit is used to enable waveform generator output RTO0/RTO2/RTO4 to P30/P32/P34.
• The initial value for these bits is “0”.
(Note)
If waveform generator is disabled (DTCR:TMD2 to TMD0=000B) RTO0/RTO2/RTO4 output the
same value in output compare RT0/RT2/RT4.
bit9
OTD1:
Output level bit
• This bit is used to change the output level for output compare 1/3/5 (RT1/RT3/RT5).
• The initial value of the compare output is “0”.
• Ensure that the compare operation is stopped before a value is written. When reading this bit,
this bit indicate the output compare value in RT1/RT3/RT5.
bit8
OTD0:
Output level bit
• This bit is used to change the output level for output compare 0/2/4 (RT0/RT2/RT4).
• The initial value of the compare output is “0”.
• Ensure that the compare operation is stopped before a value is written. When reading this bit,
this bit indicates the output compare value in RT0/RT2/RT4.
bit15
bit14
302
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Compare Vontrol Tegister, Lower Byte (OCS0/OCS2/OCS4)
Figure 14.4-13 Compare Vontrol Register (OCS0/OCS2/OCS4)
Address
bit7
6
5
4
3
2
1
0
Initial value
ch.0: 00007CH IOP1 IOP0 IOE1 IOE0 BUF1 BUF0 CST1 CST0 00001100B
ch.2: 00007EH R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ch.4: 000080H
CST0
Compare operation enable bit
0
Disable compare operation for compare register 0/2/4
1
Enable compare operation for compare register 0/2/4
CST1
Compare operation enable bit
0
Disable compare operation for compare register 1/3/5
1
Enable compare operation for compare register 1/3/5
BUF0
Compare buffer disable bit
0
Enable compare buffer for compare register 0/2/4
1
Disable compare buffer for compare register 0/2/4
BUF1
Compare buffer disable bit
0
Enable compare buffer for compare register 1/3/5
1
Disable compare buffer for compare register 1/3/5
IOE0
Compare match interrupt enable bit
0
Disable compare match interrupt for compare register 0/2/4
1
Enable compare match interrupt for compare register 0/2/4
IOE1
Compare match interrupt enable bit
0
Disable compare match interrupt for compare register 1/3/5
1
Enable compare match interrupt for compare register 1/3/5
Compare match interrupt flag bit
IOP0
Read
Write
0
No compare match interrupt for
compare register 0/2/4
Clear this bit
1
Compare match interrupt for
compare register 0/2/4
No effect
Compare match interrupt flag bit
IOP1
R/W : Read and Write
Read
Write
0
No compare match interrupt for
compare register 1/3/5
Clear this bit
1
Compare match interrupt for
compare register 1/3/5
No effect
: Initial value
—
: Not used
303
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-4 Compare Control Register (OCS0/OCS2/OCS4)
Bit name
Function
IOP1:
Compare match
interrupt flag bit
• This bit is an interrupt flag for when compare register 1/3/5 is matched with the value of
16-bit free-run timer.
• “1” is set to this bit when the compare register value matches the 16-bit free-run timer
value.
• While the interrupt request bits (IOE1) is enabled, an output compare interrupt occurs
when the IOP1 bit is set.
• Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
bit6
IOP0:
Compare match
interrupt flag bit
• This bit is an interrupt flag for when compare register 0/2/4 is matched with the value of
16-bit free-run timer.
• “1” is set to this bit when the compare register value matches the 16-bit free-run timer
value.
• While the interrupt request bits (IOE0) is enabled, an output compare interrupt occurs
when the IOP0 bit is set.
• Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
bit5
IOE1:
Compare match
interrupt enable bit
• This bit is used to enable output compare interrupt for compare register 1/3/5.
• While the “1” is written to this bit, an output compare interrupt occurs when an interrupt
flag (IOP1) is set.
bit4
IOE0:
Compare match
interrupt enable bit
• This bit is used to enable output compare interrupt for compare register 0/2/4.
• While the “1” is written to this bit, an output compare interrupt occurs when an interrupt
flag (IOP0) is set.
bit3
BUF1:
Compare buffer
disable bit
• This bit is used to disable buffer function for output compare register 1/3/5.
• Writing “0” will enable the buffer function.
bit2
BUF0:
Compare buffer
disable bit
• This bit is used to disable buffer function for output compare register 0/2/4.
• Writing “0” will enable the buffer function.
CST1:
Compare operation
enable bit
• This bit is used to enable the compare operation between 16-bit free-run timer and
compare register 1/3/5.
• Ensure that a value is written into the compare register and timer data register before the
compare operation is enabled.
Note:
Since output compare is synchronized with the 16-bit free-run timer clock, stopping the
16-bit free-run timer stops compare operation.
CST0:
Compare operation
enable bit
• This bit is used to enable the compare operation between 16-bit free-run timer and
compare register 0/2/4.
• Ensure that a value is written into the compare register and timer data register before the
compare operation is enabled.
(Note)
Since output compare is synchronized with the 16-bit free-run timer clock, stopping the
16-bit free-run timer stops compare operation.
bit7
bit1
bit0
304
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.4.6
Input Capture Register (IPCP0 to IPCP3)
Input capture registers are used to hold the count value of 16-bit timer when a valid
edge of the input waveform is detected.
■ Input Capture Register (IPCP0 to IPCP3)
Figure 14.4-14 Input Capture Data Registers (IPCP0 to IPCP3)
Input Capture Data Register (Upper)
Address: ch.0 000061H
ch.1 000063H
ch.2 000065H
ch.3 000067H
Read/write
Initial value
bit
15
CP15
14
CP14
12
CP13
CP12
R
X
R
X
R
X
R
X
13
11
10
CP11 CP10
8
IPCP0 to
IPCP3
CP09
CP08
R
X
R
X
2
1
CP01
CP00
R
X
R
X
R
X
R
X
9
Input Capture Data Register (Lower)
Address: ch.0 000060H
ch.1 000062H
ch.2 000064H
ch.3 000066H
Read/write
Initial value
bit
7
6
5
4
CP07
CP06
CP05
CP04
CP03 CP02
R
X
R
X
R
X
R
X
3
R
X
R
X
0
IPCP0 to
IPCP3
This register is used to store the value of the 16-bit timer when a valid edge of the corresponding external
pin input waveform is detected. (Word access instruction to this register is recommended. No data can be
written to this register.)
305
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.4.7
Input Capture Control Status Registers (ICS23, PICS01)
Input capture control status registers (ICS23, PICS01) are used to control edge
selection, interrupt request enable, interrupt request flag and to indicate valid edge
detected for input capture 0 to 3.
■ Input Capture Control Status Register, Upper Byte (ICSH23)
Figure 14.4-15 Input Capture Control Status Register (ICSH23)
Address bit15
00006BH
R
: Read-only
-
: Not used
: Initial value
14
13
12
11
10
9
8
Initial value
IEI3
IEI2
------00B
R
R
IEI2
Valid edge indication bit (input capture 2)
0
Falling edge detected
1
Rising edge detected
IEI3
Valid edge indication bit (input capture 3)
0
Falling edge detected
1
Rising edge detected
Table 14.4-5 Input Capture Control Status Register (ICSH23)
Bit name
bit15
to
bit10
bit9
bit8
306
Function
Unused bit
• The read value is indeterminate.
• Writing to this bit has no effect on the operation.
IEI3:
Valid edge
indication bit
• This bit is an valid edge indication bit for capture register 3, to indicate a rising or falling edge
is detected.
• “0” is written to this bit when falling edge is detected.
• “1” is written to this bit when rising edge is detected.
• This bit is read-only.
(Note)
The read value is meaningless when EG31, EG30 = 00.
IEI2:
Valid edge
indication bit
• This bit is an valid edge indication bit for capture register 2, to indicate a rising or falling
edge is detected.
• “0” is written to this bit when falling edge is detected.
• “1” is written to this bit when rising edge is detected.
• This bit is read-only.
(Note)
The read value is meaningless when EG21, EG20 = 00.
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Input Capture Control Status Register, Lower Byte (ICSL23)
Figure 14.4-16 Input Capture Control Status Register (ICSL23)
Address bit7
6
5
4
3
2
1
0
Initial value
00006AH ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EG21
EG20
Edge selection bit (input capture 2)
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
EG31
EG30
Edge selection bit (input capture 3)
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
ICE2
Interrupt request enable bit (input capture 2)
0
Disable interrupt request
1
Enable interrupt request
ICE3
Interrupt request enable bit (input capture 3)
0
Disable interrupt request
1
Enable interrupt request
Interrupt request flag bit (input capture 2)
ICP2
Read
Write
0
No valid edge detected
Clear this bit
1
Valid edge detected
No effect
Interrupt request flag bit (input capture 3)
ICP3
R/W : Read and Write
Read
Write
0
No valid edge detected
Clear this bit
1
Valid edge detected
No effect
: Initial value
307
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-6 Input Capture Control Status Register (ICSL23)
Bit name
Function
ICP3:
Interrupt request
flag bit
(Input capture 3)
• This bit is used as interrupt request flag for input capture 3.
• “1” is set to this bit upon detection of a valid edge in an external input pin.
• While the interrupt enable bit (ICE3) is set, an interrupt can be generated upon detection
of a valid edge.
• Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
bit6
ICP2:
Interrupt request
flag
(Input capture 2)
• This bit is used as interrupt request flag for input capture 2.
• “1” is set to this bit upon detection of a valid edge in an external input pin.
• While the interrupt enable bit (ICE2) is set, an interrupt can be generated upon detection
of a valid edge.
• Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
bit5
ICE3:
Interrupt request
enable bit
(Input capture 3)
• This bit is used to enable input capture interrupt request for input capture 3.
• While “1” is written to this bit, an input capture interrupt is generated when the interrupt
flag (ICP3) is set.
bit4
ICE2:
Interrupt request
enable bit
(Input capture 2)
• This bit is used to enable input capture interrupt request for input capture 2.
• While “1” is written to this bit, an input capture interrupt is generated when the interrupt
flag (ICP2) is set.
bit3,
bit2
EG31, EG30:
Edge selection
bit
(Input capture 3)
• These bits are used to specify the valid edge polarity of an external input for input
capture 3.
• These bits are also used to enable input capture operation.
bit1,
bit0
EG21, EG20:
Edge selection
bit
(Input capture 2)
• These bits are used to specify the valid edge polarity of an external input for input
capture 2.
• These bits are also used to enable input capture operation.
bit7
308
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ PPG Output Control / Input Capture Control Status Register, Upper Byte (PICSH01)
Figure 14.4-17 PPG Output Control/Input Capture Control Status Register (PICSH01)
Address bit15
14
13
12
11
10
9
000069H PGEN5 PGEN4PGEN3 PGEN2 PGEN1 PGEN0 IEI1
R/W
R
R/W
: Read-only
R/W : Read and Write
R/W
R/W
R/W
R/W
R
8
Initial value
IEI0
00000000B
R
IEI0
Valid edge indication bit (input capture 0)
0
Falling edge detected
1
Rising edge detected
IEI1
Valid edge indication bit (input capture 1)
0
Falling edge detected
1
Rising edge detected
PGEN0
PPG output enable bit
0
Disable PPG0 output to RTO0
1
Enable PPG0 output to RTO0
PGEN1
PPG output enable bit
0
Disable PPG0 output to RTO1
1
Enable PPG0 output to RTO1
PGEN2
PPG output enable bit
0
Disable PPG0 output to RTO2
1
Enable PPG0 output to RTO2
PGEN3
PPG output enable bit
0
Disable PPG0 output to RTO3
1
Enable PPG0 output to RTO3
PGEN4
PPG output enable bit
0
Disable PPG0 output to RTO4
1
Enable PPG0 output to RTO4
PGEN5
PPG output enable bit
0
Disable PPG0 output to RTO5
1
Enable PPG0 output to RTO5
: Initial value
309
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-7 PPG output control/input capture control status register (PICSH01)
Bit name
bit15
to
bit10
bit9
bit8
310
Function
PGEN5 to
PGEN0:
PPG output
enable bits
• This bit is used to select PPG0 output to RTO0 to RTO5.
IEI1:
Valid edge
indication bit
• This bit is an valid edge indication bit for capture register 1, to indicate a rising or
falling edge is detected.
• “0” is written to this bit when falling edge is detected.
• “1” is written to this bit when rising edge is detected.
• This bit is read-only.
(Note)
The read value is meaningless when EG11, EG10 = 00B.
IEI0:
Valid edge
indication bit
• This bit is an value edge indication bit for capture register 0, to indicate a rising or
falling edge is detected.
• “0” is written to this bit when falling edge is detected.
• “1” is written to this bit when rising edge is detected.
• This bit is read-only.
(Note)
The read value is meaningless when EG01, EG00 = 00B.
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Input Capture Control Status Register, Lower Byte (PICSL01)
Figure 14.4-18 Input Capture Control Status Register (PICSL01)
Address bit7
6
5
4
3
2
1
0
Initial value
000068H ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EG01
EG00
Edge selection bit (input capture 0)
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
EG11
EG10
Edge selection bit (input capture 1)
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
ICE0
Interrupt request enable bit (input capture 0)
0
Disable interrupt request
1
Enable interrupt request
ICE1
Interrupt request enable bit (input capture 1)
0
Disable interrupt request
1
Enable interrupt request
Interrupt request flag bit (input capture 0)
ICP0
Read
Write
0
No valid detected
Clear this bit
1
Valid detected
No effect
Interrupt request flag bit (input capture 1)
ICP1
R/W : Read and Write
Read
Write
0
No valid edge detected
Clear this bit
1
Valid edge detected
No effect
: Initial value
311
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-8 Input Capture Control Status Register (PICSL01)
Bit name
Function
ICP1:
Interrupt request
flag bit
(Input capture 1)
• This bit is used as interrupt request flag for input capture 1.
• “1” is set to this bit upon detection of a valid edge of an external input pin.
• While the interrupt enable bit (ICE1) is set, an interrupt can be generated upon
detection of a valid edge.
• Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
bit6
ICP0:
Interrupt request
flag bit
(Input capture 0)
• This bit is used as interrupt request flag for input capture 0.
• “1” is set to this bit upon detection of a valid edge of an external input pin.
• While the interrupt enable bit (ICE0) is set, an interrupt can be generated upon
detection of a valid edge.
• Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
bit5
ICE1:
Interrupt request
enable bit
(Input capture 1)
• This bit is used to enable input capture interrupt request for input capture 1.
• While “1” is written to this bit, an input capture interrupt is generated when the
interrupt flag (ICP1) is set.
bit4
ICE0:
Interrupt request
enable bit
(Input capture 0)
• This bit is used to enable input capture interrupt request for input capture 0.
• While “1” is written to this bit, an input capture interrupt is generated when the
interrupt flag (ICP0) is set.
bit3,
bit2
EG11, EG10:
Edge selection
bit
(Input capture 1)
• These bits are used to specify the valid edge polarity of an external input for input
capture 1.
• These bits are also used to enable input capture operation.
bit1,
bit0
EG01, EG00:
Edge selection
bit
(Input capture 0)
• These bits are used to specify the valid edge polarity of an external input for input
capture 0.
• These bits are also used to enable input capture operation.
bit7
312
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.4.8
16-bit Timer Register (TMRR0/TMRR1/TMRR2)
16-bit timer registers hold the compare value of 16-bit timers.
■ 16-bit Timer Registers (TMRR0/TMRR1/TMRR2)
Figure 14.4-19 16-bit Timer Registers (TMRR0/TMRR1/TMRR2)
16-bit Timer Register (Upper)
bit
Address: ch.0 000051H
ch.1 000053H
ch.2 000055H
Read/write
Initial value
TR15
15
13
12
11
10
9
8
TR13
TR12
TR11
TR10
TR09
TR08
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
2
1
TR07
TR06
TR05
TR03
TR02
TR01
TR00
R/W
X
R/W
X
R/W
X
TR14
14
R/W
X
TMRR0/TMRR1/
TMRR2
16-bit Timer Register (Lower)
bit
Address: ch.0 000050H
ch.1 000052H
ch.2 000054H
Read/write
Initial value
R/W
X
TR04
R/W
X
R/W
X
R/W
X
R/W
X
0
TMRR0/TMRR1/
TMRR2
R/W
X
These registers are used to store the comparison value of 16-bit timers. The value in these registers will be
reloaded when the 16-bit timer is started to operate. Therefore, if the value is re-written into these registers
during timer operation, these value will be valid at the next timer initiation/operation.
In dead-time timer mode, these registers are used to set the non-overlap time.
• Non-overlap time = (set value + 1) × selected clock.
Notes:
• The value of "0000H" cannot be set.
• The maximum offset of non-overlap time is -1 selected clock.
In timer mode, these registers are used to set the GATE time for PPG timer 0 operation.
• GATE time = (set value + 1) × selected clock.
Notes:
• The value of "0000H" cannot be set and maximum offset is -1 selected clock.
• The maximum offset of GATE time is -1 selected clock.
313
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.4.9
16-bit Timer Control Register (DTCR0/DTCR1/DTCR2)
16-bit timer control registers (DTCR0/DTCR1/DTCR2) are used to control the operation
mode, interrupt request enable, interrupt request flag, GATE signal enable and output
level polarity for the waveform generator.
■ 16-bit Timer Control Register (DTCR0/DTCR2)
Figure 14.4-20 16-bit Timer Control Register (DTCR1)
Address
bit 7
6
5
4
3
2
1
0
Initial value
ch.0: 000056H DMOD GTEN1 GTEN0 TMIF TMIE TMD2 TMD1 TMD0 00000000B
ch.2: 000058H R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TMD2 TMD1 TMD0
Operation mode bit
0
0
0
Waveform generator is stopped.
0
0
1
PPG timer 0 output pulse while RT signal is “H”.
0
1
0
The rising edge of each RT signal will trigger
16-bit timer to start. PPG timer 0 output pulse
until the 16-bit timer stopped. (Timer mode)
1
0
0
Generate non-overlap signal by RT signal.
(Dead-time timer mode)
1
1
1
Generate non-overlap signal by PPG timer 0.
(Dead-time timer mode)
Others
Prohibited
TMIE
Interrupt request enable bit
0
Disable an interrupt when the 16-bit timer underflow
1
Enable an interrupt when the 16-bit timer underflow
Interrupt request flag bit
TMIF
R/W : Read and Write
: Initial value
314
Read
Write
0
No counter underflow detected
Clear this bit
1
Counter underflow detected
No effect
GTEN0
GATE signal control bit 0
0
GATE signal is not controlled by RT0/RT4 (asynchronous mode)
1
GATE signal is controlled by RT0/RT4 (synchronous mode)
GTEN1
GATE signal control bit 1
0
GATE signal is not controlled by RT1/RT5 (asynchronous mode)
1
GATE signal is controlled by RT1/RT5 (synchronous mode)
DMOD
Output polarity control bit
0
Normal polarity output
1
Inverted polarity output
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-9 16-bit Timer Control Registers (DTCR0/DTCR2) bit
Bit name
Function
bit7
DMOD:
Output polarity
control bit
• This bit is used to set the output polarity of U/V/W in dead-time timer mode.
• By setting this bit, the output polarity of U/V/W is inverted.
(Note)
This bit is meaningless when dead-time timer mode is not selected (bit2: TMD2 = 0).
bit6
GTEN1:
GATE signal
control bit 1
• This bit is used to control the GATE signal output for PPG timer 0 by RT1/RT5.
bit5
GTEN0:
GATE signal
control bit 0
• This bit is used to control the GATE signal output of PPG timer 0 by RT0/RT4.
TMIF:
Interrupt request
flag bit
• This bit is used as an interrupt request flag for 16-bit timers.
• This bit will be set to "1" when 16-bit timer 0/2 is underflow.
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
(Notes)
• This bit functions only in mode TMD2 to TMD0=000B or 001B. In other modes, this
bit is always "0".
• If both software clear (writing "0") and hardware set (16-bit timer 0/2 underflow)
occurs simultaneously, software clear takes the higher priority to clear this bit.
TMIE:
Interrupt request
enable / software
trigger bit
• This bit is used as the software trigger bit and interrupt enable bit for the 16-bit timer 0/
2.
• When TMD22 to TMD0=000B or 001B, this bit is used as software trigger for 16-bit
timer. Setting this bit from “0” to “1” trigger the 16-bit timer to reload and starts downcounting.
• When this bit is “1” and the interrupt flag bit (bit4: TIMF) is “1”, an interrupt request is
sent to CPU.
(Note)
To retrigger the 16-bit timer, be sure to write “0” before write “1” to this bit.
TMD2 to TMD0:
Operation mode
bits
• These bits are used to select the operation mode of the waveform generator.
• When TMD2 to TMD0=000B, output compare RT0/RT4 and RT1/RT5 outputs to
RTO0/RTO4 and RTO1/RTO5 respectively. And 16-bit timer can be used as reload
timer.
• When TMD2 to TMD0=001B, output compare RT0/RT4 and RT1/RT5 outputs to
RTO0/RTO4 and RTO1/RTO5 respectively if PPG0 output is disabled
(PICSH01:PGEN0/PGEN4=0, PGEN1/PGEN5=0). And 16-bit timer can be used as
reload timer.
(Notes)
• To operate the waveform generator in dead-time timer mode, be sure to select 2channel mode for RT1/RT5 (OCS1/OCS5:CMOD=1)
• When TMD2 to TMD0=111B is selected, RTO0/RTO4 and RTO1/RTO5 output are
independent of setting in PICSH01:PGEN0/PGEN4,PGEN1/PGEN5.
bit4
bit3
bit2
to
bit0
315
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ 16-bit Timer Control Register (DTCR1)
Figure 14.4-21 16-bit Timer Control Register (DTCR1)
Address
ch.1: 000057H
bit 15
14
13
12
11
10
9
8
Initial value
DMOD GTEN1 GTEN0 TMIF TMIE TMD2 TMD1 TMD0 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TMD2 TMD1 TMD0
Operation mode bit
0
0
0
Waveform generator is stopped.
0
0
1
PPG timer 0 output pulse while RT signal is “H”.
0
1
0
The rising edge of each RT signal will trigger
16-bit timer to start. PPG timer 0 output pulse
until the 16-bit timer stopped. (Timer mode)
1
0
0
Generate non-overlap signal by RT signal.
(Dead-time timer mode)
1
1
1
Generate non-overlap signal by PPG timer 0.
(Dead-time timer mode)
Others
Prohibited
TMIE
Interrupt request enable bit
0
Disable an interrupt when the 16-bit timer underflow
1
Enable an interrupt when the 16-bit timer underflow
Interrupt request flag bit
TMIF
R/W : Read and Write
: Initial value
316
Read
Write
0
No counter underflow detected
Clear this bit
1
Counter underflow detected
No effect
GTEN0
GATE signal control bit 0
0
GATE signal is not controlled by RT2 (asynchronous mode)
1
GATE signal is controlled by RT2 (synchronous mode)
GTEN1
GATE signal control bit 1
0
GATE signal is not controlled by RT3 (asynchronous mode)
1
GATE signal is controlled by RT3 (synchronous mode)
DMOD
Output polarity control bit
0
Normal polarity output
1
Inverted polarity output
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-10 16-bit Timer Control Registers (DTCR1) bit
Bit name
Function
bit15
DMOD:
Output polarity
control bit
• This bit is used to set the output polarity of U/V/W in dead-time timer mode.
• By setting this bit, the output polarity of U/V/W is inverted.
(Note)
This bit is meaningless when dead-time timer mode is not selected (bit10: TMD2 = 0).
bit14
GTEN1:
GATE signal
control bit 1
• This bit is used to control the GATE signal output for PPG timer 0 by RT3.
bit13
GTEN0:
GATE signal
control bit 0
• This bit is used to control the GATE signal output of PPG timer 0 by RT2.
TMIF:
Interrupt
request
flag bit
• This bit is used as an interrupt request flag for 16-bit timers.
• This bit will be set to "1" when 16-bit timer 1 is underflow.
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
(Notes)
• This bit functions only in mode TMD2 to TMD0=000B or 001B. In other modes, this
bit is always "0".
• If both software clear (writing "0") and hardware set (16-bit timer 1 underflow) occurs
simultaneously, software clear takes the higher priority to clear this bit.
TMIE:
Interrupt
request
enable bit
• This bit is used as the software trigger bit and interrupt enable bit for the 16-bit timer.
• When TMD2 to TMD0=000B or 001B, this bit is used as software trigger for 16-bit timer.
Setting this bit from “0” to “1” trigger the 16-bit timer to reload and starts down-counting.
• When this bit is “1” and the interrupt flag bit (bit12: TIMF) is “1”, an interrupt request is
sent to CPU.
(Note)
To retrigger the 16-bit timer, be sure to write “0” before write “1” to this bit.
TMD2 to
TMD0:
Operation mode
bit
• These bits are used to select the operation mode of the waveform generator.
• When TMD2 to TMD0=000B, output compare RT2 and RT3 outputs to RTO2 and RTO3
respectively. And 16-bit timer can be used as reload timer.
• When TMD2 to TMD0=001B, output compare RT2 and RT3 outputs to RTO2 and RTO3
respectively if PPG0 output is disabled (PICSH01:PGEN2=0, PGEN3=0). And 16-bit
timer can be used as reload timer.
(Notes)
• To operate the waveform generator in dead-time timer mode, be sure to select 2channel mode for RT3 (OCS3:CMOD=1)
• When TMD2 to TMD0=111B is selected, RTO2 and RTO3 output are independent of
setting in PICSH01:PGEN2,PGEN3.
bit12
bit11
bit10
to
bit8
317
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.4.10
Waveform Control Register (SIGCR)
Waveform control register is used to control how the operating clock frequencies, noise
cancellation function enable, DTTI0 input enable and DTTI0 interrupt.
■ Waveform Control Register (SIGCR)
Figure 14.4-22 Waveform Control Register (SIGCR)
Address bit15
14
13
12
11
10
9
8
Initial value
000059H DTIE DTIF NRSL DCK2 DCK1 DCK0 NWS1 NWS0 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NWS1
NWS0
DTTI0 Noise width selection bits
0
0
Cancel 4-cycle noise.
0
1
Cancel 8-cycle noise.
1
0
Cancel 16-cycle noise.
1
1
Cancel 32-cycle noise.
DCK2 DCK1 DCK0
Operating clock selection bit
0
0
0
φ (62.5 ns, φ = 16 MHz)
0
0
1
φ/2 (125 ns, φ = 16 MHz)
0
1
0
φ/4 (250 ns, φ = 16 MHz)
0
1
1
φ/8 (500 ns, φ = 16 MHz)
1
0
0
φ/16 (1 µs, φ = 16 MHz)
1
0
1
φ/32 (2 µs, φ = 16 MHz)
1
1
0
φ/64 (4 µs, φ = 16 MHz)
1
1
1
Prohibited
φ: Machine clock
NRSL
Noise cancellation function enable bit
0
DTTI0 input does not go thru the noise cancellation circuit.
1
DTTI0 input goes thru the noise cancellation circuit.
DTTI0 interrupt flag bit
DTIF
R/W : Read and Write
: Initial value
318
Read
Write
0
No interrupt request
Clear this bit
1
Has interrupt request
No effect
DTIE
DTTI0 input enable bit
0
Disable DTTI0 input
1
Enable DTTI0 input
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-11 Waveform Control Register (SIGCR)
Bit name
Function
DTIE:
DTTI0 input
enable bit
• This bit is used to enable the DTTI0 pin to control the output level of RTO0 to RTO5
pin.
DTIF:
DTTI0 interrupt
flag bit
• This bit is an interrupt flag for DTTI0.
• When DTTI0 input is enabled (DTIE=1) and low level of DTTI0 is detected, this bit
will be set and interrupt request will send to CPU.
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
(Notes)
• If noise cancellation function is enabled (NRSL=1), this bit will be set to "1" when
noise pulse width is passed.
• If both software clear (writing "0") and hardware set (low level of DTTI0 is detected)
occurs simultaneously, software clear takes the higher priority to clear this bit.
bit13
NRSL:
Noise
cancellation
function
enable bit
• This bit is used to enable the noise cancellation function.
• Noise cancellation circuit will receive DTTI0 input signal when the low level is held
until the counter overflows. The counter is n-bit counter which is operated by the low
level input. The value of n can be 2, 3, 4 and 5 which depends on the setting of NWS1
and NWS0.
(Notes)
• To cancel the noise pulse width, it takes approximately 2n machine cycles.
• When the noise cancellation circuit is selected, the input will become invalid in a
mode such as STOP mode in which the internal clock is stopped.
bit12
to
bit10
DCK2 to DCK0:
Operating clock
selection bit
• These bits are used to select the operating clock for the 16-bit timer.
bit9,
bit8
NWS1, NWS0:
DTTI0 Noise
width selection
bits
• These bits are used to select the noise pulse width to be removed for DTTI0 pin.
bit15
bit14
319
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.5
Multi-functional Timer Interrupts
The multi-functional timer is enabled to generate interrupts in 16-bit free-run timer, 16bit output compare, 16-bit input capture and waveform generator.
■ 16-bit Free-run Timer Interrupts
Table 14.5-1 lists the interrupt control bits and interrupt causes of the 16-bit free-run timer.
Table 14.5-1 Interrupt Control Bits and Interrupt Causes of the 16-bit Free-run Timer
16-bit free-run timer
Compare Clear
Zero Detect
Interrupt request flag bit
TCCSH:ICLR
TCCSH:IRQZF
Interrupt request enable bit
TCCSH:ICRE
TCCSH:IRQZE
Interrupt cause
16-bit free-run timer value matches with
compare clear
register (CPCLR)
16-bit free-run timer value equals zero
In the 16-bit free-run timer, the ICLR bit of the timer control status register (TCCSH) is set to "1" when
timer value matches compare clear register (CPCLR). If an interrupt request is enabled (TCCSH:ICRE =
1) in this operation, the interrupt request is output to the interrupt controller.
The IRQZF bit of the timer control status register (TCCSH) is set to "1" when timer value equals "0000H".
If an interrupt request is enabled (TCCSH:IRQZE = 1) in this operation, the interrupt request is output to
the interrupt controller.
■ 16-bit Free-run Timer Interrupts and EI2OS
Table 14.5-2 lists the 16-bit free-run timer interrupts and EI2OS.
Table 14.5-2 16-bit Free-run Timer Interrupts and EI2OS
Channel
Interrupt
number
Interrupt control register
Vector table address
EI2OS
Register name
Address
Lower
Middle
Upper
Compare clear *1
#34 (22H)
ICR11
0000BBH
FFFF74H
FFFF75H
FFFF76H
Zero detect *2
#31 (1FH)
ICR10
0000BAH
FFFF80H
FFFF81H
FFFF82H
∆
*1: The same interrupt control register as that for 16-bit free-run timer compare clear is assigned to 16-bit input capture
channels 0/1.
*2: The same interrupt control register as that for 16-bit free-run timer zero detect is assigned to 16-bit PPG timer 2.
320
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ 16-bit Output Compare Interrupts
Table 14.5-3 lists the interrupt control bits and interrupt causes of the 16-bit output compare.
Table 14.5-3 Interrupt Control Bits and Interrupt Causes of the 16-bit Output Compare 0 to 5
16-bit output compare 0/1
16-bit output compare 2/3
16-bit output compare 4/5
Interrupt request flag bit
OCS0:IOP0/IOP1
OCS2:IOP0/IOP1
OCS4:IOP0/IOP1
Interrupt request enable bit
OCS0:IOE0/IOE1
OCS2:IOE0/IOE1
OCS4:IOE0/IOE1
Interrupt cause
16-bit free-run timer value
16-bit free-run timer value
16-bit free-run timer value
matches with output compare matches with output compare matches with output compare
register (OCCP0/OCCP1)
register (OCCP2/OCCP3)
register (OCCP4/OCCP5)
In the 16-bit output compare, the IOP0/IOP1 bit of the compare control register (OCS0/OCS2/OCS4) is set
to "1" when 16-bit free-run timer value matches output compare register (OCCP0 to OCCP5). If an
interrupt request is enabled (OCS0/OCS2/OCS4:IOE0/IOE1 = 1) in this operation, the interrupt request is
output to the interrupt controller.
■ 16-bit Output Compare Interrupts and EI2OS
Table 14.5-4 lists the 16-bit output compare interrupts and EI2OS
Table 14.5-4 16-bit Output Compare Interrupts and EI2OS
Channel
Interrupt
number
Interrupt control register
Vector table address
EI2OS
Register name
Address
Lower
Middle
Upper
Output compare 0 match *1
#12 (0CH)
ICR00
0000B0H
FFFFCCH FFFFCDH FFFFCEH
Output compare 1 match *2
#15 (0FH)
ICR02
0000B2H
FFFFC0H
FFFFC1H
FFFFC2H
Output compare 2 match *3
#17 (11H)
ICR03
0000B3H
FFFFB8H
FFFFB9H
FFFFBAH
Output compare 3 match *4
#19 (13H)
ICR04
0000B4H
FFFFB0H
FFFFB1H
FFFFB2H
Output compare 4 match *5
#21 (15H)
ICR05
0000B5H
FFFFA8H
FFFFA9H
FFFFAAH
Output compare 5 match *6
#23 (17H)
ICR06
0000B6H
FFFFA0H
FFFFA1H
FFFFA2H
O
*1:
*2:
*3:
*4:
The same interrupt control register as that for 16-bit output compare 0 is assigned to A/D conversion termination.
The same interrupt control register as that for 16-bit output compare 1 is assigned to 16-bit PPG timer 1.
The same interrupt control register as that for 16-bit output compare 2 is assigned to 16-bit reload timer 1 underflow.
The same interrupt control register as that for 16-bit output compare 3 is assigned to DTP/external interrupt channels 0/1 detection
DTTI0.
*5: The same interrupt control register as that for 16-bit output compare 4 is assigned to DTP/external interrupt channels 2/3 detection /
DTTI1.
*6: The same interrupt control register as that for 16-bit output compare 5 is assigned to PWC timer 1.
321
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ 16-bit Input Capture Interrupts
Table 14.5-5 lists the interrupt control bits and interrupt causes of the 16-bit input capture.
Table 14.5-5 Interrupt Control Bits and Interrupt Causes of the 16-bit Input Capture 0 to 3
16-bit input capture 0/1
16-bit input capture 2/3
Interrupt request flag bit
PICSL01:ICP0/ICP1
ICSL23:ICP2/ICP3
Interrupt request enable bit
PICSL01:ICE0/ICE1
ICSL23:ICE2/ICE3
Interrupt cause
Valid edge is detected in IN0/IN1
Valid edge is detected in IN2/IN3
In the 16-bit input capture, the ICP0 to ICP3 bit of the input capture control register (PICSL01/ICSL23) is
set to "1" when valid edge is detected in IN0 to IN3. If an interrupt request is enabled (PICSL01/
ICSL23:ICE0/ICE1 = 1) in this operation, the interrupt request is output to the interrupt controller.
■ 16-bit Input Capture Interrupts and EI2OS
Table 14.5-6 lists the 16-bit input capture interrupts and EI2OS.
Table 14.5-6 16-bit Input Capture Interrupts and EI2OS
Interrupt control register
Interrupt
number
Channel
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
Input capture 0/1 *1
#33 (21H)
ICR11
0000BBH
FFFF78H
FFFF79H
FFFF7AH
*2
#35 (23H)
ICR12
0000BCH
FFFF70H
FFFF71H
FFFF72H
O
Input capture 2/3
*1: The same interrupt control register as that for 16-bit input capture 0/1 is assigned to 16-bit free-run timer compare clear.
*2: The same interrupt control register as that for 16-bit input capture 2/3 is assigned to Time-base timer.
■ Waveform Generator Interrupts
lists the interrupt control bits and interrupt causes of the waveform generator.
Table 14.5-7 Interrupt Control Bits and Interrupt Causes of the Waveform Generator
Waveform generator
16-bit timer 0/1/2
DTTI0
Interrupt request flag bit
DTCR0/DTCR1/DTCR2:TMIF
SIGCR:DTIF
Interrupt request enable bit
DTCR0/DTCR1/DTCR2:TMIE
--
Interrupt cause
16-bit timer 0/1/2 underflow
Low level is detected in DTTI0
In the waveform generator, the TMIF bit of the 16-bit timer control register (DTCR0/DTCR1/DTCR2) is
set to "1" when 16-bit timer underflow and DTCR0/DTCR1/DTCR2:TMD2 to TMD0=000B or 001B. If an
interrupt request is enabled (DTCR0/DTCR1/DTCR2:TMIE = 1) in this operation, the interrupt request is
output to the interrupt controller.
322
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Waveform Generator Interrupts and EI2OS
Table 14.5-8 lists the waveform generator interrupts and EI2OS.
Table 14.5-8 Waveform Generator Interrupts and EI2OS
Interrupt control register
Channel
Interrupt number
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
16-bit timer 0/1/2
underflow *1
#29 (1DH)
ICR09
0000B9H
FFFF88H
FFFF89H
FFFF8AH
DTTI0 *2
#20 (14H)
ICR04
0000B4H
FFFFACH
FFFFADH
FFFFAEH
∆
*1: The same interrupt control register as that for 16-bit timer 0/1/2 underflow is assigned to 16-bit reload timer 0 underflow.
*2: The same interrupt control register as that for DTTI0 is assigned to DTP/external interrupt channels 0/1 detection and 16-bit output
compare 3.
■ EI2OS Function of the Multi-functional Timer
Since the multi-functional timer has a circuit that coordinates with EI2OS, the interrupt generated can start
EI2OS.
However, EI2OS is available only when other peripheral functions sharing the interrupt control register
(ICR) do not use interrupts. For example, when 16-bit free-run timer compare clear uses EI2OS, interrupts
of 16-bit input capture channels 0/1 must be disabled.
323
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.6
Operation of Multi-functional Timer
This section describes the operation of the multi-functional timer.
■ Operation of Multi-functional Timer
● 16-bit free-run timer
The 16-bit free-run timer starts counting up from value set in timer data register (TCDT) after a reset has
been completed. The counter value is used as the reference time for 16-bit output compare and 16-bit input
capture.
● 16-bit output compare
The 16-bit output compare is used to compare the value set in the specified output compare register with
the value of the 16-bit free-run timer. If a match is detected, the interrupt flag is set and the output level is
inverted.
● 16-bit input capture
The 16-bit input capture is used to detect a specified valid edge. If a valid edge is detected, the interrupt
flag is set and the value of 16-bit free-run timer is fetched and stored into the input capture data register.
● Waveform generator
Waveform generator can produce various waveform such as dead-time, by using the real-time outputs (RT0
to RT5), 16-bit PPG timer 0 and 16-bit timers.
324
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.6.1
Operation of 16-bit free-run timer
The 16-bit free-run timer starts counting up from counter value specified in timer data
register (TCDT) after a reset has been completed. The counter value is used as the
reference time for 16-bit output compare and 16-bit input capture.
■ Timer Clear
The counter value of 16-bit free-run timer is cleared in the following conditions:
• When a match with compare clear register is detected in up-count mode (TCCSL:MODE=0)
• When "1" is written to the SCLR bit of the TCCSL register during operation. The timer will be cleared
at the valid edge of count clock.
Note:
If writing "0" to the SCLR bit before a valid edge of count clock, the SCLR bit is cleared and the timer
would not be cleared to "0000H".
• When "0000H" is written to the TCDT register during stop.
• Reset
By a reset, the counter is immediately cleared. By a software clear or a match with compare clear register,
the counter is cleared in synchronization with the count timing. If the
Figure 14.6-1 16-bit Free-run Timer Clear Timing
φ
Compare
register value
N
Compare match
cleared by hardward
writing “1”
writing “1”
writing “0”
TCCS : SCLR
Counter value
N -1
N
0000
0001
0000
0001
0002
325
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Timer Mode
Two count modes can be selected in 16-bit free-run timer
• up-count mode (TCCSL:MODE=0)
• up-down count mode (TCCSL:MODE=1)
In up-count mode, counter starts counting from pre-set timer data register (TCDT), counts up until counter
value matches value of compare clear register (CPCLR), then counter is cleared to "0000H" and then counts
up again.
In up-down count mode, counter starts counting from pre-set timer data register (TCDT), counts up until
counter value matches value of compare clear register (CPCLR), then counter changes from up-count to
down-count, counts down until counter value reaches "0000H" and then counts up again.
There is a buffer in mode bit, TCCSL:MODE, it can be written at any time no matter the timer is operating
or stopped. While the timer is operating, value written to this bit is buffered and the count mode will be
changed when timer value is "0000H".
Figure 14.6-2 Change Timer Mode while Timer is Operating
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Compare clear
buffer register
TCCSL:MODE
326
Timer starts
Change to up-down mode
Change to up mode
BFFFH
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Compare Clear Buffer
There is a selected buffer function on compare clear register (CPCLR). In buffer enable (TCCSL:BFE=1),
data written in compare clear buffer register (CPCLRB) will transfer to CPCLR at zero detection of the 16bit free-run timer. In buffer disable (TCCSL:BFE=0), CPCLRB is transparent, data can directly be written
into CPCLR.
Figure 14.6-3 Operation in Up-count Mode with Compare Clear Buffer is disabled (TCCSL:BFE=0)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Timer starts
Zero detect
Zero detect
Reset
Compare clear
buffer register
value
Compare clear
register value
BFFFH
FFFFH
7FFFH
BFFFH
FFFFH
7FFFH
Figure 14.6-4 Operation in Up-count Mode with Compare Clear Buffer is enabled (TCCSL:BFE=1)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Timer starts
Reset
Compare clear
buffer register
value
Compare clear
register value
Zero detect
Zero detect
BFFFH
BFFFH
FFFFH
7FFFH
7FFFH
FFFFH
327
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Figure 14.6-5 Operation in Up-down Count Mode with Compare Clear Buffer enabled (TCCSL:BFE=1)
Counter value
FFFFH
Compare clear match
BFFFH
7FFFH
3FFFH
Time
0000H
Timer starts
Reset
Compare clear
buffer register
value
Compare clear
register value
328
Zero detect
BFFFH
BFFFH
7FFFH
FFFFH
7FFFH
FFFFH
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Timer Interrupts
Two interrupts can be generated from 16-bit free-run timer:
• Compare clear interrupt
• Zero detect interrupt
Compare clear interrupt is generated when the timer value matches compare clear register (CPCLR). Zero
detect interrupt is generated when the timer value reaches "0000H".
Note:
Software clear (TCCSL:SCLR=1) will not generate zero detect interrupt.
Figure 14.6-6 Interrupts Generated in Up-count Mode (TCCSL:MODE=0)
Counter value
N-1
N
0
1
Compare clear interrupt
Zero detect interrupt
Figure 14.6-7 Interrupts Generated in Up-down Count Mode (TCCSL:MODE=1)
Counter value
N-1
N
N-1
0
Compare clear interrupt
Zero detect interrupt
329
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Interrupt Mask Function
The number of times of Interrupt source can be masked by setting TCCSH:MSI2 to MSI0. MSI2 to MSI0
configure a 3-bit reload down counter, which reloads when its count value reaches "000B". Count value can
also be loaded by writing directly to MSI2 to MSI0. The mask count equals the value set in MSI2 to MSI0
and there is no interrupt source will be masked when MSI2 to MSI0 equals "000B"
The interrupt source depends on the count mode (TCCSL:MODE). In up-count mode, only compare clear
interrupt can be masked, zero detect interrupt is generated in every zero detection. In up-down count mode,
only zero detect interrupt can be masked, compare clear interrupt is generated in every compare clear.
Note:
Software clear (TCCSL:SCLR=1) will not generate zero detection.
Figure 14.6-8 Compare Clear Interrupt masked in Up-count Mode
Counter value
2nd
1st
FFFFH
Compare clear match
3rd
4th
5th
6th
BFFFH
7FFFH
3FFFH
Time
0000H
Timer starts
Reset
Zero detect interrupt
Compare
clear
interrupt
TCCSH:MSI2:0=000B
Software
clear
TCCSH:MSI2:0=001B
TCCSH:MSI2:0=010B
* Both zero detect interrupt and compare clear interrupt are software cleared
330
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Figure 14.6-9 Zero Detect Interrupt masked in Up-down Count Mode
Counter value
2nd
1st
FFFFH
Compare clear match
3rd
4th
6th
5th
BFFFH
7FFFH
3FFFH
Time
0000H
Timer starts
1st
Reset
2nd
Zero detect
3rd
4th
5th
6th
Compare clear interrupt
TCCSH:MSI2:0=000B
Zero
detect
interrupt
Software
clear
TCCSH:MSI2:0=001B
TCCSH:MSI2:0=010B
* Both zero detect interrupt and compare clear interrupt are software cleared
■ External Count Clock Selected
The 16-bit free-run timer is incremented based on the input clock (internal or external clock). When
external clock is selected, the 16-bit free-run timer counts up at a rising edge when the initial value of
external input is "1" or at a falling edge when initial value of external clock input is "0" after external clock
mode is selected (TCCSH:ECKE=1).
Figure 14.6-10 16-bit Free-run Timer Count Timing
φ
External clock
input
TCCSH:ECKE
Count clock
Counter value
N
N+1
331
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.6.2
Operation of 16-bit Output Compare
The output compare unit is used to compare the value set in the specified compare
register with the value of the 16-bit free-run timer. If a match is detected, the interrupt
flag is set and the output level is inverted.
■ 16-bit Output Compare Operation
● Compare operation can be performed for individual channel (OCS1/OCS3/OCS5:CMOD = 0)
Figure 14.6-11 Sample Output Waveform when Compare Registers 0 and 1 are used individually when the
Initial Output Value is "0" (Free-run Timer in Up-count Mode)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
Compare 0
interrupt
Compare 1
interrupt
332
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Figure 14.6-12 Sample Output Waveform when Compare Registers 0 and 1 are used individually when the
Initial Output Value is "0" (Free-run Timer in Up-down Count Mode)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
Compare 0
interrupt
Compare 1
interrupt
● Output level can be changed by using a pair of compare registers (OCS1/OCS3/OCS5:CMOD = 1)
Figure 14.6-13 Sample Output Waveform when Compare Registers 0 and 1 are used in a Pair when the
Initial Output Value is "0" (Free-run Timer in Up-count Mode)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Compare register 0
value
Compare register 1
value
RT0
RT1
BFFFH
7FFFH
associated with compare 0
associated with compare 0 & 1
Compare 0
interrupt
Compare 1
interrupt
333
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Figure 14.6-14 Sample Output Waveform when Compare Register 0 and 1 are used in a Pair when the
Initial Output Value is "0" (Free-run Timer in Up-down Count Mode)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
associated with compare 0
associated with compare 0 &1
RT1
Compare 0
interrupt
Compare 1
interrupt
● Output level when compare buffer is disabled
Figure 14.6-15 Sample Output Waveform when Compare Buffer is disabled
(Free-run Timer in Up-count Mode)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Timer starts
Reset
Compare buffer
register 0 value
BFFFH
3FFFH
BFFFH
Compare
register 0 value
BFFFH
3FFFH
BFFFH
RT0
Interrupt
334
Compare clear match
Compare clear match
CHAPTER 14 MULTI-FUNCTIONAL TIMER
● Output level when compare buffer is selected at compare clear match
Figure 14.6-16 Sample Output Waveform when Compare Buffer is enable
(Free-run Timer in Up-down Count Mode)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Zero detection
Timer starts
Reset
Compare buffer
register 0 value
Compare
register 0 value
Compare clear match
BFFFH
BFFFH
BFFFH
3FFFH
3FFFH
3FFFH
BFFFH
RT0
Interrupt
335
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ 16-bit Output Compare Timing
When the free-run timer matches the value set in the compare register, the output compare unit generates a
compare match signal to invert the output and generate an interrupt. When a compare match occurs, the
output is inverted in synchronization with the count timing of the counter.
Note:
When the compare register is updated, comparison with the counter value is not performed.
Figure 14.6-17 Compare Operation upon Update of Compare Registers
Counter value
N
N+1
N+2
N+3
No match signal is generated.
Compare
register 0 value
Compare
register 0 write
Compare
register 1 value
Compare
register 1 write
M
N+1
N+3
L
Compare 0 stop
Compare 1 stop
Figure 14.6-18 Compare Interrupt Timing
φ
Counter value
N
N+1
Compare
register
value
N
Compare
match
Interrupt
Figure 14.6-19 Output Pin Change Timing
Counter value
Compare
register
value
Compare
match
signal
Pin output
336
N
N+1
N
N
N+1
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.6.3
Operation of 16-bit Input Capture
The input capture unit is used to detect a specified valid edge. If a valid edge is
detected, the interrupt flag is set and the value of 16-bit free-run timer is loaded into the
capture register.
■ 16-bit Input Capture Operation
Figure 14.6-20 Sample Input Capture Timing
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
IN0
IN1
IN example
Capture register 0
Undefined
Capture register 1
Capture register
example
Capture 0 interrupt
Undefined
Undefined
3FFFH
7FFFH
BFFFH
3FFFH
Capture 1 interrupt
Capture example
interrupt
Interrupt is generated
with another valid edge
(Note) Capture 0: Rising edge
Capture 1: Falling edge
Capture example: Both edges
Interrupt is cleared
by software
337
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ 16-bit Input Capture Input Timing
Figure 14.6-21 16-bit Input Capture Timing for Input Signals
φ
Machine clock
Counter value
Input capture
input
N
N+1
Valid edge
Capture signal
Capture register
Interrupt
338
N+1
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.6.4
Operation of Waveform Generator
Waveform generator can produce various waveform such as dead-time, by using the
real-time outputs (RT0 to RT5), 16-bit PPG timer 0 and 16-bit timers 0/1/2.
■ Output Condition of RTO0 to RTO5 and GATE
Table 14.6-1 Output Condition of RTO0 to RTO5, GATE and Register Bit Setting
TMD2 TMD1 TMD0 GTENx PGENx
RTOx
GATE
0
0
0
X
X
Real-time output, RTx
Always “0”
0
0
1
X
0
Real-time output, RTx
OR(RTx & GTENx)
0
0
1
0
1
PPG0 output pulse when RTx is high
Always “0”
0
0
1
1
1
Gate triggered PPG0 output pulse when RTx is high
OR(RTx)
Output “H” from rising edge of RTx to 16-bit timer 0
underflow (x=0,1)
0
1
0
X
0
Output “H” from rising edge of RTx to 16-bit timer 1
OR(RTOx & GTENx)
underflow (x=2,3)
Output “H” from rising edge of RTx to 16-bit timer 2
underflow (x=4,5)
PPG0 output pulse from rising edge of RTx to 16-bit
timer 0 underflow (x=0,1)
0
1
0
0
1
PPG0 output pulse from rising edge of RTx to 16-bit
timer 1 underflow (x=2,3)
Always “0”
PPG0 output pulse from rising edge of RTx to 16-bit
timer 2 underflow (x=4,5)
0
1
0
1
1
Gate triggered PPG0 output pulse from rising edge of OR(output “H” from
RTx to 16-bit timer 0 underflow (x=0,1)
RTx/y/z rising edge to
Gate triggered PPG0 output pulse from rising edge of timer 0/1/2 underflow)
RTx to 16-bit timer 1 underflow (x=2,3)
x=0,1
Gate triggered PPG0 output pulse from rising edge of y=2,3
z=4,5
RTx to 16-bit timer 2 underflow (x=4,5)
Generate non-overlap signal by RT1 (x=0,1) *1
1
0
0
X
X
Generate non-overlap signal by RT3 (x=2,3) *1
Always “0”
Generate non-overlap signal by RT5 (x=4,5) *1
1
1
1
0
X
Generate non-overlap signal by PPG0
Always “0”
1
1
1
1
X
Generate non-overlap signal by gate triggered PPG0
OR(RTx)
Always “0”
Always “0”
Others
*1 In order to generate non-overlap signal, be sure to select 2-channel mode for RT1/RT3/RT5 (OCS1/OCS3/
OCS5:CMOD=1)
*2 RTO0/RTO1 is controlled by DTCR0:TMD2 to TMD0, RTO2/RTO3 is controlled by DTCR1:TMD2 to TMD0 and
RTO4/RTO5 is controlled by DTCR2:TMD2 to TMD0.
339
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ PPG0 Output Control
PPG0 output to RTO0 to RTO5 can be enabled by PGEN0 to PGEN5 in PPG output control/input capture
control status register (PICSH01).
■ Gate Triggered PPG0 Output
In waveform generator, a GATE signal can be generated by using real-time outputs RT0 to RT5 or cope
with 16-bit timers 0/1/2 to trigger PPG0 counting. When 16-bit timer is used, two real-time outputs RT0/
RT2/RT4 and RT1/RT3/RT5 is operated with one 16-bit timer 0/1/2 to generate six individual gate signal.
And these six gate signals are logically OR to generate a GATE signal to trigger PPG0 counting.
If PGEN0 to PGEN5 signal is also used, six different waveforms can be output to RTO0 to RTO5 by using
one PPG0 only.
■ Generating GATE Signal during Each RTx is at "H" Level when GTENx is active
(DTCR0/DTCR1/DTCR2:TMD2 to TMD0=001B or 111B)
Figure 14.6-22 Generating GATE Signal during RTx is at "H" Level
16-bit free-run timer
FFFFH
BFFFH
Count value
7FFFH
3FFFH
Time
0000H
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
GATE0
GATE1
GATE
340
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Generating GATE Signal from Rising Edge of Each RTx until 16-bit Timer 0/1/2
Underflow when GTENx is active (DTCR0/DTCR1/DTCR2:TMD2 to TMD0=010B)
Figure 14.6-23 Generating GATE Signal from Rising Edge of RTx until 16-bit Timer Underflow
16-bit free-run timer
FFFFH
BFFFH
Count value
7FFFH
3FFFH
Time
0000H
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
GATE0
GATE1
Time of
16-bit timer 0
Time of
16-bit timer 0
GATE
Note:
Each 16-bit timer is used for two RTs. i.e. 16-bit timer 0 is used for RT0 and RT1; 16-bit timer 1 is
used for RT2 and RT3; 16-bit timer 2 is used for RT4 and RT5. Therefore, do not use an RT and
attempt to start the corresponding timer that is already operating. Doing so may cause that the
outputting GATE signal will be extended and malfunction will be occurred.
341
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.6.4.1
Operation in Timer Mode
With RT0 to RT5 rising edge, the 16-bit timer is reloaded, starts down-counting and the
PPG timer 0 keeps outputting to RTO0 to RTO5 until the 16-bit timer is underflow.
■ PPG0 Output Pulse from Tising Rdge of RT to 16-bit Timer Underflow
(DTCR0/DTCR1/DTCR2:TMD2 to TMD0=010B)
Figure 14.6-24 Waveform generated when TMD2 to TMD0=010B
Setting up registers:
T CDT
: 0000H
PCSR
T CCS
: XXXXXXXXXX0X0XXXB
PDUT
: XXXXH
CPCLR
: XXXXH (Cycle setting)
PCNT
: XXXXH
PICS01
: XXH (PPG0 output selection)
OCCP0 to OCCP5 : XXXXH (Compare value)
OCS0 to OCS5
: XXXXH
: -XX0XXXXXXXXXX11B
DTCR0 to DTCR2 : 011XX010B
TMRR0 to TMRR2 : XXXXH (Non-overlap timing setting)
SIGCR
Note:
: XXXXXX00B (DTTI input and 16-bit timer count clock setting)
“X” must be set according to the operation.
16-bit free-run timer
FFFFH
Count
value
BFFFH
7FFFH
3FFFH
0000H
Time
PPG0
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
GAT E
RTO0
RTO1
Time of
16-bit timer 0
Note:
342
Time of
16-bit timer 0
Each 16-bit timer is used for two RTs. i.e. 16-bit timer 0 is used for RT0 and RT1; 16-bit timer 1 is
used for RT2 and RT3; 16-bit timer 2 is used for RT4 and RT5. Therefore, do not use an RT and
attempt to start PPG0 which is under operation. Doing so may cause that the outputting GATE signal
will be extended and malfunction will be occurred.
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.6.4.2
Operation in Dead-time Timer Mode
The dead-time generator will input the real-time output (RT1/RT3/RT5), select PPG timer
0 pulse output, and output non-overlap signals (inverted signals) to external pins (RTO0
to RTO5).
■ Making Non-overlap Signals by using RT1/RT3/RT5 in Normal Polarity
(DTCR0/DTCR1/DTCR2:TMD2 to TMD0=100B)
When selecting non-overlap signal for an active level "0" (normal polarity) in DTCR0/DTCR1/
DTCR2:DMOD, a delay corresponding to the non-overlap time set in the TMRR0/TMRR1/TMRR2
register (16-bit timer register) is applied. The delay is applied at a rising edge of RT1/RT3/RT5 or its
falling edge. If RT1/RT3/RT5 pulse width is smaller than the set non-overlap time, the 16-bit timer will
restart down-counting from TMRR0/TMRR1/TMRR2 value at the next RT's edge.
Figure 14.6-25 Non-overlap Signal Generation by RT1/RT3/RT5 in Normal Polarity
Setting up registers:
• TCDT
: 0000H
• CPCLR
: XXXXH (Cycle setting)
• TCCS
: X--XXXXXX0X0XXXB
• OCS0 to OCS5
: -XX1XXXXXXXXXX11B
• OCCP0 to OCCP5 : XXXXH (Compare value)
• DTCR0 to DTCR2 : 0XXXX100B
• TMRR0 to TMRR2 : XXXXH (Non-overlap timing setting)
• SIGCR
Note:
: XXXXXXXXB (DTTI0 input and 16-bit timer count clock setting)
“X” must be set according to the operation.
16-bit timer 0
TMRR0 set value
Count
value
RT1
RTO0 (U)
RTO1 (X)
1 machine cycle
Pin name
1.5 machine cycle
Output signal
RTO0 (U)
Signal with delay is applied at RT1 rising edge
RTO2 (V)
Signal with delay is applied at RT3 rising edge
RTO4 (W)
Signal with delay is applied at RT5 rising edge
RTO1 (X)
Inverted signal with delay is applied at RT1 falling edge
RTO3 (Y)
Inverted signal with delay is applied at RT3 falling edge
RTO5 (Z)
Inverted signal with delay is applied at RT5 falling edge
343
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Making Non-overlap Signals by using RT1/RT3/RT5 in Inverted Polarity
(DTCR0/DTCR1/DTCR2:TMD2 to TMD0=100B)
When selecting non-overlap signal for a active level "1" (inverted polarity) in DTCR0/DTCR1/
DTCR2:DMOD, a delay corresponding to the non-overlap time set in the TMRR0/TMRR1/TMRR2
register (16-bit timer register) is applied. The delay is applied at a rising edge of RT1/RT3/RT5 or its
falling edge. If RT1/RT3/RT5 pulse width is smaller than the set non-overlap time, the 16-bit timer will
restart down-counting from TMRR0/TMRR1/TMRR2 value at the next RT's edge.
Figure 14.6-26 Non-overlap Signal Generation by RT1/RT3/RT5 in Inverted Polarity
Setting up registers:
• TCDT
: 0000H
• CPCLR
: XXXXH (Cycle setting)
• TCCS
: XXXXXXXXXX0X0XXXB
• OCS0 to OCS5
: -XX1XXXXXXXXXX11B
• OCCP0 to OCCP5: XXXXH (Compare value)
• DTCR0 to DTCR2 : 1XXXX100B
• TMRR0 to MRR2 : XXXXH (Non-overlap timing setting)
• SIGCR
Note:
: XXXXXXXXB (DTTI0 input and 16-bit timer count clock setting)
“X” must be set according to the operation.
16-bit timer 0
TMRR0 set value
Count
value
RT1
RTO0 (U)
RTO1 (X)
1 machine cycle
Pin name
344
1.5 machine cycle
Output signal
RTO0 (U)
Inverted signal with delay is applied at RT1 rising edge
RTO2 (V)
Inverted signal with delay is applied at RT3 rising edge
RTO4 (W)
Inverted signal with delay is applied at RT5 rising edge
RTO1 (X)
Signal with delay is applied at RT1 falling edge
RTO3 (Y)
Signal with delay is applied at RT3 falling edge
RTO5 (Z)
Signal with delay is applied at RT5 falling edge
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Making Non-overlap Signals by using PPG in Normal Polarity
(DTCR0/DTCR1/DTCR2:TMD2 to TMD0=111B)
When selecting non-overlap signal for a active level "0" (normal polarity) in DTCR0/DTCR1/
DTCR2:DMOD, a delay corresponding to the non-overlap time set in the TMRR0/TMRR1/TMRR2
register (16-bit timer register) is applied. The delay is applied at a rising edge of PPG timer 0 pulse signal
or its inverted signal. If PPG timer pulse width is smaller than the set non-overlap time, the 16-bit timer
will start down-counting from TMMR0/TMMR1/TMMR2 value at the next edge of PPG0 pulse.
Figure 14.6-27 Non-overlap Signal Generation by PPG0 in Normal Polarity
Setting up registers:
• TCDT
: 0000H
• PCSR
• TCCS
: XXXXXXXXXX0X0XXXB
• PDUT
: XXXXH
: XXXXH (Cycle setting)
• PCNT
: XXXXH
• CPCLR
: XXXXH
• OCCP0 to OCCP5: XXXXH (Compare value)
• OCS0 to OCS5
: -XX1XXXXXXXXXX11B
• DTCR0 to DTCR2 : 0XXXX111B
• TMRR0 to TMRR2: XXXXH (Non-overlap timing setting)
: XXXXXXXXB (DTTI0 input and 16-bit timer count clock setting)
• SIGCR
Note:
“X” must be set according to the operation.
16-bit timer 0
TMRR0 set value
Count
value
PPG0
RTO0 (U)
RTO1 (X)
1 machine cycle
Pin name
1.5 machine cycle
Output signal
RTO0 (U)
Signal with delay is applied at PPG0 rising edge
RTO2 (V)
Signal with delay is applied at PPG0 rising edge
RTO4 (W)
Signal with delay is applied at PPG0 rising edge
RTO1 (X)
Inverted signal with delay is applied at PPG0 falling edge
RTO3 (Y)
Inverted signal with delay is applied at PPG0 falling edge
RTO5 (Z)
Inverted signal with delay is applied at PPG0 falling edge
345
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Making Non-overlap Signals by using PPG in Inverted Polarity
(DTCR0/DTCR1/DTCR2:TMD2 to TMD0=111B)
When selecting non-overlap signal for an active level "1" (inverted polarity) in DTCR0/DTCR1/
DTCR2:DMOD, a delay corresponding to the non-overlap time set in the TMRR0/TMRR1/TMRR2
register (16-bit timer register) is applied. The delay is applied at a rising edge of PPG timer 0 pulse signal
or its inverted signal. If PPG timer 0 pulse width is smaller than the set non-overlap time, the 16-bit timer
will start down-counting from TMMR0/TMMR1/TMMR2 value at the next edge of PPG0 pulse.
Figure 14.6-28 Non-overlap Signal Generation by PPG0 in Inverted Polarity
Setting up registers:
• TCDT
• PCSR
: 0000H
• TCCS
: XXXXXXXXXX0X0XXXB
• CPCLR
: XXXXH (Cycle setting)
• OCCP0 to OCCP5
:XXXXH (Compare value)
• OCS0 to OCS5
: -XX1XXXXXXXXXX11B
: XXXXH
• PDUT
: XXXXH
• PCNT
: XXXXH
• DTCR0 to DTCR2
: 1XXXX111B
• TMRR0 to TMRR2
: XXXXH (Non-overlap timing setting)
• SIGCR
: XXXXXXXXB (DTTI0 input and 16-bit timer count clock setting)
Note:
“X” must be set according to the operation.
16-bit timer 0
TMRR0 set value
Count
value
PPG0
RTO0 (U)
RTO1 (X)
1 machine cycle
Pin name
346
1.5 machine cycle
Output signal
RTO0 (U)
Inverted signal with delay is applied at PPG0 rising edge
RTO2 (V)
Inverted signal with delay is applied at PPG0 rising edge
RTO4 (W)
Inverted signal with delay is applied at PPG0 rising edge
RTO1 (X)
Signal with delay is applied at PPG0 falling edge
RTO3 (Y)
Signal with delay is applied at PPG0 falling edge
RTO5 (Z)
Signal with delay is applied at PPG0 falling edge
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.6.4.3
Operation of DTTI0 Pin Control
By setting "1" to waveform control register, SIGCR: bit7 (DTIE), the output of RTO0 to RTO5
can be controlled by the DTTI0 pin. When "L" level in DTTI0 is detected, the output of RTO0
to RTO5 will be fixed to an inactive level until the interrupt flag, SIGCR: bit6 (DTIF) is
cleared. The inactive level of RTO0 to RTO5 can be set by PDR3 in port 3 by software.
■ DTTI0 Pin Input Operation
Even when the "L" level of DTTI0 pin input is detected, the timer will keep running for the waveform
generator operation, but no waveform will outputted to external pins P30/RTO0 to P35/RTO5.
Figure 14.6-29 Operation when DTTI0 Input is enabled
Setting up registers:
• TCDT
: 0000H
• CPCLR
• TCCS
: XXXXXXXXXX0X0XXXB
: XXXXH (Cycle setting)
• OCS0 to OCS5
: -XX1XXXXXXXXXX11B
• OCCP0 to OCCP5 : XXXXH (Compare value)
• PDR3
: XXXXXX00B (Inactive level setting)
• DTCR0 to DTCR2 : 0XXXX100B
• TMRR0 to TMRR2 : XXXXH (Non-overlap timing setting)
• SIGCR
Note:
: 1XXXXXXXB (DTTI0 input and 16-bit timer count clock setting)
“X” must be set according to the operation.
16-bit free-run timer
FFFFH
Count value
BFFFH
7FFFH
3FFFH
Time
0000H
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT1
RTO0
RTO1
DTTI0
DTIF
Output inactive
Software Clear
347
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ DTTI0 Pin Noise Cancellation Function
By setting bit5 (NRSL) of the waveform control register (SIGCR) to "1", the noise cancellation function for
DTTI0 pin input is enabled. When noise cancellation function is enabled, the time for fixing an output pin
RTO0 to RTO5 to inactive level is delayed for about 4, 8, 16 or 32 machine cycles (selected by
SIGCR:NWS1,NWS0). Since the noise cancellation circuit uses a peripheral clock, input is invalidated
even if the DTTI0 input is enabled in a mode such as STOP mode in which the oscillation stops.
■ DTTI0 Interrupt
When low level of DTTI0 is detected, DTTI0 interrupt flag (SIGCR:DTIF) is set to "1" after noise
cancellation time is passed and an interrupt request is sent to interrupt controller.
Figure 14.6-30 DTTI0 Interrupt Timing
DTTI0
SIGCR: DTIF
Noise cancellation time controlled
by SIGCR:NWS1,NWS0
Software write “0” in SIGCR: DTIF
Notes:
348
• If SIGCR:NWS1,NWS0 is changed within noise cancellation time, the larger value of NWS1,
NWS0 will take effect.
• SIGCR:DTIF can only be software clear.
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.7
Usage Notes on the Multi-functional Timer
Notes on using the multi-functional timer are given below.
■ Usage Notes on the 16-bit Free-run Timer
● Notes about using a program for setting
• After reset, the timer value is "0000H", zero detect interrupt flag will be set to "1" in next count clock
after timer enable (TCCSL:STOP=0).
• Since the timer mode bit (TCCSL:MODE) has a buffer, changing timer mode will take effect in next
count cycle. Zero detect interrupt is always generated when timer mode is changed from up-count to updown count mode.
• Software clear timer (TCCSL:SCLR=1) will initialize the timer but not generate zero detect interrupt.
● Notes about interrupts
• When the IRQZF bit of the timer control status register (TCCSH) is set to "1" and an interrupt request is
enabled (TCCSH:IRQZE=1), control cannot be returned from interrupt processing. Always clear the
IRQZF bit.
• When the ICLR bit of the timer control status register (TCCSH) is set to "1" and an interrupt request is
enabled (TCCSH:ICRE=1), control cannot be returned from interrupt processing. Always clear the
ICLR bit.
• Since the 16-bit free-run timer shares an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the 16-bit free-run timer, shared resource interrupts must be disabled.
■ Usage Notes on the 16-bit Output Compare
● Notes about interrupts
• When the IOP bit of the compare control register (OCS0/OCS2/OCS4) is set to "1" and an interrupt
request is enabled (OCS0/OCS2/OCS4:IOE=1), control cannot be returned from interrupt processing.
Always clear the IOP bit.
• Since the 16-bit output compare shares an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the 16-bit output compare, shared resource interrupts must be disabled.
349
CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Usage Notes on the 16-bit Input Capture
● Notes about interrupts
• When the ICP bit of the input capture control status register (PICSL01/ICSL23) is set to "1" and an
interrupt request is enabled (PICSL01/ICSL23:ICE=1), control cannot be returned from interrupt
processing. Always clear the ICP bit.
• If input capture pins IN is toggled after ICP bit is set but before interrupt routine is processed, the edge
indication bit (ICSH23:IEI3,IEI2 or PICSH01:IEI1,IEI0) will show the latest edge detected.
• Since the 16-bit input capture shares an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the 16-bit input capture, shared resource interrupts must be disabled.
■ Usage Notes on the Waveform Generator
● Notes on using a program for setting
• Change the TMD2, TMD1 and TMD0 bits of the 16-bit timer control register (DTCR0/DTCR1/
DTCR2) when the waveform generator is under operation (TMD2 to TMD0=001B, 010B, 100B or
111B), always be sure no trigger source and timer is not counting. Otherwise unexpected waveform in
RTO will be occurred due to prescheduled output by previous trigger. But RTO output becomes normal
once after timer is underflow or retriggered by new trigger source in new mode setting.
Trigger source is H level of RT when TMD2 to TMD0=001B, rising edge of RT when TMD2 to
TMD0=010B, rising/falling edge of RT when TMD2 to TMD0=100B or rising/falling edge of PPG0
when TMD2 to TMD0=111B.
For example, changing TMD2 to TMD0 from 100B to 111B, you can set in following procedures
1) set TMRR0/TMRR1/TMRR2 to a very small value like 0001H
2) set RT1/RT3/RT5 to output "L"/"H" and wait until timer 0/1/2 underflow
3) change mode bits TMD2, TMD1 and TMD0 and corresponding setting
4) corrected output waveform will appear in RTO pins one machine cycle later
• Writing a value in 16-bit timer register (TMRR0/TMRR1/TMRR2) during timer counting, new value
will be valid at the next timer trigger. And always be sure to use a word transfer instruction (MOVW A,
dir, etc.) to access timer register.
• Change the DCK2, DCK1 and DCK0 bits of the waveform control register (SIGCR) when the timer is
not counting.
• Change the NWS1 and NWS0 bits of waveform control register (SIGCR) when the noise cancellation
function is disabled (SIGCR: NRSL=0).
● Notes about interrupts
• When the TMIF bit of the timer control register (DTCR) is set to "1" and an interrupt request is enabled
(DTCR:TMIE=1), control cannot be returned from interrupt processing. Always clear the TMIF bit.
• When the DTIF bit of the waveform control register (SIGCR) is set to "1", control cannot be returned
from interrupt processing. Always clear the DTIF bit.
• Since the waveform generator shares an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the waveform generator, shared resource interrupts must be disabled.
350
CHAPTER 14 MULTI-FUNCTIONAL TIMER
14.8
Sample Programs for the Multi-functional Timer
This section contains sample programs for the multi-functional timer.
■ Sample Program for 16-bit Free-run Timer
● Processing
• A 4 ms compare clear interrupt is generated with 16-bit free-run timer 0.
• The timer is used in up-down mode to repeatedly generate a compare clear interrupt.
• EI2OS is not used.
• 16 MHz is used for the machine clock, and 62.5 ns is used for the count clock.
● Coding example
ICR11
EQU
0000BBH
;Interrupt control register for the
16-bit free-run timer
TCCS
EQU
00005EH
;Timer control status register
CPCLRB
EQU
000058H
;Compare clear buffer register
ICLR
EQU
TCCS:9
;Interrupt request flag bit
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
;Assumes that stack pointer (SP) has already been
initialized
AND
CCR,#0BFH
;Interrupt disable
MOV
I:ICR11,#00H
;Interrupt level 0 (strongest)
MOVW
I:CPCLRB,#0FFFFH ;Set compare clear value to change
16-bit free-run timer from up-count to
down-count
MOVW
I:TCCS,#0110H
;Sets up-down mode, 62.5 ns count clock
;Enables compare clear interrupt
;Disables interrupt mask
;Clears interrupt flag and enable timer
LOOP:
MOV
ILM,#07H
;Sets ILM in PS to level 7
OR
CCR,#40H
; Interrupt enable
MOV
A,#00H
;Endless loop
MOV
A,#01H
;
BRA
LOOP
;
;-------Interrupt program--------------------------------------------------------------------------------------------
351
CHAPTER 14 MULTI-FUNCTIONAL TIMER
WARI:
CLRB
I:ICLR
;
:
;
User processing
;
:
;Clears interrupt request flag
RETI
CODE
;Returns from interrupt
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------VECT
VECT
CSEG
ABS=0FFH
ORG
0FF74H
DSL
WARI
ORG
0FFDCH
DSL
START
DB
00H
;Sets vector for interrupt #34 (22H)
;Sets reset vector
;Sets single-chip mode
ENDS
END
START
■ Sample Program for 16-bit Output Compare
● Processing
A output compare match interrupt is generated when the count value of 16-bit free-run timer is matched
with output compare 0.
• The 16-bit free-run timer is used in up-count mode.
• EI2OS is not used.
• 16 MHz is used for the machine clock, and 62.5 ns is used for the count clock of 16-bit free-run timer.
● Coding example
ICR00
EQU
0000B0H
;Interrupt control register for the output compare 0
TCCS
EQU
00005EH
;Timer control status register
CPCLRB
EQU
000058H
;Compare clear buffer register
OCCP0
EQU
000070H
;Output compare register 0
OCCP1
EQU
000072H
;Output compare register 1
OCS01
EQU
00007CH
;Compare control register
IOP
EQU
OCS01:6
;Interrupt request flag bit
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
;Assumes that stack pointer (SP) has already been
initialized
352
CHAPTER 14 MULTI-FUNCTIONAL TIMER
AND
CCR,#0BFH
;Interrupt disable
MOV
I:ICR00,#00H
;Interrupt level 0 (strongest)
MOVW
I:TCCS,#0000H
;Enables 16-bit free-run timer
;Sets up-count mode
MOVW
I:OCCP0,#0BFFFH
;Set output compare register 0
MOVW
I:OCCP1,#07FFFH
;Set output compare register 1
MOVW
I:OCS01,#0C1FH
;Enables output compare output
;Enables compare match interrupt 0
;Clears interrupt flag and enable output compare
LOOP:
MOV
ILM,#07H
;Sets ILM in PS to level 7
OR
CCR,#40H
; Interrupt enable
MOV
A,#00H
;Endless loop
MOV
A,#01H
;
BRA
LOOP
;
;-------Interrupt program-------------------------------------------------------------------------------------------WARI:
CLRB
I:IOP
;
:
;
User processing
;
:
RETI
CODE
;Clears interrupt request flag
;Returns from interrupt
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------VECT
VECT
CSEG
ABS=0FFH
ORG
0FFCCH
DSL
WARI
ORG
0FFDCH
DSL
START
DB
00H
;Sets vector for interrupt #12 (0CH)
;Sets reset vector
;Sets single-chip mode
ENDS
END
START
353
CHAPTER 14 MULTI-FUNCTIONAL TIMER
354
CHAPTER 15
MULTI-PULSE GENERATOR
This chapter describes the specification and operation
of the Multi-pulse Generator.
15.1 Overview of Multi-pulse Generator
15.2 Block Diagram of Multi-pulse Generator
15.3 Multi-pulse Generator Pins
15.4 Registers of Multi-pulse Generator
15.5 Multi-pulse Generator Interrupts
15.6 Operation of Multi-pulse Generator
15.7 Usage Notes on the Multi-pulse Generator
15.8 Sample Programs for the Multi-pulse Generator
355
CHAPTER 15 MULTI-PULSE GENERATOR
15.1
Overview of Multi-pulse Generator
The Multi-pulse Generator consists of a 16-bit PPG timer, a 16-bit reload timer and a
waveform sequencer. By using the waveform sequencer, 16-bit PPG timer output signal
can be directed to Multi-pulse Generator output (OPT5 to OPT0) according to the input
signal of Multi-pulse Generator (SNI2 to SNI0). Meanwhile, the OPT5 to OPT0 output
signal can be hardware terminated by DTTI1 input in case of emergency. The OPT5 to
OPT0 output signals are synchronized with the PPG signal in order to eliminate the
unwanted glitch.
Note:
In MB90465 series, 16-bit PPG timer and waveform sequencer are not present in
Multi-pulse Generator, but 16-bit Reload Timer can be used individually.
For the detail information about 16-bit Reload Timer and 16-bit PPG Timer, please refer
to Chapter 12, 16-bit Reload Timer and Chapter 13, 16-bit PPG Timer respectively.
■ Function of Waveform Sequencer
● Output Signal Control
With waveform sequencer, it is possible to generate 16-bit PPG waveform output and DC chopper
waveform output at the Multi-pulse Generator output (OPT5 to OPT0).
• When an effective edge of the input signal from Multi-pulse Generator position detect input (SNI2 to
SNI0) or when the 16-bit reload timer is underflow or when the OPDBR0 register is written, one of
Output Data Buffer Registers (OPDBRB to OPDBR0) will be loaded into the Output Data Register
(OPDR).
• The Output Data Register (OPDR) determines the 16-bit PPG timer output to which OPT output (OPT5
to OPT0). By loading different Output Data Buffer Registers (OPDBRB to OPDBR0) into the Output
Data Register (OPDR). Various combination of OPT outputs (OPT5 to OPT0) can be obtained.
• Therefore, the 16-bit PPG timer output can be presented/absented at Multi-pulse Generator output
(OPT5 to OPT0) or switch the PPG timer output signal from one OPT output to another OPT output
according to the sequence set in the Output Data Register (OPDR) and 12 Output Data Buffer Registers
(OPDBRB to OPDBR0). Meanwhile, the 16-bit reload timer can insert a delay when switch OPT
output.
• Table 15.1-1 shows the combination the data transfer from OPDBRB to OPDBR0 registers to OPDR
register.
Table 15.1-1 Data Transfer from OPDBRB to OPDBR0 Registers to OPDR Register
Combination
356
Data transfer from OPDBRB to OPDBR0 to OPDR
1
Data transfer from OPDBR0 to OPDR after OPDBR0 is written by software.
2
Triggered by the16-bit reload timer 0 underflow.
3
Triggered by the position detection input (SNI2 to SNI0).
4
Triggered by the 16-bit reload timer 0 underflow.
The 16-bit timer is started by the position detection comparison circuit.
5
Triggered either by the 16-bit reload timer 0 underflow, or by the position detection input.
CHAPTER 15 MULTI-PULSE GENERATOR
• In the waveform sequencer, there is a 16-bit timer that can be used to measure the speed of the motor
and disable the OPT output in case of position detect missing.
• Forced stop control using DTTI1 pin input
External pin control can be performed through clockless DTTI1 pin input even when oscillation is
stopped. (The pin level can be set by each pin or software.) There is selectable noise filter for DTTI1
input. Table 15.1-2 shows the noise width for noise filter of DTTI1 pin.
Table 15.1-2 Noise Width for Noise Filter
Selection
Noise width for DTTI1 and SNI2 to SNI0 pins
1
Cancel 4-cycle noise.
2
Cancel 8-cycle noise.
3
Cancel 16-cycle noise.
4
Cancel 32-cycle noise.
● PPG Synchronization for Output Signal
In order to avoid short pulse (or glitch) during sequencer state changes, the write timing (WTO) needs to be
delayed and synchronized with the next coming edge of PPG output waveform. See Figure 15.1-1 and
Figure 15.1-2 for details. This function can be enabled or disabled by software. WTS1 and WTS0 bits of
the Input Control Register (IPCR) are used to disable this function and to select the polarity of the PPG
edge to synchronize with.
Figure 15.1-1 PPG Rising Edge Synchronization
PPG
Asynchronous State Change
WTS1,WTS0 = 00B
OP5
Glitch
OP4
Synchronous State Change
WTS1,WTS0 = 01B
OP5’
OP4’
Sequencer changes
state due to, e.g. the
reload timer 0 underflow.
357
CHAPTER 15 MULTI-PULSE GENERATOR
Figure 15.1-2 PPG Falling Edge Synchronization
PPG
Asynchronous State Change
WTS1,WTS0 = 00B
Glitch
OP5
OP4
Synchronous State Change
WTS1,WTS0 = 10B
OP5’
OP4’
Sequencer changes
state due to, e.g. the
reload timer 0 underflow.
Note:
Switch from one PPG synchronization mode to another PPG synchronization mode (e.g. from risingedge synchronization to falling-edge synchronization or vice versa) is inhibited, no synchronization
mode must be the transit for such switch.
● Input Position Detect Control
The input signal at the Multi-pulse Generator input pins (SNI2 to SNI0) is used to detect the rotor position
of the DC motor. There is a Noise Filter for all SNI2 to SNI0 input and Table 15.1-2 shows the noise width
for noise filter of SNI2 to SNI0 pins. The followings are conditions for the input position detect circuit:
• 3 edge selection for all SNI2 to SNI0; Rising edge, falling edge and both edges.
• Compare the levels of SNI2 to SNI0 inputs with RDA2 to RDA0 bits of Output Data Register (OPDR:
RDA2 to RDA0).
After above condition met, the writing timing signal will be generated for the data transfer between
OPDBR registers and OPDR register.
Furthermore, the edge detection for individual input (SNI2 to SNI0) can be disable/enable.
358
CHAPTER 15 MULTI-PULSE GENERATOR
15.2
Block Diagram of Multi-pulse Generator
Figure 15.2-1 shows the block diagram of the Multi-pulse Generator and Figure 15.2-2
shows the block diagram of the Waveform Sequencer.
■ Block Diagram of Multi-pulse Generator
Figure 15.2-1 Block Diagram of Multi-pulse Generator
Pin
DTTI
OPT5
Pin P05/OPT5
P45/SNI2
Pin
SNI2
OPT4
Pin P04/OPT4
P44/SNI1
Pin
SNI1
OPT3
Pin P03/OPT3
P43/SNI0
Pin
SNI0
OPT2
Pin P02/OPT2
P15/INT5/TIN0
Pin
TIN0
OPT1
Pin P01/OPT1
OPT0
Pin P00/OPT0
F2MC-16LX Bus
P12/INT2/DTTI1
WAVEFORM
SEQUENCER
16-BIT PPG TIMER 1
16-BIT RELOAD TIMER 0
PPG1
TOUT
TIN
PPG1
Interrupt #22
Interrupt #22
Interrupt #26
Interrupt #26
Interrupt #28
Interrupt #28
WIN0
TIN0O
Pin P15/INT5/TIN0
*
* : The dash line shows the TIN0 path in MB90465 series.
The 16-bit reload timer 0 can be used individually
in MB90465 series.
Pin P16/INT6/TO0
● 16-bit PPG Timer 1
The 16-bit PPG Timer 1 is used to provide a PPG signal for Waveform Sequencer. The detail of 16-bit PPG
Timer 1 is described in Chapter 13, 16-bit PPG Timer.
● 16-bit Reload Timer 0
The 16-bit Reload Timer 0 is used to act as interval timer for Waveform Sequencer. The detail of 16-bit
Reload Timer 0 is described in Chapter 12, 16-bit Reload Timer.
● Waveform Sequencer
The Waveform Sequencer is the heart of Multi-pulse Generator, that can generate various waveforms. The
block diagram is shown in Figure 15.2-2.
359
CHAPTER 15 MULTI-PULSE GENERATOR
■ Block Diagram of Waveform Sequencer
Figure 15.2-2 Block Diagram of Waveform Sequencer
Interrupt
# 26
WRITE TIMING INTERRUPT
Interrupt #22
POSITION DETECTION INTERRUPT
OPCR Register
PDIRT
DTIE DTIF NRSL OPS2 OPS1 OPS0 WTIF WTIE PDIF PDIE OPE5 OPE4 OPE3 OPE2 OPE1 OPE0
From PPG1
WTS1
WTS0
OPDBRB to OPDBR0
Registers
SYN Circuit
Pin P01/OPT1
OPx1/OPx0
OUTPUT
CONTROL
CIRCUIT
Pin P02/OPT2
Pin P03/OPT3
Pin P04/OPT4
Pin P05/OPT5
P12/INT2/DTTI1
DTTI1 Control
Circuit
Noise
Filter
Pin
RDA2 to
RDA0
D1
D0
DECODER
3
3
COMPARE CLEAR INTERRUPT
BNKF
F2MC-16LX Bus
OUTPUT DATA BUFFER REGISTER x 12
OPDR Register
Pin P00/OPT0
Pin P15/INT5/TIN0
WTO
16-BIT TIMER
CCIRT
P43/SNI0
WTIN1
Pin
WTO
DATA WRITE
CONTROL UNIT
POSITION
DETECT
CIRCUIT
OPS2
3
OPS1
SELECTOR
P44/SNI1
Pin
P45/SNI2
OPS0
Pin
TIN0O
WTIN0
TIN0O
WTIN0
WTIN1
WTIN1
COMPARISON CIRCUIT
WTS1 WTS0 CPIF CPIE CPD2 CPD1 CPD0 CMPE CPE1 CPE0 SNC2 SNC1 SNC0 SEE2 SEE1 SEE0
COMPARE MATCH INTERRUPT
IPCR Register
S21
S20
S11
NCCR Register
360
S10
S01
S00
D1
D0
PDIRT
Interrupt #28
CHAPTER 15 MULTI-PULSE GENERATOR
● 16-bit Timer
The 16-bit timer is used to act as an interval timer for motor speed checking and abnormal detection timer
when control DC sensorless motor. The detail is shown in Figure 15.2-3.
● Comparison Circuit
The Comparison Circuit is used to compare the RDA2 to RDA0 bits of the Output Data Register (OPDR:
RDA2 to RDA0) with the CPD2 to CPD0 bits of the Input Control Register (IPCR: CPD2 to CPD0) for
motor direction change. A compare match interrupt is generated when a match is happened.
● Data Write Control Unit
The Data Write Control Unit is used to generate the write signal (WTO) for transferring data from the
Output Data Buffer Register (OPDBR) to Output Data Register (OPDR). The detail is shown in Figure
15.2-4.
● Decoder
The Decoder is used to decode the bit15 to bit12 of Output Data Register (OPDR: BNKF, RDA2 to RDA0)
to select which Output Data Buffer Register (OPDBRB to OPDBR0) is loaded into Output Data Register.
● DTTI1 Control
The DTTI1 Control is used to stop the Multi-pulse Generator output in case of emergency, that is triggered
by level "0" of DTTI1 input.
● Noise Filter
The Noise Filter is used to filter out the noise of the input signal in which there are 4 kind of sampling
clock for selection.
● Output Control Unit
The Output Control Unit is used to enable/disable PPG signal to the Multi-pulse Generator Outputs (OPT5
to OPT0).
● Position Detect Circuit
The Position Detect Circuit is used to detect the edge/level of the position input (SNI2 to SNI0). The detail
is shown in Figure 15.2-5.
● SYN Circuit
The SYN Circuit is used to synchronize the OPT5 to OPT0 outputs with the PPG signal.
● Noise Cancellation Control Register (NCCR)
The Noise Cancellation Control Register (NCCR) is used to select one of four sampling clock for the Noise
Filter.
361
CHAPTER 15 MULTI-PULSE GENERATOR
● Output Control Register (OPCR)
The Output Control Register (OPCR) is a register which enables the write timing interrupt and flag,
position detect interrupt and flag, sets the data transfer method, and sets the control of the OPT5 to OPT0
and DTTI1 pins.
● Output Data Buffer Register (OPDBRB to OPDBR0)
The Output Data Buffer Register is composed of twelve registers (OPDBRB to OPDBR0). The value of the
OPDBRx register specified by the BNKF, RDA2 to RDA0 bits is loaded into the OPDR register at the
rising edge of the write signal generated by the Data Write Control Unit.
● Output Data Register (OPDR)
The Output Data Register (OPDR) is used to store the output data to the OPT5 to OPT0 pins.
362
CHAPTER 15 MULTI-PULSE GENERATOR
■ Block Diagram of 16-bit Timer
Figure 15.2-3 Block Diagram of 16-bit Timer
Compare Clear Interrupt (CCIRT)
φ
TCSR
TCLR
ICLR
ICRE MODE TMEN CLK2
CLK1
CLK0
Prescaler
Clock
RST
RST
16-bit up counter
Latch
Q D
C
T[15:0]
F2MC-16LX Bus
CLK
16-bit compare clear
register
Compare circuit
WTO
WTIN1
16-bit timer buffer register
LD
● 16-bit Up Counter
The 16-bit Up Counter will be cleared when the match is happened between the count value and the
Compare Clear register.
● Compare Circuit
The Compare Circuit is used to compare the count value of the 16-bit Up Counter and the Compare Clear
register.
● Compare Clear Register (CPCR)
The Compare Clear Register (CPCR) is used to store the 16-bit value which is used to compare the value of
the 16-bit Up Counter.
363
CHAPTER 15 MULTI-PULSE GENERATOR
● Timer Buffer Register (TMBR)
The Timer Buffer Register (TMBR) is used store the value of the 16-bit Up Counter when a write timing
interrupt or position detect interrupt occurs.
● Timer Control Register (TCSR)
The Timer Control Status Register (TCSR) is used to control the operation of the 16-bit timer such as the
clock frequency, enable/disable the interrupt.
■ Block Diagram of Data Write Control Unit
Figure 15.2-4 Block Diagram of Data Write Control Unit
Write OPDBR0
From 16-bit
reload timer 0
TOUT
WTIN0
1-CYCLE
DELAY
CIRCUIT
FALLING
EDGE
DETECTOR
SELECTOR 1
WTO
RISING AND
FALLING
EDGE
DETECTOR
To 16-bit
reload timer 0
TIN
TIN0O
SELECTOR 0
Pin
P15/INT5/TIN0
From position
detect circuit
WTIN1
WTIN1
DECODER
OPS2
OPS1
OPS0
● 1-Cycle Delay Circuit
The 1-Cycle Delay Circuit is used to delay one CPU clock cycle of the trigger signal when the Output Data
Buffer Register 0 (OPDBR0) is written.
364
CHAPTER 15 MULTI-PULSE GENERATOR
● Selector 0
The Selector 0 is used to select from either WTIN1 of the Position Detect Circuit or external pin (P15/
INT5/TIN0) to enable the count of the 16-bit Reload Timer 0.
● Selector 1
The Selector 1 is used to select from among Write OPDBR or TOUT of 16-bit Reload timer 0 or WTIN1 of
Position Detect Circuit to generate the Write Timing signal (WTO).
● Falling Edge Detector
The Falling Edge Detector is used to detect the falling edge of the 16-bit Reload Timer 0 output (TOUT).
● Rising and Falling Edge Detector
The Rising and Falling Edge Detector is used to detect the rising and falling edge of the 16-bit Reload
Timer 0 output (TOUT).
When timer underflow trigger is used in following modes, the WTIN0 signal is generated by the trigger
edge selected by OPS2 to OPS0 bits:
Table 15.2-1 TOUT Trigger Edge Selection for WTIN0
OPS2
OPS1
OPS0
TOUT Trigger Edge for WTIN0
0
0
0
-
0
1
0
Rise and Fall
0
1
0
-
0
1
1
Fall
1
0
0
Rise and Fall
1
0
1
Rise and Fall
1
1
0
-
1
1
1
Fall
365
CHAPTER 15 MULTI-PULSE GENERATOR
■ Block Diagram of Position Detection Circuit
Figure 15.2-5 Block Diagram of Position Detection Circuit
RDA2
RDA1
RDA0
COMPARISON
CIRCUIT
NOISE
FILTER
CIRCUIT
SNI0
EDGE
DETECTION
CIRCUIT 0
SEE0
CPE1
CPE0
EDGE
DETECTION
CIRCUIT 1
NOISE
FILTER
CIRCUIT
SNI1
WTIN1
SEE1
CPE1
CPE0
CMPE
EDGE
DETECTION
CIRCUIT 2
NOISE
FILTER
CIRCUIT
SNI2
SELECTOR
CPE1
CPE0
SEE2
● Comparison Circuit
The Comparison Circuit is used to compare the level of the position detection input (SNI2 to SNI0) with
RDA2 to RDA0 bits of the Output Data Register (OPDR: RDA2 to RDA0). If the selector is selected, a
data write time output signal is generated when a match is detected.
● Edge Detect Circuit 0, 1, 2
Edge Detect Circuit 0, 1 and 2 are identical.
The Edge Detect Circuit is used to compare the edge of the position input (SNI2 to SNI0) with 3 different
kind of edge setting. If the selector is selected, a data write time output signal is generated when an
effective edge is detected at the one of SNI2 to SNI0 inputs.
● Noise Filter
The Noise Filter is used to filter out the noise of the input signal in which there are 4 kind of sampling
clock for selection.
● Selector
The Selector is used to select from either Edge Detect Circuit or Comparison Circuit to generate data write
time output signal to the Data Write Control Unit.
366
CHAPTER 15 MULTI-PULSE GENERATOR
15.3
Multi-pulse Generator Pins
This section describes the pins of the Multi-pulse Generator and provides a pin block
diagram.
■ Pins of Multi-pulse Generator
Multi-pulse Generator uses P00/OPT0 to P05/OPT5, P43/SNI0 to P45/SNI2, P12/INT2/DTTI1 and P15/
INT5/TIN0.
● P00/OPT0 to P05/OPT5 Pins
P00/OPT0 to P05/OPT5 pins can function either as a general-purpose I/O port (P00 to P05) or as waveform
output for Multi-pulse Generator.
Enabling waveform output bit (OPCLR: OPE5 to OPE0 = 111111B) automatically sets the P00/OPT0 to
P05/OPT5 pin as an output pin, regardless of the port data direction register (DDR0: bit5 to bit0) value, and
sets the pin to function as the OPT5 to OPT0 pin.
● P43/SNI0 to P45/SNI2 Pins
P43/SNI0 to P45/SNI2 pins can function either as a general-purpose I/O port (P43 to P45) or as the position
detect input for Multi-pulse Generator.
Set P43/SNI0 to P45/SNI2 pins as an input port in the data direction register (DDR4: bit5 to bit3 = 000B)
when using as SNI2 to SNI0 pins.
● P12/INT2/DTTI1 Pin
P12/INT2/DTTI1 pin can function either as a general-purpose I/O port (P12) or external interrupt INT2, or
as the DTTI1 input for Multi-pulse Generator.
Set P12/INT2/DTTI1 pin as an input port in the data direction register (DDR1: bit1 = 0) when using as
DTTI1 pins.
● P15/INT5/TIN0 Pin
P15/INT5/TIN0 pin can function either as a general-purpose I/O port (P15) external interrupt INT5, or as
the input of 16-bit Reload Timer 0 for Multi-pulse Generator.
Set P15/INT5/TIN0 pin as an input port in the data direction register (DDR1: bit5 = 0) when using as TIN0
pins.
367
CHAPTER 15 MULTI-PULSE GENERATOR
■ Block Diagram of Multi-pulse Generator Pins
Figure 15.3-1 Block Diagram of P00/OPT0 to P05/OPT5 Pins
RDR
Resource output
Port data register (PDR)
Direct resource input
Resource output enable
Pull-up resistor
About 50kΩ
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
Figure 15.3-2 Block Diagram of P12/INT2/DTTI1 to P15/INT5/TIN0 Pins
RDR
Resource input
Resource output
Port data register (PDR)
Resource output enable
Pull-up resistor
About 50kΩ
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
Figure 15.3-3 Block diagram of P43/SNI0 to P45/SNI2 pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
368
Standby control (SPL = 1)
CHAPTER 15 MULTI-PULSE GENERATOR
15.4
Registers of Multi-pulse Generator
This section describes the registers of the Multi-pulse Generator.
■ Registers of Multi-pulse Generator
Figure 15.4-1 Registers of Multi-pulse Generator
Output Control Register (Upper)
bit
14
15
13
11
12
10
8
9
OPCUR
_
Address: 00008BH
DTIE
Read/Write
R/W
Initial Value
0
NRSL
OPS2
OPS1 OPS0 WTIF
WTIE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
DTIF
Output Control Register (Lower)
bit
5
7
6
OPE5 OPE4
3
4
2
0
1
OPCLR
Address: 00008AH
PDIF
PDIE
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
OPE3 OPE2 OPE1 OPE0
Output Data Register (Upper)
15
bit
Address: 003FF9H
14
12
13
10
11
9
8
OPDR
_
BNKF RDA2
RDA1
RDA0
OP51 OP50
OP41
OP40
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
X
X
X
X
Output Data Register (Lower)
bit
7
6
5
4
OP20
OP11 OP10
3
1
2
0
OPDR
Address: 003FF8H
OP31
Read/Write
R
X
Initial Value
OP30 OP21
OP01 OP00
R
R
R
R
R
R
R
X
X
X
X
X
X
X
(Continued)
369
CHAPTER 15 MULTI-PULSE GENERATOR
(Continued)
Output Data Buffer Registers (Upper)
15
bit
Addresses:
003FF7H to E1H
(Odd Addresses)
13
14
_
BNKF RDA2
12
11
9
10
RDA1
RDA0
OP51 OP50
8
OPDBRB to
OPDBR0
OP41 OP40
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
5
4
3
2
1
Output Data Buffer Registers (Lower)
6
7
bit
Addresses:
003FF6H to E0H
(Even Addresses)
OP31
OP30 OP21
OP20
OP11 OP10
0
OP01
OP00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
OPDBRB to
OPDBR0
Input Control Register (Upper)
15
bit
Address: 00008DH
13
14
11
12
9
10
8
IPCUR
WTS1 WTS0
CPIF
CPIE
CPD2 CPD1 CPD0 CMPE
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
6
5
4
3
Input Control Register (Lower)
bit
7
0
2
1
SEE1
SEE0
IPCLR
Address: 00008CH
CPE1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
CPE0 SNC2 SNC1
SNC0 SEE2
(Continued)
370
CHAPTER 15 MULTI-PULSE GENERATOR
(Continued)
Compare Clear Register (Upper)
bit 15
13
14
12
11
9
10
8
CPCR
Address: 003FFBH
_
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
X
X
X
X
X
X
X
X
5
4
3
2
1
Compare Clear Register (Lower)
7
bit
6
0
CPCR
Address: 003FFAH
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
X
X
X
X
X
X
X
X
14
13
Timer Buffer Register (Upper)
bit
15
11
12
9
T10
T09
T08
R
R
R
0
0
0
8
TMBR
Address: 003FFDH
T15
T14
T13
T12
T11
Read/Write
R
R
R
R
R
Initial Value
0
0
Timer Buffer Register (Lower)
bit
7
0
0
0
6
5
4
3
2
1
0
TMBR
Address: 003FFCH
T07
Read/Write
R
Initial Value
0
T06
Timer Control Status Register
bit 15
Address: 00008FH
10
T05
T04
T03
T02
T01
T00
R
R
R
R
R
R
R
0
0
0
0
0
0
0
13
14
11
12
9
10
8
NCCR
S21
S20
S11
S10
S01
S00
D1
D0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
6
5
4
3
Noise Cancellation Control Register
bit 7
Address: 00008EH
0
2
1
CLK1
CLK0
TCSR
TCLR MODE ICLR
ICRE
TMEN CLK2
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
371
CHAPTER 15 MULTI-PULSE GENERATOR
15.4.1
Output Control Register (OPCR)
The Output Control Register (OPCR) is a register which enables the write timing
interrupt and flag, position detect interrupt and flag, sets the data transfer method, and
sets the control of the OPT5 to OPT0 and DTTI1 pins.
■ Output Control Upper Register (OPCUR)
Figure 15.4-2 Output Control Upper Register (OPCUR)
Address bit
00008BH
15
14
13
12
11
10
9
8
Initial value
DTIE
DTIF
NRSL
OPS2
OPS1
OPS0
WTIF
WTIE
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WTIE
Write timing interrupt enable bit
0
Disable interrupt.
1
Enable interrupt.
Write timing interrupt request flag bit
WTIF
Read
Write
0
No valid detected.
Clear this bit.
1
Valid detected.
No effect.
OPS2
OPS1
OPS0
Function
0
0
0
Data transfer from OPDBR0 to OPDR after
OPDBR0 is written by software.
0
0
1
Data transfer from OPDBR to OPDR is triggered
by the16-bit reload timer 0 underflow.
0
1
0
Data transfer from OPDBR to OPDR is triggered
by the position detection input.
0
1
1
Data transfer from OPDBR to OPDR is triggered
by the write signal generated by the 16-bit reload
timer 0 underflow, the 16-bit timer is started by
the positon detection comparison circuit.
1
0
0
Data transfer from OPDBR to OPDR is triggered
by the write signal generated either by the 16-bit
reload timer 0 underflow, or by the position
detection input.
1
0
1
One-shot position dectection or timer underflow.
1
1
0
One-shot position dectection.
1
1
1
One-shot position dectection and timer
underfow.
NRSL
Noise filter enable bit
0
DTTI1 input does not go through the noise filter.
1
DTTI1 input goes through the noise filter.
DTTI1 interrupt request flag bit
DTIF
X
: Initial value
372
Write
0
No valid detected.
Clear this bit.
1
Valid detected.
No effect.
: Indeterminate
R/W : Readable and writable
—
Read
: Not used
DTIE
DTTI1 control enable bit
0
Disable control by the DTTI1 input.
1
Enable control by the DTTI1 input.
CHAPTER 15 MULTI-PULSE GENERATOR
Table 15.4-1 Output Control Upper Register (OPCUR) Bits
Bit name
Function
DTIE:
DTTI1 control
enable bit
• DTTI1 pin input enable bit.
• This bit is used to enable the DTTI1 pin to control the output levels of the OPT5 to
OPT0 pins. The software can set the inactive level for each OPTx pin in PDRx of
PORTx.
DTIF:
DTTI1 interrupt
flag bit
• DTTI1 interrupt request flag.
• It is an interrupt request flag of the DTTI1 input, which is set whenever a falling
edge of DTTI1 is detected and the DTTI1 control enable bit is set to “1”.
• When this bit is set to “1”, the interrupt is generated. This bit is cleared by writing
“0”. Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
bit13
NRSL:
Noise filter
enable bit
• This bit is used to select the noise cancellation function when DTTI1 pin input is
enabled.
• The noise cancellation circuit starts the internal n-bit counter when an active level is
input (the value of n can be 2, 3, 4, 5, which depends on the setting of D1,D0 bits in
the Noise Cancellation Register). If the active level is held until the counter
overflows, the circuit accepts input from the DTTI1 pin. Therefore, the pulse width
of noise that can be cancelled is about 2n machine cycles.
(Note)
When the noise cancellation circuit is enable, the input becomes invalid in a mode
such as STOP mode in which the internal clock is stopped.
bit12
to
bit10
OPS2 to OPS0:
Data transfer
method selection bits
• OPTx pin output timing control selection bits.
• These bits are used to select the OPDR register write timing control operation mode.
Data is transferred from the Output Data Buffer Register to the Output Data Register
at the write timing controlled by the selected operation mode.
bit9
WTIF:
Write timing
interrupt flag
bit
• Write timing interrupt request flag.
• It is an interrupt request flag of the output timing switch, which is set by the write
signal. Data in the OPDBRx register which specified by the BNKF, RDA2 to RDA0
bits in Output Data Register (OPDR) is transferred to the OPDR at the rising edge of
the write signal and the WTIF bit is set to “1”.
• When this bit is set to “1”, the interrupt is generated if the write timing interrupt
enable bit (WTIE) is also set to “1”. This bit is cleared by writing “0”. Writing “1”
has no effect.
• In read-modify-write operation, “1” is always read.
bit8
WTIE:
Write timing
interrupt enable
bit
• Write timing interrupt enable bit.
• When this bit is set to “1”, the interrupt is generated if write timing interrupt request
flag (WTIF) is also set to “1”.
bit15
bit14
373
CHAPTER 15 MULTI-PULSE GENERATOR
■ Output Control Lower Register (OPCLR)
Figure 15.4-3 Output Control Lower Register (OPCLR)
Address
00008AH
bit
7
6
5
4
3
2
1
0
Initial value
PDIF
PDIE
OPE5
OPE4
OPE3
OPE2
OPE1
OPE0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OPE0
OPT0 output enable bit
0
Disable OPT0 pin output. (Initial value)
1
Enable OPT0 pin output.
OPE1
OPT1 output enable bit
0
Disable OPT1 pin output. (Initial value)
1
Enable OPT1 pin output.
OPE2
OPT2 output enable bit
0
Disable OPT2 pin output. (Initial value)
1
Enable OPT2 pin output.
OPE3
OPT3 output enable bit
0
Disable OPT3 pin output. (Initial value)
1
Enable OPT3 pin output.
OPE4
OPT4 output enable bit
0
Disable OPT4 pin output. (Initial value)
1
Enable OPT4 pin output.
OPE5
OPT5 output enable bit
0
Disable OPT5 pin output. (Initial value)
1
Enable OPT5 pin output.
PDIE
Position detection interrupt enable bit
0
Disable interrupt. (Initial value)
1
Enable interrupt.
Position detection interrupt request flag bit
PDIF
X
: Indeterminate
R/W : Readable and writable
: Initial value
—
374
: Not used
Read
Write
0
No valid detected.
Clear this bit.
1
Valid detected.
No effect.
CHAPTER 15 MULTI-PULSE GENERATOR
Table 15.4-2 Output Control Lower Register (OPCLR) Bits
Bit name
Function
bit7
PDIF:
Position detect
interrupt flag
bit
• Position detection interrupt request flag.
• It is an interrupt request flag for the position detection. When CMPE is set to "0" and the
SNI2 to SNI0 bits are compared and matched with the RDA2 to RDA0 bit, or when CMPE
is set to "1" and any effective edge is detected at SNI2 to SNI0 pins, this bit is set to "1".
• When this bit is set to "1", the interrupt is generated if the position detection interrupt
enable bit (PDIE) is also set to "1". This bit is cleared by writing "0". Writing “1” has no
effect.
• In read-modify-write operation, "1" is always read.
bit6
PDIE:
Position detect
interrupt enable
bit
• Position detection interrupt enable bit.
• When this bit is set to "1", the interrupt is generated if position detection interrupt request
flag (PDIF) is also set to "1".
bit5
to
bit0
OPE5 to OPE0:
OPT5 to OPE0
output enable
bits
• Output enable bits of OPT5 to OPE0 pins.
• When these bits are set, the outputs to the OPT5 to OPE0 pins are enable.
375
CHAPTER 15 MULTI-PULSE GENERATOR
15.4.2
Output Data Register (OPDR)
This is a register which stores the output data to the OPT5 to OPT0 pins.
■ Output Data Upper Register (OPDR)
Figure 15.4-4 Output Data Upper Register (OPDR)
Address bit 15
003FF9H
14
13
12
11
10
9
8
Initial value
BNKF
RDA2
RDA1
RDA0
OP51
OP50
OP41
OP40
0000XXXXB
R
R
R
R
R
R
R
R
OP41
OP40
0
0
Pin OPT4 outputs “L” level.
0
1
Pin OPT4 outputs the output of the PPG
timer.
1
0
Pin OPT4 outputs the inverted output of
the PPG timer.
1
1
Pin OPT4 outputs “H” level.
OP51
OP50
0
0
Pin OPT5 outputs “L” level.
0
1
Pin OPT5 outputs the output of the PPG
timer.
1
0
Pin OPT5 outputs the inverted output of
the PPG timer.
1
1
Pin OPT5 outputs “H” level.
BNKF RDA2 RDA1 RDA0
X
: Indeterminate
—
376
: Not used
OPT5 output waveform selection bits
OPDBR register selection bits
0
0
0
0
Data in OPDBR0 is loaded to OPDR.
0
0
0
1
Data in OPDBR1 is loaded to OPDR.
0
0
1
0
Data in OPDBR2 is loaded to OPDR.
0
0
1
1
Data in OPDBR3 is loaded to OPDR.
0
1
0
0
Data in OPDBR4 is loaded to OPDR.
0
1
0
1
Data in OPDBR5 is loaded to OPDR.
0
1
1
0
Data in OPDBR6 is loaded to OPDR.
0
1
1
1
Data in OPDBR7 is loaded to OPDR.
1
0
0
0
Data in OPDBR8 is loaded to OPDR.
1
0
0
1
Data in OPDBR9 is loaded to OPDR.
1
0
1
0
Data in OPDBRA is loaded to OPDR.
1
0
1
1
Data in OPDBRB is loaded to OPDR.
R/W : Readable and writable
: Initial value
OPT4 output waveform selection bits
Other values
Prohibited.
CHAPTER 15 MULTI-PULSE GENERATOR
Table 15.4-3 Output Data Upper Register (OPDR) Bits
Bit name
Function
bit15
to
bit12
BNKF, RDA2 to
RDA0:
OPDBR register
selection bits
• These bits indicate the addresses of the OPDBR registers and decide which
Output Data Buffer Register value is loaded into the OPDR register.
bit11,
bit10
OP51, OP50:
OPT5 output
waveform
selection bits
• These bits are used to select the kind of the output waveform to the OPT5 pin.
bit9,
bit8
OP41, OP40:
OPT4 output
waveform
selection bits
• These bits are used to select the kind of the output waveform to the OPT4 pin.
377
CHAPTER 15 MULTI-PULSE GENERATOR
■ Output Data Lower Register (OPDR)
Figure 15.4-5 Output Data Lower Register (OPDR)
Address bit 7
003FF8H
X
6
5
4
3
2
1
0
Initial value
OP31
OP30
OP21
OP20
OP11
OP10
OP01
OP00
XXXXXXXXB
R
R
R
R
R
R
R
R
: Indeterminate
R/W : Readable and writable
: Initial value
—
378
: Not used
OP01
OP00
OPT0 output waveform selection bits
0
0
Pin OPT0 outputs “L” level.
0
1
Pin OPT0 outputs the output of the PPG
timer.
1
0
Pin OPT0 outputs the inverted output of
the PPG timer.
1
1
Pin OPT0 outputs “H” level.
OP11
OP10
0
0
Pin OPT1 outputs “L” level.
0
1
Pin OPT1 outputs the output of the PPG
timer.
1
0
Pin OPT1 outputs the inverted output of
the PPG timer.
1
1
Pin OPT1 outputs “H” level.
OP21
OP20
0
0
Pin OPT2 outputs “L” level.
0
1
Pin OPT2 outputs the output of the PPG
timer.
1
0
Pin OPT2 outputs the inverted output of
the PPG timer.
1
1
Pin OPT2 outputs “H” level.
OP31
OP30
0
0
Pin OPT3 outputs “L” level.
0
1
Pin OPT3 outputs the output of the PPG
timer.
1
0
Pin OPT3 outputs the inverted output of
the PPG timer.
1
1
Pin OPT3 outputs “H” level.
OPT1 output waveform selection bits
OPT2 output waveform selection bits
OPT3 output waveform selection bits
CHAPTER 15 MULTI-PULSE GENERATOR
Table 15.4-4 Output Data Lower Register (OPDR) Bits
Bit name
Function
bit7,
bit6
OP31, OP30:
OPT3 output
waveform
selection bits
• These bits are used to select the kind of the output waveform to the OPT3 pin.
bit5,
bit4
OP21, OP20:
OPT2 output
waveform
selection bits
• These bits are used to select the kind of the output waveform to the OPT2 pin.
bit3,
bit2
OP11, OP10:
OPT1 output
waveform
selection bits
• These bits are used to select the kind of the output waveform to the OPT1 pin.
bit1,
bit0
OP01, OP00:
OPT0 output
waveform
selection bits
• These bits are used to select the kind of the output waveform to the OPT0 pin.
379
CHAPTER 15 MULTI-PULSE GENERATOR
15.4.3
Output Data Buffer Register (OPDBR)
The Output Data Buffer Register is composed of twelve registers (OPDBRB to
OPDBR0). The value of the OPDBRx register specified by the BNKF, RDA2 to RDA0 bits
is loaded into the OPDR register at the rising edge of the write signal generated by the
Data Write Control Unit.
■ Output Data Buffer Upper Register (OPDBR)
Figure 15.4-6 Output Data Buffer Upper Register (OPDBR)
Address bit 15
14
13
12
11
10
9
8
Initial value
003FF7H
BNKF
to 003FE1H
RDA2
RDA1
RDA0
OP51
OP50
OP41
OP40
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OP41 OP40
0
Setting for OPT4 pin to output “L” level.
0
1
Setting for OPT4 pin to output the output of
the PPG timer.
1
0
Setting for OPT4 pin to output the inverted
output of the PPG timer.
1
1
Setting for OPT4 pin to output “H” level.
OP51 OP50
0
: Indeterminate
R/W : Readable and writable
Setting for OPT5 pin to output “L” level.
0
1
Setting for OPT5 pin to output the output of
the PPG timer.
1
0
Setting for OPT5 pin to output the inverted
output of the PPG timer.
1
1
Setting for OPT5 pin to output “H” level.
380
: Not used
OPDBR register selection bits
0
0
0
0
Set OPDBR0 as next to be loaded to OPDR.
0
0
0
1
Set OPDBR1 as next to be loaded to OPDR.
0
0
1
0
Set OPDBR2 as next to be loaded to OPDR.
0
0
1
1
Set OPDBR3 as next to be loaded to OPDR.
0
1
0
0
Set OPDBR4 as next to be loaded to OPDR.
0
1
0
1
Set OPDBR5 as next to be loaded to OPDR.
0
1
1
0
Set OPDBR6 as next to be loaded to OPDR.
0
1
1
1
Set OPDBR7 as next to be loaded to OPDR.
1
0
0
0
Set OPDBR8 as next to be loaded to OPDR.
1
0
0
1
Set OPDBR9 as next to be loaded to OPDR.
1
0
1
0
Set OPDBRA as next to be loaded to OPDR.
1
0
1
1
Set OPDBRB as next to be loaded to OPDR.
: Initial value
—
OPT5 output waveform selection bits
0
BNKF RDA2 RDA1 RDA0
X
OPT4 output waveform selection bits
0
Other values
Prohibited.
CHAPTER 15 MULTI-PULSE GENERATOR
Table 15.4-5 Output Data Buffer Upper Register (OPDBR) Bits
Bit name
Function
bit15
to
bit12
BNKF, RDA2 to
RDA0:
OPDBR register
selection bits
• These bits indicate the addresses of the OPDBR registers and decide which
Output Data Buffer Register value is loaded into the OPDR register after it is
loaded into the OPDR register.
bit11,
bit10
OP51, OP50:
OPT5 output
waveform
selection bits
• These bits are used to select the kind of the output waveform to the OPT5 pin after
it is loaded into the OPDR register.
bit9,
bit8
OP41, OP40:
OPT4 output
waveform
selection bits
• These bits are used to select the kind of the output waveform to the OPT4 pin after
it is loaded into the OPDR register.
381
CHAPTER 15 MULTI-PULSE GENERATOR
■ Output Data Buffer Lower Register (OPDBR)
Figure 15.4-7 Output Data Buffer Lower Register (OPDBR)
Address bit 7
6
5
4
3
2
1
0
Initial value
003FF6H
OP31
to 003FE0H
OP30
OP21
OP20
OP11
OP10
OP01
OP00
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
: Indeterminate
R/W : Readable and writable
: Initial value
—
382
: Not used
OP01
OP00
0
0
Setting for OPT0 pin to output “L” level.
OPT0 output waveform selection bits
0
1
Setting for OPT0 pin to output the output
of the PPG timer.
1
0
Setting for OPT0 pin to output the
inverted output of the PPG timer.
1
1
Setting for OPT0 pin to output “H” level.
OP11
OP10
OPT1 output waveform selection bits
0
0
Setting for OPT1 pin to output “L” level.
0
1
Setting for OPT1 pin to output the output
of the PPG timer.
1
0
Setting for OPT1 pin to output the
inverted output of the PPG timer.
1
1
Setting for OPT1 pin to output “H” level.
OP21
OP20
OPT2 output waveform selection bits
0
0
Setting for OPT2 pin to output “L” level.
0
1
Setting for OPT2 pin to output the output
of the PPG timer.
1
0
Setting for OPT2 pin to output the
inverted output of the PPG timer.
1
1
Setting for OPT2 pin to output “H” level.
OP31
OP30
OPT3 output waveform selection bits
0
0
Setting for OPT3 pin to output “L” level.
0
1
Setting for OPT3 pin to output the output
of the PPG timer.
1
0
Setting for OPT3 pin to output the
inverted output of the PPG timer.
1
1
Setting for OPT3 pin to output “H” level.
CHAPTER 15 MULTI-PULSE GENERATOR
Table 15.4-6 Output Data Buffer Lower Register (OPDBR) Bits
Bit name
Function
bit7,
bit6
OP31, OP30:
OPT3 output
waveform
selection bits
• These bits are used to select the kind of the output waveform to the OPT3 pin after it
is loaded into the OPDR register.
bit5,
bit4
OP21, OP20:
OPT2 output
waveform
selection bits
• These bits are used to select the kind of the output waveform to the OPT2 pin after it
is loaded into the OPDR register.
bit3,
bit2
OP11, OP10:
OPT1 output
waveform
selection bits
• These bits are used to select the kind of the output waveform to the OPT1 pin after it
is loaded into the OPDR register.
bit1,
bit0
OP01, OP00:
OPT0 output
waveform
selection bits
• These bits are used to select the kind of the output waveform to the OPT0 pin after it
is loaded into the OPDR register.
383
CHAPTER 15 MULTI-PULSE GENERATOR
15.4.4
Input Control Register (IPCR)
The Input Control Register (IPCR) is a register which sets the control of the position
detection inputs.
■ Input Control Upper Register (IPCUR)
Figure 15.4-8 Input Control Upper Register (IPCUR)
Address bit 15
00008DH
14
13
12
11
10
9
8
Initial value
WTS1
WTS0
CPIF
CPIE
CPD2
CPD1
CPD0
CMPE
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CMPE
Position detection comparison enable bit
0
Disable comparison operation. (Initial value)
1
Enable comparison operation.
CPD2 CPD1 CPD0
Comparsion bits
0
0
0
Compare match if RDA2 to RDA0 = 000.
0
0
1
Compare match if RDA2 to RDA0 = 001.
0
1
0
Compare match if RDA2 to RDA0 = 010.
0
1
1
Compare match if RDA2 to RDA0 = 011.
1
0
0
Compare match if RDA2 to RDA0 = 100.
1
0
1
Compare match if RDA2 to RDA0 = 101.
1
1
0
Compare match if RDA2 to RDA0 = 110.
1
1
1
Compare match if RDA2 to RDA0 = 111.
CPIE
Comparison interrupt request enable bit
0
Disable interrupt. (Initial value)
1
Enable interrupt.
Comparison interrupt request flag bit
CPIF
X
: Indeterminate
R/W : Readable and writable
: Initial value
—
384
: Not used
Read
Write
0
No valid detected.
Clear this bit.
1
Valid detected.
No effect.
WTS1
WTS0
Write timing and PPG synchronization selection bits
0
0
No synchronization. (Initial value)
0
1
Rising edge synchronization. ↑
1
0
Falling edge synchronization. ↓
1
1
Both edges synchronization. ↑ & ↓
CHAPTER 15 MULTI-PULSE GENERATOR
Table 15.4-7 Input Control Upper Register (IPCUR) Bits
Bit name
Function
WTS1, WTS0:
PPG edge
synchronization
selection bits
• These bits are used to select the synchronization edge of the next coming of PPG
signal with the write timing.
bit13
CPIF:
Comparison
interrupt request
flag bit
• Comparison interrupt request flag.
• It is a comparison interrupt request flag for the comparison circuit. When the
SNI2 to SNI0 bits are compared and matched with the CPD2 to CPD0 bits, this
bit is set to “1”.
• When comparison interrupt enable bit (CPIE) is also set to “1”, the interrupt is
generated.
• This bit is cleared by writing “0”. Writing “1” has no effect.
• In read-modify-write operation, “1’ is always read.
bit12
CPIE:
Comparison
interrupt request
enable bit
• Comparison interrupt enable bit.
• When this bit is set to “1” and the comparison interrupt request flag (CPIF) is
also set to “1”, the interrupt is generated.
bit11
to
bit9
CPD2 to CPD0:
Comparison
bits
• These bits are used to compare with the RDA2 to RDA0 bits of the Output Data
Register, when the value of these bits are matched with the value of RDA2 to
RDA0 bits, the compare interrupt flag (CPIF) is set to “1”.
bit8
CMPE:
Position
detection
comparison
enable bit
• This bit is used to enable the comparison operation for the position detection.
bit15,
bit14
385
CHAPTER 15 MULTI-PULSE GENERATOR
■ Input Control Lower Register (IPCLR)
Figure 15.4-9 Input Control Lower Register (IPCLR)
Address bit 7
00008CH
6
5
4
3
2
1
0
Initial value
CPE1
CPE0
SNC2
SNC1
SNC0
SEE2
SEE1
SEE0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SEE0
SNI0 enable bit
0
Disable SNI0 edge detection. (Initial value)
1
Enable SNI0 edge detection.
SEE1
SNI1 enable bit
0
Disable SNI1 edge detection. (Initial value)
1
Enable SNI1 edge detection.
SEE2
SNI2 enable bit
0
Disable SNI2 edge detection. (Initial value)
1
Enable SNI2 edge detection.
SNC0
Noise filter enable bit for SNI0
0
SNI0 input do not go through the noise
cancellation circuit.
1
SNI0 input goes through the noise cancellation
circuit.
SNC1
Noise filter enable bit for SNI1
0
SNI1 input do not go through the noise
cancellation circuit.
1
SNI1 input goes through the noise cancellation
circuit.
SNC2
X
: Indeterminate
Noise filter enable bit for SNI2
0
SNI2 input do not go through the noise
cancellation circuit.
1
SNI2 input goes through the noise cancellation
circuit.
CPE1
CPE0
Edge selection bits
0
0
No edge detection. (stopped state)
(Initial value)
0
1
Rising edge detection. ↑
1
0
Falling edge detection. ↓
1
1
Both edges detection. ↑ & ↓
R/W : Readable and writable
: Initial value
—
386
: Not used
CHAPTER 15 MULTI-PULSE GENERATOR
Table 15.4-8 Input Control Lower Register (IPCLR) Bits
Bit name
Function
CPE1, CPE0:
Input polarity
selection bits
• Input polarity selection bits.
• These bits are used to select the polarity of the input edge for the position detection,
the position detection operates according to the input edge polarity set to these bits.
bit5
to
bit3
SNC2 to
SNC0:
Noise filter
enable bits for
SNI2 to SNI0
• These bits are used to select the noise cancellation function when the inputs of the
pins SNI2 to SNI0 are enable.
• The noise cancellation circuit starts the internal n-bit counter when an active level is
inputted (the value of n can be 2, 3, 4, 5, which depends on the setting of S21,S20,
S11,S10 and S01,S00 bits in the Noise Cancellation Register). If the active level is
held until the counter overflows, the circuit accepts input from the SNI2 to SNI0
pins. Therefore, the pulse width of noise that can be cancelled is about 2n machine
cycles.
(Note)
When the noise cancellation circuit is enable, the input becomes invalid in a mode
such as STOP mode in which the internal clock is stopped.
bit2
to
bit0
SEE2 to SEE0:
SNI2 to SNI0
enable bits
• Pins SNI2 to SNI0 edge detection enable bits.
• When they are set to “1”, the edge detection of the pins SNI2 to SNI0 are enable.
• Please set these bits before setting CMPE to “1”.
bit7,
bit6
387
CHAPTER 15 MULTI-PULSE GENERATOR
15.4.5
Compare Clear Register (CPCR)
The Compare Clear Register (CPCR) is 16-bit register. When this register is matched
with the count value of 16-bit timer, the 16-bit timer is reset to "0000H".
■ Compare Clear Register (CPCR)
Compare Clear Register is a 16-bit register and is used to compare the count value of the 16-bit timer. The
initial value of this register is undetermined, so that the register must be set a value before starting an
operation.
Notes:
Word access instruction to this register must be used.
When this register is matched with the count value of 16-bit timer, 16-bit timer is reset to "0000H"
and the compare clear interrupt flag is set. Furthermore, when the interrupt operation is enabled,
interrupt request is sent to the CPU.
If the Compare Clear Register (CPCR) is loaded a value same as the Timer Counter value at that
moment, the comparison operation will NOT be performed until next same counter value.
Figure 15.4-10 Compare Clear Register (CPCR)
Compare Clear Register (Upper)
bit 15
Address: 003FFBH
Read/write
Initial value
14
13
12
11
10
9
8
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
5
4
3
2
1
0
CPCR
Compare Clear Register (Lower)
bit
Address: 003FFAH
Read/write
Initial value
388
7
6
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
CPCR
CHAPTER 15 MULTI-PULSE GENERATOR
15.4.6
Timer Buffer Register (TMBR)
The Timer Buffer Register (TMBR) is used to read the count value of 16-bit timer.
■ Timer Buffer Register (TMBR)
The timer buffer register is used to store the count value of the 16-bit timer at the moment when a write
timing or position detection trigger is generated, and the counter is then cleared to "0000H".
Note:
Word access instruction to the Timer Buffer Register must be used.
Figure 15.4-11 Timer Buffer Register (TMBR)
Timer Buffer Register (Upper)
bit
Address: 003FFDH
Read/write
Initial value
15
14
13
12
11
10
T15
T14
T13
T12
T11
T10
R
0
R
0
R
0
R
0
R
0
R
0
3
9
8
T09
T08
R
0
TMBR
R
0
Timer Buffer Register (Lower)
bit
Address: 003FFCH
Read/write
Initial value
7
6
5
4
T07
T06
T05
T04
R
0
R
0
R
0
R
0
2
1
0
T03
T02
T01
T00
R
0
R
0
R
0
R
0
TMBR
389
CHAPTER 15 MULTI-PULSE GENERATOR
15.4.7
Timer Control Status Register (TCSR)
The Timer Control Status Register (TCSR) is used to control the operation of the 16-bit
timer.
■ Timer Control Status Register (TCSR)
Figure 15.4-12 Timer Control Status Register (TCSR)
Address bit
00008EH
7
6
5
4
3
2
1
0
Initial value
TCLR
MODE
ICLR
ICRE
TMEN
CLK2
CLK1
CLK0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock frequency selection bit
CLK2 CLK1 CLK0
0
0
Count
clock
φ = 16 MHz
φ = 8 MHz
φ = 4 MHz
φ = 1 MHz
0
φ
62.5 ns
125 ns
0.25 µs
1 µs
0
0
1
φ/2
125 ns
0.25 µs
0.5 µs
2 µs
0
1
0
φ/4
0.25 µs
0.5 µs
1 µs
4 µs
0
1
1
φ/8
0.5 µs
1 µs
2 µs
8 µs
1
0
0
φ/16
1 µs
2 µs
4 µs
16 µs
1
0
1
φ/32
2 µs
4 µs
8 µs
32 µs
1
1
0
φ/64
4 µs
8 µs
16 µs
64 µs
1
1
1
φ/128
8 µs
16 µs
32 µs
128 µs
φ: Machine cycle
TMEN
Timer enable bit
0
Counting is disabled. (Initial value)
1
Counting is enabled.
ICRE
Compare clear interrupt request enable bit
0
Interrupt is disabled.
1
Interrupt is enabled.
Compare clear interrupt request flag bit
ICLR
Read
Write
0
No interrupt request.
Clear this bit.
1
Has interrupt request.
No effect.
MODE
Counter reset condition bit
0
Reset counter by write timing trigger.
1
Reset counter by position detection trigger.
Timer clear bit
TCLR
X
: Initial value
—
390
Read
: Indeterminate
R/W : Readable and writable
: Not used
0
Always read as “0”.
1
Write
No effect.
Initialize counter to “0000H”.
CHAPTER 15 MULTI-PULSE GENERATOR
Table 15.4-9 Timer Control Status Register (TCSR)
Bit name
Function
bit7
TCLR:
Timer clear bit
• The read value is always “0”.
• Writing “1” to this bit initialize the counter to “0000H”.
• Writing “0” has no effect.
bit6
MODE:
Timer reset
condition bit
• This bit is used to set the reset condition for the 16-bit timer.
• When it is “0”, 16-bit timer is reset by the write timing signal.
• When it is “1”, 16-bit timer is reset by the position detection signal.
(Note)
Reset of the counter value is done at the changing point of the count value.
bit5
ICLR:
Compare clear
interrupt request
flag bit
• This bit is an interrupt request flag for compare clear.
• When the compare clear register and 16-bit free-run timer value are matched, the
counter is cleared and this bit becomes “1”.
• Interrupt is generated when the interrupt request enable bit (bit12: ICRE) is set to
“1”.
• Writing “0” clears this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
bit4
ICRE:
Compare clear
interrupt request
enable bit
• This is the interrupt request enable bit for the compare clear.
• When this bit is “1” and the interrupt flag (bit13: ICLR) is set to “1”, an interrupt
is generated.
bit3
TMEN:
Timer enable bit
• This bit is used to enable/disable the counting of the 16-bit timer.
• Writing “1” to this bit enables the counting of the 16-bit timer.
• Writing “0” to this bit disables the counting of the 16-bit timer.
(Note)
When the 16-bit timer is disable, the output compare operation is also disabled.
bit2
to
bit0
CLK2 to CLK0:
Clock frequency
selection bit
• These bits are used to select count clock for the 16-bit free-run timer.
(Note)
It is recommend to change these bits when the timer is in stop state because the
clock is changed as soon as these bits are updated.
391
CHAPTER 15 MULTI-PULSE GENERATOR
15.4.8
Noise Cancellation Control Register (NCCR)
The Noise Cancellation Control Register (NCCR) is used to control the noise pulse
width to be cancelled for DTTI1 and SNIx pins.
■ Noise Cancellation Control Register (NCCR)
Figure 15.4-13 Noise Cancellation Control Register (NCCR)
Address bit 7
00008FH
X
6
5
4
3
2
1
0
Initial value
S21
S20
S11
S10
S01
S00
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Indeterminate
R/W : Readable and writable
: Initial value
—
392
: Not used
D1
D0
DTTI1 noise width selection bit
0
0
Cancel 4-cycle noise.
0
1
Cancel 8-cycle noise.
1
0
Cancel 16-cycle noise.
1
1
Cancel 32-cycle noise.
S01
S00
SNI0 noise width selection bit
0
0
Cancel 4-cycle noise.
0
1
Cancel 8-cycle noise.
1
0
Cancel 16-cycle noise.
1
1
Cancel 32-cycle noise.
S11
S10
SNI1 noise width selection bit
0
0
Cancel 4-cycle noise.
0
1
Cancel 8-cycle noise.
1
0
Cancel 16-cycle noise.
1
1
Cancel 32-cycle noise.
S21
S20
SNI2 noise width selection bit
0
0
Cancel 4-cycle noise.
0
1
Cancel 8-cycle noise.
1
0
Cancel 16-cycle noise.
1
1
Cancel 32-cycle noise.
CHAPTER 15 MULTI-PULSE GENERATOR
Table 15.4-10 Noise Cancellation Control Register (NCCR) Bits
Bit name
Function
bit7,
bit6
S21,S20:
Noise width
selection bits
• These bits are used to specify the noise pulse width to be removed for SNI2 pin.
bit5,
bit4
S11,S10:
Noise width
selection bits
• These bits are used to specify the noise pulse width to be removed for SNI1 pin.
bit3,
bit2
S01,S00:
Noise width
selection bits
• These bits are used to specify the noise pulse width to be removed for SNI0 pin.
bit1,
bit0
D1,D0:
Noise width
selection bits
• These bits are used to specify the noise pulse width to be removed for DTTI1 pin.
393
CHAPTER 15 MULTI-PULSE GENERATOR
15.5
Multi-pulse Generator Interrupts
The Multi-pulse Generator can generate an interrupt request when in the following
causes:
• Write timing output is generated by the Data Write Control Unit
• Any valid position detection input is detected
• Comparison match between CPD2 to CPD0 of Input Control Register (IPCR: CPD2 to
CPD0) and RDA2 to RDA0 bit of Output Data Register (OPDR: RDA2 to RDA0)
• Compare Clear is generated by the 16-bit Timer
• DTTI1 is changed to low signal level
■ Multi-pulse Interrupts
There are five interrupt causes generated from Multi-pulse Generator, that are as follows:
• Write Timing Interrupt
• Compare Clear Interrupt
• Position Detect Interrupt
• Compare Match Interrupt
• DTTI1 Interrupt
Write Timing Interrupt is multiplexed with Compare Clear Interrupt and Position Detect Interrupt is
multiplexed with Compare Match Interrupt.
● Write Timing Interrupt
If the WTIE bit of the Output Control Register (OPCR: WTIE) is set to "1", this Write Timing Interrupt is
generated when the write timing is generated by the Data Write Control Circuit to make data transfer from
one of 12 Output Data Buffer Registers (OPDBRB to OPDBR0) to the Output Data Register (OPDR).
When this interrupt is generated, the write timing interrupt flag bit of the Output Control Register (OPCR:
WTIF) is set to "1".
● Compare Clear Interrupt
If the ICRE bit of the Timer Control Register (TCSR: ICRE) is set to "1", this Compare Clear Interrupt is
generated when the 16-bit Timer is underflow.
When this interrupt is generated, the Compare Clear interrupt flag bit of the Timer Control Register (TCSR:
ICLR) is set to "1".
394
CHAPTER 15 MULTI-PULSE GENERATOR
● Position Detect Timing Interrupt
If the PDIE bit of the Output Control Register (OPCR: PDIE) is set to "1", this Position Detect Interrupt is
generated when the write timing is output by Position Detect Circuit to make data transfer from one of 12
Output Data Buffer Registers (OPDBRB to OPDBR0) to the Output Data Register (OPDR). This write
timing output can be generated by either the compare match of the level of the position input (SNI2 to
SNI0) with RDA2 to RDA0 bits of the Output Data Register (OPDR: RDA2 to RDA0), or a edge detected
of the position input (SNI2 to SNI0) with one of 3 different kinds of edge setting.
When this interrupt is generated, the position detect interrupt flag bit of the Output Control Register
(OPCR: PDIF) is set to "1".
● Compare Match Interrupt
If the CPIE bit of the Input Control Register (IPCR: CPIE) is set to "1", this Compare Match Interrupt is
generated when the RDA2 to RDA0 bits of the Output Data Register (OPDR: RDA2 to RDA0) are
matched with the CPD2 to CPD0 bits of the Input Control Register (IPCR: CPD2 to CPD0).
When this interrupt is generated, the Compare match interrupt flag bit of the Input Control Register (IPCR:
CPIF) is set to "1".
● DTTI1 Interrupt
If the DTIE bit of the Output Control Register (OPCR: DTIE) is set to "1", this DTTI1 Interrupt is
generated whenever a low input is detected at the DTTI1 pin.
When this interrupt is generated, the DTTI1 interrupt flag bit of the Output Control Register (OPCR: DTIF)
is set to "1".
■ Multi-pulse Generator Interrupt Source
INTERRUPT #22:This interrupt is generated when a DTTI1 interrupt is happened.
DTTI1 interrupt is generated if OPCR: DTIE is set to "1" when a low level input
is detected at the DTTI1 pin.
INTERRUPT #26:This interrupt is generated when either a Write Timing interrupt or Compare
Clear interrupt is happened.
Write timing interrupt is generated if OPCR: WTIE is set to "1" when a write timing
signal is generated from the Data Write Control Circuit.
Compare clear interrupt is generated if TCSR: ICRE is set to "1" when the count value of
16-bit timer matches with the Compare clear register (CPCR).
INTERRUPT #28:This interrupt is generated when either a Position Detect interrupt or Compare
Match interrupt is happened.
Position detect interrupt is generated if OPCR: PDIE is set to "1" when an effective edge
at SNI2 to SNI0 is detected.
Compare match interrupt is generated if IPCR: CPIE is set to "1" when the SNI2 to SNI0
inputs match with the RDA2 to RDA0 bits of the Output Data Register (OPDR).
395
CHAPTER 15 MULTI-PULSE GENERATOR
■ Multi-pulse Generator Interrupts and EI2OS
Table 15.5-1 Multi-pulse Generator Interrupts and EI2OS
Interrupt control register
Interrupt cause
Interrupt
number
Vector table address
EI2OS
Register
name
Address
Lower
Upper
Bank
DTTI1
#22 (16H)
ICR05
0000B5H
FFFFACH
FFFFADH
FFFFAEH
×
Write Timing or
Compare Clear
#26(1AH)
ICR07
0000B7H
FFFF94H
FFFF95H
FFFF96H
❍
Position Detect or
Compare Match
#28 (1CH)
ICR08
0000B8H
FFFF8CH
FFFF8DH
FFFF8EH
❍
❍ : Support EI2OS
■ Multi-pulse Generator EI2OS Functions
Multi-pulse Generator has a circuit for operating EI2OS, which can be started up when either Write Timing/
Compare Clear interrupt or Position Detect/Compare Match interrupt is generated.
However, EI2OS is available only when other peripheral functions sharing the interrupt control register
(ICR) do not use interrupts. For example, when Write Timing/Compare Clear interrupt is used to trigger
EI2OS, DTP/external interrupt channels 4/5 detection must be disabled.
396
CHAPTER 15 MULTI-PULSE GENERATOR
15.6
Operation of Multi-pulse Generator
The operation of the Multi-pulse Generator will be described in the following sections.
According to the setting of (OPx1/OPx0) bits in the Output Data Register (OPDR), the
OPTx pin outputs the corresponding kind of waveforms ("H" or "L" or PPG output). See
Table 15.6-1.
■ Output Data Register Block Diagram
Figure 15.6-1 Output Data Register Block Diagram
POSITION DETECT CIRCUIT
16-BIT PPG TIMER 1
OUTPUT CONTROL CIRCUIT
OUTPUT DATA REGISTER
OP51/OP50
OP41/OP40
OP31/OP30
OP21/OP20
OP11/OP10
OP01/OP00
OPT5
OPT4
OPT3
OPT2
OPT1
OPT0
DTTI1
DECODER
OUTPUT DATA BUFFER REGISTER x 12
DATA WRITE CONTROL UNIT
16-BIT RELOAD TIMER 0
BNKF/RDA2
RDA1/RDA0
397
CHAPTER 15 MULTI-PULSE GENERATOR
■ Output Data Register (OPDR)
The content of the Output Data Register (OPDR) is received from the Output Data Buffer Register
(OPDBRB to OPDBR0) according to the write timing signal (WTO) generated by the Data Write Control
Unit, and the OPTx output waveform is updated. Moreover, the output level can be compulsorily fixed by
the DTTI1 pin input.
Table 15.6-1 Output Data Register (OPDR)
OPx1,OPx0 Setting
OPTx Output
OPx1,OPx0 = 0,0
Low Level
OPx1,OPx0 = 0,1
16-bit PPG Timer Output
OPx1,OPx0 = 1,0
16-bit PPG Timer Inverted Output
OPx1,OPx0 = 1,1
High Level
The OPTx output waveform timing diagram is shown in Figure 15.6-2 and the operation is explained in
following paragraphs.
■ OPTx Output Waveform Timing Diagram (WTS1,WTS0 = 00B)
Figure 15.6-2 OPTx Output Waveform Timing Diagram (WTS1,WTS0 = 00B)
WTO
OPx1,
OPx0
(OPDR)
00
01
11
10
PPG
OPTx
L Output
398
PPG Output
H Output
PPG Inverted Output
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.1
Operation of Position Detection
This section describes the operation of the Position Detection Circuit. When the
effective position is detected, a Data Write Timing Output (WTIN1) will be generated to
the Data Write Control Unit and a Position Detect Interrupt is generated if the OPCR:
PDIE is set to "1".
■ Operation of Position Detection
The WTIN1 signal is generated by the Position Detection Circuit under the following conditions:
• A comparison match between SNI2 to SNI0 and RDA2 to RDA0, which is triggered by any effective
edge of SNI2 to SNI0.
• A detection of effective edge at SNIx which is enabled by the corresponding SEEx bit.
When the CMPE bit (bit8) of the Input Control Register (IPCR) is set to "0", only the edge detection of
SINx pins enabled by the SEE2 to SEE0 bits will engage in the edge detection operation for the position
detection. For instance, when only the SEE0 bit is set to "1", the input edge to the pin SNI0 is in effect, the
data write output signal is generated only when an effective edge is detected at the SIN0 pin. See Figure
15.6-3 for the timing diagram of the edge detection when CMPE = 0.
When the CMPE bit (bit8) of the Input Control Register (IPCR) is set to "1", the SNI2 to SNI0 will be
engaged in the comparison operation with the RDA2 to RDA0 bits. The comparison is triggered by any
edge change at SNI2 to SNI0 pins. See Figure 15.6-4 for the timing diagram of the edge detection when
CMPE = 1.
■ Edge Detection Timing Diagram (CMPE = 0)
Figure 15.6-3 Edge Detection Timing Diagram (CMPE = 0)
CMPE
CPE1,
CPE0
01
10
11
SNI2
SNI1
SNI0
WTIN1
RISING EDGE
DETECTION
FALLING EDGE
DETECTION
BOTH EDGES
DETECTION
399
CHAPTER 15 MULTI-PULSE GENERATOR
■ Both Edges Detection and SNIx/RDAx Comparison Timing Diagram (CMPE = 1)
Figure 15.6-4 Both Edges Detection and SNIx/RDAx Comparison Timing Diagram (CMPE = 1)
CMPE
CPE1,
CPE0
RDA2 to
RDA0
(OPDR)
11
110
010
001
SNI2
SNI1
SNI0
WTIN1
COMPARISON
MATCH
COMPARISON
MATCH
COMPARISON
MATCH
■ WTIN1 Output Condition and Register Setting
Table 15.6-2 WTIN1 Output Condition and Register Setting
CMPE
CPE1
CPE0
SEEx
0
0
0
0
No output. (Initial value)
0
X
X
0
No output.
0
0
0
1
No output.
0
0
1
1
Detect SNIx rising edge.
0
1
0
1
Detect SNIx falling edge.
0
1
1
1
Detect SNIx both edges.
1
0
0
X
Prohibited.
1
0
1
X
Detect SNIx rising edge and SNIx/RDAx comparison match.
1
1
0
X
Detect SNIx falling edge and SNIx/RDAx comparison match.
1
1
1
X
Detect SNIx both edges and SNIx/RDAx comparison match.
Note:
400
WTIN1 Output Condition
When CMPE = 1, SEEx should be set to "0", setting SEEx = 1 is not recommended.
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.2
Operation of Data Write Control Unit
The Data Write Control Unit is used to generate the write timing output (WTO) for
transferring data from the Output Data Buffer Register (OPDBR) to Output Data Register
(OPDR).
■ Operation of Data Write Control Unit
The Write Timing Output (WTO) can be generated by the following condition:
• After OPDBR0 is written by software.
• Triggered by the 16-bit reload timer 0 underflow.
• Triggered by the 16-bit reload timer 0 underflow. The 16-bit timer is started by the position detection
comparison circuit.
• Triggered by the position detection input (SNI2 to SNI0) (16-bit Reload timer 0 acts as a delay).
• Triggered either by the 16-bit reload timer 0 underflow, or by the position detection input.
At the mean time the cause of generation of WTO will be defined by setting different value of OPS2 to
OPS0 bit of the Output Control Register (OPCR: OPS2 to OPS0).
■ Signal Flow Diagram for OPDBR0 by Setting OPS2 to OPS0 = 000B
Figure 15.6-5 Signal Flow Diagram for OPDBR0 (OPS2 to OPS0 = 000B)
TIN
TIN0O
TIN0
Pin TIN0
WTO
WRITE
TIMING
OUTPUT
16-BIT RELOAD TIMER 0
TOUT
OPDBR0 WRITE SIGNAL
SNI2 to Pin
SNI0
POSITION
DETECTION
WTIN0
OPDBR0W
WTIN1
DATA WRITE CONTROL UNIT
The write timing output signal is generated from the Data Write Control Unit whenever a value is written to
the OPDBR0 register, and the data in OPDBR0 is transferred to OPDR register one cycle later.
401
CHAPTER 15 MULTI-PULSE GENERATOR
■ OPDR Register Write Timing Diagram (OPS2 to OPS0 = 000B)
Figure 15.6-6 OPDR Register Write Timing Diagram (OPS2 to OPS0 = 000B)
000
OPS2 to OPS0
RDA2 to RDA0
(OPDR)
101
001
OPDBR0W
OPDBR1W
OPDBR0[0]
OPDBR1[0]
WTO
OP00
■ Signal Flow Diagram for Reload Timer 0 Underflow by Setting OPS2 to OPS0 = 001B
Figure 15.6-7 Signal Flow Diagram for Reload Timer 0 Underflow (OPS2 to OPS0 = 001B)
TIN
TIN0O
TIN0
Pin TIN0
WTO
WRITE
TIMING
OUTPUT
16-BIT RELOAD TIMER 0
TOUT
OPDBR0 WRITE SIGNAL
SNI2 to Pin
SNI0
POSITION
DETECTION
WTIN0
OPDBR0W
WTIN1
DATA WRITE CONTROL UNIT
The 16-bit reload timer 0 can be triggered by both TIN input and software to generate the write signal at
this setting. The write signal is controlled by the 16-bit reload timer 0 underflow.
402
CHAPTER 15 MULTI-PULSE GENERATOR
■ Signal Flow Diagram for Position Detection by Setting OPS2 to OPS0 = 010B or 110B
Figure 15.6-8 Signal Flow Diagram for Position Detection (OPS2 to OPS0 = 010B or 110B)
TIN
TIN0O
TIN0
Pin TIN0
WTO
WRITE
TIMING
OUTPUT
16-BIT RELOAD TIMER 0
TOUT
OPDBR0 WRITE SIGNAL
SNI2 to
SNI0
Pin
POSITION
DETECTION
WTIN0
OPDBR0W
WTIN1
DATA WRITE CONTROL UNIT
The write signal is generated by a comparison match or effective edge input of position detection.
■ Signal Flow Diagram for Reload Timer 0 and Position Detection by Setting OPS2 to
OPS0 = 011B or 111B
Figure 15.6-9 Signal Flow Diagram for Reload Timer 0 & Position Detect (OPS2 to OPS0 = 011B or 111B)
TIN
TIN0O
TIN0
Pin TIN0
WTO
WRITE
TIMING
OUTPUT
16-BIT RELOAD TIMER 0
TOUT
OPDBR0 WRITE SIGNAL
SNI2 to
SNI0
Pin
POSITION
DETECTION
WTIN0
OPDBR0W
WTIN1
DATA WRITE CONTROL UNIT
At this setting the16-bit reload timer 0 is started by the compare match or effective edge input of the
position detection circuit, write signal is then generated whenever the 16-bit reload timer 0 is underflow.
The compare match is triggered by any effective edge change in SNI2 to SNI0 pins.
403
CHAPTER 15 MULTI-PULSE GENERATOR
■ Signal Flow Diagram for Reload Timer 0 or Position Detection by Setting OPS2 to
OPS0 = 100B or 101B
Figure 15.6-10 Signal Flow Diagram for Reload Timer 0 or Position Detect (OPS2 to OPS0 = 100B or 101B)
TIN
TIN0O
TIN0
Pin TIN0
WTO
WRITE
TIMING
OUTPUT
16-BIT RELOAD TIMER 0
TOUT
OPDBR0 WRITE SIGNAL
SNI2 to
SNI0
POSITION
DETECTION
Pin
WTIN0
OPDBR0W
WTIN1
DATA WRITE CONTROL UNIT
At this setting the write signal is generated by the compare match or effective edge input of the position
detection or whenever the 16-bit reload timer 0 is underflow. The compare match is triggered by any
effective edge change in SNI2 to SNI0 pins.
■ OPDR Register Write Timing Diagram
(OPS2 to OPS0 = 001B, 010B, 011B, 100B, 101B, 110B, 111B)
Figure 15.6-11 OPDR Register Write Timing Diagram
(OPS2 to OPS0 = 001B, 010B, 011B, 100B, 101B, 110B, 111B)
OPS2 to OPS0
BNKF,
RDA2 to RDA0
(OPDR)
OPDBR1[0]
OPDBR4[0]
OPDBR7[0]
WTO
OP00
404
001 or 010 or 011 or 100 or 101 or 110 or 111
0001
0100
0111
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.3
Operation of Output Data Buffer Register
The Output Data Buffer Register (OPDBR) is composed of twelve registers. By loading
different OPDBR register into the Output Data Register (OPDR), various kind of
waveform is output at the Multi-pulse Generator Output (OPT5 to OPT0).
■ Operation of Output Data Buffer Register
The data in the Output Data Buffer Register (OPDBR) whose address specified by the BNKF, RDA2 to
RDA0 bits is transferred to the Output Data Register (OPDR) at the write timing generated by the Data
Write Control Unit.
The BNKF, RDA2 to RDA0 bits of the Output Data Buffer Register (OPDBR) decide the order of data
transfer to the Output Data Register (OPDR), and the OPx1/OPx0 bits decide the shape of the output
waveform. The output waveform is updated automatically as long as the write timing (WTO) is generated.
An example of setting the Output Data Buffer Register (OPDBR) is shown in Table 15.6-3.
Table 15.6-3 Output Data Buffer Register (OPDBR)
No.
0
1
2
3
4
5
6
7
8
9
A
BNKF
0
0
0
0
0
1
0
X
X
0
1
RDA2
1
1
0
0
1
0
0
X
X
1
0
RDA1
0
0
1
0
1
1
1
X
X
0
1
RDA0
0
1
1
1
0
0
0
X
X
0
1
OP51
0
0
0
1
0
0
0
X
X
0
0
OP50
0
0
1
1
0
0
0
X
X
0
1
OP41
1
0
0
0
0
1
0
X
X
0
0
OP40
1
1
0
0
0
1
0
X
X
1
0
OP31
0
0
0
0
0
0
1
X
X
0
0
OP30
0
0
0
0
1
0
1
X
X
0
0
OP21
0
0
0
0
1
0
0
X
X
0
0
OP20
1
0
0
0
1
1
0
X
X
0
0
OP11
0
0
1
0
0
0
0
X
X
0
1
OP10
0
0
1
0
0
0
1
X
X
0
1
OP01
0
1
0
0
0
0
0
X
X
1
0
OP00
0
1
0
1
0
0
0
X
X
1
0
OPBDR No. Sequence
4
5
3
1
6
A
2
X
X
4
B
OPT5 Output
L
L
PPG
H
L
L
L
X
X
L
PPG
OPT4 Output
H
PPG
L
L
L
H
L
X
X
PPG
L
OPT3 Output
L
L
L
L
PPG
L
H
X
X
L
L
OPT2 Output
PPG
L
L
L
H
PPG
L
X
X
L
L
OPT1 Output
L
L
H
L
L
L
PPG
X
X
L
H
OPT0 Output
L
H
L
PPG
L
L
L
X
X
H
L
405
CHAPTER 15 MULTI-PULSE GENERATOR
Setting the Output Data Buffer Register 0 (OPDBR0) (No. 0) as shown in Table 15.6-3 initializes the value
of the Output Data Register (OPDR). The following sequence begins to operate according to the write
timing generated:
No. 4 -> No. 6 -> No. 2 -> No. 3 -> No. 1 -> No. 5 -> No. A -> No. B -> No. 9 -> No. 4 and recycle.
The data is transferred to the Output Data Register (OPDR) sequentially. The Output Data Buffer Register
(OPDBR) is not used if it is not set, e.g. No. 7 and No. 8 in Table 15.6-3.
406
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.4
Operation of Data Transfer of Output Data Register
Eight methods can be used to transfer data from the Output Data Buffer Register
(OPDBR) to the Output Data Register (OPDR) automatically, which are described in the
following paragraphs. Each method is selected by setting the OPS2 to OPS0 bits in the
Output Control Register (OPCR).
■ Operation of Data Transfer of Output Data Register
There are eight methods of data transfer from Output Data Buffer Registers (OPDBRB to OPDBR0) to the
Output Data Register (OPDR):
•
•
•
•
•
•
•
•
OPDBR0 Write
16-bit Reload Timer Underflow
Position Detection
Position Detection and 16-bit Reload Timer Underflow
Position Detection or 16-bit Reload Timer Underflow
One-shot Position Detection
One-shot Position Detection and 16-bit Reload Timer Underflow
One-shot Position Detection or 16-bit Reload Timer Underflow
The value of the Output Data Buffer Register (OPDBR) which is selected by the BNKF, RDA2 to RDA0
bits in Output Data Register (OPDR), is transferred to the Output Data Register (OPDR) when the write
signal is generated from the Data Write Control Circuit. However, at the time when OPS2 to OPS0 = 000B,
the value of OPDBR0 is always transferred to the Output Data Register (OPDR) in spite of the value of
BNKF, RDA2 to RDA0 bits. Figure 15.6-2 shows structure between OPDBRB to OPDBR0 registers and
OPDR register.
When the data transfer method is changed, the next Data Buffer Register to be selected is always
specified by the BNKF, RDA2 to RDA0 bits in the Data Output Register. This does not apply to the
OPDBR0 Write method, in OPDBR0 Write method BNKF, RDA2 to RDA0 bits are ignored. Word
access to Output Data Register must be used.
RDA1
RDA0
Figure 15.6-12 Structure between OPDBRB to OPDBR0 and OPDR Registers
OPS2
OPS1
OPS0
BNKF
RDA2
OPDBR0
WTO
Note:
OPDBR1
OPDBR2
OPDBR3
OPDBR4
OPDBR5
OPDBR6
OPDBR7
OPDBR8
12 TO 1 SELECTOR
OPDR
TO OUTPUT
CONTROL
CIRCUIT
OPDBR9
OPDBRA
OPDBRB
407
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.4.1
When OPDBR0 Write
The timing change of the output pin OPTx, which is triggered by the OPDBR0 write, is
shown in Figure 15.6-13.
Note:
Word access to Output Data Buffer Register 0 must be used in this operation, byte
access to either lower register or upper register does not start any transfer operation.
The reload timer 0 is free to be used in this operation mode.
■ Timing Generated by OPDBR0 Write (OPS2 to OPS0 = 000B)
Figure 15.6-13 Timing Generated by OPDBR0 Write (OPS2 to OPS0 = 000B)
RDA2 to
RDA0
(OPDR)
000
001
110
OPDBR0W
OPDBR1W
OPDBR2W
WTO
OP01,
OP00
(OPDR)
PPG
OPT0
408
00
01
11
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.4.2
When 16-bit Reload Timer Underflow
The timing change of the output pin OPTx, which is triggered by the 16-bit reload timer
0 underflow, is shown in Figure 15.6-14 and Figure 15.6-15.
■ Timing Generated by Reload Timer Underflow
Figure 15.6-14 Timing Generated by Reload Timer Underflow
BNKF,
RDA2,
RDA1,
RDA0
No. 0
No. 4
No. 6
No. 2
0100
0110
0010
0011
No. 3
0001
No. 1
No. 5
No. A
0101
1010
1011
OPT5
OPT4
OPT3
OPT2
OPT1
OPT0
TIMER
STARTS
16-BIT RELOAD TIMER 0 UNDERFLOW OCCURS
409
CHAPTER 15 MULTI-PULSE GENERATOR
The data transfer from the Output Data Buffer Register (OPDBR) specified by the BNKF, RDA2 to RDA0
bits to the Output Data Register (OPDR) is updated automatically whenever a 16-bit reload timer 0
underflow is generated as shown in Figure 15.6-15.
In order to use this method, the reload timer should be used in "Reload Mode". Software trigger is needed
to be used for the startup of the reload timer. The 16-bit reload timer 0 is needed for setting the update time
in advance and executing the continuous control action.
■ Timing Generated by Reload Timer Underflow (OPS2 to OPS0 = 001B)
Figure 15.6-15 Timing Generated by Reload Timer Underflow (OPS2 to OPS0 = 001B)
Reload
timer 0
counter
action
RDA2 to
RDA0
(OPDR)
100
110
101
011
001
00
01
11
00
10
WTIN0
(TOUT)
WTO
OP01,
OP00
(OPDR)
PPG
OPT0
410
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.4.3
When Position Detection
The output timing change, which is triggered by the input pin SNIx for the position
detection, is shown in Figure 15.6-16 and Figure 15.6-17.
■ Timing Generated by Position Detection
Figure 15.6-16 Timing Generated by Position Detection
BNKF,
RDA2,
RDA1,
RDA0
No. 0
No. 4
No. 6
No. 2
0100
0110
0010
0011
No. 3
0001
No. 1
No. 5
No. A
0101
1010
1011
OPT5
OPT4
OPT3
OPT2
OPT1
OPT0
WRITE SI GNAL IS GENERATE D WH EN TH ERE IS A COMPARI SON MATCH BETWEEN RDA2 ~ RDA0 AND
SNI 2 ~ SNI 1 OR ANY EFFECTI VE EDGE INPUT AT SI N2 ~ SI N1, THE COMPARSI ON I S TRI GGERED BY
TH E INPUT EDGE POSI TI ON DETECTI ON INPUT TERMI NAL SI Nx.
SNI2
SNI1
SNI0
411
CHAPTER 15 MULTI-PULSE GENERATOR
The comparisons between pin SNI2 and RDA2 bit, pin SNI1 and RDA1 bit, pin SNI0 and RDA0 bit are
done for each position detection.
The OPTx output waveform is updated according to the effective edge input to pin SNIx as shown in
Figure 15.6-17. The data of the Output Data Buffer Register (OPDBR) specified by the BNKF, RDA2 to
RDA0 bits is transferred to the Output Data Register (OPDR), and the output data is renewed automatically
when pins SNI2 to SNI0 are compared with the value of the RDA2 to RDA0 bits and matches.
The reload timer 0 is free to be used in this operation mode.
■ Timing Generated by Position Detection (OPS2 to OPS0 = 010B)
Figure 15.6-17 Timing Generated by Position Detection (OPS2 to OPS0 = 010B)
SNI2
SNI1
SNI0
RDA2 to
RDA0
(OPDR)
100
110
101
011
001
01
11
00
10
WTIN1
WTO
OP01,
OP00
(OPDR)
PPG
OPT0
412
00
11
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.4.4
When Position Detection and Timer Underflow
The output timing change of the operation of the Position Detection and Reload Timer
underflow is shown in Figure 15.6-18 and Figure 15.6-19.
■ Timing Generated by Position Detection and Timer Underflow
Figure 15.6-18 Timing Generated by Position Detection and Timer Underflow
BNKF,
RDA2,
RDA1,
RDA0
No. 0
No. 4
No. 6
No. 2
0100
0110
0010
0011
No. 3
0001
No. 1
No. 5
No. A
0101
1010
1011
OPT5
OPT4
OPT3
OPT2
OPT1
OPT0
WRI TE SI GNAL I S GENERATED BY 16-BI T RELOA D TI MER 0 UNDERFLOW
16-BI T RELOAD T I MER 0 DOWN-COUNTI NG TI ME
SNI2
SNI1
SNI0
413
CHAPTER 15 MULTI-PULSE GENERATOR
The comparison for the position detection is done in pair for each SNIx pin and RDAx bit (SNI2 and
RDA2, SNI1 and RDA1, SNI0 and RDA0), a comparison match starts the 16-bit reload timer 0. The write
signal is generated by the16-bit reload timer 0 underflow.
Pin OPTx output waveform according to the effective edge input to pin SNIx is shown as in Figure 15.619. The 16-bit reload timer 0 is started when the pins SNI2 to SNI0 are compared with the value of the
RDA2 to RDA0 bits and matches. Data transfer from the Output Data Buffer register (OPDBR) specified
by the RDA2 to RDA0 bits to the Output Data Register (OPDR) is triggered by the underflow of the 16-bit
reload timer 0. The operation of output data is renewed automatically.
In order to use this method, the reload timer should be used in " Single Shot Mode". TIN0O must be longer
than two machine cycles.
414
CHAPTER 15 MULTI-PULSE GENERATOR
■ Timing Generated by Position Detection and Timer Underflow (OPS2 to OPS0 = 011B)
Figure 15.6-19 Timing Generated by Position Detection and Timer Underflow (OPS2 to OPS0 = 011B)
SNI2
SNI1
SNI0
TIN0O
(TIN)
Reload
timer 0
counter
action
RDA2 to
RDA0
(OPDR)
100
110
010
011
001
01
11
00
10
WTIN0
(TOUT)
WTO
OP01,
OP00
(OPDR)
00
11
PPG
OPT0
415
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.4.5
When Position Detection or Timer Underflow
The output timing changes of the operation of the Position Detection or Reload Timer
underflow are shown in Figure 15.6-20 and Figure 15.6-21. This operation mode is
selected by setting the OPS2 to OPS0 = 100B.
■ Timing Generated by Position Detection or Timer Underflow
Figure 15.6-20 Timing Generated by Position Detection or Timer Underflow
BNKF,
RDA2,
RDA1,
RDA0
No. 0
No. 4
No. 6
No. 2
0100
0110
0010
0011
No. 3
0001
No. 1
No. 5
No. A
0101
1010
1011
OPT5
OPT4
OPT3
OPT2
OPT1
OPT0
TI MER
STARTS
16-BIT RELOAD TI MER 0 UNDERFLOW OCCURS
SNI2
SNI1
SNI0
WRI TE SI GNAL I S GENERATED WH EN T HERE IS A COMPARISON MATCH BETWEEN RDA2 ~ RDA0 AND
SNI 2 ~ SNI 1 OR ANY EFFECTI VE EDGE INPUT AT SI N2 ~ SI N1, THE COMP ARSI ON IS TRI GGERED BY
TH E INPUT EDGE POSI TI ON DETECTI ON INPUT T ERMI NAL SI Nx.
416
CHAPTER 15 MULTI-PULSE GENERATOR
■ Timing Generated by Position Detection or Timer Underflow (OPS2 to OPS0 = 100B)
Figure 15.6-21 Timing Generated by Position Detection or Timer Underflow (OPS2 to OPS0 = 100B)
SNI2
SNI1
SNI0
WTIN1
Reload
Timer 0
Counter
Action
RDA2 to
RDA0
100
010
101
011
111
01
11
00
10
(OPDR)
WTIN0
(TOUT)
WTO
OP01,
OP00
00
11
(OPDR)
PPG
OPT0
417
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.4.6
When One-shot Position Detection
The output timing change, which is triggered by the input pin SNIx for the one-shot
position detection, is shown in Figure 15.6-22.
■ When One-shot Position Detection
Same as operation of position detection except that no further position detection will be recognized after
the first valid detection until it is changed to ANY OTHER operation mode. The OPTx output waveform is
shown in Figure 15.6-22.
The reload timer 0 is free to be used in this operation mode.
■ Timing Generated by One-shot Position Detection (OPS2 to OPS0 = 110B)
Figure 15.6-22 Timing Generated by One-shot Position Detection (OPS2 to OPS0 = 110B)
SNI2
SNI1
SNI0
RDA2 to
RDA0
100
110
00
01
(OPDR)
WTIN1
WTO
OP01,
OP00
11
(OPDR)
PPG
OPT0
OPS2 to
OPS0
418
110
010
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.4.7
When One-shot Position Detection and Timer
Underflow
The output timing change of the operation of the One-shot Position Detection and
Reload Timer underflow is shown in Figure 15.6-23.
■ When One-shot Position Detection and Timer Underflow
Same as operation of position detection and timer underflow except that no further position detection will
be recognized after first valid position detection until it is changed to ANY OTHER operation mode. Pin
OPTx output waveform is shown as in Figure 15.6-23.
In order to use this method, the reload timer should be used in " Single Shot Mode". TIN0O must be longer
than two machine cycles.
■ Timing Generated by One-shot Position Detection and Timer Underflow
(OPS2 to OPS0 = 111B)
Figure 15.6-23 Timing Generated by One-shot Position Fetection and Timer Underflow (OPS2 to OPS0 = 111B)
SNI2
SNI1
SNI0
TIN0O
(TIN)
Reload
timer 0
counter
action
RDA2 to
RDA0
100
110
00
01
(OPDR)
WTIN0
(TOUT)
WTO
OP01,
OP00
11
(OPDR)
PPG
OPT0
OPS2 to
OPS0
111
011
419
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.4.8
When One-shot Position Detection or Timer Underflow
The output timing change of the operation of the One-shot Position Detection or Reload
Timer underflow is shown in Figure 15.6-24. This operation mode is selected by setting
the OPS2 to OPS0 = 101B.
■ When One-shot Position Detection or Timer Underflow
Same as operation of position detection or timer underflow except that no further position detection will be
recognized after first valid position detection until it is changed to ANY OTHER operation mode. Pin
OPTx output waveform is shown as in Figure 15.6-24.
■ Timing Generated by One-shot Position Detection or Timer Underflow
(OPS2 to OPS0 = 101B)
Figure 15.6-24 Timing Generated by One-shot Position Detection or Timer Underflow (OPS2 to OPS0 = 101B)
SNI2
SNI1
SNI0
WTIN1
Reload
timer 0
counter
action
RDA2 to
RDA0
101
110
00
01
(OPDR)
WTIN0
(TOUT)
WTO
OP01,
OP00
11
(OPDR)
PPG
OPT0
OPS2 to
OPS0
420
101
100
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.5
Operation of DTTI1 Input Control
This section describes the operation of the DTTI1 Input Control Circuit.
■ Operation of DTTI1 Input Control
The DTTI1 circuit controls the output of the value of PDRx (PORTx Data Register) to the pin OPTx which
is multiplexed with the PORTx where OPTx is enable by setting OPEx = 1. The operation mode is enabled
by the DTIE bit (bit15) of the Output Control Register (OPCR).
Note:
Before the DTTI1 circuit is in effect, make sure that the PORTx which is multiplexed with the OPTx
is configured as an output port by setting its Data Direction Register.
When the DTIE bit (bit14) of the Output Control Register (OPCR) is set to "1", the waveform output at
OPT5 to OPT0 pins are enabled by the valid level of the DTTI1 pin. When the low input level is placed at
the DTTI1 pin, the output of OPTx is fixed at the inactive level. The software can set the inactive level for
each OPTX pin in PDRx of PORTx, the OPTx pin is then drived by the data written in the PDRx of
PORTx.
Even while the output is fixed at the inactive level by the input of the DTTI1 pin, the timer keeps running,
the position detection function does not stop and the data transfer from the Output Data Buffer Register
(OPDBR) to the Output Data Register (OPDR) is continued for waveform generation, but no waveform is
outputted to the OPT5 to OPT0 pins.
Figure 15.6-25 shows the DTTI1 circuit block diagram and Figure 15.6-26 shows the DTTI1 circuit timing
diagram when D1,D0 is set to "00B".
■ DTTI1 Circuit Block Diagram
Figure 15.6-25 DTTI1 Circuit Block Diagram
DTTI1 PIN
DTIE
D1
D0
NRSL
INPUT ENANLE OR
DISABLE SELECTOR
N-CYCLE DELAY
CIRCUIT
N can be 4, 8, 16, 32
depending on the
setting of D1,D0 bits
in the Noise Cacellation
Register (NCCR).
NOISE CANCELLATION
SELECTOR
DTTI1 INTERRURT AND
CONTROL GENERATOR
DTIF
DTISP
421
CHAPTER 15 MULTI-PULSE GENERATOR
■ DTTI1 Circuit Timing Diagram (D1,D0 = 00B)
Figure 15.6-26 DTTI1 Circuit Timing Diagram (D1,D0 = 00B)
φ
DTTI1
DTIE*
NRSL
DTIF
DTISP
DTTI1
DTIE
NRSL
DTIF*
DTISP
4 Cycles
* DTIF goes to low only by writing a “0” to it.
Note:
422
In worst case the time from DTTI1 being recognized (after noise cancellation) to DTISP in effect
takes 2 cycles, in best case it takes 1 cycle.
CHAPTER 15 MULTI-PULSE GENERATOR
■ Relationship between DTTI1 and OPTx Output
Table 15.6-4 Relationship between DTTI1 and OPTx Output
NRSL
DTIE
DTTI1
Function
X
0
X
DTTI1 has no effect on OPTx. (Initial value)
0
1
0
DTTI1 takes effect. Noise filter is not enable. An “L” input at DTTI1 pin triggers the
output of the inactive level set in PDRx. The DTTI1 interrupt is generated.
0
1
1
DTTI1 has no effect on OPTx.
1
1
0
DTTI1 takes effect. Noise filter is enable. An “L” input at DTTI1 pin triggers the
output of the inactive level set in PDRx. The DTTI1 interrupt is generated.
1
1
1
DTTI1 has no effect on OPTx.
423
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.6
Operation of Noise Cancellation Function
This section describes the noise cancellation function for the SNIx and DTTI1 pins.
■ Operation of Noise Cancellation Function
● DTTI1 Pin Noise Cancellation Function
When NRSL bit (bit12) of the Output Control Register (OPCR) is set to "1", the noise cancellation function
for DTTI1 pin input can be used. When the noise cancellation function is selected, the time for fixing an
output pin at the inactive level is delayed for about 4, 8, 16 or 32 machine clocks by the noise cancellation
circuit.
Note:
Since the DTTI1 Input Control Circuit uses a peripheral clock, input is invalidated even if the DTTI1
input is enabled in a mode such as STOP mode in which the oscillator stops.
● SNI2 to SNI0 Pins Noise Cancellation Function
When SNC2 to SNC0 bits (bit5 to bit3) of the Input Control Register (IPCR) are set to "1", the noise
cancellation function for SNI2 to SNI0 pins input can be used. When the noise cancellation function is
selected, the input is delayed for about four machine clocks by the noise cancellation circuit. Since the
noise cancellation circuit uses a peripheral clock, input is invalidated in a mode such as STOP mode in
which the oscillator stops even if the SNIx input is enabled.
● Programmable Noise Cancellation Circuit
Noise to be cancelled is programmable to have pulse width less than 4, 8, 16 and 32 machine cycles, i.e.
for 16 MHz machine clock, the circuit can filter 0.25 µs to 2 µs width pulses. The control for the
programming of the noise cancellation circuit of the SNIx and DTTI1's pins are separated. Figure 15.4-13
shows the noise cancellation control register.
424
CHAPTER 15 MULTI-PULSE GENERATOR
15.6.7
Operation of 16-bit Timer
The 16-bit timer has buffer and compare clear function, which is used for motor speed
checking and abnormal detection timeout. The 16-bit timer starts counting up from
counter value "0000H" after a reset has been completed and counting enable bit is set.
■ 16-bit Timer Operation
The counter value is cleared in the following conditions:
• When an overflow has occurred.
• When a match with Compare Clear Register (CPCR) is detected.
• When "1" is written to the TCLR bit of the TCSR register during operation.
• When a write timing signal is generated and MODE bit of the TCSR is "0".
• When a position detection signal is generated and MODE bit of the TCSR is "1".
• Reset
An interrupt can be generated when the counter is cleared due to a match with Compare Clear Register.
There is no interrupt when an overflow occurs.
Note:
Word access to Compare Clear Register and Timer Buffer Register must be used.
Figure 15.6-27 Clearing the Counter by an Overflow
Counter value
Overflow
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Interrupt
Figure 15.6-28 Clearing the Counter upon a Match with Compare Clear Register
Counter value
FFFFH
BFFFH
Match
Match
7FFFH
3FFFH
Time
0000H
Reset
Compare clear
register value
BFFFH
Interrupt
425
CHAPTER 15 MULTI-PULSE GENERATOR
■ 16-bit Timer Timing
The 16-bit timer is incremented based on the prescaler clock and counts up at a rising edge.
Note:
Before the prescaler clock is changed, the Timer Counter should be disable first by setting the
TMEN bit to "0".
Figure 15.6-29 16-bit Timer Count Timing
CPU clock
Prescaler clock
N
Counter value
N+1
N+2
N+3
N+4
The counter can be cleared upon a reset, software clear (TCLR), a match with Compare Clear Register, the
Write Timing signal or the Position Detection signal. By a reset, the counter is immediately cleared. By a
match with Compare Clear Register, software clear (TCLR), the Write Timing signal or the Position
Detection signal, the counter is cleared in synchronization with the count timing.
Figure 15.6-30 16-bit Timer Clear Timing
φ
Compare
register value
N
Prescaler clock
Compare match
Counter value
426
N-1
N
0000H
0001H
0002H
CHAPTER 15 MULTI-PULSE GENERATOR
■ 16-bit Timer Buffer Operation Timing Diagram
Figure 15.6-31 16-bit Timer Buffer Operation Timing Diagram
CPU clock
CLK
Counter value
Timer buffer
MODE
0000H
0001H
0002H
XXXXH
0000H
0001H
0002H
0002H
0 or 1
Load buffer
TMEN
WTO
WTIN1
Timer reset
427
CHAPTER 15 MULTI-PULSE GENERATOR
■ The Use of the 16-bit Timer in Multi-pulse Generator
The timer is reset when write timing or position detection interrupt flag is set, which is selectable by the
MODE bit in the Timer Control Status Register (TCSR).
The timer can be started or stopped by setting the TMEN bit in the Timer Control Status Register (TCSR).
There is no timer overflow interrupt. Whenever the timer is restarted, the current counter value is latched to
a buffer for speed calculation.
If the counter value is matched with Compare Clear Register (CPCR), it interrupts the CPU and the timer is
reset.
Note:
If the Compare Clear Register (CPCR) is loaded a value same as the Timer Counter value at that
moment, the comparison operation will NOT be performed until next same counter value.
The Compare Clear interrupt shares the same interrupt vector with the Write Timing interrupt while
Compare Match interrupt shares the same vector as that of the Position Detect interrupt.
■ 16-bit Timer in Multi-pulse Generator Operation Diagram
Figure 15.6-32 16-bit Timer in Multi-pulse Generator Operation Diagram
Compare
Clear
Register
(CPCR)
If no desired position
detect signal appears
for a timeout period,
it means abnormal.
Counter value
Current counter
value is latched
into buffer.
Timer is reset, which is triggered
by write timing or position detection.
428
Timer is reset, which is triggered
by write timing or position detection.
CHAPTER 15 MULTI-PULSE GENERATOR
15.7
Usage Notes on the Multi-pulse Generator
Notes on using the Multi-pulse Generator are given below.
■ Usage Notes on the Waveform Sequencer
● Notes on using a program for setting
• Switch from one PPG synchronization mode to another PPG synchronization mode (e.g. from risingedge synchronization (IPCUR: WTS1,WTS0 = 01B) to falling-edge synchronization (IPCUR:
WTS1,WTS0 = 10B) or vice versa) is inhibited, no synchronization mode (IPCUR: WTS1,WTS0 = 00B)
must be the transit for such switch.
• When the data transfer method is changed, the next data buffer register to be selected is always specified
by the BNKF, RDA2 to RDA0 bits in the data output register (OPDR). This does not apply to the
OPDBR0 write method (OPCUR: OPS2 to OPS0 = 000B), in OPDBR0 write method BNKF, RDA2 to
RDA0 bits are ignored.
• Word access to output data register (OPDR) must be used.
• When using OPDBR0 write method for data transfer (OPCUR: OPS2 to OPS0 = 000B), word access to
output data buffer register 0 must be used, byte access to either lower register or upper register does not
start any transfer operation.
• In order to use the 16-bit reload timer underflow transfer method (OPCUR: OPS2 to OPS0 = 010B), the
reload timer should be used in "Reload Mode". Software trigger is needed to be used for the startup of
the reload timer. The 16-bit reload timer is needed for setting the update time in advance and executing
the continuous control action.
• In order to use the position detection and timer underflow transfer method (OPCUR: OPS2 to OPS0 =
011B or 111B), the reload timer should be used in "Single Shot Mode". TIN0O must be longer than two
machine cycles.
• Before DTTI1 circuit is in effect (OPCUR: DTIE = 1), make sure that the PORTx which is multiplexed
with the OPTx is configured as an output port by setting its data direction register (DDRx).
• Since the DTTI1 input control circuit uses a peripheral clock, input is invalidated even if the DTTI1
input is enabled (OPCUR: DTIE = 1) in a mode such as STOP mode in which the oscillator stops.
• In worst case the time from DTTI1 being recognized (after noise cancellation) to DTISP in effect takes
2 cycles, in best case it takes 1 cycle.
• Always change the D1 and D0 bits of noise cancellation control register (NCCR) when the noise
cancellation function is disabled (OPCUR: NRSL = 0).
• Always change the S21, S20, S11, S10, S01 and S00 bits of noise cancellation control register (NCCR)
when the noise cancellation function is disabled (IPCLR: SNC2 to SNC0 = 000B).
429
CHAPTER 15 MULTI-PULSE GENERATOR
● Notes about interrupts
• When the DTIF bit of the output control upper register (OPCUR) is set to "1", control cannot be
returned from interrupt processing. Always clear the DTIF bit.
• When the WTIF bit of the output control upper register (OPCUR) is set to "1", control cannot be
returned from interrupt processing. Always clear the WTIF bit.
• When the PDIF bit of the output control lower register (OPCLR) is set to "1", control cannot be returned
from interrupt processing. Always clear the PDIF bit.
• When the CPIF bit of the input control upper register (IPCUR) is set to "1", control cannot be returned
from interrupt processing. Always clear the CPIF bit.
• Since the above interrupts share an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by these interrupts, shared resource interrupts must be disabled.
■ Usage Notes on the 16-bit Timer
● Notes about using a program for setting
• Word access to compare clear register (CPCR) and timer buffer register (TMBR) must be used.
• Before the prescaler clock is changed, the timer counter should be disable first by setting the TMEN bit
to "0". Change the CLK2, CLK1 and CLK0 bits of the timer control status register (TCSR) only when
the timer is not counting.
• If the compare clear register (CPCR) is loaded a value same as the timer counter value at that moment,
the comparison operation will NOT be performed until next same counter value.
● Notes about interrupts
• When the ICLR bit of the timer control status register (TCSR) is set to "1" and an interrupt request is
enabled (TCSR: ICRE = 1), control cannot be returned from interrupt processing. Always clear the
ICLR bit.
• Since the 16-bit timer shares an interrupt vector with other resource, interrupt causes must be checked
carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the 16-bit timer, shared resource interrupts must be disabled.
430
CHAPTER 15 MULTI-PULSE GENERATOR
15.8
Sample Programs for the Multi-pulse Generator
This section contains sample programs for the Multi-pulse Generator.
■ Sample Program for the Multi-pulse Generator
● Processing
• An output in PPG is directed to OPT0 and an inverted output in PPG is directed to OPT1 when write
timing interrupt is generated.
• OPDBR0 write method is used for data transfer to output data register OPDR.
• The 16-bit PPG timer is used in PWM and is started with a software trigger.
• EI2OS is not used.
• 16 MHz is used for the machine clock, and 62.5 ns is used for the count clock of 16-bit PPG timer.
● Coding example
ICR07
EQU
0000B7H
;Interrupt control register for the waveform sequencer
PCSR1
EQU
000042H
;PPG period setting register
PDUT1
EQU
000044H
;PPG duty setting register
PCNT1
EQU
000046H
;PPG control status register
OPCR
EQU
00008AH
;Output control register
OPDBR0
EQU
003FE0H
;Output data buffer register
WTIF
EQU
OPCR:9
;Interrupt request flag bit
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
;Assumes that stack pointer (SP) has already been
initialized
AND
CCR,#0BFH
;Interrupt disable
MOV
I:ICR01,#00H
;Interrupt level 0 (strongest)
MOVW
I:PCSR0,#0064H
;Sets the period of the PPG output
MOVW
I:PDUT0,#003CH
;Sets the duty ratio of the PPG output
MOVW
I:PCNT0,#01100000000000110B
;Enables PPG output in normal polarity
;Enables 16-bit PPG timer, and 62.5 ns clock
;Software triggers PPG
;Select PWM mode
;Clears interrupt flag, and starts counter
MOVW
I:OPCR,#0103H
;Enable OPT0 and OPT1 output
;Sets OPDBR0 write method for data transfer
431
CHAPTER 15 MULTI-PULSE GENERATOR
; Enable write timing interrupt
;Clears interrupt flag
MOVW
I:OPDBR0,#0009H
;Sets OPT0 pin as PPG output
;Sets OPT1 pin as inverted PPG output
;Starts data transfer
LOOP:
MOV
ILM,#07H
;Sets ILM in PS to level 7
OR
CCR,#40H
;Interrupt enable
MOV
A,#00H
;Endless loop
MOV
A,#01H
;
BRA
LOOP
;
;-------Interrupt program-------------------------------------------------------------------------------------------WARI:
CLRB
I:WTIF
;
:
;
User processing
;
:
RETI
CODE
;Clears interrupt request flag
;Returns from interrupt
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------VECT
VECT
CSEG
ABS=0FFH
ORG
0FF94H
DSL
WARI
ORG
0FFDCH
DSL
START
DB
00H
ENDS
END
432
START
;Sets vector for interrupt #26 (1AH)
;Sets reset vector
;Sets single-chip mode
CHAPTER 16
PWC Timer
This chapter explains the functions and operations of
the PWC timer.
16.1 Overview of the PWC Timer
16.2 Block Diagram of the PWC Timer
16.3 PWC Timer Pins
16.4 PWC Timer Registers
16.5 PWC Timer Interrupts
16.6 Operation of the PWC Timer
16.7 Usage Notes on the PWC Timer
16.8 Sample Programs for the PWC Timer
433
CHAPTER 16 PWC Timer
16.1
Overview of the PWC Timer
The PWC timer (pulse-width measurement) is the multi-functional 16-bit up counter with
the reload function and also has a function that calculates the pulse width of the input
signal.
The PWC timer consists of a 16-bit counter, an input pulse divider, a division rate
control register, a count input pin, a pulse output pin, and a 16-bit control register.
■ PWC Timer (× 2, PWC Timer 0 is not present in MB90465 Series)
The MB90460 series contain two PWC timer channels, while MB90465 series contains only PWC timer 1.
The PWC timer has the following characteristics:
● Timer function
• Generates an interrupt request at the specified time interval.
• Outputs the pulse signal that is synchronized with the timer period.
• Selects the counter clock from three internal clocks.
● Pulse-width measurement function
• Generates an interrupt request at the specified time interval.
• Outputs the pulse signal that is synchronized with the timer period.
• Selects the counter clock from three internal clocks.
● Pulse-width measurement function
• Measures the time between external pulse input events.
• Selects the counter clock from three internal clocks.
• Count mode
- H pulse width (rising edge to falling edge) / L pulse width (falling edge to rising edge)
- Rising edge period (rising edge to falling edge) / falling edge period (falling edge to rising edge)
- Intermediate edge count (rising or falling edge to falling or rising edge)
• Uses the 16-bit input divider to divide the input pulse by 22, 24, 26, and 28 to enable period
measurement.
• Generates an interrupt request at completion of count.
• Selects single count or continuous count.
● PWC timer operation
This block is a multi-functional timer that is based on the 16-bit up-count timer and contains a count input
pin and an 8-bit input divider. The block has two main functions, a timer function and a pulse-with
measurement function, both of which enable the selection of two types of count clocks.
434
CHAPTER 16 PWC Timer
16.2
Block Diagram of the PWC Timer
Figure 16.2-1 PWC timer block diagram.
■ PWC Timer Block Diagram
Figure 16.2-1 PWC Timer Block Diagram
PWC read
Error
detection
ERR
16
PWC
16
Write enabled
16
Overflow
Reload
P07/PWO0
P23/PWO1
F.F.
Data transfer
16
Clock
Overflow
22
16-bit up-count timer
23
Timer clear
F2MC-16LX bus
Count
enabled
Count bit
output
Flag setting
Control circuit
Start edge
selection
Count end
edge
Count start edge
End edge
selection
Overflow interrupt request
15
CKS1, CKS0,
Divider clear
Internal clock
(machine clock / 4)
Divider ON/OFF
P06/PWI0
P22/PWI1
Edge
detection
Count end interrupt request
PWCS
Clock
Clock
divider
8-bit
divider
CKS1
ERR CKS0
Division
rate
selection
2
DIVR
435
CHAPTER 16 PWC Timer
16.3
PWC Timer Pins
This section describes the pins of the PWC timer and provides a pin block diagram.
■ PWC Timer Pins
The pins of the PWC timer are shared with the general-purpose ports. Table 16.3-1 lists the functions of
the pins, I/O format, and settings required to use the 16-bit reload timer.
Table 16.3-1 16-bit PWC Timer Pins
Pin name
Pin function
I/O format
P06/PWI0
Port 0 input-output /
timer input
CMOS output /
Port 0 input-output / CMOS input
P07/PWO0
timer output
Pull-up option Standby control
Settings required for pins
Setting for the input port
(DDR0: bit6 = 0)
Selection
allowed
Setting for timer enable
(PWCSL0: MOD2 to MOD0 not
equal 0)
Available
Port 2 input-output /
P22/PWI1
timer input
CMOS output /
CMOS
Port 2 input-output / hysteresis input
P23/PWO1
timer output
Setting for the input port
(DDR2: bit2 = 0)
Not
provided
Setting for timer enable
(PWCSL1: MOD2 to MOD0 not
equal 0)
■ Block Diagram of the PWC Timer Pins
Figure 16.3-1 shows the block diagram of the PWC timer 0 pins.
Figure 16.3-1 Block Diagram of the PWC Timer 0 Pins
RDR
Resource output
Port data register (PDR)
Direct resource input
Resource output enable
Pull-up resistor
Internal data bus
About 50k
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
436
Standby control (SPL = 1)
CHAPTER 16 PWC Timer
Figure 16.3-2 shows the block diagram of the PWC timer 1 pins.
Figure 16.3-2 Block Diagram of the PWC Timer 1 Pins
Resource output
Resource input
Resource output enable
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
437
CHAPTER 16 PWC Timer
16.4
PWC Timer Registers
Following are the PWC timer registers.
■ PWC Timer Registers
Figure 16.4-1 PWC Timer Registers
PWC control status register (Upper)
Address: ch.0 000009Hbit 15
ch.1 000029H
STRT
14
13
12
11
10
9
STOP
EDIR
EDIE
OVIR
OVIE
ERR
POUT
Read/write
Initial value
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
5
4
3
2
R/W
0
8
PWCSH0,
PWCSH1
PWC control status register (Lower)
Address: ch.0 000008H
ch.1 000028H
bit
Read/write
Initial value
7
6
CKS1
CKS0
R/W
0
R/W
0
R/W
0
1
0
S/C
MOD2 MOD1 MOD0
R/W
0
R/W
0
R/W
0
11
10
Reserved Reserved
R/W
0
R/W
0
PWCSL0,
PWCSL1
PWC data buffer register (Upper)
bit 15
Address: ch.0 00000BH
ch.1 00002BH PW15
14
13
12
PW14
PW13
PW12
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
6
5
4
3
PW06
PW05
PW04
R/W
X
R/W
X
R/W
X
R/W
X
6
5
4
3
2
—
—
—
—
—
R/W
X
PWC data buffer register (Lower)
bit
7
Address: ch.0 00000AH
ch.1 00002AH
PW07
Read/write
Initial value
R/W
X
PW11 PW10
9
8
PW09
PW08
R/W
X
R/W
X
R/W
X
2
1
0
PW01
PW00
R/W
X
R/W
X
PW03 PW02
R/W
X
PWC0,PWC1
PWC0,PWC1
Division rate control register
bit
Address: ch.0 00000CH
ch.1 00002CH
Read/write
Initial value
438
7
—
1
DIV1
R/W
0
0
DIV0
R/W
0
DIV0,DIV1
CHAPTER 16 PWC Timer
16.4.1
PWC Control Status Register
(PWCSH0/PWCSH1, PWCSL0/PWCSL1)
The PWC control status register (PWCSH0/PWCSH1, PWCSL0/PWCSL1) controls the
PWC timer operation and reads the PWC timer state.
■ PWC Control Status Register, Upper Byte (PWCSH0/PWCSH1)
Figure 16.4-2 PWC Control Status Register (PWCSH0/PWCSH1)
Address
bit
15
14
13
ch.0: 000009H STRT STOP EDIR
ch.1: 000029H R/W
R/W
R
12
11
10
9
8
Initial value
EDIE
OVIR
OVIE
ERR
POUT
00000000B
R/W
R/W
R/W
R
R/W
POUT
Pulse output bit
0
When previous value is "1" and timer overflows
1
When previous value is "0" and timer overflows
ERR
Error flag bit
0
Count result is not overwritten
1
Count result is overwritten before previous value is read
OVIE
Overflow interrupt request enable bit
0
Disables overflow interrupt request
1
Enables overflow interrupt request
Overflow interrupt request bit
OVIR
Read
Write
0
No timer overflow
Clear this bit
1
Timer overflows
No effect
EDIE
End interrupt enable bit
0
Disables end interrupt request
1
Enables end interrupt request
EDIR
End interrupt request flag bit
0
Pulse-width measurement is operating
1
Pulse-width measurement is terminated
Operation status indication
STRT STOP
X
Write
0
0
Timer stops (the timer is not
started or count ends)
No function. Operation is not
affected
0
1
No meaning
Starts or restarts the timer
(enables count)
1
0
No meaning
Stops the timer operation
(disables count)
1
1
Timer count operation in
progress (counting)
No function. The operation is not
affected
: Indeterminate
R/W : Read and write
: Initial value
—
Read
: Not used
439
CHAPTER 16 PWC Timer
Table 16.4-1 PWC Control Status Register (PWCSH0/PWCSH1)
Bit name
bit15,
bit14
STRT, STOP:
Start and Stop bits
Function
•
•
•
•
•
These bits are used to start, restart, and stop the 16-bit up-count timer.
When these bits are read, the timer operation status is returned.
These bits can be read and written. The meaning of bits depend on whether they are read or written.
In read-modify-write operation, “11B” is always read.
When the STRT and STOP bits are written to start and stop the timer, a bit manipulation instruction
(such as bit clear instruction) can be used. However, when the operation status (which always indicates
that the timer is operating, for example) is read, a bit manipulation instruction cannot be used.
• This bit indicates that measurement terminated in pulse-width measurement mode.
• When pulse-width measurement terminates, the bit is set (PWC0/PWC1 contains the measurement
bit13
EDIR:
End interrupt
request flag bit
result).
• This bit is cleared automatically when the measurement result in PWC data buffer register, PWC0/
PWC1, is read.
• In timer mode, this bit is meaningless.
• This bit is read-only, writing this bit is meaningless.
EDIE:
End interrupt
enable bit
• This bit is used to control a measurement termination interrupt request in pulse-width count mode.
• When this bit is “1” and EDIR is set to “1”, the end interrupt request will be generated to CPU.
• Always set “0” in timer mode.
bit11
OVIR:
Overflow interrupt
request bit
•
•
•
•
•
bit10
OVIE:
Overflow interrupt
request enable bit
bit12
This bit is used to specify when the 16-bit up-count timer overflows. The operation affects all modes.
When timer overflow occurs (FFFFH to 0000H), the bit is set.
Writing “0” will clear the bit.
Writing “1” has no effect.
In read-modify-write operation, “1” is always read.
(Note)
In H/L pulse-width count mode, do not use this bit for pulse-width time measurement.
• This bit is used to enable timer overflow interrupt request.
• When this bit is “1” and OVIR is set to “1”, the overflow interrupt request will be generated to CPU.
(Note)
In the H/L pulse-width count mode, set this bit to “0”.
• This bit is used to execute a continuous count in the pulse-width count mode. This flag indicates that
bit9
ERR:
Error flag bit
the next count has been completed before the previous count result is read from PWC0/PWC1. If this
state occurs, PWC0/PWC1 is overwritten by new count result and the previous result is lost. The count
operation continues regardless of the value of this bit.
• The bit is read-only. Writing to this bit is meaningless.
• When the count result that has not been read is overwritten by the next result, the bit is set.
• This bit is cleared automatically when the measurement result in PWC data buffer register, PWC0/
PWC1, is read.
• When the 16-bit up-count timer overflows in timer mode, this bit is reversed.
• In the pulse-width count mode, this bit is meaningless.
• The bit can be read and written. However, the bit can be written only if the timer stops (both bit15:
bit8
440
POUT:
Pulse output bit
STRT and bit14: STOP are set to “0”). If the bit is written during timer operation (both bit15: STRT and
bit14: STOP are set to “1”), the bit value remains unchanged.
• When the POUT value is “0” and the timer overflows in the range from FFFFH to 0000H or the timer
stops and "1" is written, the bit is set.
• When the POUT value is “1” and the timer overflows in the range from FFFFH to 0000H or the timer
stops and “0” is written, the bit is cleared. The bit is also cleared by reset.
CHAPTER 16 PWC Timer
■ PWC control Status Register, Lower Byte (PWCSL0/PWCSL1)
Figure 16.4-3 PWC Control Status Register (PWCSL0/PWCSL1)
Address
bit
ch.0: 000008H
ch.1: 000028H
7
6
5
4
3
CKS1 CKS0 Reserved Reserved
R/W
R/W
R/W
S/C
R/W
2
1
0
Initial value
MOD2 MOD1 MOD0 00000000B
R/W
R/W
R/W
R/W
MOD2 MOD1 MOD0 Operation mode / count edge selection
0
0
0
Timer mode and no pulse output
0
0
1
Timer mode and pulse output (PWO pin valid):
reload mode only
0
1
0
All edge-to-edge pulse-width measurement
mode (rising edge or falling edge to falling edge
or rising edge)
0
1
1
Division period measurement mode
(when the input divider is used)
1
0
0
Rising edge-to-rising edge period measurement
mode (rising edge to rising edge)
1
0
1
H pulse-width measurement mode
(rising edge to falling edge)
1
1
0
L pulse-width measurement mode
(falling edge to rising edge)
1
1
1
Falling edge-to-falling edge period measurement
mode (falling edge to falling edge)
Count mode
selection
S/C
: Indeterminate
R/W : Read and write
Pulse-width count
mode
0
Single
No reload (one shot) Stop after one
measurement mode
measurement
1
Reload
Continuous
(reload timer)
measurement mode Buffer register is
valid
CKS1 CKS0
X
Timer mode
Continuous
measurement:
Buffer register is
valid
Count clock selection
0
0
Machine clock divided by 4
(0.25µs for machine cycle at 16 MHz)
0
1
Machine clock divided by 16
(1.0 µs for machine cycle at 16 MHz)
1
0
Machine clock divided by 32
(2.0 µs for machine cycle at 16 MHz)
1
1
Setting prohibited (undefined)
: Initial value
—
: Not used
441
CHAPTER 16 PWC Timer
Table 16.4-2 PWC Control Status Register (PWCSL0/PWCSL1)
Bit name
bit7,
bit6
CLK1,CLK0:
Clock select bits
bit5,
bit4
Reserved bits
bit3
S/C:
Singe/continuous bit
Function
• CKS1 and CKS0 bits are used to select the internal count clock. These bits are used to select
the internal count clock.
• After reset, the bits are initialized to “00B”. The bits can be read and written. However, “11B”
cannot be set.
(Note)
After the timer is started, changing the setting is prohibited. Write these bits before
the timer is started or after the timer is stopped.
• There bits are reserved. Always write “00B” to these bits.
• The S/C bit is used to select the count mode.
• After reset, the bit is initialized to “0”. The bit can be read and written.
(Note)
After the timer is started, changing the setting is prohibited. Write this bit before the
timer is started or after the timer is stopped.
• Setting these bits enables selection of the operating mode and the pulse edge that fits the pulsewidth count.
• After reset, these bits are initialized to “000B”. These bits can be read and written.
bit2
to
bit0
442
MOD2 to MOD0:
Operation mode bits
(Note)
After the timer is started, changing the setting is prohibited. Write these bits before
the timer is started or after the timer is stopped.
If the continuous measurement mode is set for the setting marked *, the number of
edges are totaled and the divider for the internal count clock is not cleared at the end
of count. In all other modes, the divider for the internal count clock is cleared at the
end of the count.
CHAPTER 16 PWC Timer
16.4.2
PWC Data Buffer Register (PWC0/PWC1)
The PWC data buffer register (PWC0/PWC1) has functions that depend on the operation
mode of the PWC timer.
■ PWC Data Buffer Register (PWC0/PWC1)
Figure 16.4-4 PWC Data Buffer Register (PWC0/PWC1)
PWC data buffer register (Upper)
bit 15
Address: ch.0 00000BH
ch.1 00002BH PW15
14
13
12
PW14
PW13
PW12
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
6
5
4
3
PW06
PW05
PW04
R/W
X
R/W
X
R/W
X
R/W
X
11
10
PW11 PW10
9
8
PW09
PW08
R/W
X
R/W
X
R/W
X
2
1
0
PWC0,PWC1
PWC data buffer register (Lower)
bit
7
Address: ch.0 00000AH
ch.1 00002AH
PW07
Read/write
Initial value
R/W
X
PW03 PW02
R/W
X
R/W
X
PW01
PW00
R/W
X
R/W
X
PWC0,PWC1
● Timer mode
In the reload timer operation mode (PWCSL0/PWCSL1:S/C = 1), this register contains the reload value.
The register can be read or written.
In the single timer operation mode (PWCSL0/PWCSL1:S/C = 0), direct access to this register accesses the
up-count timer. In this mode, this register can be read or written. However, the register is written only
when the timer stops. The register can always be read and the current timer value is read.
● Pulse-width measurement mode (read-only)
In the continuous measurement mode (PWCSL0/PWCSL1:S/C = 1), this register functions as the buffer
register and contains the previous count result. This register is read-only. Writing to this register has no effect.
In the single measurement mode (PWCSL0/PWCSL1:S/C = 0), direct access to this register accesses the upcount timer. In this mode, the register is also read-only. Writing to this register has no effect. The register can
always be read and the current timer value is read. After the count, the register contains the count results.
Notes:
• To access this register, always use the word transfer instruction.
• After reset, this register is initialized to "0000H".
443
CHAPTER 16 PWC Timer
16.4.3
Division Rate Control Register (DIV0/DIV1)
The division rate control register (DIV0/DIV1) is used in the division period
measurement mode (PWCSL:MOD2, 1, and 0 = 011B). This register has no meaning in
other modes.
■ Division Rate Control Register (DIV0/DIV1)
Figure 16.4-5 Division Rate Control Register (DIV0/DIV1)
Address bit
ch.0: 00000CH
ch.1: 00002CH
X
7
6
5
4
3
2
1
0
Initial value
—
—
—
—
—
—
DIV1
DIV0
------00B
—
—
—
—
—
—
R/W
R/W
DIV1
DIV0
0
0
22 = divided by 4
0
1
24 = divided by 16
1
0
26 = divided by 64
1
1
28 = divided by 256
: Indeterminate
R/W : Read and write
Division rate selection bits
: Initial value
—
: Not used
Table 16.4-3 Division Rate Control Register (DIV0/DIV1)
Bit name
bit7
to
bit2
bit1,
bit0
444
Unused bit
DIV1,DIV0:
Division rate selection bits
Function
• The read value is indeterminate.
• Writing to these bits has no effect on the operation.
• In the division range measurement mode, this register is used to divide the pulse input
from the measurement pin and measure the one-period width after division.
• After reset, these bits are initialized to “00B”. These bits can be read and written.
(Note)
After the timer starts, the setting cannot be changed. Write these bits before the
timer has started or after the timer has stopped.
CHAPTER 16 PWC Timer
16.5
PWC Timer Interrupts
The PWC timer is enabled to generate an interrupt request in an overflow of the counter
or measurement terminated in pulse-width measurement mode. It is also coordinated
with the extended intelligent I/O service (EI2OS).
■ PWC Timer Interrupts
Table 16.5-1 lists the interrupt control bits and interrupt causes of the PWC timer.
Table 16.5-1 Interrupt Control Bits and Interrupt Causes of the PWC Time
PWC timer 0
Interrupt request flag bit
PWC timer 1
PWCSL0: OVIR
PWCSL0: EDIR
PWCSL1: OVIR
PWCSL1: EDIR
Interrupt request enable bit PWCSL0: OVIE
PWCSL0: EDIE
PWCSL1: OVIE
PWCSL1: EDIE
Interrupt cause
Measurement
Overflow of the 16-bit terminated in pulseup counter
width measurement
mode
Measurement
Overflow of the 16-bit terminated in pulseup counter
width measurement
mode
In the PWC timer, the OVIR bit of the PWC control status register (PWCSL) is set to "1" by an overflow
(from FFFFH to 0000H) of the up counter. If an interrupt request is enabled (PWCSL:OVIE = 1) in this
operation, the interrupt request is output to the interrupt controller.
The EDIR bit of the PWC control status register (PWCSL) is set to "1" by measurement terminated in
pulse-width measurement mode. If an interrupt request is enabled (PWCSL:EDIE = 1) in this operation,
the interrupt request is output to the interrupt controller.
■ PWC Timer Interrupts and EI2OS
Table 16.5-2 lists the PWC timer interrupts and EI2OS.
Table 16.5-2 16-bit PWC Timer Interrupts and EI2OS
Interrupt control register
Channel
Interrupt
number
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
PWC timer 0*1
#13 (0DH)
ICR01
0000B1H
FFFFC8H
FFFFC9H
FFFFCAH
PWC timer 1*2
#24 (18H)
ICR06
0000B6H
FFFF9CH
FFFF9DH
FFFF9EH
O
*1: The same interrupt number as that for 16-bit PPG timer 0 is assigned to PWC timer 0.
*2: The same interrupt number as that for output compare channel 5 match is assigned to PWC timer 1.
445
CHAPTER 16 PWC Timer
■ EI2OS Function of the PWC Timer
Since the PWC timer has a circuit that coordinates with EI2OS, the counter can start EI2OS when an
overflow or measurement termination occurs.
However, EI2OS is available only when other peripheral functions sharing the interrupt control register
(ICR) do not use interrupts. For example, when PWC timer 0 uses EI2OS, interrupts of the 16-bit PPG
timer 0 must be disabled.
446
CHAPTER 16 PWC Timer
16.6
Operation of the PWC Timer
The PWC timer is the multi-functional timer based on the 16-bit up-count timer and
contains the count input pin and 8-bit input divider. The block has two main functions:
timer function and pulse-width count function. Both the timer function and the pulsewidth count function enable the selection of two types of count clocks.
■ Timer Function
The timer function is the up-count timer that enables selection of the operation in single mode or reload
mode.
When the timer is started, a timer count is performed at each count clock.
When an overflow occurs in the range from FFFFH to 0000H, an interrupt request is issued.
If an overflow occurs, the following occurs:
During single mode, count is discontinued (see Figure 16.6-1).
During reload mode, the reload register contents are reloaded to the timer and the count is restarted (see
Figure 16.6-2).
Figure 16.6-1 Timer Operation (Single Mode)
Timer count value
Overflow
Overflow
FFFFH
Write to
PWC
(Restart is invalid)
0000H
Timer starts
Timer starts
OVIR flag setting, Timer stops
OVIR flag setting, Timer stops
Time
447
CHAPTER 16 PWC Timer
Figure 16.6-2 Timer Operation (Reload Mode)
Timer count value
Overflow
Overflow
Overflow
Overflow
Overflow
FFFFH
(Restart is invalid)
PWC write value
Reload
Reload
Reload
Reload
Reload
Reload
0000H
Write to PWC
Timer starts
Restart
Reload
Timer stop
OVIR flag setting
Time
POUT bit
If the timer is started at L level, the level is not toggled when the timer is restarted
(except when an overflow occurs simultaneously)
■ Pulse-width Measurement Function
The pulse-width measurement function calculates the time between the specified events related to the input
pulse.
When this function is activated, a count is started after the specified count start edge is input. If the counter
is cleared to "0000H", a count is started when the start edge is detected, then the stop edge is detected. The
count value during this period is held in the register as the pulse width.
When the measurement terminates or an overflow occurs, an interrupt request can be generated. When the
measurement is completed, the following occurs:
• Single measurement mode
The operation is discontinued (see Figure 16.6-3).
• Continuous measurement mode
The timer value is transferred to the buffer register and the timer is in free-run state until the next edge is
input (see Figure 16.6-4).
448
CHAPTER 16 PWC Timer
Figure 16.6-3 Pulse-width Measurement Operation (Single Measurement Mode, H-width Measurement
Mode)
PWC input
measured pulse
(The solid line indicates the timer count value)
Timer count value
FFFFH
Timer
clears
0000H
Start of
Timer
measurement starts
Timer
stops
EDIR flag setting (termination of measurement)
Time
Figure 16.6-4 Pulse-width Measurement Operation (Continuous Measurement Mode, H-width
Measurement Mode)
PWC input
measured pulse
(The solid line indicates the timer count value)
Timer count value
Data transfer
to PWC
FFFFH
Timer
clears
Data transfer
to PWC
Timer clear
0000H
Start of
Timer
measurement starts
OVIR flag Timer
setting
starts
EDIR flag setting
(termination of measurement)
OVIR flag
setting
EDIR flag setting
Time
*
*: The timer value during this period is not guaranteed (a timer overflow may result in OVIR being set)
449
CHAPTER 16 PWC Timer
16.6.1
Operation Mode Selection
Operation modes and count modes are selected according to the setting of PWCS.
■ Operation Mode Selection
The following registers are used to set the selection of operation modes and count modes:
● Operation mode setting: PWCSL:MOD2, MOD1, and MOD0 bits
Select the timer mode or pulse-width measurement mode to specify control of the count operation.
● Count mode setting: PWCSL:S/C bit
Select single measurement or continuous measurement or reload operation or one-shot operation.
Table 16.6-1 lists the operation modes selected using the mode setting bits.
Table 16.6-1 Operation Mode Selection
Operation mode
Timer
Pulse-width
measurement
Pulse-width
measurement
450
MOD2 MOD1 MOD0
One-shot timer
0
0
0
0
Reload timer
1
0
0
0/1
Setting prohibited
0
0
0
1
Rising edge or falling edge to Single measurement: Buffer invalid
falling edge or rising edge:
All edge-to-edge
Continuous measurement: Buffer valid
measurement
0
0
1
0
1
0
1
0
Division count:
Divide by 4 to 256
Single measurement: Buffer invalid
0
0
1
1
Continuous measurement: Buffer valid
1
0
1
1
Rising edge to rising edge:
Rising edge to rising edge
period
measurement
Single measurement: Buffer invalid
0
1
0
0
Continuous measurement: Buffer valid
1
1
0
0
Rising edge to falling edge:
H pulse-width
measurement
Single measurement: Buffer invalid
0
1
0
1
Continuous measurement: Buffer valid
1
1
0
1
Falling edge to rising edge:
L pulse-width
measurement
Single measurement: Buffer invalid
0
1
1
0
Continuous measurement: Buffer valid
1
1
1
0
Falling edge to falling edge:
Falling edge-to-falling edge
period
measurement
Single measurement: Buffer invalid
0
1
1
1
Continuous measurement: Buffer valid
1
1
1
1
After reset, the one-shot timer is selected as an initial value.
Note:
S/C
Before the timer starts, always selects the operation mode.
CHAPTER 16 PWC Timer
16.6.2
Starting and Stopping the Timer and Pulse-width
Measurement and Clearing the Timer
To start, restart, and forcibly stop the timer and pulse-width measurement, use the
PWCSH0/PWCSH1:STRT and PWCSH0/PWCSH1:STOP.
The 16-bit up-count timer is cleared to "0000H" at reset and when the measurement start
edge is detected and the count is started in the pulse-width measurement mode.
■ Starting and Stopping Timer and Pulse-width Measurement
Writing "0" to the PWCSH0/PWCSH1:STRT bit starts or restarts the operation, and writing "0" to the
PWCSH0/PWCSH1:STOP bit stops the operation. However, unless the value is written to these two bits
are different, none of the bits executes operations. If an instruction (byte or word instruction) other than the
bit manipulation instruction is being used, a value is written to the following bit combinations only.
Table 16.6-2 Pulse-width Measurement Operation
(Single Measurement Mode, H-width Measurement Mode)
Function
STRT
STOP
Starts and restarts the timer or pulse-width measurement
0
1
Stops the timer or pulse-width measurement
1
0
If a bit manipulation instruction (clear bit instruction) is being used, the hardware automatically writes the
above combination of values. The user need not know which value is to be written.
● Operation after start
Timer mode: The count operation is started immediately.
Pulse-width measurement mode: Measurement is started after the measurement start edge is input. After
the measurement start edge is detected, the 16-bit up-count timer is cleared to "0000H" and the count is
started.
● Restarting the timer
While the timer operation continues after the timer is started in the timer mode or pulse-width measurement
mode, starting the start (writing "0" to the PWCSH0/PWCSH1:STRT bit) is called timer restart. The
operations to be executed during restart are dependent on the following modes:
One-shot mode: The operation is not affected.
Reload timer mode: Reload is executed and the operation is continued. If the timer is restarted when an
overflow occurs, the overflow flag (PWCSH0/PWCSH1:OVIR) is set and the POUT bit is reversed.
Pulse-width measurement mode: In the measurement start edge wait state, the operation is not affected.
During measurement, the count stops and the timer state returns to the "measurement start edge wait" state.
When the timer is restarted on termination of measurement, the measurement termination flag (PWCSH0/
PWCSH1:EDIR) is set and the measurement results are transferred to PWC0/PWC1 in continuous
measurement mode.
451
CHAPTER 16 PWC Timer
● Stopping the timer
In one-shot timer mode or single measurement mode, measurement is automatically discontinued when the
timer overflows or at the end of a count. The user need not know if the timer has stopped. However, in
other modes, the timer must be stopped. This is also true when the timer is to be stopped before the timer
automatically stops.
● Checking operation state
The previously described STRT and STOP bits function as bits that indicate the operation state of the timer
during a read operation. Table 16.6-3 lists the contents of the indicated values
Table 16.6-3
Functions of Operation State Indication Bits
STRT
STOP
Operation state
0
0
Timer is stopping (except measurement start edge wait state).
The bits indicate that the timer has not started or a measurement has terminated.
1
1
Measurement start edge wait state or timer count operation
During a read operation, both the STRT bit and the STOP bit have the same value. However, during a read
operation using the read modify write instruction (such as bit manipulation instruction), the values of the
bits are always 11B. Do not use this instruction to read the values of the bits.
■ Clearing theTimer
In the following cases, the 16-bit up-count timer is cleared to "0000H":
• During reset
• When a count has started after the count start edge is detected in the pulse-width measurement mode
452
CHAPTER 16 PWC Timer
16.6.3
Timer Mode Operation
The timer mode includes the one-shot operation mode and reload operation mode.
■ One-shot Operation Mode
When the timer is started in this mode, a count is incremented at each count clock. The timer automatically
stops when an overflow occurs from FFFFH to 0000H.
If PWC0/PWC1 is set before the timer has started, the count is started from this set value. After overflow,
the set value is deleted and the current count value remains in PWC0/PWC1.
PWCSH0/PWCSH1:POUT is reversed if an overflow occurs.
■ Reload Operation Mode
When the timer is started in this mode, the reload value in PWC0/PWC1 is set in the timer and the count is
incremented at each count clock. If an overflow occurs when the timer counts FFFFH to 0000H, the reload
value in PWC0/PWC1 is set in the timer again, the PWCSH0/PWCSH1:POUT bit is reversed, and the
count operation is repeated. The timer does not stop until a value is written to the PWCSH0/
PWCSH1:STOP to stop the timer or it is reset. The port bit will output to pin PWO0/PWO1 if pulse output
mode is specified.
The reload value (set in PWC0/PWC1 before the timer is started) is stored during a count. When the timer
is started or restarted and an overflow occurs, the reload value is always set in the timer. If the value that is
set during a count is to be changed, a new reload value becomes valid when the next overflow occurs or the
timer is restarted.
■ Timer Value and Reload Value
In one-shot operation mode, direct access to PWC0/PWC1 accesses the up-count timer. When a value is
written to PWC0/PWC1, the value is written directly to the timer. When PWC0/PWC1 is read during a
count operation, the current timer value is read. If the value is set in PWC0/PWC1 before the timer is
started, the timer starts a count from the specified value.
In reload operation mode, the up-count timer cannot be accessed and PWC0/PWC1 functions as a reload
register (stores the reload value). When the timer is started or restarted and an overflow occurs, the value
written to PWC0/PWC1 is always set in the timer. When PWC0/PWC1 is read, the stored reload value is
read.
The PWC0/PWC1 value and timer value are undefined if the timer is set in one-shot mode after the
operation is discontinued in reload mode. Therefore, always set the values before the timer is used.
The PWC0/PWC1 value is undefined if the timer is set in reload mode after the operation is forcibly
discontinued in one-shot mode. Therefore, always set the value before the timer is used.
■ Interrupt Request Generation
During operation in timer mode, an overflow enables the generation of an interrupt request. If the
increment of a timer count causes an overflow, the overflow flag is set, an overflow interrupt request is
enabled, and an interrupt request is generated.
453
CHAPTER 16 PWC Timer
■ Timer Period
If the timer is started in one-shot mode after "0000H" is set in PWC0/PWC1, a timer overflow occurs and
the count is discontinued if the count exceeds 65536. The following formula is used to calculate the time
from start to stop of the timer.
T1 = (65536-n1) x t
T1 ...... Time from start to stop (µs)
n1 ...... Timer value set in PWC0/PWC1 when the timer is started
t ...... Count clock period (µs)
If the timer is started after "0000H" is set in PWC0/PWC1, a timer overflow occurs every time the count
exceeds 65536. The following formula is used to calculate the reload period and the PWO pin output pulse
period.
TR............ Reload period (overflow period) (µs)
TR = (65536-NR) x t
TPOUT ...... PWO0/PWO1 pin output pulse period (µs)
NR .......... Reload value stored in PWC0/PWC1
t .............. Time from start to stop (µs)
■ Count Clock and Maximum Period
In timer mode, when "0000H" is set in PWC0/PWC1, the maximum period results.
Table 16.6-4 lists the count clock period and maximum timer period corresponding to the machine cycle
(indicated by f in the table) at 16 MHz
Table 16.6-4
Count Clock and Period
Count clock selection
Count clock period
Maximum timer period
454
When CKS1,CKS0=00B
(φ/4)
When CKS1,CKS0=01B
(φ/16)
When CKS1,CKS0=10B
(φ/32)
0.25 µs
1 µs
2 µs
16.38 ms
65.5 ms
131.1 ms
CHAPTER 16 PWC Timer
■ Flowchart of Timer Mode Operation
Figure 16.6-5 Flowchart of Timer Mode Operation
Setting
-Select count clock
-Select operation mode and timer mode
-Clear interrupt flag
-Enable interrupt
-Set pulse output initial value
Set value in PWC
Restart
Start by STRT bit
Reload operation mode
Single operation mode
Reload PWC value to timer
Start count
Start count
Addition
Addition
Overflow occurs
Set OVIR flag
Reverse POUT
bit value
Overflow occurs
Set OVIR flag
Reverse POUT
bit value
Discontinue count
Discontinue operation
455
CHAPTER 16 PWC Timer
16.6.4
Pulse Width Measurement Mode Operation
The signal for pulse-width measurement is input from the PWI pin.
The pulse-width measurement mode includes the single measurement mode in which
the count is performed only once and continuous measurement mode in which the
pulse width is continuously measured.
■ Single Measurement Mode and Continuous Measurement Mode
The differences between the single measurement mode and continuous measurement mode are as follows:
● Single measurement mode
When the first count end edge is input, the timer discontinues the count, the count end flag (EDIR) of
PWCSH0/PWCSH1 is set, and the subsequent measurement is not performed. However, if a timer restart
is also specified, the timer state changes to measurement start edge wait state.
● Continuous measurement mode [H/L pulse-width measurement mode]
When the count end edge is input, the count end flag (EDIR) of PWCSH0/PWCSH1 is set, the timer count
result is transferred to PWC0/PWC1, and the timer may continue incrementing the count in a free-run state.
When the next count start edge is input, the timer is cleared to "0000H" and the pulse-width count is started.
Notes:
When the count end edge is input and the timer enters a free-run state, the timer may overflow and the
OVIR flag may be set. In the H/L pulse-width measurement mode, do not use the OVIR flag to
measure the pulse-width time.
[All edge-to-edge pulse-width measurement mode, division period measurement mode, rising edge-torising edge measurement mode, and falling edge-to-falling edge measurement mode]
When the count end edge (count start edge) is input, the count end flag (EDIR) of PWCSH0/PWCSH1
is set, the timer count result is transferred to PWC0/PWC1, the timer is cleared to "0000H" and the
count is restarted.
■ Measurement Result Data
Handling of the measurement result, timer value, and PWC0/PWC1 function varies with the single
measurement mode and continuous measurement mode as follows:
● Single measurement mode
When PWC0/PWC1 is read during timer operation, the current timer value is read.
When PWC0/PWC1 is read after termination of measurement, the measurement results are read.
456
CHAPTER 16 PWC Timer
● Continuous measurement mode
At termination of measurement, the timer measurement results are transferred to PWC0/ PWC1.
When PWC0/ PWC1 is read, the previous measurement results are read. While measurement is in
progress, the previous measurement results are stored in PWC0/ PWC1. During measurement, the timer
value cannot be read.
In continuous measurement mode, unless the previous measurement results are read before completion of
the next measurement, a new measurement result overwrites the existing value. The error flag (ERR) of
PWCSH0/PWCSH1 is set. When PWC0/ PWC1 is read, the error flag (ERR) is cleared automatically.
■ Minimum Input Pulse Width
The pulse must be input to the pulse-width count input pin (PWI0/PWI1) longer than the following
minimum input pulse width.
Pulse width: 2 machine cycles (0.125 µs or more for the machine clock at 16 MHz)
However, the input pulse that is shorter than the above specification may also be recognized as a valid
pulse.
■ Calculating Pulse Width/period
The pulse width or pulse period of the measurement object is calculated based on the count result read from
PWC0/PWC1 at the end of a count as follows.
TW...... Measured pulse width or pulse period (µs)
TW = n x t / Div (µs)
n ...... Measurement result contained in PWC0/PWC1
t ...... Count clock period (µs)
Div ...... Division rate set in the division rate register (DIV0/DIV1)
(a value of "1" is used in a mode other than the division count mode)
■ Pulse Width/period Measurement Range
The range of the pulse width/period that can be measured depends on the count clock and division rate of
an input divider.
Table 16.6-5 lists the measurement range for the machine cycle (indicated by φ) at 16 MHz
Table 16.6-5
Pulse Width Measurement Range
Division rate
DIV1,
DIV0
No division
-
Divide-by 4
00B
0.125 µs to 4.10 ms [62.5 ns]
0.125 µs to 16.38 ms [0.25 µs] 0.125 µs to 32.75 ms [500 ns]
Divide-by 16
01B
0.125 µs to 1024 µs [15.6 ns]
0.125 µs to 4.10 ms [62.5 ns]
0.125 µs to 8.19 ms [125 ns]
Divide-by 64
00B
0.125 µs to 256 µs [3.91 ns]
0.125 µs to 1024 µs [15.6 ns]
0.125 µs to 2.048 ms [31.25 ns]
Divide-by 256
11B
0.125 µs to 64 µs [0.98 ns]
0.125 µs to 256 µs [3.91 ns]
0.125 µs to 512 µs [7.81 ns]
CKS1,CKS0=00B (φ/4)
CKS1,CKS0=01B (φ/16)
0.125 µs to 16.38 ms [0.25 µs] 0.125 µs to 65.5 ms [1.0 µs]
CKS1,CKS0=10B (φ/32)
0.125 µs to 131 ms [2 µs]
(Note) The number in [ ] indicates the resolution per bit.
457
CHAPTER 16 PWC Timer
■ Interrupt Request Generation
In the pulse-width measurement mode, the following two interrupt requests can be generated:
● Timer overflow interrupt request
If an overflow occurs during a count, the overflow flag is set. When the overflow interrupt request is
enabled, an interrupt request is generated.
● Measurement termination interrupt request
When the measurement termination edge is detected, the count end flag (EDIR) of PWCSH0/PWCSH1 is
set. If the measurement termination interrupt is enabled, an interrupt request is generated.
The measurement termination flag (EDIR) is automatically cleared when PWC0/ PWC1 is read.
■ Measurement Mode and Measurement Operation
Table 16.6-6 lists measurement mode operations.
Table 16.6-6
Measurement Mode Operation (1/2)
Measurement mode MOD2 MOD1 MOD0
Measurement operation
w
H pulse-width
measurement
1
0
1
Start of
measurement
w
Termination of
measurement
Termination of
measurement
Start
The H period width is measured.
Start of measurement:
Termination of measurement:
When the rising edge is detected
When the falling edge is detected
w
L pulse-width
measurement
1
1
0
Start of
measurement
w
Termination of
measurement
Termination of
measurement
Start
The L period width is measured.
Start of measurement:
End of measurement:
w
Rising edge-to-rising
edge period
measurement
Start of
measurement
1
0
When the falling edge is detected
When the rising edge is detected
w
Termination of
measurement
Start
0
w
Termination
Start
Termination
The rising edge-to-rising edge time is measured.
Start of measurement:
Termination of measurement:
458
When the rising edge is detected
When the rising edge is detected
CHAPTER 16 PWC Timer
Table 16.6-6
Measurement Mode Operation (2/2)
Measurement mode MOD2 MOD1 MOD0
Measurement operation
w
Start of
measurement
Falling edge-to-falling
edge period
measurement
1
1
w
Termination of
measurement
Start
w
Termination
Termination
Start
1
The falling edge-to-falling edge time is measured.
Start of measurement:
Termination of measurement:
w
Start of
measurement
All edge pulse-width
measurement
0
1
When the falling edge is detected
When the falling edge is detected
w
Termination of
measurement
Start
0
w
Termination
Start
Termination
The width between continuous input edges is measured.
Start of measurement:
Termination of measurement:
When the edge is detected
When the edge is detected
φ
w
Start of
measurement
Division
measurement
0
1
1
w
Termination of
measurement
Start
w
Termination
(Divided by 4 in the above example.)
The input pulse is divided by the division rate set in the division rate
register (DIVR), and the measurement period is obtained as a result.
Start of measurement:
The falling edge is detected after
the operation is started.
Termination of measurement:
One period of division signal ends.
W: Pulse width being measured
In all modes, the timer does not start count during the period from the start of measurement to input of
measurement start edge. After the measurement start edge is input, the timer is cleared to "0000H", and the
count is incremented at each count clock until the measurement termination edge is input.
When the measurement termination edge is input, the following operations are executed
(1) The count end flag (EDIR) of PWCSH0/PWCSH1 is set.
(2) The timer stops count operation (except if the timer is restarted at the same time or
continuous measurement mode of the H/L pulse-width measurement is used).
(3)Continuous measurement mode: The timer value (measurement result) is transferred to PWC0/PWC1.
(4) Single measurement mode: Measurement is terminated (except if the timer is restarted at
the same time).
If all edge-to-edge pulse-width measurement, period measurement, falling edge-to-falling edge period
measurement, or rising edge-to-rising edge period measurement is done in continuous measurement mode,
the termination edge becomes the next measurement start edge.
459
CHAPTER 16 PWC Timer
■ Flowchart of Pulse-width Measurement Operation
Figure 16.6-6 Flowchart of Pulse-width Measurement Mode Operation
Setting
-Select count clock
-Select operation mode and timer mode
-Clear interrupt flag
-Enable interrupt
Restart
Start by STRT bit
Continuous measurement mode
Detect count start page
Single operation mode
Detect count start page
Clear timer
Clear timer
Start count
Start count
Addition
Addition
Overflow occurs
Set OVIR flag
Detect count end edge
Set EDIR flag
Discontinue count*
Transfer timer value to PWC
Overflow occurs
Set OVIR flag
Detect count end edge
Set EDIR flag
Discontinue count*
Discontinue operation
*: Except continuous measurement mode of H/L pulse-width measurement
460
CHAPTER 16 PWC Timer
16.7
Usage Notes on the PWC Timer
Notes on using the PWC timer are given below.
■ Usage Notes on the PWC Timer
● Notes about using a program for setting
• Changing the following PWCS0/PWCS1 bit values is prohibited during timer operation. The bit values
are changed only before the timer is started or after the operation is discontinued.
[bit7, bit6] CKS1 and CKS0: Clock selection bits
[bit3] S/C: Measurement mode (single or continuous) selection bit
[bit2 to bit0] MOD2, MOD1, and MOD0: Operation mode and measurement edge selection bits
Note that the value of pulse output level indication bit (POUT: bit8) remains unchanged even if the bit
is written during timer operation.
• Changing the DIV0/DIV1 value is prohibited during timer operation. Change the DIV0/DIV1 value
before the timer is started or after the operation has stopped.
• Setting the clock selection bits CKS1 and CKS0 of PWC control status register (PWCSL0/PWCSL1) to
11B is prohibited.
• The PWC0/PWC1 and timer values are determined when the timer is set in the one-shot mode or after
the operation is terminated in reload timer mode. Therefore, always set the values after the timer is
used.
• The PWC0/PWC1 value is undefined if the timer is set in reload timer mode after the operation is
discontinued in the one-shot mode. Therefore, always set the value before the timer is used.
• To change the mode from pulse-width measurement mode to timer mode, always set the value in
PWC0/PWC1 before the timer has started.
• When division period measurement mode is used in pulse-width measurement mode, the input pulse is
divided. Note that the pulse width calculated from the count result becomes a mean.
• During continuous measurement in pulse-width measurement mode, the division circuit for an internal
count clock is not cleared, and the number of edges smaller than the count clock is added to the count
result.
461
CHAPTER 16 PWC Timer
● Notes about using a program for status checking
• In timer mode, the value of the measurement termination interrupt request flag (EDIR) of PWCSH0/
PWCSH1 is insignificant. Therefore, always set "0" in the count end interrupt request (EDIE) enable bit
of PWCSH0/PWCSH1.
• The STRT and STOP bits of PWC control status register (PWCSH0/PWCSH1) are dependent on
whether they are read or written (see the details of registers). Read modify write instruction always
reads the bits as 11B. So bit manipulation instruction cannot be used to read the operation state.
However, a bit manipulation instruction (bit clear instruction) can be used to start or stop the timer by
writing the STRT or STOP bit.
• In the pulse-width measurement mode, the measurement start edge causes the timer to be cleared, and
the previous timer data is insignificant.
● Notes about pulse input to the pulse width measurement input pin
• Minimum pulse width is divide-by 2 of machine cycle (0.125 µs or more for the machine cycle at 16 MHz)
• Maximum input frequency is divide-by 4 of machine cycle (4 MHz or less for the machine cycle at 16 MHz)
If a pulse width smaller than the above or a frequency larger than the above is input, the timer operation
is not guaranteed. A noise violating the above constraint and appearing in the input signal must be
reduced.
• If a pulse width smaller than the above or a frequency larger than the above is input, the timer operation
is not guaranteed. A noise violating the above constraint
● Notes about restart the timer during operation
• If the timer is restarted when an overflow occurs in reload timer mode, the timer is restarted but the
overflow flag (OVIR) is set and the POUT bit is reversed (that is, the same operation as the normal
overflow is executed).
• If the timer is restarted when the measurement termination edge is detected in one-shot pulse-width
measurement mode, the timer is restarted and enters measurement start edge wait state but the
measurement termination flag (EDIR) is also set.
• If the timer is restarted when the measurement termination edge is detected in continuous pulse-width
measurement mode, the timer is restarted and enters the measurement start edge wait state, the count
termination flag (EDIR) is set, and the measurement results are transferred to PWC0/PWC1.
• To restart the timer during operation, note the flag (OVIR, EDIR) operations to generate interrupts and
exercise other controls.
462
CHAPTER 16 PWC Timer
● Notes about interrupts
• When the OVIR bit of the PWC control status register (PWCSH0/PWCSH1) is set to "1" and an
interrupt request is enabled (PWCSH0/PWCSH1:OVIE = 1), control cannot be returned from interrupt
processing. Always clear the OVIR bit.
• When the EDIR bit of the PWC control status register (PWCSH0/PWCSH1) is set to "1" and an
interrupt request is enabled (PWCSH0/PWCSH1:EDIE = 1), control cannot be returned from interrupt
processing. Always clear the OVIR bit.
• Since the PWC timer shares an interrupt vector with other resource, interrupt causes must be checked
carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the PWC timer, shared resource interrupts must be disabled.
463
CHAPTER 16 PWC Timer
16.8
Sample Programs for the PWC Timer
This section contains sample programs for the PWC timer.
■ Sample Program for the PWC Timer
● Processing
• An output PWO0 of 30.6 Hz is generated with PWC timer 0.
• The PWC is used in reload timer mode to repeatedly generate an overflow interrupt.
• EI2OS is not used.
• 16 MHz is used for the machine clock, and 0.25 µs is used for the count clock.
● Coding example
ICR01
EQU
0000B1H
;Interrupt control register for the PWC timer
PWCS0
EQU
000008H
;PWC control status register
PWC0
EQU
00000AH
;PWC data buffer register
OVIR
EQU
PWCS0:11
;Interrupt request flag bit
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
;Assumes that stack pointer (SP) has already been
initialized
AND
CCR,#0BFH
;Interrupt disable
MOV
I:ICR01,#00H
;Interrupt level 0 (strongest)
MOVW
I:PSC0,#0FF00H
;Sets the reload value
MOVW
I:PWCS0,#4409H
;Sets reload timer mode, 0.25µ s clock
;Enable PWC output
;Sets overflow interrupt
;Clears interrupt flag and starts PWC timer
MOV
OR
LOOP:
ILM,#07H
CCR,#40H
;Sets ILM in PS to level 7
;Interrupt enable
MOV
A,#00H
;Endless loop
MOV
A,#01H
;
BRA
LOOP
;
;-------Interrupt program-------------------------------------------------------------------------------------------WARI:
CLRB
;
464
:
I:OVIR
;Clears interrupt request flag
CHAPTER 16 PWC Timer
;
User processing
;
:
RETI
CODE
;Returns from interrupt
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------VECT
VECT
CSEGABS=0FFH
ORG
0FFC8H
DSL
WARI
ORG
0FFDCH
DSL
START
DB
00H
;Sets vector for interrupt #13 (0DH)
;Sets reset vector
;Sets single-chip mode
ENDS
END
START
465
CHAPTER 16 PWC Timer
466
CHAPTER 17
UART
This chapter explains the functions and operation of
UART.
17.1 Overview of UART
17.2 Block Diagram of UART
17.3 UART Pins
17.4 UART Registers
17.5 UART Interrupts
17.6 UART Baud Rates
17.7 Operation of UART
17.8 Usage Notes on UART
17.9 Sample Program for UART
467
CHAPTER 17 UART
17.1
Overview of UART
UART is a general-purpose serial data communication interface for performing
synchronous or asynchronous (start-stop synchronization) communication with
external devices. The UART has a normal bidirectional communication function (normal
mode), additionally the master-slave communication function (multiprocessor mode) is
only available for the master system.
■ UART Functions (× 2)
● UART functions
UART is a general-purpose serial data communication interface for transmitting serial data to and receiving
data from another CPU and peripheral devices. It has the functions listed in Table 17.1-1.
Table 17.1-1 UART Functions
Function
Data buffer
Full-duplex, double buffering
Transfer mode
• Clock synchronous
• Clock asynchronous (start-stop synchronization)
Baud rate
• A dedicated baud rate generator is provided. Eight settings can be selected
• An external clock can be input
• Internal clock (internal clocks supplied from 16-bit reload timer 0 can be used)
Data length
• 7 bits (in asynchronous normal mode only)
• 8 bits
Signal mode
Non-return to zero (NRZ)
Reception error detection
• Framing error
• Overrun error
• Parity error (cannot be detected in multiprocessor mode)
Interrupt request
• Reception interrupt (reception completion and reception error detection)
• Transmission interrupt (transmission completion)
• Extended intelligent I/O service (EI2OS) is available for both transmission and
reception interrupts
Master-slave communication
function (multiprocessor mode)
One-to-n communication (one master to n slaves) can be performed (this function is
supported only for the master system)
Note:
468
During clock synchronous transfer, start and stop bits are not added so only data is transferred in
UART.
CHAPTER 17 UART
Table 17.1-2 UART Operation Mode
Data length
Operation mode
0
Normal mode
1
Multiprocessor
2
Normal mode
When parity is
disabled
When parity is
enabled
7 or 8 bits
8+1*1
bits
8 bits
Synchronization
on mode
Stop bit length
Asynchronous
–
Asynchronous
–
Synchronous
1 or 2 bits *2
None
– : Setting not possible.
*1: "+1" indicates the address/data selection bit (A/D) for communication control.
*2: During reception, only one stop bit can be detected.
■ UART Interrupt and EI2OS
Table 17.1-3 UART Interrupt and EI2OS
Interrupt control register
Interrupt cause
Interrupt
number
Vector table address
EI²OS
Register
name
Address
Lower
Upper
Bank
UART1 reception
interrupt
#37(25H)
ICR13
0000BDH
FFFF68H
FFFF69H
FFFF6AH
UART1 transmission
interrupt
#38(26H)
ICR13
0000BDH
FFFF64H
FFFF65H
FFFF66H
UART0 reception
interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
UART0 transmission
interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
∆
∆
: Provided with a function that detects a UART reception error and stops EI2OS
∆ : Usable when ICR13 and ICR14 or interrupt causes that share an interrupt vector are not used
469
CHAPTER 17 UART
17.2
Block Diagram of UART
UART consists of the following 11 blocks, the block diagram is shown in Figure 17.2-1.
■ Block Diagram of UART
Figure 17.2-1 Block Diagram of UART
From
communication
prescaler
Reception interrupt
#39 (27H)*
<#37 (25H)*>
Baud rate
generator
P42/SCK0
<P62/SCK1> External clock
Reception control
circuit
Transmission control
circuit
Start bit detect
circuit
Transmission
start circuit
P40/SIN0
<P60/SIN1>
Reception status
judgment circuit
Reception bit
counter
Transmission bit
counter
Reception parity
counter
Transmission
parity counter
Reception shifter
Start of transmission
Control bus
Reception clock
End of reception
Clock
selection
circuit
16-bit reload timer
Transmission
interrupt
#40 (28H)*
<#38 (26H)*>
Transmission clock
P41/SOT0
<P61/SOT1>
Transmission shifter
SIDR0/SIDR1
SODR0/SODR1
EI2OS reception error
signal (to CPU)
F2MC-16LX bus
SMR0/SMR1
register
*: Interrupt number
470
MD1
MD0
CS2
CS1
CS0
RST
SCKE
SOE
SCR0/SCR1
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR0/SSR1
register
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
Control signal
CHAPTER 17 UART
● Clock selector
The clock selector selects the dedicated baud rate generator, external input clock, or internal clock (clock
supplied from the 16-bit reload timer) as the transmitting and receiving clocks.
● Reception control circuit
The reception control circuit consists of a received bit counter, start bit detection circuit, and received
parity counter. The received bit counter counts receive data bits. When reception of one data item for the
specified data length is complete, the received bit counter generates a reception interrupt request. The start
bit detection circuit detects start bits from the serial input signal. When the circuit detects a start bit, it
writes data in the SIDR1 register by shifting at the specified transfer rate. The received parity counter
calculates the parity of the receive data.
● Transmission control circuit
The transmission control circuit consists of a transmission bit counter, transmission start circuit, and
transmission parity counter. The transmission bit counter counts transmission data bits. When transmission
of one data item of the specified data length is complete, the transmission bit counter generates a
transmission interrupt request. The transmission start circuit starts transmission when data is written to
SODR0/SODR1. The transmission parity counter generates a parity bit for data to be transmitted when
parity is enabled.
● Reception shift register
The reception shift register fetches receive data input from the SIN pin, shifting the data bit by bit. When
reception is complete, the reception shift register transfers receive data to the SIDR0/SIDR1 register.
● Transmission shift register
The transmission shift register transfers data written to the SODR0/SODR1 register to itself and outputs the
data to the SOT pin, shifting the data bit by bit.
● Mode control register 1 (SMC0/SMC1)
This register performs the following operations:
• Selecting a UART operation mode
• Selecting a clock input source
• Setting up the dedicated baud rate generator
• Selecting a clock rate (clock division value) when using the dedicated baud rate generator
• Specifying whether to enable serial data output to the corresponding pin
• Specifying whether to enable clock output to the corresponding pin
471
CHAPTER 17 UART
● Control register 1 (SCR0/SCR1)
This register performs the following operations:
• Specifying whether to provide parity bits
• Selecting parity bits
• Specifying a stop bit length
• Specifying a data length
• Selecting a frame data format in mode 1
• Clearing a flag
• Specifying whether to enable transmission
• Specifying whether to enable reception
● Status register 1 (SSR0/SSR1)
This register checks the transmission and reception status and error status, and enables and disables
transmission and reception interrupt requests.
● Input data register 1 (SIDR0/SIDR1)
This register retains receive data. Serial input data is converted and stored in this register.
● Output data register 1 (SODR0/SODR1)
This register sets transmission data. Data written to this register is converted to serial data and output.
472
CHAPTER 17 UART
17.3
UART Pins
This section describes the UART pins and provides a pin block diagram.
■ UART Pins
The UART pins also serve as general ports. Table 17.3-1 lists the pin functions, I/O formats and settings
required to use UART.
Table 17.3-1 UART Pins
I/O format
Pin function
P40/SIN0
Port 4 I/O or serial
data input
Set as an input port
(DDR4: bit0 = 0)
P41/SOT0
Port 4 I/O or serial
data output
Set to output enable mode
(SMR0: SOE = 1)
CMOS output
and CMOS
hysteresis input
P42/SCK0
Pull-up
Not provided
Standby control
Setting required to use
pin
Pin name
Provided
Port 4 I/O or serial
clock input/output
Set as an input port when a
clock is input
(DDR4: bit2 = 0)
Set to output enable mode
when a clock is output
(SMR0: SCKE = 1)
P60/SIN1
Port 6 I/O or serial
data input
Set as an input port
(DDR6: bit0 = 0)
P61/SOT1
Port 6 I/O or serial
data output
Set to output enable mode
(SMR1: SOE = 1)
CMOS output
and CMOS
hysteresis input
P62/SCK1
Port 6 I/O or serial
clock input/output
Not provided
Provided
Set as an input port when a
clock is input
(DDR6: bit2 = 0)
Set to output enable mode
when a clock is output
(SMR1:SCKE = 1)
473
CHAPTER 17 UART
■ Block Diagram of UART Pins
Figure 17.3-1 Block Diagram of UART Pins
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
474
Standby control (SPL = 1)
CHAPTER 17 UART
17.4
UART Registers
The following figure shows the UART registers.
■ UART Registers
Figure 17.4-1 UART Registers
Serial Control Register
15
bit
Address: ch.0 000021H
ch.1 000025H
14
13
12
11
10
9
8
SCR0/SCR1
PEN
P
R/W
0
R/W
0
Read/write
Initial value
SBL
CL
R/W
0
A/D
R/W
0
REC
RXE
TXE
W
1
R/W
0
R/W
0
R/W
0
Serial Mode Register
bit
7
6
5
4
3
2
1
0
MD0
CS2
CS1
CS0
RST
SCKE SOE
SMR0/SMR1
Address: ch.0 000020H
ch.1 000024H
MD1
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14
13
12
11
10
R/W
0
R/W
0
UART Status Register
bit
Address: ch.0 000023H
ch.1 000027H
Read/write
Initial value
15
9
8
SSR0/SSR1
PE
ORE
R
0
R
0
FRE
RDRF TDRE
R
0
R
0
R
1
BDS
RIE
TIE
R/W
0
R/W
0
R/W
0
3
2
UART Input Data Register / Output Data Register
bit
Address: ch.0 000022H
ch.2 000026H
Read/write
Initial value
7
6
5
4
1
0
SIDR0,SIDR1 /
SODR0,SODR1
D7
D6
D5
D4
D3
D2
D1
D0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Clock Division Control Register
bit 15
Address: ch.0 000019H
ch.1 00001BH
Read/write
Initial value
14
13
12
11
10
9
8
CDCR0/CDCR1
MD
DIV2
DIV1
DIV0
R/W
0
R/W
0
R/W
0
R/W
0
475
CHAPTER 17 UART
17.4.1
Serial Control Register (SCR0/SCR1)
This register specifies parity bits, selects the stop bit and data lengths, selects a frame
data format in mode 1, clears the reception error flag, and specifies whether to enable
transmission and reception.
■ Serial Control Register (SCR0/SCR1)
Figure 17.4-2 Serial Control Register (SCR0/SCR1)
Address
bit
15
c h . 0 : 0 0 0 0 2 1H
c h . 1 : 0 0 0 0 2 5H PEN
14
13
12
11
P
SBL
CL
A/D
R/W R/W R/W R/W
10
9
8
(SMR)
Initial value
0 0 0 0 0 1 0 0B
R/W R/W R/W R/W
Transmission enable bit
0
Disables transmission
1
Enables transmission
RXE
Reception enable bit
0
Disables reception
1
Enables reception
REC
Reception error flag clear bit
0
Clears the FRE, ORE, and PE flags
1
Has no effect on the others
A/D
Address/data selection bit
0
Data frame
1
Address frame
CL
Data length selection bit
0
7 bits
1
8 bits
SBL
Stop bit length selection bit
0
1-bit length
1
2-bit length
P
Parity selection bit
Enabled only when parity is provided (PEN=1)
0
Even parity
1
Odd parity
PEN
476
0
REC RXE TXE
TXE
R/W : Read/Write
: Initial value
7
Parity enable bit
0
Provides no parity bit
1
Provides a parity bit
CHAPTER 17 UART
Table 17.4-1 Serial Control Register (SCR0/SCR1)
Bit name
Function
bit15
PEN:
Parity enable bit
• This bit selects whether to add a parity bit during transmission in serial data inputoutput mode or to detect it during reception.
(Note)
No parity can be used in operation modes 1 and 2. Therefore, fix this bit to "0".
bit14
P:
Parity selection bit
• When parity is provided (PEN = 1), this bit selects an even or odd parity.
bit13
SBL:
Stop bit length
selection bit
• This bit selects the length of the stop bits or the frame end mark of send data in
asynchronous transfer mode.
(Note)
During reception, only the first bit of the stop bits is detected.
bit12
CL:
Data length selection
bit
• This bit specifies the length of send and receive data.
(Note)
Seven bits can be selected in operation mode 0 (asynchronous) only. Be sure to
select eight bits (CL = 1) in operation mode 1 (multiprocessor mode) and
operation mode 2 (synchronous).
bit11
A/D:
Address/data selection
bit
• Specify the data format of a frame to be sent or received in multiprocessor mode
(mode 1).
• Select usual data when this bit is "0", and select address data when the bit is "1".
REC:
Reception error flag
clear bit
• This bit clears the FRE, ORE and PE flags of the status register (SSR).
• Write "0" to this bit to clear the FRE, ORE and PE flag. Writing "1" to this bit has
no effect on the others.
(Note)
If UART is active and a reception interrupt is enabled, clear the REC bit only when
the FRE, DRE or PE flag indicates 1.
RXE:
Reception enable bit
• This bit controls UART reception.
• When this bit is "0", reception is disabled. When it is "1", reception is enabled.
(Note)
If this bit is cleared during reception, reception can only be disabled until the
reception of current frame is completed and the reception data is stored in the
reception data is stored in the input data register SIDR0/SIDR1.
TXE:
Transmission enable
bit
• This bit controls UART transmission.
• When this bit is "0", transmission is disabled. When the bit is "1", transmission is
enabled.
(Note)
If this bit is cleared during transmission, transmission can only be disabled until all
data in the output data register SOR0/SOR1 has been transmitted.
bit10
bit9
bit8
477
CHAPTER 17 UART
17.4.2
Serial Mode Register (SMR0/SMR1)
This register selects an operation mode and baud rate clock and specifies whether to
enable output of serial data and clocks to the corresponding pin.
■ Serial Mode Register (SMR0/SMR1)
Figure 17.4-3 Serial Mode Register (SMR0/SMR1)
Address
bit 15
ch.0:000020H
ch.1:000024H
8
(SCR)
7
6
5
4
MD1 MD0 CS2
3
Initial value
0 0 0 0 0 0 0 0B
R/W R/W R/W
Serial data output enable bit
Uses the pin as a general I/O port
1
Uses the pin as the serial data output pin of UART
Serial clock output enable bit
0
Uses the pin as a general I/O port or clock input pin of UART
1
Uses the pin as the clock output pin of UART
RST
UART reset bit
0
No effect
1
resets UART
CS2~CS0
Clock selection bit
"000B"~"100B"
Baud rate by dedicated baud rate generator
"101B"
Disables setting.
"110B"
Baud rate by internal timer
(16-bit reload timer 0)
"111B"
Baud rate by external clock
Operation mode selection bit
MD1 MD0
478
0
0
SCKE
R/W : Enables read and write.
: Initial value
1
CS1 CS0 RST SCKE SOE
R/W R/W R/W R/W R/W
SOE
2
Operation mode
0
0
0
Asynchronous (normal mode)
0
1
1
1
0
2
Asynchronous (multiprocessor mode)
Synchronous (normal mode)
1
1
-
Disables setting.
CHAPTER 17 UART
Table 17.4-2 Serial Mode Register (SMR0/SMR1)
Bit name
Function
MD1, MD0: Operation
mode selection bits
• These bits select an operation mode.
(Note)
Operation mode 1 (multiprocessor mode) can be used only from the master
system during master-slave communication. UART cannot be used from the
slave system because it has no address/data detection function during reception.
bit5
to
bit3
CS2 to CS0:
Clock selection bits
• These bits select the baud rate clock source. When the dedicated baud rate
generator is selected, the baud rate is determined by the value of these bits.
• When the dedicated baud rate generator is selected, six baud rates can be
selected for asynchronous/synchronous transfer mode. With the baud rate
generated by internal and external timer, there are totally eight baud rate
selections.
• Input clocks can be selected from external clocks (SCK0/SCK1 pin), 16-bit
reload timer 0, and the dedicated baud rate generator.
bit2
RST:
UART reset bit
• Writing "0" to this bit has no effect.
• Writing "1" to this bit resets the UART.
• Always read as "0".
SCKE:
Serial clock output
enable bit
• This bit controls the serial clock input-output ports.
• When this bit is "0", the P42/SCK0 and P62/SCK1 pins operate as general inputoutput ports (P42 and P62) or serial clock input pins. When this bit is "1", the
pins operate as serial clock output pins.
(Note)
• When using the P42/SCK0 and P62/SCK1 pins as serial clock input (SCKE =
0) pins, set the P40 and P62 as input ports. Also, select external clocks
(SMR0/SMR1: CS2 to CS0 = 111B) using the clock selection bits.
• When using the pins as serial clock output (SCKE = 1) pins, select clocks
other than external clocks (other than SMR0/SMR1: CS2 to CS0 = 111B).
(Reference)
When the SCK0/SCK1 pin is assigned to serial clock output (SCKE = 1), it
functions as the serial clock output pin regardless of the status of the general
input-output ports.
SOE:
Serial data output
enable bit
• This bit enables or disables the output of serial data.
• When this bit is "0", the P41/SOT0 and P61/SOT1 pins operate as general inputoutput ports (P41 and P61). When this bit is "1", the P41/SOT0 and P61/SOT1
pins operate as serial data output pins (SOT0/SOT1).
(Reference)
When serial data is output (SOE = 1), the enabled, the P41/SOT0 and P61/SOT1
pins function as SOT0/SOT1 pins regardless of the status of general inputoutput ports (P41 and P61).
bit7,
bit6
bit1
bit0
479
CHAPTER 17 UART
17.4.3
Serial Status Register (SSR0/SSR1)
This register checks the transmission and reception status and error status, and
enables and disables the transmission and reception interrupts.
■ Serial Status Register (SSR0/SSR1)
Figure 17.4-4 Serial Status Register (SSR0/SSR1)
Address bit
ch.0:000023 H
ch.1:000027 H
15
PE
R
14
13
12
11
10
9
ORE FRE RDRF TDRE BDS RIE
R
R
R
R
8
TIE
7
0
(SIDR/SODR)
R/W R/W R/W
TIE
Transmission interrupt request enable bit
0
Disables output of transmission interrupt request
1
Enables output of transmission interrupt request
RIE
Reception enable bit
0
Disables output of reception interrupt request
1
Enables output of reception interrupt request
BDS
Transfer direction selection bit
0
LSB first (transfer from the least significant bit)
1
MSB first (transfer from the most significant bit)
TDRE
Transmission data empty flag bit
0
Transmission data exists
(Writing transmission data is not allowed)
1
Transmission data does not exist.
(Writing transmission data is allowed)
RDRF
Receive data full flag bit
0
No receive data exists
1
Receive data exists
Framing error flag bit
FRE
0
No framing error occurred
1
ORE
X
480
: Not used
: Indefinite
: Initial value
A framing error occurred
Overrun error flag bit
0
No overrun error occurred
1
An overrun error occurred
PE
R/W : Read/Write
R : Read only
Initial value
00001000B
Parity error flag bit
0
No parity error occurred
1
A parity error occurred
CHAPTER 17 UART
Table 17.4-3 Functions of Each Bit of Status Register (SSR0/SSR1)
Bit name
Function
bit15
PE:
Parity error flag bit
• This bit is set to "1" when a parity error occurs during reception and is cleared when
"0" is written to the RFC bit of the mode control register (SMR0/SMR1).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in input data register (SIDR0/SIDR1) is invalid when this flag is set.
bit14
ORE:
Overrun error flag bit
• This bit is set to "1" when an overrun error occurs during reception and is cleared
when "0" is written to the RFC bit of the mode control register (SMR0/SMR1).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in the input data register (SIDR0/SIDR1) is invalid when this flag is set.
bit13
FRE:
Framing error flag bit
• This bit is set to "1" when a framing error occurs during reception and is cleared
when "0" is written to the RFC bit of the mode control register (SMR0/SMR1).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in the input data register (SIDR0/SIDR1) is invalid when this flag is set.
bit12
RDRF:
Receive data full flag
bit
• This flag indicates the status of the input data register (SIDR0/SIDR1).
• This bit is set to "1" when receive data is loaded into SIDR0/SIDR1 and is cleared
to "0" when input data register SIDR0/SIDR1 is read.
• A reception interrupt request is output when this bit and the RIE bit are "1".
TDRE:
Transmission data
empty flag bit
• This flag indicates the status of output data register (SODR0/SODR1).
• This bit is cleared to "0" when transmission data is written to SODR0/SODR1 and
is set to "1" when data is loaded into the transmission shift register and transmission
starts.
• A transmission interrupt request is output when this bit and the RIE bit are "1".
(Note)
This bit is set to "1" (SODR0/SODR1 empty) as its initial value.
bit10
BDS:
Transfer direction
selection bit
• This bit selects whether to transfer serial data from the least significant bit (LSB
first, BDS = 0) or the most significant bit (MSB first, BDS = 1).
(Note)
The high-order and low-order sides of serial data are interchanged with each other
during reading from or writing to the serial data register. If this bit is set to another
value after the data is written to the SDR register, the data becomes invalid.
bit9
RIE:
Reception interrupt
request enable bit
• This bit enables or disables input of a request for transmission interrupt to the CPU.
• A reception interrupt request is output when this bit and the receive data flag bit
(DRRF) are 1 or this bit and one or more error flag bits (PE, ORE and FRE) are "1".
bit8
TIE:
Transmission interrupt
request enable bit
• This bit enables or disables output of a request for transmission interrupt to the
CPU.
• A transmission interrupt request is output when this bit and the TDRE bit are "1".
bit11
481
CHAPTER 17 UART
17.4.4
Input Data Register (SIDR0/SIDR1) and Output Data
Register (SOR0/SOR1)
The input data register (SIDR0/SIDR1) is a serial data reception register. The output
data register (SODR0/SODR1) is a serial data transmission register. Both SIDR0/SIDR1
and SODR0/SODR1 registers are located in the same address.
■ Input Data Register (SIDR0/SIDR1)
Figure 17.4-5 shows the bit configuration of input data register 1.
Figure 17.4-5 Input Data Register (SIDR0/SIDR1)
Serial input data register
bit
Address : 000022H
000026H
Read/write
Initial value
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
SIDR0
SIDR1
SIDR0/SIDR1 is a register that contains receive data. The serial data signal transmitted to the SIN0/SIN1
pin is converted in the shift register and stored there. When the data length is 7 bits, the uppermost bit (D7)
contains invalid data. When receive data is stored in this register, the receive data full flag bit (SSR0/
SSR1: RDRF) is set to "1". If a reception interrupt request is enabled at this point, a reception interrupt
occurs.
Read SIDR0/SIDR1 when the RDRF bit of the status register (SSR0/SSR1) is "1". The RDRF bit is
cleared automatically to "0" when SIDR0/SIDR1 is read.
Data in SIDR0/SIDR1 is invalid when a reception error occurs (SSR0/SSR1: PE, ORE or FRE = 1).
■ Output Data Register (SODR0/SODR1)
Figure 17.4-6 shows the bit configuration of the output data register.
Figure 17.4-6 Output Data Register (SODR0/SODR1)
Serial output data register
bit
Address : 000022H
000026H
Read/write
Initial value
482
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
SODR0
SODR1
CHAPTER 17 UART
When data to be transmitted is written to this register in transmission enable state, it is transferred to the
transmission shift register, then converted to serial data, and transmitted from the serial data output terminal
(SOT0/SOT1 pin). When the data length is 7 bits, the uppermost bit (D7) contains invalid data.
When transmission data is written to this register, the transmission data empty flag bit (SS0/SS1: TDRE) is
cleared to "0". When transfer to the transmission shift register is complete, the bit is set to "1". When the
TDRE bit is "1", the next piece of transmission data can be written. If output transmission interrupt
requests have been enabled, a transmission interrupt is generated. Write the next piece of transmission data
when a transmission interrupt is generated or the TDRE bit is "1".
Note:
SODR0/SODR1 is a write-only register and SIDR0/SIDR1 is a read-only register. These registers are
located in the same address, so the read value is different from the write value. Therefore,
instructions that perform a read-modify-write (RMW) operation, such as the INC/DEC instruction,
cannot be used.
483
CHAPTER 17 UART
17.4.5
Communication Prescaler Control Register (CDCR)
This register controls the division of machine clocks.
■ Communication Prescaler Control Register (CDCR)
The operation clocks of UART can be obtained by dividing machine clocks. UART is designed to obtain
certain baud rates for various machine cycles. Output from the communication prescaler is used for the
operation clocks of I/O extended serial interfaces. The CDCR bit configuration is shown below.
Figure 17.4-7 Communication Prescaler Control Register
Address bit 15
14
13
12
11
10
9
8
Initial value
000019H
00001BH
MD
—
—
—
—
DIV2
DIV1
DIV0
0XXXX000B
R/W
—
—
—
—
R/W
R/W
R/W
MD
X
: Indeterminate
: Initial value
—
484
: Not used
div
0
—
—
—
Setting not allowed
1
0
0
0
1
1
0
0
1
2
1
0
1
0
3
1
0
1
1
4
1
1
0
0
5
1
1
0
1
6
1
1
1
0
7
1
1
1
1
8
MD
R/W : Read and write
DIV2 DIV1 DIV0
Machine clock divide mode select
0
Stops the communication prescaler.
1
Operates the communication prescaler.
CHAPTER 17 UART
Table 17.4-4 Communication Prescaler Control Register
Bit name
Function
bit15
MD:
Machine clock divide mode select bit
• This bit is the operation enable bit of the communication prescaler.
• When "0" is set, the communication prescaler stops.
• When "1" is set, the communication prescaler operates.
bit14
to
bit12
Reserved bits
• Always read as "0".
DIV2 to DIV0:
Machine clock division bits
• These bits determines the machine clock division ratios.
• Division ratios can only be set when MD is "1".
(Note)
If division ratio is changed, wait 2 cycles as stabilization time
before starting communication.
bit10
to
bit8
485
CHAPTER 17 UART
17.5
UART Interrupts
UART uses both reception and transmission interrupts. An interrupt request can be
generated for either of the receive data is set in the input register (SIDR0/SIDR1), or a
reception error occurs and transmission data is transferred from output data register 1
(SODR0/SODR1) to the transmission shift register.
The extended intelligent I-O service (EI2OS) is available for these interrupts.
■ UART Interrupts
Table 17.5-1 lists the interrupt control bits and causes of UART
Table 17.5-1 Interrupt Control Bits and Interrupt Causes of UART
Operation mode
Reception/
Interrupt
transmission request flag bit 0
1
2
Reception
Transmission
Interrupt cause
RDRF
O
O
O
Loading receive data
into buffers (SIDR0/
SIDR1)
ORE
O
O
O
Overrun error
FRE
O
O
X
Framing error
PE
O
X
X
Parity error
TDRE
O
O
O
Empty transmission
buffer (SODR0/
SODR1)
Interrupt cause When interrupt request
enable bit
flag is cleared
Receive data is read
SSR0/SSR1:RIE
0 is written to the
reception error flag clear
bit (SSR0/SSR1: REC)
SSR0/SSR1:TIE
Transmission data is
written
O: Used
X: Not used
● Reception interrupt
If one of the following events occurs in reception mode, the corresponding flag bit of the status register is
set to "1":
• Data reception is complete (SSR0/SSR1: RDRF)
• Overrun error (SSR0/SSR1: ORE)
• Framing error (SSR0/SSR1: FRE)
• Parity error (SSR0/SSR1: PE)
When at least one of the flag bits is "1" and the reception interrupts are enabled (SSR0/SSR1: RIE = 1), a
reception interrupt request is output to the interrupt controller.
When the input data register (SIDR0/SIDR1) is read, the receive data full flag (SSR0/SSR1: RDRF) is
automatically cleared to "0". When "0" is written to the REC bit of the control register (SCR0/SCR1), all
the reception error flags (SSR0/SSR1: PE, ORE and FRE) are cleared to "0".
486
CHAPTER 17 UART
● Transmission interrupt
When transmission data is transferred from the output data register (SODR0/SODR1) to the transfer shift
register, the TDRE bit of the status register (SSR0/SSR1) is set to "1". When the transmission interrupts
have been enabled (SSR0/SSR1: TIE = 1), a transmission interrupt request is output to the interrupt
controller.
■ UART Interrupts and EI2OS
Table 17.5-2 UART Interrupts and EI2OS
Interrupt control register
Interrupt cause
Vector table address
Interrupt number
EI²OS
Register name
Address
Lower
Upper
Bank
UART1 reception
interrupt
#37(25H)
ICR13
0000BDH
FFFF68H FFFF69H FFFF6AH
UART1 transmission
interrupt
#38(26H)
ICR13
0000BDH
FFFF64H FFFF65H FFFF66H
UART0 reception
interrupt
#39(27H)
ICR14
0000BEH
FFFF60H FFFF61H FFFF62H
UART0 transmission
interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH FFFF5DH FFFF5EH
∆
∆
: Provided with a function that detects a UART reception error and stops EI2OS
∆ : Usable when interrupt causes that share the ICR13 and ICR14 or the interrupt vectors are not used
■ UART EI2OS Functions
UART has a circuit for operating EI2OS, which can be started up for either reception or transmission
interrupts.
● For reception
EI2OS can be used regardless of the status of other resources.
● For transmission
UART shares the interrupt registers (ICR13 and ICR14) with the UART reception interrupts. Therefore,
EI2OS can be started up only when no UART reception interrupts are used.
487
CHAPTER 17 UART
17.5.1
Reception Interrupt Generation and Flag Set Timing
The following are the reception interrupt causes: completion of reception (SSR0/SSR1:
RDRF) and occurrence of a reception error (SSR0/SSR1: PE, ORE, or FRE).
■ Reception Interrupt Generation and Flag Set Timing
Receive data is stored in input data register 1 (SIDR0/SIDR1) if a stop bit is detected (in operation mode 0
or 1) or the last bit of data is detected (in operation mode 2) during reception. If a reception error is
detected, the error flags (SSR0/SSR1: PE, ORE and FRE) are set, then the receive data flag (SSR0/SSR1:
RDRF) is set to "1". If one of the error flags is "1" in each mode, the SIDR0/SIDR1 register contains
invalid data.
● Operation mode 0 (asynchronous, normal mode)
The RDRF bit is set to "1" when a stop bit is detected. If a reception error is detected, the error flags (PE,
ORE and FRE) are set.
● Operation mode 1 (asynchronous, multiprocessor mode)
The RDRF bit is set to "1" when a stop bit is detected. If a reception error is detected, the error flags (ORE
and FRE) are set. Parity errors cannot be detected.
● Operation mode 2 (synchronous, normal mode)
The RDRF bit is set when the last bit of receive data (D7) is detected. If a reception error is detected, the
error flag (ORE) is set. Parity and framing errors cannot be detected. Figure 17.5-1 below shows the
reception operation and flag set timing.
Figure 17.5-1 Reception Operation and Flag Set Timing
Receive data
(operation mode 0)
ST
D0
D1
D5
D6
D7/P
SP
Receive data
(operation mode 1)
ST
D0
D1
D6
D7
A/D
SP
D0
D1
D4
D5
D6
D7
Receive data
(operation mode 2)
PE, ORE, FRE*
RDRF
A reception interrupt occurs.
*
: The PE flag cannot be used in mode 1
The PE and PRE flags cannot be used in mode 2
ST : Start bit
SP : Stop bit
A/D : Mode 2 (multiprocessor mode) address/data selection bit
● Reception interrupt generation timing
When the RDRF, PE, ORE or FRE flag is set to "1" in the reception interrupt enable state (SSR0/SSR1:
RIE = 1), reception interrupt requests (#37 and #39) are generated.
488
CHAPTER 17 UART
17.5.2
Transmission Interrupt Generation and Flag Set Timing
A transmission interrupt is generated when the next piece of data is ready to be written
to the output data register (SODR0/SODR1).
■ Transmission Interrupt Heneration and Flag Set Timing
The transmission data empty flag bit (SSR0/SSR1: TDRE) is set to "1" when data written to the output data
register (SODR0/SODR1) is transferred to the transmission shift register, and the next piece of data is
ready to be written. TDRE is cleared to "0" when transmission data is written to SODR0/SODR1. Figure
17.5-2 shows the transmission operation and flag set timing.
Figure 17.5-2 Transmission Operation and Flag Set Timing
[Operation modes 0 and 1]
SODR write
TDRE
An interrupt request is issued to the CPU.
SOT interrupt
SOT output
ST D0
D1 D2
D3
D4 D5
D6 D7
SP SP ST D0
A/D
D1 D2
D3
[Operation mode 2]
SODR write
TDRE
An interrupt request is issued to the CPU.
SOT interrupt
SOT output
ST: Start bit
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
D0 to D7: Data bits
SP: Stop bit
A/D: Address/data multiplexer
● Transmission interrupt request generation timing
If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR0/SSR1: TIE = 1), transmission
interrupt requests (#38 and #40) are generated.
Note:
A transmission completion interrupt is generated immediately after the transmission interrupts are
enabled (TIE = 1) because the TDRE bit is set to "1" as its initial value. TDRE is a read-only bit that
can be cleared only by writing new data to the output data register (SODR0/SODR1). Carefully
specify the transmission interrupt enable timing.
489
CHAPTER 17 UART
17.6
UART Baud Rates
One of the following can be selected as the UART transmitting/receiving block, the
block diagram show as below.
■ UART Baud Rate Selection
The baud rate selection circuit is designed as shown below. One of the following three types of baud rates
can be selected:
● Baud rates determined using the dedicated baud rate generator
UART has an internal dedicated baud rate generator. One of eight baud rates can be selected using the
mode control register (SMR0/SMR1).
An asynchronous or synchronous baud rate is selected using the machine clock frequency by setting the
CS2 to CS0 bits of the mode control register (SMR0/SMR1).
● Baud rates determined using the internal timer
The internal clock supplied from 16-bit reload timer 0 is used as it is (synchronous) or by dividing it by 16
(asynchronous) for the baud rate. Any baud rate can be set by setting the reload value.
● Baud rates determined using the external clock
The clock input from the UART clock pulse input pins (P42/SCK0 and P62/SCK1) is used as it is
(synchronous) or by dividing it by 16 (asynchronous) for the baud rate. Any baud rate can be set
externally.
490
CHAPTER 17 UART
Figure 17.6-1 Baud Rate Selection Circuit
SMR0/SMR1 : CS2 to CS0
(Clock selection bits)
[Dedicated baud rate generator]
3
Clock selector
CDCR0/CDCR1 : MD, DIV2 to DIV0
(Prescaler enable and selection bits)
When the bits
are 000B to 101B
4
φ
Frequency divider
(synchronous)
Frequency divider
(asynchronous)
Selects the internal fixed
division ratios
Machine clock prescaler
[Internal timer]
TMCSR0/TMCSR1 : CSL1, CSL0
2
When the bits
are 110B
Clock selector
φ
Down
counter
UF
1/1 (synchronous)
1/16 (asynchronous)
Baud rate
SCKI
φ/21 φ/23 φ/25
Prescaler
16-bit reload timer 0
When the bits
are 111B
[External clock]
P42/SCK0, P62/SCK1
Pin
1/1 (synchronous)
1/16 (asynchronous)
SMR0/SMR1 : MD1
(Synchronous or asynchronous clock selection)
φ : Machine clock frequency
491
CHAPTER 17 UART
17.6.1
Baud Rates Determined Using the Dedicated Baud Rate
Generator
This section describes the baud rates that can be set when the clock from the dedicated
baud rate generator is selected as the UART transfer clock.
■ Baud Rates determined using the Dedicated Baud Rate Generator
When the transfer clock is generated using the dedicated baud rate generator, the machine clock is divided
with the machine clock prescaler. The divided machine clock is then divided by the transfer clock division
ratio selected with the clock selector again.The machine clock division ratios are common to the
asynchronous and synchronous baud rates, but different values set internally are selected as the transfer
clock division ratio for the asynchronous and synchronous baud rates.
The actual transfer rate can be calculated using the following formulas:
asynchronous baud rate = φ × (prescaler division ratio) × (asynchronous transfer clock division ratio)
synchronous baud rate = φ × (prescaler division ratio) × (synchronous transfer clock division ratio)
φ : Machine clock frequency
● Division ratios for the prescaler (common to asynchronous and synchronous baud rates)
Each machine clock division ratio is selected using the DIV2 to DIV0 bits of the CDCR register as listed in
Table 17.6-1
Table 17.6-1 Selection of Each Division Ratio for the Machine Clock Prescaler
492
MD
DIV2
DIV1
DIV0
div
0
–
–
–
Setting not allowed
1
0
0
0
1
1
0
0
1
2
1
0
1
0
3
1
0
1
1
4
1
1
0
0
5
1
1
0
1
6
1
1
1
0
7
1
1
1
1
8
CHAPTER 17 UART
● Synchronous transfer clock division ratios
A division ratio for synchronous baud rates is selected using the CS2 to CS0 bits of the mode control
register (SMR0/SMR1) as listed in Table 17.6-2.
Table 17.6-2 Selection of Synchronous Baud Rate Division Ratios
CS2
CS1
CS0
CLK synchronization
Calculation formula
0
0
0
2 MHz
(φ ÷ div) / 1
0
0
1
1 MHz
(φ ÷ div) / 2
0
1
0
500 kHz
(φ ÷ div) / 4
0
1
1
250 kHz
(φ ÷ div) / 8
1
0
0
125 kHz
(φ ÷ div) / 16
1
0
1
62.5 kHz
(φ ÷ div) / 32
Note that the calculation is supposing that φ (machine cycle) = 16 MHz and div (machine clock division
ratio) = 8. The maximum baud rate is 1/8 machine clock.
● Asynchronous transfer clock division ratios
A division ratio for asynchronous baud rates is selected using the CS2 to CS0 bits of the mode control
register (SMR0/SMR1) as listed in Table 17.6-3.
Table 17.6-3 Selection of Asynchronous Baud Rate Division Ratios
CS2
CS1
CS0
Asynchronous (start-stop
synchronization)
0
0
0
76923 Hz
(φ ÷ div) / (8 × 13 × 2)
0
0
1
38461 Hz
(φ ÷ div) / (8 × 13 × 4)
0
1
0
19230 Hz
(φ ÷ div) / (8 × 13 × 8)
0
1
1
9615 Hz
(φ ÷ div) / (8 × 13 × 16)
1
0
0
500 kHz
(φ ÷ div) / (8 × 2 × 2)
1
0
1
250 kHz
(φ ÷ div) / (8 × 2 × 4)
Calculation formula
Note that the calculation is supposing that φ (machine clock) = 16 MHz, div (machine clock division ratio) = 1.
493
CHAPTER 17 UART
● Internal timer
When CS2 to CS0 are set to "110B" and the internal timer is selected, the formulas for calculating baud
rates (when using the reload timer) are as follows:
Asynchronous (start-stop synchronization): ( φ÷ N) / (16 × 2 × (n + 1))
CLK synchronization: ( φ÷N) / (2 × (n + 1))
N: Division ratio for the prescaler of 16-bit re-load timer count clock
n: reload value of the 16-bit reload timer
Note:
In mode 2 (CLK synchronization mode), SCK0/SCK1 is up to three clocks later than SCKI. A
logically attainable transfer rate is 1/3 of the system clock frequency. However, 1/4 of the system
clock frequency is recommended as taken from the actual specifications.
● External clock
When CS2 to CS0 are set to "111B" and the external clock is selected, note the following:
If the external clock frequency is specified as f, the following baud rates are assumed:
Asynchronous (start-stop synchronization): f/16
CLK synchronization: f
Note that the maximum external clock frequency f is 2 MHz.
494
CHAPTER 17 UART
17.6.2
Baud Rates Determined Using the Internal Timer (16-bit
Reload Timer 0)
This section describes the settings used when the internal clock supplied from 16-bit
reload timer 0 is selected as the UART transfer clock. It also shows the baud rate
calculation formulas.
■ Baud Rates determined using the Internal Timer (16-bit Reload Timer 0)
Writing 110B to the CS2 to CS0 bits of the mode control register (SMR0/SMR1) selects the baud rate
determined using the internal timer. Any baud rate can be set by specifying a prescaler division ratio and
reload value for 16-bit reload timer 0. Figure 17.6-2 shows the baud rate selection circuit for the internal
timer.
Figure 17.6-2 Baud Rate Selection Circuit for the Internal Timer (16-bit Reload Timer 0)
SMR0/SMR1 : CS2 to CS0 = 110B
(Selects the internal timer)
Clock selector
16-bit reload timer output
(the frequency is specified with
a prescaler division ratio and
reload value)
1/1 (synchronous)
1/16 (asynchronous)
Baud rate
SCKI
SMR0/SMR1 : MD1
(Synchronous or asynchronous clock selection)
● Baud rate calculation formulas
φ
Asynchronous baud rate =
φ
Synchronous baud rate =
bps
X (n + 1) x 2 x 16
X (n + 1) x 2
bps
φ: Machine clock frequency
X: Division ratio for the prescaler of 16-bit reload timer 0 (21, 23, 25)
n: Reload value for 16-bit reload timer 0 (0 to 65535)
495
CHAPTER 17 UART
● Examples of setting reload values (machine clock: 7.3728 MHz)
Table 17.6-4 Baud Rates and Reload Values
Reload value
Baud rate
(bps)
Clock asynchronous
(start-stop synchronization)
Clock synchronous
X=21(machine cycle
divided by 2)
X=23 (machine cycle
divided by 8)
X=21(machine cycle
divided by 2)
X=23 (machine cycle
divided by 8)
38400
2
–
47
11
19200
5
–
95
23
9600
11
2
191
47
4800
23
5
383
95
2400
47
11
767
191
1200
95
23
1535
383
600
191
47
9071
767
300
383
95
6143
1535
X: Division ratio for the prescaler of 16-bit reload timer 0
- : Setting not allowed
496
CHAPTER 17 UART
17.6.3
Baud Rates Determined Using the External Clock
This section describes the settings used when the external clock is selected as the
UART transfer clock. It also shows the baud rate calculation formulas.
■ Baud Rates determined using the External Clock
The following three settings are required to select the baud rate determined by using the external clock:
• Write 111B to the CS2 to CS0 bits of the mode control register (SMR0/SMR1) to select the baud rate
determined by using the external clock input.
• Set the P42/SCK0 and P62/SCK1 pins as input ports (DDR4: bit2 = 0 and DDR6: bit2 = 0).
• Write "0" to the SCKE bit of the mode control register (SMR0/SMR1) to set the pin as an external clock
input pin.
As shown in Figure 17.6-3, a baud rate is selected using the external clock input from the SCK1 pin. To
change the baud rate, the external input clock cycle must be changed because the internal division ratio is
fixed.
Figure 17.6-3 Baud Rate Selection Circuit for the External Clock
SMR0/SMR1 : CS2 to CS0 = 111B
(Selects the external clock)
Clock selector
P42/SCK0
P62/SCK1
1/1 (synchronous)
1/16 (asynchronous)
Pin
Baud rate
SCKI
SMR0/SMR1 : MD1
(Synchronous or asynchronous clock selection)
● Baud rate calculation formulas
Asynchronous baud rate = f/16
Synchronous baud rate = f
f: External clock frequency (up to 2 MHz)
497
CHAPTER 17 UART
17.7
Operation of UART
UART operates in operation modes 0 and 2 for normal bidirectional serial
communication and in operation mode 1 for master-slave communication.
■ Operation of UART
● Operation modes
There are three UART operation modes: modes 0 to 2. As listed in Table 17.7-1, an operation mode can be
selected according to the inter-CPU connection method and data transfer mode
Table 17.7-1 UART Operation Mode
Data length
Operation mode
Synchronization mode Stop bit length
When parity is disabled When parity is enabled
0
Normal mode
7 or 8 bits
Asynchronous
1
Multiprocessor
8+1*1 bits
–
Asynchronous
2
Normal mode
8 bits
–
Synchronous
1 or 2 bits *2
None
-: Setting not possible.
*1: "+1" indicates the address/data selection bit (A/D) for communication control.
*2: During reception, only one stop bit can be detected.
Note:
Operation mode 1 of UART is used only from the master system during master-slave connection.
● Inter-CPU connection method
One-to-one connection (normal mode) and master-slave connection (multiprocessor mode) can be selected.
For either connection method, the data length, whether to enable parity, and the synchronization method
must be common to all CPUs. Select an operation mode as follows:
• In the one-to-one connection method, operation mode 0 or 2 must be used in the two CPUs. Select
operation mode 0 for asynchronous transfer mode and operation mode 2 for synchronous transfer mode.
• Select operation mode 1 for the master-slave connection method and use it from the master system.
Select "When parity is disabled" for this connection method.
● Synchronization method
Asynchronous mode (start-stop synchronization) or clock synchronous mode can be selected in different
operation modes.
● Signal mode
UART can treat data only in NRZ (Non-return to Zero) format.
498
CHAPTER 17 UART
● Operation enable bit
UART controls both transmission and reception using the operation enable bit for TXE (transmission) and
that for RXE (reception). If each of the operations is disabled, stop it as follows:
• If reception operation is disabled during reception (data is input to the reception shift register), finish
frame reception and store the received data in the input data register (SIDRI). Then stop the reception
operation.
• If the transmission operation is disabled during transmission (data is output from the transmission shift
register), wait until there is no data in the output data register (SODR0/SODR1) before stopping the
transmission operation.
499
CHAPTER 17 UART
17.7.1
Operation in Asynchronous Mode (Operation Modes 0
and 1)
When UART is used in operation mode 0 (normal mode) or operation mode 1
(multiprocessor mode), the asynchronous transfer mode is selected.
■ Operation in Asynchronous Mode
● Transfer data format
Transfer data begins with the start bit (L level) and ends with the stop bit (H level). The data of the
specified data bit length is transferred in LSB first mode.
• In operation mode 0, the length of data with no parity is fixed to 7 bits, and that of data with parity is
fixed to 8 bits.
• In operation mode 1, the length of data is fixed to 8 bits with an address/data (A/D) selection bit added
instead of parity.
Figure 17.7-1 shows the data format in asynchronous mode.
Figure 17.7-1 Transfer Data Format (Operation Modes 0 and 1)
[Operation mode 0]
ST
D0
D1
D2
D3
D4
D5
D6
[Operation mode 1]
ST
D0
D1
D2
D3
D4
D5
D6
*
D7/P SP
D7
A/D
SP
* : D7 (bit 7) when parity is not provided
P (parity) when parity is provided
ST : Start bit
SP : Stop bit
A/D : Address/data selection bit in operation mode 1 (multiprocessor mode)
● Transmission operation
Transmission data is written to the output data register (SODR0/SODR1) when the transmission data empty
flag bit (SSR0/SSR1: TDRE) is "1". This data is transmitted if the transmission operation is enabled
(SCR0/SCR1: TXE = 1).
The TDRE flag is again set to "1" when the transmission data is transferred to the transmission shift register
and its transmission starts. Then, the next piece of transmission data gets ready to be set. At this point, a
transmission interrupt request is output requesting that the next piece of transmission data be set in the
SODR0/SODR1 register if that request is enabled (SSR0/SSR1: TIE = 1). The TDRE flag is cleared to "0"
when the transmission data is written to SODR0/SODR1.
500
CHAPTER 17 UART
● Reception operation
Reception operation is performed every time it is enabled (SCR0/SCR1: RXE = 1). When a start bit is
detected, a frame of data is received according to the data format specified by the control register (SCR0/
SCR1). After the frame has been received, the error flag is set if an error occurs, then the receive data full
flag bit (SSR0/SSR1: RDRF) is set to "1". At this point, a reception interrupt request is output if it is
enabled (SSR0/1: TIE = 1).
Check each flag of the input data register (SIDR0/SIDR1). If the reception is normal, read the input data
register (SIDR0/SIDR1). If an error is found, proceed to error handling. The RDRF flag is cleared to "0"
every time receive data is read from SIDR0/SIDR1.
● Stop bit
For transmission, 1 or 2 bits can be selected. During reception however, the first bit is the only one that is
always checked.
● Error detection
• In mode 0, parity, overrun and framing errors can be detected.
• In mode 1, overrun and framing errors can be detected but parity errors cannot be detected.
● Parity 0
Parity can only be used in operation mode 0 (asynchronous, normal mode). Whether to provide parity can
be specified using the PEN bit of the control register (SCR0/SCR1). Even or odd parity can also be
specified using the P bit of the control register (SDR0/SDR1). In operation mode 1 (asynchronous,
multiprocessor mode) and operation mode 2 (synchronous, normal mode), parity cannot be used. Figure
17.7-2 shows both transmission and receive data when parity is enabled.
Figure 17.7-2 Transmission Data when Parity is enabled
SIN0/SIN1
SP
A parity error occurs
during reception with even parity
(SCR0/SCR1: P=0)
SP
Transmission with even parity
(SCR0/SCR1: P=0)
ST
1 0 1 1 0 0 0
SOT0/SOT1
ST
1 0 1 1 0 0 1
SOT0/SOT1
ST
SP
Transmission with odd parity
(SCR0/SCR1: P=1)
1 0 1 1 0 0 0
Data
ST : Start bit
SP : Stop bit
Note : Parity is disabled in operation modes 1 and 2
Parity
501
CHAPTER 17 UART
17.7.2
Operation in Synchronous Mode (Operation Mode 2)
The clock synchronous transfer method is used for UART operation mode 2 (normal
mode).
■ Operation in Synchronous Mode (Operation Mode 2)
● Transfer data format
In synchronous mode, 8-bit data is transferred using the LSB first method, in which start and stop bits are
not added. Figure 17.7-3 shows the data format in clock synchronous mode.
Figure 17.7-3 Transfer Data Format (Operation Mode 2)
Transmission data writing
Mark level
Transmitting and reception
clock
RXE, TXE
Transmission and reception
data
1
0
1
LSB
1
0
0
1
0
MSB
(Mode 2)
01001101B is transferred.
● Clock supply
In clock synchronous mode (I/O extended serial), as many clocks as the number of transmission and
reception bits must be supplied.
• When the internal clock (dedicated baud rate generator or internal timer) is selected, the data receiving
synchronous clocks is generated automatically if data is transmitted.
• When the external clock is selected, confirm that the transmission side UART output data register
(SODR0/SODR1) contains data (SSR0/SSR1: TDRE = 0). Then, clocks for just 1 byte must be
supplied from outside.
The mark level (H) must be retained before transmission starts and after it is complete.
● Error detection
Only overrun errors can be detected; parity and framing errors cannot be detected.
502
CHAPTER 17 UART
● Initialization
The following shows the set values of each control register using the synchronous mode:
[Mode control register (SMR0/SMR1)]
MD1,MD0:"10B"
CS2,CS1,CS0:Specify clock input using the clock selector.
SCKE:1 for dedicated baud rate generator or internal timer
0 for clock output and external clock (clock input)
SOE:1 for transmission; 0 for reception only
[Control register (SCR0/SCR1)]
PEN:"0"
P,SBL,A/D:These bits make no sense.
CL:1 (8-bit data)
REC:0 (the error flag is cleared for initialization.)
RXE,TXE:At least one of the two bits is set to "1".
[Status register (SSR0/SSR1)]
RIE:1 when using interrupts; 0 when using no interrupts.
TIE:1 when using interrupts; 0 when using no interrupts.
● Starting communication
Write data to the output data register (SODR0/SODR1) to start communication. Temporary data must be
written to SODR0/SODR1 to start communication for reception.
● Ending communication
The RDRF flag of the status register (SSR0/SSR1) is set to "1" when transmission or reception of a data
frame is complete. During reception, check the overrun error flag bit (SSR0/SSR1) to see if
communication is performing normally.
503
CHAPTER 17 UART
17.7.3
Bidirectional Communication Function (Normal Mode)
In operation mode 0 or 2, normal serial bidirectional communication (one-to-one
connection) is available. Select operation mode 0 for asynchronous communication
and operation mode 2 for synchronous communication.
■ Bidirectional Communication Function
The settings shown in Figure 17.7-4 are required to operate UART in normal mode (operation mode 0 or 2).
Figure 17.7-4 Settings for UART Operation Mode 0
bit 15
SCR0/SCR1,
SMR0/SMR1
14
PEN
P
0
×
Mode 0
Mode 2
SSR0/SSR1,
SIDR0/SIDR1
SODR0/SODR1
13
12
SBL CL
×
1
11
10
9
8
×
6
5
4
3
2
1
Set conversion data (during writing).
Retain receive data (during reading).
×
DDR4 (UART0)
DDR6 (UART1)
: Bit used
x : Bit not used
1 : Set "1"
0 : Set "0"
: Set "0" to use an input pin
● Inter-CPU connection
As shown in Figure 17.7-5, interconnect two CPU's.
Figure 17.7-5 Connection Example of UART Bidirectional Communication
SOT
SOT
SIN
SCK
CPU-1
504
Ouput
0
AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 RST SCKE SOE
×
×
0
0
0
×
×
0
1
0
PE OREFRE RDRFTDRE BDS RIE TIE
Mode 0
Mode 2
7
Input
SIN
SCK
CPU-2
CHAPTER 17 UART
● Communication procedure
Communication starts from the transmitting system at an optional timing when transmission data has been
prepared. An ANS is returned periodically (byte by byte in this example) when the receiving system
receives transmission data. Figure 17.7-6 shows an example of a bidirectional communication flowchart.
Figure 17.7-6 Example of Bidirectional Communication Flowchart
(Transmitting system)
(Receiving system)
Start
Start
Set operation mode
(0 or 2)
Set operation mode(same mode
as that for the transmitting side)
Set 1-byte data in UODR
and perform communication
Data transmission
Any received data?
NO
YES
Any received data?
NO
Read and process received data.
YES
Data transmission
Read and process received data.
(ANS)
Transmit 1-byte data
505
CHAPTER 17 UART
17.7.4
Master-slave Communication Function (Multiprocessor
Mode)
With UART, communication with multiple CPUs connected in master-slave mode is
available in operation mode 1. However, UART can be used only from the master
system.
■ Master-slave Communication Function
The settings shown in Figure 17.7-7 are required to operate UART in multiprocessor mode (operation
mode 1).
Figure 17.7-7 Settings for UART Operation Mode 1
bit 15
SCR0/SCR1,
SMR0/SMR1
PEN
SSR0/SSR1,
SIDR0/SIDR1
SODR0/SODR1
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 RST SCKE SOE
×
1
0
0
×
1
0
Set transmission data (during writing).
PE OREFRE RDRFTDRE BDS RIE TIE Retain
receive data (during reading).
×
DDR4 (UART0)
DDR6 (UART1)
: Bit used
x : Bit not used
1 : Set "1"
0 : Set "0"
: Set "0" to use an input pin
● Inter-CPU connection
As shown in Figure 17.7-8, a communication system consists of one master CPU and multiple slave CPUs
connected to two communication lines. UART can be used only from the master CPU.
Figure 17.7-8 Connection Example of UART Master-slave Communication
SOT0/SOT1
SIN0/SIN1
Master CPU
SOT
SIN
Slave CPU #0
506
SOT
SIN
Slave CPU #1
CHAPTER 17 UART
● Function selection
Select the operation mode and data transfer mode for master-slave communication as shown in Table
Table 17.7-2 Selection of the Master-slave Communication Function
Operation mode
Data
Master CPU
Synchronizati
on method
Stop bit
None
Asynchronous
1 or 2
bits
Slave CPU
A/D = 1
+
8-bit address
Address transmission and reception
Mode 1
Data transmission and reception
Parity
–
A/D = 0
+
8-bit data
● Communication procedure
When the master CPU transmits address data, communication starts. The A/D bit in the address data is set
to "1", and the communication destination slave CPU is selected. Each slave CPU checks the address data
using a program. When the address data indicates the address assigned to a slave CPU, the slave CPU
communicates with the master CPU (ordinary data).
Figure 17.7-9 shows a flowchart of master-slave communication (multiprocessor mode).
507
CHAPTER 17 UART
Figure 17.7-9 Master-slave Communication Flowchart
(Master CPU)
Start
Select transfer mode 1
Set the data for selecting the slave
CPUs in D0 to D7 and set “1” in A/D
to transfer one byte
Set “0” in A/D
Reception is enabled
Communication with the slave CPU
NO
End communication?
YES
Communicate with
other slave CPU?
NO
YES
Reception is disabled
End
508
CHAPTER 17 UART
17.8
Usage Notes on UART
Notes on using UART are given below.
■ Notes on using UART
● Enabling operations
In UART, the control register (SCR0/SCR1) has both TXE (transmission) and RXE (reception) operation
enable bits. Both transmission and reception operations must be enabled before the transfer starts because
they have been disabled as the default value (initial value). The transfer can also be canceled by disabling
its operation as required.
● Communication mode setting
Set the communication mode while the system is not operating. If the mode is set during transmission or
reception, the transmission or reception data is not guaranteed.
● Synchronous mode
UART clock synchronous mode (operation mode 2) uses clock control (I/O extended serial) mode, in
which start and stop bits are not added to the data.
● Transmission interrupt enabling timing
The default (initial value) of the transmission data empty flag bit (SSR0/SSR1: TRE) is "1" (no
transmission data and transmission data write enable state). A transmission interrupt request is generated
as soon as the transmission interrupt requests are enabled (SSR0/SSR1: TIE = 1). Be sure to set the TIE
flag to "1" after setting the transmission data.
509
CHAPTER 17 UART
17.9
Sample Program for UART
This section contains a sample program for UART.
■ Sample Program for UART
● Processing specifications
The UART1 bidirectional communication function (normal mode) is used to perform serial transmission
and reception.
• Operation mode 0, asynchronous mode, eight data bits, two stop bits and no parity are set.
• The P60/SIN1 and P61/SOT1 pins are used for communication.
• The dedicated baud rate generator is used and the baud rate is set to about 9600 bps.
• Character 13H is transmitted from the SOT1 pin and is received using an interrupt.
• The machine clock (φ) is assumed to be 16 MHz.
● Coding example
ICR13
EQU
0000BDH
;UART1 transmission and reception interrupt control register
DDR6
EQU
000016H
;Port-6 data direction register
CDCR1
EQU
00001BH
;Communication prescaler register 1
SMR1
EQU
000024H
;Mode control register 1
SCR1
EQU
000025H
;Control register 1
SIDR1
EQU
000026H
;Input data register 1
SODR1
EQU
000026H
;Output data register 1
SSR1
EQU
000027H
;Status register 1
REC
EQU
SCR1:2
;Reception error flag clear bit
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
ABS = 0FFH
START:
;
:
;Assumes that stack pointer (SP) has already been
; initialized
AND
CCR,#0BFH
;Disables interrupts
MOV
I:ICR13,#00H
;Interrupt level 0 (highest)
MOV
I:DDR6,#00000000B
;Sets SIN1 pin as input pin
MOV
I:CDCR1,#080H
;Enables communication prescaler
MOV
I:SMR1,#00010001B
;Operation mode 0 (asynchronous)
;Uses dedicated baud rate generator (9615 bps)
;Disables clock pulse output and enables data output
MOV
I:SCR1,#00010011B
;No parity and two stop bits
;Clears eight data bits and reception error flag
510
CHAPTER 17 UART
;Enables transmission and reception operations
MOV
I:SSR1,#00000010B
;Disables transmission interrupts and enables reception
; interrupts
LOOP:
MOV
I:SODR1,#13H
;Writes transmission data
MOV
ILM,#07H
;Sets ILM in PS to level 7
OR
CCR,#40H
;Enables interrupts
MOV
A,#00H
;Endless loop
MOV
A,#01H
BRA
LOOP
;-------Interrupt program------------------------------------------------------------------------------------------WARI:
MOV
A,SIDR1
;Reads receive data
CLRB
I:REC
;Clears reception interrupt request flag
;
:
;
User processing
;
:
RETI
CODE
;Returns from the interrupt
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------VECT
VECT
CSEG
ABS=0FFH
ORG
0FF68H
DSL
WARI
ORG
0FFDCH
DSL
START
DB
00H
;Sets vector for interrupt #37 (25H)
;Sets reset vector
;Sets single-chip mode
ENDS
511
CHAPTER 17 UART
512
CHAPTER 18
DTP/EXTERNAL INTERRUPT
CIRCUIT
This chapter describes the functions and operation of
the DTP/external interrupt circuit.
18.1 Overview of the DTP/External Interrupt Circuit
18.2 Block Diagram of the DTP/External Interrupt Circuit
18.3 DTP/External Interrupt Circuit Pins
18.4 DTP/External Interrupt Circuit Registers
18.5 Operation of the DTP/External Interrupt Circuit
18.6 Usage Notes on the DTP/External Interrupt Circuit
18.7 Sample Programs for the DTP/External Interrupt Circuit
513
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.1
Overview of the DTP/External Interrupt Circuit
The data transfer peripheral (DTP)/external interrupt circuit is located between external
peripherals and the F2MC-16LX CPU. It receives interrupt requests and data transfer
requests from peripherals and passes them to the CPU to generate external interrupt
requests or activate the extended intelligent I/O service (EI2OS).
■ DTP/external Interrupt Functions
The DTP/external interrupt circuit is activated by the signal supplied to a DTP/external interrupt pin. The
CPU accepts the signal using the same procedure it uses for normal hardware interrupts and generates
external interrupts or activates the extended intelligent I/O service (EI2OS).
If the extended intelligent I/O service (EI2OS) is disabled when an interrupt request is accepted by the
CPU, the circuit executes its external interrupt function and branches to an interrupt routine. If EI2OS is
enabled, the circuit executes its DTP function, which performs automatic data transfer using EI2OS and
branches to an interrupt processing routine after the data transfer has been performed a specified number of
times.
Table 18.1-1 provides an overview of the DTP/external interrupt circuit.
Table 18.1-1 Overview of the DTP/external Interrupt Circuit
External interrupt function
Input pins
DTP function
Eight (P10/INT0/DTTI0 to P16/INT6, P63/INT7)
By using the request level setting register (ELVR), the level or edge to be detected can be selected
for each pin
Interrupt cause
Input of H level or L level or rising edge or
falling edge
Input of H level or L level
Interrupt number
#20 (14H), #22 (16H), #25 (19H), #27 (1BH)
Interrupt control
The output of interrupt requests is enabled and disabled using the DTP/interrupt enable register
(ENIR)
Interrupt flag
Interrupt causes are stored in the DTP/interrupt cause register (EIRR)
Processing selection
EI2OS is disabled (ICR: ISE = 0)
EI2OS is enabled (ICR: ISE = 1)
Processing
The circuit branches to an external interrupt
processing routine
The circuit performs automatic data transfer
using EI2OS for a specified number of times
and then branches to an interrupt routine
ICR: Interrupt control register
514
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
■ Interrupt of the DTP/external Interrupt Circuit and EI2OS
Table 18.1-2 Interrupt of the DTP/external Interrupt Circuit and EI2OS
Interrupt control register
Channel
Interrupt
number
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
INT0/INT1
#20 (14H)
ICR04
0000B4H
FFFFACH
FFFFADH
FFFFAEH
INT2/INT3
#22 (16H)
ICR05
0000B5H
FFFFA4H
FFFFA5H
FFFFA6H
INT4/INT5
#25 (19H)
ICR07
0000B7H
FFFF98H
FFFF99H
FFFF9AH
INT6/INT7
#27 (1BH)
ICR08
0000B8H
FFFF90H
FFFF91H
FFFF92H
O
O: Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal.
515
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.2
Block Diagram of the DTP/External Interrupt Circuit
The DTP/external interrupt circuit consists of four blocks, the block diagram is shown in
Figure 18.2-1.
■ Block Diagram of the DTP/external Interrupt Circuit
Figure 18.2-1 Block Diagram of the DTP/external Interrupt Circuit
Request level setting register (ELVR)
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
2
Pin
2
2
2
2
2
2
Selector
Selector
P63/INT7
Pin
P10/INT0/DTTI0
Selector
Pin
Selector
P16/INT6/TO0
Pin
P11/INT1
Pin
Internal data bus
2
Selector
Selector
P15/INT5/TIN0
Pin
P12/INT2/DTTI1
Pin
Selector
Selector
Pin
P14/INT4
P13/INT3
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Interrupt request number
#20(14H)
#22(16H)
#25(19H)
#27(1BH)
EN7
516
EN6
EN5
EN4
EN3
EN2
EN1
EN0
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
● DTP/external interrupt input detection circuit
Upon detecting the level or edge selected for each pin by the interrupt request level setting register
(ELVR), this circuit sets to "1" the IR bit of the DTP/external interrupt cause register (EIRR) that
corresponds to the pin.
● Request level setting register (ELVR)
This register selects the effective level or edge for each pin.
● DTP/interrupt cause register (EIRR)
This register stores DTP/external interrupt causes. It contains an external interrupt request flag bit for each
pin. The bit is set to "1" if a valid signal is input to the corresponding pin.
● DTP/interrupt enable register (ENIR)
This register enables and disables external interrupts for each pin.
517
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.3
DTP/External Interrupt Circuit Pins
This section describes the DTP/external interrupt circuit pins and provides a pin block
diagram.
■ DTP/external Interrupt Circuit Pins
The DTP/external interrupt circuit pins are also used as general ports. Table 18.3-1 lists the pin functions,
I/O formats, and settings required to use the DTP/external interrupt circuit.
Table 18.3-1 DTP/external Interrupt Circuit Pins
Pin name
Function
I/O format
Pull-up resistor Standby control
Setting required to use pins
P10/INT0/
DTTI0
Set the pin as an input port
(DDR1: bit8 = 0)
P11/INT1
Set the pin as an input port
(DDR1: bit9 = 0)
P12/INT2/
DTTI1*
Set the pin as an input port
(DDR1: bit10 = 0)
P13/INT3
Port 1 input-output/
external interrupt
input/resource inputoutput
Selectable
CMOS output /CMOS
hysteresis input
Provided
Set the pin as an input port
(DDR1: bit11 = 0)
P14/INT4
Set the pin as an input port
(DDR1: bit12 = 0)
P15/INT5/
TIN0
Set the pin as an input port
(DDR1: bit13 = 0)
P16/INT6/TO0
Set the pin as an input port
(DDR1: bit14 = 0)
P63/INT7
Port 6 input-output/
external interrupt input
*: Pin name not applicable to MB90465 series
518
Not
provided
Set the pin as an input port
(DDR6: bit3 = 0)
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
■ Block Diagram of the DTP/external Interrupt Circuit Pins
Figure 18.3-1 Block Diagram of the DTP/external Interrupt Circuit Pins (INT0 to INT6)
RDR
Resource input
Resource output
Port data register (PDR)
Resource output enable
Pull-up resistor
About 50k
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
Figure 18.3-2 Block Diagram of the DTP/external Interrupt Circuit Pins (INT7)
Resource output
Resource input
Resource output enable
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
External interrupt enable
519
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.4
DTP/External Interrupt Circuit Registers
This section describes DTP/external interrupt circuit registers.
■ DTP/External Interrupt Circuit Registers
Figure 18.4-1 DTP/external Interrupt Circuit Registers
DTP / Interrupt Cause Register
bit 15
14
13
12
11
10
9
8
ER5
ER4
ER3
ER2
ER1
ER0
R/W
X
R/W
X
R/W
X
R/W
X
4
3
Address: 000031H
ER7
ER6
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
2
1
0
EN1
EN0
EIRR
DTP / Interrupt Enable Register
bit
Address: 000030H
Read/write
Initial value
7
6
5
EN7
EN6
EN5
R/W
0
R/W
0
EN4
EN3
EN2
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
ENIR
R/W
0
Request Level Setting Register (Upper)
15
14
13
12
11
10
9
8
Address: 000033H
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
Read/write
Initial value
R/W
0
R/W
0
bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
LB0
LA0
ELVRH
Request Level Setting Register (Lower)
bit
Address: 000032H
Read/write
Initial value
520
7
6
5
4
LB3
LA3
LB2
LA2
LB1
LA1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
ELVRL
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.4.1
DTP/interrupt Cause Register (EIRR)
The DTP/interrupt cause register (EIRR) stores and clears interrupt causes.
■ DTP/interrupt Cause Register (EIRR)
Figure 18.4-2 DTP/interrupt Cause Register (EIRR)
Address bit 15
000031H
14
13
12
11
9
8
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
R/W R/W
R/W R/W R/W R/W
ER7
ER0
0
R/W
10
: Read/write
1
7
0
(ENIR)
Initial value
XXXXXXXXB
R/W R/W
External interrupt request flag bit
Read
Write
No DTP/external interrupt is input
A DTP/external interrupt is input
This bit is cleared
No effect
Table 18.4-1 Function Description of Each Bit of the DTP/interrupt Cause Register (EIRR)
Bit name
bit15
to
bit8
Notes:
ER7 to ER0:
External interrupt
request flag bits
Function
• Each of these bits is set to "1" if a signal with the edge or level selected by bits LB7,
LA7 to LB0, LA0 of the request level setting register (ELVR) is input to the DTP/
external interrupt pin (stores an interrupt cause).
• If these bits and corresponding bits EN7 to EN0 of the DTP/interrupt enable register
(ENIR) are "1", an interrupt request is output to the CPU.
• Writing "0" to this bit clears the bit. Writing "1" to this bit does not change the bit
value and has no effect on other bits.
(Note)
If more than one external interrupt request output is enabled (ENIR: EN7 to EN0 =
1), clear only the bit that caused the CPU to accept an interrupt (bits ER7 to ER0 set to
"1"). Do not clear the other bits without a reason.
(Reference)
When the extended intelligent I/O service (EI²OS) is activated, the corresponding
external interrupt request flag bit is automatically cleared when the transfer of one
data ends.
• The value of the DTP/external interrupt request flag bit (EIRR:ER) is valid only when the
corresponding DTP/external interrupt request enable bit (ENIR:EN) is set to "1". When the DTP/
external interrupt is not enabled (ENIR:EN=0), the DTP/external interrupt cause bit may be set
regardless of the presence or absence of a DTP/external interrupt cause.
• Immediately before enabling the DTP/external interrupt (ENIR:EN=1), clear the corresponding
DTP/external interrupt request flag bit (EIRR:ER).
521
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.4.2
DTP/interrupt Enable Register (ENIR)
The DTP/interrupt enable register (ENIR) enables and disables the output of interrupt
requests to the CPU.
■ DTP/interrupt Enable Register (ENIR)
Figure 18.4-3 DTP/interrupt Enable Register (ENIR)
Address bit 15
000030H
8
7
6
5
4
3
2
1
0
Initial value
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 00000000B
(EIRR)
R/W R/W R/W R/W R/W R/W R/W R/W
EN7
External interrupt request enable bits
R/W
: Read/write enabled
: Initial value
EN0
0
An external interrupt request is disabled.
1
An external interrupt request is enabled.
Table 18.4-2 Function Description of Each Bit of the DTP/interrupt Enable Register (ENIR)
Bit name
bit7
to
bit0
Note:
522
EN7 to EN0:
External interrupt
request enable bits
Function
Each of these bits enables and disables the output of interrupt requests to the CPU. If
these bits and corresponding bits ER7 to ER0 of the DTP/interrupt cause register
(EIRR) are "1", an interrupt request is output to the CPU.
(References)
• To use a DTP/external interrupt pin, write "0" to the corresponding bit of the
port direction register to set the pin as an input port.
• The states of the DTP/external interrupt pins can be read directly using the port
data register regardless of the states of external interrupt request enable bits.
• Bits ER7 to ER0 of the DTP/interrupt cause register (EIRR) are set to "1" if an
interrupt cause is detected regardless of the values of external interrupt request
enable bits.
Immediately before enabling the DTP/external interrupt (ENIR:EN=1), clear the corresponding DTP/
external interrupt request flag bit (EIRR:ER).
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
Table 18.4-3 Correspondence between the DTP/interrupt Control Registers (EIRR, ENIR) and Each
Channel
DTP/external interrupt pin
Interrupt number External interrupt request flag bit
P63/INT7
P16/INT6
#27 (1BH)
P15/INT5
P14/INT4
#25 (19H)
P13/INT3
P12/INT2/DTTI1*
#22 (16H)
P11/INT1
P10/INT0/DTTI0
#20 (14H)
External interrupt request
enable bit
ER7
EN7
ER6
EN6
ER5
EN5
ER4
EN4
ER3
EN3
ER2
EN2
ER1
EN1
ER0
EN0
*: Pin name not applicable to MB90465 series
523
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.4.3
Request Level Setting Register (ELVR)
The request level setting register (ELVR) selects the level or edge of the signal input to
each DTP/external interrupt pin that is to be detected as a DTP/external interrupt cause.
■ Request Level Setting Register (ELVR)
Figure 18.4-4 Request Level Setting Register (ELVR)
Address bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
000033H LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00000000B
R/W: Read/write enabled
:Initial value
LB 7 to
LB 0
LA 7 to
LA 0
0
0
0
1
1
0
1
1
External interrupt request detection selection bits
L level is to be detected.
H level is to be detected.
Rising edge is to be detected.
Falling edge is to be detected.
Table 18.4-4 Function Eescription of Each bit of the Request Level Setting Register (ELVR)
Bit name
bit15
to
bit0
LB7, LB0 to LA7, LA0:
Request detection
selection bits
Function
• Each of these bits selects the level or edge of the signal input to the DTP/
external interrupt pin to be detected as a DTP/external interrupt cause.
• Two bits are assigned to each pin.
(Reference)
If the selected detection signal is input to a DTP/external interrupt pin, the
external interrupt request flag bit is set to "1" regardless of the settings of the
DTP/interrupt enable register (ENIR).
Table 18.4-5 Correspondence between Request Level Setting Register (ELVR) and Each Channel
DTP/external interrupt pin
Interrupt number
P63/INT7
P16/INT6
LB7, LA7
#27 (1BH)
#25 (19H)
P13/INT3
P12/INT2/DTTI1*
*: Pin name not applicable to MB90465 series
524
LB4, LA4
LB3, LA3
#22 (16H)
LB2, LA2
LB1, LA1
P11/INT1
P10/INT0/DTTI0
LB6, LA6
LB5, LA5
P15/INT5
P14/INT4
Bit name
#20 (14H)
LB0, LA0
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.5
Operation of the DTP/External Interrupt Circuit
The DTP/external interrupt circuit provides the external interrupt function and the DTP
function. This section describes the settings required for each function and the
operation of the circuit.
■ Setting the DTP/external Interrupt Circuit
Figure 18.5-1 shows the settings required to operate the DTP/external interrupt circuit.
Figure 18.5-1 DTP/external Interrupt Circuit
11
10
9
8
ICR08/ICR07
or
ICS3 ICS2 ICS1 ICS0 ISE
ICR05/ICR04
bit 15
14
13
12
IL2
IL1
IL0
3
2
1
0
ICS3 ICS2 ICS1 ICS0 ISE
7
6
5
4
IL2
IL1
IL0
For the external interrupt function
For the DTP function
EIRR/
ENIR
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
ELVR
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
DDR1
P16 P15 P14 P13 P12 P11 P10
DDR6
P63
: Used
: Set the bit corresponding to the bit used to 1
: Set the bit corresponding to the bit used to 0
0 : Specifies 0
1 : Specifies 1
Set the DTP/external interrupt circuit registers with the following procedure:
1. Set as an input port the general I/O port to be used also as a pin to input external interrupts.
2. Set the target bit of the DTP/interrupt enable register (ENIR) to disable interrupts.
3. Set the target bit of the request level setting register (ELVR).
4. Clear the target bit of the DTP/interrupt cause register (EIRR).
5. Set the target bit of the DTP/interrupt enable register (ENIR) to enable interrupts.
The procedure for setting the DTP/external interrupt circuit registers must start with disabling the output of
external interrupt requests (ENIR:EN7 to EN0 = 0). Before the output of external interrupt requests can be
enabled (ENIR:EN7 to EN0 = 1), the corresponding interrupt request flag bits must be cleared (ENIR:EN7
to EN0 = 0).
This is in order to avoid interrupt requests from being generated accidentally while the registers are being
set.
525
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
● Switching between the external interrupt function and the DTP function
Switching between the external interrupt function and the DTP function is accomplished by the ISE bit of
the corresponding interrupt control register (ICR). If the ISE bit is "1", the extended intelligent I/O service
(EI2OS) is enabled and the circuit executes its DTP function. If it is "0", EI2OS is disabled and the circuit
executes the its external interrupt function.
Note:
If multiple interrupt requests are assigned to a single ICR register, the interrupt level (IL2 to IL0) is
common to all of the interrupt requests. As a rule, when one interrupt request uses EI2OS, the other
interrupt requests cannot use it.
■ Operation of the DTP/external Interrupt Circuit
Table 18.5-1 shows the control bits and interrupt causes of the DTP/external interrupt circuit.
Table 18.5-1 Control Bit and Interrupt Cause of the DTP/external Interrupt Circuit
DTP/external interrupt circuit
Interrupt request flag bit
EIRR: ER7 to ER0
Interrupt request enable bit
ENIR: EN7 to EN0
Interrupt cause
Input of an effective edge or level to pin INT7 to INT0
When DTP/external input requests are set, the resource will generate an interrupt request signal to the
interrupt controller whenever an interrupt cause indicated in the request level setting register (ELVR) is
received at the corresponding pin. If the ISE bit is "0", the interrupt processing microprogram is executed.
If it is "1", the extended intelligent I/O service handling (DTP handling) microprogram is executed.
526
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
Figure 18.5-2 shows the operation of the DTP/external interrupt circuit.
Figure 18.5-2 Operation of the DTP/external Interrupt Circuit
DTP/external interrupt circuit
Another request
Interrupt controller
CPU
ELVR
ICRYY
ELVR
IL
CMP
ICRXX
ELVR
CMP
ILM
Interrupt processing
microprogram
Cause
DTP handling routine
(EI2OS is started)
Generation of DTP/
external interrupt request
Transfer data between memory
and peripheral
Accepted by
interrupt controller?
Update descriptor
Descriptor
data counter
0
Interrupt processing routine
Accepted by CPU?
≠0
Return from DTP handling routine
Start interrupt processing
microprogram
ICR: ISE
Set again or stop
Return to CPU processing
1
0
Start external interrupt flag.
Processing. Clear interrupt flag.
Return from external interrupt
527
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.5.1
External Interrupt Function
The DTP/external interrupt circuit has an external interrupt function that generates an
interrupt request when a selected signal level is input to a DTP/external interrupt pin.
■ External Interrupt Function
If the edge or level selected for a DTP/external interrupt pin by the request level setting register (ELVR) is
detected at that pin, the corresponding ER7 to ER0 bit of the DTP/interrupt cause register (EIRR) is set to
"1". If, in this state, the corresponding interrupt request enable bit of the DTP/interrupt enable register is
set to "1" to enable interrupts (ENIR:EN7 to EN0 = 1), the interrupt cause is reported to the interrupt
controller. The interrupt controller checks the magnitude of the interrupt level (ICR:IL2 to IL0) in relation
to those of the interrupt requests from other peripheral functions, the interrupt priority, etc. The CPU
checks the magnitudes of the interrupt level mask register (PS:ILM2 to ILM0) and the interrupt level, the
interrupt enable bit (PS:CCR: 1), etc. When the interrupt request is accepted by the CPU, the CPU
executes an internal interrupt processing routine (microprogram) and branches to the interrupt processing
routine. In the interrupt processing routine, 0 must be written to the corresponding interrupt request flag bit
to clear the interrupt request.
Notes:
528
• An ER bit is set to "1" if a DTP/external interrupt cause is generated, regardless of the state of the
corresponding EN bit.
• When the interrupt routine is activated, the ER bit that caused the routine to be activated must be
cleared. If the ER bit is kept at 1, control cannot return from the interrupt. Only clear the flag bit
that caused the interrupt; do not clear the other bits without reason.
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.5.2
DTP Function
The DTP/external interrupt circuit has a DTP function that detects a signal supplied to a
DTP/external interrupt pin from an external peripheral and activates the extended
intelligent I/O service.
■ Operation of the DTP Function
The DTP function detects a data transfer request signal from an external peripheral to automatically transfer
data between memory and the peripheral.
The extended intelligent I/O service (EI2OS) is activated by the external interrupt function using level
detection. The operation of the DTP function is the same as that of the external interrupt function up to the
point that the CPU accepts an interrupt request. If the operation of EI2OS is enabled (ICR:ISE = 1), EI2OS
is activated to start data transfer when an interrupt request is accepted. When the transfer of one data unit
ends, the descriptor is updated and the interrupt request flag bit is cleared to wait for the next request from
the pin. When the entire transfer using EI2OS is completed, control is transferred to the interrupt
processing routine.
The external peripheral must remove only the level of the data transfer request signal (DTP external
interrupt cause) within three cycles of the first transfer.
Figure 18.5-3 Example of Interfacing to the External Peripheral
Rising edge request, or H level request (ELVR: LB0, LA0 = 01B)
Input to the INTO pin
(DTP/external interrupt cause)
*Intelligent I/O service data transfer
Internal operation of
the CPU (microprogram)
from i/o register to memory.
Descriptor selection
and reading
Descriptor updating
Write address
Read address
Address bus pin
Data bus pin
Read data
Write data
Read signal
Write signal
*1
Internal bus
Register
External peripheral
Data, address bus
IRQ
Data
transfer
request
Read operation
DTP/external
interrupt cause*2
INT
DTP/external
interrupt circuit
Write
operation*3
*1
Interrupt
request
CPU
(EI2OS)
Internal
Memory
MB90460/465 series
*1, *2 : Must be removed within three machine cycles of transfer.
*3 : If the extended intelligent I/O service is in peripheral -> memory transfer mode.
529
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.6
Usage Notes on the DTP/External Interrupt Circuit
Notes on the signal to be input to the DTP/external interrupt circuit, release from
standby mode, and interrupts are given below.
■ Usage Notes on the DTP/external Interrupt Circuit
● Conditions for external peripherals using the DTP function
To support the DTP function, external peripherals must be able to clear data transfer requests automatically
in response to transfer operations. If a transfer request is not removed within three machine cycles of the
start of transfer, the DTP/external interrupt circuit interprets the request as another transfer request.
● Input polarities of external interrupts
• If the request level setting register (ELVR) is set so that an edge is detected, the pulse width must be at
least three machine cycles for the edge to be detected.
• If the request input level is level setting, the pulse width requires a longer period than the minimum
pulse width stated on the data sheet. Also, as long as the interrupt input pin retains the active level,
interrupt requests continue to be generated to the interrupt controller, even if the DTP/external interrupt
cause register is cleared.
• If the register is set for level detection, and the level to be detected as an interrupt cause is input, cause
F/F in the DTP/interrupt cause register (EIRR) is set to "1" to store the cause, as shown in Figure 18.6-1.
Even if the cause is removed, the request to the interrupt controller remains active provided the output
of interrupt requests is enabled. Thus, to cancel the request to the interrupt controller, clear the external
interrupt request flag bit and cause F/F, as shown in Figure 18.6-2.
Figure 18.6-1 Clearing the Cause Retention Circuit when a Level is Specified
DTP/external
interrupt cause
DTP/interrupt input
detection circuit
Cause flip-flop
(in the EIRR register)
Enable gate
The cause is stored until the register is cleared
530
To interrupt
controller
(interrupt
request)
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
Figure 18.6-2 DTP/external Interrupt Cause and Interrupt Request when the Output of Interrupt Requests
is enabled
DTP/external interrupt
cause (when the H level
is detected)
H level
Removal of the interrupt cause
Interrupt request to the
interrupt controller
Request becomes inactive when
cause flip-flop is cleared
● Notes about interrupts
When the external interrupt function is used, control cannot return from the interrupt processing routine if
the external interrupt request flag bit is "1" and the output of interrupt requests is enabled. In the interrupt
processing routine, the external interrupt request flag bit must be cleared. (When the DTP function is used,
EI2OS automatically clears the bit.) For level detection, the external interrupt request flag bit is set again as
soon as it is cleared if the level assumed as an interrupt cause continues to be input. Either disable the
output of interrupt requests or remove the interrupt cause, if required.
531
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
18.7
Sample Programs for the DTP/External Interrupt Circuit
This section contains sample programs for the external interrupt function and the DTP
function.
■ Sample Program for the External Interrupt Function
● Processing
• The rising edge of the pulse input to the INT0 pin is detected, and an external interrupt is generated.
● Coding example
ICR04
EQU
0000B4H
;Interrupt control register for the DTP/external
interrupt circuit
DDR6
EQU
000016H
;
DDR1
EQU
000011H
;Port 1 direction register
ENIR
EQU
000030H
;DTP/interrupt enable register
EIRR
EQU
000031H
;DTP/interrupt cause register
ELVRL
EQU
000032H
;Request level setting register
ELVRH
EQU
000033H
;Request level setting register
ER0
EQU
EIRR:0
;INT0 interrupt flag bit
EN0
EQU
ENIR:0
;INT0 interrupt enable bit
;-------Main program-----------------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
;Assumes that stack pointer (SP) has already been
initialized
MOV
I:DDR1,#00000000B ;Sets DDR1 as an input port
AND
CCR,#0BFH
;Disables interrupts
MOV
I:ICR04,#00H
;Interrupt level: 0 (highest). Disables EI2OS
CLRB
I:EN0
;Disables INT0, using ENIR
MOV
I:ELVRL,#00000010B ;Selects the rising edge for INT0
CLRB
I:ER0
;Clears the cause for INT0 using EIRR
SETB
I:EN0
;Enables INT0 using ENIR
MOV
ILM,#07H
;Sets ILM in PS to level 7
OR
CCR,#40H
;Enables interrupts
LOOP:
MOV
A,#00H
;Endless loop
MOV
A,#01H
BRA
LOOP
;-------Interrupt program----------------------------------------------------------------------------------------------WARI
CLRB
I:ER0
;Clears the interrupt request flag
;
:
;
User processing
;
:
532
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
RETI
;Returns from interrupt
CODE
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFACH
;Sets vector for interrupt #20 (14H)
DSL
WARI
ORG
0FFDCH
;Sets reset vector
DSL
START
DB
00H
;Sets single-chip mode
VECT
ENDS
END
START
■ Sample Program for the DTP Function
● Processing
• The H level of the signal input to the INT0 pin is detected, and channel 0 of the extended intelligent I/O
service (EI2OS) is activated.
• Data is output from RAM to port 0 by DTP processing (EI2OS).
● Coding example
ICR04
DDR0
DDR1
ENIR
EIRR
ELVRL
ELVRH
ER0
EN0
BAPL
BAPM
BAPH
EQU
0000B4H
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
000010H
000011H
000030H
000031H
000032H
000033H
EIRR:0
ENIR:0
000100H
000101H
000102H
;Interrupt control register for the DTP/external
interrupt circuit
;Port 0 direction register
;Port 1 direction register
;DTP/interrupt enable register
;DTP/interrupt cause register
;Request level setting register
;Request level setting register
;INT0 interrupt flag bit
;INT0 interrupt enable bit
;Buffer address pointer, lower
;Buffer address pointer, middle
;Buffer address pointer, upper
ISCS
EQU
000103H
;EI2OS status register
IOAL
EQU
000104H
;I/O address register, lower
IOAH
EQU
000105H
;I/O address register, upper
DCTL
EQU
000106H
;Data counter, lower
DCTH
EQU
000107H
;Data counter, upper
;-------Main program-----------------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
;Assumes that stack pointer (SP) has already been
initialized
MOV
I:DDR0,#11111111B ;Sets DDR0 as an output port
MOV
I:DDR1,#00000000B ;Sets DDR1 as an input port
AND
CCR,#0BFH
;Disables interrupts
MOV
I:ICR04,#08H
;Interrupt level: 0 (highest)
533
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT
;Enables EI2OS. Channel 0
MOV
BAPL,#00H
;Sets the address of the output data
MOV
BAPM,#06H
;
MOV
BAPH,#00H
;
MOV
ISCS,#12H
;Byte transfer. I/O address fixed. Buffer address
+ 1. Transfer from memory to I/O
MOV
IOAL,#00H
;Specifies port 0 (PDR0) as the transfer destination
MOV
IOAH,#00H
;address pointer
MOV
DCTL,#0AH
;Number of transfers: 10
MOV
DCTH,#00H
;
CLRB
I:EN0
;Disables INT0 using ENIR
MOV
I:ELVRL,#00000001B;Selects H level for INT0
CLRB
I:ER0
;Clears the cause of INT0 using EIRR
SETB
I:EN0
;Enables INT0 using ENIR
MOV
ILM,#07H
;Sets ILM in PS to level 7
OR
CCR,#40H
;Enables interrupts
LOOP:
MOV
A,#00H
;Endless loop
MOV
A,#01H
;
BRA
LOOP
;
;-------Interrupt program------------------------------------------------------------------------------------------WARI:
CLRB
I:ER0
;Clears the interrupt request flag
;
:
;
;Switches the channel and changes the transfer
address, if required
;
User processing
;Specifies processing again, such as the termination
of EI2OS. To terminate the processing, interrupts
must be disabled
;
:
RETI
;Returns from the interrupt
CODE
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFACH
;Sets vector for interrupt #20 (14H)
DSL
WARI
ORG
0FFDCH
;Sets reset vector
DSL
START
DB
00H
;Sets single-chip mode
VECT
ENDS
END
STAR
534
CHAPTER 19
DELAYED INTERRUPT
GENERATOR MODULE
This chapter describes the functions and operation of
the delayed interrupt generator module.
19.1 Overview of the Delayed Interrupt Generator Module
19.2 Delayed Interrupt Generator Module Register
19.3 Operation of the Delayed Interrupt Generator Module
19.4 Usage Notes on the Delayed Interrupt Generator Module
535
CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE
19.1
Overview of the Delayed Interrupt Generator Module
The delayed interrupt generator module generates interrupts for task switching. By
using this module, software can issue and cancel interrupt requests for the F2MC-16LX
CPU.
■ Block Diagram of the Delayed Interrupt Generator Module
Figure 19.1-1 shows the block diagram of the delayed interrupt generator module.
F2MC-16LX bus
Figure 19.1-1 Block Diagram of the Delayed Interrupt Generator Module
536
Delayed interrupt cause issuance/cancellation decoder
Interrupt cause latch
CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE
19.2
Delayed Interrupt Generator Module Register
This section lists the delayed interrupt generator module register.
■ Delayed Interrupt Generator Module Register (DIRR)
Figure 19.2-1 Delayed Interrupt Generator Module Register (DIRR)
Address bit
00009FH
15
14
13
12
11
10
9
8
Initial value
—
—
—
—
—
—
—
R0
-------0B
—
—
—
—
—
—
—
R/W
R/W: Read and write
R0
Delayed interrupt request
0
Clears delayed interrupt request
1
Generates delayed interrupt request
: Initial value
—
: Not used
Table 19.2-1 Delayed Interrupt Generator Module Register (DIRR)
Bit name
bit15
to
bit9
bit8
Reserved bits
R0:
Delayed interrupt
request bit
Function
• Both "0" and "1" may be written to the reserved bit area, however, the set bit and clear
bit instructions should be used to access this register to prepare for future expansion.
•
•
•
•
•
This bit is used to controls the generation or clearing of a delayed interrupt request.
Writing "1" to this register generates a delayed interrupt request.
Writing "0" to this register clears the delayed interrupt request.
The register is cleared at reset.
Both "0" and "1" may be written to the reserved bit area. However, the set bit and clear
bit instructions should be used to access this register to prepare for future expansion.
537
CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE
19.3
Operation of the Delayed Interrupt Generator Module
When software causes the CPU to write "1" to the relevant bit of DIRR, the request latch
in the delayed interrupt generator module is set and an interrupt request is generated to
the interrupt controller.
■ Operation of the Delayed Interrupt Generator Module
When software causes the CPU to write "1" to the relevant bit of DIRR, the request latch in the delayed
interrupt generator module is set and an interrupt request is generated to the interrupt controller. If the
priority of other interrupt requests is lower than that of this interrupt or no other interrupt request is
generated, the interrupt controller generates an interrupt request to the F2MC-16LX CPU. The F2MC16LX CPU compares the ILM bit of the internal CCR register and the interrupt request. When the request
level is higher than that of the ILM bit, the CPU starts the hardware interrupt processing microprogram
immediately after execution of the current instruction ends. As a result, the interrupt processing routine for
this interrupt is executed. This interrupt cause is cleared and task switching is done by writing "0" to the
relevant bit of DIRR in the interrupt processing routine. Figure 19.3-1 Operation of the delayed interrupt
generator module shows the operation of the delayed interrupt generator module.
Figure 19.3-1 Operation of the Delayed Interrupt Generator Module
Delayed interrupt generation module
Delayed interrupt controller
WRITE
F2MC-16LX CPU
Other requests
ICR yy
IL
CMP
DIRR
CMP
ICR xx
ILM
NTA
538
CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE
19.4
Usage Notes on the Delayed Interrupt Generator Module
Notes on using the delayed interrupt generator module are given below.
■ Usage Notes on the Delayed Interrupt Request Latch
• This latch is set by writing "1" to the relevant bit of DIRR and cleared by writing "0" to the same bit.
Note that interrupt processing is restarted at the moment control returns from interrupt processing unless
software is created to clear the cause in the interrupt processing routine.
539
CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE
540
CHAPTER 20
8/10-BIT A/D CONVERTER
This chapter describes the functions and operation of
the 8/10-bit A/D converter.
20.1 Overview of the 8/10-bit A/D Converter
20.2 Block Diagram of the 8/10-bit A/D Converter
20.3 8/10-bit A/D Converter Pins
20.4 8/10-bit A/D Converter Registers
20.5 8/10-bit A/D Converter Interrupts
20.6 Operation of the 8/10-bit A/D Converter
20.7 Usage Notes on the 8/10-bit A/D Converter
20.8 Sample Program 1 for the 8/10-bit A/D Converter (Single
Conversion Mode Using EI2OS)
20.9 Sample Program 2 for the 8/10-bit A/D Converter (Continuous
Conversion Mode Using EI2OS)
20.10 Sample Program 3 for the 8/10-bit A/D Converter (Stop
Conversion Mode Using EI2OS)
541
CHAPTER 20 8/10-BIT A/D CONVERTER
20.1
Overview of the 8/10-bit A/D Converter
Using the RC-type successive approximation conversion method, the 8/10-bit A/D
converter converts an analog input voltage into a 10-bit or 8-bit digital value.
An input signal is selected from eight channels for analog input pins. The conversion
can be activated by software, an internal clock, and 16-bit free-run timer zero detection.
■ Functions of the 8/10-bit A/D Converter
The converter converts the analog voltage input to an analog input pin (input voltage) to a digital value.
The converter has the following features:
• The minimum conversion time is 6.13 µs (for a machine clock of 16 MHz; includes the sampling time).
• The minimum sampling time is 3.75 µs (for a machine clock of 16 MHz).
• The converter uses the RC-type successive approximation conversion method with a sample and hold
circuit.
• A resolution of 10 bits or 8 bits can be selected.
• Up to eight channels for analog input pins can be selected by a program.
• At the end of A/D conversion, an interrupt request can be generated and EI2OS can be activated.
• In the interrupt-enabled state, the conversion data protection function prevents any part of the data from
being lost through continuous conversion.
• The conversion can be activated by software, 16-bit reload timer 1 (rising edge) and 16-bit free-run
timer zero detection edge.
Table 20.1-1 lists three types of conversion modes.
Table 20.1-1 8/10-bit A/D Converter Conversion Modes
Single conversion
Scan conversion
Single conversion mode
Converts the input of a specified
channel (single channel) just once.
Converts the inputs of two or more consecutive
channels (up to eight channels) just once.
Continuous conversion mode
Converts the input of a specified
channel (single channel) repeatedly.
Converts the inputs of two or more consecutive
channels (up to eight channels) repeatedly.
Stop conversion mode
Converts the input of a specified
channel (single channel), after which it
is on standby for the next activation.
Converts the inputs of two or more consecutive
channels (up to eight channels).
When a channel has been converted, the
converter is put on standby for the next
activation.
542
CHAPTER 20 8/10-BIT A/D CONVERTER
■ 8/10-bit A/D Converter Interrupts and EI2OS
Table 20.1-2 8/10-bit A/D Converter Interrupts and EI2OS
Interrupt control register
Interrupt no.
#11 (0BH)
Vector table address
EI²OS
Register
name
Address
Lower
Upper
Bank
ICR00
0000B0H
FFFFD0H
FFFFD1H
FFFFD2H
O
O: Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal.
543
CHAPTER 20 8/10-BIT A/D CONVERTER
20.2
Block Diagram of the 8/10-bit A/D Converter
The 8/10-bit A/D converter has nine blocks, the block diagram is shown in Figure 20.2-1.
■ Block Diagram of the 8/10-bit A/D Converter
Figure 20.2-1 Block Diagram of the 8/10-bit A/D Converter
AVCC
AVR
AVSS
D/A converter
MPX
Sequential compare register
Comparator
AN7
F2MC-16LX bus
AN1
AN2
AN3
AN4
AN5
AN6
Input circuit
AN0
Decoder
Sample and hold circuit
Data register
ADCR0/ADCR1
A/D control register 0
A/D control register 1
16-bit reload timer 1
ADCS0/
ADCS1
Operation clock
16-bit free-run timer zero detection
φ
Prescaler
φ : Machine clock
● A/D control status register (ADCS0/ADCS1)
This register selects activation by software or another activation trigger, the conversion mode, and the A/D
conversion channel. It also enables or disables interrupt requests, checks the interrupt request status, and
indicates whether the conversion has halted or is in progress.
● A/D data register (ADCR0/ADCR1)
This register holds the result of A/D conversion and selects the resolution for A/D conversion.
544
CHAPTER 20 8/10-BIT A/D CONVERTER
● Clock selector
The clock selector selects the clock for activating A/D conversion. Either 16-bit reload timer channel 1
output or 16-bit free-run timer zero detection can be used as the activation clock.
● Decoder
This circuit selects the analog input pin to be used based on the settings of the ANE0 to ANE2 bits and
ANS0 to ANS2 bits of the A/D control status register (ADCS0).
● Analog channel selector
This circuit selects the pin to be used from eight analog input pins.
● Sample and hold circuit
This circuit maintains the input voltage of the channel selected by the analog channel selector. It samples
and maintains the input voltage obtained immediately after the activation of A/D conversion. This circuit
protects the A/D conversion from any variations in the input voltage during approximation.
● D/A converter
This circuit generates a reference voltage for comparison with the input voltage maintained by the sample
and hold circuit.
● Comparator
This circuit compares the input voltage maintained by the sample and hold circuit with the output voltage
of the D/A converter to determine which is greater.
● Control circuit
This circuit determines the A/D conversion value based on the decision signal generated by the comparator.
When the A/D conversion has been completed, the circuit sets the conversion result in the A/D data register
(ADCR0/ADCR1) and generates an interrupt request.
545
CHAPTER 20 8/10-BIT A/D CONVERTER
20.3
8/10-bit A/D Converter Pins
This section describes the 8/10-bit A/D converter pins and provides pin block diagrams.
■ 8/10-bit A/D Converter Pins
The A/D converter pins are also used as general ports. Table 20.3-1 lists the pin functions, I/O formats, and
settings required to use the 8/10-bit A/D converter.
Table 20.3-1 8/10-bit A/D Converter Pins
Function
Pin name
Channel 0
P50/AN0
Channel 1
P51/AN1
Channel 2
P52/AN2
Channel 3
P53/AN3
Channel 4
P54/AN4
Channel 5
P55/AN5
Channel 6
P56/AN6
Channel 7
P57/AN7
Pin function
Input-output
signal type
Port 5 input/
output or
analog input
CMOS
output/CMOS
hysteresis input or
analog input
Pull-up
option
Not
selectable
Standby
control
I/O port setting for
using the pin
Not
selectable
Set port 5 as an input port
(DDR5: bit8 to bit15 = 0).
Set port 5 as an analog
input port (ADER: bit8 to
bit15 = 1)
■ Block Diagrams of the 8/10-bit A/D Converter Pins
Figure 20.3-1 Block Diagram of the P50/AN0 to P57/AN7 Pins
ADER
Internal data bus
Port data register (PDR)
Analog input
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
546
Standby control (SPL = 1)
CHAPTER 20 8/10-BIT A/D CONVERTER
Notes:
• The MB90460/465 series runs only in single-chip mode so only internal ROM and RAM and
internal peripheral address space can be accessed.
• To use the pin as an analog input pin, set the corresponding bit of the ADER register to "1". The
value read from the PDR5 register is "0".
547
CHAPTER 20 8/10-BIT A/D CONVERTER
20.4
8/10-bit A/D Converter Registers
This section lists the 8/10-bit A/D converter registers.
■ 8/10-bit A/D Converter Registers
Figure 20.4-1 8/10-bit A/D Converter Registers
Analog Input Enable Register
15
14
13
12
11
10
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
RESV
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
W
0
R/W
0
4
3
2
1
0
bit
Address: 000017H
Read/write
Initial value
9
8
ADER
A/D Control Status Register 1
bit
Address: 000035H
Read/write
Initial value
9
8
ADCS1
A./D Control Status Register 2
bit
Address: 000034H
Read/write
Initial value
7
6
5
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
ADCS0
A/D Data Register (Upper)
bit
15
14
13
12
11
Address: 000037H
S10
ST1
ST0
CT1
Read/write
Initial value
R/W
0
W
0
W
0
10
9
8
CT0
D9
D8
W
0
W
0
R
X
R
X
ADCR1
A/D Data Register (Lower)
bit
Address: 000036H
Read/write
Initial value
548
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
ADCR0
CHAPTER 20 8/10-BIT A/D CONVERTER
20.4.1
A/D Control Status Register 1 (ADCS1)
A/D control status register 1 (ADCS1) selects activation by software or activation
trigger, enables or disables interrupt requests, and indicates interrupt request status
and whether conversion is halted or in progress.
■ A/D Control Status Register 1 (ADCS1)
Figure 20.4-2 A/D Control Status Register 1 (ADCS1)
Address
000035H
bit 15
14
13
12
11
BUSY
INT
INTE
PAUS STS1 STS0 STRT RESV
R/W
R/W
R/W
R/W
R/W
10
9
R/W
8
W
7
0
Initial value
(ADCS0)
00000000B
R/W
RESV
Reserved bit
Always write 0 to this bit
A/D conversion activation bit
(valid only when activated by software (ADC2: EXT= 0))
STRT
Does not activate the A/D conversion
Activate the A/D conversion function
0
1
A/D activation select bit
STS1 STS0
0
0
Activation by software
0
1
Activation by external trigger or software
1
0
1
1
Activation by timer or software
Activation by external trigger, timer, or
software
Halt flag bit
(valid only when EI2OS is used)
PAUS
A/D conversion is not halted
A/D conversion is halted
0
1
Interrupt request enable bit
INTE
Disables interrupt request output
1
Enables interrupt request output
Interrupt request flag bit
INT
Read
Write
0
A/D conversion has not been completed
Clears this bit
1
A/D conversion has been completed
No effect
Busy bit
BUSY
R/W : Read/write
W : Write only
- : Undefined
: Initial value
0
Read
Write
0
A/D conveision is halted
Stops the A/D conversion
1
A/D conversion is in progress
No effect
A/D conversion is halt.
549
CHAPTER 20 8/10-BIT A/D CONVERTER
Table 20.4-1 A/D Dontrol Status Register 1 (ADCS1)
Bit name
Function
BUSY:
Busy bit
• This bit indicates the operating status of the A/D converter.
• If the value read from this bit is "0", A/D conversion has halted. If the read value is "1",
A/D conversion is in progress.
• Writing "0" to this bit forces the A/D conversion to stop. Writing "1" to this bit does not
change the bit value and has no effect on other bits.
(Note)
Never select forced stop (BUSY = 0) and software activation (STRT = 1) simultaneously.
bit14
INT:
Interrupt
request flag
bit
• When A/D conversion data is set in the A/D data register, this bit is set to "1".
• When both this bit and the interrupt request enable bit (ADCS: INTE) are "1", an
interrupt request is generated. If EI²OS has been enabled, it is activated.
• Writing "0" to this bit clears the bit. Writing "1" to this bit does not change the bit value
and has no effect on other bits.
• When EI²OS is activated, this bit is cleared.
(Note)
When clearing this bit by writing "0" it, do so only while the A/D converter is not
operating.
bit13
INTE:
Interrupt
request
enable bit
• This bit enables or disables interrupt output to the CPU.
• When both this bit and the interrupt request flag bit (ADCS: INT) are set to "1", an
interrupt request is generated.
• When EI²OS is used, set this bit to "1".
bit12
PAUS:
Halt flag bit
• When A/D conversion stops temporarily, this bit is set to "1".
• This A/D converter has just one A/D data register. In continuous conversion mode, if a
conversion result were written before the previous conversion result was read by the CPU,
the previous result would be lost. When continuous conversion mode is selected, the
program must be written so that the conversion result is automatically transferred to
memory by EI²OS each time a conversion is completed. This bit also protects against
multiple interrupts preventing the completion of conversion data transfer before the next
conversion. When a conversion is completed, this bit is set to "1". This status is
maintained until EI²OS finishes transferring the contents of the data register. Meanwhile,
the A/D conversion is halted so that no conversion data can be stored. When EI²OS
completes the transfer, the A/D converter automatically resumes the conversion.
(Note)
This bit is valid only when EI²OS is used.
bit11,
bit10
STS1, STS0:
A/D
activation
select bit
• These bits select how A/D conversion is to be activated.
• When two or more activation causes are shared, activation is the result of the cause that
occurs first.
(Note)
Change the setting during A/D conversion only while there is no corresponding activation
cause, since the change becomes effective immediately.
bit9
STRT:
A/D
conversion
activation bit
• This bit allows software to start A/D conversion.
• Writing "1" to this bit activates A/D conversion.
• In stop conversion mode, conversion cannot be reactivated with this bit.
• In byte/word instruction, "1" is read.
• In read-modify-write instruction, "0" is read.
(Note)
Never select forced stop (BUSY = 0) and software activation (STRT = 1)
simultaneously.
bit8
RESV:
Reserved bit
(Note)
Always write "0" to this bit.
bit15
550
CHAPTER 20 8/10-BIT A/D CONVERTER
20.4.2
A/D Control Status Register 0 (ADCS0)
A/D control status register 0 (ADCS0) selects the conversion mode and A/D conversion
channel.
■ A/D Control Status Register 0 (ADCS0)
Figure 20.4-3 A/D Control Status Register 0 (ADCS0)
bit 15
Address
000034H
8
(ADCS: H)
6
7
5
4
3
2
1
0
MD1
MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
R/W
R/W
R/W
R/W
R/W
ANE2 ANE1 ANE0
R/W
R/W
Initial value
00000000B
R/W
A/D conversion end channel select bits
0
0
0
AN0 pin
0
0
1
AN1 pin
0
1
0
AN2 pin
0
1
1
AN3 pin
1
0
0
AN4 pin
1
0
1
AN5 pin
1
1
0
AN6 pin
1
1
1
AN7 pin
A/D conversion start channel select bits
ANS2 ANS1 ANS0
Halt
0
0
0
AN0 pin
0
0
1
AN1 pin
0
1
0
AN2 pin
0
1
1
AN3 pin
1
0
0
AN4 pin
1
0
1
AN5 pin
1
1
0
AN6 pin
1
1
1
AN7 pin
MD1
R/W: Read/write
: Initial value
Read during
conversion
Read during a pause in
stop conversion mode
Number of
the current
conversion
channel
Number of the last
conversion channel
MD0
A/D conversion mode select bits
0
0
Single conversion mode 1 (reactivation allowed
during operation)
0
1
Single conversion mode 2 (reactivation not
allowed during operation)
1
0
1
1
Continuous conversion mode (reactivation not
allowed during operation)
Stop conversion mode (reactivation not allowed
during operation)
551
CHAPTER 20 8/10-BIT A/D CONVERTER
Table 20.4-2 A/D Control Status Register 0 (ADCS0)
Bit name
bit7,
bit6
bit5
to
bit3
552
Function
MD1, MD0:
A/D conversion
mode select bits
• These bits select the conversion mode of the A/D conversion function.
• The two-bit value of the MD1 and MD0 bits determines the mode that is selected
from among four modes: single conversion mode 1, single conversion mode 2,
continuous conversion mode, and stop conversion mode.
• The operation in each mode is described below:
Single conversion mode 1:
Just a single A/D conversion from the channel set by ANS2 to ANS0 to the channel
set by ANE2 to ANE0 is performed.
Reactivation during operation is allowed.
Single conversion mode 2:
Just a single A/D conversion from the channel set by ANS2 to ANS0 to the channel
set by ANE2 to ANE0 is performed.
Reactivation during operation is not allowed.
Continuous conversion mode:
A/D conversion from the channel set by ANS2 to ANS0 to the channel set by ANE2
to ANE0 is performed repeatedly. The repeated conversion continues until it is
stopped by the BUSY bit.
Reactivation during operation is not allowed.
Stop conversion mode:
A/D conversion from the channel set by ANS2 to ANS0 to the channel set by ANE2
to ANE0 is performed repeatedly with a pause after the conversion of each channel.
The repeated conversion continues until it is stopped by the BUSY bit.
Reactivation during operation is not allowed. In the pause state, the conversion is
reactivated when an activation cause selected by the STS1 and STS0 bits is
generated.
(Note)
In the single conversion modes, continuous conversion mode, and stop conversion
mode, no reactivation by a timer, external trigger, or software is allowed.
ANS2 to ANS0:
A/D conversion start
channel select bits
• These bits set the A/D conversion start channel and indicate the number of the
current conversion channel.
• When activated, A/D conversion starts from the channel specified by these bits.
• During A/D conversion, the bits indicate the number of the current conversion
channel. During a pause in stop conversion mode, the bits indicate the number of
the last conversion channel.
• As for the lead value of this bit, even when the value is set to this bit, not the set
value but the channel number in which A/D was converted last time is read until the
analog to digital conversion is begun.
• At the reset, the bit is initialized to "000B".
(Notes)
• Do not use a read-modify-write instruction to set the sampling time setting bits
(ST1, ST0), comparison time setting bits (CT1, CT0), or A/D conversion end
channel select bits (ANE2, ANE1, ANE0) after setting the A/D conversion start
channel select bits (ANS2, ANS1, ANS0).
• As for ANS2, ANS1 and ANS0, the last conversion channel is read until A/D
conversion starts. Therefore, if a read-modify-write instruction is used to set the
ST1, ST0 bits, the CT1, CT0 bits, and the ANE2, ANE1 and ANE0 bits after the
ANS2, ANS1 and ANS0 are set, the value of ANS2, ANS1 and ANS0 may be
rewritten.
CHAPTER 20 8/10-BIT A/D CONVERTER
Table 20.4-2 A/D Control Status Register 0 (ADCS0)
Bit name
bit2
to
bit0
ANE2 to ANE0:
A/D conversion end
channel select bits
Function
• These bits set the A/D conversion end channel.
• When activated, A/D conversion is performed up to the channel specified by these
bits.
• When these bits specify the channel specified by ANS2 to ANS0, just that channel
is converted. In continuous or stop conversion mode, the start channel specified by
ANS2 to ANS0 is converted after the channel specified by these bits. If the start
channel is greater than the end channel, the start channel to AN7 and AN0 to the
end channel are converted in that order in a single series of conversions.
553
CHAPTER 20 8/10-BIT A/D CONVERTER
20.4.3
A/D Data Register (ADCR0/ADCR1)
The A/D data register (ADCR0/ADCR1) holds the result of A/D conversion and selects
the resolution of A/D conversion.
■ A/D Data Register (ADCR0/ADCR1)
Figure 20.4-4 A/D Data Register (ADCR0/ADCR1)
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
000037H S10
000036H
R/W
ST1
ST0
CT1
CT0
-
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
-
R
R
R
R
R
R
R
R
R
R
Initial value
00000 -XX
XXXXXXXXB
AD data bits
D9 to D0
Conversion data
CT0
0
1
0
1
44 machine cycles (5.50µs@8MHz)
66 machine cycles (4.12µs@16MHz)
88 machine cycles (5.50µs@16MHz)
176 machine cycles (11.0µs@16MHz)
ST1
0
0
1
1
ST0
0
1
0
1
Sampling time setting bits
20 machine cycles (2.5µs@8MHz)
32 machine cycles (2.0µs@16MHz)
48 machine cycles (3.0µs@16MHz)
128 machine cycles (8.0µs@16MHz)
S10
0
1
554
Comparison time setting bits
CT1
0
0
1
1
AD data bit
10-bit resolution mode (D9 to D0)
8-bit resolution mode (D7 to D0)
CHAPTER 20 8/10-BIT A/D CONVERTER
Table 20.4-3 Function Description of Each bit of A/D Control Status Register 0 (ADCS0)
Bit name
Function
S10:
A/D conversion
resolution
selection bit
• This bit selects an A/D conversion resolution.
• Writing "0" to this bit selects a resolution of 10 bits, and writing "1" to this bit selects a
resolution of 8 bits.
(Note)
The data bit to be used depends on the resolution.
ST1, ST0:
Sampling time
setting bits
• These bits select the sampling time for A/D conversion.
• When A/D conversion is activated, analog input is fetched during the time set in this
bit.
(Note)
Setting these bits to "00B" (for 8 MHz) during 16 MHz operation may disable normal
fetching of the analog voltage.
bit12,
bit11
CT1, CT0:
Comparison time
setting bits
• These bits select the comparison time for A/D conversion.
• After analog input is fetched (i.e., sampling time elapses), conversion result data is
defined and stored in bit9 to bit0 of this register after the time set in these bits.
(Note)
Setting these bits to "00B" (for 8 MHz) during 16 MHz operation may disable normal
acquisition of the analog conversion value.
bit10
Unused bit
• The read value is indeterminate.
• Writing to this bit has no effect on the operation.
D9 to D0:
A/D data bits
• The A/D conversion results are stored and the register is rewritten each time
conversion ends.
• Usually, the last conversion value is stored.
• The initial value of this register is undefined.
(Note)
The conversion data protection function is provided. (See "20.6 Operation of the 8/10bit A/D Converter".) Do not write data to these bits during A/D conversion.
bit15
bit14,
bit13
bit9
to
bit0
Notes:
• To rewrite the S10 bit, do so while the A/D is in a pause before conversion. If the bit is rewritten
after the conversion, the contents of ADCR become undefined.
• To read the contents of the ADCR register in 10-bit mode, use a word transfer instruction (MOVW
A, 0036H, etc.).
555
CHAPTER 20 8/10-BIT A/D CONVERTER
20.5
8/10-bit A/D Converter Interrupts
The 8/10-bit A/D converter can generate an interrupt request when the data for the A/D
conversion is set in the A/D data register. This function supports the extended
intelligent I/O service (EI2OS).
■ 8/10-bit A/D Converter Interrupts
Table 20.5-1 indicates the interrupt control bits of the 8/10-bit A/D converter and the interrupt cause.
Table 20.5-1 Interrupt Control Bits of the 8/10-bit A/D Converter and the Interrupt Cause
8/10-bit A/D converter
Interrupt request flag bit
ADCS1: INT
Interrupt request enable bit
ADCS1: INTE
Interrupt cause
Writing the A/D conversion result to the A/D data register
When A/D conversion is performed and its result is set in the A/D data register (ADCR), the INT bit of the
A/D control status register (ADCS1) is set to "1". If the interrupt request is enabled (ADCS1: INTE = 1),
an interrupt request is output to the interrupt controller.
■ 8/10-bit A/D Converter Interrupts and EI2OS
Table 20.5-2 8/10-bit A/D Converter Interrupts and EI2OS
Interrupt control register
Interrupt no.
#11 (0BH)
Vector table address
EI²OS
Register
name
Address
Lower
Upper
Bank
ICR00
0000B0H
FFFFD0H
FFFFD1H
FFFFD2H
O
O: Available
■ EI2OS Function of the 8/10-bit A/D Converter
Using the EI2OS function, the 8/10-bit A/D converter can transfer the A/D conversion result to memory.
When the transfer is performed, a conversion data protection function halts the A/D conversion until the A/D
conversion data is transferred to memory, and clears the INT bit. The function prevents any part of the data
from being lost.
556
CHAPTER 20 8/10-BIT A/D CONVERTER
20.6
Operation of the 8/10-bit A/D Converter
The 8/10-bit A/D converter has three conversion modes: single conversion mode,
continuous conversion mode, and stop conversion mode. This section describes
operation in each mode.
■ Operation in Single Conversion Mode
In single conversion mode, the analog inputs from the channel specified by the ANS bits to the channel
specified by the ANE bits are sequentially converted. When the channels up to the end channel specified
by the ANE bits have been converted, A/D conversion stops. If the start and end channels are the same
(ANS = ANE), just the channel specified by the ANS bits is converted.
Figure 20.6-1 shows the settings required for operation in single conversion mode.
Figure 20.6-1 Settings for Single Conversion Mode
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADCS BUSY INT INTE PAUS STS1 STS0 STRT RESV MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
ADCR
S10
ST1
ST0
CT1
CT0
-
Holds the conversion data.
: Used
: Set to "1" the bit corresponding to the pin used.
0 : Set "0".
ADER
Reference:
The following are sample conversion sequences in single conversion mode:
ANS = 000B, ANE = 011B : AN0 → AN1 → AN2 → AN3 → End
ANS = 110B, ANE = 010B : AN6 → AN7 → AN0 → AN1 → AN2 End
ANS = 011B, ANE = 011B : AN3 → End
■ Operation in Continuous Conversion Mode
In continuous conversion mode, the analog inputs from the channel specified by the ANS bits to the
channel specified by the ANE bits are sequentially converted. When the end channel specified by the ANE
bits has been processed, A/D conversion starts again from the channel specified by the ANS bits. If the
start and end channels are the same (ANS = ANE), the conversion of the channel specified by the ANS bits
is repeated.
Figure 20.6-2 shows the settings required for operation in continuous conversion mode.
557
CHAPTER 20 8/10-BIT A/D CONVERTER
Figure 20.6-2 Settings for Continuous Conversion Mode
bit
ADCS
ADCR
15
14
BUSY INT
S10
ST1
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTE PAUS STS1 STS0 STRT RESV MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
ST0
CT1
CT0
-
Holds the conversion data.
: Used
: Set to "1" the bit corresponding to the pin used.
1 : Set "1".
0 : Set "0".
ADER
Reference:
The following are sample conversion sequences in continuous conversion mode:
ANS = 000B, ANE = 011B : AN0 → AN1 → AN2 → AN0 → Repeat
ANS = 110B, ANE = 010B : AN6 → AN7 → AN0 → AN1 → AN2 → AN6 → Repeat
ANS = 011B, ANE = 011B : AN3 → AN3 → Repeat
■ Operation in Stop Conversion Mode
In stop conversion mode, the analog inputs from the channel specified by the ANS bits to the channel
specified by the ANE bits are sequentially converted with a pause after the conversion of each channel.
When the end channel specified by the ANE bits has been processed, A/D conversion, with pauses, starts
again with the channel specified by the ANS bits. If the start and end channels are the same (ANS = ANE),
the conversion of the channel specified by the ANS bits is repeated. To reactivate conversion during a
pause, generate the activation cause specified by the STS1 and STS0 bits.
Figure 20.6-3 shows the settings required for operation in stop conversion mode.
Figure 20.6-3 Settings for Stop Conversion Mode
bit
ADCS
ADCR
ADER
558
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BUSY INT INTE PAUS STS1 STS0 STRT RESV MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
S10
ST1
ST0
CT1
CT0
-
Holds the conversion data.
: Used
: Set to "1" the bit corresponding to the pin used.
1 : Set "1".
0 : Set "0".
CHAPTER 20 8/10-BIT A/D CONVERTER
Reference:
The following are sample conversion sequences in stop conversion mode:
ANS = 000B, ANE = 011B :
AN0 → Pause → AN1 → Pause → AN2 → Pause → AN0 → Repeat
ANS = 110B, ANE = 001B :
AN6 → Pause → AN7 → Pause → AN0 → Pause → AN1 → AN6 → Repeat
ANS = 011B, ANE = 011B :
AN3 → Pause → AN3 → Pause → Repeat
559
CHAPTER 20 8/10-BIT A/D CONVERTER
20.6.1
Conversion using EI2OS
The 8/10-bit A/D converter can use EI2OS transfer the A/D conversion result to memory.
■ Conversion using EI2OS
Figure 20.6-4 shows the operation flow when EI2OS is used.
Figure 20.6-4 Sample Operation Flowchart when EI2OS is used
Starting A/D conversion
Sample and hold
Starting EI2OS
Conversion
Transferring data
End of conversion
Has the
data transfer been
Issuing interrupt
YES
repeated for the specified
number of time?*
Interrupt processing
NO
Clearing interrupt
* : The number of timers is determined according to the EI2OS setting.
When EI2OS is used, the conversion data protection function prevents any part of the data from being lost
even in continuous conversion. Multiple data items can be safely transferred to memory.
560
CHAPTER 20 8/10-BIT A/D CONVERTER
20.6.2
A/D Conversion Data Protection Function
When A/D conversion is performed in the interrupt enabled state, the conversion data
protection function operates.
■ A/D Conversion Data Protection Function
The A/D converter has just one data register that holds conversion data. When a single A/D conversion is
completed, the data in the data register is rewritten.
If the conversion data were not transferred to memory before the next conversion data was stored, part of
the conversion data would be lost. The data protection function operates in the interrupt enabled state
(INTE = 1), as described below, to prevent loss of data.
● Data protection function when EI2OS is not used
When conversion data is stored in the A/D data register (ADCR0/ADCR1), the INT bit of the A/D control
status register1 (ADCS1) is set to "1".
While the INT bit is "1", A/D conversion is halted.
Halt status is released when the INT bit is cleared after data in the A/D data register (ADCR0/ADCR1) has
been transferred to memory by the interrupt routine.
● Data protection function when EI2OS is used
In continuous conversion using EI2OS, the PAUS bit of the A/D control status register1 (ADCS1) is kept at
"1" when a conversion ends. This status continues until EI2OS finishes transferring the conversion data
from the data register to memory. In the meantime, the A/D conversion is halted, and the next conversion
data is not stored. When the data transfer to memory is completed, the PAUS bit is cleared to "0" and
conversion resumes.
Figure 20.6-5 shows the operation flow of the data protection function when EI2OS is used.
561
CHAPTER 20 8/10-BIT A/D CONVERTER
Figure 20.6-5 Operation Flowchart of the Data Protection Function when EI2OS is used
Set EI2OS
Start continuous A/D
conversion
End first conversion
Store data in the data
register
Activate EI2OS
End second conversion
Has EI2OS
ended?
NO
Halt A/D
YES
Store data in the data
register
Third conversion
Activate EI2OS
Continue
Terminate all conversions
Continue
Store data in the data
register
Activate EI2OS
Interrupt processing routine
Initialize or stop A/D
End
<Note> The steps while the A/D converter is halted are omitted.
Notes:
562
• The conversion data protection function operates only in the interrupt enabled state (ADCS1: INTE = 1).
• If interrupts are disabled during a pause in A/D conversion while EI2OS is operating, A/D conversion
may start again. This will cause new data to be written before the old data is transferred.
Reactivation attempted during a pause will cause the old data to be destroyed.
• Reactivation attempted during a pause will destroy the standby data.
CHAPTER 20 8/10-BIT A/D CONVERTER
20.7
Usage Notes on the 8/10-bit A/D Converter
Notes on using the 8/10-bit A/D converter.
■ Usage Notes on the 8/10-bit A/D Converter
● Analog input pin
The A/D input pins are also used as the I/O pins of port 5. The port 5 data register (DDR5) and analog
input enable register (ADER) determine which pin is used for which purpose.
To use a pin as analog input, write "0" to the corresponding bit of DDR5 and change the port setting to
input. Then, set the analog input mode (ADEx = 1) in the ADER register and determine the input gate of
the port.
If an intermediate-level signal is input in the port input mode (ADEx = 0), a leakage current flows through
the gate.
● Note on using an internal timer
To start the A/D converter with an internal timer, set the STS1 and STS0 bits of A/D control status register
1 (ADCS1) accordingly. Set the input value of the internal timer at the inactive level (L for the internal
timer). Otherwise, operation may start concurrently with writing to the ADCS register.
● Sequence of turning on the A/D converter and analog input
Do not turn on power to the A/D converter (AVcc, AVR) and to the analog inputs (AN0 to AN7) before the
digital power supply (Vcc) has been turned on.
Do not turn off the digital power supply (Vcc) before power to the A/D converter and the analog inputs has
been turned off.
● Supply voltage to the A/D converter
The supply voltage to the A/D converter (AVcc) must not exceed the digital power supply (Vcc);
otherwise, latch-up may occur.
563
CHAPTER 20 8/10-BIT A/D CONVERTER
20.8
Sample Program 1 for the 8/10-bit A/D Converter
(Single Conversion Mode Using EI2OS)
This section contains a sample program for A/D conversion in single conversion mode
using EI2OS.
■ Sample Program for Single Conversion Mode using EI2OS
● Processing
• Analog inputs AN1 to AN3 are converted once.
• The conversion data is sequentially transferred to addresses 200H to 205H.
• A resolution of 10 bits is selected.
• The conversion is activated by software.
Figure 20.8-1 shows a flowchart of the program using EI2OS (single conversion mode).
Figure 20.8-1 Flowchart of Program using EI2OS (Single Conversion Mode)
Start conversion
AN1 → Interrupt → EI2OS transfer
AN2 → Interrupt → EI2OS transfer
AN3 → Interrupt → EI2OS transfer
End
Interrupt sequence
Parallel processing
● Coding example
564
BAPL
BAPM
BAPH
EQU
EQU
EQU
000100H
000101H
000102H
;Lower buffer address pointer
;Intermediate buffer address pointer
;Upper buffer address pointer
ISCS
IOAL
IOAH
DCTL
DCTH
DDR5
ADER
ICR00
ADCS0
ADCS1
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
000103H
000104H
000105H
000106H
000107H
000015H
000017H
0000B0H
000034H
000035H
;EI2OS status register
;Lower I/O address register
;Upper I/O address register
;Lower data counter
;Upper data counter
;Port 5 direction register
;Analog input enable register
;Interrupt control register for A/DC
;A/D control status register
;
CHAPTER 20 8/10-BIT A/D CONVERTER
ADCR0
EQU
000036H
;A/D data register
ADCR1
EQU
000037H
;
;-------Main program-----------------------------------------------------------------------------------------------------CODE
CSEG
START:
;Assumes that the stack pointer (SP) has already
been initialized
AND
CCR,#0BFH
;Disables interrupts
MOV
ICR00,#00H
;Interrupt level: 0 (highest priority)
MOV
BAPL,#00H
;Sets the address to which the conversion data is
transferred and stored
MOV
BAPM,#02H
;(Uses 200H to 205H.)
MOV
BAPH,#00H
;
MOV
ISCS,#18H
;Transfers word data, adds 1 to the address, then
transfers the data from I/O to memory
MOV
IOAL,#36H
;Sets the address of the analog data register as the
MOV
IOAH,#00H
;transfer source address pointer
MOV
DCTL,#03H
MOV
MOV
MOV
MOV
MOV
DDR5,#11110001B
ADER,#00001110B
DCTH,#00H
ADCS0,#0BH
ADCS1,#0A2H
;Sets the EI2OS transfer count to three, which is the
same value as the conversion count
;Sets P51 to P53 as input
;Sets P51/AN1 to P53/AN3 as analog inputs
;
;Single activation. Converts AN1 to AN3
;Software activation. Begins A/D conversion.
Enables interrupts
;Sets ILM in PS to level 7
;Enables interrupts
;Endless loop
MOV
ILM,#07H
OR
CCR,#40H
LOOP:
MOV
A,#00H
MOV
A,#01H
BRA
LOOP
;-------Interrupt program-------------------------------------------------------------------------------------ED_INT1:
MOV
I:ADCS1,#00H
;Stops A/D conversion. Clears and disables the
interrupt flag
RETI
;Returns from interrupt
CODE
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFD0H
;Sets vector for interrupt #11 (0BH)
DSL
ED_INT1
ORG
0FFDCH
;Sets reset vector
DSL
START
DB
00H
;Sets single-chip mode
VECT
ENDS
END
START
565
CHAPTER 20 8/10-BIT A/D CONVERTER
20.9
Sample Program 2 for the 8/10-bit A/D Converter
(Continuous Conversion Mode Using EI2OS)
This section contains a sample program for A/D conversion in continuous conversion
mode using EI2OS.
■ Sample Program for Continuous Conversion Mode using EI2OS
● Processing
• Analog inputs AN3 to AN5 are converted twice. Two conversion data items are obtained for each
channel.
• The conversion data is sequentially transferred to addresses 600H to 60BH.
• A resolution of 10 bits is selected.
• The conversion is activated by 16-bit reload timer 1.
Figure 20.9-1 shows a flowchart of the program using EI2OS (continuous conversion mode).
Figure 20.9-1 Flowchart of Program using EI2OS (Continuous Conversion Mode)
Start conversion
AN3 → Interrupt → EI2OS transfer
AN4 → Interrupt → EI2OS transfer
After six transfers
AN5 → Interrupt → EI2OS transfer
Interrupt sequence
End
● Coding example
BAPL
BAPM
BAPH
EQU
EQU
EQU
000100H
000101H
000102H
;Lower buffer address pointer
;Middle buffer address pointer
;Upper buffer address pointer
ISCS
EQU
000103H
;EI2OS status register
IOAL
EQU
000104H
;Lower I/O address register
IOAH
EQU
000105H
;Upper I/O address register
DCTL
EQU
000106H
;Lower data counter
DCTH
EQU
000107H
;Upper data counter
DDR5
EQU
000015H
;Port 5 direction register
ADER
EQU
000017H
;Analog input enable register
ICR00
EQU
0000B0H
;Interrupt control register for A/DC
ADCS0
EQU
000034H
;A/D control status register
ADCS1
EQU
000035H
;
ADCR0
EQU
000036H
;A/D data register
ADCR1
EQU
000037H
;
TMCSRL1
EQU
000086H
;Lower control status register 1
TMCSRH1
EQU
000087H
;
TMRD1
EQU
000088H
;16-bit reload register 1
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
566
CHAPTER 20 8/10-BIT A/D CONVERTER
START:
AND
MOV
CCR,#0BFH
ICR10,#08H
MOV
MOV
MOV
MOV
BAPL,#00H
BAPM,#06H
BAPH,#00H
ISCS,#18H
MOV
MOV
IOAL,#36H
IOAH,#00H
MOV
DCTL,#06H
MOV
MOV
MOV
MOV
DDR5,#00000000B
ADER,#00111000B
DCTH,#00H
ADCS0,#9DH
MOV
ADCS1,#0A8H
MOV
MOV
WTMRD1,#0320H
TMCSRH1,#00H
MOV
TMCSRL1,#12H
;Assumes that the stack pointer (SP) has already
been initialized
;Disables interrupts
;Interrupt level; 0 (highest priority). Enables
interrupts
;Sets the address to which conversion data is stored
;(Uses 600H to 60BH.)
;
;Transfers word data, adds 1 to the address, then
;transfers from I/O to memory
;Sets the address of the analog data register as the
;transfer source address pointer
;Six transfers by EI2OS (two transfers each for three
channels)
;Sets P50 to P57 as input
;Sets P53/AN3 to P55/AN5 as analog input
;
;Continuous conversion mode. Converts
AN3 to AN5 CH
;Activates the 16-bit timer, starts A/D conversion,
and enables interrupts
;Sets the timer value to 800 (320H), 100µs
;Sets the clock source to 125 ns and disables
external trigger
;Disables timer output, disables interrupts, and
enables reload
;Activates the 16-bit reload timer 1
;Sets ILM in PS to level 7
;Enables interrupts
;Endless loop
MOV
TMCSRL1,#13H
MOV
ILM,#07H
OR
CCR,#40H
LOOP:
MOV
A,#00H
MOV
A,#01H
BRA
LOOP
;-------Interrupt program------------------------------------------------------------------------------------------------ED_INT1:
MOV
I:ADCS1,#80H
;Does not stop A/D conversion. Clears and disables
the interrupt flag
RETI
;Returns from interrupt
CODE
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFD0H
;Sets vector for interrupt #11 (0BH)
DSLED_INT1
ORG
0FFDCH
;Sets reset vector
DSL
START
DB
00H
;Sets single-chip mode
VECT
ENDS
ENDSTART
567
CHAPTER 20 8/10-BIT A/D CONVERTER
20.10
Sample Program 3 for the 8/10-bit A/D Converter
(Stop Conversion Mode Using EI2OS)
This section contains a sample program for A/D conversion in stop conversion mode
using EI2OS.
■ Sample Program for Stop Conversion Mode using EI2OS
● Processing
• Analog input AN3 is converted 12 times at regular intervals.
• The conversion data is sequentially transferred to addresses 600H to 617H.
• A resolution of 10 bits is selected.
• The conversion is activated by 16-bit reload timer 1.
Figure 20.10-1 shows a flowchart of the program using EI2OS (stop conversion mode).
Figure 20.10-1 Flowchart of Program using EI2OS (Stop Conversion Mode)
AN3 → Interrupt → EI2OS transfer
Start conversion
After 12 transfers
Stop
Interrupt sequence
Activation by 16-bit reload timer 1
End
● Coding example
568
BAPL
BAPM
BAPH
EQU
EQU
EQU
000100H
000101H
000102H
;Lower buffer address pointer
;Middle buffer address pointer
;Upper buffer address pointer
ISCS
IOAL
IOAH
DCTL
DCTH
DDR5
ADER
ICR00
ADCS0
ADCS1
ADCR0
ADCR1
TMCSRL1
TMCSRH1
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
000103H
000104H
000105H
000106H
000107H
000015H
000017H
0000B0H
000034H
000035H
000036H
000037H
000086H
000087H
;EI2OS status register
;Lower I/O address register
;Upper I/O address register
;Lower data counter
;Upper data counter
;Port 5 direction register
;Analog input enable register
;Interrupt control register for A/DC
;A/D control status register
;
;A/D data register
;
;Lower control status register 1
;
CHAPTER 20 8/10-BIT A/D CONVERTER
TMRD1
EQU
000088H
;16-bit reload register 1
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
START:
;Assumes that the stack pointer (SP) has already
been initialized
AND
CCR,#0BFH
;Disables interrupts
MOV
ICR00,#08H
;Interrupt level: TMCSR1:L0 (highest priority)
MOV
BAPL,#00H
;Sets the address to which conversion data is stored
MOV
BAPM,#06H
;(Uses 600H to 617H.)
MOV
BAPH,#00H
;
MOV
ISCS,#19H
;Transfers word data, adds 1 to the address,
;transfers from I/O to memory, then ends by a
;resource request
MOV
IOAL,#36H
;Sets the address of the analog data register as the
MOV
IOAH,#00H
;transfer source address pointer
MOV
MOV
MOV
MOV
MOV
DCTL,#0CH
DDR5,#00000000B
ADER,#00001000B
ADCS0,#0DBH
ADCS1,#0A8H
MOV
MOV
WTMRD1,#0320H
TMCSRH1,#00H
MOV
TMCSRL1,#12H
;Transfers only channel 3 twelve times by EI2OS
;Sets P50 to P57 as input
;Sets P53/AN3 as analog input
;Stop conversion mode. Converts AN3 CH
;Activates the 16-bit timer, starts A/D conversion,
and enables interrupts
;Sets the timer value to 800 (320H), 100 µs
;Sets the clock source to 125 ns and disables
external trigger
;Disables timer output, disables interrupts, and
enables reload
;Activates the 16-bit reload timer 1
;Sets ILM in PS to level 7
;Enables interrupts
;Endless loop
MOV
TMCSRL1,#13H
MOV
ILM,#07H
OR
CCR,#40H
LOOP:
MOVA,#00H
MOVA,#01H
BRA
LOOP
;-------Interrupt program------------------------------------------------------------------------------------------------ED_INT1:
MOV
I:ADCS1,#80H
;Does not stop A/D conversion. Clears and disables
the interrupt flag
RETI
;Returns from interrupt
CODE
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG0
FFD0H
;Sets vector for interrupt #11 (0BH)
DSL
ED_INT1
ORG
0FFDCH
;Sets reset vector
DSL
START
DB
00H
;Sets single-chip mode
VECT
ENDS
END
START
569
CHAPTER 20 8/10-BIT A/D CONVERTER
570
CHAPTER 21
ROM CORRECTION
FUNCTION
This chapter describes the functions and operation of
the ROM correction function.
21.1 Overview of the ROM Correction Function
21.2 Block Diagram of ROM Correction Function
21.3 ROM Correction Function Registers
21.4 Operation of the ROM Correction Function
21.5 Example of Using ROM Correction Function
571
CHAPTER 21 ROM CORRECTION FUNCTION
21.1
Overview of the ROM Correction Function
An instruction code to be read by the CPU is replaced forcibly with an INT9 instruction
code (01H) when the corresponding address is equal to the value set in a program
address detect register. A program patch application function can be implemented by
processing with the INT #9 interrupt routine.
■ Program Address Detection Registers (× 2)
There are two program address detection registers (PADR0/PADR1), each is provided with an interrupt
enable bit and interrupt flag.
■ ROM Correction Interrupts
When the interrupt enable bit is "1", the value set in the program address detection register is compared
with the address. If the value matches the address, "1" is set in the interrupt flag bit and the instruction code
to be read to the CPU, is forcibly replaced with an INT9 instruction code.
The interrupt flag bit is cleared to "0" by writing "0" to it using an instruction.
572
CHAPTER 21 ROM CORRECTION FUNCTION
21.2
Block Diagram of ROM Correction Function
The block diagram of ROM correction function is shown as below.
■ Block Diagram of ROM Correction Function
Figure 21.2-1 Block Diagram of ROM Correction Function
Address latch
Comparator
INT9
command
F2MC-16LX bus
Address detection register 0/1
F2MC-16LX
AD0E/AD1E AD0D/AD1D
PACSR
CPU
573
CHAPTER 21 ROM CORRECTION FUNCTION
21.3
ROM Correction Function Registers
The section lists the ROM correction function registers.
■ ROM Correction Function Registers
Figure 21.3-1 Registers of ROM Correction Function
Program Address Detection Register 0/1
Upper byte
Middle byte
Lower byte
Address : 1FF2H/1FF1H/1FF0H
PADRH0
PADRM0
PADRL0
PADR0
Address : 1FF5H/1FF4H/1FF3H
PADRH1
PADRM1
PADRL1
PADR1
Read/write
Initial value
(R/W)
(XXXXXXXXB)
(R/W)
(XXXXXXXXB)
(R/W)
(XXXXXXXXB)
Program Address Detection Control Status Register
bit
Address : 00009EH
Read/write
Initial value
574
7
6
5
4
3
2
1
0
—
—
—
—
AD1E
AD1D
AD0E
AD0D
(-)
(0)
(-)
(0)
(-)
(0)
(-)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
PACSR
CHAPTER 21 ROM CORRECTION FUNCTION
21.3.1
Program Aaddress Detection Register (PADR0/PADR1)
The program address detection register (PADR0/PADR1) is a 24-bit register and used to
store the address to be compared with internal address bus.
■ Program Address Detection Register 0/1 (PADR0/PADR1)
Figure 21.3-2 Program Address Detection Register 0/1
Program Address Detection Register 0/1
Upper byte
Middle byte
Lower byte
Address : 1FF2H/1FF1H/1FF0H
PADRH0
PADRM0
PADRL0
PADR0
Address : 1FF5H/1FF4H/1FF3H
PADRH1
PADRM1
PADRL1
PADR1
Read/write
Initial value
(R/W)
(XXXXXXXXB)
(R/W)
(XXXXXXXXB)
(R/W)
(XXXXXXXXB)
The value written to this register is compared with a target address. If the value matches the address, and
the corresponding interrupt enable bit of the PACSR register is "1", the corresponding interrupt bit is set to
"1" to request the CPU to generate an INT9 instruction. If the corresponding interrupt enable bit is "0", no
operation is performed.
Table 21.3-1 lists the correspondence between the program address detection register and PACSR.
Table 21.3-1 Correspondence between Program Address Detection Register and PACSR
Program address detection register
Interrupt enable bit
Interrupt bit
PADR0
AD0E
AD0D
PADR1
AD1E
AD1D
575
CHAPTER 21 ROM CORRECTION FUNCTION
21.3.2
Program Address Detection Control Status Register
(PACSR)
The program address detection control status register (PACSR) is an 8-bit register and
used to control the operation of ROM correction function.
■ Program Address Detection Control Status Register (PACSR)
Figure 21.3-3 Program Address Detection Control Status Register
Address
bit 7
6
5
4
3
2
1
0
Initial value
00009EH
—
—
—
—
AD1E
AD1D
AD0E
AD0D
----0000B
—
—
—
—
R/W
R/W
R/W
R/W
Address detection flag 0 bit
AD0D
Read
Write
0
No address compare match
Clear this bit
1
Address compare match
No effect
AD0E
Address detection register 0 enable bit
0
Disable interrupt request
1
Enable interrupt request
Address detection flag 1 bit
AD1D
Read
Write
0
No address compare match
Clear this bit
1
Address compare match
No effect
Address detection register 1 enable bit
AD1E
R/W : Readable and writable
: Initial value
—
576
: Not used
Read
Write
0
No address compare match
Clear this bit
1
Address compare match
No effect
CHAPTER 21 ROM CORRECTION FUNCTION
Table 21.3-2 Program Address Detection Control Status Register
Bit name
Function
bit7
to
bit4
Reserved bits
• Always write “0” to these bits.
bit3
AD1E:
Address detection register 1
enable bit
• ADR1 operation enable bit.
• When this bit is “1”, the value set in the PADR1 register is compared with the
address. If the two values are equal, an INT9 instruction is generated and the
AD1D bit is set to “1”.
bit2
AD1D:
Address detection flag 1 bit
• ADR1 address match detection bit.
• This bit is set to “1” to indicate that the value set in the PADR1 register
matches the address. It is cleared to “0” by writing “0” to it. It is left
unchanged by writing “1” to it.
bit1
AD0E:
Address detection register 0
enable bit
• ADR0 operation enable bit.
• When this bit is “1”, the value set in the PADR0 register is compared to the
address. If the two values are equal, an INT9 instruction is generated and the
AD0D bit is set to “1”.
bit0
AD0D:
Address detection flag 0 bit
• ADR0 address match detection bit.
• This bit is set to “1” to indicate that the value set in the PADR0 register is
equal to the address. It is cleared to “0” by writing “0” to it. It is left
unchanged by writing “1” to it.
577
CHAPTER 21 ROM CORRECTION FUNCTION
21.4
Operation of the ROM Correction Function
If the program counter specifies the same address as that in program address detection
register (PADR), the INT9 instruction is executed. The ROM correction function can be
done by processing the INT9 instruction routine.
■ Operation of the ROM Correction Function
An instruction code to be read by the CPU is replaced forcibly with an INT9 instruction code (01H) when
the corresponding address is equal to the value set in an address detection register. Therefore, the CPU
executes the INT9 instruction when executing the set instruction.
A program patch application function can be implemented by processing with the INT #9 interrupt routine.
There are two address detection registers, of which each is provided with an interrupt enable bit and
interrupt flag. When the address is equal to the value set in the address detection register, and the interrupt
enable bit is "1", assume the following: the interrupt flag is set to "1", and the instruction code to be read
by the CPU is replaced forcibly with the INT9 instruction code. The interrupt flag is cleared to "0" by
writing "0" to it using an instruction.
Note:
578
The address match detection function fails if an address later than the first byte of the instruction is
set in the address detection register. The value in the set address is replaced with "01H"so a wrong
instruction is executed or an invalid address is accessed. Before changing the value set in the
address detection register, set the interrupt enable bit to "0". If data is written while the interrupt
enable bit is "1", the address may be wrongly detected during writing, causing a malfunction.
CHAPTER 21 ROM CORRECTION FUNCTION
21.5
Example of Using ROM Correction Function
This section contains example of Using the Address Match Detection Function.
■ System Configuration
Figure 21.5-1 System Configuration Example
E2PROM
MCU
F2MC-16LX
Pull-up resistor
Connector (UART)
SIN
■ E2PROM Memory Map
Table 21.5-1 E2PROM Memory Map
Address
Meaning
0000H
Number of bytes of patch program No. 0
(0 for no program error)
0001H
Bit7 to bit0 of program address No. 0
0002H
Bit15 to bit8 of program address No. 0
0003H
Bit24 to bit26 of program address No. 0
0004H
Number of bytes of patch program No. 1
(0 for no program error)
0005H
Bit7 to bit0 of program address No. 1
0006H
Bit15 to bit8 of program address No. 1
0007H
Bit24 to bit16 of program address No. 1
to 0010H+
Number of bytes of patch program No. 0
Original of patch program No. 0
■ Initial State
The contents of E2PROM are all 0's.
579
CHAPTER 21 ROM CORRECTION FUNCTION
■ If a Program Error Occurs
The original of a patch program and its address is transferred to the MCU via the connector (UART). The
MCU writes the information to E2PROM.
■ Reset Sequence
After the reset sequence is completed, the MCU reads the value of E2PROM. If the number of bytes of the
patch program is not 0, the MCU reads the original patch program and writes it to RAM. Then, the MCU
sets the program address to PADR0 or PADR1 and enables the program to run. The first address of the
program written to RAM is saved in RAM as specified for each address detection register.
■ INT9 Interrupt
During execution of an interrupt routine, control checks the interrupt flag for an address in which an
interrupt was enabled, and branches to the corresponding program. The information stacked by the interrupt
is deleted. The interrupt flag is also cleared.
Figure 21.5-2 System Configuration Example
MB90460/465 series
FFFFFFH
(3)
Abnormal program
ROM
(1)
PC = Trigger address
External E2PROM
O Number of program byte
Register setting
for ROM correction
O Interrupt trigger address
O Corrected program
Data sent via UART
RAM
Corrected program
(2)
000000H
580
CHAPTER 21 ROM CORRECTION FUNCTION
Figure 21.5-3 Flowchart of Program Patch Processing
Reset
Read the 00H of E2PROM
INT9
YES
0000H (E2PROM) = 0
NO
Clear interrupt program
Read the address
0001H to 0003H (E2PROM)
MOV
PADR0 (MCU)
To patch program
JMP 000400H
Read the patch program
0010H to 0090H (E2PROM)
MOV
Patch program execution
000400H to 000480H
000400H to 000480H (MCU)
Enable compare
End of patch program
JMP FF0050H
MOV PACSR, #02H
Normal program execution
MB90462/467
NO
FFFFFFH
PC = PADR0
FF0050H
YES
E2PROM
INT9
ROM
Abnormal program
FFFFH
FF0000H
0090H
FE0000H
Patch program
0010H
001100H
Stack area
Lower program address: 00
RAM area
0003H
Middle program address: 00
0002H
Upper program address: 00
0001H
0000H
Size of patch
program in byte: 80
RAM
000480H
Patch program
000400H
RAM / Register area
000100H
I/O area
000000H
581
CHAPTER 21 ROM CORRECTION FUNCTION
582
CHAPTER 22
ROM MIRRORING FUNCTION
SELECTION MODULE
This chapter explains the function and operation of the
MB90460/465 series ROM mirroring function selection
module.
22.1 Overview of the ROM Mirroring Function Selection Module
22.2 ROM Mirroring Function Selection Register (ROMM)
583
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE
22.1
Overview of the ROM Mirroring Function Selection Module
The ROM mirroring function selection module can access bank FF located in ROM from
bank 00 by setting the register.
■ ROM Mirroring Function Selection Module Register
ROM Mirror Function Selection Register
bit
Address : 00006FH
Read/write
Initial value
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
MI
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(W)
(1)
(–)
■ ROM Mirroring Function Selection Module Block Diagram
Figure 22.1-1 ROM Mirroring Function Selection Module Block Diagram
F2MC-16LX bus
ROM mirroring register
Address area
FF bank
00 bank
ROM
584
ROMM
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE
22.2
ROM Mirroring Function Selection Register (ROMM)
The ROM mirroring function selection register (ROMM) is used to enable mirroring
function.
■ ROM Mirroring Function Selection Register (ROMM)
Figure 22.2-1 ROM Mirroring Function Selection Register
bit 15
14
13
12
11
10
9
8
Reserved ReservedReservedReservedReserved ReservedReserved
MI
R/W R/W R/W R/W R/W R/W R/W
W
Reset value
XXXXXXX1B
bit8
MI
0
1
R/W : Readable and writable
W
: Write only
: Indeterminate
X
: Initial value
ROM mirroring function selection bit
Disable ROM mirroring function
Enable ROM mirroring function
bit15 to bit9
Reserved bit
Reserved
0
Always write "0" to these bits.
Table 22.2-1 ROM Mirroring Function Selection Register
Bit name
Function
bit15
to
bit9
Reserved bits
The read value is undefined.
Always write "0" to these bits.
bit8
MI:
ROM mirroring
function select bit
This bit enables or disables the ROM mirroring function.
When set to "0": Disables ROM mirroring function
When set to "1": Enables ROM mirroring function
When the ROM mirroring function is enabled (MI = 1), data at ROM addresses
FF4000H to FFFFFFH can be read by accessing addresses 004000H to 00FFFFH.
Note:
Bank 00 accesses FF4000H to FFFFFFH from 004000H to 00FFFFH. Therefore, FFF000H to
FF3FFFH cannot be accessed even by selecting the ROM mirroring function.
585
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE
MB90462
MB90467
MB90F462
MB90F462A
MB90F463A
MB90V460
Address 1
FF0000H
FF0000H
FF0000H
FF0000H
FE0000H
FF0000H
Address 2
000900H
000900H
000900H
000900H
000900H
002100H
Figure 22.2-2 Memory Space
Address
FFFFFFH
Address 1
ROM area
ROM area
010000H
ROM area
004000H
002000H
Address 2
RAM area
RAM area
I/O area
I/O area
000100H
0000C0H
000000H
When MI = 1
586
When MI = 0
Internal
area
CHAPTER 23
512K / 1024K BIT FLASH
MEMORY
The following explains the functions and operations of
the 512K / 1024K bit flash memory.
Three methods of data writing/deleting to the flash
memory are provided:
23.1 Overview of the 512K / 1024K Bit Flash Memory
23.2 512K / 1024K Bit Flash Memory Sector Configuration
23.3 Flash Memory Control Status Register (FMCS)
23.4 Method of Starting the Automatic Algorithm in Flash Memory
23.5 Verifying Automatic Algorithm Execution Status
23.6 Detailed Explanation on the Flash Memory Write/Delete
23.7 Flash Security Feature
23.8 Programming Example of 512K Bit Flash Memory
587
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.1
Overview of the 512K / 1024K Bit Flash Memory
The 512K bit flash memory is allocated in the FF bank on the CPU memory map while
1024K bit flash memory is allocated in FE and FF bank. The function of the flash
memory interface circuit enables the read/access or program access from the CPU to
the flash memory, same as the mask ROM. The write/delete operation to the flash
memory can be executed through the flash memory interface circuit by executing an
instruction issued from the CPU. Therefore, the flash memory mounted can be
rewritten under the control of the internal CPU, so that the program or data can be
upgraded or updated more efficiently. However, no selector operation such as the
enable sector protect can be used.
■ Characteristics of the 512K / 1024K Bit Flash Memory
• 512K Bit: 64K words x 8 bits/32K words x 16 bits
(16K+8K+8K+32K) sector configuration
• 1024K Bit: 128K words x 8 bits/64K words x 16 bits
(64K+16K+8K+8K+32K) sector configuration
• Automatic program algorithm (same as the Embedded Algorithm TM *
: MBM29F400TA)
• Installation of the deletion temporary stop/delete restart function
• Write/delete completion detected by the data polling or toggle bit
• Write/delete completion detected by the CPU interrupt
• Compatibility with the JEDEC standard-type command
• Each sector deletion can be executed (Sectors can be freely combined)
• Number of write/delete operations 10,000 times guaranteed
*: Embedded AlgorithmTM is the trademark of Advanced Micro Devices, Inc.
■ Procedure for Writing/Deleting the data to the Flash Memory
The write/delete operation of the flash memory cannot be executed simultaneously. In executing the data
write/delete operation in the flash memory, only the write operation can be executed without a program
access from the flash memory, by copying a program on the flash memory to RAM and executing the
program.
■ Register on the Flash Memory
• Flash memory control status register (FMCS)
bit
Address:0000AEH
Read/Write
Initial value
588
7
INTE
(R/W)
(0)
6
5
4
3
2
RDYINT
WE
RDY
Reserved
LPM1
(R/W)
(0)
(R/W)
(0)
(R)
(1)
(W)
(0)
(W)
(0)
1
Reserved
(W)
(0)
0
LPM0
(R/W)
(0)
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.2
512K / 1024K Bit Flash Memory Sector Configuration
Figure 23.2-1 and Figure 23.2-2 and shows the sector configuration in the 512K bit flash
memory. The address indicated in Figure 23.2-1 and Figure 23.2-2 is classified into the
upper address and lower address of each sector.
■ Sector Configuration
When accessing the 512Kbit flash memory from the CPU, four sector addresses, SA0 to SA3, are allocated
in the FF bank register.
Figure 23.2-1 512K Bit Flash Memory Sector Configuration
Flash memory
SA3 (16 Kbytes)
SA2 (8 Kbytes)
SA1 (8 Kbytes)
SA0 (32 Kbytes)
CPU address
*Writer address
FFFFFFH
7FFFFH
FFC000H
FFBFFFH
7C000H
7BFFFH
FFA000H
7A000H
FF9FFFH
79FFFH
FF8000H
FF7FFFH
78000H
77FFFH
FF0000H
70000H
When accessing the 1024Kbit flash memory from the CPU, five sector addresses, SA0 to SA4, are
allocated in the FE and FF bank register.
Figure 23.2-2 1024K Bit Flash Memory Sector Configuration
Flash memory
SA4 (16 Kbytes)
SA3 (8 Kbytes)
SA2 (8 Kbytes)
SA1 (32 Kbytes)
CPU address
FFFFFFH
7FFFFH
FFC000H
FFBFFFH
7C000H
7BFFFH
FFA000H
7A000H
FF9FFFH
79FFFH
FF8000H
78000H
77FFFH
FF7FFFH
FF0000H
SA0 (64 Kbytes)
*Writer address
FEFFFFH
70000H
6FFFFH
FE0000H
60000H
*: Writer address
The writer address is equivalent to the CPU address when writing the data to the flash memory using the
parallel writer. If the write/delete operation is executed using the general-purpose writer, the write/delete
operation is executed using this address.
589
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.3
Flash Memory Control Status Register (FMCS)
The FMCS, which exists in the flash memory interface circuit, is used when data is
written to or erased from flash memory.
■ Control Status Register (FMCS)
bit
Address:0000AEH
Read/Write
Initial value
7
INTE
(R/W)
(0)
6
5
4
3
2
RDYINT
WE
RDY
Reserved
LPM1
(R/W)
(0)
(R/W)
(0)
(R)
(1)
(W)
(0)
(W)
(0)
1
Reserved
(W)
(0)
0
LPM0
(R/W)
(0)
● Contents of the bits
[bit7] INTE (Interrupt Enable)
This bit generates an interrupt to the CPU when the write/delete operation to the flash memory is
terminated.
When the INTE bit is "1" and the RDYINT bit is "1" an interrupt generated and sent to the CPU. If the
INTE bit is "0", no interrupt is generated:
0: Interrupt disabled when the write/delete operation is terminated.
1: Interrupt enabled when the write/delete operation is terminated.
[bit6] RDYINT (Ready Interrupt)
This bit indicates the flash memory operating status.
After the write/delete to the flash memory is terminated, this bit is set to "1". While this bit is "0" after
the end of write/delete operation to the flash memory, the flash memory cannot be written or deleted.
After the write/delete operation is terminated and this bit is set to "1", the flash memory can be written
or deleted. This bit is cleared to "0" by writing "0" and the writing of "1" is ignored. At the termination
time of the automatic algorithm in the flash memory (see "23.4 Method of Starting the Automatic
Algorithm in Flash Memory"), this bit is set to "1". While using the read modify write (RMW)
instruction, "1" can be read at any time.
0: During the write/delete operation
1: Write/delete operation terminated (An interrupt request is generated)
[bit5] WE (Write Enable)
This bit is the write enable bit for the flash memory area.
When this bit is "1", the write instruction after issuing command sequence to FF bank (see "23.4
Method of Starting the Automatic Algorithm in Flash Memory") is equivalent to writing to the flash
memory area. When this bit is "0", no write/delete signal is generated. This bit is used when the flash
memory write/delete command is started.
0: Flash memory write/delete disabled
1: Flash memory write/delete enabled
590
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
[bit4] RDY (Ready)
This bit is the flash memory write/delete permission bit.
While this bit is "0", the write/delete cannot be executed to the flash memory. Even in this state,
however, suspend commands such as the read/reset command and the sector deletion temporary stop
can be accepted.
0: During the write/delete operation
1: Write/delete operation terminated (Next data write/delete operation permitted)
[bit3, bit1] Reserved bits
These bits are the reserved bits for testing. When these bits are usually used, they must be set to "0".
[bit2, bit0] LPM1, LPM0 (Low-power Mode)
These bits control the current consumption in the flash memory when accessing the flash memory.
However, the access time from the CPU to the flash memory greatly dependent upon the setting.
Therefore, the set values should be selected, depending on the CPU operating frequency.
01: Low-power consumption mode
(Internal operating frequency operating at 4 MHz or less)
10: Low-power consumption mode
(Internal operating frequency operating at 8 MHz or less)
11: Low-power consumption mode
(Internal operating frequency operating at 10 MHz or less)
00: Normal power consumption mode
(Internal operating frequency operating at 12.58 MHz or less)
Note:
The RDYINT bit and RDY bit are not changed simultaneously. Create a program using one of the
RDYINT bit or RDY bit for determination.
Automatic algorithm
Termination time
RDYINT bit
RDY bit
1 machine cycle
591
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.4
Method of Starting the Automatic Algorithm in Flash
Memory
There are four types of commands for starting the automatic algorithm in the flash
memory, i.e., the read/reset command, write command, and chip deletion command. In
addition, the sector deletion command can be temporarily stopped and restarted.
■ Command Sequence Table
Table 23.4-1 lists the commands to be used for writing/deleting the data to the flash memory. All the data
is written to the command register in units of bytes, though it should be accessed and written in units of
words.
In this case, the data in the upper bytes is ignored.
Table 23.4-1 Command Sequence Table
Bus 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle
Command
write
sequence
cycle Address
Data
Address
Data
Address
Data
Ad-dress
Data
Address
Data
Address
Data
Read/reset
1
FFXXXX
XXF0
-
-
-
-
-
-
-
-
-
-
Read/reset
4
FFAAAA
XXAA
FF5554
XX55
FFAAAA
XXF0
RA
RD
-
-
-
-
Write
program
4
FFAAAA
XXAA
FF5554
XX55
FFAAAA
XXA0
PA (even)
PD
(word)
-
-
-
-
Chip
deletion
6
FFAAAA
XXAA
FF5554
XX55
FFAAAA
XX80
FFAAAA
XXAA
FF5554
XX55
FFAAAA
XX10
Sector
deletion
6
FFAAAA
XXAA
FF5554
XX55
FFAAAA
XX80
FFAAAA
XXAA
FF5554
XX55
SA (even)
XX30
Sector deletion temporary stop Temporarily stops the sector deletion command when inputting Address "FFXXXX" Data(xxB0H).
Sector deletion restart
Restarts the sector deletion command when inputting Address "FFXXXX" Data(xx30H).
* : Two types of read/reset commands can reset the flash memory to the read mode.
Note:
592
The addresses in the above table are the values on the CPU memory map. All the addresses and
data are represented in hexadecimal. However, "X" is an optional value.
RA: Read address
PA: Write address. Only the even address can be specified.
SA: Sector address.
For details, see "23.2 512K / 1024K Bit Flash Memory Sector Configuration"
RD: Read data
PD: Write data. Only the word data can be specified
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.5
Verifying Automatic Algorithm Execution Status
The flash memory contains the hardware for posting the internal flash memory
operating status or the flash memory operation completion, because the automatic
algorithm executes the sequence of data writing/deleting procedures. This automatic
algorithm can verify the internal flash memory operating status, depending on the
following hardware sequence.
■ Hardware Sequence Flag
The hardware sequence flag consists of the four flag bits, DQ7, DQ6, DQ5, and DQ3. These flag bits have
the data polling flag (DQ7) function, toggle bit flag (DQ6) function, time limit exceeded flag (DQ5)
function, and sector deletion timer flag (DQ3) function, respectively. These functions can verify whether
the write/chip sector deletion is terminated or whether the deletion code write is valid.
The hardware sequence flag can be referenced by accessing/reading the address of the target sector in the
flash memory, after setting the command sequence (see "23.4 Method of Starting the Automatic Algorithm
in Flash Memory"). Table 23.5-1 indicates the hardware sequence flag bit allocation.
Table 23.5-1 Hardware Sequence Flag Bit Allocation
Bit no.
Hardware
sequence flag
7
6
5
4
3
2
1
0
DQ7
DQ6
DQ5
-
DQ3
-
-
-
It can be determined whether automatic write/chip sector deletion is being performed, depending on the end
of write processing, by checking the hardware sequence flag or the RDY bit in the flash memory control
register (FMCS). After the write/delete operation is terminated, the flash memory is returned to the read/
reset status. To actually create a program, it should be verified whether automatic write/delete operation is
terminated, depending on any flag, and the next operation such as the data reading should be executed.
Also, it can be verified whether the second sector deletion code write command or later commands are
valid, depending on the hardware sequence flag. The following explains the hardware sequence flags.
Table 23.5-2 lists the hardware sequence flag functions.
593
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
Table 23.5-2 Hardware Sequence Flag Functions
State
DQ7
DQ6
DQ5
DQ3
DQ7 -->
DATA:7
Toggle -->
DATA:6
0 -->
DATA:5
0 -->
DATA:3
Chip/sector deletion
operation --> Deletion
completion
0 --> 1
Toggle -->
Stop
0 --> 1
1
Sector deletion wait -->
Deletion start
0
Toggle
0
0 --> 1
Deletion processing -->
Sector deletion
temporary stop (sector
being deleted)
0 --> 1
Toggle --> 1
0
1 --> 0
Sector deletion
temporary stop -->
Deletion restart (sector
being deleted)
1 --> 0
1 --> Toggle
0
0 --> 1
While the sector
deletion is being
temporarily stopped -->
(sector not being deleted)
DATA:7
DATA:6
DAATA:5
DATA:3
DQ7
Toggle
1
0
0
Toggle
1
1
Write operation --> Write
completion (when the
write address is specified)
Status
transition during
normal
operation
Write operation
Abnormal operation
594
Chip/sector deletion
operation
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.5.1
Data Polling Flag (DQ7)
The data polling flag (DQ7) indicates whether the automatic algorithm is being executed
or has been terminated, using the data polling function. Table 23.5-3 shows the data
polling flag status transition.
■ When the Write Operation is Executed.
When the read/access is executed during automatic write algorithm execution, the flash memory outputs the
reverse data of bit7 in the last-written data, irrespective of the specified address. When the read/access is
executed at the end of the automatic write algorithm, the flash memory outputs the data of bit7 in the
specified read address. When the read/access is executed at the end of the automatic write algorithm, the
flash memory outputs the data of bit7 in the specified read address.
■ When the Chip/Sector Deletion Operation is Executed.
When the read/access is executed during the chip/sector deletion algorithm execution, the flash memory
outputs "0" from the sector being deleted by the sector deletion, or irrespective of the specified address
during the chip deletion. Similarly, the flash memory outputs "1" at the end of chip/sector deletion
algorithm.
■ When the Sector Deletion Temporary Stop is Executed.
When the access/read is executed while executing the sector deletion temporary stop, the flash memory
outputs "1" if the specified address is the sector being deleted. However, the flash memory outputs the data
of bit7 (DATA:7) of the specified read address, if the specified address is not the sector being deleted. By
referencing this together with the toggle bit flag (DQ6), it can be determined whether the current sector is
in the temporary stop state or which sector is being deleted.
Note:
When the automatic algorithm is started, the read/access to the specified address is ignored. As for
the data reading, the end of data polling flag (DQ7) is posted, and then other data bit can be output.
Therefore, the data read operation after the end of the automatic algorithm should be executed next
to the read/access after verifying the end of data polling flag.
595
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
Table 23.5-3 Data Polling Flag Station Transition
- Status transition during normal operation
Operating
status
Sector deletion
-->Deletion
Chip/sector
Sector deletion temporary stop
Write operation
deletion
wait-->Start
--> Completion
(Sector being
-->Completion
deleted)
DQ7-->DATA:7
DQ7
0-->1
0-->1
0
- Status transition during abnormal operation
Operating status
Write operation
Chip/sector deletion operation
DQ7
DQ7
0
596
Sector deletion
temporary stop
-->Restart
(Sector being
deleted)
1-->0
During the sector
deletion temporary
stop (Sector not
being deleted)
DATA:7
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.5.2
Toggle Bit Flag (DQ6)
The toggle bit flag specifies whether the automatic algorithm is being executed or has
been terminated, using the toggle bit function, the same as the data polling flag. Table
23.5-4 shows the toggle bit flag status transition.
■ When the Write Operation or Chip/Sector Deletion Operation is Executed.
When the continuous read/access is executed during the automatic write algorithm or chip/sector deletion
algorithm execution, the flash memory outputs the toggle status, in which "1" and "0" are alternately output
for each read operation, irrespective of the specified address. If the continuous read/access is executed at
the end of the automatic write algorithm or chip/sector deletion algorithm, the flash memory stops the
toggle operation in bit6 and outputs the data of bit6 (DATA:6) in the specified read address.
■ When the Sector Deletion Temporary Stop is Executed.
When the read/access is executed while executing the sector deletion temporary stop, the flash memory
outputs "1" if the specified address belongs to the sector being deleted. The flash memory outputs the data
of bit6 (DATA:6) in the specified read address unless the specified address belongs to the sector being
deleted.
Reference:
When executing the write operation, the toggle bit executes the toggle operation for about 2 ms, then
terminates it without rewriting the data, if the sector to be written is write-protected.
When executing the deletion operation, the toggle bit executes the toggle operation for about 100
ms, then returns to the read/reset status without rewriting the data, if all the selected sectors are
protected from rewriting.
Toggle Bit Flag Status Transition
Table 23.5-4 Toggle Bit Flag Status Transition
- Status transition during normal operation
Operating Write operation
--> Completion
status
DQ6
Toggle
-->DATA:6
Sector deletion
-->Deletion
Chip/sector
Sector deletion temporary stop
deletion
wait-->Start
(Sector being
-->Completion
deleted)
Toggle-->Stop
Toggle
Toggle-->1
Sector deletion
temporary stop
-->Restart
(Sector being
deleted)
1-->Toggle
During the sector
deletion temporary
stop (Sector not
being deleted)
DATA:6
- Status transition during abnormal operation
Operating status
DQ6
Write operation
Toggle
Chip/sector deletion operation
Toggle
597
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.5.3
Time limit Exceeded Flag (DQ5)
The time limit exceeded flag indicates that the automatic algorithm execution time has
exceeded the time defined within the flash memory (i.e., internal pulse count). Table
23.5-5 shows the transition of the time limit exceeded flag status.
■ When the Write Operation or Chip/Sector Deletion Operation is Executed.
When the read/access is executed after starting the write or chip/sector deletion automatic algorithm, this
flag is set to "0" if the execution time is within the defined time (required for writing/deletion), or it outputs
"1" if this execution time exceeds the defined time. This is not related to the state in which the automatic
algorithm is being executed or has been terminated, so it can be determined whether the write/delete has
succeeded or failed. Thus, when this flag is set to "1", it indicates that the write operation has failed if the
automatic algorithm is being performed by the data polling function or toggle bit function.
For example, a fail occurs if an attempt is made to write "1" to the flash memory with "0" written. In this
case, the flash memory is locked and the automatic algorithm is not terminated. Therefore, no valid data is
set in data polling flag (DQ7). The toggle bit flag (DQ6) does not stop the toggle operation, so the
execution time exceeds the time limit. Then, the time limit exceeded flag (DQ5) outputs "1". This event
indicates that the flash memory has not been correctly used, but does not indicate that the flash memory is
not good. If this event occurs, the reset command should be executed.
Table 23.5-5 Transition of the Time Limit Exceeded Flag Status
- Status transition during normal operation
Operating
status
DQ5
Sector deletion
-->Deletion
Chip/sector
Sector deletion
Write operation
temporary stop
deletion
wait-->Start
--> Completion
(Sector being
-->Completion
deleted)
0-->1
0-->DATA:5
0
0
- Status transition during abnormal operation
Operating status
Write operation
DQ5
1
598
Chip/sector deletion operation
1
Sector deletion
temporary stop
-->Restart
(Sector being
deleted)
0
During the sector
deletion temporary
stop (Sector not
being deleted)
DATA:5
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.5.4
Sector Deletion Timer Flag (DQ3)
After starting the sector deletion command, the sector deletion timer flag indicates
whether it is "during the sector deletion waiting period". Table 23.5-6 shows the sector
deletion timer flag status transition.
■ When the Sector Deletion Operation is Executed.
When the read/access is executed after starting the sector deletion command, the flash memory outputs "0"
if this flag indicates "during the sector deletion waiting period" irrespective of the address specified by the
address signal from the sector having issued the command. However, the flash memory outputs "1" if this
flag exceeds the defined sector deletion waiting period.
When the deletion algorithm is being executed by the data polling function or toggle bit function, the
internally-controlled deletion operation is started if this flag is "1". The succeeding sector deletion code to
be written and other commands except the sector deletion temporary stop command are ignored until
deletion is terminated.
If this flag is "0", the flash memory accepts the additional sector deletion code to be written. To verify this
event, it is recommended that this flag status be checked before writing the succeeding sector deletion code.
If this flag is "1" when the second time the status is checked, the additional sector deletion code may not be
accepted.
■ When the Sector Deletion Operation is Executed.
When the read/access is executed while executing the sector deletion temporary stop, the flash memory
outputs "1" if the specified address belongs to the sector being deleted. However, unless the specified
address belongs to the sector being deleted, the flash memory outputs the data of bit3 (DATA:3) of the
specified read address.
Sector Deletion Timer Flag Status Transition
Table 23.5-6 Sector Deletion Timer Flag Status Transition
- Status transition during normal operation
Operating
status
DQ3
Sector deletion
-->Deletion
Chip/sector
Write operation
Sector deletion temporary stop
deletion
--> Completion
(Sector being
-->Completion wait-->Start
deleted)
1
0-->DATA:3
0-->1
1-->0
Sector deletion
temporary stop
-->Restart
(Sector being
deleted)
0-->1
During the sector
deletion temporary
stop (Sector not
being deleted)
DATA:3
- Status transition during abnormal operation
Operating status
DQ3
Write operation Chip/sector deletion operation
0
1
599
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6
Detailed Explanation on the Flash Memory Write/Delete
This section explains the procedures for issuing the command to start the automatic
algorithm, reading/resetting the flash memory, writing the data to the flash memory,
deleting the chip, deleting the sector, temporarily stopping the sector deletion, and
restarting the sector deletion.
■ Detailed Explanation on the Flash Memory Write/Delete
The read/reset, write, chip deletion, sector deletion, sector deletion temporary stop, or deletion start
operation can be performed by the automatic algorithm which can be started by setting the command
sequence (see "23.4 Method of Starting the Automatic Algorithm in Flash Memory") to each bus write
cycle. The write cycles to the respective buses must be executed continuously. The ending time of the
automatic algorithm can be notified by the data polling function and so on. After the normal end of the
automatic algorithm, the flash memory returns to the read/reset status.
23.6.1 Setting the Read/Reset Status
23.6.2 Writing the Data
23.6.3 Deleting the Data (Chip Deletion)
23.6.4 Deleting the Data (Sector Deletion)
23.6.5 Temporarily Stopping the Sector Deletion
23.6.6 Restarting the Sector Deletion
600
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6.1
Setting the Read/Reset Status
This section explains the procedure of issuing the read/reset command and setting the
flash memory to the read/reset status.
■ Setting the Read/Reset Status
When the flash memory is set to the read/reset status, the read/reset command can be executed by
continuously sending the read/reset command, listed in the command sequence table (see "23.4 Method of
Starting the Automatic Algorithm in Flash Memory"), to the target sector in the flash memory.
There are two types of read/reset command sequences, one is that the bus operation is executed once and
the other is that the bus operations are executed three times. However, these command sequences have no
essential difference.
The read/reset status is the initial status of the flash memory. When the power supply is turned on, or when
the command is normally terminated, the flash memory is always set to the read/reset status. The read/reset
status means the status of the flash memory that is waiting for another command to be input.
In the read/reset status, data can be read from the flash memory by executing a usual read/access command.
The data can be program-accessed from CPU same as the mask ROM. This command is not required for
usual data reading. This command should be mainly used for initializing the automatic algorithm if the
command has not been normally terminated for any reason.
601
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6.2
Writing the Data
This section explains the procedure of issuing the write command and writing the data
to the flash memory. Figure 23.6-1 shows an example of procedure of writing data to
the flash memory.
■ Writing the Data
The automatic algorithm for writing the data to the flash memory can be performed by continuously
sending the write command, listed in the command sequence table (see "23.4 Method of Starting the
Automatic Algorithm in Flash Memory"), to the target sector in the flash memory. When the data write
operation to the target address in the 4th cycle has been terminated, the automatic algorithm is started for
automatic writing.
■ How to Specify the Address
Only even addresses can be specified as the write address in the write data cycle. If an odd address is
specified, data cannot be correctly written. That is, it is necessary to write the data in units of words to
even addresses.
Data can be written to the flash memory, and any address sequence may be specified, even if data has been
written across the sector boundary. However, only one-word data can be written by executing the write
command once.
■ Notes on Writing the Data
By writing the data, data "0" cannot be returned to data "1". If data "1" is written to data "0", the data
polling algorithm (DQ7) or toggle operation (DQ6) is not terminated and the flash memory element is
determined to be bad. Then, the time limit exceeded flag (DQ5) error may be determined by the excess of
the write defined time, or data "1" may be apparently written but is not actually done. However, if data is
read from the flash memory in the read/reset status, data remains "0". Only the deletion operation enables
data "0" to be changed to data "1".
All commands are ignored while automatic writing is being performed. Note that the data at the address for
writing is not assured if the hardware is reset during automatic writing.
■ Procedure of Writing the Data to the Flash Memory
Figure 23.6-1 shows an example of procedure of writing the data to the flash memory. Using the hardware
sequence flag (see "23.5 Verifying Automatic Algorithm Execution Status"), the status of the automatic
algorithm within the flash memory can be determined. Here, the data polling flag (DQ7) is used for
verifying the end of writing.
The data reading for checking the flag is started from the last-written address. The data polling flag (DQ7)
is changed at the same time when the time limit exceeded flag (DQ5) is changed, so the data polling flag
(DQ7) must be rechecked even if the time limit exceeded flag (DQ5) is "1".
Similarly, the toggle bit flag (DQ6) stops the toggle operation at the same time when the time limit
exceeded flag (DQ5) is changed to "1", so the toggle bit flag (DQ6) must be rechecked.
602
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
Figure 23.6-1 Example of Procedure of Writing the Data to the Flash Memory
Start the write
FMCS:WE (bit5)
Flash memory write
enabled
Write command sequence
1.FxAAAA
XXAA
2.Fx5554
XX55
3.FxAAAA
XXA0
4.Write address
Write data
Next address
Internal address read
Data
Data polling (DQ7)
Data
0
Time limit (DQ5)
1
Internal address read
Data
Data polling (DQ7)
Data
Write error
Last address
FMCS:WE(bit5)
Flash memo ry write disabled
Verification using
the hardware sequence flag
Write completion
603
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6.3
Deleting the Data (Chip Deletion)
This section explains the procedure of issuing the chip deletion command and deleting
all the data in the flash memory.
■ Deleting the data (Chip deletion)
All the data can be deleted from the flash memory by continuously sending the chip deletion command,
listed in the command sequence table (see "23.4 Method of Starting the Automatic Algorithm in Flash
Memory"), to the target sector in the flash memory.
The chip deletion command is executed by executing the bus operation six times. When the 6th-cycle write
operation has been completed, the chip deletion operation is started. The user need not write the data to the
flash memory before chip deletion operation. During the automatic deletion algorithm execution, the flash
memory writes data "0" to all the cells and verifies them before they are automatically deleted.
604
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6.4
Deleting the Data (Sector Deletion)
This section explains the procedure of issuing the sector deletion command and
deleting any sector from the flash memory. This command enables each sector to be
deleted, and two or more sectors to be specified at the same time.
■ Deleting the data (Sector deletion)
Any sector can be deleted from the flash memory by continuously sending the sector deletion command,
listed in the command sequence table (see "23.4 Method of Starting the Automatic Algorithm in Flash
Memory"), to the target sector in the flash memory.
Method of Specifying a Sector
The sector deletion command is executed by executing the bus operation six times. The sector deletion
wait of 50 µs is started by writing the sector deletion code (30H) to any accessible even address in the target
sector in the 6th-cycle bus operation. To delete two or more sectors, the deletion code (30H) should be
written to the address in the target sector just after the above operation.
■ Notes on Specifying Two or More Sectors
The deletion operation is started after the last sector deletion code is written and the sector deletion wait
period of 50 µs is terminated. Thus, the next deletion sector address and deletion code (i.e. in the 6th cycle
of the command sequence) must be input each within 50 µs to delete two or more sectors simultaneously,
which may not be accepted later than 50 µs. It can be checked whether the succeeding sector deletion code
write operation is valid, using the sector deletion timer flag (DQ3). In this case, the address from which the
sector deletion timer flag (DQ3) is read must indicate the sector to be deleted.
■ Procedure of Deleting a Sector
Using the hardware sequence flag (see "23.5 Verifying Automatic Algorithm Execution Status"), the status
of the automatic algorithm within the flash memory can be determined. Figure 23.6-2 shows an example of
procedure of deleting the sector from the flash memory. Here, the toggle bit flag (DQ6) is used for
verifying the end of writing. Note that data to be used for checking the flag is read from the sector to be
deleted.
The toggle bit flag (DQ6) stops the toggle operation at the same time when the time limit exceeded flag
(DQ5) is changed to "1", so the toggle bit flag (DQ6) must be rechecked even if the time limit exceeded
flag (DQ5) is "1".
Similarly, the data polling flag (DQ7) is changed at the same time when the time limit exceeded flag (DQ5)
is changed, so the data polling flag (DQ7) must be rechecked.
605
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
Figure 23.6-2 Example of Procedure of Deleting the Sector from the Flash Memory
Start the deletion.
FMCS:WE(bit5)
Flash memory deletion enabled
Deletion command sequence
XXAA
1. FFAAAA
XX55
2. FF5554
XX80
3. FFAAAA
XXAA
4. FFAAAA
XX55
5. FF5554
Input the code to the sector to be
deleted. (30H)
Is there another sector
to be deleted?
Internal adress read 1
Internal adress read 2
Sector deletion
completion
Toggle (DQ6)
Data 1 = Data 2
Time limit (DQ5)
Internal adress read
Internal adress read
Toggle bit (DQ6)
Data 1 = Data 2
Delete error
Last sector
FMCS:WE(bit5)
Flash memory deletion disabled
Verification using
the hardware sequence flag
606
Deletion completion
Next sector
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6.5
Temporarily Stopping the Sector Deletion
This section explains the procedure of issuing the sector deletion temporary stop
command and temporarily stopping the deletion of a sector from the flash memory.
This command can read the data from the sector not being deleted.
■ Temporarily Stopping the Sector Deletion
The sector deletion from the flash memory can be temporarily stopped by sending the sector deletion
temporary stop command, listed in the command sequence table (see "23.4 Method of Starting the
Automatic Algorithm in Flash Memory"), to the target sector in the flash memory.
The sector deletion temporary stop command stops the sector deletion operation temporarily, and enables
the data reading from the sector not being deleted. In this case, only the read operation can be executed,
but the write operation cannot be done. This command is valid only during the sector deletion operation
including the deletion waiting time, but it is ignored during the chip deletion operation or the write
operation.
This command is executed by writing the deletion temporary stop code (B0H). In this case, the address
must indicate an address within the flash memory. During the deletion temporary stop operation, the
reissued deletion temporary stop command is ignored.
If the sector deletion temporary stop command is input during the sector deletion waiting period, the sector
deletion wait is immediately terminated to stop the deletion operation, and the flash memory enters the
deletion stop status. If the sector deletion temporary stop command is input during the sector deletion
operation after the sector deletion waiting period, the flash memory enters the deletion temporary stop
status after a lapse of up to 20 µs. The sector deletion temporary stop command must be executed 20 µs or
more after the sector deletion command or sector deletion restart command is issued.
607
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.6.6
Restarting the Sector Deletion
This section explains the procedure of issuing the sector deletion restart command and
restarting the operation of deleting a sector from the flash memory, which has been
temporarily stopped.
■ Restarting the Sector Deletion
The sector deletion operation which has been temporarily stopped can be restarted by sending the sector
deletion restart command, listed in the command sequence table (see "23.4 Method of Starting the
Automatic Algorithm in Flash Memory"), to the target sector in the flash memory.
The sector deletion restart command is used to restart the sector deletion operation when the flash memory
is in the sector deletion temporary stop status caused by the sector deletion temporary stop command. This
command is executed by writing the deletion restart code (30H). In this case, the address must indicate an
address within the flash memory area.
However, the sector deletion restart command issued during the sector deletion operation is ignored.
608
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.7
Flash Security Feature
The Flash Security Controller provides possibilities to protect the content of the flash
memory from being read from external pins.
■ Flash Security Feature
One predefined address of the flash memory is assigned to the Flash Security Controller (MB90F462,
MB90F462A: FF0001H; MB90F463A: FE0001H). If the protection code of "01H" is written in this address,
access to the flash memory is restricted. Once the flash memory is protected, preforming the chip erase
operation only can unlock the function otherwise read/write access to the flash memory from any external
pins is not generally possible.
This function is suitable for applications requiring security of self-containing program and data stored in
the flash memory. If the target application requires any part of the program to locate outside the
microcontroller, the Flash Security Controller can not offer the intended features. For this reason, the
External Vector Fetch mode should not be used when the protection code is set.
Programming of the flash microcontroller by standard parallel programmer may require unique set-up. For
example, with the programmer from Minato Electronics the device checking should be turned off. Writing
the protection code is generally recommended to take place at the end of the flash programming. This is to
avoid unnecessary protection during the programming.
In order to re-program the once protected flash memory, the chip erase operation should be preformed.
For further information, please contact Fujitsu.
609
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.8
Programming Example of 512K Bit Flash Memory
This section presents a programming example for the use of 512K bit flash memory.
■ Programming Example Using 512K Bit Flash Memory
NAME FLASHWE
TITLE FLASHWE
;--------------------------------------------------------------------------;512-KB FLASH Sample program for 512-KB FLASH
;
;1: Transfer the program from the flash memory (address: FFBC00H sector: SA2) to RAM (address: 000700H).
;2: Run the transferred program in RAM.
;3: Write the value of PDR1 to the flash memory (address: FF0000H sector: SA0).
;4: Read the written value (address: FF0000H sector: SA0), and output the value to PDR2.
;5: Erase the sector (SA0) to which the value was written.
;6: Output a confirmation that the data was erased.
; Requirements:
;
- Number of bytes transferred to RAM: 100 H (256 B)
;
- Determination that writing or erasing has ended
;
Determined via DQ5 (timing limit exceeded flag)
;
Determined via DQ6 (toggle bit flag)
;
Determined via RDY (FMCS)
;
- Error handling
;
Output Hi to P00 to P07.
;
Issue a reset command.
;--------------------------------------------------------------------------;
RESOUS
IOSEG
ABS=00
;"RESOUS" I/O segment definition
ORG
0000H
PDR0
RB
1
PDR1
RB
1
PDR2
RB
1
PDR3
RB
1
ORG
0010H
DDR0
RB
1
DDR1
RB
1
DDR2
RB
1
DDR3
RB
1
ORG
00A1H
CKSCR
RB
1
ORG
00AEH
FMCS
RB
1
ORG
006FH
ROMM
RB
1
RESOUS
ENDS
;
SSTA
SSEG
RW
0127H
STA_T
RW
1
SSTA
ENDS
;
DATA
DSEG
ABS=0FFH
;Flash command address
ORG
5554H
COMADR2 RW
1
ORG
0AAAAH
COMADR1 RW
1
610
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
DATA ENDS
;///////////////////////////////////////////////////////////////
;Main program (SA1)
;///////////////////////////////////////////////////////////////
CODE CSEG
START:
;//////////////////////////////////////////////////////
;Initialization
;//////////////////////////////////////////////////////
MOV
CKSCR,#0BAH
;Set a frequency multiplier of three.
MOV
RP,#0
MOV
A,#!STA_T
MOV
SSB,A
MOVW
A,#STA_T
MOVW
SP,A
MOV
ROMM,#00H
;Mirror OFF
MOV
PDR0,#00H
;For error check
MOV
DDR0,#0FFH
MOV
PDR1,#00H
;Data input port
MOV
DDR1,#00H
MOV
PDR2,#00H
;Data output port
MOV
DDR2,#0FFH
;////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
;The flash memory write/erase program (FFBC00H) is transferred to RAM (1500H address).
;////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
MOVW
A,#0700H
;Destination RAM area
MOVW
A,#0BC00H
;Source address (location of program)
MOVW
RW0,#100H
;Number of bytes of data transferred to RAM
MOVS
ADB,PCB
;Transfer 100H from FFBC00H to 000700H.
CALLP
000700H
;Jump to the address where the transferred program
;exists.
;/////////////////////////////////////////////////////
;Data output
;/////////////////////////////////////////////////////
OUT
MOV
A,#0FEH
MOV
ADB,A
MOVW
RW2,#0000H
MOVW
A,@RW2+00
MOV
PDR2,A
END
JMP
*
CODE
ENDS
;///////////////////////////////////////////////////////////////////
; Flash program write/erase program (SA2)
;///////////////////////////////////////////////////////////////////
RAMPRG CSEG
ABS=0FFH
ORG
0BC00H
;
////////////////////////////////////////////
;
Initialization
;
////////////////////////////////////////////
MOVW
RW0,#0500H
;RW0: Reserve RAM space for input area
00:0500 to
MOVW
RW2,#0000H
;RW2: Flash memory write address
FF:0000 to
MOV
A,#00H
;DTB modification
MOV
DTB,A
;Bank specification for @RW0
MOV
A,#0FFH
;ADB modification 1
MOV
ADB,A
;Bank specification for write mode specification
;address
611
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
MOV
MOV
PDR3,#00H
DDR3,#00H
;Switch initialization
;
WAIT1
BBC
PDR3:0,WAIT1
;Writing starts if PDR3:0 Hi.
;
;/////////////////////////////////////////////////
; Write (SA0)
;/////////////////////////////////////////////////
MOV
A,PDR1
MOVW
@RW0+00,A
;PDR1 data is stored in RAM.
MOV
FMCS,#20H
;Write mode setting
MOVW ADB:COMADR1,#00AAH
;Flash write command 1
MOVW ADB:COMADR2,#0055H
;Flash write command 2
MOVW ADB:COMADR1,#00A0H
;Flash write command 3
;
MOVW
A,@RW0+00
; Input data (RW0) is written to flash memory (RW2).
MOVW
@RW2+00,A
WRITE
; Wait time check
;
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
;
If the "time-limit-exceeded" check flag is set while toggling is on, branches to ERROR.
;
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOW
;Time limit exceeded
MOVW
A,@RW2+00
;AH
MOVW
A,@RW2+00
;AL
XORW
A
;XOR of AH and AL (1 when the values
are different.)
AND
A,#40H
;Checks whether the DQ6 toggle bit is
different.
BNZ
ERROR
;If it is different, branches to ERROR
;
///////////////////////////////////////////////
;
Write-end check (FMCS-RDY)
;
////////////////////////////////////////////////
NTOW
MOVW
A,FMCS
AND
A,#10H
;FMCS RDY bit (4 bit) is extracted.
BZ
WRITE
;Verifies that writing has ended.
MOV
FMCS,#00H
;Write mode is released.
;/////////////////////////////////////////////////////
; Write data output
;/////////////////////////////////////////////////////
MOVW
RW2,#0000H
;Write data output
MOVW
A,@RW2+00
MOV
PDR2,A
;
WAIT2
BBC
PDR3:1,WAIT2
;If PDR3:1 Hi, erasing of the sector starts.
;
;/////////////////////////////////////////////
; Erasing sectors (SA0)
;/////////////////////////////////////////////
MOVW
@RW2+00,#0000H
;Address initialization
MOV
FMCS,#20H
;Erase mode setting
MOVW
ADB:COMADR1,#00AAH
;Flash memory erase command 1
MOVW
ADB:COMADR2,#0055H
;Flash memory erase command 2
MOVW
ADB:COMADR1,#0080H
;Flash memory erase command 3
MOVW
ADB:COMADR1,#00AAH
;Flash memory erase command 4
MOVW
ADB:COMADR2,#0055H
;Flash memory erase command 5
612
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
MOVW
@RW2+00,#0030H
;Issuing the erase command to the sector to be erased. 6
; Wait-time check
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
When the "time-limit-exceeded" check flag is set and toggling is on, branches to ERROR.
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOE
;Time limit exceeded
MOVW
A,@RW2+00
;AH From DQ6 during writing
MOVW
A,@RW2+00
;AL Hi and Low are output alternately by each read.
XORW
A
;XOR of AH and AL (If the DQ6 value is toggled,
XOR is 1, indicating that writing is in progress.)
AND
A,#40H
;Checks whether the DQ6 toggle bit is Hi.
BNZ
ERROR
;If the bit is Hi, branches to ERROR
;
////////////////////////////////////////////////
;
Erase-end check (FMCS-RDY)
;
////////////////////////////////////////////////
NTOE
MOVW
A,FMCS
;
AND
A,#10H
;FMCS RDY bit (4 bit) is extracted.
BZ ELS
;Verifies that erasing of the sector has ended.
MOV
FMCS,#00H
;Flash memory erase mode is released.
RETP
;Returns to the main program.
;//////////////////////////////////////////////
; Error
;//////////////////////////////////////////////
ERROR
MOV
ADB:COMADR1,#0F0H
;Reset command (enabling data reading)
MOV
FMCS,#00H
;Flash command mode is released.
MOV
PDR0,#0FFH
;Confirmation of error processing.
RETP
;Returns to the main program.
RAMPRG ENDS
;/////////////////////////////////////////////
VECT
CSEG
ABS=0FFH
ORG
0FFDCH
DSL
START
DB
00H
VECT
ENDS
;
END START
ELS
;
;
;
613
CHAPTER 23 512K / 1024K BIT FLASH MEMORY
614
CHAPTER 24
EXAMPLE OF F2MC-16LX
MB90F462/F462A/F463A
CONNECTION FOR SERIAL
WRITING
This chapter describes examples of F2MC-16LX
MB90F462/F462A/F463A connections for serial writing.
24.1 Standard Configuration for Serial On-board Writing (Fujitsu Standard)
24.2 Example of Connection for Serial Writing (When Power Supplied by
User)
24.3 Example of Connection for Serial Writing (When Power Supplied
from Writer)
24.4 Example of Minimum Connection with Flash Microcontroller
Programmer (When Power Supplied by User)
24.5 Example of Minimum Connection with Flash Microcontroller
Programmer (When Power Supplied from Writer)
615
CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING
24.1
Standard Configuration for Serial On-board Writing
(Fujitsu Standard)
MB90F462/F462A/F463A supports serial on-board writing (Fujitsu standard) to flash
ROM. This describes the specifications for serial on-board writing.
■ Standard Configuration for Fujitsu Standard Serial On-board Writing
The AF200 flash microcontroller programmer of Yokogawa Digital Computer Co., Ltd. is used for
Fujitsu standard serial on-board writing.
Host interface cable (AZ201)
RS232C
AF200
flash
microcontroller
programmer
+
memory card
General-purpose common cable (AZ210)
Clock
synchronous
serial
MB90F462/F462A/F463A
user system
Operable in stand-alone mode
Note:
Contact Yokogawa Digital Computer Co., Ltd. for the functionality and operation of the AF200 flash
microcontroller programmer and information on the general-purpose common cable (AZ210) and
connectors.
Table 24.1-1 Pins used for Fujitsu Standard Serial On-board Writing
Pin
Function
Description
MD2, MD1, MD0
Mode pin
Used to enable write mode for the flash microcomputer programmer.
X0, X1
Oscillator pin
In write mode, since the operation clock is one times the CPU clock, the
oscillation clock frequency is the internal operation clock.
The resonator used for serial rewriting is therefore 1 MHz to 16 MHz.
P00, P01
Write program start pin
–
RSTX
Reset pin
–
SIN0
Serial data input pin
SOT0
Serial data output pin
SCK0
Serial clock input pin
C
C pin
Capacitance pin for power stabilization. Connect a ceramic capacitor
of about 0.1 µF to the outside.
VCC
Power supply pin
Write voltage (5 V ± 10%)
VSS
Ground pin
Used also as the ground pin for the flash microcontroller programmer.
616
UART0 is used in CLK synchronous mode.
CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING
Note:
When the P00, P01, SIN0, SOT0, SCK0 pins are also used by the user system, the control circuit shown below
is required. (The /TICS signal of the flash microcontroller programmer can separate the user circuit during
serial writing. See the connection example shown later.)
Figure 24.1-1 Control Circuit
AF200
write control pin
MB90F462/F462A/F463A
write control pin
10kΩ
AF200
/TICS pin
User
Refer to the following four serial writing examples in Section 24.2 to 24.5.
• Example of serial write connection when power supplied by user
• Example of serial write connection when power supplied from writer
• Example of minimum connection to flash microcontroller programmer when power supplied by user
• Example of minimum connection to flash microcontroller programmer when power supplied from
writer
Table 24.1-2 System Configuration of AF200 Flash Microcontroller Programmer
(Yokogawa Digital Computer Co., Ltd.)
Type
Function
AF200 ACP
Flash microcontroller programmer/100 V power supply adapter
AF200 AC2P
Flash microcontroller programmer/power supply adapter with overseas specification
AZ201
RS232C cable for PC/AT
AZ210
Standard target probe (a) Length: 1 m
FF001
Control module for Fujitsu F2MC-16LX flash microcontroller
FF001 P2
2 MB PC Card (Option)
FF001 P4
4 MB PC Card (Option)
For more information, contact the Sales Department, Equipment Business Division, Yokogawa Digital
Computer Co., Ltd. (Telephone: (81)-42-333-6224).
617
CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING
24.2
Example of Connection for Serial Writing (When Power
Supplied by User)
Figure 24.2-1 is an example of serial write connection when power is supplied by the
user.
MD2=1 and MD0=0 are input from TAUX3 and TMODE respectively in AF200 flash
microcontroller programmer. Serial write mode: MD2, MD1, MD0 = 110B
■ Example of Connection for Serial Writing (when Power Supplied by User)
Figure 24.2-1 Example of Connection for Serial Writing in MB90F462/F462A/F463A Internal Vector Mode
(when Power Supplied by User)
AF200 flash
microcontroller
programmer
User system
Connector
DX10-28S
MB90F462/F462A/F463A
(19)
TAUX3
MD2
MD1
TMODE
MD0
(12)
X0
1MHz to 16MHz
X1
(23)
TAUX
P00
(10)
/TICS
User
/TRES
(5)
P01
User
C
TTXD
TVcc
GND
SIN0
SOT0
SCK0
(13)
(27)
(6)
TRXD
TCK
(2)
(7,8,
14,15,
21,22,
1,28)
Vcc
User power
supply
Pin 14
Pins 3, 4, 9, 11, 16,
17, 18,20, 24, 25,
and 26 are open.
DX10-28S,right-angle type
Vss
Pin 1
DX10-28S
Pin 28
Pin 15
Connector (made by Hirose Electric) pin layout
618
CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING
• When the user system also uses pins SIN0, SOT0 and SCK0, the control circuit shown below is
necessary, just as it is for P00. (During serial writing, the user circuit can be disconnected by the flash
microcontroller programmer /TICS signal.)
• Before connecting the AF200, turn off the power supplied by the user.
AF200
write control pin
MB90F462/F462A/F463A
write control pin
10k
AF200
/TICS pin
User
619
CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING
24.3
Example of Connection for Serial Writing (When Power
Supplied from Writer)
Figure 24.3-1 is an example of serial write connection when power is supplied from the
writer.
MD2=1 and MD0 are input from TAUX3 and TMODE respectively in AF200 flash
microcontroller programmer. Serial write mode: MD2, MD1, MD0 = 110B
■ Example of Connection for Serial Writing (when Power Supplied from Writer)
Figure 24.3-1 Example of Connection for Serial Writing in MB90F462/F462A/F463A Internal Vector Mode
(when Power Supplied from Writer)
AF200 flash
microcontroller
programmer
User system
Connector
DX10-28S
MB90F462/F462A/F463A
(19)
TAUX3
MD2
MD1
TMODE
MD0
(12)
X0
1MHz to 16MHz
X1
(23)
TAUX
P00
(10)
/TICS
User
/TRES
(5)
P01
User
C
TTXD
TVcc
GND
SIN0
SOT0
SCK0
(13)
(27)
(6)
TRXD
TCK
(2)
(7,8,
14,15,
21,22,
1,28)
Vcc
User power
supply
Pin 14
Pins 3, 4, 9, 11, 16,
17, 18,20, 24, 25,
and 26 are open.
DX10-28S, right-angle type
620
Vss
Pin 1
DX10-28S
Pin 28
Pin 15
Connector (made by Hirose Electric) pin layout
CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING
• When the SIN0, SOT0 and SCK0 pins are also used by the user system, the control circuit shown below
is necessary, just as it is for P00. (During serial writing, the user circuit can be disconnected by the flash
microcontroller /TICS signal.)
• Before connecting the AF200, turn off the power supplied by the user.
• When supplying write power from the AF200, do not create a short with the power supplied by the user.
AF200
write control pin
MB90F462/F462A/F463A
write control pin
10k
AF200
/TICS pin
User
621
CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING
24.4
Example of Minimum Connection with Flash Microcontroller
Programmer (When Power Supplied by User)
Figure 24.4-1 is an example of the minimum connection with the flash microcontroller
programmer when power is supplied by the user.
Serial write mode: MD2, MD1, MD0 = 110B
■ Example of Minimum Connection with Flash Microcontroller Programmer
(when Power Supplied by User)
If the pins are set as shown in Figure 24.4-1 during writing to flash memory, MD2, MD1, MD0, P00 and
flash microcontroller programmer connection is unnecessary.
Figure 24.4-1 Example of Minimum Connection with Flash Microcomputer Programmer
(when Power Supplied by User)
AF200 flash
microcontroller
programmer
User system
Serial write 1
MB90F462/F462A/463A
MD2
Serial
rewriting
MD1
MD0
X0
1MHz to 16MHz
X1
Serial
write 0
P00
User circuit
Serial write 1
User circuit
P01
C
Connector
DX10-28S
(5)
RSTX
(13)
(6)
SIN0
SOT0
SCK0
(2)
Vcc
/TRES
TTXD
TRXD
TCK
TVcc
(27)
GND
(7,8,
14,15,
21,22,
1,28)
Pins 3, 4, 9, 10, 11,
12, 16, 17, 18, 19,
20, 23, 24, 25, and
26 are open.
DX10-28S, right-angle type
622
User power supply Vss
Pin 14
Pin 1
DX10-28S
Pin 15
Pin 28
Connector (made by Hirose Electric) pin layout
CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING
• When the user system also uses the SIN0, SOT0 and SCK0 pins the control circuit shown below is
necessary. (During serial writing, the user circuit can be disconnected by the flash microcontroller
programmer /TICS signal.)
• Before connecting the AF200, turn off the power supplied by the user.
AF200
write control pin
MB90F462/F462A/F463A
write control pin
10k
AF200
/TICS pin
User
623
CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING
24.5
Example of Minimum Connection with Flash Microcontroller
Programmer (When Power Supplied from Writer)
Figure 24.5-1 is an example of the minimum connection with the flash microcontroller
programmer when power is supplied from the writer.
■ Example of Minimum Connection with Flash Microcontroller Programmer
(when Power Supplied from Writer)
If the pins are set as shown in Figure 24.5-1 during writing to flash memory, MD2, MD1, MD0, P00 and
flash microcontroller programmer connection is unnecessary.
Figure 24.5-1 Example of Minimum Connection with Flash Microcontroller Programmer
(when Power Supplied from Writer)
AF200 flash
microcontroller
programmer
User system
MB90F462/F462A/F463A
Serial write1
MD2
MD1
Serial
write1
MD0
Serial write0
X0
1MHz to 16MHz
X1
P00
Serial
write0
User circuit
Serial write1
User
circuit
P01
C
Connector
DX10-28S
/TRES
TTXD
TRXD
TCK
TVcc
Vcc
TVPP1
GND
(5)
(13)
(27)
(6)
(2)
(3)
(16)
(7,8,
14,15,
21,22,
1,28)
Pins 4, 9, 10, 11, 12,
17, 18, 19, 20, 23, 24,
25, and 26 are open.
DX10-28S, right-angle type
624
RSTX
SIN0
SOT0
SCK0
User power
supply
Pin 14
Vcc
Vss
Pin 1
DX10-28S
Pin 28
Pin 15
Connector (made by Hirose Electric) pin layout
CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING
• When the user system also uses the SIN0, SOT0, SCK0 pins, the control circuit shown below is
necessary. (During serial writing, the user circuit can be disconnected by the flash microcontroller
programmer /TICS signal.)
• Before connecting the AF200, turn off the power supplied by the user.
• When write power is supplied from the AF200, do not create a short with the power supplied by user.
AF200
write control pin
MB90F462/F462A/F463A
write control pin
10k
AF200
/TICS pin
User
625
CHAPTER 24 EXAMPLE OF F2MC-16LX MB90F462/F462A/F463A CONNECTION FOR SERIAL WRITING
626
APPENDIX
The appendixes contain an I/O map and F2MC-16LX
instructions description.
APPENDIX A I/O MAP
APPENDIX B Instructions
627
APPENDIX
APPENDIX A
I/O MAP
Table A-1 lists the addresses assigned to the registers for peripheral functions in the
MB90460/465 series.
■ I/O Map
Table A-1 I/O Map (1/6)
Address
Abbreviation
Register
000000H
PDR0
Port 0 data register
R/W
R/W
Port 0
XXXXXXXXB
000001H
PDR1
Port 1 data register
R/W
R/W
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 data register
R/W
R/W
Port 2
XXXXXXXXB
000003H
PDR3
Port 3 data register
R/W
R/W
Port 3
XXXXXXXXB
000004H
PDR4
Port 4 data register
R/W
R/W
Port 4
Initial value
-XXXXXXXB
000005H
PDR5
Port 5 data register
R/W
R/W
Port 5
XXXXXXXXB
000006H
PDR6
Port 6 data register
R/W
R/W
Port 6
----XXXXB
000007H
Prohibited area
000008H
PWCSL0
PWC control status register CH.0 (lower byte)
R/W
R/W
000009H
PWCSH0
PWC control status register CH.0 (upper byte)
R/W
R/W
00000AH
00000BH
00000CH
PWC0
PWC data buffer register CH.0
DIV0
Divide ratio control register CH.0
00000DH
to 0FH
-
R/W
R/W
R/W
00000000B
00000000B
PWC timer
(CH.0)*
XXXXXXXXB
XXXXXXXXB
------00B
Prohibited area
000010H
DDR0
Port 0 direction register
R/W
R/W
Port 0
00000000B
000011H
DDR1
Port 1 direction register
R/W
R/W
Port 1
00000000B
000012H
DDR2
Port 2 direction register
R/W
R/W
Port 2
00000000B
000013H
DDR3
Port 3 direction register
R/W
R/W
Port 3
00000000B
000014H
DDR4
Port 4 direction register
R/W
R/W
Port 4
-0000000B
Port 5
00000000B
000015H
DDR5
Port 5 direction register
R/W
R/W
000016H
DDR6
Port 6 direction register
R/W
R/W
Port 6
----0000B
000017H
ADER
Analog input enable register
R/W
R/W
Port 5, A/D
11111111B
R/W
Communication
prescaler 0
0---0000B
000018H
000019H
Prohibited area
CDCR0
Clock division control register 0
00001AH
Clock division control register 1
R/W
R/W
Communication
prescaler 1
0---0000B
RDR0
Port 0 pull-up resistor setting register
R/W
R/W
Port 0
00000000B
RDR1
Port 1 pull-up resistor setting register
R/W
R/W
Port 1
00000000B
00001BH
CDCR1
00001CH
00001DH
000020H
R/W
Prohibited area
00001EH
to 1FH
628
Byte access Word access Resource name
Prohibited area
SMR0
Serial mode register 0
R/W
R/W
Serial control register 0
R/W
R/W
000021H
SCR0
000022H
SIDR0 /
SODR0
Input data register 0 /
Output data register 0
R/W
R/W
000023H
SSR0
Serial status register 0
R/W
R/W
00000000B
00000100B
UART0
XXXXXXXXB
00001000B
APPENDIX A I/O MAP
Table A-1 I/O Map (2/6)
Address
Abbreviation
000024H
SMR1
000025H
SCR1
000026H
SIDR1 /
SODR1
000027H
SSR1
Register
Byte access Word access Resource name
Serial mode register 1
R/W
Initial value
R/W
00000000B
00000100B
Serial control register 1
R/W
R/W
Input data register 1 /
Output data register 1
R/W
R/W
Status register 1
R/W
R/W
UART1
XXXXXXXXB
00001000B
000028H
PWCSL1
PWC control status register CH.1 (lower byte)
R/W
R/W
00000000B
000029H
PWCSH1
PWC control status register CH.1 (upper byte)
R/W
R/W
00000000BB
-
R/W
R/W
R/W
00002AH
PWC timer
(CH.1)
XXXXXXXXB
PWC1
PWC data buffer register CH.1
DIV1
Divide ratio control register CH.1
000030H
ENIR
Interrupt / DTP enable register
R/W
R/W
00000000B
000031H
EIRR
Interrupt / DTP cause register
R/W
R/W
XXXXXXXXB
000032H
ELVRL
R/W
R/W
000033H
ELVRH
R/W
R/W
00000000B
000034H
ADCS0
A/D control status register (lower byte)
R/W
R/W
00000000B
000035H
ADCS1
A/D control status register (upper byte)
R/W
R/W
000036H
ADCR0
R
R
000037H
ADCR1
R/W
R/W
00002BH
00002CH
00002DH to 2FH
000038H
000039H
00003AH
00003BH
00003CH
00003DH
00003EH
00003FH
000040H
XXXXXXXXB
------00B
Prohibited area
Request level setting register
A/D data register
DTP/external
interrupt
8/10-bit A/D
converter
00000000B
00000000B
XXXXXXXXB
00000-XXB
11111111B
PDCR0
PPG0 down counter register
-
R
PCSR0
PPG0 period setting register
-
W
PDUT0
PPG0 duty setting register
-
W
PCNTL0
PPG0 control status register (lower byte)
R/W
R/W
--000000B
R/W
R/W
00000000B
PCNTH0
PPG0 control status register (upper byte)
11111111B
XXXXXXXXB
16-bit PPG timer XXXXXXXXB
(CH.0)
XXXXXXXXB
XXXXXXXXB
11111111B
PDCR1
PPG1 down counter register
-
R
PCSR1
PPG1 period setting register
-
W
PDUT1
PPG1 duty setting register
-
W
000046H
PCNTL1
PPG1 control status register (lower byte)
R/W
R/W
--000000B
000047H
PCNTH1
PPG1 control status register (lower byte)
R/W
R/W
00000000B
000041H
000042H
000043H
000044H
000045H
000048H
11111111B
XXXXXXXXB
16-bit PPG timer XXXXXXXXB
(CH.1)*
XXXXXXXXB
XXXXXXXXB
11111111B
PDCR2
PPG2 down counter register
-
R
PCSR2
PPG2 period setting register
-
W
PDUT2
PPG2 duty setting register
-
W
00004EH
PCNTL2
PPG2 control status register (lower byte)
R/W
R/W
--000000B
00004FH
PCNTH2
PPG2 control status register (upper byte)
R/W
R/W
00000000B
000049H
00004AH
00004BH
00004CH
00004DH
11111111B
XXXXXXXXB
16-bit PPG timer XXXXXXXXB
(CH.2)
XXXXXXXXB
XXXXXXXXB
629
APPENDIX
Table A-1 I/O Map (3/6)
Address
000050H
Abbreviation
Register
Initial value
XXXXXXXXB
TMRR0
16-bit timer register 0
-
R/W
TMRR1
16-bit timer register 1
-
R/W
TMRR2
16-bit timer register 2
-
R/W
000056H
DTCR0
16-bit timer control register 0
R/W
R/W
00000000B
000057H
DTCR1
16-bit timer control register 1
R/W
R/W
00000000B
000058H
DTCR2
16-bit timer control register 2
R/W
R/W
00000000B
R/W
R/W
00000000B
-
R/W
-
R/W
R/W
R/W
000051H
000052H
000053H
000054H
000055H
000059H
00005AH
00005BH
00005CH
00005DH
SIGCR
TCDT
TCCSL
00005FH
TCCSH
000061H
000062H
000063H
000064H
000065H
000066H
000067H
Waveform control register
CPCLRB / Compare clear buffer register / Compare clear
CPCLR register
00005EH
000060H
IPCP0
IPCP1
IPCP2
IPCP3
Timer data register
Timer control status register
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Waveform
generator
XXXXXXXXB
XXXXXXXXB
11111111B
11111111B
16-bit
free-run timer
00000000B
00000000B
00000000B
R/W
R/W
-0000000B
Input capture data register CH.0
-
R
XXXXXXXXB
Input capture data register CH.0
-
R
XXXXXXXXB
Input capture data register CH.1
-
R
XXXXXXXXB
Input capture data register CH.1
-
R
XXXXXXXXB
R
XXXXXXXXB
Input capture data register CH.2
-
Input capture data register CH.2
-
R
Input capture data register CH.3
-
R
Input capture data register CH.3
-
R
XXXXXXXXB
16-bit input
capture
(CH.0 to CH.3)
XXXXXXXXB
XXXXXXXXB
000068H
PICSL01
PPG output control / input capture control status
register 01 (lower byte)
R/W
R/W
00000000B
000069H
PICSH01
PPG output control / input capture control status
register 01 (upper byte)
R/W
R/W
00000000B
00006AH
ICSL23
Input capture control status register 23 (lower
byte)
R/W
R/W
00000000B
00006BH
ICSH23
Input capture control status register 23 (upper
byte)
R
R
------00B
00006CHto 6EH
00006FH
630
Byte access Word access Resource name
Prohibited area
ROMM
ROM mirroring function selection register
W
W
ROM mirroring
function
-------1B
APPENDIX A I/O MAP
Table A-1 I/O Map (4/6)
Address
000070H
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
Abbreviation
Register
Byte access Word access Resource name
OCCPB0 / Output compare buffer register / Output compare
OCCP0 register 0
-
R/W
OCCPB1 / Output compare buffer register / Output compare
OCCP1 register 1
-
R/W
OCCPB2 / Output compare buffer register / Output compare
OCCP2 register 2
-
R/W
OCCPB3 / Output compare buffer register / Output compare
OCCP3 register 3
-
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
OCCPB4 / Output compare buffer register / Output compare
OCCP4 register 4
-
R/W
OCCPB5 / Output compare buffer register / Output compare
OCCP5 register 5
-
R/W
Initial value
XXXXXXXXB
XXXXXXXXB
Output compare XXXXXXXXB
(CH.0 to CH.5) XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00007CH
OCS0
Compare control register 0
R/W
R/W
00007DH
OCS1
Compare control register 1
R/W
R/W
-0000000B
00007EH
OCS2
Compare control register 2
R/W
R/W
00000000B
00007FH
OCS3
Compare control register 3
R/W
R/W
-0000000B
000080H
OCS4
Compare control register 4
R/W
R/W
00000000B
000081H
OCS5
Compare control register 5
R/W
R/W
-0000000B
00000000B
000082H
TMCSRL0 Timer control status register CH.0 (lower byte)
R/W
R/W
000083H
TMCSRH0 Timer control status register CH.0 (upper byte)
R/W
R/W
-
R/W
000084H
000085H
TMR0 /
TMRD0
16-bit timer register /
16-bit reload register CH.0
000086H
TMCSRL1 Timer control status register CH.1 (lower byte)
R/W
R/W
000087H
TMCSRH1 Timer control status register CH.1 (upper byte)
R/W
R/W
000088H
00000000B
----0000B
16-bit reload timer
(CH.0)
XXXXXXXXB
XXXXXXXXB
00000000B
----0000B
16-bit reload timer
(CH.1)
XXXXXXXXB
TMR1 /
TMRD1
16-bit timer register /
16-bit reload register CH.1
-
R/W
00008AH
OPCLR
Output control lower register
R/W
R/W
00000000B
00008BH
OPCUR
Output control upper register
R/W
R/W
00000000B
00008CH
IPCLR
Input control lower register
R/W
R/W
00008DH
IPCUR
Input control upper register
R/W
R/W
00008EH
TCSR
Timer control status register
R/W
R/W
00000000B
00008FH
NCCR
Noise cancellation control register
R/W
R/W
00000000B
000089H
000090H to 9DH
00009EH
XXXXXXXXB
Waveform
sequencer*
00000000B
00000000B
Prohibited area
PACSR
Program address detect control status register
R/W
R/W
Address match
detection
----0000B
00009FH
DIRR
Delayed interrupt cause / clear register
R/W
R/W
Delayed interrupt
-------0B
0000A0H
LPMCR
Low-power consumption mode register
R/W
R/W
00011000B
0000A1H
CKSCR
Clock selection register
R/W
R/W
Low-power
consumption
control register
11111100B
0000A2H
to A7H
Prohibited area
0000A8H
WDTC
Watchdog control register
R/W
R/W
Watchdog timer
X-XXX111B
0000A9H
TBTC
Time-base timer control register
R/W
R/W
Time-base timer
1--00100B
R/W
Flash memory
interface circuit
00010000B
0000AAH
to ADH
0000AEH
0000AFH
Prohibited area
FMCS
Flash memory control status register
R/W
Prohibited area
631
APPENDIX
Table A-1 I/O Map (5/6)
Address
Abbreviation
0000B0H
ICR00
Interrupt control register 00
R/W
R/W
00000111B
0000B1H
ICR01
Interrupt control register 01
R/W
R/W
00000111B
0000B2H
ICR02
Interrupt control register 02
R/W
R/W
00000111B
0000B3H
ICR03
Interrupt control register 03
R/W
R/W
00000111B
0000B4H
ICR04
Interrupt control register 04
R/W
R/W
00000111B
0000B5H
ICR05
Interrupt control register 05
R/W
R/W
00000111B
0000B6H
ICR06
Interrupt control register 06
R/W
R/W
00000111B
0000B7H
ICR07
Interrupt control register 07
R/W
R/W
0000B8H
ICR08
Interrupt control register 08
R/W
R/W
0000B9H
ICR09
Interrupt control register 09
R/W
R/W
00000111B
0000BAH
ICR10
Interrupt control register 10
R/W
R/W
00000111B
0000BBH
ICR11
Interrupt control register 11
R/W
R/W
00000111B
0000BCH
ICR12
Interrupt control register 12
R/W
R/W
00000111B
0000BDH
ICR13
Interrupt control register 13
R/W
R/W
00000111B
0000BEH
ICR14
Interrupt control register 14
R/W
R/W
00000111B
0000BFH
ICR15
Interrupt control register 15
R/W
R/W
00000111B
0000C0H to FFH
632
Register
Byte access Word access Resource name
Interrupt
controller
Initial value
00000111B
00000111B
External area
001FF0H
PADRL0
Program address detection register 0 (lower byte)
R/W
R/W
XXXXXXXXB
001FF1H
PADRM0
Program address detection register 1 (middle byte)
R/W
R/W
XXXXXXXXB
001FF2H
PADRH0
Program address detection register 2 (upper byte)
R/W
R/W
001FF3H
PADRL1
Program address detection register 3 (lower byte)
R/W
R/W
001FF4H
PADRM1
Program address detection register 4 (middle byte)
R/W
R/W
XXXXXXXXB
001FF5H
PADRH1
Program address detection register 5 (upper byte)
R/W
R/W
XXXXXXXXB
Address match
detection
XXXXXXXXB
XXXXXXXXB
APPENDIX A I/O MAP
Table A-1 I/O Map (6/6)
Address
003FE0H
003FE1H
003FE2H
003FE3H
003FE4H
003FE5H
003FE6H
003FE7H
003F78H
003FE9H
003FEAH
003FEBH
003FECH
003FEDH
003FEEH
003FEFH
003FF0H
003FF1H
003FF2H
003FF3H
003FF4H
003FF5H
003FF6H
003FF7H
003FF8H
003FF9H
003FFAH
003FFBH
003FFCH
003FFDH
003FFEHto 003FFFH
Abbreviation
OPDBR0
OPDBR1
OPDBR2
OPDBR3
OPDBR4
OPDBR5
OPEBR6
OPEBR7
OPEBR8
OPEBR9
OPEBRA
OPEBRB
OPDR
CPCR
TMBR
Register
Output data buffer register 0
Byte access Word access Resource name
-
Initial value
R/W
00000000B
R/W
00000000B
Output data buffer register 0
-
Output data buffer register 1
-
R/W
00000000B
Output data buffer register 1
-
R/W
00000000B
Output data buffer register 2
-
R/W
00000000B
Output data buffer register 2
-
R/W
00000000B
Output data buffer register 3
-
R/W
00000000B
Output data buffer register 3
-
R/W
00000000B
Output data buffer register 4
-
R/W
00000000B
R/W
00000000B
Output data buffer register 4
-
Output data buffer register 5
-
R/W
00000000B
Output data buffer register 5
-
R/W
00000000B
Output data buffer register 6
-
R/W
00000000B
Output data buffer register 6
-
R/W
00000000B
Output data buffer register 7
-
R/W
00000000B
Output data buffer register 7
-
R/W
Output data buffer register 8
-
R/W
00000000B
Output data buffer register 8
-
R/W
00000000B
Output data buffer register 9
-
R/W
00000000B
Output data buffer register 9
-
R/W
00000000B
Output data buffer register A
-
R/W
00000000B
Waveform
sequencer*
00000000B
Output data buffer register A
-
R/W
00000000B
Output data buffer register B
-
R/W
00000000B
Output data buffer register B
-
R/W
00000000B
Output data register
-
R
XXXXXXXXB
Output data register
-
R
0000XXXXB
Compare clear register
-
R/W
XXXXXXXXB
Compare clear register
-
R/W
XXXXXXXXB
Timer buffer register
-
R
00000000B
-
R
00000000B
Timer buffer register
Prohibited area
633
APPENDIX
● Meaning of abbreviations used for reading and writing
R/W:Read and write enabled
R:Read-only
W:Write-only
● Explanation of initial values
0:The bit is initialized to 0.
1:The bit is initialized to 1.
X:The initial value of the bit is undefined.
-:The bit is not used. Its initial value is undefined.
● Instruction using IO addressing e.g. MOV A, io, is not supported for registers area 003FE0H to
003FFFH.
*: These registers are not present in MB90465 series.
634
APPENDIX B Instructions
APPENDIX B Instructions
APPENDIX B describes the instructions used by the F2MC-16LX.
B.1 Instruction Types
B.2 Addressing
B.3 Direct Addressing
B.4 Indirect Addressing
B.5 Execution Cycle Count
B.6 Effective address field
B.7 How to Read the Instruction List
B.8 F2MC-16LX Instruction List
B.9 Instruction Map
Code: CM44-10120-3EB
635
APPENDIX
B.1
Instruction Types
The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an
effective address field of each instruction or using the instruction code itself.
■ Instruction Types
The F2MC-16LX supports the following 351 types of instructions:
636
•
41 transfer instructions (byte)
•
38 transfer instructions (word or long word)
•
42 addition/subtraction instructions (byte, word, or long word)
•
12 increment/decrement instructions (byte, word, or long word)
•
11 comparison instructions (byte, word, or long word)
•
11 unsigned multiplication/division instructions (word or long word)
•
11 signed multiplication/division instructions (word or long word)
•
39 logic instructions (byte or word)
•
6 logic instructions (long word)
•
6 sign inversion instructions (byte or word)
•
1 normalization instruction (long word)
•
18 shift instructions (byte, word, or long word)
•
50 branch instructions
•
6 accumulator operation instructions (byte or word)
•
28 other control instructions (byte, word, or long word)
•
21 bit operation instructions
•
10 string instructions
APPENDIX B Instructions
B.2
Addressing
With the F2MC-16LX, the address format is determined by the instruction effective
address field or the instruction code itself (implied). When the address format is
determined by the instruction code itself, specify an address in accordance with the
instruction code used. Some instructions permit the user to select several types of
addressing.
■ Addressing
The F2MC-16LX supports the following 23 types of addressing:
•
Immediate (#imm)
•
Register direct
•
Direct branch address (addr16)
•
Physical direct branch address (addr24)
•
I/O direct (io)
•
Abbreviated direct address (dir)
•
Direct address (addr16)
•
I/O direct bit address (io:bp)
•
Abbreviated direct bit address (dir:bp)
•
Direct bit address (addr16:bp)
•
Vector address (#vct)
•
Register indirect (@RWj j = 0 to 3)
•
Register indirect with post increment (@RWj+ j = 0 to 3)
•
Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
•
Long register indirect with displacement (@RLi + disp8 i = 0 to 3)
•
Program counter indirect with displacement (@PC + disp16)
•
Register indirect with base index (@RW0 + RW7, @RW1 + RW7)
•
Program counter relative branch address (rel)
•
Register list (rlst)
•
Accumulator indirect (@A)
•
Accumulator indirect branch address (@A)
•
Indirectly-specified branch address (@ear)
•
Indirectly-specified branch address (@eam)
637
APPENDIX
■ Effective Address Field
Table B.2-1 lists the address formats specified by the effective address field.
Table B.2-1 Effective Address Field
Code
Representation
00
R0
RW0
RL0
01
R1
RW1
(RL0)
02
R2
RW2
RL1
03
R3
RW3
(RL1)
04
R4
RW4
RL2
05
R5
RW5
(RL2)
06
R6
RW6
RL3
07
R7
RW7
(RL3)
08
@RW0
09
@RW1
Address format
Default bank
Register direct: Individual parts correspond to the
byte, word, and long word types in order from the
left.
None
DTB
DTB
Register indirect
0A
@RW2
ADB
0B
@RW3
SPB
0C
@RW0+
DTB
0D
@RW1+
DTB
Register indirect with post increment
0E
@RW2+
ADB
0F
@RW3+
SPB
10
@RW0+disp8
DTB
11
@RW1+disp8
DTB
Register indirect with 8-bit displacement
12
@RW2+disp8
ADB
13
@RW3+disp8
SPB
14
@RW4+disp8
DTB
15
@RW5+disp8
DTB
Register indirect with 8-bit displacement
16
@RW6+disp8
ADB
17
@RW7+disp8
SPB
18
@RW0+disp16
DTB
19
@RW1+disp16
DTB
Register indirect with 16-bit displacement
638
1A
@RW2+disp16
ADB
1B
@RW3+disp16
SPB
1C
@RW0+RW7
Register indirect with index
DTB
1D
@RW1+RW7
Register indirect with index
DTB
1E
@PC+disp16
PC indirect with 16-bit displacement
PCB
1F
addr16
Direct address
DTB
APPENDIX B Instructions
B.3
Direct Addressing
An operand value, register, or address is specified explicitly in direct addressing mode.
■ Direct Addressing
● Immediate addressing (#imm)
Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32).
Figure B.3-1 Example of Immediate Addressing (#imm)
MOVW A, #01212H (This instruction stores the operand value in A.)
Before execution
A 2233
4455
After execution
A 4455
1 2 1 2 (Some instructions transfer AL to AH.)
● Register direct addressing
Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.32 shows an example of register direct addressing.
Table B.3-1 Direct Addressing Registers
General-purpose register
Special-purpose register
Byte
R0, R1, R2, R3, R4, R5, R6, R7
Word
RW0, RW1, RW2, RW3, RW4, RW5, RW6,
RW7
Long word
RL0, RL1, RL2, RL3
Accumulator
A, AL
Pointer
SP *
Bank
PCB, DTB, USB, SSB, ADB
Page
DPR
Control
PS, CCR, RP, ILM
*: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on
the value of the S flag bit in the condition code register (CCR). For branch instructions, the program
counter (PC) is not specified in an instruction operand but is specified implicitly.
639
APPENDIX
Figure B.3-2 Example of Register Direct Addressing
MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.)
Before execution
A 0716
2534
Memory space
R0
After execution
A 0716
2564
??
Memory space
R0
34
● Direct branch addressing (addr16)
Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which
indicates the branch destination in the logical address space. Direct branch addressing is used for an
unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are
specified by the program counter bank register (PCB).
Figure B.3-3 Example of Direct Branch Addressing (addr16)
JMP 3B20H (This instruction causes an unconditional branch by direct branch
addressing in a bank.)
Before execution
After execution
640
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
62
4F3C21H
20
4F3C22H
3B
JMP 3B20H
APPENDIX B Instructions
● Physical direct branch addressing (addr24)
Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical
direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
Figure B.3-4 Example of Direct Branch Addressing (addr24)
JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit
addressing.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 3 3
Memory space
333B20H
Next instruction
4F3C20H
63
4F3C21H
20
4F3C22H
3B
4F3C23H
33
JMPP 333B20H
● I/O direct addressing (io)
Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the
physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB)
and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an
instruction using I/O direct addressing.
Figure B.3-5 Example of I/O Direct Addressing (io)
MOVW A, i : 0C0H (This instruction reads data by I/O direct addressing and stores it
in A.)
Before execution
After execution
A 0716
2534
Memory space
0000C0H
EE
0000C1H
FF
A 2534 FFEE
641
APPENDIX
● Abbreviated direct addressing (dir)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB).
Figure B.3-6 Example of Abbreviated Direct Addressing (dir)
MOV S : 20H, A (This instruction writes the contents of the eight low-order bits of A in
abbreviated direct addressing mode.)
Before execution
A 4455
DPR 6 6
After execution
A 4455
DPR 6 6
1212
DTB 7 7
Memory space
776620H
1212
DTB 7 7
??
Memory space
776620H
12
● Direct addressing (addr16)
Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are
specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for
this mode of addressing.
Figure B.3-7 Example of Direct Addressing (addr16)
MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.)
Before execution
After execution
642
A 2020
A AABB
AABB
0123
DTB 5 5
DTB 5 5
Memory space
553B21H
01
553B20H
23
APPENDIX B Instructions
● I/O direct bit addressing (io:bp)
Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp",
where the larger number indicates the most significant bit (MSB) and the lower number indicates the least
significant bit (LSB).
Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp)
SETB i : 0C1H : 0 (This instruction sets bits by I/O direct bit addressing.)
Memory space
Before execution
0000C1H
00
Memory space
After execution
0000C1H
01
● Abbreviated direct bit addressing (dir:bp)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp)
SETB S : 10H : 0 (This instruction sets bits by abbreviated direct bit addressing.)
Memory space
Before execution
DTB 5 5
DPR 6 6
556610H
00
Memory space
After execution
DTB 5 5
DPR 6 6
556610H
01
● Direct bit addressing (addr16:bp)
Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-10 Example of Direct Bit Addressing (addr16:bp)
SETB 2222H : 0 (This instruction sets bits by direct bit addressing.)
Memory space
Before execution
DTB 5 5
552222H
00
Memory space
After execution
DTB 5 5
552222H
01
643
APPENDIX
● Vector Addressing (#vct)
Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector
numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Figure B.3-11 Example of Vector Addressing (#vct)
CALLV #15 (This instruction causes a branch to the address indicated by the interrupt
vector specified in an operand.)
Before execution
PC 0 0 0 0
Memory space
PCB F F
After execution
FFC000H
EF
FFFFE0H
00
FFFFE1H
D0
CALLV #15
PC D 0 0 0
PCB F F
Table B.3-2 CALLV Vector List
Instruction
Vector address L
Vector address H
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
Note: A PCB register value is set in XX.
Note:
When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of
INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2 ).
644
APPENDIX B Instructions
B.4
Indirect Addressing
In indirect addressing mode, an address is specified indirectly by the address data of
an operand.
■ Indirect Addressing
● Register indirect addressing (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to
23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register
(SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when
RW2 is used.
Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)
MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores
it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
● Register indirect addressing with post increment (@RWj+ j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After operand
operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word).
Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system
stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank
register (ADB) when RW2 is used.
If the post increment results in the address of the register that specifies the increment, the incremented
value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to
writing by an instruction and, therefore, the register that would be incremented becomes write data.
645
APPENDIX
Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)
MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post
increment and stores it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 1 1
DTB 7 8
● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
Memory is accessed using the address obtained by adding an offset to the contents of general-purpose
register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric
values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or
RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is
used, or additional data bank register (ADB) when RW2 or RW6 is used.
Figure B.4-3 Example of Register Indirect Addressing with Offset
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+10H)
RW1 D 3 0 F
After execution
A 2534 FFEE
RW1 D 3 0 F
646
DTB 7 8
DTB 7 8
Memory space
78D31FH
EE
78D320H
FF
APPENDIX B Instructions
● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+25H)
RL2 F 3 8 2
After execution
4B02
Memory space
824B27H
EE
824B28H
FF
A 2534 FFEE
RL2 F 3 8 2
4B02
● Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the
operand address of each of the following instructions is not deemed to be (next instruction address +
disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect
addressing with an offset and stores it in A.)
Before execution
A 0716
2534
Memory space
PCB C 5 PC 4 5 5 6
After execution
A 2534
FFEE
PCB C 5 PC 4 5 5 A
+4
C54556H
73
C54557H
9E
C54558H
20
C54559H
00
MOVW
A, @PC+20H
C5455AH
.
.
.
+20H
C5457AH
EE
C5457BH
FF
647
APPENDIX
● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with
a base index and stores it in A.)
Before execution
A 0716
RW1 D 3 0 F
WR7 0 1 0 1
After execution
A 2534
RW1 D 3 0 F
WR7 0 1 0 1
648
2534
+
DTB 7 8
FFEE
DTB 7 8
Memory space
78D410H
EE
78D411H
FF
APPENDIX B Instructions
● Program counter relative branch addressing (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the program
counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is
not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte
bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to
23 are indicated by the program counter bank register (PCB).
Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel)
BRA 10H (This instruction causes an unconditional relative branch.)
Before execution
After execution
PC 3 C 2 0
PC 3 C 3 2
PCB 4 F
PCB 4 F
Memory space
4F3C32H
Next instruction
4F3C21H
10
4F3C20H
60
BRA 10H
● Register list (rlst)
Specify a register to be pushed onto or popped from a stack.
Figure B.4-8 Configuration of the Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is 1 and deselected when the bit is 0.
649
APPENDIX
Figure B.4-9 Example of Register List (rlist)
POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to
multiple word registers indicated by the register list.)
SP
34FA
SP
34FE
RW0
×× ××
RW0
02 01
RW1
×× ××
RW1
×× ××
RW2
×× ××
RW2
×× ××
RW3
×× ××
RW3
×× ××
RW4
×× ××
RW4
04 03
RW5
×× ××
RW5
×× ××
RW6
×× ××
RW6
×× ××
RW7
×× ××
RW7
×× ××
Memory space
SP
Memory space
01
34FAH
01
34FAH
02
34FBH
02
34FBH
03
34FCH
03
34FCH
04
34FDH
04
34FDH
34FEH
SP
Before execution
34FEH
After execution
● Accumulator indirect addressing (@A)
Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the
accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB).
Figure B.4-10 Example of Accumulator Indirect Addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
A
0716
2534
DTB B B
After execution
A
0716
DTB B B
650
FFEE
Memory space
BB2534H
EE
BB2535H
FF
APPENDIX B Instructions
● Accumulator indirect branch addressing (@A)
The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the
accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are
specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however,
address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for
unconditional branch instructions.
Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A)
JMP @A (This instruction causes an unconditional branch by accumulator indirect
branch addressing.)
Before execution
PC 3 C 2 0
A 6677
After execution
PC 3 B 2 0
A 6677
PCB 4 F
3B20
Memory space
4F3B20H
Next instruction
4F3C20H
61
JMP @A
PCB 4 F
3B20
● Indirect specification branch addressing (@ear)
The address of the branch destination is the word data at the address indicated by ear.
Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear)
JMP @@RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
After execution
PC 3 C 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
PC 3 B 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
Memory space
217F48H
20
217F49H
3B
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
08
JMP @@RW0
651
APPENDIX
● Indirect specification branch addressing (@eam)
The address of the branch destination is the word data at the address indicated by eam.
Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam)
JMP @RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
PC 3 C 2 0
PCB 4 F
RW0 3 B 2 0
After execution
PC 3 B 2 0
RW0 3 B 2 0
652
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
00
JMP @RW0
APPENDIX B Instructions
B.5
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, "correction
value" determined by the condition, and the number of cycles for instruction fetch.
■ Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by adding the
number of cycles required for each instruction, "correction value" determined by the condition, and the
number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal
ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments.
Therefore, intervening in data access increases the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the
program fetches every byte of an instruction being executed. Therefore, intervening in data access increases
the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register,
internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the
cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register.
Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add
the "access count x cycle count for the halt" as a correction value to the normal execution count.
653
APPENDIX
■ Calculating the Execution Cycle Count
Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value
data.
Table B.5-1 Execution Cycle Counts in Each Addressing Mode
(a) *
Code
Operand
00
|
07
Ri
Rwi
RLi
08
|
0B
Execution cycle count in
each addressing mode
Register access count in
each addressing mode
See the instruction list.
See the instruction list.
@RWj
2
1
0C
|
0F
@RWj+
4
2
10
|
17
@RWi+disp8
2
1
18
|
1B
@RWi+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
*: (a) is used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List".
654
APPENDIX B Instructions
Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles
(b) byte *
Operand
(c) word *
(d) long *
Cycle
count
Access
count
Cycle
count
Access
count
Cycle
count
Access
count
Internal register
+0
1
+0
1
+0
2
Internal memory
Even address
+0
1
+0
1
+0
2
Internal memory
Odd address
+0
1
+2
2
+4
4
External data bus
16-bit even address
+1
1
+1
1
+2
2
External data bus
16-bit odd address
+1
1
+4
2
+8
4
External data bus
8-bits
+1
1
+4
2
+8
4
*: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction
List".
Note:
When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
-
+2
External data bus 16-bits
-
+3
External data bus 8-bits
+3
-
Notes:
• When an external data bus is used, the cycle counts during which an instruction is made to wait
by ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
655
APPENDIX
B.6
Effective address field
Table B.6-1 shows the effective address field.
■ Effective Address Field
Table B.6-1 Effective Address Field
Code
Representation
00
01
02
03
04
05
06
07
08
09
0A
R0
R1
R2
R3
R4
R5
R6
R7
@RW0
@RW1
@RW2
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
@RW3
@RW0+
@RW1+
@RW2+
@RW3+
@RW0+disp8
@RW1+disp8
@RW2+disp8
@RW3+disp8
@RW4+disp8
@RW5+disp8
@RW6+disp8
@RW7+disp8
@RW0+disp16
@RW1+disp16
@RW2+disp16
@RW3+disp16
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Address format
Byte count of
extended
address part *
Register direct: Individual parts correspond to
the byte, word, and long word types in order
from the left.
-
Register indirect
0
Register indirect with post increment
0
Register indirect with 8-bit displacement
1
Register indirect with 16-bit displacement
2
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
*1: Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC-16LX
Instruction List".
656
APPENDIX B Instructions
B.7
How to Read the Instruction List
Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table
B.7-2 describes the symbols used in the same list.
■ Description of Instruction Presentation Items and Symbols
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Mnemonic
Description
Uppercase, symbol: Represented as is in the assembler.
Lowercase: Rewritten in the assembler.
Number of following lowercase: Indicates bit length in the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table B.2-1 for the alphabetical letters in items.
RG
B
Operation
Indicates the number of times a register access is performed during instruction
execution.
The number is used to calculate the correction value for CPU intermittent
operation.
Indicates the correction value used to calculate the actual number of cycles during
instruction execution.
The actual number of cycles during instruction execution can be determined by
adding the value in the ~ column to this value.
Indicates the instruction operation.
LH
Indicates the special operation for bit15 to bit08 of the accumulator.
Z: Transfers 0.
X: Transfers after sign extension.
-: No transfer
AH
Indicates the special operation for the 16 high-order bits of the accumulator.
*: Transfers from AL to AH.
-: No transfer
Z: Transfers 00 to AH.
X: Transfers 00H or FFH to AH after AL sign extension.
657
APPENDIX
Table B.7-1 Description of Items in the Instruction List (2/2)
Item
Description
I
Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N
(negative), Z (zero), V (overflow), C (carry).
*: Changes upon instruction execution.
-: No change
S: Set upon instruction execution.
R: Reset upon instruction execution.
S
T
N
Z
V
C
RMW
Indicates whether the instruction is a Read Modify Write instruction (reading data
from memory by the I instruction and writing the result to memory).
*: Read Modify Write instruction
-: Not Read Modify Write instruction
Note:
Cannot be used for an address that has different meanings between read and
write operations.
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
A
658
Explanation
The bit length used varies depending on the 32-bit accumulator instruction.
Byte: Low-order 8 bits of byte AL
Word: 16 bits of word AL
Long word: 32 bits of AL and AH
AH
16 high-order bits of A
AL
16 low-order bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
program counter bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
APPENDIX B Instructions
Table B.7-2 Explanation on Symbols in the Instruction List (2/2)
Symbol
Ri
Explanation
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of addr24
ad24 16-23
Bit16 to bit23 of addr24
io
I/O area (000000H to 0000FFH)
#imm4
4-bit immediate data
#imm8
8-bit immediate data
#imm16
16-bit immediate data
#imm32
32-bit immediate data
ext (imm8)
16-bit data obtained by sign extension of 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
Bit offset
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
PC relative branch
ear
Effective addressing (code 00 to 07)
eam
Effective addressing (code 08 to 1F)
rlst
Register list
659
APPENDIX
B.8
F2MC-16LX Instruction List
Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX.
■ F2MC-16LX Instruction List
Table B.8-1 41 Transfer Instructions (Byte)
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RLi+disp8
A,#imm4
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
Ri,A
ear,A
eam,A
io,A
@RLi+disp8,A
Ri,ear
Ri,eam
ear,Ri
eam,Ri
Ri,#imm8
io,#imm8
dir,#imm8
ear,#imm8
eam,#imm8
@AL,AH
A,ear
A,eam
Ri,ear
Ri,eam
#
~
RG
B
2
3
1
2
2+
2
2
2
3
1
2
3
2
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
3
4
2
2
3 + (a)
3
2
3
10
1
3
4
2
2
3 + (a)
3
2
3
5
10
3
4
2
2
3 + (a)
3
10
3
4 + (a)
4
5 + (a)
2
5
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
0
0
1
1
0
0
0
0
2
0
0
0
1
1
0
0
0
0
1
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
2
0
4
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2 × (b)
0
2 × (b)
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)+disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
660
APPENDIX B Instructions
Table B.8-2 38 Transfer Instructions (Word, Long Word)
Mnemonic
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW
XCHW
XCHW
MOVL
MOVL
MOVL
MOVL
MOVL
A,dir
A,addr16
A,SP
A,RWi
A,ear
A,eam
A,io
A,@A
A,#imm16
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
SP,A
RWi,A
ear,A
eam,A
io,A
@RWi+disp8,A
@RLi+disp8,A
RWi,ear
RWi,eam
ear,RWi
eam,RWi
RWi,#imm16
io,#imm16
ear,#imm16
eam,#imm16
@AL,AH
A,ear
A,eam
RWi, ear
RWi, eam
A,ear
A,eam
A,#imm32
ear,A
eam,A
#
~
RG
B
2
3
1
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
2
2+
5
2
2+
3
4
1
2
2
3 + (a)
3
3
2
5
10
3
4
1
2
2
3 + (a)
3
5
10
3
4 + (a)
4
5 + (a)
2
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
4
5 + (a)
3
4
5 + (a)
0
0
0
1
1
0
0
0
0
1
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
0
2
0
4
2
2
0
0
2
0
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
(c)
0
2 × (c)
0
2 × (c)
0
(d)
0
0
(d)
Operation
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi)+disp8)
word (A) ← ((RLi)+disp8)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi)+disp8) ← (A)
word ((RLi)+disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
word ((A)) ← (AH)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (ear) ← (A)
long(eam) ← (A)
LH
AH
I
S
T
N
Z
V
C
RMW
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a), (c), and (d) in the table.
661
APPENDIX
Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A,ear
A,eam
A,#imm32
A,ear
A,eam
A,#imm32
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
2
3
4+(a)
2
3
5+(a)
3
4+(a)
2
3
4+(a)
2
3
5+(a)
3
4+(a)
6
7+(a)
4
6
7+(a)
4
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
2
0
0
2
0
0
0
0
(c)
0
0
2 × (c)
0
(c)
0
0
(c)
0
0
2 × (c)
0
(c)
0
(d)
0
0
(d)
0
Operation
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear)+ (C)
byte (A) ← (A) + (eam)+ (C)
byte (A) ← (AH) + (AL) + (C)
(decimal)
byte (A) ← (A) - imm8
byte (A) ← (A) - (dir)
byte (A) ← (A) - (ear)
byte (A) ← (A) - (eam)
byte (ear) ← (ear) - (A)
byte (eam) ← (eam) - (A)
byte (A) ← (AH) - (AL) - (C)
byte (A) ← (A) - (ear) - (C)
byte (A) ← (A) - (eam) - (C)
byte (A) ← (AH) - (AL) - (C)
(decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) - (AL)
word (A) ← (A) - (ear)
word (A) ← (A) - (eam)
word (A) ← (A) - imm16
word (ear) ← (ear) - (A)
word (eam) ← (eam) - (A)
word (A) ← (A) - (ear) - (C)
word (A) ← (A) - (eam) - (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) - (ear)
long (A) ← (A) - (eam)
long (A) ← (A) - imm32
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
662
APPENDIX B Instructions
Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
INC
ear
2
3
2
0
INC
eam
2+
5+(a)
0
2 × (b)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
byte (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
byte (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DEC
ear
2
3
2
0
byte (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
DEC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
INCW
ear
2
3
2
0
word (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
INCW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DECW
ear
2
3
2
0
DECW
eam
2+
5+(a)
0
2 × (c)
INCL
ear
2
7
4
0
INCL
eam
2+
9+(a)
0
2 × (d)
DECL
ear
2
7
4
0
DECL
eam
2+
9+(a)
0
2 × (d)
word (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
Table B.8-5 11 Compare Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
Mnemonic
A
1
1
0
0
byte (AH) - (AL)
Operation
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
663
APPENDIX
Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIVU
A
1
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A
1
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1: 3: Division by 0 7: Overflow 15: Normal
*2: 4: Division by 0 8: Overflow 16: Normal
*3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal
*4: 4: Division by 0 7: Overflow 22: Normal
*5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal
*6: (b): Division by 0 or overflow 2 × (b): Normal
*7: (c): Division by 0 or overflow 2 × (c): Normal
*8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0.
*9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0.
*10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0.
*11: 3: Word (AH) is 0. 11: Word (AH) is not 0.
*12: 4: Word (ear) is 0. 12: Word (ear) is not 0.
*13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0.
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
664
APPENDIX B Instructions
Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIV
A
2
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
Z
-
-
-
-
-
-
*
*
-
DIV
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
Z
-
-
-
-
-
-
*
*
-
DIV
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
Z
-
-
-
-
-
-
*
*
-
DIVW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MUL
A
2
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULW
A
2
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1:
*2:
*3:
*4:
3: Division by 0, 8 or 18: Overflow, 18: Normal
4: Division by 0, 11 or 22: Overflow, 23: Normal
5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal
When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal
When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal
*5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal
When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal
*6: (b): Division by 0 or overflow, 2 × (b): Normal
*7: (c): Division by 0 or overflow, 2 × (c): Normal
*8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative
*9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative
*10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative
*11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative
*12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative
*13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative
Notes:
• The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a
pre-operation count or a post-operation count depending on the detection timing.
• When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed.
• See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
665
APPENDIX
Table B.8-8 39 Logic 1 Instructions (Byte, Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
AND
A,#imm8
2
2
0
0
byte (A) ← (A) and imm8
-
-
-
-
-
*
*
R
-
AND
A,ear
2
3
1
0
byte (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
AND
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
byte (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
byte (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
AND
ear,A
2
3
2
0
AND
eam,A
2+
5+(a)
0
2 × (b)
OR
A,#imm8
2
2
0
0
byte (A) ← (A) or imm8
-
-
-
-
-
*
*
R
-
-
OR
A,ear
2
3
1
0
byte (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
OR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
OR
ear,A
2
3
2
0
byte (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
OR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XOR
A,#imm8
2
2
0
0
byte (A) ← (A) xor imm8
-
-
-
-
-
*
*
R
-
-
XOR
A,ear
2
3
1
0
byte (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XOR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XOR
ear,A
2
3
2
0
byte (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XOR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOT
A
1
2
0
0
byte (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOT
ear
2
3
2
0
byte (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOT
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
ANDW
A
1
2
0
0
word (A) ← (AH) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
A,#imm16
3
2
0
0
word (A) ← (A) and imm16
-
-
-
-
-
*
*
R
-
-
ANDW
A,ear
2
3
1
0
word (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
word (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
word (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
0
word (A) ← (AH) or (A)
-
-
-
-
-
*
*
R
-
-
0
word (A) ← (A) or imm16
-
-
-
-
-
*
*
R
-
-
1
0
word (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
0
(c)
word (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
ANDW
ear,A
2
3
2
0
ANDW
eam,A
2+
5+(a)
0
2 × (c)
ORW
A
1
2
0
ORW
A,#imm16
3
2
0
ORW
A,ear
2
3
ORW
A,eam
2+
4+(a)
word (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
word (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
0
word (A) ← (AH) xor (A)
-
-
-
-
-
*
*
R
-
-
0
word (A) ← (A) xor imm16
-
-
-
-
-
*
*
R
-
-
1
0
word (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
4+(a)
0
(c)
word (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
3
2
0
word (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
1
2
0
0
word (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
ear
2
3
2
0
word (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
eam
2+
5+(a)
0
2 × (c)
word (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
ORW
ear,A
2
3
2
0
ORW
eam,A
2+
5+(a)
0
2 × (c)
XORW
A
1
2
0
XORW
A,#imm16
3
2
0
XORW
A,ear
2
3
XORW
A,eam
2+
XORW
ear,A
2
XORW
eam,A
NOTW
A
NOTW
NOTW
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
666
APPENDIX B Instructions
Table B.8-9 6 Logic 2 Instructions (Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
ANDL
A,ear
2
6
2
0
long (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ORL
A,ear
2
6
2
0
long (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
XORL
A,ear
2
6
2
0
long (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (d) in the table.
Table B.8-10 6 Sign Inversion Instructions (Byte, Word)
Mnemonic
NEG
A
#
~
RG
B
1
2
0
0
NEG
ear
2
3
2
0
NEG
eam
2+
5+(a)
0
2 × (b)
NEGW
A
1
2
0
0
NEGW
ear
2
3
2
0
NEGW
eam
2+
5+(a)
0
2 × (c)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
byte (A) ← 0 - (A)
X
-
-
-
-
*
*
*
*
-
byte (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
byte (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
word (A) ← 0 - (A)
-
-
-
-
-
*
*
*
*
-
word (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
word (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
Table B.8-11 1 Normalization Instruction (Long Word)
Mnemonic
NRML
A,R0
#
~
RG
B
2
*1
1
0
Operation
long (A) ← Shift left to the position where '1' is set
for the first time.
byte (R0) ← Shift count at that time
LH
AH
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
*
-
-
-
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
667
APPENDIX
Table B.8-12 18 Shift Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
RORC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
ear
2
3
2
0
byte (ear) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
*
ROLC
ear
2
3
2
0
byte (ear) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
*
ASR
A,R0
2
*1
1
0
byte (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSR
A,R0
2
*1
1
0
byte (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSL
A,R0
2
*1
1
0
byte (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRW
A
1
2
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSRW
A/SHRW A
1
2
0
0
word (A) ← Logical right shift (A, 1 bit)
-
-
-
-
*
R
*
-
*
-
LSLW
A/SHLW A
1
2
0
0
word (A) ← Logical left shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
ASRW
A,R0
2
*1
1
0
word (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRW
A,R0
2
*1
1
0
word (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLW
A,R0
2
*1
1
0
word (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRL
A,R0
2
*2
1
0
long (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRL
A,R0
2
*2
1
0
long (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLL
A,R0
2
*2
1
0
long (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
668
APPENDIX B Instructions
Table B.8-13 31 Branch 1 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
BZ/BEQ
rel
2
*1
0
0
Branch on (Z) = 1
-
-
-
-
-
-
-
-
-
-
BNZ/
BNE
rel
2
*1
0
0
Branch on (Z) = 0
-
-
-
-
-
-
-
-
-
-
BC/BLO
rel
2
*1
0
0
Branch on (C) = 1
-
-
-
-
-
-
-
-
-
-
BNC/
BHS
rel
2
*1
0
0
Branch on (C) = 0
-
-
-
-
-
-
-
-
-
-
BN
rel
2
*1
0
0
Branch on (N) = 1
-
-
-
-
-
-
-
-
-
-
BP
rel
2
*1
0
0
Branch on (N) = 0
-
-
-
-
-
-
-
-
-
-
BV
rel
2
*1
0
0
Branch on (V) = 1
-
-
-
-
-
-
-
-
-
-
BNV
rel
2
*1
0
0
Branch on (V) = 0
-
-
-
-
-
-
-
-
-
-
BT
rel
2
*1
0
0
Branch on (T) = 1
-
-
-
-
-
-
-
-
-
-
BNT
rel
2
*1
0
0
Branch on (T) = 0
-
-
-
-
-
-
-
-
-
-
BLT
rel
2
*1
0
0
Branch on (V) xor (N) = 1
-
-
-
-
-
-
-
-
-
-
BGE
rel
2
*1
0
0
Branch on (V) xor (N) = 0
-
-
-
-
-
-
-
-
-
-
BLE
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BGT
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BLS
rel
2
*1
0
0
Branch on (C) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BHI
rel
2
*1
0
0
Branch on (C) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BRA
rel
2
*1
0
0
Unconditional branch
-
-
-
-
-
-
-
-
-
-
JMP
@A
1
2
0
0
word (PC) ← (A)
-
-
-
-
-
-
-
-
-
-
JMP
addr16
3
3
0
0
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
JMP
@ear
2
3
1
0
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
JMP
@eam
2+
4+(a)
0
(c)
-
JMPP
@ear *3
2
5
2
0
JMPP
@eam *3
2+
6+(a)
0
(d)
JMPP
addr24
4
4
0
0
CALL
@ear *4
2
6
1
(c)
CALL
@eam *4
2+
7+(a)
0
CALL
addr16 *5
3
6
CALLV
#vct4 *5
1
CALLP
@ear *6
CALLP
CALLP
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
2 × (c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
0
(c)
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
7
0
2 × (c)
Vector call instruction
-
-
-
-
-
-
-
-
-
-
2
10
2
2 × (c)
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
@eam *6
2+
11+(a)
0
*2
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
addr24 *7
4
10
0
2 × (c)
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
*1: 4 when a branch is made; otherwise, 3
*2: 3 × (c) + (b)
*3: Read (word) of branch destination address
*4: W: Save to stack (word) R: Read (word) of branch destination address
*5: Save to stack (word)
*6: W: Save to stack (long word), R: Read (long word) of branch destination address
*7: Save to stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
669
APPENDIX
Table B.8-14 19 Branch 2 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S T N Z V C
RMW
CBNE
A,#imm8,rel
3
*1
0
0
Branch on byte (A) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
A,#imm16,rel
4
*1
0
0
Branch on word (A) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CBNE
ear,#imm8,rel
4
*2
1
0
Branch on byte (ear) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CBNE
eam,#imm8,rel *9
4+
*3
0
(b)
Branch on byte (eam) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
ear,#imm16,rel
5
*4
1
0
Branch on word (ear) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CWBNE
eam,#imm16,rel*9
5+
*3
0
(c)
Branch on word (eam) not equal to imm16
-
-
-
-
-
*
*
*
*
-
DBNZ
ear,rel
3
*5
2
0
byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0
-
-
-
-
-
*
*
*
-
-
DBNZ
eam,rel
3+
*6
2
*
DWBNZ
ear,rel
3
*5
2
DWBNZ
eam,rel
3+
*6
2
2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0
2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0
0
word (ear) ← (ear) - 1, Branch on (ear) not equal to 0
-
-
-
-
-
*
*
*
-
-
-
-
-
-
*
*
*
-
-
-
-
-
-
-
*
*
*
-
*
INT
#vct8
2
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT
addr16
3
16
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INTP
addr24
4
17
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
1
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT9
RETI
LINK
#imm8
UNLINK
1
*8
0
*7
Return from interrupt
-
-
*
*
*
*
*
*
*
-
2
6
0
(c)
Saves the old frame pointer in the stack upon entering the
function, then sets the new frame pointer and reserves the
local pointer area.
-
-
-
-
-
-
-
-
-
-
1
5
0
(c)
Recovers the old frame pointer from the stack upon exiting
the function.
-
-
-
-
-
-
-
-
-
-
RET
*10
1
4
0
(c)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
RETP
*11
1
6
0
(d)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
*1: 5 when a branch is made; otherwise, 4
*2: 13 when a branch is made; otherwise, 12
*3: 7+(a) when a branch is made; otherwise, 6+(a)
*4: 8 when a branch is made; otherwise, 7
*5: 7 when a branch is made; otherwise, 6
*6: 8+(a) when a branch is made; otherwise, 7+(a)
*7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption
*8: 15 when jumping to the next interruption request; 17 when returning from the current interruption
*9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction.
*10: Return from stack (word)
*11: Return from stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
670
APPENDIX B Instructions
Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
PUSHW
A
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (A)
-
-
-
-
-
-
-
-
-
-
PUSHW
AH
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (AH)
-
-
-
-
-
-
-
-
-
-
PUSHW
PS
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (PS)
-
-
-
-
-
-
-
-
-
PUSHW
rlst
2
*3
*5
*4
(SP) ← (SP) - 2n, ((SP)) ← (rlst)
-
-
-
-
-
-
-
-
-
-
POPW
A
1
3
0
(c)
word (A) ← ((SP)), (SP) ← (SP) + 2
-
*
-
-
-
-
-
-
-
-
POPW
AH
1
3
0
(c)
word (AH) ← ((SP)), (SP) ← (SP) + 2
-
-
-
-
-
-
-
-
-
-
POPW
PS
1
4
0
(c)
word (PS) ← ((SP)), (SP) ← (SP) + 2
-
-
*
*
*
*
*
*
*
-
POPW
rlst
2
*2
*5
*4
(rlst) ← ((SP)), (SP) ← (SP) + 2n
-
-
-
-
-
-
-
-
-
-
JCTX
@A
1
14
0
6 × (c)
Context switch instruction
-
-
*
*
*
*
*
*
*
-
AND
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) and imm8
-
-
*
*
*
*
*
*
*
-
OR
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) or imm8
-
-
*
*
*
*
*
*
*
-
MOV
RP,#imm8
2
2
0
0
byte (RP) ← imm8
-
-
-
-
-
-
-
-
-
-
MOV
ILM,#imm8
2
2
0
0
byte (ILM) ← imm8
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,ear
2
3
1
0
word (RWi) ← ear
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,eam
2+
2+(a)
1
0
word (RWi) ← eam
-
-
-
-
-
-
-
-
-
-
MOVEA
A,ear
2
1
0
0
word (A) ← ear
-
*
-
-
-
-
-
-
-
-
MOVEA
A,eam
2+
1+(a)
0
0
word (A) ← eam
-
*
-
-
-
-
-
-
-
-
ADDSP
#imm8
2
3
0
0
word (SP) ← (SP) + ext(imm8)
-
-
-
-
-
-
-
-
-
-
ADDSP
#imm16
3
3
0
0
word (SP) ← (SP) + imm16
-
-
-
-
-
-
-
-
-
-
MOV
A,brg1
2
*1
0
0
byte (A) ← (brg1)
Z
*
-
-
-
*
*
-
-
-
MOV
brg2,A
-
2
1
0
0
byte (brg2) ← (A)
-
-
-
-
-
*
*
-
-
NOP
1
1
0
0
No operation
-
-
-
-
-
-
-
-
-
-
ADB
1
1
0
0
Prefix code for AD space access
-
-
-
-
-
-
-
-
-
-
DTB
1
1
0
0
Prefix code for DT space access
-
-
-
-
-
-
-
-
-
-
PCB
1
1
0
0
Prefix code for PC space access
-
-
-
-
-
-
-
-
-
-
SPB
1
1
0
0
Prefix code for SP space access
-
-
-
-
-
-
-
-
-
-
NCC
1
1
0
0
Prefix code for flag no-change
-
-
-
-
-
-
-
-
-
-
CMR
1
1
0
0
Prefix code for common register bank
-
-
-
-
-
-
-
-
-
-
*1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2
*2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register)
*3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register)
*4: (POP count) × (c) or (PUSH count) × (c)
*5: (POP count) or (PUSH count)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (c) in the table.
671
APPENDIX
Table B.8-16 21 Bit Operand Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
MOVB
A,dir:bp
3
5
0
(b)
byte (A) ← (dir:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,addr16:bp
4
5
0
(b)
byte (A) ← (addr16:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,io:bp
3
4
0
(b)
byte (A) ← (io:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
dir:bp,A
3
7
0
2 × (b)
bit (dir:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
addr16:bp,A
4
7
0
2 × (b)
bit (addr16:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
io:bp,A
3
6
0
2 × (b)
bit (io:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
SETB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
CLRB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
BBC
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBS
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
io:bp,rel
4
*2
0
(b)
SBBS
addr16:bp,rel
5
*3
0
2 × (b)
Branch on (io:bp) b = 1
-
-
-
-
-
-
*
-
-
-
Branch on (addr16:bp) b = 1,
bit (addr16:bp) b ← 1
-
-
-
-
-
-
*
-
-
*
WBTS
io:bp
3
*4
0
WBTC
io:bp
3
*4
0
*5
Waits until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
*5
Waits until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
RMW
*1: 8 when a branch is made; otherwise, 7
*2: 7 when a branch is made; otherwise, 6
*3: 10 when the condition is met; otherwise, 9
*4: Undefined count
*5: Until the condition is met
Note:
See Table B.5-1 and Table B.5-2 for information on (b) in the table.
Table B.8-17 6 Accumulator Operation Instructions (Byte, Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
SWAP
Mnemonic
1
3
0
0
byte (A)0-7 ↔ (A)8-15
Operation
-
-
-
-
-
-
-
-
-
-
SWAPW
1
2
0
0
word (AH) ↔ (AL)
-
*
-
-
-
-
-
-
-
-
EXT
1
1
0
0
Byte sign extension
X
-
-
-
-
*
*
-
-
-
EXTW
1
2
0
0
Word sign extension
-
X
-
-
-
*
*
-
-
-
ZEXT
1
1
0
0
Byte zero extension
Z
-
-
-
-
R
*
-
-
-
ZEXTW
1
1
0
0
Word zero extension
-
Z
-
-
-
R
*
-
-
-
672
APPENDIX B Instructions
Table B.8-18 10 String Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
MOVS / MOVSI
2
*2
*5
*3
byte transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
MOVSD
2
*2
*5
*3
byte transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCEQ / SCEQI
2
*1
*8
*4
byte search @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCEQD
2
*1
*8
*4
byte search @AH- ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILS / FILSI
2
6m+6
*8
*3
byte fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
MOVSW / MOVSWI
2
*2
*5
*6
word transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSWD
2
*2
*5
*6
word transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI
2
*1
*8
*7
word search @AH+ - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCWEQD
2
*1
*8
*7
word search @AH- - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILSW / FILSWI
2
6m+6
*8
*6
word fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
*1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs
*2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0)
*3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually.
*4: (b) × n
*5: 2 × (b) × (RW0)
*6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually.
*7: (c) × n
*8: (b) × (RW0)
Note:
m: RW0 value (counter value), n: Loop count
See Table B.5-1 and Table B.5-2 for information on (b) and (c) in the table.
673
APPENDIX
B.9
Instruction Map
Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction
map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX
instruction map.
■ Structure of Instruction Map
Figure B.9-1 Structure of Instruction Map
Basic page map
Bit operation
instructions
Character string
operation
instructions
2-byte
instructions
: Byte 1
ea instructions × 9 : Byte 2
An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An
instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it
references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2
shows the correspondence between an actual instruction code and instruction map.
674
APPENDIX B Instructions
Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map
Some instructions do
not contain byte 2.
Instruction
code
Length varies
depending on the
instruction.
Byte 1
Byte 2
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
*: The extended page map is a generic name of maps for bit operation instructions, character
string operation instructions, 2-byte instructions, and ea instructions. Actually, there are
multiple extended page maps for each type of instructions.
An example of an instruction code is shown in Table B.9-1 .
Table B.9-1 Example of an Instruction Code
Byte 1
(from basic page map)
Byte 2
(from extended page map)
NOP
00 +0=00
-
AND A, #8
30 +4=34
-
MOV A, ADB
60 +F=6F
00 +0=00
@RW2+d8, #8, rel
70 +0=70
F0 +2=F2
Instruction
675
676
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
A
ZEXT
SWAP
ADDSP
DTB
ADB
SPB
#8
A, #8
dir, A
A, dir
io, A
A, io
JMP
BRA
60
MULU
DIVU
ea
@A instruction 2
A
MOVW
MOVX
RET
SP, A A, addr16
A0
B0
C0
ea
instruction 8
D0
E0
rel
rel
LSRW
ASRW
LSLW
SWAPW
ZEXTW
XORW
ORW
ANDW
ORW
PUSHW
POPW
A, #16
AH
AH
MOVW
ea, RWi
Bit operation MOV
A instruction
ea, Ri
MOVW
RWi, ea
PUSHW
POPW
2-byte
XCHW
A
rlst
rlst instruction
RWi, ea
Character
XORW
PUSHW
POPW
XCH
operation
A
A, #16
PS
PS string
Ri, ea
instruction
A
ANDW
PUSHW
POPW
A
A, #16
A
CMPW
MOVL
MOVW
RETI
A, #16
A, #32 addr16, A
ADDSP
MULUW
NOTW
A
#16
A
A
A
EXTW
A
BHI
BLS
BGT
BLE
rel
rel
rel
rel
rel
BGE
CMPL
CMPW
A, #32
NEGW
A
rel
rel
rel
rel
rel
rel
BLT
BT
BNV
BV
BP
BN
BNC/BHS
rel
BC/BLO
BNZ/BNE
rel
BZ/BEQ
MOV
MOV
CBNE A, CWBNE A, MOVW
MOVW
INTP
MOV
RP, #8
ILM, #8
#8, rel
#16, rel
A, #16 A,addr16
addr24
Ri, ea
#4
F0
rel
ADDW
MOVW
MOVW
INT
ea
MOVW
MOVW
MOVW
MOV A,
MOVW
A, #16
A, dir
A, io
#vct8 instruction 9
A, RWi
RWi, A RWi, #16 @RWi+d8 @RWi+d8, A
NOT
ea
instruction 7
MOVX
MOVX
CALLP
ea
A, dir
A, io
addr24 instruction 6
MOVW
MOVW
RETP
A, #8
A, SP
io, #16
A, #8
90
BNT
SUBL
SUBW
A, #32
A
A
A
XOR
OR
OR
CCR, #8
80
ea
MOV
MOV
MOV
MOV
MOVX A, MOV
CALL
rel instruction 1
A, Ri
Ri, A
Ri, #8
A, Ri @RWi+d8
A, #4
70
MOV
JMP
ea
A, addr16
addr16 instruction 3
MOV
MOV
50
MOVX
MOV
JMPP
ea
A, #8
A, #8 addr16, A
addr24 instruction 4
MOV
MOV
MOV
40
SUBW
MOVW
MOVW
INT
MOVEA
A
A, #16
dir, A
io, A
addr16
RWi, ea
UNLINK
A
CMP
A
A, #8
A, #8
SUBC
SUB
ADD
30
AND
AND
MOV
MOV
CALL
ea
CCR, #8
A, #8
dir, #8
io, #8
addr16 instruction 5
CMP
A
A, dir
A, dir
ADDC
SUB
ADD
20
LINK
ADDL
ADDW
#imm8
A, #32
EXT
@A
PCB
A
JCTX
SUBDC
ADDDC
NEG
NCC
INT9
A
CMR
10
NOP
00
APPENDIX
Table B.9-2 Basic Page Map
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
10
MOVB
io:bp, A
20
30
CLRB
io:bp
40
50
SETB
io:bp
60
70
BBC
io;bp, rel
80
90
BBS
io:bp, rel
A0
B0
MOVB
MOVB A, MOVB
MOVB
CLRB
CLRB
SETB
SETB
BBC
BBC
BBS
BBS
A, dir:bp addr16:bp
dir:bp, A addr16:bp,A
dir:bp addr16:bp
dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel
MOVB
A, io:bp
00
WBTS
io:bp
C0
D0
WBTC
io:bp
E0
SBBS
addr16:bp
F0
APPENDIX B Instructions
Table B.9-3 Bit Operation Instruction Map (First Byte = 6CH)
677
678
MOVSI
MOVSD
PCB, PCB
PCB, DTB
PCB, ADB
PCB, SPB
DTB, PCB
DTB, DTB
DTB, ADB
DTB, SPB
ADB, PCB
ADB, DTB
ADB, ADB
ADB, SPB
SPB, PCB
SPB, DTB
SPB, ADB
SPB, SPB
+1
+2
+3
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
10
+0
00
MOVSWI
20
MOVSWD
30
40
50
60
70
90
A0
B0
C0
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SCEQI
SCEQD
SCWEQI SCWEQD FILSI
PCB
PCB
PCB
PCB
PCB
80
D0
FILSI
SPB
ADB
DTB
PCB
E0
F0
APPENDIX
Table B.9-4 Character String Operation Instruction Map (First Byte = 6EH)
LSLW
LSLL
LSL
MOVW
MOVW
A, R0
A, R0
A, R0 @RL2+d8, A A, @RL2+d8
MOVW
MOVW
NRML
A, @A @AL, AH
A, R0
ASRW
ASRL
ASR
MOVW
MOVW
A, R0
A, R0
A, R0 @RL3+d8, A A, @RL3+d8
LSRW
LSRL
LSR
A, R0
A, R0
A, R0
+D
+E
+F
MOVW
MOVW
@RL1+d8, A A, @RL1+d8
MOVW
MOVW
@RL0+d8, A A, @RL0+d8
+C
+B
+A
+9
+8
A
MOV
MOV
MOVX
MOV
MOV
A, PCB
A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8
+6
ROLC
MOV
MOV
A, @A @AL, AH
+5
A
MOV
MOV
MOVX
MOV
MOV
A, DPR
DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8
+4
ROLC
MOV
MOV
A, USB
USB, A
+3
+7
MOV
MOV
MOVX
MOV
MOV
A, SSB
SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8
+2
40
MOV
MOV
A, ADB
ADB, A
30
+1
20
MOV
MOV
MOVX
MOV
MOV
A, DTB
DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8
10
+0
00
50
DIVU
MULW
MUL
60
A
A
A
70
80
90
A0
B0
C0
D0
E0
F0
APPENDIX B Instructions
Table B.9-5 2-byte Instruction Map (First Byte = 6FH)
679
680
50
90
B0
D0
@RW1, @RW1+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
@RW2, @RW2+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
@RW3, @RW3+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
SUBL
SUBL A,
A, RL2 @RW5+d8
SUBL
SUBL A,
A, RL3 @RW6+d8
SUBL
SUBL A,
A, RL3 @RW7+d8
ADDL
ADDL A,
A, RL2 @RW5+d8
ADDL
ADDL A,
A, RL3 @RW6+d8
ADDL
ADDL A,
A, RL3 @RW7+d8
ADDL
ADDL A, SUBL
SUBL A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ADDL
ADDL A, SUBL
SUBL A, Use
@RW0+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW0+RW7
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
#16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
,#8, rel
ADDL
ADDL A, SUBL
SUBL A, Use
@RW1+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW1+RW7
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
#16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
,#8, rel
ADDL
ADDL A,
A,@RW2+ @PC+d16
ADDL
ADDL A, SUBL
SUBL A, Use
A,@RW3+
addr16 A,@RW3+
addr16 prohibited
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
SUBL
SUBL A,
A,@RW2+ @PC+d16
@RW0, @RW0+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
SUBL
SUBL A,
A, RL2 @RW4+d8
Use
prohibited
ANDL
ANDL A,
A,@RW2+ @PC+d16
ANDL
ANDL A,
A, RL3 @RW7+d8
ANDL
ANDL A,
A, RL3 @RW6+d8
ANDL
ANDL A,
A, RL2 @RW5+d8
ANDL
ANDL A,
A, RL2 @RW4+d8
ORL
ORL A,
A,@RW2+ @PC+d16
ORL
ORL A,
A, RL3 @RW7+d8
ORL
ORL A,
A, RL3 @RW6+d8
ORL
ORL A,
A, RL2 @RW5+d8
ORL
ORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A,@RW2+ @PC+d16
XORL
XORL A,
A, RL3 @RW7+d8
XORL
XORL A,
A, RL3 @RW6+d8
XORL
XORL A,
A, RL2 @RW5+d8
XORL
XORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A, RL1 @RW3+d8
addr16,
,#8, rel
Use
@PC+d16,
prohibited
,#8, rel
@RW3, @RW3+d16
#8, rel
,#8, rel
@RW2, @RW2+d16
#8, rel
,#8, rel
@RW1, @RW1+d16
#8, rel
,#8, rel
@RW0, @RW0+d16
#8, rel
,#8, rel
R7, @RW7+d8,
#8, rel
#8, rel
R6, @RW6+d8,
#8, rel
#8, rel
R5, @RW5+d8,
#8, rel
#8, rel
R4, @RW4+d8,
#8, rel
#8, rel
R3, @RW3+d8,
#8, rel
#8, rel
addr16, CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
#16, rel A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 prohibited
@PC+d16, CMPL
CMPL A,
#16, rel A,@RW2+ @PC+d16
RW7, @RW7+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW7+d8
RW6, @RW6+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW6+d8
RW5, @RW5+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW5+d8
RW4, @RW4+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW4+d8
ORL
ORL A,
A, RL1 @RW3+d8
R2, @RW2+d8,
#8, rel
#8, rel
R1, @RW1+d8,
#8, rel
#8, rel
ADDL
ADDL A,
A, RL2 @RW4+d8
ANDL
ANDL A,
A, RL1 @RW3+d8
XORL
XORL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW1+d8
+4
RW3, @RW3+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW3+d8
ORL
ORL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW1+d8
SUBL
SUBL A,
A, RL1 @RW3+d8
ANDL
ANDL A,
A, RL1 @RW2+d8
ANDL
ANDL A,
A, RL0 @RW1+d8
ADDL
ADDL A,
A, RL1 @RW3+d8
RW2, @RW2+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW2+d8
RW1, @RW1+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW1+d8
+3
CBNE ↓
F0
R0, @RW0+d8,
#8, rel
#8, rel
CBNE ↓
E0
SUBL
SUBL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW0+d8
C0
ADDL
ADDL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW0+d8
A0
+2
ANDL
ANDL A,
A, RL0 @RW0+d8
80
SUBL
SUBL A,
A, RL0 @RW1+d8
70
ADDL
ADDL A,
A, RL0 @RW1+d8
60
RW0, @RW0+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW0+d8
CWBNE ↓ CWBNE ↓
40
+1
30
+0
20
SUBL
SUBL A,
A, RL0 @RW0+d8
10
ADDL
ADDL A,
A, RL0 @RW0+d8
00
APPENDIX
Table B.9-6 ea Instruction 1 (First Byte = 70H)
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW7+d8
@RL3 @@RW7+d8
RL3 @RW7+d8
RL3 @RW7+d8
A, RL3 @RW7+d8
RL3, A @RW7+d8,A
R7, #8 @RW7+d8,#8
A, RW7 @RW7+d8
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8
A,@RW0 @RW0+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8
A,@RW1 @RW1+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8
A,@RW2 @RW2+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8
A,@RW3 @RW3+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+,A
addr16, A @RW3+, #8
addr16, #8 A,@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW6+d8
@RL3 @@RW6+d8
RL3 @RW6+d8
RL3 @RW6+d8
A, RL3 @RW6+d8
RL3, A @RW6+d8,A
R6, #8 @RW6+d8,#8
A, RW6 @RW6+d8
D0
+6
C0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW5+d8
@RL2 @@RW5+d8
RL2 @RW5+d8
RL2 @RW5+d8
A, RL2 @RW5+d8
RL2, A @RW5+d8,A
R5, #8 @RW5+d8,#8
A, RW5 @RW5+d8
B0
+5
A0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW4+d8
@RL2 @@RW4+d8
RL2 @RW4+d8
RL2 @RW4+d8
A, RL2 @RW4+d8
RL2, A @RW4+d8,A
R4, #8 @RW4+d8,#8
A, RW4 @RW4+d8
90
+4
80
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW3+d8
@RL1 @@RW3+d8
RL1 @RW3+d8
RL1 @RW3+d8
A, RL1 @RW3+d8
RL1, A @RW3+d8,A
R3, #8 @RW3+d8,#8
A, RW3 @RW3+d8
70
+3
60
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW2+d8
@RL1 @@RW2+d8
RL1 @RW2+d8
RL1 @RW2+d8
A, RL1 @RW2+d8
RL1, A @RW2+d8,A
R2, #8 @RW2+d8,#8
A, RW2 @RW2+d8
50
+2
40
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW1+d8
@RL0 @@RW1+d8
RL0 @RW1+d8
RL0 @RW1+d8
A, RL0 @RW1+d8
RL0, A @RW1+d8,A
R1, #8 @RW1+d8,#8
A, RW1 @RW1+d8
30
+1
20
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW0+d8
@RL0 @@RW0+d8
RL0 @RW0+d8
RL0 @RW0+d8
A, RL0 @RW0+d8
RL0, A @RW0+d8,A
R0, #8 @RW0+d8,#8
A, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-7 ea Instruction 2 (First Byte = 71H)
681
682
D0
E0
F0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A A,@RW3+
addr16 A,@RW3+
addr16
+D
+E
+F
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R7 @RW7+d8
A, R7 @RW7+d8
R7, A @RW7+d8,A
A, R7 @RW7+d8
A, R7 @RW7+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R6 @RW6+d8
A, R6 @RW6+d8
R6, A @RW6+d8,A
A, R6 @RW6+d8
A, R6 @RW6+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R5 @RW5+d8
A, R5 @RW5+d8
R5, A @RW5+d8,A
A, R5 @RW5+d8
A, R5 @RW5+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R4 @RW4+d8
A, R4 @RW4+d8
R4, A @RW4+d8,A
A, R4 @RW4+d8
A, R4 @RW4+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R3 @RW3+d8
A, R3 @RW3+d8
R3, A @RW3+d8,A
A, R3 @RW3+d8
A, R3 @RW3+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R2 @RW2+d8
A, R2 @RW2+d8
R2, A @RW2+d8,A
A, R2 @RW2+d8
A, R2 @RW2+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R1 @RW1+d8
A, R1 @RW1+d8
R1, A @RW1+d8,A
A, R1 @RW1+d8
A, R1 @RW1+d8
+C
INC
DEC
R7 @RW7+d8
C0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ROLC
RORC
RORC
INC
R7 @RW7+d8
R7 @RW7+d8
ROLC
INC
DEC
R6 @RW6+d8
B0
+B
ROLC
RORC
RORC
INC
R6 @RW6+d8
R6 @RW6+d8
ROLC
INC
DEC
R5 @RW5+d8
A0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ROLC
RORC
RORC
INC
R5 @RW5+d8
R5 @RW5+d8
ROLC
INC
DEC
R4 @RW4+d8
90
+A
ROLC
RORC
RORC
INC
R4 @RW4+d8
R4 @RW4+d8
ROLC
INC
DEC
R3 @RW3+d8
INC
DEC
R2 @RW2+d8
INC
DEC
R1 @RW1+d8
80
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R0 @RW0+d8
A, R0 @RW0+d8
R0, A @RW0+d8,A
A, R0 @RW0+d8
A, R0 @RW0+d8
70
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ROLC
RORC
RORC
INC
R3 @RW3+d8
R3 @RW3+d8
ROLC
60
INC
DEC
R0 @RW0+d8
50
+9
ROLC
RORC
RORC
INC
R2 @RW2+d8
R2 @RW2+d8
ROLC
40
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ROLC
RORC
RORC
INC
R1 @RW1+d8
R1 @RW1+d8
ROLC
30
ROLC
RORC
RORC
INC
R0 @RW0+d8
R0 @RW0+d8
20
ROLC
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX
Table B.9-8 ea Instruction 3 (First Byte = 72H)
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16
+B
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A @RW3+, #16
addr16, #16 A,@RW3+
addr16
INCW @
+F
INCW
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @@PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16
CALL @
+E
CALL
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7
XCHW
XCHW A,
A, RW7 @RW7+d8
XCHW
XCHW A,
A, RW6 @RW6+d8
XCHW
XCHW A,
A, RW5 @RW5+d8
+D @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7
INCW @
MOVW
MOVW
RW7, #16 @RW7+d8,#16
MOVW
MOVW
RW6, #16 @RW6+d8,#16
MOVW
MOVW
RW5, #16 @RW5+d8,#16
XCHW
XCHW A,
A, RW4 @RW4+d8
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7
INCW
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW7 @RW7+d8
RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, A @RW7+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW6 @RW6+d8
RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, A @RW6+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW5 @RW5+d8
RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, A @RW5+d8,A
MOVW
MOVW
RW4, #16 @RW4+d8,#16
+C @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7
JMP @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16
+A
JMP
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16
+9
CALL @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16
+8
CALL
CALL
CALL
RW7 @@RW7+d8
JMP
JMP
@RW7 @@RW7+d8
+7
JMP @
CALL
CALL
RW6 @@RW6+d8
JMP
JMP
@RW6 @@RW6+d8
+6
JMP
CALL
CALL
RW5 @@RW5+d8
JMP
JMP
@RW5 @@RW5+d8
+5
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW4 @RW4+d8
RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, A @RW4+d8,A
XCHW
XCHW A,
A, RW3 @RW3+d8
XCHW
XCHW A,
A, RW2 @RW2+d8
XCHW
XCHW A,
A, RW1 @RW1+d8
CALL
CALL
RW4 @@RW4+d8
MOVW
MOVW
RW3, #16 @RW3+d8,#16
MOVW
MOVW
RW2, #16 @RW2+d8,#16
MOVW
MOVW
RW1, #16 @RW1+d8,#16
JMP
JMP
@RW4 @@RW4+d8
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW3 @RW3+d8
RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, A @RW3+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW2 @RW2+d8
RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, A @RW2+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW1 @RW1+d8
RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, A @RW1+d8,A
+4
F0
XCHW
XCHW A,
A, RW0 @RW0+d8
E0
CALL
CALL
RW3 @@RW3+d8
D0
MOVW
MOVW
RW0, #16 @RW0+d8,#16
C0
JMP
JMP
@RW3 @@RW3+d8
B0
+3
A0
CALL
CALL
RW2 @@RW2+d8
90
JMP
JMP
@RW2 @@RW2+d8
80
+2
70
CALL
CALL
RW1 @@RW1+d8
60
JMP
JMP
@RW1 @@RW1+d8
50
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW0 @RW0+d8
RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, A @RW0+d8,A
40
+1
30
CALL
CALL
RW0 @@RW0+d8
20
JMP
JMP
@RW0 @@RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-9 ea Instruction 4 (First Byte = 73H)
683
684
ADD
A, SUB
SUB
SUB
ADDC
A, ADDC
A,
ADDC
ADDC A,
A, CMP
CMP
CMP
CMP
A,
A,
A, AND
AND
AND
AND
AND
AND
A,
A,
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r PC+d16, r
+F A,@RW3+
ADD
ADD
SUB
SUB
ADDC
ADDC
CMP
CMP
AND
AND
OR
OR
XOR
XOR
DBNZ
DBNZ
A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+
A, addr16 A,@RW3+ A, addr16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ADD
SUB
CMP
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW1+ @RW1+RW7 @RW1+, r W1+RW7, r
A,
CMP
OR
OR
A,
A,@RW1+ @RW1+RW7
ADD
ADD
ADDC A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ADDC
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW0+ @RW0+RW7 @RW0+, r W0+RW7, r
A,
OR
OR
A,
A,@RW0+ @RW0+RW7
SUB
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
SUB
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW3 @RW3+d16 @RW3, r W3+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
A,
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW2 @RW2+d16 @RW2, r W2+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW1 @RW1+d16 @RW1, r W1+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW0 @RW0+d16 @RW0, r W0+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
R7, r RW7+d8, r
ADD
F0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
R6, r RW6+d8, r
E0
ADD
D0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
R5, r RW5+d8, r
C0
ADD
B0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
R4, r RW4+d8, r
A0
ADD
90
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
R3, r RW3+d8, r
80
ADD
70
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
R2, r RW2+d8, r
60
ADD
50
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
R1, r RW1+d8, r
40
ADD
30
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
R0, r RW0+d8, r
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX
Table B.9-10 ea Instruction 5 (First Byte = 74H)
NOT
NOT
R2 @RW2+d8
SUB
SUB
SUB
SUB
ADD
SUB
SUB
@RW1+RW7,A @RW1+, A @RW1+RW7,A
ADD @R
@RW0+RW7,A @RW0+, A @RW0+RW7,A
ADD @R
+F
ADD
ADD
@RW3+, A addr16, A
SUB
SUB
@RW3+, A addr16, A
+E @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
ADD
+D @RW1+, A
ADD
+C @RW0+, A
ADD
NOT
NOT
@RW1+ @RW1+RW7
NOT
NOT
@RW0+ @RW0+RW7
SUBC
SUBC A, NEG
NEG A,
AND
AND
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
OR
OR
@RW3+, A addr16, A
XOR
XOR
@RW3+, A addr16, A
NOT
NOT
@RW3+
addr16
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
NOT
NOT
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A
NOT
NOT
@RW3 @RW3+d16
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
+B
XOR
NOT
NOT
R7, A @RW7+d8, A
R7 @RW7+d8
XOR
NOT
NOT
R6, A @RW6+d8, A
R6 @RW6+d8
XOR
NOT
NOT
R5, A @RW5+d8, A
R5 @RW5+d8
XOR
NOT
NOT
R4, A @RW4+d8, A
R4 @RW4+d8
XOR
NOT
NOT
R3, A @RW3+d8, A
R3 @RW3+d8
XOR
R2, A @RW2+d8,A
XOR
NOT
NOT
R1, A @RW1+d8, A
R1 @RW1+d8
NOT
NOT
@RW2 @RW2+d16
XOR
F0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
NEG A,
AND
AND
OR
OR
R7 @RW7+d8
R7, A @RW7+d8, A
R7, A @RW7+d8, A
XOR
XOR
XOR
XOR
XOR
XOR
E0
XOR
NOT
NOT
R0, A @RW0+d8, A
R0 @RW0+d8
D0
+A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R7, A @RW7+d8, A
R7, A @RW7+d8, A
A, R7 @RW7+d8
ADD
NEG A,
AND
AND
OR
OR
R6 @RW6+d8
R6, A @RW6+d8, A
R6, A @RW6+d8, A
NEG A,
AND
AND
OR
OR
R5 @RW5+d8
R5, A @RW5+d8, A
R5, A @RW5+d8, A
NEG A,
AND
AND
OR
OR
R4 @RW4+d8
R4, A @RW4+d8, A
R4, A @RW4+d8, A
NEG A,
AND
AND
OR
OR
R3 @RW3+d8
R3, A @RW3+d8, A
R3, A @RW3+d8, A
NEG A,
AND
AND
OR
OR
R2 @RW2+d8
R2, A @RW2+d8,A
R2, A @RW2+d8,A
NEG A,
AND
AND
OR
OR
R1 @RW1+d8
R1, A @RW1+d8, A
R1, A @RW1+d8, A
XOR
C0
NOT
NOT
@RW1 @RW1+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R6, A @RW6+d8, A
R6, A @RW6+d8, A
A, R6 @RW6+d8
ADD
B0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R5, A @RW5+d8, A
R5, A @RW5+d8, A
A, R5 @RW5+d8
ADD
A0
+9
ADD
SUB
SUB
SUBC
SUBC A, NEG
R4, A @RW4+d8, A
R4, A @RW4+d8, A
A, R4 @RW4+d8
ADD
90
NOT
NOT
@RW0 @RW0+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R3, A @RW3+d8, A
R3, A @RW3+d8, A
A, R3 @RW3+d8
ADD
80
NEG A,
AND
AND
OR
OR
R0 @RW0+d8
R0, A @RW0+d8, A
R0, A @RW0+d8, A
70
ADD
ADD
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R2, A @RW2+d8,A
R2, A @RW2+d8,A
A, R2 @RW2+d8
60
ADD
50
ADD
SUB
SUB
SUBC
SUBC A, NEG
R1, A @RW1+d8, A
R1, A @RW1+d8, A
A, R1 @RW1+d8
40
ADD
30
ADD
SUB
SUB
SUBC
SUBC A, NEG
R0, A @RW0+d8, A
R0, A @RW0+d8, A
A, R0 @RW0+d8
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-11 ea Instruction 6 (First Byte = 75H)
685
686
ADDW A, SUBW
ADDW
ADDCW
CMPW
ADDCW A, CMPW
ADDCW A,
ANDW
CMPW A, ANDW
CMPW A,
ORW
ORW
ANDW A, ORW
ANDW A,
ANDW A,
ORW
ORW
ORW
A,
A,
A, XORW
XORW A, DWBNZ
DWBNZ
+F A,@RW3+
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
addr 16 A,@RW3+ addr 16
A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr16 A,@RW3+
addr 16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r @PC+d16,r
SUBW A, ADDCW
SUBW A,
ANDW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW1+ @RW1+RW7 @RW1+, r @RW1+RW7,r
SUBW
ADDW A,
ADDW
CMPW A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
CMPW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW0+ @RW0+RW7 @RW0+, r @RW0+RW7,r
ADDCW A,
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ADDCW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW3 @RW3+d16 @RW3, r @RW3+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
SUBW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW2 @RW2+d16 @RW2, r @RW2+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
SUBW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW1 @RW1+d16 @RW1, r @RW1+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADDW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW0 @RW0+d16 @RW0, r @RW0+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
ADDW
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, r @RW7+d8,r
F0
+7
E0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, r @RW6+d8,r
D0
+6
C0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, r @RW5+d8,r
B0
+5
A0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, r @RW4+d8,r
90
+4
80
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, r @RW3+d8,r
70
+3
60
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, r @RW2+d8,r
50
+2
40
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, r @RW1+d8,r
30
+1
20
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, r @RW0+d8,r
10
+0
00
APPENDIX
Table B.9-12 ea Instruction 7 (First Byte = 76H)
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
@RW3 @RW3+d16
SUBW
SUBW
@RW3+, A addr16, A
ADDW
ADDW
@RW3+, A addr16, A
+F
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
ORW
ORW
@RW3+, A addr16, A
XORW
XORW
@RW3+, A addr16, A
NOTW
NOTW
@RW3+
addr16
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
@RW2+ @PC+d16
SUBW
SUBW
@RW2+, A @PC+d16,A
ADDW
ADDW
@RW2+, A @PC+d16,A
+E
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7
SUBCW
+D
SUBW
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7
SUBW
SUBCW
+C
ADDW
ADDW
SUBW
SUBCW A,
+B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
SUBW
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
@RW2 @RW2+d16
ADDW
ADDW
SUBW
+A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
SUBW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
@RW1 @RW1+d16
ADDW
ADDW
SUBCW A,
+9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
@RW0 @RW0+d16
SUBW
NOTW
NOTW
RW7 @RW7+d8
NOTW
NOTW
RW6 @RW6+d8
NOTW
NOTW
RW5 @RW5+d8
+8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
SUBW
XORW
XORW
RW7, A @RW7+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
A, RW7 @RW7+d8
RW7 @RW7+d8
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
+7
ADDW
XORW
XORW
RW6, A @RW6+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
A, RW6 @RW6+d8
RW6 @RW6+d8
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
+6
ADDW
XORW
XORW
RW5, A @RW5+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
A, RW5 @RW5+d8
RW5 @RW5+d8
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
+5
NOTW
NOTW
RW4 @RW4+d8
XORW
XORW
RW4, A @RW4+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
A, RW4 @RW4+d8
RW4 @RW4+d8
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
+4
F0
NOTW
NOTW
RW0 @RW0+d8
E0
NOTW
NOTW
RW3 @RW3+d8
D0
XORW
XORW
RW3, A @RW3+d8, A
C0
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
A, RW3 @RW3+d8
RW3 @RW3+d8
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
B0
+3
A0
NOTW
NOTW
RW2 @RW2+d8
90
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
A, RW2 @RW2+d8
RW2 @RW2+d8
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
80
+2
70
NOTW
NOTW
RW1 @RW1+d8
60
XORW
XORW
RW1, A @RW1+d8, A
50
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
A, RW1 @RW1+d8
RW1 @RW1+d8
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
40
+1
30
XORW
XORW
RW0, A @RW0+d8, A
20
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
A, RW0 @RW0+d8
RW0 @RW0+d8
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
10
+0
00
APPENDIX B Instructions
Table B.9-13 ea Instruction 8 (First Byte = 77H)
687
688
DIV
DIV
A, DIVW
DIVW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
DIV
DIV
A, DIVW
DIVW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW MULUW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MULU
MULU A, MULUW MULUW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MULU
MULU A, MULUW MULUW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
+9
+A
+B
+C
+D
+E
+F A, @RW3+
MULU
DIV
DIV
A, DIVW
DIVW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
addr16 A,@RW3+ addr16
A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
A, DIVW
DIVW A,
addr16 A,@RW3+
addr16
DIV
DIV
A, DIVW
DIVW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
F0
+7
E0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
D0
+6
C0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
B0
+5
A0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
90
+4
80
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
70
+3
60
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
50
+2
40
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
30
+1
20
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
10
+0
00
APPENDIX
Table B.9-14 ea Instruction 9 (First Byte = 78H)
MOVEA
MOVEA RW1
RW1,RW4 ,@RW4+d8
MOVEA
MOVEA RW1
RW1,RW5 ,@RW5+d8
MOVEA
MOVEA RW1
RW1,RW6 ,@RW6+d8
MOVEA
MOVEA RW1
RW1,RW7 ,@RW7+d8
MOVEA
MOVEA RW1
RW1,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,@RW1 ,@RW1+d16
MOVEA
MOVEA RW1
RW1,@RW2 ,@RW2+d16
MOVEA
MOVEA RW1
RW1,@RW3 ,@RW3+d16
MOVEA
MOVEA RW0
RW0,RW4 ,@RW4+d8
MOVEA
MOVEA RW0
RW0,RW5 ,@RW5+d8
MOVEA
MOVEA RW0
RW0,RW6 ,@RW6+d8
MOVEA
MOVEA RW0
RW0,RW7 ,@RW7+d8
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
+4
+5
+6
+7
50
70
90
B0
C0
D0
F0
MOVEA
MOVEA RW3
RW3,@RW2+ ,@PC+d16
MOVEA
MOVEA RW4
RW4,@RW2+ ,@PC+d16
MOVEA
MOVEA RW7
RW7,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
RW6,@RW3+ RW6, addr16 RW7@RW3+ RW7, addr16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2+ ,@PC+d16
RW6,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16
MOVEA
MOVEA RW2
RW2,@RW2+ ,@PC+d16
+F
MOVEA
MOVEA RW1
RW1,@RW2+ ,@PC+d16
MOVEA
MOVEA RW0
RW0,@RW2+ ,@PC+d16
MOVEA RW1
+E
MOVEA
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW1+ ,@RW1+RW7 RW6,@RW1+ ,@RW1+RW7 RW7,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW7
RW7,@RW3 ,@RW3+d16
MOVEA
MOVEA RW7
RW7,@RW2 ,@RW2+d16
MOVEA
MOVEA RW7
RW7,@RW1 ,@RW1+d16
MOVEA
MOVEA RW7
RW7,@RW0 ,@RW0+d16
MOVEA
MOVEA RW7
RW7,RW7 ,@RW7+d8
MOVEA
MOVEA RW7
RW7,RW6 ,@RW6+d8
MOVEA
MOVEA RW7
RW7,RW5 ,@RW5+d8
MOVEA
MOVEA RW7
RW7,RW4 ,@RW4+d8
MOVEA
MOVEA RW7
RW7,RW3 ,@RW3+d8
MOVEA
MOVEA RW7
RW7,RW2 ,@RW2+d8
MOVEA
MOVEA RW7
RW7,RW1 ,@RW1+d8
MOVEA
MOVEA RW7
RW7,RW0 ,@RW0+d8
E0
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW1+ ,@RW1+RW7 RW3,@RW1+ ,@RW1+RW7 RW4,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW3 ,@RW3+d16 RW6,@RW3 ,@RW3+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2 ,@RW2+d16 RW6,@RW2 ,@RW2+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW1 ,@RW1+d16 RW6,@RW1 ,@RW1+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW0 ,@RW0+d16 RW6,@RW0 ,@RW0+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW7 ,@RW7+d8
RW6,RW7 ,@RW7+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW6 ,@RW6+d8
RW6,RW6 ,@RW6+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW5 ,@RW5+d8
RW6,RW5 ,@RW5+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW4 ,@RW4+d8
RW6,RW4 ,@RW4+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW3 ,@RW3+d8
RW6,RW3 ,@RW3+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW2 ,@RW2+d8
RW6,RW2 ,@RW2+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW1 ,@RW1+d8
RW6,RW1 ,@RW1+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW0 ,@RW0+d8
RW6,RW0 ,@RW0+d8
A0
+D RW0,@RW1+ ,@RW1+RW7 RW1,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW4
RW4,@RW3 ,@RW3+d16
MOVEA
MOVEA RW4
RW4,@RW2 ,@RW2+d16
MOVEA
MOVEA RW4
RW4,@RW1 ,@RW1+d16
MOVEA
MOVEA RW4
RW4,@RW0 ,@RW0+d16
MOVEA
MOVEA RW4
RW4,RW7 ,@RW7+d8
MOVEA
MOVEA RW4
RW4,RW6 ,@RW6+d8
MOVEA
MOVEA RW4
RW4,RW5 ,@RW5+d8
MOVEA
MOVEA RW4
RW4,RW4 ,@RW4+d8
MOVEA
MOVEA RW4
RW4,RW3 ,@RW3+d8
MOVEA
MOVEA RW4
RW4,RW2 ,@RW2+d8
MOVEA
MOVEA RW4
RW4,RW1 ,@RW1+d8
MOVEA
MOVEA RW4
RW4,RW0 ,@RW0+d8
80
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW0+ ,@RW0+RW7 RW6,@RW0+ ,@RW0+RW7 RW7,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW3
RW3,@RW3 ,@RW3+d16
MOVEA
MOVEA RW3
RW3,@RW2 ,@RW2+d16
MOVEA
MOVEA RW3
RW3,@RW1 ,@RW1+d16
MOVEA
MOVEA RW3
RW3,@RW0 ,@RW0+d16
MOVEA
MOVEA RW3
RW3,RW7 ,@RW7+d8
MOVEA
MOVEA RW3
RW3,RW6 ,@RW6+d8
MOVEA
MOVEA RW3
RW3,RW5 ,@RW5+d8
MOVEA
MOVEA RW3
RW3,RW4 ,@RW4+d8
MOVEA
MOVEA RW3
RW3,RW3 ,@RW3+d8
MOVEA
MOVEA RW3
RW3,RW2 ,@RW2+d8
MOVEA
MOVEA RW3
RW3,RW1 ,@RW1+d8
MOVEA
MOVEA RW3
RW3,RW0 ,@RW0+d8
60
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW0+ ,@RW0+RW7 RW3,@RW0+ ,@RW0+RW7 RW4,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW2
RW2,@RW3 ,@RW3+d16
MOVEA
MOVEA RW2
RW2,@RW2 ,@RW2+d16
MOVEA
MOVEA RW2
RW2,@RW1 ,@RW1+d16
MOVEA
MOVEA RW2
RW2,@RW0 ,@RW0+d16
MOVEA
MOVEA RW2
RW2,RW7 ,@RW7+d8
MOVEA
MOVEA RW2
RW2,RW6 ,@RW6+d8
MOVEA
MOVEA RW2
RW2,RW5 ,@RW5+d8
MOVEA
MOVEA RW2
RW2,RW4 ,@RW4+d8
MOVEA
MOVEA RW2
RW2,RW3 ,@RW3+d8
MOVEA
MOVEA RW2
RW2,RW2 ,@RW2+d8
MOVEA
MOVEA RW2
RW2,RW1 ,@RW1+d8
MOVEA
MOVEA RW2
RW2,RW0 ,@RW0+d8
40
+C RW0,@RW0+ ,@RW0+RW7 RW1,@RW0+ ,@RW0+RW7
+B RW0,@RW3 ,@RW3+d16
+A RW0,@RW2 ,@RW2+d16
+9 RW0,@RW1 ,@RW1+d16
MOVEA RW1
MOVEA
MOVEA RW1
RW1,RW3 ,@RW3+d8
MOVEA
MOVEA RW0
RW0,RW3 ,@RW3+d8
+3
MOVEA
MOVEA
MOVEA RW1
RW1,RW2 ,@RW2+d8
MOVEA
MOVEA RW0
RW0,RW2 ,@RW2+d8
+2
+8 RW0,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,RW1 ,@RW1+d8
MOVEA
MOVEA RW0
RW0,RW1 ,@RW1+d8
+1
30
MOVEA
MOVEA RW1
RW1,RW0 ,@RW0+d8
20
MOVEA
MOVEA RW0
RW0,RW0 ,@RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79H)
689
690
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW3+
addr16 @RW3+
addr16
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16
@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX
Table B.9-16 MOV Ri, ea Instruction (First Byte = 7AH)
MOVW
MOVW RW5,
RW5,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4, MOVW
MOVW RW5, MOVW
MOVW RW6, MOVW
MOVW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, @RW2+ @PC+d16
RW2, @RW2+ @PC+d16
RW3, @RW2+ @PC+d16
RW4, @RW2+ @PC+d16
MOVW
MOVW
RW1, @RW3+ RW1, addr16
MOVW
RW0, @RW1+
MOVW
MOVW
RW0, @RW2+ @PC+d16
MOVW
MOVW
RW0, @RW3+ RW0, addr16
+9
+A
+B
+C
+D
+E
+F
MOVW
MOVW
RW2, @RW3+ RW2, addr16
MOVW
MOVW
RW3, @RW3+ RW3, addr16
MOVW
MOVW
RW5, @RW3+ RW5, addr16
MOVW
MOVW
RW5, @RW2+ @PC+d16
MOVW
MOVW
RW6, @RW3+ RW6, addr16
MOVW
MOVW RW6,
RW6, @RW2+ @PC+d16
MOVW
MOVW
RW7, @RW3+ RW7, addr16
MOVW
MOVW RW7,
RW7, @RW2+ @PC+d16
MOVW RW7,
@RW1+RW7
MOVW
MOVW RW7,
RW7,@RW3 @RW3+d16
MOVW
MOVW RW7,
RW7,@RW2 @RW2+d16
MOVW
MOVW RW7,
RW7,@RW1 @RW1+d16
MOVW
MOVW RW7,
RW7,@RW0 @RW0+d16
MOVW
MOVW RW7,
RW7, RW7 @RW7+d8
MOVW
MOVW RW7,
RW7, RW6 @RW6+d8
MOVW
MOVW RW7,
RW7, RW5 @RW5+d8
MOVW
MOVW RW7,
RW7, RW4 @RW4+d8
MOVW RW6, MOVW
@RW1+RW7 RW7, @RW1+
MOVW
MOVW RW6,
RW6,@RW3 @RW3+d16
MOVW
MOVW RW6,
RW6,@RW2 @RW2+d16
MOVW
MOVW RW6,
RW6,@RW1 @RW1+d16
MOVW
MOVW RW6,
RW6,@RW0 @RW0+d16
MOVW
MOVW RW6,
RW6, RW7 @RW7+d8
MOVW
MOVW RW6,
RW6, RW6 @RW6+d8
MOVW
MOVW RW6,
RW6, RW5 @RW5+d8
MOVW
MOVW RW6,
RW6, RW4 @RW4+d8
MOVW
MOVW
@RW1+RW7 RW6, @RW1+
MOVW
MOVW RW5,
RW5, RW6 @RW6+d8
MOVW
MOVW RW5,
RW5, RW5 @RW5+d8
MOVW RW4, MOVW
@RW1+RW7 RW5, @RW1+
MOVW
MOVW
RW4, @RW3+ RW4, addr16
MOVW RW3, MOVW
@RW1+RW7 RW4, @RW1+
MOVW
MOVW RW5,
RW5,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16
+8
MOVW RW2, MOVW
@RW1+RW7 RW3, @RW1+
MOVW
MOVW RW5,
RW5,@RW1 @RW1+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
MOVW
MOVW
RW0, RW7 @RW7+d8
+7
MOVW RW1, MOVW
@RW1+RW7 RW2, @RW1+
MOVW
MOVW RW5,
RW5,@RW0 @RW0+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
MOVW
MOVW
RW0, RW6 @RW6+d8
+6
MOVW
MOVW
@RW1+RW7 RW1, @RW1+
MOVW
MOVW RW5,
RW5, RW7 @RW7+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
MOVW
MOVW
RW0, RW5 @RW5+d8
+5
MOVW
MOVW RW5,
RW5, RW4 @RW4+d8
MOVW
MOVW RW7,
RW7, RW3 @RW3+d8
MOVW
MOVW RW7,
RW7, RW2 @RW2+d8
MOVW
MOVW RW7,
RW7, RW1 @RW1+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
MOVW
MOVW RW6,
RW6, RW3 @RW3+d8
MOVW
MOVW RW6,
RW6, RW2 @RW2+d8
MOVW
MOVW RW6,
RW6, RW1 @RW1+d8
MOVW
MOVW
RW0, RW4 @RW4+d8
MOVW
MOVW RW5,
RW5, RW3 @RW3+d8
MOVW
MOVW RW5,
RW5, RW2 @RW2+d8
MOVW
MOVW RW5,
RW5, RW1 @RW1+d8
+4
F0
MOVW
MOVW RW7,
RW7, RW0 @RW0+d8
E0
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
D0
MOVW
MOVW RW6,
RW6, RW0 @RW0+d8
C0
MOVW
MOVW
RW0, RW3 @RW3+d8
B0
MOVW
MOVW RW5,
RW5, RW0 @RW0+d8
A0
+3
90
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
80
MOVW
MOVW
RW0, RW2 @RW2+d8
70
+2
60
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
50
MOVW
MOVW
RW0, RW1 @RW1+d8
40
+1
30
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
20
MOVW
MOVW
RW0, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7BH)
691
692
+F
+E
+D
+C
+B
+A
+9
+8
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R1 addr16, R1
MOV
MOV
@RW3+, R0 addr16, R0
MOV
MOV
MOV
@RW2+, R1 @PC+d16, R1
@RW2+, R0 @PC+d16, R0
MOV
MOV
MOV
MOV
MOV
@RW0+, R1 @RW0+RW7, R1
MOV
@RW3, R1 @RW3+d16, R1
MOV
@RW2, R1 @RW2+d16, R1
MOV
@RW1, R1 @RW1+d16, R1
MOV
@RW1+, R1 @RW1+RW7, R1
MOV
MOV
@RW0, R1 @RW0+d16, R1
MOV
@RW1+, R0 @RW1+RW7, R0
MOV
@RW0+, R0 @RW0+RW7, R0
MOV
@RW3, R0 @RW3+d16, R0
MOV
@RW2, R0 @RW2+d16, R0
MOV
@RW1, R0 @RW1+d16, R0
MOV
@RW0, R0 @RW0+d16, R0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R2 addr16, R2
MOV
@RW2+, R2 @PC+d16, R2
MOV
@RW1+, R2 @RW1+RW7, R2
MOV
@RW0+, R2 @RW0+RW7, R2
MOV
@RW3, R2 @RW3+d16, R2
MOV
@RW2, R2 @RW2+d16, R2
MOV
@RW1, R2 @RW1+d16, R2
MOV
@RW0, R2 @RW0+d16, R2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R3 addr16, R3
MOV
@RW2+, R3 @PC+d16, R3
MOV
@RW1+, R3 @RW1+RW7, R3
MOV
@RW0+, R3 @RW0+RW7, R3
MOV
@RW3, R3 @RW3+d16, R3
MOV
@RW2, R3 @RW2+d16, R3
MOV
@RW1, R3 @RW1+d16, R3
MOV
@RW0, R3 @RW0+d16, R3
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R4 addr16, R4
MOV
@RW2+, R4 @PC+d16, R4
MOV
@RW1+, R4 @RW1+RW7, R4
MOV
@RW0+, R4 @RW0+RW7, R4
MOV
@RW3, R4 @RW3+d16, R4
MOV
@RW2, R4 @RW2+d16, R4
MOV
@RW1, R4 @RW1+d16, R4
MOV
@RW0, R4 @RW0+d16, R4
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R5 addr16, R5
MOV
@RW2+, R5 @PC+d16, R5
MOV
@RW1+, R5 @RW1+RW7, R5
MOV
@RW0+, R5 @RW0+RW7, R5
MOV
@RW3, R5 @RW3+d16, R5
MOV
@RW2, R5 @RW2+d16, R5
MOV
@RW1, R5 @RW1+d16, R5
MOV
@RW0, R5 @RW0+d16, R5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R6 addr16, R6
MOV
@RW2+, R6 @PC+d16, R6
MOV
@RW1+, R6 @RW1+RW7, R6
MOV
@RW0+, R6 @RW0+RW7, R6
MOV
@RW3, R6 @RW3+d16, R6
MOV
@RW2, R6 @RW2+d16, R6
MOV
@RW1, R6 @RW1+d16, R6
MOV
@RW0, R6 @RW0+d16,
R6
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R7 addr16, R7
MOV
@RW2+, R7 @PC+d16, R7
MOV
@RW1+, R7 @RW1+RW7, R7
MOV
@RW0+, R7 @RW0+RW7, R7
MOV
@RW3, R7 @RW3+d16, R7
MOV
@RW2, R7 @RW2+d16, R7
MOV
@RW1, R7 @RW1+d16, R7
MOV
@RW0, R7 @RW0+d16, R7
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R7, R0 @RW7+d8, R0
R7, R1 @RW7+d8, R1
R7, R2 @RW7+d8, R2
R7, R3 @RW7+d8, R3
R7, R4 @RW7+d8, R4
R7, R5 @RW7+d8, R5
R7, R6 @RW7+d8, R6
R7, R7 @RW7+d8, R7
F0
+7
E0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R6, R0 @RW6+d8, R0
R6, R1 @RW6+d8, R1
R6, R2 @RW6+d8, R2
R6, R3 @RW6+d8, R3
R6, R4 @RW6+d8, R4
R6, R5 @RW6+d8, R5
R6, R6 @RW6+d8, R6
R6, R7 @RW6+d8, R7
D0
+6
C0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R5, R0 @RW5+d8, R0
R5, R1 @RW5+d8, R1
R5, R2 @RW5+d8, R2
R5, R3 @RW5+d8, R3
R5, R4 @RW5+d8, R4
R5, R5 @RW5+d8, R5
R5, R6 @RW5+d8, R6
R5, R7 @RW5+d8, R7
B0
+5
A0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R4, R0 @RW4+d8, R0
R4, R1 @RW4+d8, R1
R4, R2 @RW4+d8, R2
R4, R3 @RW4+d8, R3
R4, R4 @RW4+d8, R4
R4, R5 @RW4+d8, R5
R4, R6 @RW4+d8, R6
R4, R7 @RW4+d8, R7
90
+4
80
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R3, R0 @RW3+d8, R0
R3, R1 @RW3+d8, R1
R3, R2 @RW3+d8, R2
R3, R3 @RW3+d8, R3
R3, R4 @RW3+d8, R4
R3, R5 @RW3+d8, R5
R3, R6 @RW3+d8, R6
R3, R7 @RW3+d8, R7
70
+3
60
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R2, R0 @RW2+d8, R0
R2, R1 @RW2+d8, R1
R2, R2 @RW2+d8, R2
R2, R3 @RW2+d8, R3
R2, R4 @RW2+d8, R4
R2, R5 @RW2+d8, R5
R2, R6 @RW2+d8, R6
R2, R7 @RW2+d8, R7
50
+2
40
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R1, R0 @RW1+d8, R0
R1, R1 @RW1+d8, R1
R1, R2 @RW1+d8, R2
R1, R3 @RW1+d8, R3
R1, R4 @RW1+d8, R4
R1, R5 @RW1+d8, R5
R1, R6 @RW1+d8, R6
R1, R7 @RW1+d8, R7
30
+1
20
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R0, R0 @RW0+d8, R0
R0, R1 @RW0+d8, R1
R0, R2 @RW0+d8, R2
R0, R3 @RW0+d8, R3
R0, R4 @RW0+d8, R4
R0, R5 @RW0+d8, R5
R0, R6 @RW0+d8, R6
R0, R7 @RW0+d8, R7
10
+0
00
APPENDIX
Table B.9-18 MOV ea, Ri Instruction (First Byte = 7CH)
MOVW
MOVW@RW2
@RW2, RW1 +d16, RW1
MOVW
MOVW@RW3
@RW3, RW1 +d16, RW1
MOVW
MOVW@RW0
@RW0+, RW1 +RW7,RW1
MOVW
MOVW@RW1
@RW1+,RW1 +RW7,RW1
MOVW
MOVW@PC
@RW2+,RW1 +d16, RW1
MOVW
MOVW
@RW3+,RW1 addr16, RW1
MOVW
MOVW@RW2
@RW2, RW0 +d16, RW0
MOVW
MOVW@RW3
@RW3, RW0 +d16, RW0
MOVW
MOVW@RW0
@RW0+,RW0 +RW7,RW0
MOVW
MOVW@RW1
@RW1+,RW0 +RW7,RW0
MOVW
MOVW@PC
@RW2+,RW0 +d16, RW0
MOVW
MOVW
@RW3+,RW0 addr16, RW0
+B
+C
+D
+E
+F
MOVW
MOVW
@RW3+,RW2 addr16, RW2
MOVW
MOVW@PC
@RW2+,RW2 +d16, RW2
MOVW
MOVW@RW1
@RW1+,RW2 +RW7,RW2
MOVW
MOVW@RW0
@RW0+,RW2 +RW7,RW2
MOVW
MOVW@RW3
@RW3, RW2 +d16, RW2
MOVW
MOVW@RW2
@RW2, RW2 +d16, RW2
MOVW
MOVW
@RW3+,RW3 addr16, RW3
MOVW
MOVW@PC
@RW2+,RW3 +d16, RW3
MOVW
MOVW@RW1
@RW1+,RW3 -+RW7,RW3
MOVW
MOVW@RW0
@RW0+,RW3 +RW7,RW3
MOVW
MOVW@RW3
@RW3, RW3 +d16, RW3
MOVW
MOVW@RW2
@RW2, RW3 +d16, RW3
MOVW
MOVW@RW1
@RW1, RW3 +d16, RW3
MOVW
MOVW
@RW3+,RW4 addr16, RW4
MOVW
MOVW@PC
@RW2+,RW4 +d16, RW4
MOVW
MOVW@RW1
@RW1+,RW4 +RW7,RW4
MOVW
MOVW@RW0
@RW0+,RW4 +RW7,RW4
MOVW
MOVW@RW3
@RW3, RW4 +d16, RW4
MOVW
MOVW@RW2
@RW2, RW4 +d16, RW4
MOVW
MOVW@RW1
@RW1, RW4 +d16, RW4
MOVW
MOVW
@RW3+,RW5 addr16, RW5
MOVW
MOVW@PC
@RW2+,RW5 +d16, RW5
MOVW
MOVW@RW1
@RW1+,RW5 +RW7,RW5
MOVW
MOVW@RW0
@RW0+,RW5 +RW7,RW5
MOVW
MOVW@RW3
@RW3, RW5 +d16, RW5
MOVW
MOVW@RW2
@RW2, RW5 +d16, RW5
MOVW
MOVW@RW1
@RW1, RW5 +d16, RW5
MOVW
MOVW
@RW3+,RW6 addr16, RW6
MOVW
MOVW @PC
@RW2+,RW6 +d16, RW6
MOVW
MOVW@RW1
@RW1+,RW6 +RW7,RW6
MOVW
MOVW@RW0
@RW0+,RW6 +RW7,RW6
MOVW
MOVW@RW3
@RW3, RW6 +d16, RW6
MOVW
MOVW@RW2
@RW2, RW6 +d16, RW6
MOVW
MOVW@RW1
@RW1, RW6 +d16, RW6
MOVW
MOVW
@RW3+,RW7 addr16, RW7
MOVW
MOVW@PC
@RW2+,RW7 +d16, RW7
MOVW
MOVW@RW1
@RW1+,RW7 +RW7,RW7
MOVW
MOVW@RW0
@RW0+,RW7 +RW7,RW7
MOVW
MOVW@RW3
@RW3, RW7 +d16, RW7
MOVW
MOVW@RW2
@RW2, RW7 +d16, RW7
MOVW
MOVW@RW1
@RW1, RW7 +d16, RW7
MOVW
MOVW@RW0
@RW0, RW7 +d16, RW7
+A
MOVW
MOVW@RW1
@RW1, RW2 +d16, RW2
MOVW
MOVW@RW0
@RW0, RW6 +d16, RW6
MOVW
MOVW@RW1
@RW1, RW1 +d16, RW1
MOVW
MOVW@RW0
@RW0, RW5 +d16, RW5
MOVW
MOVW@RW1
@RW1, RW0 +d16, RW0
MOVW
MOVW@RW0
@RW0, RW4 +d16, RW4
+9
MOVW
MOVW@RW0
@RW0, RW3 +d16, RW3
MOVW
MOVW@RW0
@RW0, RW1 +d16, RW1
MOVW
MOVW@RW0
@RW0, RW0 +d16, RW0
+8
MOVW
MOVW@RW0
@RW0, RW2 +d16, RW2
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW7, RW0 @RW7+d8, RW0
RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7
F0
+7
E0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW6, RW0 @RW6+d8, RW0
RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7
D0
+6
C0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW5, RW0 @RW5+d8, RW0
RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7
B0
+5
A0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW4, RW0 @RW4+d8, RW0
RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7
90
+4
80
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW3, RW0 @RW3+d8, RW0
RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7
70
+3
60
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW2, RW0 @RW2+d8, RW0
RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7
50
+2
40
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW1, RW0 @RW1+d8, RW0
RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7
30
+1
20
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW0, RW0 @RW0+d8, RW0
RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7
10
+0
00
APPENDIX B Instructions
Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH)
693
694
XCH
XCH
XCH
XCH
R1,
XCH
XCH R1,
R1,@RW2 W2+d16, A
XCH
XCH
R2,
XCH
XCH R2,
R2,@RW2 W2+d16, A
XCH
XCH
R3,
XCH
XCH R3,
R3,@RW2 W2+d16, A
XCH
XCH
R4,
XCH
XCH R4,
R4,@RW2 W2+d16, A
XCH
XCH
R5,
XCH
XCH R5,
R5,@RW2 W2+d16, A
XCH
XCH
R6,
XCH
XCH R6,
R6,@RW2 W2+d16, A
XCH
XCH
R7,
XCH
XCH R7,
R7,@RW2 W2+d16, A
XCH
XCH
XCH
XCH
XCH
R1, XCH
XCH
R2, XCH
XCH
R3, XCH
XCH
R4, XCH
XCH
R5, XCH
XCH
R6, XCH
XCH
R7,
+F R0,@RW3+ R0, addr16
XCH
XCH
R1,@RW3+ R1, addr16
XCH
XCH
R2,@RW3+ R2, addr16
XCH
XCH
R3,@RW3+ R3, addr16
XCH
XCH
R4,@RW3+ R4, addr16
XCH
XCH
R5,@RW3+ R5, addr16
XCH
XCH
R6,@RW3+ R6, addr16
XCH
XCH
R7,@RW3+ R7, addr16
+E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16
R0, XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7
+D R0,@RW1+
XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7
XCH
+C R0,@RW0+
+B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
R0,
+A R0,@RW2 W2+d16, A
R0,
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
+9
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
+8
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
F0
+7
E0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX
Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH)
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2+ @PC+d16
RW1,@RW2+ @PC+d16
RW2,@RW2+ @PC+d16
RW3,@RW2+ @PC+d16
RW4,@RW2+ @PC+d16
RW5,@RW2+ @PC+d16
RW6,@RW2+ @PC+d16
RW7,@RW2+ @PC+d16
XCHW
XCHW
RW0,@RW3+ RW0, addr16
+E
+F
XCHW
XCHW
RW7,@RW3+ RW7, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1+ @RW1+RW7 RW1,@RW1+ @RW1+RW7 RW2,@RW1+ @RW1+RW7 RW3,@RW1+ @RW1+RW7 RW4,@RW1+ @RW1+RW7 RW5,@RW1+ @RW1+RW7 RW6,@RW1+ @RW1+RW7 RW7,@RW1+ @RW1+RW7
+D
XCHW
XCHW
RW6,@RW3+ RW6, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
+C
XCHW
XCHW
RW5,@RW3+ RW5, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW3 @RW3+d16
RW1,@RW3 @RW3+d16
RW2,@RW3 @RW3+d16
RW3,@RW3 @RW3+d16
RW4,@RW3 @RW3+d16
RW5,@RW3 @RW3+d16
RW6,@RW3 @RW3+d16
RW7,@RW3 @RW3+d16
+B
XCHW
XCHW
RW4,@RW3+ RW4, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2 @RW2+d16
RW1,@RW2 @RW2+d16
RW2,@RW2 @RW2+d16
RW3,@RW2 @RW2+d16
RW4,@RW2 @RW2+d16
RW5,@RW2 @RW2+d16
RW6,@RW2 @RW2+d16
RW7,@RW2 @RW2+d16
+A
XCHW
XCHW
RW3,@RW3+ RW3, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1 @RW1+d16
RW1,@RW1 @RW1+d16
RW2,@RW1 @RW1+d16
RW3,@RW1 @RW1+d16
RW4,@RW1 @RW1+d16
RW5,@RW1 @RW1+d16
RW6,@RW1 @RW1+d16
RW7,@RW1 @RW1+d16
+9
XCHW
XCHW
RW2,@RW3+ RW2, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0 @RW0+d16
RW1,@RW0 @RW0+d16
RW2,@RW0 @RW0+d16
RW3,@RW0 @RW0+d16
RW4,@RW0 @RW0+d16
RW5,@RW0 @RW0+d16
RW6,@RW0 @RW0+d16
RW7,@RW0 @RW0+d16
+8
XCHW
XCHW
RW1,@RW3+ RW1, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW7 @RW7+d8
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
RW5, RW7 @RW7+d8
RW6, RW7 @RW7+d8
RW7, RW7 @RW7+d8
F0
+7
E0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW6 @RW6+d8
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
RW5, RW6 @RW6+d8
RW6, RW6 @RW6+d8
RW7, RW6 @RW6+d8
D0
+6
C0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW5 @RW5+d8
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
RW5, RW5 @RW5+d8
RW6, RW5 @RW5+d8
RW7, RW5 @RW5+d8
B0
+5
A0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW4 @RW4+d8
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
RW5, RW4 @RW4+d8
RW6, RW4 @RW4+d8
RW7, RW4 @RW4+d8
90
+4
80
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW3 @RW3+d8
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
RW5, RW3 @RW3+d8
RW6, RW3 @RW3+d8
RW7, RW3 @RW3+d8
70
+3
60
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW2 @RW2+d8
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
RW5, RW2 @RW2+d8
RW6, RW2 @RW2+d8
RW7, RW2 @RW2+d8
50
+2
40
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW1 @RW1+d8
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
RW5, RW1 @RW1+d8
RW6, RW1 @RW1+d8
RW7, RW1 @RW1+d8
30
+1
20
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW0 @RW0+d8
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
RW5, RW0 @RW0+d8
RW6, RW0 @RW0+d8
RW7, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7FH)
695
APPENDIX
696
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
697
INDEX
Index
Numerics
1024K Bit Flash Memory
Characteristics of the 512K/1024K Bit Flash Memory
.......................................................... 588
16-bit Free-run TImer
Block Diagram of 16-bit Free-run TImer ............ 283
16-bit Free-run Timer
16-bit Free-run Timer (×1) ................................ 280
16-bit Free-run Timer Interrupts ........................ 320
16-bit Free-run Timer Interrupts and EI2OS ........ 320
16-bit Free-run Timer Registers ......................... 289
Sample Program for 16-bit Free-run Timer ......... 351
Usage Notes on the 16-bit Free-run Timer .......... 349
16-bit Input Capture
16-bit Input Capture (×4) .................................. 281
16-bit Input Capture Input Timing ..................... 338
16-bit Input Capture Interrupts........................... 322
16-bit Input Capture Interrupts and EI2OS .......... 322
16-bit Input Capture Operation .......................... 337
Block Diagram of 16-bit Input Capture............... 284
Usage Notes on the 16-bit Input Capture ............ 350
16-bit Output Compare
16-bit Output Compare (×6) .............................. 280
16-bit Output Compare Interrupts ...................... 321
16-bit Output Compare Interrupts and EI2OS ...... 321
16-bit Output Compare Operation ...................... 332
16-bit Output Compare Registers ....................... 290
16-bit Output Compare Timing.......................... 336
Block Diagram of 16-bit Output Compare .......... 284
Sample Program for 16-bit Output Compare ....... 352
Usage Notes on the 16-bit Output Compare ........ 349
16-bit PPG Timer
16-bit PPG Timer (×1) ...................................... 281
16-bit PPG Timer (×3,PPG1 is not present in
MB90465 Series) ................................ 258
16-bit PPG Timer Interrupts .............................. 271
16-bit PPG Timer Interrupts and EI2OS.............. 272
16-bit PPG Timer Pins ...................................... 260
16-bit PPG Timer Registers............................... 262
Block Diagram of 16-bit PPG Timer .................. 259
Block Diagram of the 16-bit PPG Timer Pins...... 260
EI2OS Function of the 16-bit PPG Timer............ 272
Sample Program for the 16-bit PPG Timer.......... 277
Usage Notes on the 16-bit PPG Timer ................ 276
16-bit Reload Register
16-bit Reload Register (TMRD0/TMRD1).......... 242
16-bit Reload Timer
16-bit Reload Timer Interrupts........................... 243
16-bit Reload Timer Interrupts and EI2OS .......... 243
16-bit Reload Timer Interrupts and EI2OS .......... 232
698
16-bit Reload Timer Pins .................................. 235
16-bit Reload Timer Registers........................... 236
16-bit Reload Timer Settings............................. 244
Baud Rates determined using the Internal Timer
(16-bit Reload Timer 0) ....................... 495
Block Diagram of the 16-bit Reload Timer ......... 233
Block Diagram of the 16-bit Reload Timer Pins
......................................................... 235
EI2OS Function of the 16-bit Reload Timer ........ 243
Overview of the 16-bit Reload Timer................. 230
Usage Notes on the 16-bit Reload Timer ............ 252
16-bit Timer
16-bit Timer Buffer Operation Timing Diagram
......................................................... 427
16-bit Timer in Multi-pulse Generator Operation
Diagram ............................................. 428
16-bit Timer Operation ..................................... 425
16-bit Timer Timing......................................... 426
Block Diagram of 16-bit Timer ......................... 363
PPG0 Output Pulse from Rising Edge of RT to 16-bit
Timer Underflow (DTCR0/DTCR1/
DTCR2:TMD2 to TMD0=010B) .......... 342
The Use of the 16-bit Timer in Multi-pulse Generator
......................................................... 428
Usage Notes on the 16-bit Timer ....................... 430
16-bit Timer Buffer Operation Timing Diagram
16-bit Timer Buffer Operation Timing Diagram
......................................................... 427
16-bit Timer Control Register
16-bit Timer Control Register (DTCR0/DTCR2)
......................................................... 314
16-bit Timer Control Register (DTCR1)............. 316
16-bit Timer Register
16-bit Timer Register (TMR0/TMR1)................ 241
16-bit Timer Registers
16-bit Timer Registers (TMRR0/TMRR1/TMRR2)
......................................................... 313
24-bit Operand
Linear Addressing by 24-bit Operand Specification
........................................................... 34
512K
Characteristics of the 512K/1024K Bit Flash Memory
......................................................... 588
512K Bit Flash Memory
Programming Example Using 512K Bit Flash
Memory ............................................. 610
8/10-bit A/D Converter
8/10-bit A/D Converter Interrupts...................... 556
8/10-bit A/D Converter Interrupts and EI2OS
................................................. 543, 556
INDEX
8/10-bit A/D Converter Pins.............................. 546
8/10-bit A/D Converter Registers ...................... 548
Block Diagram of the 8/10-bit A/D Converter..... 544
Block Diagrams of the 8/10-bit A/D Converter Pins
.......................................................... 546
EI2OS Function of the 8/10-bit A/D Converter
.......................................................... 556
Functions of the 8/10-bit A/D Converter ............ 542
Usage Notes on the 8/10-bit A/D Converter........ 563
A
A
Accumulator (A) ................................................42
A/D Control Status Register
A/D Control Status Register 0 (ADCS0) .............551
A/D Control Status Register 1 (ADCS1) .............549
A/D Conversion
A/D Conversion Data Protection Function ..........561
A/D Converter
8/10-bit A/D Converter Interrupts ......................556
8/10-bit A/D Converter Interrupts and EI2OS
..................................................543, 556
8/10-bit A/D Converter Pins ..............................546
8/10-bit A/D Converter Registers .......................548
Block Diagram of the 8/10-bit A/D Converter
..........................................................544
Block Diagrams of the 8/10-bit A/D Converter Pins
..........................................................546
EI2OS Function of the 8/10-bit A/D Converter
..........................................................556
Functions of the 8/10-bit A/D Converter .............542
Usage Notes on the 8/10-bit A/D Converter ........563
A/D Data Register
A/D Data Register (ADCR0/ADCR1) ................554
Access Space
Bank Registers and Access Space.........................35
Accumulator
Accumulator (A) ................................................42
ADB
Bank Registers (PCB,DTB,USB,SSB,ADB) .........54
Bank Select Prefixes (PCB,DTB,ADB,SPB) .........58
ADCR
A/D Data Register (ADCR0/ADCR1) ................554
ADCS
A/D Control Status Register 0 (ADCS0) .............551
A/D Control Status Register 1 (ADCS1) .............549
Addressing
Addressing.......................................................637
Addressing by Indirect Specification with a 32-bit
............................................................34
Bank Addressing and Default Space .....................36
Direct Addressing .............................................639
Indirect Addressing...........................................645
Linear Addressing and Bank Addressing...............33
Linear Addressing by 24-bit Operand Specification
............................................................34
Assignment
DIP-64P-M01 Pin Assignment.............................10
FPT-64P-M06 Pin Assignment ..............................8
FPT-64P-M09 Pin Assignment ..............................9
Asynchronous Mode
Operation in Asynchronous Mode ......................500
699
INDEX
B
Bank Addressing
Bank Addressing and Default Space..................... 36
Linear Addressing and Bank Addressing .............. 33
Bank Registers
Bank Registers (PCB,DTB,USB,SSB,ADB) ......... 54
Bank Registers and Access Space ........................ 35
Bank Select Prefixes
Bank Select Prefixes (PCB,DTB,ADB,SPB) ......... 58
BAP
Buffer Address Pointer (BAP) ........................... 143
Baud Rate
UART Baud Rate Selection............................... 490
Baud Rates
Baud Rates determined using the Dedicated Baud Rate
Generator ........................................... 492
Baud Rates determined using the External Clock
.......................................................... 497
Baud Rates determined using the Internal Timer
(16-bit Reload Timer 0) ....................... 495
Bidirectional Communication
Bidirectional Communication Function .............. 504
Bit Flash Memory
Characteristics of the 512K/1024K Bit Flash Memory
.......................................................... 588
Block Diagram
Block Diagram of 16-bit Free-run TImer ............ 283
Block Diagram of 16-bit Input Capture............... 284
Block Diagram of 16-bit Output Compare .......... 284
Block Diagram of 16-bit PPG Timer .................. 259
Block Diagram of 16-bit Timer.......................... 363
Block Diagram of Data Write Control Unit ......... 364
Block Diagram of Multi-functional Timer .......... 282
Block Diagram of Multi-functional Timer Pins
.......................................................... 287
Block Diagram of Multi-pulse Generator............ 359
Block Diagram of Multi-pulse Generator Pins
...................