hm91230-cm71-10118-1e.pdf

FUJITSU SEMICONDUCTOR
CM71-10118-1E
CONTROLLER MANUAL
FR60Lite
32-BIT MICROCONTROLLER
MB90230 Series
User’s Manual
FR60Lite
32-BIT MICROCONTROLLER
MB90230 Series
User’s Manual
FUJITSU LIMITED
CONTENTS
■ Objectives and intended reader
■ Trademarks
■ Organization of this manual
This manual consists of the following 22 chapters and 1 appendices:
CHAPTER 1 Overview
This chapter describes the features and basic specifications of MB90520A series.
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The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely
for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not
warrant proper operation of the device with respect to use based on such information. When you develop equipment
incorporating the device based on such information, you must assume any responsibility arising out of such use of the
information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as
license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of
Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party' s intellectual property right or other
right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other
rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use
requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection
with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for
export of those products from Japan.
©2004 FUJITSU LIMITED Printed in Japan
ii
TOC
Chapter 1
1.
2.
3.
4.
How to Handle the Device .....................................................................................................
Instruction for Use..................................................................................................................
Caution: debug-related matters .............................................................................................
How to Use This Document ...................................................................................................
Chapter 2
1.
2.
2.1
2.2
3.
4.
5.
5.1
5.2
6.
7.
8.
1.
2.
3.
4.
5.
6.
7.
8.
9.
25
29
32
38
40
43
FR60Lite Architecture....................................................................... 45
Overview..............................................................................................................................
Features ..............................................................................................................................
CPU .....................................................................................................................................
32-bit/16-bit Bus Converter..................................................................................................
Harvard/Princeton Bus Converter........................................................................................
Instruction Overview ............................................................................................................
Data Structure......................................................................................................................
Word Alignment ...................................................................................................................
Addressing...........................................................................................................................
Chapter 5
11
11
11
12
13
14
15
15
15
16
17
20
Basic Information.............................................................................. 25
Pin Function List ..................................................................................................................
I/O Circuit Type....................................................................................................................
I/O Map ................................................................................................................................
Interrupt Vector Table ..........................................................................................................
Terminal state table according to mode...............................................................................
Notes ...................................................................................................................................
Chapter 4
1
3
6
7
MB91230 Overview ........................................................................... 11
Overview..............................................................................................................................
Features ..............................................................................................................................
FR60Lite CPU Core...................................................................................................
Peripheral Function ...................................................................................................
Model Configuration.............................................................................................................
Block Diagram .....................................................................................................................
CPU .....................................................................................................................................
General-purpose Register .........................................................................................
Dedicated Register List .............................................................................................
Memory Map........................................................................................................................
Pin Assignment Diagram .....................................................................................................
Package...............................................................................................................................
Chapter 3
1.
2.
3.
4.
5.
6.
Introduction ......................................................................................... 1
45
46
47
47
47
48
49
50
51
Register (CPU)................................................................................... 53
1.
General-purpose Register ................................................................................................... 53
2.
Dedicated Register .............................................................................................................. 53
2.1
PC: Program Counter ................................................................................................ 54
iii
2.2
2.3
2.4
2.5
2.6
2.7
PS: Program Status Register ....................................................................................
TBR: Table-base Register .........................................................................................
RP: Return Pointer ....................................................................................................
SSP: System Stack Pointer .......................................................................................
USP: User Stack Pointer ...........................................................................................
MDH, MDL: Multiply & Divide Register......................................................................
Chapter 6
1.
2.
3.
4.
5.
6.
7.
8.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
9.
1.
2.
3.
3.1
3.2
3.3
3.4
4.
4.1
4.2
4.3
4.4
5.
6.
EIT: Exceptions, Interrupts, and Traps ........................................... 61
Overview..............................................................................................................................
Features ..............................................................................................................................
EIT Trigger...........................................................................................................................
Return from EIT ...................................................................................................................
EIT Interrupt Level ...............................................................................................................
EIT Vector Table..................................................................................................................
Multiple EIT Processing .......................................................................................................
Operation .............................................................................................................................
User Interrupt operation.............................................................................................
Operation of INT Instruction ......................................................................................
Operation of INTE Instruction ....................................................................................
Operation of Step Trace Trap....................................................................................
Operation of Undefined-instruction Exception ...........................................................
Coprocessor Absent Trap..........................................................................................
Coprocessor Error Trap.............................................................................................
Operation of RETI Instruction ....................................................................................
Caution ................................................................................................................................
Chapter 7
61
61
61
61
62
62
63
65
65
66
66
67
67
68
68
68
68
Branch Instruction ............................................................................ 69
Branch Instruction with Delay Slot .......................................................................................
Operation of Branch Instruction with Delay Slot ..................................................................
Actual Example (with Delay Slot).........................................................................................
JMP:D @Ri / CALL:D @Ri Instruction ......................................................................
RET:D Instruction ......................................................................................................
Bcc:D rel Instruction ..................................................................................................
CALL:D Instruction ....................................................................................................
Restrictions on Branch Instruction with Delay Slot ..............................................................
Available Instructions for Delay Slot ..........................................................................
Step Trace Trap ........................................................................................................
Interrupt .....................................................................................................................
Undefined-instruction Exception................................................................................
Branch Instruction without Delay Slot ..................................................................................
Operation of Branch Instruction without Delay Slot .............................................................
Chapter 8
54
58
58
58
59
60
69
69
70
70
70
70
70
71
71
71
71
71
72
72
Status Transition of Device.............................................................. 73
1.
Overview.............................................................................................................................. 73
2.
Features .............................................................................................................................. 73
3.
Status Transition Diagram ................................................................................................... 74
3.1
RUN (Normal Operation) ........................................................................................... 75
3.2
Sleep ......................................................................................................................... 75
iv
3.3
3.4
3.5
3.6
3.7
3.8
Stop ...........................................................................................................................
Oscillation-stabilization-wait RUN..............................................................................
Oscillation-stabilization-wait Reset ............................................................................
Operation-initialization Reset (RST) ..........................................................................
Setting-initialization Reset (INIT) ...............................................................................
Priority of Each Request of Status Transition............................................................
Chapter 9
1.
2.
3.
4.
4.1
4.2
4.3
4.4
4.5
5.
5.1
5.2
5.3
5.4
5.5
5.6
6.
6.1
6.2
6.3
6.4
6.5
6.6
7.
7.1
7.2
7.3
7.4
7.5
7.6
8.
8.1
8.2
9.
9.1
10.
11.
75
75
76
76
76
76
Reset .................................................................................................. 77
Overview..............................................................................................................................
Features ..............................................................................................................................
Configuration .......................................................................................................................
Registers..............................................................................................................................
RSRR: Reset Cause Register ...................................................................................
STCR: Standby Control Register...............................................................................
MOD: Mode Pins .......................................................................................................
Mode Vector ..............................................................................................................
Reset Vector..............................................................................................................
INIT Pin Input (INIT: Settings Initialization Reset) ..............................................................
Trigger .......................................................................................................................
Releasing the Reset Request....................................................................................
Flag ...........................................................................................................................
Reset Level ...............................................................................................................
Initialization Triggered by INIT Pin Input (INIT) .........................................................
Reset Cancellation Sequence ...................................................................................
Watchdog Reset (INIT: Settings Initialization Reset)...........................................................
Trigger .......................................................................................................................
Releasing the Reset Request....................................................................................
Flag ...........................................................................................................................
Reset Level ...............................................................................................................
Initialization Triggered by Watchdog Reset (INIT).....................................................
Reset Cancellation Sequence ...................................................................................
Software Reset (RST: Operation Initialization Reset).........................................................
Trigger .......................................................................................................................
Releasing the Reset Request....................................................................................
Flag ...........................................................................................................................
Reset Level ...............................................................................................................
Items Initialized by Operation Reset (RST) ...............................................................
Reset Cancellation Sequence ...................................................................................
Reset Operation Modes.......................................................................................................
Normal (Asynchronous) Reset Mode ........................................................................
Synchronous Reset Operation ..................................................................................
MCU Operation Mode..........................................................................................................
Bus Modes and Access Modes .................................................................................
Sample Program..................................................................................................................
Cautions ..............................................................................................................................
77
77
78
79
79
80
81
81
82
83
83
83
83
83
83
84
85
85
85
85
85
85
85
86
86
86
86
86
86
86
87
87
87
88
88
89
90
Chapter 10 Standby.............................................................................................. 91
1.
Overview.............................................................................................................................. 91
v
2.
3.
4.
4.1
4.2
5.
5.1
5.2
6.
7.
7.1
7.2
7.3
7.4
7.5
7.6
8.
9.
Features .............................................................................................................................. 91
Configuration ....................................................................................................................... 92
Registers.............................................................................................................................. 93
STCR: Standby Control Register............................................................................... 93
..................................................................... TBCR: Timebase timer control register 94
Operation ............................................................................................................................. 95
Sleep Mode ............................................................................................................... 95
Stop mode ................................................................................................................. 96
Settings................................................................................................................................ 97
Q&A ..................................................................................................................................... 97
How do I change to sleep mode? .............................................................................. 97
How do I change to stop mode?................................................................................ 98
How do I set pins to high impedance (Hi-z) during stop mode? ................................ 98
How do I halt the main clock oscillation during stop mode? ...................................... 98
How do I recover from sleep mode?.......................................................................... 98
How do I recover from stop mode? ........................................................................... 99
Sample Programs .............................................................................................................. 100
Cautions ............................................................................................................................ 102
Chapter 11 Clock Control .................................................................................. 103
1.
2.
3.
4.
4.1
4.2
4.3
4.4
5.
5.1
5.2
5.3
6.
7.
7.1
7.2
7.3
7.4
7.5
7.6
8.
9.
Overview............................................................................................................................ 103
Features ............................................................................................................................ 103
Configuration ..................................................................................................................... 104
Registers............................................................................................................................ 105
CLKR: Clock Source Control Register..................................................................... 105
DIV0: Clock Division Setting Register 0 .................................................................. 107
DIV1: Clock Division Setting Register 1 .................................................................. 108
OSCCR: Oscillation Control Register ...................................................................... 109
Operation ........................................................................................................................... 110
Clock Setup Sequence (Example)........................................................................... 110
Halting and Restarting the Main Clock Oscillation During Subclock Mode (Example) ...
110
Notes ....................................................................................................................... 111
Settings.............................................................................................................................. 112
Q & A ................................................................................................................................. 113
How do I enable or disable clock operation?........................................................... 113
How do I select the main PLL multiplier ratio? ........................................................ 113
How do I select the operating clock source? ........................................................... 113
How do I set the operation clock divide ratios? ....................................................... 114
How do I halt the main clock in subclock mode?..................................................... 115
How do I halt the subclock in main clock mode?..................................................... 115
Sample Programs .............................................................................................................. 116
Cautions ............................................................................................................................ 118
Chapter 12 Timebase Counter........................................................................... 119
1.
Overview............................................................................................................................ 119
2.
Features ............................................................................................................................ 119
2.1
Timebase Counter (when used to generate the oscillation stabilization wait) ......... 119
vi
2.2
Events that Invoke an Oscillation Stabilization Wait................................................ 119
3.
Configuration ..................................................................................................................... 120
4.
Registers............................................................................................................................ 121
4.1
STCR: Standby Control Register............................................................................. 121
4.2
CLKR: Clock Source Control Register..................................................................... 122
5.
Operation ........................................................................................................................... 123
5.1
INIT Pin Input .......................................................................................................... 123
5.2
Watchdog Reset (The specified oscillation stabilization wait time is generated
automatically) 124
5.3
Recovering from Stop Mode via an Interrupt........................................................... 125
5.4
The lock wait time for the main PLL must be generated by software. ..................... 126
5.5
Generating an Oscillation Stabilization Wait when Changing from Subclock Mode to
Main Clock Mode 126
5.6
When Recovering from an Abnormal State with the Main PLL Selected ................ 126
5.7
Types of Oscillation Stabilization Wait..................................................................... 127
5.8
Whether or not a Stabilization Wait is Required for Each State Transition ............. 128
6.
Settings.............................................................................................................................. 129
7.
Q&A ................................................................................................................................... 130
7.1
How do I setup the oscillation stabilization wait time that is generated automatically? ..
130
7.2
How do I set the oscillation stabilization wait time without generating it automatically?.
131
7.3
What is the clear timing for the timebase counter? ................................................. 131
8.
Sample Program................................................................................................................ 132
9.
Cautions ............................................................................................................................ 133
Chapter 13 Timebase Timer............................................................................... 135
1.
2.
3.
4.
4.1
4.2
5.
5.1
6.
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8.
9.
Overview............................................................................................................................ 135
Features ............................................................................................................................ 135
Configuration ..................................................................................................................... 136
Register ............................................................................................................................. 137
TBCR: Timebase Timer Control Register............................................................... 137
CTBR: Timebase Counter Clear Register ............................................................... 138
Operation ........................................................................................................................... 139
Timebase Timer Interrupt Example (Main PLL Lock Wait)...................................... 139
Setting ............................................................................................................................... 140
Q & A ................................................................................................................................. 141
What are the types of interval time used in the timebase timer (and the timebase counter
used by the timebase timer) and how to select them? 141
What Is the count clock of the timebase counter?................................................... 141
How to operate the timebase timer?........................................................................ 141
How is the timebase timer (=timebase counter) operation stopped? ...................... 141
How is the timebase counter (=timebase timer) cleared? ....................................... 141
How about the interrupt-associated registers? ....................................................... 141
What are the interrupt types? ................................................................................. 142
How is an interrupt enabled?................................................................................... 142
Sample Program................................................................................................................ 143
Caution .............................................................................................................................. 144
vii
Chapter 14 Watchdog Timer.............................................................................. 145
1.
2.
3.
4.
4.1
4.2
4.3
5.
5.1
5.2
5.3
5.4
5.5
5.6
6.
7.
7.1
7.2
7.3
7.4
7.5
8.
9.
Overview............................................................................................................................
Features ............................................................................................................................
Configuration .....................................................................................................................
Register .............................................................................................................................
RSRR: Watchdog Timer Control Register ...............................................................
WPR: Watchdog Reset Generation Postponement Register ..................................
CTBR: Timebase Counter Clear Register ...............................................................
Operation ...........................................................................................................................
Watchdog (Detecting Runaway)..............................................................................
Starting the Watchdog Timer and Setting the Watchdog Timer Period..................
Postponing the Generation of a Watchdog Reset ..................................................
Confirming that the Watchdog Reset has been Generated....................................
Temporarily Stopped Watchdog Timer (Automatic Generation Postponement) ...
Stopping the Watchdog Timer .................................................................................
Setting ...............................................................................................................................
Q & A .................................................................................................................................
What are the types of watchdog interval time and how are they selected?............
How is the watchdog operation started (set to valid)?............................................
How can we check that the watchdog reset has been generated? ........................
How is the watchdog stopped?...............................................................................
How do I clear the watchdog timer (1-bit counter)?................................................
Sample Program................................................................................................................
Caution ..............................................................................................................................
Chapter 15
1.
2.
3.
4.
4.1
5.
5.1
5.2
6.
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8.
9.
145
145
146
147
147
148
148
149
149
150
150
150
150
150
151
152
152
152
152
152
152
153
154
Main Clock Oscillation Stability Wait Timer ................................ 155
Overview............................................................................................................................ 155
Features ............................................................................................................................ 155
Configuration ..................................................................................................................... 156
Register ............................................................................................................................ 157
OSCR: Control Register for the Main Clock Oscillation Stability Wait Timer........... 157
Operation ........................................................................................................................... 158
Main Clock Oscillation Stability Wait ...................................................................... 158
Interval Interrupt ...................................................................................................... 159
Setting ............................................................................................................................... 160
Q & A ................................................................................................................................. 161
What are the types of interval time (wait time) and how are they selected? ........... 161
How do I select the count clock? ............................................................................. 161
How is the main clock oscillation stability wait timer count operation enabled/disabled?
161
How is the main clock oscillation stability wait timer cleared?................................. 161
What happens with the interrupt-associated registers?........................................... 161
What are the types of interrupt? .............................................................................. 162
how is an interrupt enabled? ................................................................................... 162
How is the main clock oscillation stability wait timer stopped counting? ................ 162
Sample Program................................................................................................................ 163
Caution .............................................................................................................................. 165
viii
Chapter 16 Clock Timer ..................................................................................... 167
1.
2.
3.
4.
4.1
5.
5.1
5.2
5.3
6.
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8.
9.
Overview............................................................................................................................
Features ............................................................................................................................
Configuration .....................................................................................................................
Register .............................................................................................................................
WPCR: Clock Timer Control Register .....................................................................
Operation ...........................................................................................................................
Subclock Oscillation Stability Wait Interrupt ............................................................
Interval Interrupt (Clock Interrupt)............................................................................
Returning from the Stop Mode due to Interval Operation (Clock Interrupt) ............
Setting ...............................................................................................................................
Q & A .................................................................................................................................
What are the types of interval time (wait time) and how are they selected? ..........
How is the count clock selected? ...........................................................................
How does the clock timer count up?........................................................................
How is the clock timer cleared?...............................................................................
What are interrupt-associated registers?................................................................
What are the types of interrupt? .............................................................................
How is the interrupt enabled?.................................................................................
How is the clock timer stopped counting? ...............................................................
Sample Program................................................................................................................
Caution ..............................................................................................................................
167
167
168
169
169
170
170
171
172
173
174
174
174
174
174
174
175
176
176
177
178
Chapter 17 Delayed Interrupt ............................................................................ 179
1.
2.
3.
4.
4.1
5.
6.
7.
7.1
7.2
8.
9.
Overview............................................................................................................................
Features ............................................................................................................................
Configuration .....................................................................................................................
Register .............................................................................................................................
DICR: Delay Control Register..................................................................................
Operation ...........................................................................................................................
Setting ...............................................................................................................................
Q & A .................................................................................................................................
What are interrupt-associated registers?................................................................
How interrupt request is generated/released?........................................................
Sample Program................................................................................................................
Caution ..............................................................................................................................
179
179
179
180
180
180
181
181
181
181
181
181
Chapter 18 Bit Search ........................................................................................ 183
1.
2.
3.
4.
4.1
Overview............................................................................................................................
Features ............................................................................................................................
Configuration .....................................................................................................................
Register .............................................................................................................................
BSD0: 0 Detection Register / BSD1:1 Detection Register / BSDC: Changing Point
Detection Data Register 185
4.2
BSRR: Detection Result Register............................................................................
5.
Operation ...........................................................................................................................
5.1
Zero detection .........................................................................................................
5.2
One Detection .........................................................................................................
ix
183
183
184
185
186
187
187
187
5.3
6.
7.
7.1
7.2
7.3
7.4
8.
9.
Changing Point Detection........................................................................................
Setting ...............................................................................................................................
Q & A .................................................................................................................................
How is data written? ................................................................................................
How is scanning started? ........................................................................................
How is a result read?...............................................................................................
How is the previous bit search state restored?.......................................................
Sample Program................................................................................................................
Caution ..............................................................................................................................
188
189
190
190
190
190
190
191
192
Chapter 19 I/O Port ............................................................................................. 193
1.
2.
3.
4.
4.1
4.2
4.3
4.4
5.
6.
7.
7.1
7.2
7.3
7.4
8.
9.
Overview............................................................................................................................
Features ............................................................................................................................
Configuration .....................................................................................................................
Register .............................................................................................................................
PDR: Port Data Register .........................................................................................
DDR: Data Direction Register..................................................................................
PFR: Port Function Register....................................................................................
PCR: Pull-up Resistor Control Register...................................................................
Operation ...........................................................................................................................
Setting ...............................................................................................................................
Q & A ................................................................................................................................
How are multi-purpose port output values set? .......................................................
How are the multi-purpose port input/output set?....................................................
How are the peripheral function output/input set? ..................................................
How are the pull-up resistors built in the port used? ...............................................
Sample Program................................................................................................................
Caution ..............................................................................................................................
193
193
194
197
197
199
201
202
203
204
204
204
204
204
204
205
205
Chapter 20 Interrupt Control ............................................................................. 207
1.
2.
3.
4.
4.1
4.2
5.
6.
7.
7.1
7.2
7.3
7.4
7.5
8.
9.
Overview............................................................................................................................
Features ............................................................................................................................
Configuration .....................................................................................................................
Registers............................................................................................................................
ICR: Interrupt Control Register ................................................................................
Interrupt Vector........................................................................................................
Operation ...........................................................................................................................
Setting ...............................................................................................................................
Q & A .................................................................................................................................
How can I set interrupt levels? ................................................................................
How do I enable interrupts?.....................................................................................
How do I disable interrupts? ....................................................................................
How can I set interrupt vectors? ..............................................................................
How can I set an I flag? ..........................................................................................
Sample Programs ..............................................................................................................
Caution ..............................................................................................................................
207
207
208
212
212
214
215
216
216
216
216
216
216
217
218
219
Chapter 21 External Interrupt ............................................................................ 221
x
1.
2.
3.
4.
4.1
4.2
4.3
5.
6.
7.
7.1
7.2
7.3
7.4
7.5
8.
9.
Overview............................................................................................................................
Features ............................................................................................................................
Configuration .....................................................................................................................
Registers............................................................................................................................
ELVR: Interrupt Eequest Level Register..................................................................
EIRR: Interrupt Request Register............................................................................
ENIR: Interrupt Request Enable Register................................................................
Operation ...........................................................................................................................
Setting ...............................................................................................................................
Q & A .................................................................................................................................
What are the types and setting procedures of detect levels?..................................
How do I set INT pin as the input? ..........................................................................
What interrupt registers are used? ..........................................................................
Interrupt types .........................................................................................................
How do I enable, disable, and clear interrupts? ......................................................
Sample Programs ..............................................................................................................
Caution ..............................................................................................................................
221
221
222
225
225
226
226
227
228
228
228
228
229
229
230
230
231
Chapter 22 U-timer ............................................................................................. 233
1.
2.
3.
4.
4.1
4.2
4.3
5.
5.1
5.2
5.3
6.
7.
7.1
7.2
7.3
7.4
7.5
8.
9.
Overview............................................................................................................................
Features ............................................................................................................................
Configuration .....................................................................................................................
Registers............................................................................................................................
UTIM: U-timer Register............................................................................................
UTIMER: Reload Register .......................................................................................
UTIMC: U-timer Control Register ............................................................................
Operation ...........................................................................................................................
Operations: In the case of (2n+2): ..........................................................................
Formula of the clock rate .........................................................................................
Operation after reset release...................................................................................
Setting ...............................................................................................................................
Q & A .................................................................................................................................
How do I set (rewrite) a reload value?.....................................................................
What are the types of count clock? .........................................................................
What are operation modes? ....................................................................................
How do I enable / disable the count operation of the U-timer?...............................
How do I initialize the U-timer?................................................................................
Sample Programs ..............................................................................................................
Caution ..............................................................................................................................
233
233
234
235
235
235
236
238
238
238
239
239
239
239
240
240
240
240
241
242
Chapter 23 UART ................................................................................................ 243
1.
2.
3.
4.
4.1
4.2
4.3
Overview............................................................................................................................
Features ............................................................................................................................
Configuration .....................................................................................................................
Registers............................................................................................................................
SMR: Serial Mode Register .....................................................................................
SCR: Serial Control Register...................................................................................
SSR: Serial status register ......................................................................................
xi
243
243
244
249
249
250
252
4.4
SIDR: Serial Input Data Register / SODR: Serial Output Data Register .................
5.
Operation ...........................................................................................................................
5.1
Mode 0/1: Asynchronous mode (normal/multiprocessor) ........................................
5.2
Mode 0/1: Asynchronous mode (normal/multiprocessor) ........................................
5.3
Mode 2: Clock synchronous mode ..........................................................................
6.
Setting ...............................................................................................................................
7.
Q & A .................................................................................................................................
7.1
What are the possible combinations of the settings? ..............................................
7.2
How do I select an operation mode? .......................................................................
7.3
The types and the selection methods of the operation clock...................................
7.4
How do I control the SCK pin, the SIN pin, and the SOT pin? ................................
7.5
How do I enable/stop the operation of UART? ........................................................
7.6
How do I set the parity?...........................................................................................
7.7
How do I set a data length?.....................................................................................
7.8
How do I select the STOP bit length?......................................................................
7.9
How do I clear the error flag? ..................................................................................
7.10
How do I set the transfer direction?.........................................................................
7.11
How do I clear the receive completed flag?.............................................................
7.12
What are the types and the meanings of error flags?..............................................
7.13
Where is the receive data stored?...........................................................................
7.14
Which is the status to check the timing to write the transmit data? .........................
7.15
Where are the transmit data written to? ..................................................................
7.16
How do I clear the transmit buffer empty flag? ........................................................
7.17
How do I select a data format (address/data)?........................................................
7.18
How do I start the receive/transmit? ........................................................................
7.19
How do I stop the operation? ..................................................................................
7.20
How do I confirm the operation completion? ...........................................................
7.21
How do I set the baud rate? ....................................................................................
7.22
What interrupt registers are used? ..........................................................................
7.23
Interrupt Types ........................................................................................................
7.24
How do I enable, disable, and clear interrupts? ......................................................
7.25
What is an example of the system construction in the mode 1? .............................
7.26
What is the flow chart in the mode 1? .....................................................................
8.
Sample Programs ..............................................................................................................
9.
Caution ..............................................................................................................................
254
255
255
256
257
258
261
261
261
261
262
262
262
262
262
263
263
263
263
263
263
263
263
264
264
264
264
264
265
265
265
266
266
267
269
Chapter 24 Free-run Timer................................................................................. 271
1.
2.
3.
4.
4.1
4.2
5.
5.1
5.2
6.
7.
Overview............................................................................................................................
Features ............................................................................................................................
Configuration Diagram.......................................................................................................
Registers............................................................................................................................
TCCS: Timer Control Register.................................................................................
TCDT: Timer Data Register.....................................................................................
Operation ...........................................................................................................................
Count Operation of the Free-run Timer ..................................................................
Various Clear Operations of the Free-run Timer ....................................................
Setting ...............................................................................................................................
Q & A .................................................................................................................................
xii
271
271
272
274
274
276
277
277
278
279
280
7.1
What are the types of the internal clock, and how do I select? ...............................
7.2
How do I select the external clock? .........................................................................
7.3
How do I enable / disable the count operation of the free-run timer?......................
7.4
How do I clear the free-run timer? ...........................................................................
7.5
What interrupt registers are used? ..........................................................................
7.6
Interrupt Types ........................................................................................................
7.7
How do I enable interrupts?.....................................................................................
7.8
How do I stop the free-run timer? ............................................................................
8.
Sample Programs ..............................................................................................................
9.
Caution ..............................................................................................................................
280
280
280
281
281
281
281
281
282
283
Chapter 25 Input Capture................................................................................... 285
1.
2.
3.
4.
4.1
4.2
5.
5.1
5.2
6.
7.
7.1
7.2
7.3
7.4
7.5
7.6
8.
9.
Overview............................................................................................................................ 285
Features ............................................................................................................................ 285
Configuration ..................................................................................................................... 286
Register ............................................................................................................................. 287
IPCP: Input Capture Data Register ......................................................................... 287
ICS01: Input Capture Control Register.................................................................... 288
Operation ........................................................................................................................... 290
Capture Timing, Interrupt Timing ............................................................................ 290
Input Capture Edge Specification and Operation ................................................... 291
Settings.............................................................................................................................. 292
Q&A ................................................................................................................................... 293
What are the varieties of active edge polarity for external input, and how do I select
them? 293
What about setting the external input pins (IC0, IC1)?............................................ 293
What about interrupt-related registers? ................................................................... 293
What are the types of interrupts? ............................................................................ 293
How do I enable interrupts?..................................................................................... 293
How do I measure the pulse width of the input signal? ........................................... 294
Sample Programs .............................................................................................................. 295
Caution .............................................................................................................................. 296
Chapter 26 Output Compare.............................................................................. 297
1.
2.
3.
4.
4.1
4.2
4.3
5.
5.1
5.2
6.
7.
7.1
7.2
Overview............................................................................................................................
Features ............................................................................................................................
Configuration Diagram.......................................................................................................
Registers............................................................................................................................
OCS01: Output Control Register 01 ........................................................................
OCS23: Output Control Register 23 ........................................................................
OCCP: Compare Register .......................................................................................
Operation ...........................................................................................................................
Output Compare Output (Independent Reversal) CMODE=“0”...............................
Output Compare Output (Cooperative Reversal) CMODE=“1” ...............................
Settings..............................................................................................................................
Q & A .................................................................................................................................
How do I set the compare value? ............................................................................
How do I set the compare mode? (for OC1,OC3 input) ..........................................
xiii
297
297
298
300
300
303
306
307
307
308
309
310
310
310
7.3
7.4
7.5
7.6
7.7
7.8
How do I enable/disable the compare operation? ................................................... 310
How do I set the initial level of the compare pin output? ......................................... 310
How do I set the output for compare pins OP0-OP3? ............................................. 311
How do I clear the free-run timer? ........................................................................... 311
How do I enable the compare operation?................................................................ 311
How do I compare the free-run timer value with the compare register value and clear the
free-run timer when they match? 311
7.9
What are the interrupt-related registers?................................................................. 311
7.10
What are the types of interrupts? ............................................................................ 311
7.11
How do I enable interrupts?..................................................................................... 312
7.12
Compare value calculation procedure ..................................................................... 312
8.
Sample Program................................................................................................................ 313
9.
Caution .............................................................................................................................. 316
Chapter 27 Reload Timer ................................................................................... 317
1.
2.
3.
4.
4.1
4.2
4.3
5.
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Overview............................................................................................................................ 317
Features ............................................................................................................................ 317
Configuration ..................................................................................................................... 318
Registers............................................................................................................................ 321
TMCSR: Reload Timer Control Status Register ...................................................... 321
TMR: Timer Register ............................................................................................... 324
TMRLR: Reload register.......................................................................................... 324
Operation ........................................................................................................................... 325
Internal Clock/Reload Mode .................................................................................... 325
Internal Clock/One-shot Mode................................................................................. 326
External Event Clock Reload Mode......................................................................... 327
External Event Clock/One-shot Mode ..................................................................... 328
Operation during Reset ........................................................................................... 328
Operation during Sleep Mode.................................................................................. 328
Operation during Stop Mode ................................................................................... 328
Operation when Returning from Stop Mode ............................................................ 329
Status Transition ..................................................................................................... 329
Setting ............................................................................................................................... 330
Q & A ................................................................................................................................. 332
What is the reload value setting (rewriting) procedure? .......................................... 332
What are the kinds of count clocks and how are they selected?............................. 332
How to I enable/disable the reload timer count operation? ..................................... 332
How do I set the reload timer mode (reload/one-shot)? .......................................... 333
How do I reverse the output level? .......................................................................... 333
What are the kinds of triggers, and how do I select them?...................................... 334
What are the types of external event clock active edges and how do I select them? ....
334
7.8
How do I make a pin a TOT output pin?.................................................................. 334
7.9
How do I make the TIN pin into an external event input pin, or an external trigger input
pin? 334
7.10
How do I generate an activation trigger?................................................................. 335
7.11
What are the interrupt-related registers?................................................................. 335
7.12
How do I enable interrupts?..................................................................................... 335
7.13
How do I stop the reload timer?............................................................................... 335
xiv
8.
9.
Sample Programs .............................................................................................................. 336
Caution .............................................................................................................................. 339
Chapter 28 Programmable Pulse Generators (PPGs) ..................................... 341
1.
Overview............................................................................................................................
2.
Features ............................................................................................................................
3.
Configuration .....................................................................................................................
4.
Registers............................................................................................................................
4.1
PCSR: PPG Cycle Setting Register ........................................................................
4.2
PDUT: PPG Duty Setting Register ..........................................................................
4.3
PCN: PPG Control Status register...........................................................................
4.4
GCN10: General Control register 10 .......................................................................
4.5
GCN20: General Control Register 20......................................................................
4.6
PTMR: PPG Timer Register ....................................................................................
5.
Operation ...........................................................................................................................
5.1
PWM Operation .......................................................................................................
5.2
One-Shot Operation ................................................................................................
5.3
Restart Operation ....................................................................................................
6.
Setting ...............................................................................................................................
7.
Q & A .................................................................................................................................
7.1
How do I set (rewrite) a cycle and a duty? ..............................................................
7.2
How do I enable or disable PPG operations?..........................................................
7.3
How do I set the PPG operation mode (PWM operation/one-shot operation)?.......
7.4
How do I get it restarted? ........................................................................................
7.5
What count clocks are available and how are they selected? .................................
7.6
How do I clamp the PPG pin output level? ..............................................................
7.7
What activation triggers are available and how are they selected?.........................
7.8
How do I invert the output polarity? .........................................................................
7.9
How do I program a pin as a PPG output pin? ........................................................
7.10
How do I generate an activation trigger?.................................................................
7.11
How do I stop a PPG operation? .............................................................................
7.12
What interrupt registers are used? ..........................................................................
7.13
What interrupts are available and how are they selected?......................................
7.14
How do I enable, disable and clear interrupts? .......................................................
8.
Sample Program ...............................................................................................................
9.
Caution ..............................................................................................................................
341
341
343
346
346
347
348
350
351
351
352
352
353
354
355
357
357
357
357
357
358
358
359
360
360
361
361
361
362
362
363
367
Chapter 29 A/D Converter.................................................................................. 369
1.
2.
3.
4.
4.1
4.2
4.3
4.4
5.
5.1
Overview............................................................................................................................
Features ............................................................................................................................
Configuration .....................................................................................................................
Register .............................................................................................................................
ADCSH: A/D Control Register (upper) ....................................................................
ADCSL: A/D Control Register (lower)......................................................................
ADCT: Conversion Time Setting Register ...............................................................
ADT: Data Buffer register ........................................................................................
Operation ...........................................................................................................................
Single-shot conversion mode ..................................................................................
xv
369
369
370
373
373
374
376
377
379
379
5.2
Scan conversion mode ............................................................................................
6.
Setting ...............................................................................................................................
7.
Q & A .................................................................................................................................
7.1
What conversion modes are available and how are they selected?........................
7.2
How do I specify a bit length?..................................................................................
7.3
How do I select channels?.......................................................................................
7.4
How do I set a conversion time? .............................................................................
7.5
How do I enable analog pin input? ..........................................................................
7.6
To select how to activate the A/D converter ............................................................
7.7
To activate the A/D converter ..................................................................................
7.8
To verify the end of a conversion ............................................................................
7.9
How do I read a conversion value? .........................................................................
7.10
How do I force an A/D conversion operation to a stop? ..........................................
7.11
What interrupt registers are used? ..........................................................................
7.12
What interrupts are available?.................................................................................
7.13
How do I enable, disable, clear interrupts? .............................................................
8.
Sample ProgramS .............................................................................................................
9.
Caution ..............................................................................................................................
380
381
383
383
383
383
384
384
384
385
385
385
385
386
386
386
387
389
Chapter 30 D/A Converter.................................................................................. 393
1.
2.
3.
4.
4.1
4.2
5.
6.
7.
7.1
7.2
7.3
7.4
7.5
8.
9.
Overview............................................................................................................................ 393
Features ............................................................................................................................ 393
Configuration ..................................................................................................................... 394
Registers............................................................................................................................ 395
DADR: D/A Data Register ....................................................................................... 395
DACR: D/A Control Register ................................................................................... 395
Operation ........................................................................................................................... 396
Setting ............................................................................................................................... 397
Q & A ................................................................................................................................. 398
Where should I set digital values?........................................................................... 398
How do I program the D/A pins for D/A output? ..................................................... 398
How do I enable or disable D/A output? ................................................................. 398
How do I activate a D/A conversion?...................................................................... 398
What is the formula used to work out the value necessary to produce an expected
voltage? 398
Sample Program................................................................................................................ 399
Caution .............................................................................................................................. 400
Chapter 31 PWC.................................................................................................. 401
1.
2.
3.
4.
4.1
4.2
5.
6.
7.
Overview............................................................................................................................
Features ............................................................................................................................
Configuration .....................................................................................................................
Registers............................................................................................................................
PWCC: PWC Control Register ................................................................................
PWCD: PWC Data Register ....................................................................................
Operation ...........................................................................................................................
Setting ...............................................................................................................................
Q & A .................................................................................................................................
xvi
401
401
402
403
403
404
405
406
407
7.1
How do I program input pins (PWI, PWI1)?............................................................
7.2
How do I enable or disable PWC operations?........................................................
7.3
How do I enable PWC capture operations? ............................................................
7.4
How do I clear the counter?....................................................................................
7.5
How do I clear the capture flag?.............................................................................
7.6
How do I calculate the input signal period? ............................................................
8.
Sample Program ...............................................................................................................
9.
Caution ..............................................................................................................................
407
407
407
407
407
407
408
409
Chapter 32 Up/Down Counter............................................................................ 411
1.
2.
3.
4.
4.1
4.2
4.3
4.4
5.
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
6.
7.
7.1
7.2
7.3
7.4
Overview............................................................................................................................ 411
Feature .............................................................................................................................. 411
Configuration ..................................................................................................................... 412
Register ............................................................................................................................. 416
CCR: Counter Control Register ............................................................................... 416
CSR: Count Status Register.................................................................................... 419
UDCR: Up/Down Counter Register ......................................................................... 421
RCR: Reload/Compare Register ............................................................................. 422
Operation ........................................................................................................................... 423
Timer Mode CMS[1:0]=“00”................................................................................... 423
Up/Down Count Mode CMS[1:0]=“01”.................................................................... 424
Up/Down Count Mode CMS[1:0]=“01”.................................................................... 425
Phase Difference Count Mode (Multiply by 2) CMS[1:0]=“10” ............................... 426
Phase Difference Count Mode (Multiply by 4) CMS[1:0]=“11” ............................... 427
Clear Timing ............................................................................................................ 428
Reload Timing ......................................................................................................... 429
Writing a Value to Counter ...................................................................................... 429
Setting ............................................................................................................................... 430
Q&A ................................................................................................................................... 432
How do I select a bit length (8 or 16) of Up/Down Counter? ................................... 432
What types of count modes are available and how are they set? ........................... 432
How do I select a count source for Up/Down Counter running in the timer mode?. 432
How do I select the edge with which Up/Down Counter running in the Up/down count
mode detects an input signal (AIN or BIN)? 432
7.5
How do I set a value to Up/Down Counter? ............................................................ 432
7.6
When the Up/Down Counter's count-up value agrees with the compare value
(RCR[0:1]), how do I enable clearing of Up/Down Counter the next time when the counter
counts up? 432
7.7
How do I enable reloading of the reload value (RCR[1:0]) to Up/Down Counter when Up/
Down Counter is underflowed? 433
7.8
How do I clear Up/Down Counter? .......................................................................... 433
7.9
How do I clear Up/Down Counter using the ZIN pin?.............................................. 433
7.10
How do I control Up/Down Counter's count operation using the ZIN pin? .............. 433
7.11
How do I enable/disable Up/Down Counter's count operation? .............................. 434
7.12
How do I know the previous count direction (the current rotation direction)?.......... 434
7.13
How do I know count direction changes? ................................................................ 434
7.14
How do I know that a compare-match has occurred? ............................................. 434
7.15
How do I know that an overflow or underflow has occurred? .................................. 435
7.16
How do I set the reload/compare value? ................................................................. 435
xvii
7.17
What are interrupt-related registers?......................................................................
7.18
What interrupts are available and how are they selected?.....................................
7.19
How do I enable (select), disable or clear interrupts? .............................................
8.
Sample Programs ..............................................................................................................
9.
Caution ..............................................................................................................................
435
435
436
437
440
Chapter 33 LCD Controller ................................................................................ 441
1.
Overview............................................................................................................................ 441
2.
Features ............................................................................................................................ 441
3.
Configuration ..................................................................................................................... 442
4.
Registers............................................................................................................................ 444
4.1
LCR0: LCDC Control Register 0.............................................................................. 444
4.2
VRAM: Data Memory for Display............................................................................. 446
4.3
LCR1: LCDC Control Register 1.............................................................................. 448
4.4
LCDCMR: Common Pin Switching Register............................................................ 448
5.
Operation ........................................................................................................................... 449
5.1
LCD Controller/Driver (LCDC) Operation ................................................................ 449
5.2
1/2 Duty Cycle Output Waveform ............................................................................ 449
5.3
1/3 Duty Cycle Output Waveform ............................................................................ 451
5.4
1/4 Duty Cycle Output Waveform ............................................................................ 453
6.
Setting ............................................................................................................................... 454
7.
Q&A ................................................................................................................................... 455
7.1
How do I specify pins as COM or SEG output pins? ............................................... 455
7.2
How do I set VRM?.................................................................................................. 456
7.3
How do I set a frame period? .................................................................................. 456
7.4
How do I set a duty cycle?....................................................................................... 457
7.5
How do I control starting and stopping of LCD? ...................................................... 457
7.6
How do I enable or disable LCD display?................................................................ 457
7.7
How do I enable LCD display even in the sub-stop mode?..................................... 457
7.8
How do I select internal or external divided resistors? ............................................ 457
7.9
How do I select internal or external divided resistors? ............................................ 458
7.10
How do I use external divided resistors to shut off the current when LCD is deactivated?
458
8.
Sample Programs .............................................................................................................. 459
9.
Caution .............................................................................................................................. 462
Chapter 34 Clock Monitor .................................................................................. 463
1.
2.
3.
4.
4.1
5.
6.
7.
7.1
7.2
7.3
Overview............................................................................................................................
Features ............................................................................................................................
Configuration .....................................................................................................................
Register .............................................................................................................................
CKR: Clock Output Enable Register........................................................................
Operation ...........................................................................................................................
Settings..............................................................................................................................
Q&A ...................................................................................................................................
How do I set an output terminal (CKOT)? ...............................................................
How do I select an output frequency? .....................................................................
How do I enable/disable clock monitor output? .......................................................
xviii
463
463
464
465
465
466
467
467
467
467
467
8.
Sample Program................................................................................................................ 468
Chapter 35 Real-Time Clock .............................................................................. 469
1.
2.
3.
4.
4.1
4.2
4.3
4.4
5.
6.
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Overview............................................................................................................................ 469
Features ............................................................................................................................ 469
Configuration ..................................................................................................................... 470
Registers............................................................................................................................ 471
WTDBL: Clock Disable Register.............................................................................. 471
WTCR: RTC Control Register ................................................................................. 472
WTBR: Sub-Second Registers ................................................................................ 474
WTHR/WTMR/WTSR: Hour/Minute/Second Registers ........................................... 475
Operation ........................................................................................................................... 476
Setting ............................................................................................................................... 478
Q&A ................................................................................................................................... 480
How do I set the count period of 1 second? ............................................................ 480
How do I initialize Real-time Clock? ........................................................................ 480
How do I set or update time (hour/minute/second)?................................................ 480
How do I start or stop Real-time Clock's counting?................................................. 480
How do I confirm that Real-time Clock is active? .................................................... 480
How do I know time? ............................................................................................... 480
How do I stop Real-time Clock? .............................................................................. 480
How do I save current consumption or resume Real-time Clock in the STOP mode? ...
481
7.9
What are interrupt-related registers?....................................................................... 481
7.10
What interrupts are available and how are they selected?..................................... 481
7.11
How do I enable interrupts?..................................................................................... 481
8.
Sample Programs .............................................................................................................. 482
9.
Caution .............................................................................................................................. 483
Chapter 36 Flash Memory.................................................................................. 485
1.
2.
3.
4.
4.1
4.2
5.
5.1
5.2
6.
6.1
6.2
6.3
6.4
6.5
7.
7.1
7.2
Overview............................................................................................................................
Features ............................................................................................................................
Configuration .....................................................................................................................
Registers............................................................................................................................
FLCR: FLASH Memory Control Status Register .....................................................
FLWC: FLASH Memory Wait Register ....................................................................
Access Modes ...................................................................................................................
Access from the FR-CPU ........................................................................................
Flash Memory Mode................................................................................................
Auto Algorithms .................................................................................................................
Command Operation ...............................................................................................
Auto Algorithm Commands.....................................................................................
Hardware Sequence Flag........................................................................................
FLCR: Hardware Sequence Flag ............................................................................
Sample Use of Hardware Sequence Flag ...............................................................
Sector Protection ...............................................................................................................
List of Sector Protection Operations........................................................................
Enable Sector Protection.........................................................................................
xix
485
485
486
489
489
490
491
491
492
493
493
494
497
498
500
501
501
501
7.3
Verify Sector Protection........................................................................................... 502
7.4
Temporary Sector-protection Release..................................................................... 503
8.
Caution .............................................................................................................................. 504
Chapter 37 Flash On-Board Serial Writing....................................................... 505
1.
2.
3.
4.
5.
6.
7.
Overview............................................................................................................................
Features ............................................................................................................................
Configuration .....................................................................................................................
Pin Description...................................................................................................................
Sample Serial Write Connection........................................................................................
Flash Microcomputer Programmer System Configuration.................................................
Caution ..............................................................................................................................
505
505
506
506
507
508
508
Chapter 38 FUJITSU FLASH MCU Programmer .............................................. 509
1.
2.
3.
4.
5.
6.
7.
7.1
7.2
7.3
8.
Overview............................................................................................................................
Features ............................................................................................................................
Pin Description...................................................................................................................
Sample Onboard Overwriting Connection .........................................................................
Pin Timing Charts ..............................................................................................................
Software Installation and Execution...................................................................................
Programmer Functions ......................................................................................................
Download procedure ...............................................................................................
Procedure for erasing and writing............................................................................
Continuous Write Mode ...........................................................................................
Caution ..............................................................................................................................
509
509
510
511
512
513
514
514
515
517
518
Chapter 39 I/O Register Files............................................................................. 519
1.
2.
3.
3.1
3.2
4.
5.
Overview............................................................................................................................
Configuration .....................................................................................................................
Sample I/O Register Declaration .......................................................................................
I/O Register Variables and Bit-field Members .........................................................
Declarations ............................................................................................................
I/O Register File Usage .....................................................................................................
Caution ..............................................................................................................................
xx
519
519
520
520
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522
Chapter 1 Introduction
1.How to Handle the Device
Chapter 1
Introduction
1. How to Handle the Device
■ Device Handling Instructions
This chapter describes latch-up prevention and pin termination.
● To set latch-up prevention
CMOS IC may occur latch up when applied voltage for input terminal or output terminal is higher than VCC or lower than VSS, or
voltage higher than rating voltage is applied between VCC and VSS. Make sure not to apply voltage higher than the maximum
rating voltage since latch up may surge electric current and result in thermal destruction of the device.
● Termination of unused pin
If unused pin is not terminated, it may cause an error. Conduct pull-up or pull-down process.
● Power-supply pin
If multiple VCC and VSS exist, as a matter of device design, they are connected each other to prevent an error when their voltage
should be identical in the device. In order to reduce unnecessary radiation, prevent an strobe signal error due to upward ground
level, and comply with total output current standard, be sure to externally connect them to power supply and ground. Give
consideration to connect VCC and VSS of the device from power supply at low impedance.
Near the device, it is preferable to connect about 0.1µF ceramic condenser as a bypass condenser between VCC and VSS.
● Crystal-oscillator circuit
Noise to X0 or X1 pin may cause an error. Make a design for printed board to closely allocate X0, X1, crystal oscillator (or ceramic
oscillator), bypass condenser towards ground and the device.
It is recommended to make a printed board artwork which surrounds X0 and X1 pins using ground.
● NC and OPEN pin termination
Do not terminate NC pin and OPEN pin to use.
● Mode pins (from MD0 to MD2)
Connect pins from MD0 to MOD2 directly to VCC or VSS to use. To avoid entering test mode due to noise, make a short pattern
length between each mode pin on printed board and VCC or VSS to connect pins at low impedance.
● At the time of power-on
Immediately after power-on operation, be sure to reset INIT pin to initialize the setting (INIT). Immediately after power-on
operation, to ensure the oscillation stabilization time required for oscillation circuit, hold “L”-level input to the pin during the
oscillation stabilization time required for oscillation circuit. (INIT operation on the pin initializes the setting for oscillation
stabilization time to minimum value.)
● Source oscillation input at the time of power-on
At the time of power-on, be sure to input the clock until the oscillation stabilization wait is over.
● Caution: during the PLL clock operation
Even if oscillator is disconnected or input is stopped while selecting PLL clock, self-excited oscillation circuit in the PLL may
continue running at self-running frequency. This self-running operation is not covered by guarantee.
● Acc pin
Connect about 0.1µF condenser between Acc pin and Avcc pin.
1
Chapter 1 Introduction
1.How to Handle the Device
● For more specification about operating voltage, see the latest data sheet.
2
Chapter 1 Introduction
2.Instruction for Use
2. Instruction for Use
■ Clock Controls
By inputting “L” to INIT, ensure clock oscillation stabilization time.
■ Switching of dual-purpose port
Use PFR (Port function register) to switch between PORT and dual-purpose port.
■ Low-power-consumption mode
• For standby mode, enable synchronous standby (TBCR.SYNCS=“1”) and then use the following sequences.
(LDI
(LDI
STB
LDUB
LDUB
NOP
NOP
NOP
NOP
NOP
#value_of_standby, R0
#_STCR, R12
R0, @R12
@R12, R0
@R12, R0
value_of_standby is a write data to STCR
_STCR is the STCR address. (481H)
Write to Standby Control Register (STCR).
STCR read for synchronous standby.
Dammy read STCR again.
NOP x 5 for timing adjustment.
In addition, after returning from standby, set I flag, ILM and ICR in order to branch to interrupt handler which triggered
the return.
• If you use monitor debugger, you should avoid the following.
• Do not set breakpoints for command sequence above.
• Do not conduct stepwise execution for command sequence above.
■ Power-on sequence using two power supplies
Power-on and power-off sequence
Power-on sequence: (1) VCC3B and VCC3 (2) VCC (3) VCC3IO, AVRH, AVCC and V0-V3
Power-off sequence: (1) VCC3IO, AVRH, AVCC and V0-V3 (2) VCC (3) VCC3B and VCC3
Follow the sequence above.
If you power on Vcc first, ensure that the difference in potential between Vcc and Vcc3 becomes within 3.6V.
Power supply V3 for LCD should not exceed Vcc. Power-on V3 should be carried out after power-on Vcc3.
To power on analogue power supply Avcc and analogue signal, power Vcc3 on ahead.
■ Power supply operating conditions recommended
VCC3=VCC3B=AVCC=VCC3IO This is recommended condition.
3
Chapter 1 Introduction
2.Instruction for Use
■ Caution: PS register
Because some commands previously proceed PS register, interrupt processing routine may be broken during the use of
debugger or displayed data on PS flag may be updated due to the following excecptional operations ((1) and (2)).
In each case, it is designed to correctly re-proceed operations after the return, the operation before and after EIT is
carried out in accordance with the specification.
• In immediately preceding DIV0U or DIV0S command,
• If interrupted by user,
• If stepwise execution is carried out,
• If data event or emulator menu made a break,
The following operation may be generated.
1. D0 or D1 flag is updated ahead.
2. EIT processing routine (interruption by user or emulator) is carried out.
3. After the return from EIT, it executes DIV0U or DIV0S command and then D0 or D1 flag are updated to the
same value as 1.
• If you execute each command of ORCCR, STILM, MOV Ri or PS to enable interruption with
interruption by user generated, the following operation may be generated.
4. PS register is updated ahead.
5. EIT processing routine (interruption by user) is carried out.
6. After the return from EIT, it executes commands above, and then PS register is updated to the same value as 1.
■ Watchdog timer function
Watchdog timer function equipped with FR60Lite monitors the progress to ensure that program executes reset delay
operation within a specified time and resets CPU if reset delay operation was not executed due to runaway of program.
Once you enable watchdog timer function, it continues running until it is reset.
By way of exception, reset delay is automatically conducted under the condition where CPU program execution is
stopped. For this exceptional condition, see “Chapter 14 Watchdog Timer (Page No.145)“.
■ Register against read/modify/write command
SMR register within UART cannot use read/modify/write command. To write in SMR register, write by Byte/Half-word/
Word in consideration with write control bit (bit-5, 4, 2, 0) rather than accessing by bit-by-bit.
4
Chapter 1 Introduction
2.Instruction for Use
■ Caution: to write in the register including status flag
To write in the register including status flag (in particular, interrupt request flag) in order to control the function, note that
you should not clear status flag unintentionally.
That is, take care not to clear the flag for status bit and make control bit to be the expected value during the writing.
Especially, for control bits consisting of several bits, bit command is not available since single bit access is only
acceptable for bit command, you should write into the both of control bit and status flag at the same time by Byte/Halfword/Word access. In this case, you should not clear other bits (bits of status flag) unintentionally.
The following shows registers which mostly include both of several bits and status flag.
• TBCR
• OSCR
• TWCR
• TCCS0, TCCS1
• ICS01
• TMCSR0, TMCSR1, TMCSR2, TMCSR3
• PCN0, PCN1, PCN2, PCN3, PCN4, PCN5
• ADCSL0, ADCSL1
• CCR0, CCR1
Note: For bit command, you do not have to be careful since this matter has been already considered.
5
Chapter 1 Introduction
3.Caution: debug-related matters
3. Caution: debug-related matters
■ Stepwise execution of RETI command
Under the circumstances where interruption is often generated when carrying out stepwise execution, only relevant
interrupt processing routine is repeatedly executed after the stepwise execution of RETI. Therefore, main routine or lowlevel interruption program will not be executed.
To avoid this problem, do not proceed stepwise execution of RETI command.
Or, upon the time when no debug is needed for relevant interrupt routine, proceed the debug by prohibiting relevant
interruptions.
■ Operand break
Do not set the access for area including system stack pointer address as the target for data event break.
6
Chapter 1 Introduction
4.How to Use This Document
4. How to Use This Document
■ Main terminology: This table shows main terminology used for FR60Lite.
Term
I-bus
D-bus
F-bus
R-bus
X-bus
Meaning
32-bit-wide bus for internal instruction.
Since FR60Lite series employ internal Harvard architecture, instruction and data are independent bus. For Ibus, Harverd/Prinston-bus-converter is connected.
Internal 32-bit-wide data bus.
For D-bus, bit search module, Harverd/Prinston-bus-converter is connected.
Internal 32-bit-wide bus.
F-bus is connected to embedded ROM, embedded RAM and R-bus interface (32-bit⇔16-bit Bus-converter).
Internal 16-bit-wide data bus.
R-bus is connected to D-bus via F-bus and Harverd/Prinston-bus-converter.
For R-bus, peripheral function, I/O, clock generator and interrupt controller are connected.
Since address and data are multiplexed on the R-bus, it takes several cycle times when CPU accesses to these
resources.
32-bit-wide address and data bus. Via bus-converter for external bus,
it accesses to external bus (FR60Lite does not support this X-bus).
Main clock
(FCL-MAIN)
This a clock which acts as a benchmark for LSI operation triggered by high-speed-side oscillation.
This is connected to main clock oscillation stabilization timer and clock generator.
Subclock
(FCL-SUB)
This a clock which acts as a benchmark for LSI operation triggered by low-speed-side oscillation.
This is connected to clock timer, real-time clock and clock generator.
Base clock
(Φ)
CPU clock
(CLKB)
Peripheral clock
(CLKP)
External bus clock
(CLKT)
Main clock mode
Subclock mode
Main RUN
Sub RUN
Oscillation
stabilization time
Main clock
oscillation
stabilization wait
At the maximum speed, base clock has the same cycle as source oscillation. In PLL of the clock generator,
base clock has clock multiplied by 1, 2, 3, 4, 5, 6, 7 and 8 or clock divided by 2.
Base clock is basis clock which generates CLKB, CLKP and CKLT in the clock generator.
CPU clock is the clock which is referred by CPU, embedded ROM, embedded RAM, bit search module and
internal bus (I-bus, D-bus, F-bus and X-bus) operations. Generated from the base clock in the clock generator.
Peripheral clock is the clock which is referred by each peripheral function (peripheral functions other than bit
search module) connected to R-bus and R-bus, clock control, interrupt controller, I/O port and external
interrupt input d operations. Generated from the base clock in the clock generator.
External bus clock is the clock which is referred by external expansion bus interface connected to X-BUS and
external clock output operations. Generated from the base clock in the clock generator.
Mode which runs based on main clock. This main clock mode has status such as main RUN, main sleep, main
stop, oscillation stabilization wait RUN, oscillation stabilization wait reset and program reset.
Mode which runs based on subclock. This subclock mode has status such as sub RUN, sub sleep, sub stop,
subclock oscillation stabilization wait RUN and program reset.
Main RUN is the status which is in main clock mode and also all circuits are operable.
Sub RUN is the status which is in subclock mode and also all circuits are operable.
Upon the reset (INITX, RST), return from stop, return from PLL abnormal operation, generation of watchdog
and during main clock stop, it takes oscillation stabilization time for main clock. Time base timer counts the
time.
Wait time until main clock oscillates after main clock stops in subclock mode.
Main clock oscillation stabilization timer counts the time.
7
Chapter 1 Introduction
4.How to Use This Document
■ Access size and address position
Offset
Address
Register name
Write-only
Read-only
Address offset value/Register name
Block
Up/down counter
0, 1
Read/write
Initial value
Byte access, Half-word access, and Word access are allowed.
There are three kinds of accesses such as Byte access, Half-word access and Word access. However, note that some
registers have restricted access. For more information, see “3. I/O Map (Page No.32)” or “4. Detail Description of
Register” in each chapter.
B,H,W
B
H
W
B, H
H,W
: Byte access, Half-word access, and Wordaccess are allowed.
: Byte access (Be sure to access by Byte.)
: Half-word access (Be sure to access by Half-word.)
: Word access (Be sure to access by Word.)
: Byte access, Half-word access only (Word access is not allowed.)
: Half-word access, Word access only (Byte access is not allowed.)
Reference
The following describes address position to access.
• In Word access, address becomes multiple of 4. (Lowest order 2 bits mandatorily become “00”.)
• In Half-word access, address becomes multiple of 2. (Lowest order 1 bit mandatorily becomes “0”.)
• In Byte access, address will not be changed.
Therefore, for example, make RCR0 register to use Half-word access,
For address 0B0H, RCR1+RCR0 register is accessed.
(When address offset is +1 and +2, (Example: RCR0+UDCR1) Half-word access is not allowed.)
8
Chapter 1 Introduction
4.How to Use This Document
■ About access size and bit position
Register name Register mark
Target peripheral device Address
Access size
Bit position
(1) Counter control register (Higher byte)
This is the register (higher byte) which controls up/down counter operation.
CCRH0 (Up/down counter 0): address 00B4h (Access: Byte, Half-word, Word)
CCRH1 (Up/down counter 1): address 00B8h (Access: Byte, Half-word, Word)
M16E/Reserved
Initial value
Attribute
*
bit15: Enable 16-bit mode
M16E (CCRH0 only)
Enable 16-bit mode
8-bit x 2-channel mode (8-bit mode)
16-bit x 1-channel mode (16-bit mode)
*: CCRH1: ReservedAlways write 0 for writing. The read value is indeterminate.
When access size changes, bit position changes.
• In the case that address offset value is +0 (Example: CCRH0 register)
Access size
Byte
Address
0B4H+0H
07
06
05
04
03
02
01
00
Half-word
0B4H+0H
15
14
13
12
11
10
09
08
Word
0B4H+0H
31
30
29
28
27
26
25
24
M16E
CDCF
CFIE
CLKS
CMS1
CMS0
CES1
CES0
Bit name
Bit position
• In the case that address offset value is +1 (Example: CCRL0 register)
Access size
Byte
Address
0B4H+1H
07
06
05
04
03
02
01
00
Half-word
0B4H+0H
07
06
05
04
03
02
01
00
Word
0B4H+0H
23
22
21
20
19
18
17
16
Reserved
CTUT
UCRE
RLDE
UDCC
CGSC
CGE1
CGE0
Bit name
Bit position
• In the case that address offset value is +2 (Example: UDCR1 register)
Access size
Byte
Address
0B0H+2H
07
06
05
04
03
02
01
00
Half-word
0B0H+2H
15
14
13
12
11
10
09
08
Word
0B0H+0H
15
14
13
12
11
10
09
08
D15
D14
D13
D12
D11
D10
D9
D8
Bit name
Bit position
• In the case that address offset value is +3 (Example: UDCR 1 register)
Access size
Byte
Address
0B0H+3H
07
06
05
04
03
02
01
00
Half-word
0B0H+2H
07
06
05
04
03
02
01
00
Word
0B0H+0H
07
06
05
04
03
02
01
00
D7
D6
D5
D4
D3
D2
D1
D0
Bit name
Bit position
9
Chapter 1 Introduction
4.How to Use This Document
■ Meaning of Bit Attribute Symbols
R
W
RM
R0
R1
W0
W1
(RM0)
(RM1)
RX
WX
: Readable
: Writable
: Reading operation during read/modify/write operation.
“/” (Slash) R/W: Readable and writable. (The read value is the value written.)
“,” (comma) R,W: Values are different between read and write. (The read value is different from the
value written.)
: The read value is “0”.
: The read value is “1”.
: Always write “0”.
: Always write “1”.
: read/modify/write operation reads “0”.
: read/modify/write operation reads “1”.
: The read value is indeterminate. (Reserved bit or undefined bit)
: Writing does not affect the operation. (Undefined bit)
• Example of how R/W is used
10
• R/W
: Readable and writable. (The read value is the value written.)
• R,W
: Readable and writable. (The read value and written value are different.)
• R,RM/W
: Readable and writable. (The read value and written value are different. Read/modify/write
command reads the value written.) Example: port data register
• R(RM1),W
: Readable and writable. (The read value and written value are different. Read/modify/write
command reads 1.) Example: interrupt request flag
• R/WX
: Read-only (Read-only. Writing does not affect the operation.)
• R1,W
: Write-only (Write-only. The read value is 1.)
• R0,W
: Write-only (Write-only. The read value is 0.)
• RX,W
: Write-only (Write-only. The read value is indeterminate.)
• R/W0
: Reserved bit (The written value is 0. The read value is the value written.)
• R0/W0
: Reserved bit (The written value is 0. The read value is 0.)
• R1,W0
: Reserved bit (The written value is 0. The read value is 1.)
• RX,W0
: Reserved bit (The written value is 0. The read value is indeterminate.)
• R/W1
: Reserved bit (The written value is 1. The read value is the value written.)
• R1/W1
: Reserved bit (The written value is 1. The read value is 1.)
• R0,W1
: Reserved bit (The written value is 1. The read value is 0.)
• RX,W1
: Reserved bit (The written value is 1. The read value is indeterminate.)
• RX/WX
: Undefined bit (The read value is indeterminate. Writing does not affect the operation.)
• R0/WX
: Undefined bit (The read value is 0. Writing does not affect the operation.)
Chapter 2 MB91230 Overview
1.Overview
Chapter 2
MB91230 Overview
1. Overview
MB91230 series are general-purpose Fujitsu 32-bit RISC microcontroller which is designed for embedded control
required for high-speed real-time processing of consumer devices. CPU employs FR60Lite which is compatible with FR
families.
MB91230 series have embedded LCD controller.
2. Features
2.1 FR60Lite CPU Core
• 32-bit RISC, load/store architecture, pipeline 5 grades
• Maximum operating frequency: CLKB=33.6MHz (MAX)
(Source oscillation=4.2MHz, multiplied by 8 (PLL clock multiplier method))
• 16-bit fixed-length instruction (Base instruction)
• Instruction-execution rate: 1 command/1 cycle
• Instructions suitable for embedded application
•
Transfer command between memories
•
Bit-processing instruction
•
Barrel-shift instructions
• Instructions supporting C-language
• Function's enter command /exit command
• Multi-load/store command of register contents
• Assembler statement is also easily available.
Register's interlock function
• Multiplier's embedded application/command level support
•
Signed 32-bit multiplication: 5 cycles
•
Signed 16-bit multiplication: 3 cycles
• Interrupt (PC/PS are saved): 6 cycles (16 priority level)
• Harvard architecture enables simultaneous execution of program access and data access.
• Commands compatible with FR family
11
Chapter 2 MB91230 Overview
2.Features
2.2 Peripheral Function
• Embedded ROM capacity and ROM type
•
MASK ROM: 256KB
•
FLASH ROM: 256KB
• Embedded RAM capacity: 16KB
• General-purpose port: Maximum 98
Of the 98, N channel open drain port: 4
• A/D converter (series-parallel type)
•
Resolution: 10 bits: 8 channels (4 channels x 2 units)
•
Conversion time: 1.69µs (Minimum conversion time)
• D/A converter (R-2R system)
•
Resolution: 8 bits: 2 channels (Stand-alone)
•
Conversion rate: 0.6µs (When 20pF load is applied.)
• External interrupt input: 16 channels
• Bit search module (using REALOS)
Function to search the first bit position of “1”, “0”, “Changed” from MSB (most significant bit) within 1 word.
• UART (Full-duplex double buffer system): 4 channels
•
With parity/without parity selectable.
•
Asynchronous /synchronous communications selectable.
•
Dedicated baud rate timer (U-Timer) is embedded in each channel.
•
External clock is able to use as transfer clock.
•
Parity error, frame error, and overrun error detecting functions
• PPG: 16 bit × 6 channels
• Up/down counter: 2 channels (8 bits x 2 channels or 16 bits x 1 channel)
• Reload timer: 16 bits × 4 channels
• Free-run timer: 16 bits × 2 channels
• Clock timer: 15 bits × 1 channel
• PWC: 8 bits × 2 channels
• Input capture: 2 channels
Operates simultaneously with free-run timer 0.
• Output compare: 4 channels
•
Free-run timer 0 and output compare 0/1 operate simultaneously.
•
Free-run timer 0 and output compare 2/3 operate simultaneously.
• LCD controller: SEG00-31/COM0-3 (This is also used as port.)
• Clock monitor (Peripheral clock output function): 1 channel
• Timebase/watchdog timer (26 bits)
• Real-time clock (counts during the stop.)
• Low-consumption mode: sleep/stop function
• Package: LQFP-120, FLGA-128
• CMOS 0.35um technology
• Power supply:
12
•
MB91V230, MB91D233: 2 power supplies [Internal Logic 3.3V, I/O 5.0V (Except that ADC, DAC
output is 3.3V)]
•
MB91F233L
: Single power supply [3.3V]
input/
Chapter 2 MB91230 Overview
3.Model Configuration
3. Model Configuration
Table 3-1 MB91230-series Model Configuration List
ROM capacity
RAM capacity
Power supply
MB91V230
N/A
24KB
5V, 3.3V
MB91F233
256KB
16KB
5V, 3.3V
Package
PGA-401C
FTP-120P
Checking device
DSU4
FLASH model
N/A
Others
On Chip Debug Support Unit
MB91F233L
256KB
16KB
3.3V
FTP-120P
LGA-128P
FLASH model
N/A
MB91233L
256KB
16KB
3.3V
FTP120P
LGA-128P
MASK model
N/A
Note: For the latest information, see Data Sheet.
13
Chapter 2 MB91230 Overview
4.Block Diagram
4. Block Diagram
The following illustration shows block diagram of MB91230 series.
Figure 4-1 Block Diagram MB91230 Series (MB91V230, MB91F233, MB91F233L, MB91233L)
FR 60Lite
CPU Core
32
32
Bit search
Bus
Converter
ROM /
FLASH
RAM
X0, X1
MD0-2
INIT
X0A, X1A
Clock control
(Clock,
Standby,
Watchdog,
TBT,
32 to 16
Adapter
16
Main-ClockStabilizationTimer)
Clock Timer
VCC3B
Real Time Clock
Interrupt
controller
INT0-15
SIN0-3
SOT0-3
SCK0-3
External memory
interface
(MB91230 does
not support this
interface.)
32
PORT I/F
Clock Monitor
LCDC, driver,
and internal
reference voltage
Vcc
PORTs
CKOT
COM0-3
SEG0-31
V0-3
Up/down counter
0-1
AIN0-1
BIN0-1
ZIN0-1
Reload timer 0-3
TO0-3
External interrupt
0-15
UART 0-3
0-5
PPG 0-5
PPG0-5
UU-TIMER 0-3
IC0-1
IC0
AN0-3
ADTG
AVRH
4ch input
10/8-bit A/D 0
Input Capture 0-1
Free Run Timer 0-1
Output compare 0-1
CKI0
OP0-1
AN4-7
ADTG
4ch input
10/8-bit A/D 1
Free Run Timer 1
Output compare 2-3
CKI1
OP2-3
2ch output
8-bit D/A 0-1
8Bit-PWC 0-1
AVcc
DA0-1
PWI0-1
: Trigger signal
Note: For dual-purpose port, see “7. Pin Assignment Diagram (Page No.17)” or “1. Pin Function List (Page
No.25)“.
14
Chapter 2 MB91230 Overview
5.CPU
5. CPU
5.1 General-purpose Register
Registers R0 through R15 are general-purpose register. These registers are used as accumulator and memory access
pointer for various computing.
Figure 5-1 General-purpose Register
32 bits
[Initial value]
R0
R1
XXXX XXXXH
R12
R13
R14
R15
AC
FP
SP
XXXX XXXXH
0000 0000H
Of 16 registers, the following registers are prepared for special application. Therefore, some instructions are enhanced.
• R13: Virtual accumulator
• R14: Frame pointer
• R15: Stack pointer
Initial value after reset is indeterminate for R0 through R14. Initial value after reset is 00000000H (SSP value) for R15.
5.2 Dedicated Register List
Each register consists of 32 bits.
Figure 5-2 Dedicated Register List
Program counter
(PC)
Program status
(PS)
Table-base register
(TBR)
Return pointer
(RP)
-
ILM
-
SCR
CCR
System stack pointer (SSP)
User stack pointer
(USP)
Multiplier/division
result register
(MDH)
(MDL)
Dedicated registers are used for special purpose. There are Program counter (PC), Program status (PS), Table-base
register (TBR), Return pointer (RP), System stack pointer (SSP), User stack pointer (USP) and multiplier/division results
register (MDH/MDL).
15
Chapter 2 MB91230 Overview
6.Memory Map
6. Memory Map
Figure 6-1 Memory Map
MB91F233
MB91F233L
MB91233L
MB91V230
Direct
addressing area
0000 0000H
I/O
0000 0400H
I/O
0001 0000H
Disable access
0001 0000H
Disable access
Embedded RAM
24KB
0003 C000H
Embedded RAM
16KB
Disable access
0004 0000H
Disable access
Emulation
SRAM area
512KB
000C 0000H
Disable access
0010 0000H
0003 A000H
0004 0000H
I/O map reference
I/O
I/O
0008 0000H
0010 0000H
FFFF FFFFH
16
FFFF FFFFH
Embedded
FLASH
ROM 256KB
Disable access
Chapter 2 MB91230 Overview
7.Pin Assignment Diagram
7. Pin Assignment Diagram
■ MB91F233, MB91F233L and MB91233L (LQFP-120 package)
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
P25/SOT2
P24/SIN2
P23/PWI1/OP3
P22/PWI0/OP2
P21/CKI1/OP1
P20/CKI0/OP0
P17/INT7
P16/INT6
P15/INT5
P14/INT4
P13/INT3
P12/INT2
X0
X1
VSS
VCC
P11/INT1
P10/INT0
P07/IC1
P06/IC0
P05/SCK1
P04/SOT1
P03/SIN1
P02/SCK0
P01/SOT0
P00/SIN0
V3
V2
V1
V0
Figure 7-1 Pin Assignment Diagram of LQFP-120
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
MB91230 Series
Pin Assign
LQFP-120
INIT
MD0
MD1
MD2
P73/COM3
P72/COM2
P71/COM1
P70/COM0
P67/SEG31 *
P66/SEG30 *
P65/SEG29 *
P64/SEG28 *
PB3/SEG27
PB2/SEG26
VSS
VCC
PB1/SEG25
PB0/SEG24
PA7/SEG23
PA6/SEG22
PA5/SEG21
PA4/SEG20
PA3/SEG19
PA2/SEG18
PA1/SEG17
PA0/SEG16
P97/SEG15
P96/SEG14
P95/SEG13
P94/SEG12
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P57/INT15/TIN0/ADTG0
PF3/TOT3
PF4/TIN3/ADTG1
PD0/DA0
PD1/DA1
AVCC
AVRH
AVSS
PC0/AN0
PC1/AN1
PC2/AN2
PC3/AN3
PC4/AN4
PC5/AN5
PC6/AN6
PC7/AN7
VSS
VCC3IO
P80/SEG0
P81/SEG1
P82/SEG2
P83/SEG3
P84/SEG4
P85/SEG5
P86/SEG6
P87/SEG7
P90/SEG8
P91/SEG9
P92/SEG10
P93/SEG11
P26/SCK2
P27/SIN3
P30/SOT3
P31/SCK3
P32/AIN0
P33/BIN0
P34/ZIN0
P35/AIN1
P36/BIN1
P37/ZIN1
P40/PPG0
P41/PPG1
X0A
X1A
VCC3B
VSS
VCC3
P42/PPG2
P43/PPG3
P44/TOT0
P45/TOT1
P46/TOT2
P47/CKOT
P50/INT8
P51/INT9
P52/INT10
P53/INT11/PPG4
P54/INT12/PPG5
P55/INT13/TIN2
P56/INT14/TIN1
* Open Drain
17
Chapter 2 MB91230 Overview
7.Pin Assignment Diagram
■ MB91F233L and MB91233L (FLGA-128 package)
Figure 7-2 Pin Assignment Diagram of FLGA-128
18
Chapter 2 MB91230 Overview
7.Pin Assignment Diagram
■ Association between FLGA pin and signal of MB91F233L and MB91233L
This table shows the association between FLGA pin and signal of MB91F233L and MB91233L.
19
Chapter 2 MB91230 Overview
8.Package
8. Package
■ LQFP-120 package (FTP-120P-M05): MB91F233, MB91F233L and MB91233L
Figure 8-1 External Dimension of FTP-120P-M05
Plastic, LQFP, 120 pins
0.40mm
Lead pitch
Package width x
Package length
14.0 x 14.0mm
Lead shape
Gull-wing
Sealing method
Plastic mold
Mounting height
1.70mm MAX
Mass
0.62g
(FPT-120P-M05)
Plastic, LQFP, 120 pins
(FPT-120P-M05)
90
* Pin width and pin thickness includes coating thickness.
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 -0.10
+.008
(Mounting height)
.059 -.004
INDEX
120
31
"A"
LEAD No.
1
0.40(.016)
30
0.07(.003)
M
(Stand off)
0.45/0.75
(.018/.030)
C
20
1998 FUJITSU LIMITED F120006S-3C-4
0.25(.010)
Unit: mm (inches)
Chapter 2 MB91230 Overview
8.Package
FLGA-128 package (LGA-128P-M01):MB91F233L and MB91233L
21
Chapter 2 MB91230 Overview
8.Package
Figure 8-2 External Dimension of LGA-128P-M01
22
Chapter 2 MB91230 Overview
8.Package
The illustration below shows appearance of MB91V230 package (PGA-401C-A02).
Figure 8-3 External Dimension of PGA-401C-A02
Ceramic, PGA, 401 pins
Lead pitch
2.54 interstitial
Pin matrix
37
Sealing method
Metal sealing
(PGA-401C-A02)
Ceramic, PGA, 401 pins
(PGA-401C-A02)
SQ
2.54 (.100) TYP
DIA
1.00 (.039) DIA TYP
(4 PLCS)
45.72 (1.800)
REF
1.02 (.040) C TYP
(4 PLCS)
INDEX AREA
EXTRA INDEX PIN
5.27 (.207)
MAX
C
1994 FUJITSU LIMITED R401002SC-2-2
Unit: mm (inches)
23
Chapter 2 MB91230 Overview
8.Package
24
Chapter 3 Basic Information
1.Pin Function List
Chapter 3
Basic Information
This chapter describes MB91230 series basic information including pin function list, circuit type, I/O map, vector table
and pin status table for each mode.
1. Pin Function List
Table 1-1 Pin Function Table
Pin number
(FPT -120)
Pin number
(LGA-128)
1
A1
2
C2
3
C3
4
B1
5
E4
6
D2
7
C1
8
D3
9
E2
10
D1
11
F4
12
E3
13
14
E1
F3
15
Pin name
I/O circuit
type
Function
G2
SCK2
P26
SIN3
P27
SOT3
P30
SCK3
P31
AIN0
P32
BIN0
P33
ZIN0
P34
AIN1
P35
BIN1
P36
ZIN1
P37
PPG0
P40
PPG1
P41
X0A
X1A
VCC3B
N/A
Power-supply pin for backup (RTC)
VSS
N/A
Power-supply pin (GND)
VCC3
N/A
Power-supply pin (3.3V internal logic)
16
F1
17
G4, G3
18
G1
19
H2
20
H4
21
H1
22
J2
PPG2
P42
PPG3
P43
TOT0
P44
TOT1
P45
TOT2
P46
D
D
B
B
B
B
B
B
B
B
D
D
L
D
D
D
D
D
Clock input and output for UART2
General-purpose input/output port
Data input for UART3
General-purpose input/output port
Data input for UART3
General-purpose input/output port
Clock input and output for UART3
General-purpose input/output port
Input of up/down counter 0
General-purpose input/output port
Input of up/down counter 0
General-purpose input/output port
Input of up/down counter 0
General-purpose input/output port
Input of up/down counter 1
General-purpose input/output port
Input of up/down counter 1
General-purpose input/output port
Input of up/down counter 1
General-purpose input/output port
PPG0 output
General-purpose input/output port
PPG1 output
General-purpose input/output port
Subclock oscillation pin (32kHz)
PPG2 output
General-purpose input/output port
PPG3 output
General-purpose input/output port
Reload timer 0 output port
General-purpose input/output port
Reload timer 1 output port
General-purpose input/output port
Reload timer 2 output port
General-purpose input/output port
25
Chapter 3 Basic Information
1.Pin Function List
Table 1-1 Pin Function Table
Pin number
(FPT -120)
Pin number
(LGA-128)
23
H3
24
J1
25
K2
26
J3
27
K1
28
L2
29
J4
30
L1
31
M1
32
L3
33
K3
34
M2
35
J5
36
L4
37
M3
38
K4
39 - 46
47
48
49 - 56
57 - 64
65 - 72
26
Pin name
CKOT
P47
INT8
P50
INT9
P51
INT10
P52
PPG4
INT11
P53
PPG5
INT12
P54
TIN2
INT13
P55
TIN1
INT14
P56
ADTG0
TIN0
INT15
P57
TOT3
PF3
ADTG1
TIN3
PF4
DA0
PD0
DA1
PD1
AVCC
AVRH
AVSS
M4, J6, K5, M5, L6, AN0 - AN7
K6, L7, M6
PC0 - PC7
VSS
J7
K7
VCC3IO
SEG0 - 7
P80 - P87
M10, L11, J9, M11, SEG8 - 15
M12, K11, K10, L12 P90 - P97
H9, J11, K12, J10, SEG16 - 23
H11, J12, G9, H10 PA0 - PA7
L8,J8,M8,
L9,K8,M9, L10,K9
I/O circuit
type
D
C
C
C
C
C
C
C
C
D
D
F
F
N/A
Function
Clock monitor function output pin
General-purpose input/output port
External interrupt input
General-purpose input/output port
External interrupt input
General-purpose input/output port
External interrupt input
General-purpose input/output port
PPG4 output
External interrupt input
General-purpose input/output port
PPG5 output
External interrupt input
General-purpose input/output port
Reload timer 2 event input pin
External interrupt input
General-purpose input/output port
Reload timer 1 event input pin
External interrupt input
General-purpose input/output port
A/D converter 0 external trigger input pin
Reload timer 0 event input pin
External interrupt input
General-purpose input/output port
Reload timer 3 output port
General-purpose input/output port
A/D converter 1 external trigger input pin
Reload timer 3 event input pin
General-purpose input/output port
D/A converter 0 output pin
General-purpose input/output port
D/A converter 1 output pin
General-purpose input/output port
Analog power supply (for A/D and D/A converters)
N/A
Analog reference power supply (for A/D converter)
N/A
Analog circuit GND level input (for A/D and D/A converters)
E
A/D converter analog input pin
General-purpose input/output port
N/A
Power-supply pin (GND)
N/A
Power-supply pin (Also used as analog pin I/O.)
I
I
I
LCDC controller/driver's LCD segment output pin
General-purpose input/output port
LCDC controller/driver's LCD segment output pin
General-purpose input/output port
LCDC controller/driver's LCD segment output pin
General-purpose input/output port
Chapter 3 Basic Information
1.Pin Function List
Table 1-1 Pin Function Table
Pin number
(FPT -120)
Pin number
(LGA-128)
73, 74
H12, H11
75
G10
VCC
N/A
76
F11
VSS
N/A
77, 78
79 - 82
83 - 86
87 - 89
90
91 - 94
95
96
97
98
99
100
101
102
103
104
Pin name
SEG24, 25
PB0, PB1
SEG26, 27
PB2, PB3
SEG28 - 31
F10,E11, E9,D11
P64 - P67
COM0 - 3
E10, D12, C11, D10
P70 - P73
C12, B11, D9
MOD2, 1, 0
B12
INIT
A12, B10, C10, A11 V0 - V3
SIN0
D8
P00
SOT0
B9
P01
SCK0
A10
P02
SIN1
C9
P03
SOT1
B8
P04
SCK1
A9
P05
IC0
D7
P06
IC1
C8
P07
INT0
A8
P10
INT1
B7
P11
G12, F9
I/O circuit
type
I
I
J
I
H
G
N/A
D
D
D
D
D
D
D
D
A
A
Function
LCDC controller/driver's LCD segment output pin
General-purpose input/output port
Power-supply pin (5V I/O) MB91V230/F233
Power-supply pin (3.3V internal logic, I/O) MB91F233L/MB91233L
Power-supply pin (GND)
LCDC controller/driver's LCD segment output pin
General-purpose input/output port
LCDC controller/driver's LCD segment output pin
General-purpose input/output port (N channel-OD)
LCDC controller/driver's common pin
General-purpose input/output port
Mode input pin
External reset input
LCD controller/driver's reference power-supply input pin
Data input for UART0
General-purpose input/output port
Data output for UART0
General-purpose input/output port
Clock input and output for UART0
General-purpose input/output port
Data input for UART1
General-purpose input/output port
Data output for UART1
General-purpose input/output port
Clock input and output for UART1
General-purpose input/output port
Input capture input 0
General-purpose input/output port
Input capture input 1
General-purpose input/output port
External interrupt input
General-purpose input/output port
External interrupt input
General-purpose input/output port
Power-supply pin (5V I/O)
Power-supply pin (3.3V internal logic, I/O)
105
C7
VCC
N/A
106
B6
VSS
N/A
Power-supply pin (GND)
107
108
A7
C6
K
Main clock oscillation pin
109
A6
110
B5
111
D5
X1
X0
INT2
P12
INT3
P13
INT4
P14
A
A
A
External interrupt input
General-purpose input/output port
External interrupt input
General-purpose input/output port
External interrupt input
General-purpose input/output port
27
Chapter 3 Basic Information
1.Pin Function List
Table 1-1 Pin Function Table
Pin number
(FPT -120)
Pin number
(LGA-128)
112
B4
113
C5
114
A4
115
B3
116
C4
117
A3
118
B2
119
D4
120
A2
(38)
L5
A5, D6, E12, F2,
F12, M7
N/A
28
Pin name
I/O circuit
type
Function
INT5
P15
INT6
P16
INT7
P17
CKI0
OP0
P20
CKI1
OP1
P21
PWI0
OP2
P22
PWI1
OP3
P23
SIN2
P24
SOT2
P25
AVRL
N/A
External interrupt input
General-purpose input/output port
External interrupt input
General-purpose input/output port
External interrupt input
General-purpose input/output port
Free-run timer 0 external clock input pin
Output compare 0 output pin
General-purpose input/output port
Free-run timer 1 external clock input pin
Output compare 1 output pin
General-purpose input/output port
Pulse-width counter 0 input
Output compare 2 output pin
General-purpose input/output port
Pulse-width counter 1 input
Output compare 3 output pin
General-purpose input/output port
Data input for UART2
General-purpose input/output port
Data output for UART2
General-purpose input/output port
Analog reference power supply (for A/D converter)
NC
N/A
Unconnected pin
A
A
A
D
D
D
D
D
D
Chapter 3 Basic Information
2.I/O Circuit Type
2. I/O Circuit Type
Group
Circuit
Description
Pull-up control
P
A
P
Output trigger Pch
N
Output trigger Nch
Hysteresis input
With pull-up control (50KΩ)
CMOS level output
IOH=4mA / IOL=4mA
CMOS hysteresis input
(With standby control. When Hi-z stops, “L”)
Standby control
Pull-up control
P
P
Output trigger Pch
N
Output trigger Nch
B
Hysteresis input
Standby control
Test pin for Flash
With pull-up control (50KΩ)
CMOS level output
IOH=4mA / IOL=4mA
CMOS hysteresis input
(With standby control. When Hi-z stops, “L”)
Test pin for FLASH
Analog switch control
C
P
Output trigger Pch
N
Output trigger Nch
Hysteresis input
CMOS level output
IOH=4mA / IOL=4mA
CMOS hysteresis input
(With standby control. When Hi-z stops, “L”)
Standby control
P
Output trigger Pch
N
Output trigger Nch
D
Hysteresis input
Standby control
Test pin for Flash
CMOS level output
IOH=4mA / IOL=4mA
CMOS hysteresis input
(With standby control. When Hi-z stops, “L”)
Test pin for FLASH
Analog switch control
E
P
Output trigger Pch
N
Output trigger Nch
Hysteresis input
Standby control
Analog input
CMOS level output
IOH=4mA / IOL=4mA
CMOS hysteresis input
(With standby control. When Hi-z stops, “L”)
Also used for analog input.
Analog switch control
29
Chapter 3 Basic Information
2.I/O Circuit Type
Group
Circuit
F
Description
P
Output trigger Pch
N
Output trigger Nch
Hysteresis input
Standby control
Analog output
CMOS level output
IOH=4mA / IOL=4mA
CMOS hysteresis input
(With standby control. When Hi-z stops, “L”)
Also used for analog output.
Analog switch control
P
G
P
With pull-up (50KΩ)
IOH=4mA / IOL=4mA
CMOS hysteresis input
N
Hysteresis input
Low-impedance input
N
High-impedance input
N
H
High-pressure detection output
N
High withstanding pressure input
CMOS input
N
I
P
Output trigger Pch
N
Output trigger Nch
CMOS level output
IOH=4mA / IOL=4mA
CMOS hysteresis input
(With standby control. When Hi-z stops, “L”)
Also used for LCDC output.
Hysteresis input
Standby control
LCDC output
CMOS level output
(N channel open drain)
IOL=20mA
CMOS hysteresis input
(With standby control. When Hi-z stops, “L”)
Also used for LCDC output.
P
N
J
Output trigger Nch
Hysteresis input
Standby control
LCDC output
X1
Oscillation output
K
Main oscillation circuit
(With standby control)
X0
Standby control
30
Chapter 3 Basic Information
2.I/O Circuit Type
Group
Circuit
Description
X1A
Oscillation output
L
X0A
Sub-oscillation circuit
31
Chapter 3 Basic Information
3.I/O Map
3. I/O Map
This section shows the association between memory space and each register of peripheral resources.
• Table convention
Address
000000H
Address offset/Register name
+0
+1
+2
PDRD[R/W]
PDR2[R/W]
PDR1[R/W]
xxxxxxxx
xxxxxxxx
xxxxxxxx
+3
PDR3[R/W]
xxxxxxxx
MSB
Block
T-unit
Port data register
LSB
Data access attribute (B: Byte, H: Half-byte, W: Word)
Read/Write attribute (R: Read, W: Write)
Register name (First column register is 4n address,
Second column register is 4n+2 address...)
Leftmost register address
(For Word access, first register becomes MSB side of the data.)
Note: Bit value of register shows initial values as follows.
•"1": Initial value is "1".
• "0": Initial value is "0".
• "X": Initial value is indeterminate.
• "N/A": No physical register exists in the position.
Do not use other data access attributes to access data.
32
Chapter 3 Basic Information
3.I/O Map
Table 3-1 I/O Map
Address
Address offset value / Register name
Block
+0
+1
+2
+3
000000H
PDR0 [R/W] B
XXXXXXXX
PDR1 [R/W] B
XXXXXXXX
PDR2 [R/W] B
XXXXXXXX
PDR3 [R/W] B
XXXXXXXX
000004H
PDR4 [R/W] B
XXXXXXXX
PDR5 [R/W] B
XXXXXXXX
PDR6 [R/W] B
XXXX----
PDR7 [R/W] B
----XXXX
000008H
PDR8 [R/W] B
XXXXXXXX
PDR9 [R/W] B
XXXXXXXX
PDRA [R/W] B
XXXXXXXX
PDRB [R/W] B
----XXXX
00000CH
PDRC [R/W] B
XXXXXXXX
PDRD [R/W] B
------XX
N/A
PDRF [R/W]
---XX---
000010H
|
00003CH
N/A
N/A
N/A
N/A
000040H
EIRR0 [R/W] B, H, W
00000000
ENIR0 [R/W] B, H, W
00000000
ELVR0 [R/W] B, H, W
00000000 00000000
External interrupt
(INT0 - 7)
000044H
DICR [R/W] B, H, W
-------0
N/A
N/A
Delayed interrupt
000048H
TMRLR0 [W] H
XXXXXXXX XXXXXXXX
TMR0 [R] H
XXXXXXXX XXXXXXXX
00004CH
N/A
TMCSR0 [R/W] B, H
----0000 00000000
000050H
TMRLR1 [W] H
XXXXXXXX XXXXXXXX
TMR1 [R] H
XXXXXXXX XXXXXXXX
000054H
N/A
TMCSR1 [R/W] B, H
----0000 00000000
000058H
TMRLR2 [W] H
XXXXXXXX XXXXXXXX
TMR2 [R] H
XXXXXXXX XXXXXXXX
00005CH
N/A
TMCSR2 [R/W] B, H
----0000 00000000
000060H
000064H
000068H
00006CH
000070H
SSR0 [R/W] B, H, W
00001000
SIDR0 [R] B, H, W
SODR0[W] B, H, W
XXXXXXXX
UTIM0 [R] H (UTIMR0 [W] H)
00000000 00000000
SSR1 [R/W] B, H, W
00001000
SIDR1 [R] B, H, W
SODR1[W] B, H, W
XXXXXXXX
UTIM1 [R] H (UTIMR1 [W] H)
00000000 00000000
SSR2 [R/W] B, H, W
00001000
SIDR2 [R] B, H, W
SODR2 [W] B, H, W
XXXXXXXX
000074H
UTIM2 [R] H (UTIMR1 [W] H)
00000000 00000000
000078H
ADCSH0 [R/W] B, H, W ADCSL0 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
Reload timer 0
Reload timer 1
Reload timer 2
SMR0 [R/W] B, H, W
00--0-0-
UART0
N/A
UTIMC0 [R/W] B
0--00001
U-TIMER0
SCR1 [R/W] B, H, W
00000100
SMR1 [R/W] B, H, W
00--0-0-
UART1
N/A
UTIMC1 [R/W] B
0--00001
U-TIMER1
SCR2 [R/W] B, H, W
00000100
SMR2 [R/W] B, H, W
00--0-0-
UART2
N/A
UTIMC2 [R/W] B
0--00001
U-TIMER2
ADCT0 [R/W] H, W
000-0000 -000--00
ADTH00 [R] B, H, W
000000XX
ADTL00 [R] B, H, W
XXXXXXXX
ADTH01 [R] B, H, W
000000XX
ADTH01 [R] B, H, W
XXXXXXXX
000080H
ADTH02 [R] B, H, W
000000XX
ADTL02 [R] B, H, W
XXXXXXXX
ADTH03 [R] B, H, W
000000XX
ADTL02 [R] B, H, W
XXXXXXXX
ADCSH1 [R/W] B, H, W ADCSL1 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
Unused
SCR0 [R/W] B, H, W
00000100
00007CH
000084H
Port data
register
A/D converter 0
(Series-parallel type)
ADCT1 [R/W] H, W
000-0000 --000--00
000088H
ADTH10 [R] B, H, W
000000XX
ADTL10 [R] B, H, W
XXXXXXXX
ADTH11 [R] B, H, W
000000XX
ADTL11 [R] B, H, W
XXXXXXXX
00008CH
ADTH12 [R] B, H, W
000000XX
ADTL12 [R] B, H, W
XXXXXXXX
ADTH13 [R] B, H, W
000000XX
ADTL13 [R] B, H, W
XXXXXXXX
A/D converter 1
(Series-parallel type)
33
Chapter 3 Basic Information
3.I/O Map
Table 3-1 I/O Map
Address
+1
+2
+3
000090H
N/A
N/A
DACR1 [R/W] B, H
-------0
DACR0 [R/W] B, H
-------0
000094H
N/A
N/A
DADR1 [R/W] B, H
XXXXXXXX
DADR0 [R/W] B, H
XXXXXXXX
000098H
LCDCMR [R/W] B, H, W
N/A
LCR0 [R/W] B, H, W
00010000
LCR1 [R/W] B, H, W
00000000
----0000
00009CH
VRAM0 [R/W] B, H, W
XXXXXXXX
VRAM1 [R/W] B, H, W
XXXXXXXX
VRAM2 [R/W] B, H, W
XXXXXXXX
VRAM3 [R/W] B, H, W
XXXXXXXX
0000A0H
VRAM4 [R/W] B, H, W
XXXXXXXX
VRAM5 [R/W] B, H, W
XXXXXXXX
VRAM6 [R/W] B, H, W
XXXXXXXX
VRAM7 [R/W] B, H, W
XXXXXXXX
0000A4H
VRAM8 [R/W] B, H, W
XXXXXXXX
VRAM9 [R/W] B, H, W
XXXXXXXX
VRAM10 [R/W] B, H, W
XXXXXXXX
VRAM11 [R/W] B, H, W
XXXXXXXX
0000A8H
VRAM12 [R/W] B, H, W
XXXXXXXX
VRAM13 [R/W] B, H, W
XXXXXXXX
VRAM14 [R/W] B, H, W
XXXXXXXX
VRAM15 [R/W] B, H, W
XXXXXXXX
0000ACH
CKR [R/W] B, H, W
----0000
N/A
N/A
N/A
0000B0H
RCR1 [W] B, H, W
00000000
RCR0 [W] B, H, W
00000000
UDCR1 [R] B, H, W
00000000
UDCR0 [R] B, H, W
00000000
0000B4H
CCR0 [R/W] B, H, W
00000000 00001000
N/A
CSR0 [R/W] B, H, W
00000000
0000B8H
CCR1 [R/W] B, H, W
00000000 00001000
N/A
CSR1 [R/W] B, H, W
00000000
0000BCH
0000C0H
Block
D/A converter
LCD
controller/
driver
Clock monitor
Up/down
counter 0, 1
N/A
N/A
N/A
N/A
Unused
SSR3 [R/W] B, H, W
00001000
SIDR3 [R] B, H, W
SODR3[W] B, H, W
XXXXXXXX
SCR3 [R/W] B, H, W
00000100
SMR3 [R/W] B, H, W
00--0-0-
UART3
-
UTIMC3[R/W] B
0--00001
U-TIMER3
0000C4H
UTIM3 [R] H (UTIMR [W] H)
00000000 00000000
0000C8H
TMRLR3 [W] H
XXXXXXXX XXXXXXXX
TMR3 [R] H
XXXXXXXX XXXXXXXX
0000CCH
N/A
TMCSR3 [R/W] B, H
---00000 00000000
0000D0H
EIRR1 [R/W] B, H, W
00000000
ENIR1 [R/W] B, H, W
00000000
ELVR1 [R/W] B, H, W
00000000 00000000
Reload timer 3
External interrupt
(INT8 - 16)
0000D4H
TCDT0 [R/W] H, W
00000000 00000000
N/A
TCCS0 [R/W] B, H, W
00000000
Free-run timer 0
0000D8H
TCDT1 [R/W] H, W
00000000 00000000
N/A
TCCS1 [R/W] B, H, W
00000000
Free-run timer 1
0000DCH
IPCP1 [R] H, W
XXXXXXXX XXXXXXXX
0000E0H
N/A
N/A
IPCP0 [R] H, W
XXXXXXXX XXXXXXXX
N/A
ICS01 [R/W] B, H, W
00000000
0000E4H
OCCP1 [R/W] H, W
XXXXXXXX XXXXXXXX
OCCP0 [R/W] H, W
XXXXXXXX XXXXXXXX
0000E8H
OCCP3 [R/W] H, W
XXXXXXXX XXXXXXXX
OCCP2 [R/W] H, W
XXXXXXXX XXXXXXXX
0000ECH
OCS23 [R/W] B, H, W
---0—-00 0000--00
OCS01 [R/W] B, H, W
---0—00 0000--00
0000F0H
34
Address offset value / Register name
+0
PWCC0 [R/W] B, H, W
0---00-0
PWCD0 [R] B, H, W
XXXXXXXX
PWCC1 [R/W] B, H, W
0---00-0
PWCD1 [R] B, H, W
XXXXXXXX
Input
capture
Output
compare
PWC0, 1
Chapter 3 Basic Information
3.I/O Map
Table 3-1 I/O Map
Address
Address offset value / Register name
+1
0000F4H
N/A
WTDBL [R/W] B
------0
0000F8H
N/A
WTBR0 [R/W] B
---XXXXX
WTBR1 [R/W] B
XXXXXXXX
WTBR2 [R/W] B
XXXXXXXX
0000FCH
WTHR [R/W] B, H
---XXXXX
WTMR [R/W] B, H
--XXXXXX
WTSR [R/W] B
--XXXXXX
N/A
000100H
|
000114H
N/A
N/A
N/A
N/A
Unused
N/A
GCN20 [R/W] B
00000000
PPG
GCN10 [R/W] H
00110010 00010000
000118H
+2
+3
Block
+0
WTCR [R/W] B, H
00000000 000-00-X
00011CH
N/A
N/A
000120H
PTMR0 [R] H
11111111 11111111
PCSR0 [W] H
XXXXXXXX XXXXXXXX
000124H
PDUT0 [W] H
XXXXXXXX XXXXXXXX
PCN0 [R/W] B, H
00000000 00000000
000128H
PTMR1 [R] H
11111111 11111111
PCSR1 [W] H, W
XXXXXXXX XXXXXXXX
00012CH
PDUT1 [W] H
XXXXXXXX XXXXXXXX
PCN1 [R/W] B, H
00000000 00000000
000130H
PTMR2 [R] H
11111111 11111111
PCSR2 [W] H
XXXXXXXX XXXXXXXX
000134H
PDUT2 [W] H
XXXXXXXX XXXXXXXX
PCN2 [R/W] B, H
00000000 00000000
000138H
PTMR3 [R] H
11111111 11111111
PCSR3 [W] H
XXXXXXXX XXXXXXXX
00013CH
PDUT3 [W] H
XXXXXXXX XXXXXXXX
PCN3 [R/W] B, H
00000000 00000000
000140H
PTMR4 [R] H
11111111 11111111
PCSR4 [W] H
XXXXXXXX XXXXXXXX
PDUT4 [W] H
XXXXXXXX XXXXXXXX
PTMR5 [R] H
11111111 11111111
PCN4 [R/W] B, H
00000000 00000000
PCSR5 [W] H
XXXXXXXX XXXXXXXX
PDUT5 [W] H
XXXXXXXX XXXXXXXX
PCN5 [R/W] B, H
00000000 00000000
000144H
000148H
00014CH
Real-time
clock
Unused
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
000150H
|
0001FCH
N/A
N/A
N/A
N/A
Unused
000200H
|
0003ECH
N/A
N/A
N/A
N/A
Unused
0003F0H
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Bit search
35
Chapter 3 Basic Information
3.I/O Map
Table 3-1 I/O Map
Address
36
Address offset value / Register name
+0
+1
+2
+3
000400H
DDR0 [R/W] B
00000000
DDR1 [R/W] B
00000000
DDR2 [R/W] B
00000000
DDR3 [R/W] B
00000000
000404H
DDR4 [R/W] B
00000000
DDR5 [R/W] B
00000000
DDR6 [R/W] B
0000----
DDR7 [R/W] B
----0000
000408H
DDR8 [R/W] B
00000000
DDR9 [R/W] B
00000000
DDRA [R/W] B
00000000
DDRB [R/W] B
----0000
00040CH
DDRC [R/W] B
00000000
DDRD [R/W] B
------00
N/A
DDRF [R/W] B
---00---
000410H
|
00041CH
N/A
N/A
N/A
N/A
000420H
PFR0 [R/W] B
--00-00-
PFR1 [R/W] B
--------
PFR2 [R/W] B
-00-0000
PFR3 [R/W] B
------00
000424H
PFR4 [R/W] B
00000000
PFR5 [R/W] B
---00---
PFR6 [R/W] B
0000----
PFR7 [R/W] B
----0000
000428H
PFR8 [R/W] B
00000000
PFR9 [R/W] B
00000000
PFRA [R/W] B
00000000
PFRB [R/W] B
----0000
00042CH
PFRC [R/W] B
--------
PFRD [R/W] B
------00
N/A
PFRF [R/W] B
----0---
000430H
|
00043CH
N/A
N/A
N/A
N/A
000440H
ICR00 [R/W] B, H, W
---11111
ICR01 [R/W] B, H, W
---11111
ICR02 [R/W] B, H, W
---11111
ICR03 [R/W] B, H, W
---11111
000444H
ICR04 [R/W] B, H, W
---11111
ICR05 [R/W] B, H, W
---11111
ICR06 [R/W] B, H, W
---11111
ICR07 [R/W] B, H, W
---11111
000448H
ICR08 [R/W] B, H, W
---11111
ICR09 [R/W] B, H, W
---11111
ICR10 [R/W] B, H, W
---11111
ICR11 [R/W] B, H, W
---11111
00044CH
ICR12 [R/W] B, H, W
---11111
ICR13 [R/W] B, H, W
---11111
ICR14 [R/W] B, H, W
---11111
ICR15 [R/W] B, H, W
---11111
000450H
ICR16 [R/W] B, H, W
---11111
ICR17 [R/W] B, H, W
---11111
ICR18 [R/W] B, H, W
---11111
ICR19 [R/W] B, H, W
---11111
000454H
ICR20 [R/W] B, H, W
---11111
ICR21 [R/W] B, H, W
---11111
ICR22 [R/W] B, H, W
---11111
ICR23 [R/W] B, H, W
---11111
000458H
ICR24 [R/W] B, H, W
---11111
ICR25 [R/W] B, H, W
---11111
ICR26 [R/W] B, H, W
---11111
ICR27 [R/W] B, H, W
---11111
00045CH
ICR28 [R/W] B, H, W
---11111
ICR29 [R/W] B, H, W
---11111
ICR30 [R/W] B, H, W
---11111
ICR31 [R/W] B, H, W
---11111
000460H
ICR32 [R/W] B, H, W
---11111
ICR33 [R/W] B, H, W
---11111
ICR34 [R/W] B, H, W
---11111
ICR35 [R/W] B, H, W
---11111
000464H
ICR36 [R/W] B, H, W
---11111
ICR37 [R/W] B, H, W
---11111
ICR38 [R/W] B, H, W
---11111
ICR39 [R/W] B, H, W
---11111
000468H
ICR40 [R/W] B, H, W
---11111
ICR41 [R/W] B, H, W
---11111
ICR42 [R/W] B, H, W
---11111
ICR43 [R/W] B, H, W
---11111
00046CH
ICR44 [R/W] B, H, W
---11111
ICR45 [R/W] B, H, W
---11111
ICR46 [R/W] B, H, W
---11111
ICR47 [R/W] B, H, W
---11111
000470H
|
00047CH
N/A
N/A
N/A
N/A
Block
Data direction
register
Unused
Port function
register
Unused
Interrupt
Unused
Chapter 3 Basic Information
3.I/O Map
Table 3-1 I/O Map
Address
Address offset value / Register name
Block
+0
+1
+2
+3
000480H
RSRR [R/W] B, H
10000000
STCR [R/W] B, H
00110011
TBCR [R/W] B
00XXXX00
CTBR [W] B
XXXXXXXX
000484H
CLKR [R/W] B
00000000
WPR [W] B
XXXXXXXX
DIVR0 [R/W] B, H
00000011
DIVR1 [R/W] B, H
00000000
000488H
N/A
N/A
OSCCR [R/W] B
XXXXXXX0
N/A
Clock control
Standby
Timebase counter
Timebase timer
Watchdog timer
00048CH
WPCR [R/W] B
00---000
N/A
N/A
N/A
clock timer
000490H
OSCR [R/W] B
00---000
N/A
N/A
N/A
Main clock oscillation
stabilization timer
000494H
|
0004FCH
N/A
N/A
N/A
N/A
Unused
000500H
N/A
PCR1 [R/W] B
00000000
N/A
PCR3 [R/W] B
00000000
Pull-up control
register
000504H
|
00051CH
N/A
N/A
N/A
N/A
Unused
000520H
|
0007F8H
N/A
N/A
N/A
N/A
Unused
0007FCH
N/A
MODR *
XXXXXXXX
N/A
N/A
Operation mode
000800H
|
000AFCH
N/A
N/A
N/A
N/A
Unused
000B00H
|
000FFCH
N/A
N/A
N/A
N/A
Unused
001000H
|
001FFCH
N/A
N/A
N/A
N/A
Unused
*: This register is set by mode vector fetch. User cannot access it.
37
Chapter 3 Basic Information
4.Interrupt Vector Table
4. Interrupt Vector Table
This section shows the allocation of interrupt and interrupt vector/interrupt register.
Table 4-1 Interrupt Vector
Interrupt
Reset
Interrupt number
Hexa
Decimal
decimal
0
00
Interrupt level
Offset
TBR default
address
N/A
3FCH
000FFFFCH
Mode vector
1
01
N/A
3F8H
000FFFF8H
Reserved for system
2
02
N/A
3F4H
000FFFF4H
000FFFF0H
Reserved for system
3
03
N/A
3F0H
Reserved for system
4
04
N/A
3ECH
000FFFECH
Reserved for system
5
05
N/A
3E8H
000FFFE8H
000FFFE4H
Reserved for system
6
06
N/A
3E4H
Coprocessor absent trap
7
07
N/A
3E0H
000FFFE0H
000FFFDCH
Coprocessor error trap
8
08
N/A
3DCH
INTE instruction
9
09
N/A
3D8H
000FFFD8H
Instruction break exception
10
0A
N/A
3D4H
000FFFD4H
Operand break trap
11
0B
N/A
3C0H
000FFFD0H
Step trace trap
12
0C
N/A
3CCH
000FFFCCH
NMI request (tool)
13
0D
N/A
3C8H
000FFFC8H
Undefined-instruction exception
14
0E
3C4H
000FFFC4H
3C0H
000FFFC0H
NMI request (This product does not have this interrupt.)
15
0F
N/A
15 (FH) fixed
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
000FFFACH
External interrupt 4
20
14
ICR04
3ACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
ICR09
398H
000FFF98H
Reload timer 1
38
25
19
Reload timer 2
26
1A
ICR10
394H
000FFF94H
UART0 (Receive complete)
27
1B
ICR11
390H
000FFF90H
UART0 (Transmit complete)
28
1C
ICR12
38CH
000FFF8CH
UART1 (Receive complete)
29
1D
ICR13
388H
000FFF88H
UART1 (Transmit complete)
30
1E
ICR14
384H
000FFF84H
UART2 (Receive complete)
31
1F
ICR15
380H
000FFF80H
000FFF7CH
UART2 (Transmit complete)
32
20
ICR16
37CH
UART3 (Receive end)
33
21
ICR17
378H
000FFF78H
UART3 (Transmit end)
34
22
ICR18
374H
000FFF74H
A/D ch0
35
23
ICR19
370H
000FFF70H
A/D ch1
36
24
ICR20
36CH
000FFF6CH
External interrupt 8
37
25
ICR21
368H
000FFF68H
External interrupt 9
38
26
ICR22
364H
000FFF64H
External interrupt 10
39
27
ICR23
360H
000FFF60H
External interrupt 11
40
28
ICR24
35CH
000FFF5CH
Chapter 3 Basic Information
4.Interrupt Vector Table
Table 4-1 Interrupt Vector
Interrupt
External interrupt 12
External interrupt 13
Interrupt number
Hexa
Decimal
decimal
41
29
42
Interrupt level
Offset
TBR default
address
ICR25
358H
000FFF58H
ICR26
354H
000FFF54H
2B
ICR27
350H
000FFF50H
2A
External interrupt 14
43
External interrupt 15
44
2C
ICR28
34CH
000FFF4CH
Real-time clock
45
2D
ICR29
348H
000FFF48H
Main clock oscillation stabilization timer
46
2E
ICR30
344H
000FFF44H
Timebase timer
47
2F
ICR31
340H
000FFF40H
Reload timer 3
48
30
ICR32
33CH
000FFF3CH
Clock timer
49
31
ICR33
338H
000FFF38H
ICR34
334H
000FFF34H
UD counter 0
50
32
UD counter 1
51
33
ICR35
330H
000FFF30H
PPG0/1
52
34
ICR36
32CH
000FFF2CH
PPG2/3
53
35
ICR37
328H
000FFF28H
PPG4/5
54
36
ICR38
324H
000FFF24H
000FFF20H
Free-run timer 0
55
37
ICR39
320H
Free-run timer 1
56
38
ICR40
31CH
000FFF1CH
ICU0 (Import)
57
39
ICR41
318H
000FFF18H
ICU1 (Import)
58
3A
ICR42
314H
000FFF14H
OCU0 (Match)
59
3B
ICR43
310H
000FFF10H
000FFF0CH
OCU1 (Match)
60
3C
ICR44
30CH
OCU2 (Match)
61
3D
ICR45
308H
000FFF08H
OCU3 (Match)
62
3E
ICR46
304H
000FFF04H
Delayed interrupt bit
63
3F
ICR47
300H
000FFF00H
Reserved for system (Used on REALOS.)
64
40
N/A
2FCH
000FFEFCH
Reserved for system (Used on REALOS.)
65
41
N/A
2F8H
000FFEF8H
Reserved for system
66
42
N/A
2F4H
000FFEF4H
000FFEF0H
Reserved for system
67
43
N/A
2F0H
Reserved for system
68
44
N/A
2ECH
000FFEECH
Reserved for system
69
45
N/A
2E8H
000FFEE8H
Reserved for system
70
46
N/A
2E4H
000FFEE4H
Reserved for system
71
47
N/A
2E0H
000FFEE0H
000FFEDCH
Reserved for system
72
48
N/A
2DCH
Reserved for system
73
49
N/A
2D8H
000FFED8H
Reserved for system
74
4A
N/A
2D4H
000FFED4H
Reserved for system
75
4B
N/A
2D0H
000FFED0H
Reserved for system
76
4C
N/A
2CCH
000FFECCH
Reserved for system
77
4D
N/A
2C8H
000FFEC8H
Reserved for system
78
4E
N/A
2C4H
000FFEC4H
000FFEC0H
000FFEBCH
|
000FFC00H
Reserved for system
79
4F
N/A
2C0H
Used for INT instruction
80
|
255
50
|
FF
N/A
2BCH
|
000H
39
Chapter 3 Basic Information
5.Terminal state table according to mode
5. Terminal state table according to mode
It explains the meaning of words and phrases used in the terminal state table according to the mode.
• Input enable： It is meant to be able to input the signal from the outside.
• Input fixed 0：To prevent leakeage by the input opening, the input level is fixed to "0" internally.
• Output Hi-z： The terminal is made high impedance.
• Output hold： The state output immediately before is output as it is.
For instance, the output is maintained when outputting it as an output or a port from the function in the
surrounding.
• Hold the state immediately before：It becomes an input in case of the output or the input in case of the output
immediately before.
Table 5-1 Terminal state table according to mode
Pin No
LQFP LGA
-120 -128
1
2
A1
C2
Pin name
P26/SCK2
P27/SIN3
Port
name
(initial
value)
P26
P27
Specified function
name
Input Output I/O
SCK2
SIN3
-
3
C3
P30/SOT3
P30
-
SOT3
-
4
B1
P31/SCK3
P31
-
-
SCK3
5
E4
P32/AIN0
P32
AIN0
-
-
6
D2
P33/BIN0
P33
BIN0
-
-
7
C1
P34/ZIN0
P34
ZIN0
-
-
8
D3
P35/AIN1
P35
AIN1
-
-
9
E2
P36/BIN1
P36
BIN1
-
-
10
D1
P37/ZIN1
P37
ZIN1
-
-
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
F4
E3
E1
F3
G2
F1
G4
G1
H2
H4
H1
J2
H3
J1
K2
J3
P40
P41
P42
P43
P44
P45
P46
P47
P50
P51
P52
INT8
INT9
INT10
PPG0
PPG1
PPG2
PPG3
TOT0
TOT1
TOT2
CKOT
-
-
27
K1
P53
INT11 PPG4
-
28
L2
P54
INT12 PPG5
-
29
J4
30
L1
P40/PPG0
P41/PPG1
X0A
X1A
VCC3B/VCC
VSS
VCC3/C
P42/PPG2
P43/PPG3
P44/TOT0
P45/TOT1
P46/TOT2
P47/CKOT
P50/INT8
P51/INT9
P52/INT10
P53/INT11/
PPG4
P54/INT12/
PPG5
P55/INT13/
TIN2
P56/INT14/
TIN1
31
M1
40
P57/INT15/
TIN0/ADTG0
P55
P56
P57
INT13
TIN2
INT14
TIN1
INT15
TIN0
ADTG0
-
-
-
-
-
-
State
at Reset
at Sleep
INIT, RST
--
Remarks
at Stop
HIZ=0
HIZ=1
-
Hold the
Hold the
Output Hi-z/
state
state
Input enable immediately immediately
before
before
Output Hi-z
Input fixed 0
The pull-up option can be
selected.
The pull-up option can be
selected.
The pull-up option can be
selected.
The pull-up option can be
selected.
The pull-up option can be
selected.
The pull-up option can be
selected.
The pull-up option can be
selected.
The pull-up option can be
selected.
-
-
-
-
-
Hold the
state
immediately
before
Output Hi-z
Input fixed 0
Hold the
Output Hi-z/
state
Input enable immediately P:Hold the
state
before
immediately P: Output Hi-z
before
F: Input enable
F:Input
enable
-
-
Chapter 3 Basic Information
5.Terminal state table according to mode
Table 5-1 Terminal state table according to mode
Pin No
LQFP LGA
-120 -128
Pin name
Port
name
(initial
value)
PF3
Specified function
name
Input Output
TOT3
TIN3
ADTG1
DA0
DA1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
I/O
-
32
L3
33
K3
34
35
36
37
38
(38)
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
M2
J5
L4
M3
K4
L5
M4
J6
K5
M5
L6
K6
L7
M6
J7
K7
L8
J8
M8
L9
K8
M9
L10
K9
M10
L11
J9
M11
M12
K11
K10
L12
H9
J11
K12
J10
H11
J12
G9
H10
H12
H11
G10
F11
G12
F9
PF3/TOT3
PF4/TIN3/
ADTG1
PD0/DA0
PD1/DA1
AVCC
AVRH
AVSS
AVRL
PC0/AN0
PC1/AN1
PC2/AN2
PC3/AN3
PC4/AN4
PC5/AN5
PC6/AN6
PC7/AN7
VSS
VCC3IO
P80/SEG0
P81/SEG1
P82/SEG2
P83/SEG3
P84/SEG4
P85/SEG5
P86/SEG6
P87/SEG7
P90/SEG8
P91/SEG9
P92/SEG10
P93/SEG11
P94/SEG12
P95/SEG13
P96/SEG14
P97/SEG15
PA0/SEG16
PA1/SEG17
PA2/SEG18
PA3/SEG19
PA4/SEG20
PA5/SEG21
PA6/SEG22
PA7/SEG23
PB0/SEG24
PB1/SEG25
VCC
VSS
PB2/SEG26
PB3/SEG27
79
F10
P64/SEG28 *
P64
-
SEG28
-
80
E11
P65/SEG29 *
P65
-
SEG29
-
PF4
PD0
PD1
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
P80
P81
P82
P83
P84
P85
P86
P87
P90
P91
P92
P93
P94
P95
P96
P97
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
-
State
at Reset
at Sleep
INIT, RST
--
Hold the
Hold the
Output Hi-z/
state
state
Input enable immediately immediately
before
before
-
-
-
Hold the
Hold the
Output Hi-z/
state
state
Input enable immediately immediately
before
before
-
-
Remarks
at Stop
HIZ=0
-
HIZ=1
Output Hi-z
Input fixed 0
-
-
-
Output Hi-z
Input fixed 0
-
-
-
P(Port):
Output Hi-z/
Hold the
Hold the
Input fixed 0
Output Hi-z/
state
state
F(Peripheral):
Input enable immediately immediately
Hold the state
before
before
immediately
before
Output Hi-z/
Input enable
-
-
P(Port):
Output Hi-z/
Hold the
Hold the
Input fixed
state
state
0F(Peripheral):
immediately immediately
Hold the state
before
before
immediately
before
-
Nch-OD Pseudoterminal,
IOL=20mA
Nch-OD Pseudoterminal,
IOL=20mA
41
Chapter 3 Basic Information
5.Terminal state table according to mode
Table 5-1 Terminal state table according to mode
Pin No
LQFP LGA
-120 -128
Pin name
Port
name
(initial
value)
Specified function
name
Input Output
I/O
81
E9
P66/SEG30 *
P66
-
SEG30
-
82
D11
P67/SEG31 *
P67
-
SEG31
-
83
84
85
86
E10
D12
C11
D10
P70/COM0
P71/COM1
P72/COM2
P73/COM3
P70
P71
P72
P73
-
COM0
COM1
COM2
COM3
-
87
C12
MOD2
-
-
-
-
88
B11
MOD1
-
-
-
-
89
D9
MOD0
-
-
-
-
90
91
92
93
94
95
96
97
98
99
100
101
102
B12
A12
B10
C10
A11
D8
B9
A10
C9
B8
A9
D7
C8
INIT
V0
V1
V2
V3
P00/SIN0
P01/SOT0
P02/SCK0
P03/SIN1
P04/SOT1
P05/SCK1
P06/IC0
P07/IC1
P00
P01
P02
P03
P04
P05
P06
P07
SIN0
SIN1
IC0
IC1
103
A8
P10/INT0
P10
INT0
104
B7
P11/INT1
P11
INT1
105
106
107
108
C7
B6
A7
C6
VCC
VSS
X1
X0
-
-
109
A6
P12/INT2
P12
INT2
-
-
110
B5
P13/INT3
P13
INT3
-
-
111
D5
P14/INT4
P14
INT4
-
-
112
B4
P15/INT5
P15
INT5
-
-
113
C5
P16/INT6
P16
INT6
-
-
114
A4
P17/INT7
P17
INT7
-
-
115
116
117
118
119
120
B3
C4
A3
B2
D4
A2
A5,
D6,
E12,
F2,
M7
P20/CKI0/OP0
P21/CKI1/OP1
P22/PWI0/OP2
P23/PWI1/OP3
P24/SIN2
P25/SOT2
P20
P21
P22
P23
P24
P25
CKI0
CKI1
PWI0
PWI1
SIN2
-
OP0
OP1
OP2
OP3
SOT2
-
NC
-
-
-
-
-
42
State
at Reset
at Sleep
INIT, RST
--
Remarks
at Stop
HIZ=0
HIZ=1
P(Port): Output
Hi-z/
Hold the
Hold the
Input fixed
Output Hi-z/
state
state
0F(Peripheral):
Input enable immediately immediately
Hold the state
before
before
immediately
before
Input enable
(INIT 時 )
Input enable
(INIT 時 )
Input enable
(INIT 時 )
Input enable Input enable Input enable
-
-
-
-
-
-
-
-
-
-
Input enable
SOT0
Hold the
SCK0
state
Output Hi-z
SOT1
immediately Input fixed 0
SCK1
Hold the
before
Output Hi-z/
state
Input enable immediately
P:Hold the
before
state
immediately P:Output Hi-z
before
F:Input enable
F:Input
enable
-
Hold the
Output Hi-z/
state
Input enable immediately
before
Nch-OD Pseudoterminal,
IOL=20mA
Nch-OD Pseudoterminal,
IOL=20mA
P:Hold the
state
immediately P:Output Hi-z
before
F:Input enable
F:Input
enable
-
-
The pull-up option can be
selected.
The pull-up option can be
selected.
The pull-up option can be
selected.
The pull-up option can be
selected.
The pull-up option can be
selected.
The pull-up option can be
selected.
The pull-up option can be
selected.
The pull-up option can be
selected.
Hold the
state
immediately
before
Output Hi-z
Input fixed 0
-
-
-
-
Chapter 3 Basic Information
6.Notes
6. Notes
There is no external bus mode in the MB91230 series. Please do not set the external bus mode.
43
Chapter 3 Basic Information
6.Notes
44
Chapter 4 FR60Lite Architecture
1.Overview
Chapter 4
FR60Lite Architecture
This chapter describes the architecture of FR60Lite family.
1. Overview
CPU of FR60Lite family series employs RISC architecture and advanced function instruction for embedded application.
CPU of FR60Lite family employs Harvard architecture whose instruction bus and data bus are independent. “32-bit/16bit bus converter” realizes the interface between CPU and peripheral functions. “Harvard/Princeton bus converter”
connects both of I-bus and D-bus and realizes the interface between CPU and bus controller.
Figure 1-1 Connection Diagram of Internal Architecture
FR-CPU
I-Bus
Embedded
RAM
Embedded
ROM
D-Bus
32
32
32
32
Harvard Princeton
Bus converter
F-Bus
32
32
X-Bus 32
32
Real Bus
24
Address
32bit 16bit
Bus Converter
Bus Controller
16
16
R-Bus
Peripheral functions Port
45
Chapter 4 FR60Lite Architecture
2.Features
2. Features
■ Features of internal architecture
• Introduction of RISC architecture
• Base instruction: 1 instruction/1 cycle
• 32-bit architecture
• General-purpose register: 32-bit x 16
• 4GB of linear memory space
• Equipped with multiplier.
• 32-bit x 32-bit multiplication: 5 cycles
• 16-bit x 16-bit multiplication: 3 cycles
• Enhanced interrupt processing function
• High-speed respond (6 cycles)
• Support of multiple interrupts
• Level mask function (16 levels)
• Enhanced instruction for I/O operation
• Transfer instruction between memories
• Bit-processing instruction
• Highly efficient code
• Length of base instruction words: 16 bits
• Standby mode (Low power consumption mode)
• Sleep/Stop
• Setting function of clock division ratio
Note: MB91230 series does not support external bus interface.
46
Chapter 4 FR60Lite Architecture
3.CPU
3. CPU
CPU realizes compact implementation of 32-bit RISC FR architecture.
It employs 5-stage instruction pipeline method to execute 1 instruction per 1 cycle.
This pipeline consists of the following stages.
•
Instruction fetch (IF): outputs instruction address to fetch instruction.
•
Instruction decode (ID): decodes fetched instruction and reads register.
•
Execution (EX): executes operation.
•
Memory access (MA): loads data for memory or accesses stored data.
Figure 3-1 Instruction Pipeline
CLK
Instruction 1
WB
Instruction 2
MA
WB
Instruction 3
EX
MA
WB
Instruction 4
ID
EX
MA
WB
Instruction 5
IF
ID
EX
MA
WB
IF
ID
EX
MA
Instruction 6
WB
No instruction is executed in random order. If instruction A enters into pipeline before instruction B, instruction A always
reaches to write-back stage before instruction B.
1 instruction is executed per 1 cycle.
However, to execute the instruction, multiple cycles are required for load/store instruction with memory weight, branch
instruction without delay slot and multi-cycle instruction. In addition, slow instruction degrades instruction execution
speed.
4. 32-bit/16-bit Bus Converter
This converter generates the interface between F-bus which executes 32-bit high-speed access and R-bus which executes
16-bit access in order to realize data access from CPU to peripheral functions.
If 32-bit access comes from CPU, this converter converts the access into two 16-bit accesses to access to R bus. Some
peripheral functions have restrictions of access width.
5. Harvard/Princeton Bus Converter
This converter realizes interface between instruction access and data access of CPU, to realize smooth interface with
external bus.
CPU employs Harvard architecture whose instruction bus and data bus are independent while it employs single-bus
Princeton architecture for bus controller to control external bus. This bus converter prioritizes instruction accesses and
data accesses of CPU, and executes access control to bus controller. This always optimizes access sequence to external
bus.
47
Chapter 4 FR60Lite Architecture
6.Instruction Overview
6. Instruction Overview
FR60Lite family supports logic operation, bit operation and direct addressing instruction optimized for
embedded application as well as general RISC instruction system. Instruction-set list is indicated in appendix.
Since each instruction is 16-bit length (some instruction is 32-bit or 48-bit length), it enables you to generate
compact program code.
Instruction sets are grouped into the following a through f function groups.
■ Arithmetic Operation
This group consists of standard arithmetic operation instruction (addition, subtraction and comparison) and
shift instruction (logic shift and arithmetic shift). For addition and subtraction, the operation with carry used
for multiple word length operation and the operation useful for address calculation without changing flag
value are allowed.
In addition, it includes 32-bit x 32-bit and 16-bit x 16-bit multiplication instruction as well as 32-bit/32-bit
step division instruction.
It provides transfer instruction of immediate value which sets immediate value to register, and transfer
instruction between registers.
All arithmetic instructions are operated using general-purpose register and multiply & divide register within
CPU.
■ Load and Store
Load/store is the instruction to read and write to memory. This is also used for read and write to peripheral
functions (I/O) within chip.
Load and store consist of 3 type access lengths including byte, half-word and word. In addition to general
register-indirect memory addressing, some instructions allow register-indirect memory addressing with
displacement or with register increment/decrement.
■ Branch
This is the instruction for branch, call, interrupt and return. Branch instruction consists of instructions with
and without delay slot and it is optimized for use application. For more information of branch instruction, see
“Chapter 7 Branch Instruction (Page No.69)”.
■ Logical Operation and Bit Operation
Logical operation instruction allows the logical operation of AND, OR and EOR between general-purpose
registers or general-purpose register and memory (and I/O). Bit operation instruction allows the direct
operation of data of memory (and I/O). Memory addressing is general register indirect.
■ Direct Addressing
Direct addressing instruction is the instruction to access between I/O and general-purpose register, or
between I/O and memory. By directly instructing I/O address rather than register indirect, it enables highspeed and high-efficient access. Some instructions allow register-indirect memory addressing with register
increment/decrement.
■ Others
This is the instruction which executes flag setting, stack operation, sign extension and zero extension within
PS register. It provides the function entrance/exit which supports high-level language, and register multiload/store instruction.
48
Chapter 4 FR60Lite Architecture
7.Data Structure
7. Data Structure
FR60Lite has two data allocations as follows.
■ Bit Ordering
FR60Lite uses little endian as bit ordering.
Figure 7-1 Bit Structure of Bit Ordering
bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSB
MSB
■ Byte Ordering
FR60Lite uses big endian as byte ordering.
Figure 7-2 Bit Structure of Byte Ordering
Memory
MSB
bit31
23
15
7
LSB
0
10101010 11001100 11111111 00010001
bit
7
0
n address
10101010
(n+1) address
11001100
(n+2) address
11111111
(n+3) address
00010001
49
Chapter 4 FR60Lite Architecture
8.Word Alignment
8. Word Alignment
Since instructions and data are accessed by byte, allocated addresses vary by instruction length or data width.
■ Program Access
FR60Lite program is required to be allocated in addresses multiplied by 2.
PC's bit0 is cleared for instruction execution upon the PC update.
(PC bit 0 may be set when odd address is specified for branching address, however, it is invalid. Since the instruction
is required to be allocated in addresses multiplied by 2, there is no odd address exception.)
■ Data Access
FR60Lite provides the following alignment for addresses depending on data width when executing data access.
• Word access
: Address is multiplied by 4. (Lowest order 2 bits are mandatorily 00.)
• Half-word access: Address is multiplied by 2. (Lowest order bit is mandatorily 0.)
• Byte access:
Upon the word and half-word data accesses, some bits mandatorily become 0 for computing results of
effective address. For example, in the case of addressing mode of @(R13, Ri), register value before addition
is used as is (even if lowest order bit is 1), and lower bits of addition results are masked. Register values
before computing are not masked.
[Example] LD @(R13, R2), R0
R13
00002222
R2
00000003
Addition results
00002225H
+)
Address pin
50
00002224H
Lower 2 bits are
mandatorily masked.
Chapter 4 FR60Lite Architecture
9.Addressing
9. Addressing
Address space is 32-bit linear.
■ Map
Figure 9-1 Map
0000 0000H
Byte data
0000 0100H
Half-word data
Direct addressing area
0000 0200H
Word data
0000 0400H
000F FC00H
Vector table
000F FFFFH
FFFF FFFFH
FR60Lite’s logical address space is 4GB (232 addresses), CPU accesses the data linearly.
■ Direct Addressing Area
The following areas are used for I/O.
These spaces are referred to as direct addressing area where you can specify direct operand address by the instruction.
These direct areas vary by data size to be accessed.
• Byte access
: 0 - 0FFH
•
Half-word access : 0 - 1FFH
•
Word access
:0 - 3FFH
51
Chapter 4 FR60Lite Architecture
9.Addressing
52
Chapter 5 Register (CPU)
1.General-purpose Register
Chapter 5
Register (CPU)
1. General-purpose Register
Registers R0 through R15 are general-purpose registers. These registers are used for accumulator and memory access
pointers on various operations.
Figure 1-1 General-purpose Register
32 bit
[Initial value]
R0
R1
...
...
...
...
R12
R13
R14
R15
AC
FP
SP
XXXX XXXXH
...
...
...
...
XXXX XXXXH
0000 0000H
Of 16 registers, the following registers are reserved for special application.
• R13: Virtual accumulator
• R14: Frame pointer
• R15: Stack pointer
Initial values by reset are indeterminate for R0 through R14. Initial value by reset is 00000000H (SSP value) for R15.
2. Dedicated Register
Dedicated registers consist of program counter (PC), program status (PS), table-base register (TBR), return pointer (RP),
system stack pointer (SSP), user stack pointer (USP) and multiply & divide register (MDH/MDL).
Figure 2-1 Dedicated Register List
Program counter
Program status
Table-base register
Return pointer
System stack pointer
User stack pointer
Multiply & divide register
53
Chapter 5 Register (CPU)
2.Dedicated Register
2.1 PC: Program Counter
Program Counter (PC) consists of 32 bits.
Figure 2-2 Bit Structure of Program Counter (PC)
0
31
[Initial value]
PC
XXXXXXXXH
Program counter (PC) indicates active instruction address.
Upon the execution of the instruction, program counter (PC)’s bit 0 is cleared.
2.2 PS: Program Status Register
Program status register (PS) is the register to hold program status which consists of three parts including ILM, SCR and CCR.
All undefined bits are reserved bit. Upon the reading, “0” is always read. Writing is invalid.
Program status register (PS) consists of condition code register (CCR), system condition code register (SCR) and interrupt level
mask register (ILM).
Figure 2-3 Bit Structure of Program Status (PS)
bit
31
20
16
10
87
SCR
ILM
0
CCR
■ CCR: Condition Code Register
Figure 2-4 Structure of Condition Code Register (CCR)
bit
7
6
5
4
3
2
1
0
-
-
S
I
N
Z
V
C
Initial value
--00XXXXB
• [Bit 5] S: Stack flag
This bit specifies stack pointer.
S
0
1
Description
Uses R15 as SSP. Upon generating EIT, this bit automatically becomes “0”.
(Note that the value saved in stack is the value before clear.)
Uses R15 as USP.
This bit becomes “0” by reset.
After using R15 as USP, write “0” before executing RETI instruction.
• [Bit 4] I: Interrupt-enable flag
This bit enables and disables user interrupt request.
I
0
1
Description
Disables user interrupt.
Upon executing INT instruction, this bit becomes “0”.
(Note that the value saved in stack is the value before clear.)
Enables user interrupt.
Mask processing of user interrupt request is controlled by the value which is held in ILM.
This bit becomes “0” by reset.
54
Chapter 5 Register (CPU)
2.Dedicated Register
• [Bit 3] N: Negative flag
This bit indicates the sign when operation results is deemed as integer represented by two’s-complement numbers.
N
0
1
Description
It indicates that operation result is positive value.
It indicates that operation result is negative value.
• [Bit 2] Z: Zero flag
It indicates whether operation result is 0 or not.
Z
0
1
Description
It indicates that operation result is other than 0.
It indicates that operation result is 0.
• [Bit 1] V: Overflow flag
This bit deems that operand used for operation as integer represented by two’s-complement numbers, and indicates whether
overflow was generated or not as the result of operation results.
V
0
1
Description
It indicates that overflow was not generated as the result of operation.
It indicates that overflow was generated as the result of operation.
• [Bit 0] C: Carry flag
This bit indicates whether carry or borrow from highest-order bit was generated or not as the result of operation.
Value
0
1
Description
It indicates that neither carry nor borrow is generated.
It indicates that either carry or borrow is generated.
■ SCR: System Condition Code Register
Figure 2-5 Structure of System Condition Code Register (SCR)
10
SCR
9
D1 D0
8
T
[Initial value]
XX0 B
This section describes each bit structure of system condition code register (SCR).
• [Bit 10, 9] D1 and D0: Step division flag
D1 and D0 bits hold intermediate data during the execution of step division.
Do not modify data during the execution of division processing.
If other processes is executed during the execution of step division, step division is assured to be restarted by saving and returning
PS register value.
Initial status by reset is indeterminate for D1 and D0 bits.
Upon executing DIV0S instruction, these bits are set by referring to dividend and divisor.
Upon executing DIV0U instruction, these bits mandatorily become “00”.
• [Bit 8] T: Step trace trap flag
This bit is the flag to specify whether to enable step trace trap or not.
T value
0
1
Description
Disables step trace trap.
Enables step trace trap.
In this case, all user interrupts are disabled.
This bit is initialized to “0” by reset.
The function of step trace trap is used for emulator. During the use of emulator, you cannot use this bit for user program.
55
Chapter 5 Register (CPU)
2.Dedicated Register
■ ILM: Interrupt Level Mask Register
Figure 2-6 Register Structure of Interrupt Level Mask Register (ILM)
20
19
18
17
16
ILM4 ILM3 ILM2 ILM1 ILM0
[Initial value]
01111 B
• This is the register to hold interrupt level mask value. This bit uses the value held in ILM as level mask.
• ILM indicates corresponding interrupt level from interrupt requests entered in CPU.
• Interrupt requests are accepted only if it’s priority is higher than the level.
• For level value, the highest priority is 0 (00000B), and the lowest priority is 31 (11111B).
• Program has some restrictions on configurable data.
•
When original value is between 16 and 31,
Configurable new values are the value between 16 and 31.
If you execute the instruction to set the value between 0 and 15, “specified value +16” value is set.
•
When original value is between 0 and 15,
You can set any value between 0 and 31.
These values are initialized to 15 (01111B) by reset.
56
Chapter 5 Register (CPU)
2.Dedicated Register
■ Caution: PS Register
Since some instructions have already processed PS register in advance, the following exception operations may break interrupt
processing routine during the use of debugger, or update PS flag data.
In either cases, after returning from EIT, it is designed to execute correct reprocess so that operations before and after EIT will be
processed in accordance with specification.
• At instruction right before DIV0U/DIV0S instruction, the following 1. to 3. operation may be executed.
• If user interrupt is received,
• If step execution is executed,
• If data event or emulator menu is broken,
1. D0 or D1 flag is updated in first.
2. EIT processing routine (user interrupt or emulator) is executed.
3. After returning from EIT, it executes DIV0U/DIV0S instruction and updates D0/D1 flag to the same value as 1.
• When user interrupt is generated, if you execute each instruction of ORCCR, STILM, MOV Ri or PS to
enable interrupt, the following operations are generated.
1. Updates PS register in first.
2. Executes EIT processing routine (user interrupt).
3. After returning from EIT, executes the instruction above and updates PS register to the same vale as 1.
Note: For EIT, See “Chapter 6 EIT: Exceptions, Interrupts, and Traps (Page No.61)”.
57
Chapter 5 Register (CPU)
2.Dedicated Register
2.3 TBR: Table-base Register
Table-base register (TBR) consists of 32 bits.
Figure 2-7 Bit Structure of Table-base Register (TBR)
31
0
TBR
[Initial value]
000FFC00H
Table-base register holds head address of vector table used for EIT processes.
Vector address is made by adding offset value specified in TBR and EIT each.
2.4 RP: Return Pointer
Return pointer (RP: Return Pointer) consists of 32 bits.
Figure 2-8 Bit Structure of Return Pointer (RP)
31
RP
0
[Initial value]
XXXXXXXXH
Return pointer (RP) holds addresses returned from sub routines.
Upon executing CALL, PC values are set in this RP.
Upon executing RET, RP data are set in this PC.
2.5 SSP: System Stack Pointer
System stack pointer (SSP) is used for the pointer which receives EIT and indicates stack to save/return data for return operation.
System stack pointer (SSP) consists of 32 bits.
Figure 2-9 Bit Structure of System Stack Pointer (SSP)
31
SSP
0 [Initial value]
00000000H
When S flag is “0”, it works as R15. You can explicitly specify SSP.
Upon generating EIT, it is used for the pointer which specifies the stack to save PS and PC.
During the EIT process, this pointer reduces the value by 8, and adds 8 to the value during the return from EIT by executing RETI
instruction.
System stack pointer (SSP) works as general-purpose register R15 when S flag within CCR is “0”.
58
Chapter 5 Register (CPU)
2.Dedicated Register
2.6 USP: User Stack Pointer
User Stack Pointer (USP) consists of 32 bits.
Figure 2-10 Bit Structure of User Stack Pointer (USP)
31
0
USP
[Initial value]
00000000H
When S flag is “1”, this pointer works as R15.
You can explicitly specify USP.
You can not use it for RETI instruction.
This pointer saves and returns PC and PS values at the position where system stack pointer (SSP) indicates. After interrupt, it stores
PC in address where SSP indicates, and PS in (SSP+4) address.
Figure 2-11 Interrupt Stack
[Example]
SSP
[Before interrupt]
80000000H
[After interrupt]
SSP
7FFFFFF8H
Memory
80000000H
7FFFFFFCH
7FFFFFF8H
80000000H
7FFFFFFCH
7FFFFFF8H
PS
PC
59
Chapter 5 Register (CPU)
2.Dedicated Register
2.7 MDH, MDL: Multiply & Divide Register
Multiply & Divide register (MDH/MDL) consists of 32 bits.
Figure 2-12 Bit Structure of Multiply & Divide Register (MDH/MDL)
31
0
MDH
MDL
This is the register for multiplication and division and consists of 32 bits.
Initial value by reset is indeterminate.
■ At the executing multiplication
When 32 bits x 32 bits multiplication, operation results of 64 bits are stored in multiplication/division store register as the following
allocation.
• MDH: Upper 32 bits
• MDL: Lower 32 bits
When 16 bits x 16 bits multiplication, results are stored as follows.
• MDH: Indeterminate.
• MDL: Results of 32 bits
■ At the executing division
Upon starting operation, dividend is stored in MDL.
By computing division by executing DIV0S/DIV0U, DIV1, DIV2, DIV3, or DIV4S instruction, results are stored in MDL and
MDH.
• MDH: Remainder
• MDL: Quotient
60
Chapter 6 EIT: Exceptions, Interrupts, and Traps
1.Overview
Chapter 6
EIT: Exceptions, Interrupts, and Traps
1. Overview
EIT means that some events interrupt current program to execute other programs. ELT stands for Exception, Interrupt and
Trap.
• Exception is
the event which is generated in association with active context. It is returned to the instruction which triggered the exception.
• Interrupt is
the event which is generated regardless of active context. Interrupt is triggered by hardware.
• Trap is
the event which is generated in association with active context. Some trap is specified by program such as system call. It is returned
to the next instruction to the instruction which triggered the trap.
2. Features
•
•
•
•
Supports multiple interrupts for interrupt.
Level mask function for interrupt (User can use 15 level.)
Trap instruction (INT)
EIT for emulator trigger (hardware/software)
3. EIT Trigger
•
•
•
•
•
•
•
•
•
Reset
User interrupt (peripheral function and external interrupt)
Delayed interrupt
Undefined-instruction exception
Trap instruction (INT)
Trap instruction (INTE)
Step trace trap
Coprocessor absent trap
Coprocessor error trap
4. Return from EIT
To return from EIT, use RETI instruction.
61
Chapter 6 EIT: Exceptions, Interrupts, and Traps
5.EIT Interrupt Level
5. EIT Interrupt Level
Interrupt level is between 0 and 31, and controlled with 5 bits.
Table 5-1 Interrupt Level of EIT
Level
Binary
Decimal
00000
0
...
...
...
...
00011
3
Description
Remarks
(Reserved for system)
...
...
(Reserved for system)
00100
4
INTE instruction
Step trace trap
If original value of ILM is between 16 and 31, these
values are not configurable to ILM by program.
00101
...
...
01110
01111
10000
10001
...
...
11110
11111
5
...
...
14
15
16
17
...
...
30
31
(Reserved for system)
...
...
(Reserved for system)
NMI (for users)
Interrupt
Interrupt
...
...
Interrupt
N/A
This is not supported in this product.
When ILM is set, user Interrupt is disabled.
When ICR is set, Interrupt is disabled.
Only 16 through 31 levels are operable.
Undefined-instruction exception, coprocessor absent trap, coprocessor error trap and INT instruction are not affected by
interrupt level. Also, ILM is not changed by interrupt level.
6. EIT Vector Table
For EIT vector table, see the chapter of “Chapter 3 Basic Information (Page No.25)”.
Vector for EIT is between address which table-base register [TBR] indicates and 1 KB area.
Its size is 4 bytes per one vector. For vector number/vector address/trigger, see “4. Interrupt Vector Table (Page No.38)”.
Address arithmetic is as follows.
Vector address = [TBR] + Offset value = [TBR] + {03FCH - 4 x Vector number (No.)}
Lower two bits as the result of addition are always used for “00”.
000FFC00H through 000FFFFFH areas are initial values of vector table by reset.
If you rewrite TBR value, reset vector and mode vector always use fixed address of 000FFFFCH, 000FFFFCH.
62
Chapter 6 EIT: Exceptions, Interrupts, and Traps
7.Multiple EIT Processing
7. Multiple EIT Processing
If multiple EITs are generated at the same time, CPU repeats the operation which selects one of the EIT to accept, and
then executes EIT sequence, and detects EIT again. If there is no EIT to accept upon detecting EIT, CPU executes
instruction of the last accepted EIT handler. Therefore, if multiple EITs are generated at the same time, execution
sequence of each EIT handler is determined by the following two parameters.
■ Priority Level of Receipt of EIT Triggers
Priority level of receipt of EIT triggers means the sequence to select which EIT triggers to execute by saving PS and PC
in order to update PC and masking other triggers where appropriate.
EIT does not always mean first-in first-out handler.
Table 7-1 Priority Level of Receipt of EIT Triggers and Mask for Other Triggers
Priority level of receipt
1
2
Triggers
Reset
Undefined-instruction exception
3
INTE instruction
4
INT instruction
Coprocessor absent trap
Coprocessor error trap
User Interrupt
NMI (for users)
NMI (for emulator)
Step trace trap
5
6
7
8
9
Mask for other triggers
Cancels other triggers.
Cancellation
ILM=4
Cancels other triggers.
I flag =0
–
ILM=Level of triggers received
ILM=15 (This product does not support NMI.)
ILM=4
ILM=4
■ How to Mask Other Triggers upon the Receipt
Table below shows the execution sequence of each handler for multiple EIT triggers generated at the same time when
considering mask processes for other triggers upon the receipt of EIT triggers.
Table 7-2 Execution Sequence of EIT Handlers
Execution sequence of handlers
1
2
3
4
5
6
7
8
Triggers
Reset*
Undefined-instruction exception
INTE instruction*
Step trace trap
NMI (for users. Note that this product does not support NMI.)
INT instruction
User Interrupt
Coprocessor absent trap and coprocessor error trap
*: Cancels other triggers.
63
Chapter 6 EIT: Exceptions, Interrupts, and Traps
7.Multiple EIT Processing
Figure 7-1 Multiple EITs Process
NMI handler
Main routine
INT instruction
handler
(1) First execution
User interrupt
handler
Priority
(High) Generation of NMI
(2) Second execution
(Middle) Execution of INT instruction
(Low) Execution of user interrupt
(3) Third execution
* MB91230 does not support NMI.
64
Chapter 6 EIT: Exceptions, Interrupts, and Traps
8.Operation
8. Operation
In the following sections, note that source “PC” means instruction address which detected each EIT trigger.
Similarly, “address of next instruction” means the following addresses based on the instruction which detected the EIT.
• When LDI is 32: PC+6
• When LDI is 20, and it is COPOP, COPLD, COPST or COPSV: PC+4
• For other instructions: PC+2
8.1 User Interrupt operation
If user interrupt request occurs, it determines whether to receive its request or not in the following sequence.
■ How to determine whether to receive interrupt request or not
1. Selects the interrupt which holds the highest priority level (the smallest number) by comparing interrupt request levels
generated at the same time.
For the level to be compared, it uses the value which ICR holds corresponding to maskable interrupt.
2. Selects the interrupt request which has the earliest interrupt number if multiple interrupt requests with the same
priority level are generated.
3. Where “Interrupt level >
= Level mask value”, the interrupt request is masked without receipt. Where “Interrupt level <
Level mask value”, it goes forward to Step 4.
4. When selected interrupt request is maskable interrupt, if I flag is 0, its Interrupt request is masked without receipt and
if I flag is 1, it goes forward to Step 5.
5. If conditions above are satisfied, interrupt requests are received between instruction processes.
If user interrupt requests are received upon detecting EIT requests, CPU executes the following operations according
to the Interrupt number for the interrupt request received.
■ Operation
1. From SSP-4 to SSP
2. From PS to (SSP)*
3. From SSP-4 to SSP
4. From address of next instruction to (SSP)*
5. From interrupt level of request received to ILM
6. From “0” to S flag
7. From (TBR+Vector offset of Interrupt request received)* to PC
*: ( ) indicates the address which register specifies.
After Interrupt sequence, it detects EIT again before executing the head handler’s instruction. If any receivable EIT is
generated at this time, CPU goes to EIT process sequence.
65
Chapter 6 EIT: Exceptions, Interrupts, and Traps
8.Operation
8.2 Operation of INT Instruction
INT No. u8 instruction is operated as follows.
Branches to interrupt handler of vector specified in u8.
■ Operation
1. From SSP-4 to SSP
2. From PS to (SSP)*
3. From SSP-4 to SSP
4. From PC+2 to (SSP)*
5. From “0” to I flag
6. From “0” to S flag
7. From (TBR+3FCH-4 × u8)* to PC
*: ( ) indicates the address which register specifies.
8.3 Operation of INTE Instruction
INTE instruction is operated as follows.
Branches to vector interrupt handler of vector number 9.
■ Operation
1. From SSP-4 to SSP
2. From PS to (SSP)*
3. From SSP-4 to SSP
4. From PC+2 to (SSP)*
5. From “00100” to ILM
6. From “0” to S flag
7. From (TBR+3D8H)* to PC
*: ( ) indicates the address which register specifies.
During the execution of step, EIT is not generated by INTE.
Since INTE instruction is used for the device, do not use it.
66
Chapter 6 EIT: Exceptions, Interrupts, and Traps
8.Operation
8.4 Operation of Step Trace Trap
If you set T flag at SCR within PS and enable step trace trap function, step trace trap is generated with each executing
instruction.
■ Condition for detecting step trace trap
T flag = 1
Instructions are other than delayed branch command.
During the execution of instructions other than INTE instructions or step trace trap process routines.
If conditions above are satisfied, it is broken between instruction operations.
■ Operation
1. From SSP-4 to SSP
2. From PS to (SSP)*
3. From SSP-4 to SSP
4. From address of next instruction to (SSP)*
5. From “00100” to ILM
6. From “0” to S flag
7. From (TBR+3CCH)* to PC
*: ( ) indicates the address which register specifies.
If you set T flag to enable step trace trap, user interrupt is disabled.
In addition, EIT will not be generated by INTE instruction.
FR60Lite generates traps from next instruction to instruction which set T flag.
8.5 Operation of Undefined-instruction Exception
If any undefined instruction is detected upon decoding instruction, undefined-instruction exception is generated.
■ Condition for detecting undefined-instruction exception
• Upon the decoding instruction, undefined instruction is detected.
• It is out of delayed slot. (It is not the instruction which is right after delay branch instruction.)
If conditions above are satisfied, undefined-instruction exception will be generated.
■ Operation
1. From SSP-4 to SSP
2. From PS to (SSP)*
3. From SSP-4 to SSP
4. From PC to (SSP)*
5. From “0” to S flag
6. From (TBR+3C4H)* to PC
*: ( ) indicates the address which register specifies.
Address of the instruction which detected undefined-instruction exception is saved as PC.
67
Chapter 6 EIT: Exceptions, Interrupts, and Traps
9.Caution
8.6 Coprocessor Absent Trap
If you execute coprocessor instruction for unmounted coprocessor, coprocessor absent trap is generated.
■ Operation
1. From SSP-4 to SSP
2. From PS to (SSP)*
3. From SSP-4 to SSP
4. From address of next instruction to (SSP)*
5. From “0” to S flag
6. From (TBR+3E0H)* to PC
8.7 Coprocessor Error Trap
If error occurs during the use of coprocessor, coprocessor error trap is generated when you execute coprocessor
instruction in order to operate the coprocessor next time.
■ Operation
1. From SSP-4 to SSP
2. From PS to (SSP)*
3. From SSP-4 to SSP
4. From address of next instruction to (SSP)*
5. From “0” to S flag
6. From (TBR+3DCH)* to PC
8.8 Operation of RETI Instruction
RETI instruction is the instruction which returns from EIT process routine.
■ Operation
1. From (R15)* to PC
2. From R15+4 to R15
3. From (R15)* to PS
4. From R15+4 to R15
RETI instruction should be executed with S flag “0”.
9. Caution
• Since INTE instruction is used for the device, do not use it.
• Delay slot for branch instruction has restrictions on EIT.
See “Chapter 7 Branch Instruction (Page No.69)”.
68
Chapter 7 Branch Instruction
1.Branch Instruction with Delay Slot
Chapter 7
Branch Instruction
FR60Lite can instruct the operation with and without delay slot for branch instruction.
1. Branch Instruction with Delay Slot
• Branch instruction with delay slot
JMP:D @Ri
CALL:D label12
CALL:D @Ri
RET:D
BRA:D label9
BNO:D label9
BEQ:D
BNE:D label9
BC:D label9
BNC:D label9
BN:D
label9
BP:D
BV:D label9
BNV:D label9
BLT:D
label9
BGE:D label9
BLE:D label9
BGT:D label9
BLS:D
label9
BHI:D label9
label9
label9
2. Operation of Branch Instruction with Delay Slot
Operation with delay slot executes the instruction located in the next address where a branch instruction exists (referred to
as delay slot) and then branches before executing branched instructions.
Since it executes delay slot instruction before branch operation, apparent execution rate becomes 1 cycle. Instead, if delay
slot has no valid instruction, NOP instruction must be entered.
• Example
;
Sequence of instruction
ADD
R1
R2
BRA:D LABEL
MOV
R2
R3
...
LABEL : ST
R3
@R4
;
; Branch instruction
; Delay slot ...... To be executed before the branch.
; Branched instruction
In conditional branch instruction, regardless of whether branch parameter is approved or not, instructions located in delay
slot are executed.
In delay branch instruction, execution sequence of some instructions seems opposite, however, it only applies to updating
process on the PC. Any other operation (register update/look-up) is executed in the order of description.
69
Chapter 7 Branch Instruction
3.Actual Example (with Delay Slot)
3. Actual Example (with Delay Slot)
3.1 JMP:D @Ri / CALL:D @Ri Instruction
Ri referred in JMP:D @Ri / CALL:D @Ri instruction remains intact even if instructions within delay slot
update Ri.
• Example
LDI:32
JMP:D
LDI:8
...
#Label,
@R0
#0,
R0
; Branches to Label.
; Not affect any branched address.
R0
3.2 RET:D Instruction
RP referred in RET:D instruction remains intact even if instructions within delay slot update RP.
• Example
RET:D
MOV
...
R8,
RP
; Branches to the address previously specified in RP.
; Not affect any return operation.
3.3 Bcc:D rel Instruction
Flag referred in Bcc:D rel instruction also remains unaffected by instructions within delay slot.
• Example
ADD
#1,
R0
BC:D
Overflow
ANDCCR #0
...
; Change of flag
; Branches in accordance with the execution result of instructions above.
; This flag update is not referred in branch instruction above.
3.4 CALL:D Instruction
When RP is referred using the instruction within delay slot of CALL:D instruction, the data updated by
CALL:D instruction is read out.
• Example
CALL:D Label
MOV
RP,
...
70
R0
; Branches by updating RP.
; Transfers RP based on the execution results of CALL: D above.
Chapter 7 Branch Instruction
4.Restrictions on Branch Instruction with Delay Slot
4. Restrictions on Branch Instruction with Delay Slot
4.1 Available Instructions for Delay Slot
Instructions which meet the following requirements can only be executed in delay slot.
• 1-cycle instruction
• Non-branch instruction
• Instruction which does not affect any operation even if its sequence is changed.
“1-cycle instruction” indicates instructions whose number of cycles column in the instruction list table is described with
“1”, “a”, “b”, “c” or “d”.
4.2 Step Trace Trap
Step trace trap is not generated between the execution of branch instruction with delay slot and delay slot.
4.3 Interrupt
Interrupt is not acceptable between the execution of branch instruction with delay slot and delay slot.
4.4 Undefined-instruction Exception
If undefined instruction exists in delay slot, undefined instruction-exception is not generated. In this case, undefined
instruction works as NOP instruction.
71
Chapter 7 Branch Instruction
5.Branch Instruction without Delay Slot
5. Branch Instruction without Delay Slot
• Branch instruction without delay slot:
JMP @Ri
CALL label12
CALL @Ri
RET
BRA label9
BNO label9
BEQ label9
BNE label9
BC label9
BNC label9
BN label9
BP
BV label9
BNV label9
BLT label9
BGE label9
BLE label9
BGT label9
BLS label9
BHI label9
label9
6. Operation of Branch Instruction without Delay Slot
Operation without delay slot executes instructions in the order of instructions and never executes the
instruction located in the next address where a branch instruction exists before branch.
• Example
;
Sequence of instruction
ADD
R1
R2
BRA:D LABEL
MOV
R2
R3
...
LABEL ST
R3
@R4
;
; Branch instruction (without delay slot)
; Not to be executed.
; Branched instruction
The number of execution cycles of branch instruction without delay slot is 2 cycles for branch and 1 cycle for
no branch.
Unlike the branch instruction with delay slot where NOP is described because appropriate instruction cannot
be entered, it can increase efficiency of instruction code.
Select the operation with delay slot when valid instruction can be set in delay slot. Otherwise select the
operation without delay slot. This selection enables FR60Lite to satisfy both of execution rate and code
efficiency.
72
Chapter 8 Status Transition of Device
1.Overview
Chapter 8
Status Transition of Device
1. Overview
MB91230 basically has status and flow as illustrations below.
For more information, see “3. Status Transition Diagram (Page No.74)”.
Status transition
Power-on
Generated watchdog
INT-pin input
Setting-initialization reset
Oscillation-stabilization
reset
Operation-initialization
reset
Software-reset instruction
Run
Interrupt request
Oscillation-stabilization RUN
Stop
Interrupt request
Sleep
2. Features
■ Device status
•
•
•
•
RUN (Normal operation): Status where program is executed.
Sleep: Status where program is stopped. (Peripheral circuits are operable.)
Stop: Status where device is stopped.
Oscillation-stabilization-wait RUN: Status to return from stop to RUN status
(Status waiting until clock oscillation is stabilized.)
• Oscillation-stabilization-wait reset: Status waiting until clock oscillation is stabilized after INIT.
• Operation-initialization reset (RST): Status where program is initialized.
• Setting-initialization reset (INIT): Status where all settings are initialized.
■ Standby mode (Low-power-consumption mode)
Sleep and Stop above are standby mode.
73
Chapter 8 Status Transition of Device
3.Status Transition Diagram
3. Status Transition Diagram
This section describes status transition.
Figure 3-1 Status Transition of MB91230 Series
1
2
3
4
5
6
7
8
9
10
11
12
13
INIT pin = 0 (INIT)
INIT pin = 1 (Cancel of INIT)
Termination of oscillation-stabilization wait
Cancel of reset (RST)
Software reset (RST)
Sleep (Writing instruction)
Stop (Writing instruction)
Interrupt
External interrupt requiring no clock
Switching from main to sub (Writing instruction)
Switching from sub to main (Writing instruction)
Watchdog reset (INIT)
Sub-sleep (Writing instruction)
Highest Priority of transition request
priority Setting-initialization reset (INIT)
Termination of oscillation-stabilization wait
Operation-initialization reset (RST)
Interrupt request
Stop
Lowest Sleep
priority
Power-on
1
Setting initialization
(INIT)
2
Main clock mode
1
Oscillationstabilizationwait reset
Main stop
9
1
3
1
Program reset
(RST)
Oscillationstabilization-wait RUN
3
7
1
Main sleep
5
1
4
12
Main RUN
6
1
8
10
Subclock mode
1
11
8
12
Sub-RUN
Sub-sleep
1
13
1
3
Oscillationstabilization-wait RUN
MB91230 does not stop
oscillation while waiting
time is generated.
1
7
5
4
Program reset
(RST)
1
9
Sub-stop *
* To switch clock source between main and sub, in the RUN status where switched clock is stable,
switch clock source register (CLKR) between bit 1 and 0 (CLKS1 and CLKS0 bit).
74
Chapter 8 Status Transition of Device
3.Status Transition Diagram
3.1 RUN (Normal Operation)
This is the status where program is executed.
This is the status where all clocks are supplied and all circuits are operable.
Except that 16-bit peripheral bus stops only bus clock white there is no access.
It receives various requests for status transition. However, if synchronous reset mode is selected, status transition
operations for some requests are different from normal reset mode. For more information, see the chapter of “Chapter 9
Reset (Page No.77)”.
3.2 Sleep
This is the status where program is stopped. This status transits by program operation.
This is the status where only CPU's program is stopped and peripheral circuits are operable. Various embedded memories
and embedded internal/external buses are stopped unless DMA controller requests.
• Upon generation of valid interrupt requests, it cancels sleep status and transits to RUN (Normal operation).
• Upon generation of request of setting-initialization reset (INIT), it transits to setting-initialization reset (INIT).
• Upon generation of request of operation-initialization reset (RST), it transits to operation-initialization reset (RST).
3.3 Stop
This is the status where device is stopped. This status transits by program operation.
All internal circuits are stopped. All internal clocks are stopped and oscillation circuits and main PLL are able to be
stopped by setting.
In addition, some setting enables to provide uniform high impedance for external pins. (Except for some pins.)
• Upon generation of specific valid interrupt requests (requiring no clock), active oscillation timer interrupt or main
clock oscillation stabilization timer interrupt request, it transits to oscillation stabilization wait RUN.
• Upon generation of request of setting-initialization reset (INIT), it transits to setting-initialization reset (INIT).
• Upon generation of request of operation-initialization reset (RST), it transits to oscillation stabilization wait reset.
3.4 Oscillation-stabilization-wait RUN
This is the status where device is stopped. It transits after return from stop.
All internal circuits are stopped except for clock generation control parts (timebase counter and device status control
parts). All internal clocks are stopped while oscillation circuits and operable main PLLs are operated.
• High-impedance control of external pins by stop are cancelled.
• After configured oscillation-stabilization-wait time passed, it transits to RUN (Normal operation).
• Upon generation of request of setting-initialization reset (INIT), it transits to setting-initialization reset (INIT).
• Upon generation of request of operation-initialization reset (RST), it transits to operation-initialization reset.
• During the sub-stop of MB91230, subclock does not stop oscillation but oscillation-stabilization-wait time is
generated upon returning from sub-stop.
75
Chapter 8 Status Transition of Device
3.Status Transition Diagram
3.5 Oscillation-stabilization-wait Reset
This is the status where device is stopped. This status transits upon returning from stop or settinginitialization reset (INIT).
All internal circuits are stopped except for clock generation control parts (timebase counter and device status
control parts). All internal clocks are stopped while oscillation circuits and operable main PLL are operated.
• High-impedance control of external pins by stop is cancelled.
• For internal circuits, this status outputs operation-initialization reset (RST).
• After configured oscillation-stabilization-wait time passed, it transits to oscillation-stabilization-wait
reset.
• Upon generation of request of setting-initialization reset (INIT), it transits to setting-initialization reset
(INIT).
3.6 Operation-initialization Reset (RST)
This is the status where program is initialized. Upon receipt of request of operation-initialization reset (RST)
or termination of oscillation-stabilization-wait reset (RST), this status transits.
CPU’s program is stopped and program counter is initialized. All peripheral circuits are initialized except for
some peripheral circuits. All internal clocks, oscillation circuits and operable main PLLs are operated.
• For internal circuits, this status outputs operation-initialization reset (RST).
• Upon clear of request of operation-initialization reset (RST), this status transits to RUN (normal
operation) and executes operation-initialization reset sequence. Upon returning from settinginitialization reset (INIT), this status executes setting-initialization reset sequence.
• Upon generation of request of setting-initialization reset (INIT), it transits to setting-initilalization reset
(INIT).
3.7 Setting-initialization Reset (INIT)
This is the status where all settings are initialized. Upon receipt of request of setting-initialization reset
(INIT), it transits.
CPU’s program is stopped and program counter is initialized. All peripheral circuits are initialized.
Oscillation circuits are operated while main PLLs are stopped. All internal clocks are operated except while
“L” level is input to external INIT pins.
• For internal circuits, this status outputs setting-initialization reset (INIT) and operation-initialization
reset (RST).
• Upon clear of request of setting-initialization reset (INIT), this status cancels status of settinginitialization reset, and then it transits to oscillation-stabilization-wait reset. Then, it executes operationinitialization reset sequence.
3.8 Priority of Each Request of Status Transition
In any status, each request of status transition subjects to the following priority. However, since some
requests are only generated in specific status, such a request is invalid only in that status.
[Highest
priority]
[Lowest
priority]
76
Request of setting-initialization reset (INIT)
Termination of oscillation-stabilization-wait time (This is generated only in status of
oscillation-stabilization-wait reset and oscillation-stabilization-wait RUN.)
Request of operation-initialization reset (RST)
Request of valid interrupt (This is generated only in RUN, sleep or stop status.)
Request of stop mode (Writing in register) (This is generated only in RUN status.)
Request of sleep mode (Writing in register) (This is generated only in RUN status.)
Chapter 9 Reset
1.Overview
Chapter 9
Reset
1. Overview
When a reset is triggered, the device halts the program and all hardware operation, and then initializes all states. This
state is called a reset.
When the reset trigger condition is removed, the device changes from this initialized state to restart the program and
hardware operation. The series of steps from removal of the reset condition until operation starts is called the reset
cancellation sequence.
Figure 1-1 Flow of Reset Operation
Power ON
INIT pin input
From any state
Settings initialization reset
Watchdog timeout
Oscillation stabilization
wait reset
Operation initialization
reset
RUN
Software reset instruction
2. Features
• Types of reset
• INIT pin input: Settings initialization reset (INIT)
• Watchdog reset: Settings initialization reset (INIT)*
• Software reset: Operation initialization reset (RST)
*: Although a watchdog reset triggers the same settings initialization reset (INIT) as an INIT pin input, it does not initialize
the oscillation stabilization time selection bits (OS[1:0]) and reset cause flags (INIT, WDOG, and SRST).
• Cause of reset can be determined
The cause of the previous reset is stored in a series of flags (INIT, WDOG, and SRST).
• Operation after reset condition is removed
Operation mode: Determined by the mode pins and mode data.
Note: The MB91230 supports single chip mode only.
• A settings initialization reset (INIT) is followed by an operation reset (RST) after the oscillation
stabilization time elapses.
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Chapter 9 Reset
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
State transition control circuit (reset related)
MOD0
MOD1
MOD2
OSCD1
0
1
SLEEP
STCR: bit7
0
1
Do not change to sleep mode
Change to sleep mode
Sleep signal
STOP
STCR: bit7
Stop signal
0
1
Do not change to stop mode
Change to stop mode
STCR:
STCR:
bit1bit1
Main clock continues to operate during stop mode
State
transition
control
circuit
Main clock halts during stop mode
HIZ
STCR: bit0
0
1
Maintain pin states during stop mode
Set pins to high impedance during stop mode
Clock control
Pin control
Internal interrupts, external interrupts
SRST
0
1
STCR: bit4
Initialization reset (INIT)
Trigger software reset
Do not trigger software reset
INIT
Operation reset (RST)
INIT
RSRR:
RSRR: bit7
bit7
0
1
No INIT pin input
INIT pin input occurred
Oscillation stabilization wait ended
Clear counter and
start oscillation
stabilization wait
SRST
RSRR: bit3
bit
0
1
No software resetRS
(RST)
T)
Software reset (RST)
RSoccurred
T)
Time-base counter
(oscillation stabilization wait)
Watchdog timer
WDOG
RSRR: bit5
0
1
No watchdog timeout
Watchdog timeout(INIT)
(INIT) occurred
Figure 3-2 Register List
Software rest
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Chapter 9 Reset
4.Registers
4. Registers
4.1 RSRR: Reset Cause Register
Stores the cause of the previous reset, and sets the period and activation control for the watchdog timer.
• RSRR: Address 0480h (Access: Byte, Half-word)
7
INIT
6
-
5
WDOG
4
-
3
SRST
2
-
1
WT1
0
WT0
1
0
0
0
0
0
0
0
-
-
-
X
X
-
0
0
X
X
X
-
-
X
0
0
R/WX
RX/WX
R/WX
RX/WX
R/WX
RX/WX
R/W
R/W
bit
Initial value
(INIT pin input)
Initial value
(Watchdog reset)
Initial value
(Software reset)
Attribute
Note: See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.
Reading the reset request cause returns the reset cause flags and then clears the flag values to “0”.
If multiple resets occur prior to reading the register, the resulting flag values contain the bitwise OR of the flags for each
reset. That is, more than one flag may be set to “1”.
• Bit7: Initialization reset occurred flag
Indicates whether a reset (INIT) was triggered by INIT pin input.
INIT
0
1
Meaning
No INIT has been triggered by INIT pin input.
INIT has been triggered by pin input.
The initialization reset occurred flag (INIT) is cleared to “0” after reading.
• Bit6: Reserved bit Writing does not affect the operation. The read value is indeterminate.
• Bit5: Watchdog reset occurred flag
Indicates whether a reset (INIT) was triggered by the watchdog timer.
WDOG
0
1
Meaning
No INIT has been triggered by the watchdog timer.
INIT has been triggered by the watchdog timer.
The watchdog reset occurred flag (WDOG) is cleared to “0” after reading.
• Bit4: Reserved bit Writing does not affect the operation. The read value is indeterminate.
• Bit3: Software reset occurred flag
Indicates whether a software reset has been triggered by writing to the software reset bit (STCR.SRST).
SRST
0
1
Meaning
No RST has been triggered by a software reset.
RST has been triggered by a software reset.
The software reset occurred flag (SRST) is cleared to “0” after reading.
• Bit2: Reserved bit Writing does not affect the operation. The read value is indeterminate.
• Bit1-0: Watchdog period selection
The watchdog period selection bits (WT[1:0]) can set the period of the watchdog timer to the following:
(Φ × 216 to 217, Φ × 218 to 219, Φ × 220 to 221, Φ × 222 to 223)
See “Chapter 14 Watchdog Timer (Page No.145)” for details.
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Chapter 9 Reset
4.Registers
4.2 STCR: Standby Control Register
This register is used for software reset control (changing to standby mode, pin control in stop mode, and
clock oscillation halted in stop mode), and specifies the oscillation stabilization wait time.
Note: See also “Chapter 10 Standby (Page No.91)”.
• STCR: Address 0481h (Access: Byte, Half-word)
7
STOP
6
SLEEP
5
HIZ
4
SRST
3
OS1
2
OS0
1
OSCD2
0
OSCD1
0
0
1
1
0
0
X
1
0
0
1
1
X
X
X
1
0
0
X
1
X
X
X
X
R/W
R/W
R/W
R1,W
R/W
R/W
RX/WX
R/W
bit
Initial value
(INIT pin input)
Initial value
(Watchdog reset)
Initial value
(Software reset)
Attribute
Note: See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.
• Bit7: Stop mode
Writing “1” to the stop mode bit (STOP) changes to stop mode.
See “Chapter 10 Standby (Page No.91)” for details.
• Bit6: Sleep mode
Writing “1” to the sleep mode bit (SLEEP) changes to sleep mode.
See “Chapter 10 Standby (Page No.91)” for details.
• Bit5: High impedance mode
Writing “1” to the high impedance mode bit (HIZ) sets pin to high impedance (Hi-z) during stop mode.
See “Chapter 10 Standby (Page No.91)” for details.
• Bit4: Software reset
Writing “0” to the software reset bit triggers a software reset.
SRST
0
1
Operation
Trigger a software reset
Do not trigger a software reset
• Note that negative logic is used.
• The read value is always “1”.
• Bit3-2: Oscillation stabilization time selection
The oscillation stabilization time selection bits (OS[1:0]) set the oscillation stabilization time as follows:
(Φ2 × 21, Φ2 × 211, Φ2 × 216, Φ2 × 222)
The count is supplied by the timebase counter.
Initialized to “00” (Φ2 × 21, main clock) by a reset triggered by INIT pin input.
See “Chapter 13 Timebase Timer (Page No.135)” for details.
• Bit1: Reserved bit Writing does not affect the operation. The read value is indeterminate.
• Bit0: Halt main clock oscillation
Writing “1” to the halt main clock oscillation bit (OSCD1) halts the oscillation of the main clock during stop mode.
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Chapter 9 Reset
4.Registers
4.3 MOD: Mode Pins
These pins specify the location of the mode vector and reset vector that are read after the MCU is reset.
Signal name
MOD0
MOD1
MOD2
LQFP-120
89 pin
88 pin
87 pin
Mode pins
MD2 MD1 MD0
Mode name
Low
Low
Low
Low
Low
High
FLGA-128
D9 pin
B11 pin
C12 pin
Reset vector
Access area
Internal ROM mode
vector
External ROM mode
vector
Remarks
Internal
External
Not supported on this model.
Always set these pins to “000” on the MB91230 series.
4.4 Mode Vector
The data written to the mode register (MODR) by the mode vector fetch operation is called the mode data. (The mode
register is an internal register and cannot be written to or read from directly.)
After the mode register is set, the MCU operates in accordance with the modes (bus mode and access mode) set in this
register.
The mode data is set by all types of reset. Setting the mode data from the user program is not possible.
• Mode Vector: Address 000FFF8h (Access: Byte, Half-word, Word)
31
0
30
0
29
0
28
0
27
0
26
ROMA
25
WTH1
24
WTH0
Bit
Operation mode setting bits
• Bit32-27: Reserved bits
Always set these bits to “00000”.
If a value other than “00000” is set, the operation of the MCU is not guaranteed.
• Bit26: Internal ROM enable
Specifies whether to enable the internal ROM area.
ROMA
0
1
Function
External ROM mode
Internal ROM mode
Remarks
Not supported (setting prohibited)
Enables the internal ROM area.
Always set to “1”.
• Bit25-24: Bus width setting
This sets the bus width for external bus mode.
WTH1
0
0
1
1
WTH0
0
1
0
1
Function
8-bit bus width
16-bit bus width
---------Single chip mode
Remarks
Not supported (setting prohibited)
Not supported (setting prohibited)
Setting prohibited
Always set to “11”.
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Chapter 9 Reset
4.Registers
• Bit23-0: Undefined bits
4.5 Reset Vector
The MCU starts program execution from the address specified by the mode vector.
Initial value to load into PC.
Address
007FDH
MODR
000FFFF8 H Mode
Vector
000FFFFC H Reset
Vector
82
XXXXXXXX XXXXXXXX XXXXXXXX
PC
Chapter 9 Reset
5.INIT Pin Input (INIT: Settings Initialization Reset)
5. INIT Pin Input (INIT: Settings Initialization Reset)
5.1 Trigger
The pin is used to trigger a settings initialization reset.
A settings initialization reset (INIT) request remains active while the pin remains at the “L” level.
5.2 Releasing the Reset Request
Inputting an “H” level to the pin releases the settings initialization reset (INIT) request.
5.3 Flag
When an pin request triggers a settings initialization reset (INIT), the settings initialization reset flag (RSRR.INIT) is set
to “1”.
5.4 Reset Level
This reset has the maximum reset level and initializes all settings. This type of reset is called the settings initialization
reset (INIT)
A settings initialization reset (INIT) triggered by INIT pin input has the highest priority of all resets and has priority over
all other inputs, operations, and states.
When a settings initialization reset (INIT) occurs, it is followed by an operation reset (RST) after the oscillation
stabilization time elapses.
5.5 Initialization Triggered by INIT Pin Input (INIT)
•
•
•
•
•
Device operation mode (bus mode and external bus width setting)
All internal clock related settings (clock source selection, main PLL control, division setting)
All settings relating to the external bus CS0 area
All other settings related to pin states
All areas initialized by an operation reset (RST)
• Program operation
• CPU and internal bus
• Peripheral circuit register contents
• I/O port settings
• Device operation mode (bus mode and external bus width setting)
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Chapter 9 Reset
5.INIT Pin Input (INIT: Settings Initialization Reset)
5.6 Reset Cancellation Sequence
After cancellation (removal) of the settings initialization reset (INIT) request, the device performs the
following operations in the sequence listed.
However, in the case of a watchdog reset when the main clock oscillation is not halted in main RUN or sub
RUN mode, the oscillation stabilization wait (step 2) is not performed.
1. Removal of settings initialization reset (INIT) and change to oscillation stabilization wait state
2. Delay operation reset (RST) and halt internal clock until oscillation stabilization wait (specified by bits 2
and 3 of STCR (OS1, OS0)) has finished.
3. Set operation reset (RST) state and start internal clock
4. Clear operation reset (RST) state and change to normal operation (RUN)
5. Read mode vector from address 000FFFF8H
6. Write mode vector to MODR (mode register)
7. Read reset vector from address 000FFFFCH
8. Write reset vector in PC (program counter)
Start program execution from the address specified by PC (program counter)
Note: See explanation in “5. Operation (Page No.123)”.
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Chapter 9 Reset
6.Watchdog Reset (INIT: Settings Initialization Reset)
6. Watchdog Reset (INIT: Settings Initialization Reset)
6.1 Trigger
Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Once started, a watchdog reset request
is generated unless “A5H” and “5AH” are written to the watchdog reset delay register (WPR) within the time specified by
the watchdog period selection bits (RSRR.WT[1:0]).
6.2 Releasing the Reset Request
The watchdog reset request invokes a settings initialization reset (INIT). The watchdog reset request is released after the
request is received and the settings initialization reset (INIT) generated, or when an operation reset (RST) occurs.
6.3 Flag
When watchdog reset request triggers a settings initialization reset (INIT), the watchdog timeout flag (RSRR.WDOG) is
set to “1”.
6.4 Reset Level
This reset has the maximum reset level and initializes all settings. This type of reset is called the settings initialization
reset (INIT).
When a settings initialization reset (INIT) occurs, it is followed by an operation reset (RST) after the oscillation
stabilization time elapses.
6.5 Initialization Triggered by Watchdog Reset (INIT)
Same as for a reset triggered by an INIT pin input.
However, the oscillation stabilization time selection bits (STCR.OS[1:0]) and reset cause flags (INIT, WDOG, SRST) are
not initialized and retain their existing values.
6.6 Reset Cancellation Sequence
Same as for INIT pin input.
(See “Chapter 14 Watchdog Timer (Page No.145)” for details.)
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Chapter 9 Reset
7.Software Reset (RST: Operation Initialization Reset)
7. Software Reset (RST: Operation Initialization Reset)
7.1 Trigger
Writing “0” to the software reset bit (STCR.SRST) generates a software reset request.
A software reset requests an operation reset (RST).
7.2 Releasing the Reset Request
The software reset request is released after the request is received and the operation reset (RST) generated.
7.3 Flag
When software reset request triggers an operation reset (RST), the software reset flag (RSRR.SRST) is set to
“1”.
7.4 Reset Level
This is a normal level reset which only initializes the program and is called an operation reset (RST).
The following section lists the main items initialized by an operation reset (RST):
7.5 Items Initialized by Operation Reset (RST)
•
•
•
•
•
Program operation
CPU and internal bus
Content of registers in peripheral circuits
I/O port settings
Device operation mode (bus mode and external bus width setting)
7.6 Reset Cancellation Sequence
After cancellation (removal) of the operation reset (RST) request, the device performs the following
operations in the sequence listed.
1. Removal of operation reset (RST) and change to RUN state
2. Read mode vector from address 000FFFF8H
3. Write mode vector to MODR (mode register)
4. Read reset vector from address 000FFFFCH
5. Write reset vector to the PC (program counter)
6. Start program execution from the address specified by the PC (program counter)
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Chapter 9 Reset
8.Reset Operation Modes
8. Reset Operation Modes
The following two different modes can be used for an operation reset (RST):
• Normal (asynchronous) reset mode
• Synchronous reset mode
Which mode to use is specified by the synchronous reset operation enable bit (TBCR.SYNCR).
Pin input resets and watchdog resets always use normal reset mode.
For software resets, either normal reset mode or synchronous reset mode can be selected.
8.1 Normal (Asynchronous) Reset Mode
Normal reset operation refers to the mode when the device goes to the operation reset (RST) state immediately after an
operation reset (RST) request occurs.
For a normal reset, the device changes to the reset (RST) state immediately after a reset (RST) request is received
regardless of the current state of internal bus access.
In normal reset mode, the result on any bus operation that is in progress at the time the device changes state is not
guaranteed. However, acceptance of the operation reset (RST) request is guaranteed.
Setting the synchronous reset operation enable bit (TBCR.SYNCR) to “0” specifies normal reset mode.
Normal reset mode is the default setting after a settings initialization reset (INIT).
8.2 Synchronous Reset Operation
Synchronous reset operation refers to the mode when the device does not go to the operation reset (RST) state after a
operation reset (RST) request until after all bus access has halted.
In synchronous reset mode, the device does not go to the reset (RST) state when a reset (RST) request is received if
internal bus access is still in progress.
When such a reset request is received, a sleep request is issued to the internal bus. The device does not change to the
operation reset (RST) state until all buses have shutdown operation and changed to sleep mode.
In synchronous reset mode, the results of bus operations are guaranteed because the device does not change state until all
bus access has halted.
However, if bus access should not halt for some reason, no requests can be received while bus operation continues. In
such a case, the settings initialization reset (INIT) remains available at any time.
The following lists cases in which bus access may not stop:
If bus wait is enabled due to continuous input of RDY (ready request) to the external expansion bus interface. (However,
this does not apply to the MB91320 series as external bus operation is not supported.)
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Chapter 9 Reset
9.MCU Operation Mode
9. MCU Operation Mode
After release of a reset, the MCU starts operation in the mode specified by the mode pins and mode data.
Operation mode--+------Bus mode----+--------Single chip mode (0)
|
+{--------Internal ROM/external bus mode (1)
|
+{--------External ROM/external bus mode (2)
|
+------Access mode----+----16-bit bus width
(External bus)
+---- 8-bit bus width
Note: The MB91230 series only supports single chip mode.
9.1 Bus Modes and Access Modes
■ Bus mode
The bus mode controls internal ROM operation and the external access function. The bus mode is specified
by the mode setting pins (MD2, MD1, MD0) and internal ROM enable bit (Mode-Vector. ROMA).
The FR60Lite has the following three bus modes.
● Bus mode 0 (Single chip mode)
In this mode, internal I/O, internal RAM, and internal ROM are available but access to other areas is
disabled. External pins are used either by the peripheral functions or as general-purpose ports. Pins cannot
be used as bus pins.
● Bus mode 1 (Internal ROM, external bus mode)
Not supported on this model.
In this mode, internal I/O, internal RAM, and internal ROM are available, and access to areas for which
external access is enabled results in access to the external area. Some external pins function as bus pins.
● Bus mode 2 (External ROM, external bus mode)
Not supported on this model.
In this mode, internal I/O and internal RAM are available but access to internal ROM is prohibited.
Access to internal ROM areas and areas for which external access is enabled results in access to the
external area. Some external pins function as bus pins.
■ Access mode
The access mode controls the width of the external data bus and is set by the WTH[1:0] bits in the mode data.
As the MB91230 does not have an access mode setting because it does not support an external bus. However,
you should always set WTH[1:0]=“11” to select single chip mode.
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Chapter 9 Reset
10.Sample Program
10. Sample Program
■ Example code for reset vector and mode vector
The pragma asm directive is used as the program is coded in C.
/*---------------------------------------------------------------*/
/* MODE Vector (Vector No. 1) */
/*
*/
/* Fbus (40000H-200000H) = Ext.Bus
*/
/* 0x00000000: Ext.ROM, 8-bit_Ext.bus
*/
/* 0x01000000: Ext.ROM, 16-bit_Ext.bus
*/
/* 0x03000000: Ext.ROM, Singl_Chip
*/
/*
*/
/* FbusRAM:16KB, FbusROM:256KB = Int.Bus */
/* 0x04000000: Int.ROM, 8-bit_Ext.bus
*/
/* 0x05000000: Int.ROM, 16-bit_Ext.bus
*/
/* 0x07000000: Int.ROM, Singl_Chip
*/
/*---------------------------------------------------------------*/
#pragma asm
.import _ _ start
.section
mode_vector, data, locate=0x000ffff8
.data.w
0x07000000; Singl_Chip mode, Int.ROM
.section
int_vector, data, locate=0x000ffffc
.data.w
_ _ start
#pragma endasm
Mode vector
Reset vector
Label representing the start execution location for the program
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Chapter 9 Reset
11.Cautions
11. Cautions
• INIT pin input
Ensure that a settings initialization reset (INIT) is applied to this pin when the power is turned on. Also, after turning
on the power, ensure a sufficient oscillation stabilization wait time is provided for the oscillation circuit by holding
the input to the pin at the “L” level for the required time.
Note: The INIT reset triggered by INIT pin input initializes the oscillation stabilization wait time to its
minimum value.
• Watchdog reset
When a settings initialization reset (INIT) is triggered by a watchdog reset request, the oscillation stabilization time is
not initialized. Also, in main RUN or sub RUN mode, no oscillation stabilization wait occurs in response to a
watchdog reset request if the main clock is not halted.
• Software reset
If “1” (synchronous reset mode) is set to the synchronous reset operation enable bit (TBCR.SYNCR) when an
operation reset (RST) is triggered by a software reset request, the operation reset (RST) does not occur until all bus
access halts. Accordingly, there may be a long delay before the operation reset (RST) occurs, depending on the bus
usage.
• Settings initialization reset (INIT)
A settings initialization reset (INIT) invokes an operation reset (RST) after the oscillation stabilization wait time
elapses.
• Reset cause flags (INIT), (WDOG), and (SRST)
• Reading the reset cause register clears all the reset cause flags to “0”.
• If more than one reset occurs before the reset cause register is read, the flag values are ORed and more
than one flag may be set to “1”.
• Reset mode
A settings initialization reset (INIT) initializes the reset mode to normal reset mode.
• DMA controller
As the DMA controller halts any transfer when a request is received, it does not cause any delay in changing device
state. (However, this does not apply to the MB91320 as it does not support DMA.)
• Pin states during a reset
See “5. Terminal state table according to mode (Page No.40)” for details about pin states during a reset.
90
Chapter 10 Standby
1.Overview
Chapter 10 Standby
1. Overview
Two standby modes (low power consumption modes) are available.
• Sleep mode: Stops the program
• Stop mode: Shuts down the device
2. Features
■ Sleep mode
• Device state in sleep mode:
• Halts the program.
• CPU program execution only stops. Peripheral functions can continue to operate.
• The internal memory and internal bus halt.
• Transition to sleep mode:
• Sleep mode is invoked by the program.
• Recovery from sleep mode:
• Generation of a valid interrupt request ends sleep mode (returns to normal operation)
• An INIT pin input or generation of a watchdog reset invokes an initialization reset (INIT)
followed by an operation reset (RST).
■ Stop mode
• Device state in stop mode:
• The overall device halts.
• Internal circuits halt (with some exceptions)
• Internal clock signals halt (with some exceptions)
• Whether or not the oscillation circuit halts can be controlled by a setting (programmable).
• All external pins can be set to high impedance (programmable, excludes some pins)
• Transition to stop mode:
• Stop mode is invoked by the program.
• Recovery from sleep mode:
• The following four interrupt requests change the device to the oscillation stabilization wait state.
•External level-detect interrupt
•Interrupt generated by oscillation stabilization wait timer for the main clock when oscillation not halted.
•Clock timer interrupt when oscillation not halted.
•Real time clock interrupt when oscillation not halted.
• Input to the INIT pin invokes an initialization reset (INIT) followed by an oscillation stabilization delay and then an
operation reset (RST).
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Chapter 10 Standby
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
State transition control circuit
(for standby modes)
SYNCS
0
1
OSCD1
0
1
TB CR: bit0
Setting prohibited
Synchronous standby
SLEEP
STCR: bit7
0
1
Do not change to sleep mode.
Change to sleep mode.
Sleep signal
STOP
STCR: bit7
Stop signal
0
1
Do not change to stop mode.
STCR: bit0
Change to stop mode.
Do not halt main clock oscillation during stop mode.
Clock control
Halt main clock oscillation during stop mode.
HIZ
STCR: bit5
0
1
Maintain same states during stop mode.
Set pins to high impedance during stop mode.
SRST
Internal interrupts,
external interrupts
STCR: bit4
0
1
State
transition
control
circuit
Initialize settings (INIT)
Generate software reset.
Do not generate software reset.
INIT
Initialize operation (RST)
RSRR: bit7
INIT
0
1
No INIT pin input
INIT pin input occurred (INIT)
SRST
RSRR: bit3
0
1
No software reset (RST)
Software reset (RST) occurred
Counter cleared,
oscillation
stabilization
wait
Watchdog timer
WDOG
RSRR: bit5
0
1
No watchdog timeout
Watchdog timeout (INIT) occurred
Standby control
Oscillation stabilization
wait finished
Time-base counter
(oscillation stabilization wait)
Figure 3-2 Register List
92
Pin control
Chapter 10 Standby
4.Registers
4. Registers
4.1 STCR: Standby Control Register
Used to control transition to the stop and sleep standby modes, and to specify the pin states and whether to halt the
oscillation during stop mode.
Note: See “Chapter 9 Reset (Page No.77)” also.
• STCR: Address 0481h (Access: Byte)
7
STOP
6
SLEEP
5
HIZ
4
SRST
3
OS1
2
OS0
1
OSCD2
0
OSCD1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
1
1
0
R/W
0
R/W
X
R/W
1
R1, W
X
R/W
X
R/W
X
R/W
X
R/W
bit
Initial value
(INITX pin input)
Initial value
(Watchdog reset)
Initial value (Software reset)
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
• Bit7: Stop mode
STOP
0
1
Operation
Does not change to stop mode.
Changes to stop mode.
• Goes to “0” when a reset (INIT pin input or software reset) occurs or on recovery from stop mode.
• Going directly from main PLL operation to stop mode is prohibited. (See “9. Cautions (Page No.102)”.)
• Bit6: Sleep mode
SLEEP
0
1
Operation
Does not change to sleep mode.
Changes to sleep mode.
• If this bit and the stop mode bit (STOP) bit are set to “1” at the same time, the device goes to stop mode.
• Goes to “0” when a reset (INIT pin input or software reset) occurs or on recovery from sleep mode.
• Bit5: High impedance mode
HIZ
0
1
Operation
Maintain same pin states when changing to stop mode.
Set pin outputs to high impedance (Hi-z) during stop mode.
• The default setting is high impedance.
• Bit4: Software reset (SRST)
• Setting this bit to “0” invokes a software reset.
• Bit3-2: Oscillation stabilization time selection (OS[1:0])
• Setting these bits in the range “00”-“11” sets the oscillation stabilization time to use after recovering from stop
mode.
An INIT pin input reset or watchdog reset initialize this setting to its initial value.
(See “Chapter 12 Timebase Counter (Page No.119)”.)
• Bit1: Reserved bit (OSCD2)
• Set the same value to the OSCD2 bit as you set to the main clock oscillation halt bit (OSCD1).
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Chapter 10 Standby
4.Registers
• Bit0: Main clock oscillation halt
OSCD1
0
1
Operation of main clock during stop mode
Continue oscillation
Halt oscillation
4.2 TBCR: Timebase timer control register
This register controls the timebase timer interrupts and the options for resets and standby operation.
Note: See also “Chapter 13 Timebase Timer (Page No.135)”.
• TBCR: Address 0482h (Access: Byte)
7
TBIF
6
TBIE
5
TBC2
4
TBC1
3
TBC0
2
---
1
SYNCR
0
SYNCS
0
0
X
X
X
X
0
0
0
0
X
X
X
X
X
X
R(RM1),W
R/W
R/W
R1,W
R/W
RX/WX
RX/WX
R/W
bit
Initial value (INIT pin,
watchdog)
Initial value (Software
reset)
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
• Bit7: Interrupt request flag for timebase timer
• This flag goes to “1” when a timebase timer interrupt request occurs
• Bit6: Interrupt request enable for the timebase timer
• Writing “1” to this bit enables timebase timer interrupt requests.
• Bit5-3: Interval time selection for timebase timer
• Writing a value in the range “000”-“111” to these bits selects the interval time for the timebase timer.
(Φ × 211, × 212, × 213, × 222, × 223, × 224, × 225, × 226)
• Bit2: ReservedWriting does not affect the operation. The read value is undefined.
• Bit1: Enable synchronous reset operation
• Selects a normal reset “0” or a synchronous reset “1”.
• Bit0: Enable synchronous standby operation
SYNCS
0
1
94
Operation
Normal reset operation (Not permitted on this model).
Enable synchronous standby operation (always set this before changing to a standby mode).
Chapter 10 Standby
5.Operation
5. Operation
5.1 Sleep Mode
■ Entering sleep mode
Writing “1” to the sleep mode bit (STCR.SLEEP) changes to sleep mode. The device remains in this mode until an event
occurs to wakeup the device from sleep mode.
(See “9. Cautions (Page No.102)”.)
■ Device state in sleep mode
• CPU program execution stops. (Peripheral functions continue to operate.)
• The internal memory and internal bus halt.
• Circuits that halt during sleep mode
• Bit search module
• All internal memory
• Internal/external bus (However, this device does not support an external bus)
• Circuits that do not halt during sleep mode
• Oscillation circuit, main PLL (if enabled)
• clock generation control circuit
• Interrupt controller
• external interrupts
• Clock timer
• oscillation stabilization timer for main clock
• Active peripherals
(A/D, D/A, PWC, clock monitor, LCDC, U-timer, UART, PPG, free-run timer, input capture, output compare, reload
timer, up/down counter, real-time clock)
■ Recovery and other items
• Generation of an interrupt request that is currently enabled changes the device back to RUN mode. (Restores normal
operation.)
• An INIT pin input or generation of a watchdog reset invokes an initialization reset (INIT) followed by an operation reset
(RST).
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Chapter 10 Standby
5.Operation
5.2 Stop mode
■ Entering stop mode
Writing “1” to the stop mode bit (STCR.STOP) changes to stop mode.
The device remains in this mode until an event occurs to wakeup the device from stop mode.
(See “9. Cautions (Page No.102)”.)
■ Device state in sleep mode
• The overall device halts (internal circuits halt and the internal clock signals halt).
• Circuits that halt during stop mode
All internal circuits except those listed below.
• Circuits that do not halt during stop mode
• Oscillation circuits that are not specified to be halted
•
Oscillation circuit for subclock
•
Oscillation circuit for main clock (if enabled)
•
Main PLL circuit if oscillation is enabled and circuit not specified to be halted.
•
Oscillation stabilization timer for main clock if main clock oscillation is enabled
• Peripheral functions that are driven directly by the subclock and which have not been specified to be
halted.
•
Clock timer
•
Real-time clock (if not halted)
•
LCDC (if LCD display enabled for sub-stop mode and subclock selected as the clock source.)
• Pin states (High impedance or maintain previous state)
• When pin outputs are set to go to high impedance during stop mode
•
High impedance output:
P0, P2, P3, P4, PC, PD, PF, and pins in P1, P5, P6, P7, P8, P9, PA and PB that are set as general
purpose ports.
•
Maintain previous state:
Pins in P6, P7, P8, P9, PA, and PB that have been selected for use by peripheral functions.
• When pin outputs are set to maintain their previous states during stop mode
•
Maintain previous state:
P0, P2, P3, P4, P6, P7, P8, P9, PA, PB, PC, PD, PF, and pins in P1 and P5 that are set as general
purpose ports.
• When set as external interrupts
•
Input available state:
Pins in P1 and P5 set as external interrupt inputs using level detection.
(Whether the pin output during stop mode has been set to either high impedance or maintain
previous state.)
■ Recovery and other items
• Any of the following interrupt requests cause the device to go to the oscillation stabilization wait RUN
state and then to change back to RUN mode after the oscillation stabilization time elapses (return to normal
operation).
• External interrupts set to level detection and that do not require a specific clock.
• Oscillation stabilization timer interrupt for the main clock (if operating)
• Clock timer interrupt (if operating)
• Real-time clock interrupt (if operating)
96
• An INIT pin input or generation of a watchdog reset invokes an initialization reset (INIT) followed by an
operation reset (RST) after the oscillation stabilization time.
Chapter 10 Standby
6.Settings
6. Settings
Table 6-1 Settings Required to Change to Sleep Mode
Setting
Setting
procedure*
Setting register
Interrupt settings
(See the chapter for each peripheral function.)
—
Synchronous standby settings
Timebase timer control register (TBCR)
See 7.1
Change to sleep mode
Standby control register (STCR)
See 7.1
Operational restrictions
(See “9. Cautions (Page No.102)”.)
—
*:For the setting procedure, refer to the section indicated by the number.
Table 6-2 Settings Required to Change to Stop Mode
Setting
Setting
procedure*
Setting register
Selects the oscillation stabilization
wait time
(See “Chapter 12 Timebase Counter (Page No.119)”.)
—
Interrupt settings
(See the chapter for each peripheral function.)
—
Synchronous standby settings
Timebase timer control register (TBCR)
See 7.2
Change to stop mode
Standby control register (STCR)
See 7.2
Operational restrictions
(See “9. Cautions (Page No.102)”.)
—
*: For the setting procedure, refer to the section indicated by the number.
7. Q&A
7.1 How do I change to sleep mode?
Before you can change to sleep mode, you must first set the synchronous standby operation enable bit (TBCR.SYNCS).
Operation
To enable synchronous standby operation
Synchronous standby operation enable bit (SYNCS)
Set to “1”.
Note: Setting (SYSNCS=“0”) is prohibited.
Set using the sleep mode bit (STCR.SLEEP).
Operation
When you do not want to change to sleep mode
To change to sleep mode
Sleep mode bit (SLEEP)
Set to “0”.
Set to “1”.
Note: Some restrictions apply when changing to sleep mode. See “9. Cautions (Page No.102)” for details.
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Chapter 10 Standby
7.Q&A
7.2 How do I change to stop mode?
• When operating on the main PLL clock, the operating clock must be set to the main clock divided by two.
See “7.3 How do I select the operating clock source? (Page No.113)” for details about changing the
operating clock.
• Before you can change to stop mode, you must first set the synchronous standby operation enable bit
(TBCR.SYNCS). See section 7.1.
• Set using the stop mode bit (STCR.STOP).
Operation
When you do not want to change to stop mode
To change to stop mode
Stop mode bit (STOP)
Set to “0”.
Set to “1”.
Note: Some restrictions apply when changing to stop mode. See “9. Cautions (Page No.102)” for
details.
7.3 How do I set pins to high impedance (Hi-z) during stop mode?
Set using the high impedance mode bit (STCR.HIZ).
Operation
When you do not want to set pins to high impedance during stop
mode
To set pins to high impedance during stop mode
High impedance mode bit (HIZ)
Set to “0”.
Set to “1”.
Note: Some ports do not go to high impedance in some circumstances. (See “5.2 Stop mode (Page
No.96)”.)
7.4 How do I halt the main clock oscillation during stop mode?
Use the main clock oscillation stop bit (STCR.OSCD1).
Operation
When you do not want to halt the main clock oscillation in stop
mode
To halt the main clock oscillation during stop mode
Main clock oscillation stop bit (OSCD1)
Set to “0”.
Set to “1”.
7.5 How do I recover from sleep mode?
Two methods are available to recover from sleep mode.
• Generation of a valid interrupt request changes to RUN mode (restores normal operation).
If using interrupt processing, remember to set the I flag (I), interrupt level mask register (ILM), and
interrupt control register (ICR).
• An INIT pin input or generation of a watchdog reset invokes an initialization reset (INIT) followed by an
operation reset (RST).
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Chapter 10 Standby
7.Q&A
7.6 How do I recover from stop mode?
The following events end stop mode:
• The following four interrupts change the device to the oscillation stabilization wait state.
• External level-detect interrupt
• Oscillation stabilization wait timer for the main clock when oscillation not halted.
• Clock timer when oscillation not halted.
• Real time clock when oscillation not halted.
If using interrupt processing, remember to set the I flag (I), interrupt level mask register (ILM), and interrupt control
register (ICR).
• Input to the INIT pin invokes an initialization reset (INIT) followed by an oscillation stabilization delay and then an
operation reset (RST).
In the case of an INIT pin input, an oscillation stabilization wait is required, depending on the width of the INIT pin
input.
See also “Chapter 11 Clock Control (Page No.103)” and “Chapter 12 Timebase Counter (Page No.119)”.
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Chapter 10 Standby
8.Sample Programs
8. Sample Programs
• Sleep mode
void SLEEP(void)
{
IO_CLK.IO_TBCR.bit.SYNCS = 1; /* Synchronous standby */
#pragma asm
STM0 (R0)
STM1 (R12)
LDI #0x53, r0
LDI #0x481, r12
STB r0, @r12
LDUB @r12, r0
LDUB @r12, r0
NOP
NOP
NOP
NOP
NOP
LDM1 (R12)
LDM0 (R0)
#pragma endasm
}
• Stop mode (clock does not halt, ports maintain existing levels)
void STOP_hold_with_clock(void)
{
IO_CLK.IO_TBCR.bit.SYNCS = 1;
/* Synchronous standby */
#pragma asm
STM0 (R0)
STM1 (R12)
LDI #0x90, r0
LDI #0x481, r12
STB r0, @r12
LDUB @r12, r0
LDUB @r12, r0
NOP
NOP
NOP
NOP
NOP
LDM1 (R12)
LDM0 (R0)
#pragma endasm
}
Note: See “9. Cautions (Page No.102)”.
100
Chapter 10 Standby
8.Sample Programs
• Stop mode (clock halts, ports go to high impedance)
void STOP_Hiz_no_clock(void)
{
IO_CLK.IO_TBCR.bit.SYNCS = 1;
/* Synchronous standby */
#pragma asm
STM0 (R0)
STM1 (R12)
LDI #0xBB, r0
LDI #0x481, r12
STB r0, @r12
LDUB @r12, r0
LDUB @r12, r0
NOP
NOP
NOP
NOP
NOP
LDM1 (R12)
LDM0 (R0)
#pragma endasm
}
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Chapter 10 Standby
9.Cautions
9. Cautions
• Points to note when changing to sleep mode
When changing to sleep mode, set the synchronous standby operation enable bit (TBCR.SYNCS= “1”).
Also, in order to change to sleep mode with synchronous standby operation enabled, the STCR register
must be read after writing to the SLEEP bit. Always use the following sequence.
(LDI
(LDI
STB
LDUB
LDUB
NOP
NOP
NOP
NOP
NOP
#value_of_sleep, R0)
#_STCR, R12)
R0, @R12
@R12, R0
@R12, R0
; value_of_sleep contains the write data for STCR.
; _STCR is the address of STCR (481H).
; Write to standby control register (STCR).
; STCR read required for synchronous standby.
; Second dummy read to STCR.
; NOP x 5 required for timing
• Points to note when changing to stop mode
When changing to sleep mode, set the synchronous standby operation enable bit (TBCR.SYNCS= “1”).
Also, in order to change to stop mode with synchronous standby operation enabled, the STCR register
must be read after writing to the STOP bit. Always use the following sequence.
(LDI
(LDI
STB
LDUB
LDUB
NOP
NOP
NOP
NOP
NOP
#value_of_stop, R0)
#_STCR, R12)
R0, @R12
@R12, R0
@R12, R0
; value_of_stop contains the write data for STCR.
; _STCR is the address of STCR (481H).
; Write to standby control register (STCR).
; STCR read required for synchronous standby.
; Second dummy read to STCR.
; NOP x 5 required for timing
• When the main PLL is selected as the operation clock source
When the main PLL is selected as the operation clock source, change the operation clock source selection
to main clock divided by two before changing to stop mode.
See “5.3 Notes (Page No.111)” for details.
The restrictions that apply to the clock divide ratio setting are the same as for normal operation. Also, you
do not necessarily have to halt the PLL oscillation.
• If interrupts are disabled in the interrupt control register (ICR=“00011111B”), the device will not recover from
stop or sleep mode when an interrupt occurs.
• Always set the OSCD2 bit in the standby control register (STCR) to the same value as the OSCD1 bit.
• Pin high impedance control in stop mode
Setting the high impedance bit (STCR.HIZ) to “1” sets pin outputs to high impedance during stop mode.
If the high impedance bit (STCR.HIZ) is set to “0”, pins retain the states they have prior to entering stop
mode.
See “5. Terminal state table according to mode (Page No.40)” for details such as the operation of specific
pins.
102
Chapter 11 Clock Control
1.Overview
Chapter 11 Clock Control
1. Overview
The clock control circuit consists of the source oscillator, base clock generator, and operating clock generator.
The circuit supports a range of clock speeds from the high speed clock (33.6MHz maximum) to the low speed clock
(32.768kHz).
Source oscillation
Main clock
(source oscillation)
Base clock generator
Operating clock generator
Divide by 2
PLL
Selector
Sub clock
(source oscillation)
Divider
CPU clock
Divider
Peripheral clock
Divider
External bus clock
Base clock
2. Features
■ Source oscillation
• Main clock (FCL-MAIN): 4MHz
Input from the X0/X1 pins and used as the high speed clock
• Subclock (FCL-SUB): 32.768kHz
Input from the X0A/X1A pins and used as the low speed clock
■ Base clock (Φ): Selectable from 3 different clocks
• Main PLL (8 speeds) : FCL-MAINx1, x2, x3, x4, x5, x6, x7, x8
• Main clock divided by 2: FCL-MAIN divided by 2
• Subclock
: FCL-SUB
■ Operating clocks: Selectable from 9 different speeds
• CPU clock (CLKB): Φ/1, /2, /3, /4, /5, /6, /7, /8, /16
The clock used by the CPU, internal memory, and internal buses. The circuits that use this clock are as follows.
• CPU, internal RAM, internal ROM, bit search module,
• I bus, D bus, F bus, X bus
• On-chip debug support unit (DSU)
• Peripheral clock (CLKP): Φ/1, /2, /3, /4, /5, /6, /7, /8, /16
The clock used by the peripheral functions and peripheral bus. The circuits that use this clock are as follows.
• Peripheral bus
• Clock controller (bus interface unit only)
• Interrupt controller
• I/O ports
• External interrupt inputs, UART, 16-bit timer, and similar peripheral functions
103
Chapter 11 Clock Control
3.Configuration
• External bus clock (CLKT): Φ/1, /2, /3, /4, /5, /6, /7, /8, /16
The clock used by the external bus expansion interface. The circuits that use this clock are as follows.
• External bus expansion interface
• External CLK output
Note: The MB91230 does not support the external bus interface.
3. Configuration
Figure 3-1 Configuration Diagram
CLKR: bit2
0
1
Halt PLL
Enable (start) PLL
OSCDS 1
X0
PLL1S2CLKR: bit6-4
PLL1S0
PLL1EN
OSCCR: bit0
0
Main clock continues to
run in subclock mode
1
Main clock halts in
subclock mode
PLL2EN
CLKR: bit3
0
1
Subclock selection prohibited
Subclock selection enabled
OSCD1
STCR: bit0
0
1
Continue oscillation in stop mode
1111
CPU clock
(F CLKB)
Peripheral clock
(F CLKP)
Divider
Base
clock
(φ)
Divider
CLKS1CLKS0
00
10
11
CLKR: bit6-4
Main clock divided by 2
(main clock mode)
Main clock divided by 2
(main clock mode)
Main PLL
(main clock mode)
Subclock
(subclock mode)
Permitted
change
00=>01, 10
01=>11, 00
10=>00
11=>01
P3-P0
0000
0001
0010
0011
0100
0101
0110
0111
1000-1110
Figure 3-2 Register List
104
1000-1110
DIV R1: bit 7-4
No division
Divide by 2
Divide by 3
Divide by 4
Divide by 5
Divide by 6
Divide by 7
Divide by 8
Prohibited setting
Divide by 16
External bus clock
(F CLKT)
Base clock (φ)
01
Halt oscillation in stop mode
T3-T0
0000
0001
0010
0011
0100
0101
0110
0111
DIV R0: bit 7-4
No division
Divide by 2
Divide by 3
Divide by 4
Divide by 5
Divide by 6
Divide by 7
Divide by 8
Prohibited setting
Divide by 16
Divider
Selector
Subclock
source
( F CLK-SUB )
X0A
1000-1110
PLL
Divide by 2
X1A
x1
x2
x3
x4
x5
x6
x7
x8
1111
Main clock
source
(F CLK-MAIN )
X1
000
001
010
011
100
101
110
111
B3-B0
0000
0001
0010
0011
0100
0101
0110
0111
1111
DIV R1: bit3-0
No division
Divide by 2
Divide by 3
Divide by 4
Divide by 5
Divide by 6
Divide by 7
Divide by 8
Prohibited setting
Divide by 16
Chapter 11 Clock Control
4.Registers
4. Registers
4.1 CLKR: Clock Source Control Register
Selects the clock source for the base clock used to run the MCU and controls the PLL.
• CLKR: Address 0484h (Access: Byte)
7
-
6
PLLS2
5
PLLS1
4
PLLS0
3
PLL2EN
2
PLL1EN
1
CLKS1
0
CLKS0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
R/W0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit
Initial value (INIT pin input,
watchdog reset)
Initial value
(Software reset)
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
• Bit7: Reserved bitAlways write “0” to this bit. The read value is the value written.
• Bit6-4: PLL multiplier selection
000
Φ: Base clock (PLL multiplier)
Source (FCL-MAIN) × 1 (no multiplier)
001
Source (FCL-MAIN) × 2 (multiply by 2)
010
Source (FCL-MAIN) × 3 (multiply by 3)
011
Source (FCL-MAIN) × 4 (multiply by 4)
100
Source (FCL-MAIN) × 5 (multiply by 5)
101
Source (FCL-MAIN) × 6 (multiply by 6)
110
Source (FCL-MAIN) × 7 (multiply by 7)
111
Source (FCL-MAIN) × 8 (multiply by 8)
PLLS2-PLLS0
• The value of these bits may not be modified while the PLL multiplier selection bits (PLLS[2:0]) select main PLL as
the clock source (CLKS[1:0]=“10”) (the result of such an operation is not guaranteed). Only modify these bits when
the either the main clock divided by 2 or the subclock is selected.
• Do not set a speed that exceeds the maximum permitted frequency.
(See the explanation for the clock source selection bits (CLKS[1:0]) for details of how to change the clock source.)
• Bit3: Subclock select enable
PLL2EN
0
1
Function
Prohibit subclock selection [Initial value]
Enable subclock selection
• Modifying the subclock selection enable bit (PLL2EN) while the subclock is selected as the clock source
(CLKS[1:0]=“11”) is prohibited (result is not guaranteed). Only modify the setting when the main clock is selected.
(See the explanation for the clock source selection bits (CLKS[1:0]) for details of how to change the clock source.)
• Bit2: Enable main PLL operation
PLL1EN
0
1
Function
Halt main PLL (Initial value)
Enable main PLL operation
• Modifying the main PLL operation enable bit (PLL1EN) while the main PLL is selected as the clock source
(CLKS[1:0]=“10”) is prohibited.
• If the main clock oscillation is halted (STCR.OSCD1=“1”), the main PLL halts during stop mode even if the PLL
enable bit (PLL1EN) is set to “1”. If main PLL operation is enabled (PLL1EN=“1”), the main clock operates using
the PLL after recovering from stop mode.
105
Chapter 11 Clock Control
4.Registers
(See the explanation for the clock source selection bits (bits 1-0:) for details of changing the clock source.)
• Bit1-0: Clock source selection
CLKS1
0
0
1
1
CLKS0
0
1
0
1
Clock source setting
Main clock input from X0/X1 divided by 2 (Initial value)
Main clock input from X0/X1 divided by 2
Main PLL
Subclock
Mode
Main clock mode
Main clock mode
Main clock mode
Subclock mode
• When changing the clock mode, the value of CLKS0 may not be modified while CLKS1 is “1”.
The table below lists the cases in which the CLKS1- CLKS0 bits may be modified.
• There is no setting to select the subclock divided by 2.
• After setting “11B” (subclock), insert one or more NOP instructions.
• Selecting the subclock as the clock source is prohibited while the subclock selection enable bit (PLL2EN) is “0”.
(See table for details.)
Table 4-1 Cases When the CLKS1 and CLKS0 Bits May or May Not be Modified
Modify permitted
“00” → “01” or “10”
“01” → “11” or “00”
“10” → “00”
“11” → “01”
Modify not permitted
“00” → “11”
“01” → “10”
“10” → “01” or “11”
“11” → “00” or “10”
Example: To select the subclock after an INIT reset, first write “01B” and then write “11B” (subclock).
(See “9. Cautions (Page No.118)”.)
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Chapter 11 Clock Control
4.Registers
4.2 DIV0: Clock Division Setting Register 0
Sets the divide ratio for the clocks used for internal device operation.
DIVR0: Address 0486h (Access: Byte, Half-word)
7
B3
6
B2
5
B1
4
B0
3
P3
2
P2
1
P1
0
P0
0
0
0
0
0
0
1
1
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit
Initial value (INIT pin input,
watchdog reset)
Initial value
(software reset)
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
• Sets up the clock for the CPU and internal buses (CLKB), and the clock for the peripheral circuits and peripheral
bus (CLKP).
• Bit7-4: CLKB divide selection
B3-B0
0000
0001
0010
0011
0100
0101
0110
0111-1110
1111
CPU clock (CLKB) divide ratio
Φ/2
Φ/3
Φ/4
Φ/5
Φ/6
Φ/7
Φ/8
Prohibited setting
Φ/16
• Sets the clock divide ratio for the clock used by the CPU, internal memory, and internal buses (CLKB).
The 16 options listed in the table are available.
• Do not set a divide ratio that exceeds the maximum operating frequency of the device.
• Bit3-0: CLKP divide selection
P3-P0
0000
0001
0010
0011
0100
0101
0110
0111-1110
1111
Peripheral clock (CLKP) divide ratio
Φ/2
Φ/3
Φ/4
Φ/5
Φ/6
Φ/7
Φ/8
Prohibited setting
Φ/16
• Sets the clock divide ratio for the clock used by the peripheral circuits and peripheral bus (CLKP).
The 16 options listed in the table are available.
• Do not set a divide ratio that exceeds the maximum operating frequency of the MCU.
107
Chapter 11 Clock Control
4.Registers
4.3 DIV1: Clock Division Setting Register 1
Sets the divide ratio for the clocks used for internal device operation.
• DIVR1: Address 0487h (Access: Byte, Half-word)
7
T3
0
X
R/W
6
T2
0
X
R/W
5
T1
0
X
R/W
4
T0
0
X
R/W
3
–
0
X
R/W
2
–
0
X
R/W
1
–
0
X
R/W
0
–
0
X
R/W
bit
Initial value (INIT pin input, watchdog reset)
Initial value (software reset)
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
Sets the clock divide ratio (relative to the base clock) for the clock used by the external bus interface (CLKT).
• Bit7-4: CLKT divide selection
T3-T0
0000
0001
0010
0011
0100
0101
0110
0111-1110
1111
External bus clock (CLKT) divide ratio
Φ/2
Φ/3
Φ/4
Φ/5
Φ/6
Φ/7
Φ/8
Prohibited setting
Φ/16
• Sets the clock divide ratio for the clock used by the external bus interface (CLKT).
The 16 options listed in the table are available.
• Do not set a divide ratio that exceeds the maximum operating frequency of the device.
• If you modify the CLKP divide selection bits, the new division ratio applies from the next clock after the setting is
modified.
• As the MB91230 series does not support an external bus, setting these bits to “0000h” is recommended.
• Bit3-0: Reserved bit Always write “0” to this bit. The read value is the value written.
108
Chapter 11 Clock Control
4.Registers
4.4 OSCCR: Oscillation Control Register
This register controls the main clock oscillation in subclock mode
• OSCCR: Address 048Ah (Access: Byte)
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
OSCDS1
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
0
RX/WX
RX/WX
RX/WX
RX/WX
RX/WX
RX/WX
RX/WX
R/W
bit
Initial value (INIT pin
input, watchdog reset)
Initial value
(software reset)
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
• bit7-1: Undefined bit
Writing does not affect the operation. The read value is undefined.
• bit0: Halt main clock oscillation in subclock mode bit
OSCDS1
Operation when written to
0
Does not halt main clock during subclock mode.
1
Halt main clock during subclock mode.
Read value meaning
Main clock mode can be selected after the
oscillation stabilization time elapses.
Selecting main clock mode is prohibited.
• When the main clock is selected (CLKS[1:0]=“00”, “01”, “10”), specifying the main clock to halt during subclock
mode (OSCDS1=“1”) is prohibited.
(See “9. Cautions (Page No.118)”.)
109
Chapter 11 Clock Control
5.Operation
5. Operation
This section describes how to setup and switch between clocks.
5.1 Clock Setup Sequence (Example)
(1) Main clock oscillation stabilization, sub clock oscillation stabilization
(2) Operate using initial values (main clock divided by 2).
Setup
operating
clocks.
(2) Set divide ratios for operating clocks. (CLKB, CLKP, CLKT)
(3) Select PLL multiplier. ( PLLS[2:0] )
(4) Enable main PLL operation (PLL1EN), and enable sub clock operation (PLL2EN).
(4) Wait for main PLL to lock (See oscillation stabilization wait chapter).
Setup
base
clock.
(5) Select clock source. (CLKS[1:0] )
Main clock mode (divided by 2)
(“00”)
Main clock mode (divided by 2)
(“01”)
Main PLL mode
(“10”)
Sub clock mode
(“11”)
5.2 Halting and Restarting the Main Clock Oscillation During Subclock Mode (Example)
(1) Select sub clock mode.
Select clock source. (CLKS [1:0] = “11”)
Sub clock mode
with main clock
halted
(2) Halt main PLL (PLL1EN = "0"), halt main clock oscillation (OSCDS1 = "0")
(3) Change to standby mode
(See standby chapter.)
(3) Recover from standby mode.
Sub clock mode operation
(See standby chapter.)
(4) Main clock oscillation (OSCDS1 = “0”)
Main clock oscillation stabilization (See oscillation stabilization wait chapter)
(1) Select main clock mode (divided by 2).
Select clock source. (CLKS[1:0] = “01”)
Change to main
PLL operation
(1) Start main PLL oscillation (PLL1E = “01”)
(4) Wait for main PLL to lock
(See oscillation stabilization wait chapter)
(5) Select main PLL mode.
Select clock source. (CLKS[1:0] = “00”)
Select clock source. (CLKS[1:0] = “11”)
110
Chapter 11 Clock Control
5.Operation
5.3 Notes
■ Main PLL control
After initialization, the main PLL oscillation is halted. While halted, the output of the main PLL cannot be selected as the
clock source.
After the program starts, first set the multiplier for the main PLL that you want to use as the clock source and then, after
allowing a time for the main PLL to lock, change the clock source. The recommended method for waiting for the main
PLL to lock is to use the timebase timer interrupt.
You cannot halt the main PLL while the output of the main PLL is selected as the clock source.
Writing to the register has no effect. If you wish to stop the main PLL such as when changing to stop mode, first select
the main clock divided by 2 as the clock source and then halt the main PLL.
If the main clock oscillation is set to halt during stop mode by the main clock oscillation stop bit (STCR.OSCD1=“1”),
the main PLL stops automatically when the MCU changes to stop mode and you do not need to halt the main PLL
(CLKR.PLL1EN=“0”) explicitly beforehand. The main PLL also restarts automatically on recovering from stop mode.
When the oscillation is not set to halt during stop mode (STCR.OSCD1=“0”), the main PLL does not stop automatically.
In this case, halt the main PLL explicitly (CLKR.PLL1EN=“0”) before changing to stop mode.
■ Main PLL multiplier
When changing the main PLL multiplier setting to a value different to the initial value, set this before or at the same time
as you enable the main PLL after program execution starts. After changing the multiplier setting, wait for the main PLL
lock time before switching the clock source. The recommended method for waiting for the main PLL to lock is to use the
timebase timer interrupt.
To modify the main PLL multiplier setting during normal operation, first change the clock source to something other than
the main PLL. As in the above case, after changing the multiplier setting, wait for the main PLL lock time before
changing the clock source.
The main PLL multiplier setting can be changed while the main PLL is in use. In this case, the MCU automatically goes
to the oscillation stabilization wait state after the multiplier setting is modified and program execution halts for the time
specified as the oscillation stabilization wait time. Program execution doe not halt when changing to a clock source other
than the main PLL.
■ Clock division
The clocks used to drive the internal operation of the device allow divide ratios relative to the base clock to be set
independently for each clock. This function allows the optimum operating frequency to be selected for each circuit.
The divide ratios are set in the operating clock division setting registers (DIVR0 and DIVR1). These registers contain 4bit settings that specify the ratio for each clock. The divide ratio relative to the base clock = (register value+1). The duty
ratio is always 50, even if an odd numbered divide ratio is set.
If a setting is modified, the new setting applies from the next rising edge of the clock.
The divide ratio settings are not initialized by an operation reset (RST) and the settings from before the reset are
maintained. The ratio settings are only initialized by a settings initialization reset (INIT). When changing the clock source
from its initial setting to a high speed clock, always set the divide ratio first.
Device operation is not guaranteed if the result of the clock source selection, main PLL multiplier setting, and divide ratio
setting is a frequency that is higher than the maximum permitted frequency. Please take care with these settings. (In
particular, take care with the sequence in which you change clock source settings.)
111
Chapter 11 Clock Control
6.Settings
6. Settings
Table 6-1 Settings for Operating at 1/2 of the Main Clock
Setting
Clock source selection
Setting register
Clock source control register (CLKR)
Setting
procedure*
See 7.3
*: For the setting procedure, refer to the section indicated by the number.
Table 6-2 Settings for Operating Using the Main PLL
Setting
Main PLL operation enable
Clock source selection
Setting register
Clock source control register (CLKR)
Setting
procedure*
See 7.1
See 7.3
*: For the setting procedure, refer to the section indicated by the number.
Table 6-3 Settings for Operating Using the Subclock
Setting
Subclock selection enable
Clock source selection
Setting register
Clock source control register (CLKR)
Setting
procedure*
See 7.1
See 7.3
*: For the setting procedure, refer to the section indicated by the number.
Table 6-4 Settings for Selecting the Divide Ratio for the Operating Clocks
Setting
Clock source selection
Operating clock divide ratio selection
Setting register
Clock source control register (CLKR)
Operating clock division setting registers
(DIVR0, DIVR1)
*: For the setting procedure, refer to the section indicated by the number.
112
Setting
procedure*
See 7.3
See 7.4
Chapter 11 Clock Control
7.Q & A
7. Q & A
7.1 How do I enable or disable clock operation?
• There is no operation enable bit for the main clock. Main clock operation is always enabled.
(Halting the oscillation in subclock mode or stop mode is handled separately.)
• Main PLL operation is enabled by the main PLL operation enable bit (CLKR.PLL1EN).
Operation
To halt the main PLL
To enable operation of the main PLL
Main PLL operation enable bit (PLL1EN)
Set to “0”.
Set to “1”.
Initially, the PLL is halted and therefore PLL operation must be enabled and the PLL started after setting the PLL multiplier ratio.
• The subclock on the MB91230 does not halt and therefore no corresponding operation enable bit is provided.
Instead, the subclock selection enable bit (CLKR.PLL2EN) is used.
Operation
Subclock selection prohibited
To enable selection of the subclock
Subclock selection enable bit (PLL2EN)
Set to “0”.
Set to “1”.
7.2 How do I select the main PLL multiplier ratio?
Use the main PLL multiplier bits (CLKR.PLL1S[2:0]).
To select a x1 multiplier ratio
Set to “000”.
Example frequency:
For a 4.000MHz main clock
FΦ = 4.0MHz (Φ=250ns)
To select a x2 multiplier ratio
Set to “001”.
FΦ = 8.0MHz (Φ=125ns)
To select a x3 multiplier ratio
Set to “010”.
FΦ = 12MHz (Φ=83.33ns)
To select a x4 multiplier ratio
Set to “011”.
FΦ = 16MHz (Φ=62.50ns)
To select a x5 multiplier ratio
Set to “100”.
FΦ = 20MHz (Φ=50.00ns)
To select a x6 multiplier ratio
Set to “101”.
FΦ = 24MHz (Φ=41.67ns)
To select a x7 multiplier ratio
Set to “110”.
FΦ = 28MHz (Φ=35.71ns)
To select a x8 multiplier ratio
Set to “111”.
FΦ = 32MHz (Φ=31.25ns)
PLL multiplier
Main PLL multiplier selection bit
(PLL1S[2:0])
7.3 How do I select the operating clock source?
Use the clock source selection bits (CLKR.CLKS[1:0]) to select main clock divided by 2, main PLL, or the subclock as
the operating clock source.
Operating clock source
Clock source selection bits (CLKS[1:0])
To change from the initial value to the main clock divided by 2 Set initial values “00” or “01”.
To change from the initial value to the main PLL
Change from the initial values “00” to “10”.
First change from the initial values “00” to “01”, and
To change from the initial value to the subclock
then to “11”.
To change from the subclock to the main clock divided by 2
Change from “11” to “01”.
First change from “11” to “01”, next set
To change from the subclock to main PLL
“00”, and then set “10”.
To change from main PLL to the main clock divided by 2
Change from “10” to “00”.
First change from “10” to “00”, next set
To change from main PLL to the subclock
“01”, and then set “11”.
113
Chapter 11 Clock Control
7.Q & A
7.4 How do I set the operation clock divide ratios?
• CPU clock setting
The CPU clock setting is set using the CLKB divide ratio selection bits (DIVR0.B[3:0]).
Example frequency
When FΦ = 32MHz When FΦ = 16MHz
PLL multiplier ratio
CLKB divide ratio selection
bits(B[3:0])
To select no division
Set to “0000”.
FCLKB = 32.0MHz
FCLKB = 16.0MHz
To select divide by 2
Set to “0001”.
FCLKB = 16.0MHz
FCLKB = 8.00MHz
To select divide by 3
Set to “0010”.
FCLKB = 10.6MHz
FCLKB = 5.33MHz
To select divide by 4
Set to “0011”.
FCLKB = 8.00MHz
FCLKB = 4.00MHz
To select divide by 5
Set to “0100”.
FCLKB = 6.40MHz
FCLKB = 3.20MHz
To select divide by 6
Set to “0101”.
FCLKB = 5.33MHz
FCLKB = 2.66MHz
To select divide by 7
Set to “0110”.
FCLKB = 4.57MHz
FCLKB = 2.28MHz
To select divide by 8
Set to “0111”.
FCLKB = 4.00MHz
FCLKB = 2.00MHz
To select divide by 16
Set to “1111”.
FCLKB = 2.00MHz
FCLKB = 1.00MHz
• Peripheral clock setting
The peripheral clock setting is set using the CLKP divide ratio selection bits (DIVR0.P[3:0]).
Example frequency
When FΦ = 32MHz When FΦ = 16MHz
PLL multiplier ratio
CLKP divide ratio selection bits
(P[3:0])
To select no division
Set to “0000”.
FCLKP = 32.0MHz
FCLKP = 16.0MHz
To select divide by 2
Set to “0001”.
FCLKP = 16.0MHz
FCLKP = 8.00MHz
To select divide by 3
Set to “0010”.
FCLKP = 10.6MHz
FCLKP = 5.33MHz
To select divide by 4
Set to “0011”.
FCLKP = 8.00MHz
FCLKP = 4.00MHz
To select divide by 5
Set to “0100”.
FCLKP = 6.40MHz
FCLKP = 3.20MHz
To select divide by 6
Set to “0101”.
FCLKP = 5.33MHz
FCLKP = 2.66MHz
To select divide by 7
Set to “0110”.
FCLKP = 4.57MHz
FCLKP = 2.28MHz
To select divide by 8
Set to “0111”.
FCLKP = 4.00MHz
FCLKP = 2.00MHz
Set to “1111”.
FCLKP = 2.00MHz
FCLKP = 1.00MHz
To select divide by 16
• Setting for the external bus clock
The setting for the external bus clock is set using the CLKT divide ratio selection bits (DIVR1.T[3:0]).
114
Example frequency
When FΦ = 32MHz When FΦ = 16MHz
PLL multiplier ratio
CLKT divide ratio selection bits
(T[3:0])
To select no division
Set to “0000”.
FCLKT = 32.0MHz
FCLKT = 16.0MHz
To select divide by 2
Set to “0001”.
FCLKT = 16.0MHz
FCLKT = 8.00MHz
To select divide by 3
Set to “0010”.
FCLKT = 10.6MHz
FCLKT = 5.33MHz
To select divide by 4
Set to “0011”.
FCLKT = 8.00MHz
FCLKT = 4.00MHz
To select divide by 5
Set to “0100”.
FCLKT = 6.40MHz
FCLKT = 3.20MHz
To select divide by 6
Set to “0101”.
FCLKT = 5.33MHz
FCLKT = 2.66MHz
To select divide by 7
Set to “0110”.
FCLKT = 4.57MHz
FCLKT = 2.28MHz
To select divide by 8
Set to “0111”.
FCLKT = 4.00MHz
FCLKT = 2.00MHz
To select divide by 16
Set to “1111”.
FCLKT = 2.00MHz
FCLKT = 1.00MHz
Chapter 11 Clock Control
7.Q & A
7.5 How do I halt the main clock in subclock mode?
Set using the “halt main clock oscillation in subclock mode” bit (OSCCR.OSCDS1).
Operation in subclock mode
To not halt the main clock
To halt the main clock
Halt main clock oscillation in subclock mode bit (OSCDS1)
Set to “0”.
Set to “1”.
(See “9. Cautions (Page No.118)”.)
7.6 How do I halt the subclock in main clock mode?
No procedure is available for this operation as the subclock does not halt on the MB91230.
115
Chapter 11 Clock Control
8.Sample Programs
8. Sample Programs
Setting Procedure 1
Program 1
Change operation clock for MCU (main1/2 => PLL => sub=> PLL)
void MAIN_sample1(void)
{
CLOCK _init(void)
......
SET_MAIN_PLL(void)
......
SET_SUB_CLOCK_from_MAIN(void)
......
SET_MAIN_PLL_from_sub(void)
......
}
Initialize clocks
Change clock (to main PLL)
Change clock (to subclock)
Change clock (to main PLL)
<Initialize clocks>
Set clock control register
CLKR
void CLOCK _init(void)
{
IO_CLK.IO_CLKR.byte = 0x78;
.PLL[2:0]
PLL multiplier
.PLL2EN
Enable subclock selection
.PLL1EN
Halt main clock during subclock operation
.CLKS[1:0]
Clock selection
Set I flag
(CCR)
__EI();
/* Initialize clocks.
/* User program
/* Change to main PLL
/* User program
/* Change to subclock.
/* User program
/* Change clock to main PLL.
/*
*/
*/
*/
*/
*/
*/
*/
*/
/* Initialize clocks.
*/
/* Setting=01111000
*/
/* bit 7=0
/* bit6-4=111
PLL[2:0]
/* bit3=1
PLL2EN
/* bit2=0
PLL1EN
/* bit1-0=00
CLKS[1:0]
/*Set interrupt enable (I) flag.
Reserved bit */
x8
*/
Enable subclock selection. */
Stop main PLL. */
Main clock 1per2 */
*/
}
<Set main clock (PLL x 8)>
Start PLL
Wait for main PLL to lock
CLKR.PLL1EN
<Change from main PLL to subclock>
Change clock
Change clock
Enable PLL operation
Start main clock
Change clock
CLKR.CLKS
CLKR.CLKS
CLKR.PLL1EN
OSCCR.OSDCS
CLKR.CLKS
<Change from subclock to main PLL>
Start main clock
Main clock oscillation stabilization wait
OSCCR.OSDCS
void SET_MAIN_PLL(void)
{
IO_CLK.IO_CLKR.bit.PLL1EN = 1;
TBT_initial();
TBT_start();
}
void SET_SUB_CLOCK_from_MAIN(void)
}
IO_CLK.IO_CLKR.bit.CLKS = 0;
IO_CLK.IO_CLKR.bit.CLKS = 1;
IO_CLK.IO_CLKR.bit.PLL1EN = 0;
IO_CLK.IO_OSCCR.bit.OSCDS1=1;
IO_CLK.IO_CLKR.bit.CLKS = 3;
}
void SET_MAIN_PLL_from_sub(void)
{
IO_CLK.IO_OSCCR.bit.OSCDS1=0;
MCST_initial();
MCST_start();
SET_MAIN_PLL();
Wait for PLL to lock
}
(continued on next page)
116
/* Settings for switching to main PLL.*/
/* Start PLL.
/* Wait for main PLL to lock.
/*
*/
*/
*/
/* Select 1/2 clock.
*/
/* Select 1/2 clock.
*/
/* Stop PLL.
*/
/* Halt main clock while subclock operating. */
/* Select subclock.
*/
/* Continue to operate main clock when subclock operating. */
/* Main clock oscillation stabilization wait */
/*
*/
/* Wait for PLL to lock.
*/
Chapter 11 Clock Control
8.Sample Programs
Setting procedure 1 (continued)
Program 1 (continued)
==== TBT (wait for main PLL to lock) ====
<Initialization>
1
• Settings
Control register setting
TBT interrupt level
Register name. Bit name
TBCR
ICR31
<Start TBT>
• Timebase timer
Clear TBC
Register name. Bit name
CTBR
Clear TBT interrupt request flag>>
Enable TBT interrupts>>
TBCR. TBIF
TBCR. TBIE
==== MCST (Oscillation stabilization wait for main clock) ====
<Initialize main clock stabilization timer>
1
• Settings
Register name.Bit name
Control register settings
OSCR
Interrupt level for main clock
ICR30
oscillation stabilization wait
void TBT_initial()
{
IO_CLK.IO_TBCR.byte = 0x09;
IO_ICR[31].bit.ICR =0x10;
}
TBT_start()
{
IO_CTBR = 0xA5 ;
IO_CTBR = 0x5A ;
IO_CLK.IO_TBCR.bit.TBIF = 0;
IO_CLK.IO_TBCR.bit.TBIE = 1;
}
viod MCST_initial(void)
{
IO_OSCR.byte = 0x09;
IO_ICR[30].bit. ICR =0x10;
/* Initialize TBT.
/* Set interrupt level in range 16 to 31.
*/
*/
/* Clear timebase counter.
/* Write “A5” to CTBR.
/* Write “5A” to CTBR.
/* Clear TBT flag.
/* Enable TBT interrupts.
*/
*/
*/
*/
*/
/* Settings for changing to main PLL. */
/* Initialize main clock stabilization timer */
/*
*/
/* Initialize MCST .
*/
/* Set interrupt level in the range 16 to 31. */
}
<Start main clock stabilization timer >
• Main clock stabilization timer
Clear timer
Start timer
• Enable timer interrupt
Clear timer interrupt request flag>>
Enable timer interrupt>>
Register name. Bit name
OSCR. WCL
OSCR. WEN
void MCST_start(void)
{
IO_OSCR.bit.WCL = 0 ;
IO_OSCR.bit.WEN = 1 ;
OSCR. WIF
OSCR. WIE
IO_OSCR.bit.WIF = 0;
IO_OSCR.bit.WIE = 1;
/* Start main clock stabilization timer. */
/*
/* Clear timer.
/* Start timer.
*/
*/
*/
/* Clear timer interrupt request flag.
/* Enable timer interrupt.
*/
*/
}
==== Interrupt ====
<Interrupt for waiting for main PLL lock (TBT)>
• Interrupt processing
Register name. Bit name
Change clock (1/2 main)
CLKR. CLKS
Change clock (main PLL)
CLKR. CLKS
Disable TBT interrupt>>
TBCR. TBIE
Clear TBT interrupt request flag>>
TBCR. TBIF
__interrupt void TBT_for_PLL_int()
{
IO_CLK.IO_CLKR.bit.CLKS = 0;
IO_CLK.IO_CLKR.bit.CLKS = 2;
IO_CLK.IO_TBCR.bit.TBIE = 0;
IO_CLK.IO_TBCR.bit.TBIF = 0;
/* An interrupt is generated when the interval time elapses. ★ */
/* Main clock 1per2
/* Main PLL
/* Disable TBT interrupt.
/* Clear TBT flag.
*/
*/
*/
*/
}
<Interrupt for waiting for main clock stabilization>
• Clock change processing
Register name. Bit name
Change clock (1/2 main)
CLKR. CLKS
Disable timer interrupt>>
OSCR. TBIE
Clear timer interrupt request flag>>
OSCR. TBIF
__interrupt void MCST_int()
{
IO_CLK.IO_CLKR.bit.CLKS = 1;
IO_OSCR.bit.WIE = 0;
IO_OSCR.bit.WIF = 0;
/* An interrupt is generated when the interval time elapses. ★ */
/* Main clock 1per2 from sub
/* Disable timer interrupt.
/* Clear timer interrupt request flag.
*/
*/
*/
}
==== Interrupt vector ====
<Interrupt vector>
Setting vector in vector table is required.
Setting vector in vector table is required.
Note: The clock settings and __set_il(numeric value)) must be done
beforehand. See the clock and interrupt chapters.
/* The above interrupt routine ★ needs to be set in the vector table. */
#pragma intvect MCST_int 46
#pragma intvect TBT_for_PLL_int 47
/* Refer to the "Handbook for using the FRLite Family MB91230 Series Sample
details of the register name notation. */
I/O Register Files" for
117
Chapter 11 Clock Control
9.Cautions
9. Cautions
• Operation is not guaranteed if the clock source selection, main PLL multiplier setting, and divide ratio setting result in a
frequency that exceeds the maximum.
• Take care with the sequence in which you set or modify the clock source selection.
• When the main clock oscillation is set to halt during subclock mode (OSCDS1 = “1”), selecting the main clock
(CLKS[1:0])=“00”, “01”, or “10”) is prohibited. To select the main clock, set (OSCDS1=“0”) and then change to the
main clock after waiting for the main clock oscillation to stabilize. Use the main clock oscillation stabilization wait
timer to provide the wait time. See “Chapter 15 Main Clock Oscillation Stability Wait Timer (Page No.155)” for
details.
• When the main clock oscillation is halted (OSCDS1 = “1”), an oscillation stabilization wait time (for main clock or
subclock) is also required if a reset (INIT) occurs that switches the clock source to the main clock. In this case,
operation after the reset is not guaranteed if the wait time set in the oscillation stabilization time selection bits
(STCR.OS[1:0]) does not satisfy the oscillation stabilization time requirement for the main clock.
Always set the oscillation stabilization time selection bits (STCR.OS[1:0]) to a value that provides an adequate
oscillation stabilization time for the main clock.
In the case of an INIT reset triggered by the INIT pin, the “L” level input must be maintained for long enough for the
main clock oscillation to stabilize.
See “Chapter 12 Timebase Counter (Page No.119)” and “Chapter 15 Main Clock Oscillation Stability Wait Timer
(Page No.155)” for details of the oscillation stabilization wait.
• When changing to stop mode, the main PLL must either be halted or de-selected. Either set the main clock oscillation
halt bit (STCR.OSCDS = “1”) to halt automatically or change the operating clock to main clock divided by two before
changing to stop mode.
118
Chapter 12 Timebase Counter
1.Overview
Chapter 12 Timebase Counter
1. Overview
The timebase counter is a 26-bit up-counter that counts the subclock or the main clock divided by two.
When recovering from a state in which the selected clock source for the MCU has been, or may have been, halted, the
MCU automatically changes to the oscillation stabilization wait state to avoid any unstable output from the oscillator.
During the oscillation stabilization wait time, supply of internal and external clocks is halted and only the timebase
counter continues to operate until the time set by the oscillation stabilization wait time setting has elapsed.
Time-base counter when used to
generate the oscillation stabilization wait
Watchdog timer
Time-base counter
Main clock
divided by 2
Subclock
Time-base timer
26-bit counter
φ2
State transition
control circuit
Oscillation stabilization wait control signal
The timebase counter, timebase timer, and watchdog timer are collectively called the watchdog control unit.
2. Features
2.1 Timebase Counter (when used to generate the oscillation stabilization wait)
Type
: 26-bit up-counter
Number
:1
Clock source (Φ2): Main clock divided by two, or subclock
Clear
: Cleared automatically when changing to oscillation stabilization wait state.
2.2 Events that Invoke an Oscillation Stabilization Wait
■ Events that invoke an oscillation stabilization wait using the timebase counter
● Wait time after a settings initialization: Invoked automatically (timebase counter)
• INIT Initial oscillation stabilization wait after pin input
• Watchdog reset
• If the main clock oscillation has not been halted: Oscillation stabilization wait not required
• If the main clock oscillation has halted: Oscillation stabilization wait is required
Example: If a watchdog reset occurs during subclock mode with main clock oscillation halted
● Wait time after recovering from stop mode: Invoked automatically (timebase counter)
• Stop mode cases when clock oscillation circuit is halted:
• The oscillation stabilization wait time for the intended oscillation circuit is required
• Wait time for main PLL to lock is required (if main PLL is used)
• Stop mode cases when clock oscillation circuit is not halted:
Oscillation stabilization wait is not required unless the clock oscillation (main/PLL) has been halted.
● When recovering from abnormal state with main PLL selected
Automatically goes to the oscillation stabilization wait state to allow time for the main PLL to lock.
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Chapter 12 Timebase Counter
3.Configuration
■ Events that invoke an oscillation stabilization wait using other than the timebase counter
● Wait time after power on: Provided by pin input
● Wait time after changing from subclock to main clock: Using the main oscillation stabilization wait
timer to generate this time is recommended.
● When recovering from main clock oscillation halted: Enabling the main clock oscillation and
waiting for oscillation to stabilize is required.
● Main PLL lock wait time (for main clock operation): Using the timebase timer interrupt to generate
this time is recommended.
• A wait time is required after the main PLL operation is enabled.
• A wait time is required after the main PLL multiplier setting is changed.
3. Configuration
Figure 3-1
Configuration Diagram
Time-base counter
(when used to generate the oscillation stabilization wait)
0
1
0
1
1
1
0
1
1
0
1
1
CLKR :bit 1-0
F CL-MAIN /2
φ2 x 21
φ2 x 211
φ2 x 216
φ2 x 222
F CL-SUB /2
Time-base counter
(26-bit counter)
F CL-MAIN /2
F CL-SUB
0
1
2
3
9
21
22
23
24
210
10 11 12 13
14 15 16 17 18 19 20 21 22 23 24 25
211
215 216 217 218 219 220 221 222 223 224 225 226
212
213
214
Base clock
(φ2)
- INIT pin input
- Watchdog reset
- STOP
Figure 3-2 Register List
120
ST CR:bit 3-2
Edge detection
0
0
0
Selector
CKS1-CKS0
OS1-OS0
0
Oscillation stabilization
wait control signal
Chapter 12 Timebase Counter
4.Registers
4. Registers
4.1 STCR: Standby Control Register
Controls transition to standby modes, pin states during stop mode, whether to halt the clock during stop mode, the
oscillation stabilization wait time, and software reset.
Note: See also “Chapter 10 Standby (Page No.91)” and “Chapter 14 Watchdog Timer (Page No.145)” chapters.
• STCR: Address 0481h (Access: Byte)
7
STOP
6
SLEEP
5
HIZ
4
SRST
3
OS1
2
OS0
1
0
OSCD2 OSCD1
0
0
1
1
0
0
X
1
0
0
R/W
0
0
R/W
1
X
R/W
1
1
R1,W
X
X
R/W
X
X
R/W
X
X
RX,W
1
X
R/W
bit
Initial value
(INITX pin input)
Initial value (Watchdog)
Initial value (Software reset)
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
• Bit7: Stop mode (STOP)
• Setting “1” changes to stop mode.
• Bit6: Sleep mode (SLEEP)
• Setting “1” changes to sleep mode.
• If this bit and the stop mode bit (STOP) bit are set to “1” at the same time, the device goes to stop mode.
• Bit5: High impedance mode (HIZ)
• Setting “0” specifies that pins maintain the same states they have on entering stop mode.
• Setting “1” specifies that pin outputs go to high impedance (Hi-z) during stop mode.
• Bit4: Software reset (SRST)
• Setting “0” triggers a software reset.
• Note that negative logic is used.
• Bit3-2: Oscillation stabilization time selection
OS[1:0]
00
01
10
11
The oscillation stabilization wait time after a reset (INIT) or on recovering from stop mode.
Oscillation
When using main clock
When using subclock
stabilization
(For a 4.0MHz main clock)
(For a 32.768kHz subclock)
wait time
1.00µ
61µs
Φ2 × 21
1.0ms
62.5ms
Φ2 × 211
32ms
2.0s
Φ2 × 216
2s
128s
Φ2 × 222
• Φ2: Main clock divided by two or subclock
• In the case of a reset triggered by an INIT pin input, operation defaults to “00” (Φ2 x 21, main clock).
• In the case of other resets or on recovering from stop mode, the specified clock (main or sub) and oscillation
stabilization wait time (OS[1:0]) are used.
• The count is performed by the timebase counter.
• Bit1: Reserved bit (OSCD2)
Set the same value to the OSCD2 bit as you set to OSCD1.
• bit0: Main clock oscillation halt (OSCD1)
Setting “1” specifies that the main clock oscillation halts in stop mode.
(See “9. Cautions (Page No.133)”.)
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Chapter 12 Timebase Counter
4.Registers
4.2 CLKR: Clock Source Control Register
Selects the clock source for the base clock used to run the MCU and controls the PLL.
Note: See also the “Chapter 11 Clock Control (Page No.103)”.
• CLKR: Address 0484h (Access: Byte)
7
-
6
PLLS2
5
PLLS1
4
PLLS0
3
PLL2EN
2
PLL1EN
1
CLKS1
0
CLKS0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
R/W0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit
Initial value
(INIT pin input)
Initial value
(Software reset)
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
• Bit7: Reserved bit Always write “0” to this bit. The read value is the value written.
• Bit6-4: PLL multiplier selection (PLLS[2:0])
• This bit specifies the PLL multiplier ratio (source oscillation (FCL-MAIN) x1, x2, x3, x4, x5, x6, x7, or x8)
• Bit3: Subclock selection enable (PLL2EN)
• Setting this bit to “1” enables the subclock to be selected.
• Bit2: Main PLL operation enable (PLL1EN)
• Setting this bit to “1” starts main PLL operation. Main PLL can be selected as the operating clock after the main
PLL has locked.
• Bit1-0: Clock source selection
CLKS1
0
0
1
1
CLKS0
0
1
0
1
Clock source setting
The main clock input from X0/X1 divided by 2 (initial value)
The main clock input from X0/X1 divided by 2
Main PLL
Subclock
Mode
Main clock mode
Main clock mode
Main clock mode
Subclock mode
When changing the clock mode, the value of CLKS0 cannot be modified if CLKS1 is “1”
The table below lists the cases when the CLKS1 - CLKS0 bits may or may not be modified.
Table 4-1 Cases When the CLKS1 and CLKS0 Bits May or May Not be Modified
Modify permitted
“00” -> “01” or “10”
“01” -> “11” or “00”
“10” -> “00”
“11” -> “01”
Modify not permitted
“00” -> “11”
“01” -> “10”
“10” -> “01” or “11”
“11” -> “00” or “10”
Example: To select the subclock after an INIT reset, first write “01B” and then write “11B” (subclock)
The clock source for the timebase counter during the oscillation stabilization wait time is set by the clock source selection bits.
122
CLKS1
CLKS0
0
0
1
1
0
1
0
1
Clock source for timebase
counter during oscillation stabilization wait time
Mode
The main clock input from X0/X1 divided by 2 (initial value)
Main clock mode
Subclock
Subclock mode
Chapter 12 Timebase Counter
5.Operation
5. Operation
This section describes the events that trigger an oscillation stabilization wait and the operation in each case.
5.1 INIT Pin Input
An oscillation stabilization wait is required after turning on the power. As the wait time provided by the initialized
timebase counter is too short, the INIT pin input must be held at the “L” level.
Figure 5-1 Using the Width of the Pin Input to Provide the Oscillation Stabilization Wait Time
Using the INIT pin input to trigger
a reset and provide the oscillation
stabilization wait time for the
main clock
Example power-on Vcc
(1)
(3)
Example main clock startup
Time-base
counter count
Provide a sufficient oscillation
(5)
stabilization wait time
21
Time
000h
2 1 (Bit 0 output)
INIT pin input
(4)
(5)
(7)
(2)
State transition
Undefined
Initial value of oscillation
stabilization wait time is too short
(6)
(2)
Oscillation stabilization wait reset
Settings initialization
(INIT)
(8)
Main RUN
Operation initialization (SRST)
Reset cancellation sequence
(1) Power turned on
(2) Start INIT pin input (Settings initialization reset)
(3) Main clock oscillation starting
(4) INIT pin input (to provide a sufficient time for the main clock oscillation to stabilize)
(5) INIT pin input removed. The timebase counter is initialized and starts counting.
(6) Oscillation stabilization wait time provided by timebase timer/counter (Initial value = minimum value)
(If the INIT pin input (4) is not maintained, the wait time is too short.)
(7) Operation initialization reset, reset cancellation sequence
(8) Main RUN
■ INIT Pin input when main clock running
The device goes to the operation initialization reset (RST) state automatically after the minimum oscillation stabilization
wait time elapses.
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Chapter 12 Timebase Counter
5.Operation
5.2 Watchdog Reset (The specified oscillation stabilization wait time is generated
automatically)
If a watchdog reset occurs while the main clock oscillation is halted, the oscillation stabilization wait time is generated
automatically. (See figure below.)
Figure 5-2
Watchdog Reset when Main Clock Halted (Sub RUN)
Using the time-base counter to
provide the oscillation stabilization
wait time for the main clock
(4)
Example main clock startup
Time-base
counter
count
Provide a sufficient oscillation
stabilization wait time
(6)
2 22
(4)
Time
000h
(1) 2 22 (Bit 21 output)
(6)
Watchdog
(3)
Internal reset signal
(5)
(7)
(8) (9)
(2)
Sub RUN with main clock
oscillation halted
State transition
Oscillation stabilization wait reset
Settings initialization
(INIT)
Main RUN
Operation initialization (SRST)
Reset cancellation sequence
(1) Oscillation stabilization wait time selection (Example: Main clock divided by two × 222)
(Set the interval time beforehand to provide an adequate oscillation stabilization wait time.)
(2) Sub RUN with main clock oscillation halted
(3) Watchdog reset occurs
(4) Main clock oscillation starts
The timebase counter is cleared and starts counting.
(5) Oscillation stabilization wait
(6) Time set as the timebase timer interval time (time set in (1))
(7) Reset released, operation initialization (SRST)
(8) Operation initialization, reset sequence
(9) Main RUN
Note: If a watchdog reset occurs when the main clock oscillation is halted during subclock mode (subclock is
being used as clock source) by the main clock oscillation halt bit (OSCCR.OSCDS1), the device changes
to the oscillation stabilization wait state after the settings initialization reset (INIT) is released. The device
then changes to the operation initialization reset (RST) state after the oscillation stabilization wait time
elapses.
124
Chapter 12 Timebase Counter
5.Operation
■ Watchdog reset when main clock operating
Although no oscillation stabilization wait is required in this case, the specified wait time is generated automatically.
5.3 Recovering from Stop Mode via an Interrupt
■ When changing from main PLL operation to stop mode with the main clock oscillation halted
(STCR.OSCD[2:1]=“11”):
The main oscillation circuit generates the selected oscillation stabilization time automatically.
Figure 5-3 Recovering from Stop Mode with the Main Clock Halted to
Main PLL Operation via an Interrupt
Using the time-base timer to wait
main PLL lock
(8)
(5)
Example main PLL
startup
Provide a sufficient oscillation
stabilization wait time.
(1) 13
2
(9)
Time-base
counter count
(4)
Time
000h
(CTBR)
(3)
“A5” “5A”
“
Enable main PLL (PLL1EN)
(5)
Clear the time-base counter.
Enable the time base timer
interrupt request. (PLL1EN)
(7)
Time base timer interrupt
request (PLL1EN)
(2) Setting or switching
the main PLL value
(PLL1S[2:0])
Clock switching (CLKS[1:0])
(6)
(9)
“111”
“00”
Operation of the divided- by-2 main clock
(10)
“10”
Operation of the PLL clock
(1) Enabled interrupt is generated (end stop mode)
(2) The timebase counter is cleared automatically and then starts counting.
(3) Oscillation stabilization wait time (specified value)
(Set the interval time beforehand to provide an adequate oscillation stabilization wait time.)
(4) Interval time for timebase counter
(5) Main PLL operation
125
Chapter 12 Timebase Counter
5.Operation
■ When changing to stop mode without halting the clock oscillation circuit (main PLL/main/
sub):
Although no oscillation stabilization wait is required in this case, a wait is generated automatically. Accordingly, it is
recommended that you set the interval time to its minimum value before changing to stop mode.
• When recovering from stop mode, the device goes to the oscillation stabilization wait state immediately after stop
mode is released.
• The next state after the oscillation stabilization wait completes depends on what triggered recovery from stop mode.
• If recovery was triggered by an enabled external interrupt, clock timer interrupt, or main clock oscillation
stabilization wait timer interrupt, the device goes to the normal operating state (RUN).
• Although the subclock oscillation does not halt on the MB91230, an oscillation stabilization wait for the subclock is
generated automatically anyway when recovering from sub stop mode via an interrupt.
Note: If the main PLL continues to operate in stop mode, changing to stop mode with the main PLL clock set as
the active clock is not permitted. Always set the active clock to the main clock divided by two or the
subclock beforehand.)
5.4 The lock wait time for the main PLL must be generated by software.
■ Wait time after main PLL operation enabled:
Using the timebase timer interrupt is recommended
However, the main PLL must not be selected as the clock source.
■ Wait time after main PLL multiplier modified:
Using the timebase timer interrupt is recommended
However, the main PLL must not be selected as the clock source.
See “5. Operation (Page No.139)” for details.
5.5 Generating an Oscillation Stabilization Wait when Changing from Subclock Mode to
Main Clock Mode
■ When main clock continues to run during subclock mode:
• If not using main PLL after changing clock: No oscillation stabilization wait time
• If using main PLL after changing clock: Main PLL lock wait is required.
(Using the timebase timer interrupt is recommended. See “5.3 Recovering from Stop Mode via an Interrupt (Page
No.125)”.)
■ When main clock halts during subclock mode:
• A main clock oscillation stabilization wait is required before changing clock.
(Use the oscillation stabilization wait timer for the main clock. See “Chapter 15 Main Clock Oscillation Stability Wait
Timer (Page No.155)”.)
• When using the main PLL: A further wait is required for the main PLL to lock.
(Using the timebase timer interrupt is recommended. See “5.3 Recovering from Stop Mode via an Interrupt (Page
No.125)”.)
5.6 When Recovering from an Abnormal State with the Main PLL Selected
When the main PLL is set as the clock source and a problem of some sort occurs in main PLL control (such as the
multiplier setting being changed or the main PLL enable bit modified during main PLL operation), the device goes to the
oscillation stabilization wait state automatically to provide the main PLL lock time. The device then goes to normal
operating mode after the oscillation stabilization wait elapses.
126
Chapter 12 Timebase Counter
5.Operation
5.7 Types of Oscillation Stabilization Wait
■ Timebase counter
Automatically provides a count for the oscillation stabilization wait time.
When a trigger occurs to change the device to the oscillation stabilization wait state, the timebase counter is cleared and
then starts counting the specified oscillation stabilization wait time.
■ “L” level input to INIT pin
When device operation is restarted by inputting an “L” level to the INIT pin while the oscillation is halted (the three cases
listed below), the width of the “L” level input provides the stabilization time required by the oscillation circuit.
• INIT pin input after power turned on.
• INIT pin input when oscillation halted during stop mode
• INIT pin input when subclock selected as clock source and main clock oscillation halted.
■ Timebase timer
Using the timebase timer to generate the main PLL lock time is recommended.
See “Chapter 14 Watchdog Timer (Page No.145)” for details.
■ Main oscillation stabilization wait timer
Used when restarting the main clock while operating in subclock mode.
See “Chapter 15 Main Clock Oscillation Stability Wait Timer (Page No.155)” for details.
■ Clock timer
Used when restarting the subclock while operating in main clock mode.
See “Chapter 16 Clock Timer (Page No.167)” for details.
(Not applicable on the MB91230 as the subclock does not halt.)
127
Chapter 12 Timebase Counter
5.Operation
5.8 Whether or not a Stabilization Wait is Required for Each State Transition
See figure below.
128
Chapter 12 Timebase Counter
6.Settings
6. Settings
Table 6-1 Settings Required to Specify the Oscillation Stabilization Wait Time
Setting
Setting register
Oscillation stabilization wait time setting
Standby control register (STCR)
Setting
procedure*
See 7.1.
*: For the setting procedure, refer to the section indicated by the number.
Table 6-2 Settings Required to Setup an INITX Pin Reset
Setting
INITX pin input
Setting item
Refer to the oscillator parameters and the reset
parameters in the Data Sheet.
Setting procedure
–
• Settings required to specify the oscillation stabilization wait time for the main clock
See “Chapter 15 Main Clock Oscillation Stability Wait Timer (Page No.155)”.
• Settings required to specify the PLL lock wait time
See “Chapter 13 Timebase Timer (Page No.135)”.
129
Chapter 12 Timebase Counter
7.Q&A
7. Q&A
7.1 How do I setup the oscillation stabilization wait time that is generated automatically?
Use the oscillation stabilization wait time selection bits (STCR.OS[1:0]). (The following lists likely scenarios and the
required settings.)
Scenario
Oscillation
stabilization wait
time selection bits
(OS[1:0])
To not halt the main PLL or oscillator during stop mode
(No oscillation stabilization wait time required)
To not stop the oscillator during external clock input or
stop mode
(Main PLL lock wait time)
When using an oscillator with a fast stabilization time
such as a ceramic resonator
(Oscillation stabilization wait time (medium))
When using a standard quartz oscillator
(Oscillation stabilization wait time (long))
Example oscillation stabilization wait time
after a reset (INIT) or on
recovering from stop mode
Oscillation
4.0MHz
32.768kHz
stabilizaMain clock
Subclock
tion
running
running
wait time
Set “00”.
Φ2 × 21
1.00µ
61µs
Set “01”.
Φ2 × 211
1.0ms
62.5ms
Set to “10”.
Φ2 × 216
32ms
2.0s
Set to “11”.
Φ2 × 222
2s
128s
• Φ2: Main clock divided by 2, or subclock
• In the case of an INIT pin input, operation defaults to “00” (Φ2 × 21=main clock divided by 4).
• For other resets and when recovering from stop mode, the operation is in accordance with the specified clock (main
or sub) and oscillation stabilization wait time (OS[1:0]) setting.
• The count is performed by the timebase counter.
• Once the time is selected, it is not initialized except by a settings initialization triggered by the external INIT pin.
130
Chapter 12 Timebase Counter
7.Q&A
7.2 How do I set the oscillation stabilization wait time without generating it
automatically?
The settings described below for various cases are required.
State (before
transition)
Wait time after power on
Subclock operation
(main clock halted)
Sub sleep, sub stop
(main clock halted)
Main clock oscillation
stabilization wait
State (before
transition)
Subclock operation
(main clock halted)
Oscillation
PLL
Main
Sub
×
×
×
×
×
O
×
×
O
×
×
O/×
Oscillation
PLL
×
Main
×
Sub
O
Oscillation
State (before
transition)
PLL
Main
Sub
Subclock running (main
clock running)
×
O
O
Main clock (1/2) running
×
O
O
Is oscillation
stabilization wait
required?
Condition (after
transition)
Operation after INIT
signal input defaults to
main clock (1/2)
(Initial value)
Main clock
oscillation enabled
Main clock running
Main clock
oscillation
stabilization wait
is required
Is oscillation
stabilization wait
required?
Main clock
oscillation
stabilization wait
is required
Is oscillation
stabilization wait
required?
Main PLL running
and enabled
Start main PLL
oscillation/
Change PLL
multiplier setting
Main PLL lock
wait required
To set the oscillation
stabilization wait time
As the automatic oscillation
stabilization wait (minimum
value) is too short, the width of
the INIT pin must be sufficient
to provide the stabilization time.
To set the oscillation
stabilization wait time
Using the main clock oscillation
stabilization wait timer to
generate the time is
recommended.
To set the oscillation
stabilization wait time
Using the timebase timer to
generate the main PLL lock wait
time is recommended.
O: Oscillation running,
×: Oscillation halted
7.3 What is the clear timing for the timebase counter?
• The timebase counter is only cleared automatically by INIT pin input.
The timebase counter automatically starts counting after being cleared.
• The timebase counter can also be cleared by software.
See “Chapter 13 Timebase Timer (Page No.135)” for details.
131
Chapter 12 Timebase Counter
8.Sample Program
8. Sample Program
Setting procedure 1
Program 1
Oscillation stabilization wait time setting
void CLOCK_STABILIZATION_sample()
Initialization (TBC_initial)
{
TBC_initial();
}
<Initialize>
TBC_initial()
• Settings
Register name.Bit
name
Standby control register settings
STCR
Oscillation stabilization wait time>>
{
IO_CLK.IO_TBCR.byte =
0x09;
. OS[1:0]
/* Setting = 0011_1000
*/
/* bit7=0
STOP
Stop */
/* bit6=0
SLEEP
Sleep */
/* bit5=1
HIZ
High impedance */
/* bit4=1
SRST
Software reset */
/* bit3-2=10
OS[1:0]
Oscillation stabilization wait time */
/* bit1-0=00
OSCD[2:1] Halt oscillation */
}
Note: The clock settings and __set_il(numeric value) must be done
beforehand. See the clock and interrupt chapters.
132
/* Refer to the “FRLite Family MB91230 Series Sample I/O Register Files Usage Guide” for details of the
register name notation. */
Chapter 12 Timebase Counter
9.Cautions
9. Cautions
• Clock source
If the clock selected as the clock source is not stable, an oscillation stabilization wait time is required.
• Watchdog reset
Although an oscillation stabilization wait time is not required if a watchdog reset occurs while the main clock is
running (main or sub), a wait time is generated automatically. In this case, the oscillation stabilization wait time
(STCR.OS[1:0]) is not initialized.
• Oscillation stabilization wait time
The wait time set in the oscillation stabilization time selection bits (STCR.OS[1:0]) is not initialized by any reset other
than a reset triggered by an external pin input. For other resets including settings initialization resets (watchdog resets)
and operation initialization resets (RST), the wait time set prior to the reset is used.
• “L” level input to INIT pin
As the oscillation stabilization wait time is initialized to its minimum value when an initialization is triggered by an
INIT pin input, the wait time in this case is too short. Ensure the INIT pin input width is long enough to provide the
oscillation stabilization wait time.
In the following three cases, maintain the INIT pin input at the “L” level for long enough to provide the oscillation
stabilization wait time required by the oscillation circuit.
• INIT pin input after turning on the power
• INIT pin input after oscillation halted in stop mode
• INIT pin input when subclock selected as the clock source and main clock oscillation halted
(Accordingly, to stabilize the oscillation of both the main and subclocks, input an “L” level to the INIT pin for long
enough to provide a sufficient oscillation stabilization time for both the main and subclocks.)
• Main PLL lock wait
If enabling the main PLL from the halted state after program execution starts, the main PLL must not be used until after
sufficient time has elapsed for the main PLL to lock.
Similarly, when changing the multiplier setting for the main PLL when the PLL is running, the new main PLL clock
must not be used until after sufficient time has elapsed for the main PLL to lock.
Using the timebase timer interrupt to generate the main PLL lock wait time is recommended.
• Cases when oscillation stabilization wait is not required
Although no oscillation stabilization wait is required when recovering via an interrupt from main stop or sub stop mode
when the main clock oscillation has not been halted, the oscillation stabilization wait is generated automatically. Setting
the wait time to its minimum value prior to entering stop mode is recommended.
133
Chapter 12 Timebase Counter
9.Cautions
134
Chapter 13 Timebase Timer
1.Overview
Chapter 13 Timebase Timer
1. Overview
The timebase timer is a selector that uses the output from a 26-bit timebase counter using the base clock (Φ).
The timebase timer is an interval-interrupt generating timer that is used to acquire main PLL lock wait time and to count a
long time.
Watchdog control section
Timebase
counter
Base
clock
(φ)
Watchdog timer
26-bit counter
Timebase timer
Selector
Timebase timer interrupt
2. Features
■ Timebase timer (TBT)
• Type
: Detects timebase timer bit output and generates an interval interrupt.
• Quantity
:1
• Interval time : 8 types (Timebase timer bit output)
Period = 211/FΦ, 212/FΦ, 213/FΦ, 222/FΦ, 223/FΦ, 224/FΦ,
225/FΦ, 226/FΦ
• Operation start/stop: Always in operation (Can be replaced by interrupt request enable control)
• Timebase counter clear: Continuously writes “A5”“5A” in the timebase counter clear register CTBR using the
software.
135
Chapter 13 Timebase Timer
3.Configuration
3. Configuration
Figure 3-1 Configuration
Timebase timer
Timebase timer
Interval time
TBC2-TBC0
0 0 0
1 0 1
0 1 0
1 1 1
1 0 0
1 0 1
1 1 0
1 1 1
TBCR:bit 5 -3
φ x 2 11
φ x 2 12
φ x 2 13
φ x 2 22
φ x 2 23
φ x 2 24
φ x 2 25
φ x 2 26
TBIE
0
1
TBCR:bit 6
Interrupt disable
Interrupt enable
0
Selector
Edge detection
TBIF
0
1
With interrupt request
WRITE; 0: Flag clear
Timebase counter
(26-bit counter)
0
3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
21 22 23 24
1
2
2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 2 25 2 26
Base clock
(φ)
Timer clear
CTBR
Clears the counter
after writing "A5h"
and then "5Ah."
Figure 3-2 List of Registers
136
TBCR:bit 7
Without interrupt request
Timebase
1
Timer interrupt
(#46)
Chapter 13 Timebase Timer
4.Register
4. Register
4.1 TBCR: Timebase Timer Control Register
This register is used to set timebase timer interrupt control, reset/ standby operation option etc.
Note: Refer also to “Chapter 10 Standby (Page No.91)”.
• TBCR: Address 0482h (Access: Byte)
7
TBIF
6
TBIE
5
TBC2
4
TBC1
3
TBC0
2
---
1
SYNCR
0
SYNCS
0
0
X
X
X
X
0
0
0
0
X
X
X
X
X
X
R(RM1),W
R/W
R/W
R1,W
R/W
RX/WX
RX/WX
R/W
bit
Initial value
(INIT terminal input,
watchdog reset)
Initial value
(the software reset)
Attribute
(Refer to “■Meaning of Bit Attribute Symbols (Page No.10)” for the attributes.)
• Bit7: Timebase timer interrupt request flag
Operation
TBIF
Read
With no interrupt request
Write
Flag is cleared
With interrupt request
(The interval time set by the timebase timer
has elapsed)
Writing does not affect operation
0
1
• An interrupt request is generated if the timebase timer interrupt request enable bit is “1”, and if the timebase timer
interrupt request flag is “1”.
• Bit6: Timebase timer interrupt request enable
TBIE
0
1
Operation
Disabling the timebase timer interrupt request
Enabling the timebase timer interrupt request
• Bit5-3: Selecting the timebase timer interval time
Example
While the main clock operates While the subclock operates
(4.0MHz, PLL8 multiply)
(32.768kHz)
TBC2-TBC0
Interval time
000
Φ × 211
64.0µs
62.5ms
001
Φ×2
12
128µs
125ms
Φ×2
13
256µs
250ms
011
Φ×
222
131ms
128s
100
Φ × 223
262ms
256s
101
Φ × 224
524ms
512s
110
Φ×2
25
1048ms
1024s
Φ×2
26
2097ms
2048s
010
111
• Be sure to set the interval time before an interrupt.
(Oscillation stability wait time used when returning to the stop caused by an interrupt)
• Bit2: Reserved bit
Writing does not affect the operation. The read value is indefinite.
137
Chapter 13 Timebase Timer
4.Register
• Bit1: Enabling the synchronous reset operation
SYNCR
0
1
Operation
Ordinary reset operation
Synchronous reset operation enable
• Ordinary operation reset: Immediately resets the operation initialization when the operation initialization reset
(RST) request is generated.
Synchronous reset: Resets the operation initialization after all accesses to the bus have stopped.
• Bit0: Synchronous standby operation enable
SYNCS
0
1
Operation
Ordinary reset operation (In this product, any setting is prohibited)
Synchronous standby operation enable (Be sure to set before making the transition to standby)
4.2 CTBR: Timebase Counter Clear Register
This register is used to initialize the timebase counter.
• CTBR: Address 0483h (Access: Byte)
7
D7
X
RX/W
6
D6
X
RX/W
5
D5
X
RX/W
4
D4
X
RX/W
3
D3
X
RX/W
2
D2
X
RX/W
1
D1
X
RX/W
0
D0
X
RX/W
bit
Initial value
Attribute
(Refer to “■Meaning of Bit Attribute Symbols (Page No.10)” for the attributes)
• Continuously writing “A5H”, “5AH” in the timebase counter clear register clears the timebase counter immediately after
writing “5AH”. (All bits are “0”)
There is no time restrictions between “5AH” and “5AH”, but if “A5H” is written followed by the one other than “5AH”,
you should write “A5H” again. If not, the timebase counter cannot be cleared even if “5AH” is written.
• The read value is indefinite.
• Clearing the timebase counter using the timebase counter clear register temporarily modifies the relevant items shown
below.
• Oscillation stability wait interval
• Watchdog timer period
• Timebase timer period
138
Chapter 13 Timebase Timer
5.Operation
5. Operation
Timebase timer operation is described.
5.1 Timebase Timer Interrupt Example (Main PLL Lock Wait)
Main PLL lock wait
by the timebase timer
(8)
(5)
Example of
the Main PLL
oscillation
600 µsec. or more
(1)
(1)
2 11
Timebase
counter
count
(4)
Time
000h
(3)
““A5”
A5” “5A”
”
Clears the
(CTBR)
timebase counter
Main PLL enable (PLL1EN)
(5)
Timebase timer interrupt
request enable (PLL1EN)
(7)
Timebase timer interrupt
request (PLL1EN)
((2) Main PLL value
(6)
(9)
“111”
“111 ”
setting/switching
(PLL1S[2:0])
Clock switching (CLKS[1:0]) “00”
“00 ”
Operation with the 2-dividing main clock
(10)
“10”
“10 ”
Operation with the PLL clock
(1) Selecting the interval value in the timebase timer
(2) Selecting the main PLL value (Setting/ Switching)
(3) Writing data in the timebase counter clear register in the order of “A5” and “5A”
(4) Writing “5A” clears the timebase counter and causes the count to start from”0”
(5) Enables the main PLL to operate
(6) Clears the timebase timer interrupt request using the software
(7) Setting the timebase timer interrupt request enable bit to “1”
(8) The main PLL locks
(9) A timebase timer interrupt occurs when the timebase timer interval time has elapsed
(10) Setting the main PLL to the operation clock
139
Chapter 13 Timebase Timer
6.Setting
6. Setting
Table 6-1 Setting Required for the Timebase Timer
Setting
Setting register
Timebase timer control register
control register (TBCR)
Timebase counter clear register
(CTBR)
Setting the interval time
Timebase counter clear
Setting
method*
Refer to 7.1
Refer to 7.5
*: Refer to the number for more information on the setting method.
Table 6-2 Setting Required for Interrupting the Timebase Timer
Setting
Setting the timebase timer interrupt vector and
interrupt level
Setting the main clock oscillation stability wait timer interrupt
Interrupt request clear
Interrupt request enable
Setting register
Refer to “Chapter 20 Interrupt
Control (Page No.207)”
Refer to 7.6
Timebase timer control register
control register (TBCR)
Refer to 7.7
*: Refer to the number for more information on the setting method.
140
Setting
method*
Chapter 13 Timebase Timer
7.Q & A
7. Q & A
7.1 What are the types of interval time used in the timebase timer (and the timebase
counter used by the timebase timer) and how to select them?
There are eight types of interval time, and they are set using the interval selection bit (TBCR.TBC[2:0]).
Example) Interval time
Timebase timer
Interval time
Interval selection bit
(TBC[2:0])
FΦ =2MHz
FΦ = 32MHz
FΦ =
32.768kHz
How to select Φ × 211 ?
Set the value to “000”
1.024ms
64µs
62.5s
How to select Φ × 212 ?
Set the value to “001”
2.048ms
128µs
125s
How to select Φ × 213 ?
Set the value to “010”
4.096ms
256µs
256s
How to select Φ × 222 ?
Set the value to “011”
2.097s
131ms
35.5hour
How to select Φ × 223 ?
Set the value to “100”
4.194s
262ms
71.1hour
How to select Φ × 224 ?
Set the value to “101”
8.388s
514ms
5.9day
25 ?
How to select Φ × 2
Set the value to “110”
16.77s
1.04s
11.8day
How to select Φ × 226 ?
Set the value to “111”
33.55s
2.09s
23.7day
Φ: This is the base clock. (Refer to “Chapter 11 Clock Control (Page No.103)”.)
7.2 What Is the count clock of the timebase counter?
The count clock is a base clock.
Refer to “Chapter 11 Clock Control (Page No.103)”.
7.3 How to operate the timebase timer?
The timebase timer is always operating. (Setting is unnecessary.)
However, to use interval interrupt, interrupt setting is required.
7.4 How is the timebase timer (=timebase counter) operation stopped?
It cannot be stopped.
7.5 How is the timebase counter (=timebase timer) cleared?
If you write {A5H} and {5AH} successively in the timebase counter clear register CTBR, the timebase counter is cleared
immediately after {5AH}. (All bits are “0”.)
However, if the timebase counter is cleared, the watchdog timer is affected. (Refer to “9. Caution (Page No.144)”)
7.6 How about the interrupt-associated registers?
Setting timebase timer’s interrupt vector and interrupt level
The relationship between the interrupt level and vector is shown in the following table.
Refer to “Chapter 20 Interrupt Control (Page No.207)” for more information on the interrupt level and interrupt vector.
Interrupt vector (default)
#47
Address: 0FFF40h
Interrupt level setting bit (ICR[4:0])
Interrupt level register (ICR31)
Address: 0045Fh
The interrupt request flag (TBCR.TBIF) cannot automatically be cleared. As a result, clear it by the software before
returning from an interrupt service. (Write “0” in the interrupt request flag (TBIF).)
141
Chapter 13 Timebase Timer
7.Q & A
7.7 What are the interrupt types?
One type of interrupt is available, and an interrupt is generated when the interval time that is set using the interval
selection bit (TBCR.TBC[2:0]) has elapsed. (Selection is unnecessary.)
7.8 How is an interrupt enabled?
Interrupt request enable and interrupt request flag
Setting interrupt enable is conducted using the interrupt request enable bit (TBCR.TBIE).
Interrupt disable
Interrupt enable
Interrupt request enable bit (TBIE)
Set the value to “0”
Set the value to “1”
Clearing the interrupt request is performed using the interrupt request bit (TBCR.TBIF).
Interrupt request clear
142
Interrupt request bit (TBIF)
“0” is written
Chapter 13 Timebase Timer
8.Sample Program
8. Sample Program
Setting procedure 1
Main PLL lock wait
Program 1
void MAIN_PLL_LOCK_WAIT_sample()
{
TBT_initial();
TBT_start();
Initial setting (TBT_initial)
Startup (TBT_start)
}
Interrupt
<Initial setting>
1
• Setting
control register setting
TBT interrupt request flag clear>>
TBT interrupt disable>>
TBT interval time>>
Reserved bit
Ordinary reset>>
synchronous standby>>
2
• Interrupt-associated
TBT interrupt level
I flag setting
Register name .Bit name
TBCR
. TBIF
TBIE
. TBC
.
. SYNCR
. SYNCS
TBT_initial()
{
IO_CLK.IO_TBCR.byte = 0x09;
ICR31
(CCR)
IO_ICR[31].bit.ICR =0x10;
__EI();
/* Setting value = 0000_1001 */
/* bit7=0
TBIF
/* bit6=0
TBIE
/* bit5-3=001
TBC
/* bit2=0
-/* bit1=0
SYNCR
/* bit0=1
SYNCS
TBT interrupt request flag clear */
TBT interrupt disable */
TBT interval time */
Reserved bit */
Ordinary reset */
synchronous standby */
/* Set the interrupt level in a range of 16 to 31*/
/* interrupt enable*/
}
<TBT startup>
• Timebase timer
TBC clear
• TBT interrupt enable
TBT interrupt request flag clear>>
TBT interrupt enable>>
Register name .Bit name
CTBR
TBT_start()
{
IO_CTBR = 0xA5 ;
IO_CTBR = 0x5A ;
TBCR. TBIF
TBCR. TBIE
IO_CLK.IO_TBCR.bit.TBIF = 0;
IO_CLK.IO_TBCR.bit.TBIE = 1;
/* Timebase counter clear */
/* Writing “A5” in CTBR */
/* Write “5A” in CTBR */
/* bit7=0
/* bit6=0
TBIF
TBIE
TBT interrupt request flag clear */
TBT interrupt enable */
}
<main PLL lock wait (TBT) interrupt>
• Clock switching service
Clock switching (1/2 main)
Clock switching (main PLL)
TBT interrupt disable>>
TBT interrupt request flag clear>>
CLKR. CLKS
CLKR. CLKS
TBCR. TBIE
TBCR. TBIF
__interrupt void TBT_for_PLL_int()
{
IO_CLK.IO_CLKR.bit.CLKS = 0;
IO_CLK.IO_CLKR.bit.CLKS = 2;
IO_CLK.IO_TBCR.bit.TBIE= 0;
IO_CLK.IO_TBCR.bit.TBIF= 0;
}
/* An interrupt is generated when the interval time has elapsed */
/* bit6=0
/* bit7=0
CLKS
CLKS
TBIE
TBIF
Main clock /2
Main PLL
TBT interrupt disable */
TBT flag clear */
<Interrupt vector>
Vector table setting
/*The interrupt routine needs to be specified using the vector table */
#pragma intvect TBT_for_PLL_int 47
Notice: Set the clock and __set_il(Numeric value) in advance. Refer to the
chapters on the clock and interrupt.
/* For the description type of registers, refer to “FRLite Family MB91230 Series Sample I/O Register File Usage
Guide”. */
143
Chapter 13 Timebase Timer
9.Caution
9. Caution
• The main PLL needs the PLL lock wait time after operation enable and after modifying the rate of multiply.
We recommend that this main PLL lock wait time be acquired using the timebase interrupt.
The lockup time of PLL is approximately 600µs. Make sure that the PLL lock wait time is set to a value a little larger
than 600µs.
• Regarding the interval setting
• When modifying the timebase timer interval time, set the interrupt request enable bit (TBIE) to “0” in advance to
disable an interrupt.
• The timebase counter is always counting. Clear the timebase counter before enabling an interrupt to acquire an
accurate interval interrupt time using the timebase timer.
(If not, an interrupt request may be generated immediately after an interrupt enable.)
• About clearing the timebase counter using a program
• If you write data in the timebase counter clear register CTBR in the order of “A5H” and “5AH” the timebase counter
is cleared immediately after writing “5AH”. (All bits are “0.”)
• Although there are no restrictions on the write timings for “A5H” and “5AH” writing “A5H” followed by a one other
than “5AH” the clearing operation is not performed if “A5H” is not written again even if “5AH” is written.
• If the timebase counter is cleared, the reset signal to the watchdog is generated with a delay once.
• About clearing the timebase counter by the hardware
The timebase counter is cleared by the stop and the setting initialization reset (INIT pin input, watchdog reset). (All bits
are “0.”)
• In the stop mode
When returning to the interrupt from a stop, the timebase counter is used to acquire the clock oscillation stability wait
time. As a result, there is a possibility to unintentionally generate timebase timer’s interval interrupt. Therefore, disable
the timebase timer interrupt not to use the timebase timer before the stop is set.
144
Chapter 14 Watchdog Timer
1.Overview
Chapter 14 Watchdog Timer
1. Overview
The watchdog timer consists of a selector that uses the output from a 26-bit timebase counter using the base clock (Φ)
and a one-bit counter.
The watchdog timer generates the watchdog reset (initial setting reset) if the generation delay operation (an interval
watchdog reset) is disabled due to problems such as program runaway.
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Timebase
timer
2. Features
■ Watchdog timer
• Type
: Generates the watchdog reset (INIT) with the overflow from one-bit counter
• Quantity : 1
• Count clock (interval time): Bit output from the timebase timer
4 types
216/FΦ, 218/FΦ, 220/FΦ, 222/FΦ
(Can be set only once after the reset (RST).)
• Clearing 1-bit counter:
Successively writes “A5”“5A” to watchdog reset generation delay register WPR by the software.
• Operation start/stop: This timer starts to operate once it writes data to the watchdog control register RSRR for the first
time after the reset (RST). This timer stops only by the reset (RST).
145
Chapter 14 Watchdog Timer
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Timebase counter
(26-bit counter)
Base clock
(φ)
0
1
2
3
21 22 23 24
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226
Watchdog timer
WT1-WT0
0 0
0 1
1 0
1 1
RSRR:bit2-1
φ x 216
φ x 218
φ x 220
φ x 222
Edge detection
Selector
Clears the counter
after writing “A5h”
and then “5Ah”.
Temporary stop
For watchdog detection
Timer clear
CT BR
-Sleep
-Stop
-Oscillation stability
wait RUN
WIF
1-bit
counter
WPR
Clears the counter
after writing “A5h”
and then “5Ah”.
Figure 3-2 List of Registers
146
0
1
Watchdog reset
OSCR:bit 7
Without interrupt request
With interrupt request
WRITE; 0: Flag clear
To the reset
circuit
Chapter 14 Watchdog Timer
4.Register
4. Register
4.1 RSRR: Watchdog Timer Control Register
This register is used to set watchdog timer periods, and execute the startup control.
(This register also functions as the reset cause register that stores previously generated reset causes.)
Note: Refer also to “Chapter 9 Reset (Page No.77)”.
• RSRR: Address 0480h (Access: Byte, Half-word)
7
INIT
6
--
5
WDOG
4
--
3
SRST
2
--
1
WT1
0
WT0
1
X
0
X
0
X
0
0
X
R/WX
X
X
RX/WX
X
R/WX
X
X
RX/WX
X
R/WX
X
X
RX/WX
0
0
R/W
0
0
R/W
bit
Initial value
(INIT pin input)
Initial value (Watchdog reset)
Initial value (Software reset)
Attribute
(For the attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
The watchdog timer starts once it writes the watchdog timer control register.
• bit7: Initialization reset cause flag (INIT)
• The value is set to “1” if the reset occurs at the input to the INIT pin.
• Bit6: Reserved bit The read value is indefinite.
• Bit5: Watchdog reset cause flag (WDOG)
• The value is set to “1” if the watchdog timer is reset.
WDOG
0
1
Meaning
The reset (INIT) by the watchdog timer has not been generated.
The reset (INIT) by the watchdog timer has been generated.
• Bit4: Reserved bit Writing data in this bit does not affect the operation. The read value is indefinite.
• Bit3: Software reset cause flag (SRST)
• Writing the software reset bit (STCR.SRST) generates the reset bit enable “1”.
• Bit2: Reserved bit The read value is indefinite.
• Bit1-0: Watchdog interval time selection
WT1
WT0
The minimum writing interval required for WPR
so that the watchdog timer may not be reset
Interval between the time when WPR is last
written with 5AH and when the watchdog is
reset
(Interval time of the timebase counter
selection bit)
(Watchdog interval time)
0
0
Φ × 216 (Initial value)
Φ × 216 to Φ × 217
0
1
Φ × 218
Φ × 218 to Φ × 219
1
0
Φ × 220
Φ × 220 to Φ × 221
1
222
Φ × 222 to Φ × 223
1
Φ×
(Φ: Base clock)
• A total of four watchdog interval times are available to be selected.
• Only the data firstly written after a reset is valid, and the other data sets are invalid.
• Watchdog interval time selection bit can be read to know the set value.
Note: For more information on bits used for timers other than the watchdog timer, refer to “Chapter 9 Reset
(Page No.77)”.
147
Chapter 14 Watchdog Timer
4.Register
4.2 WPR: Watchdog Reset Generation Postponement Register
This register is used to postpone the generation of watchdog reset.
• WPR: Address 0485h (Access: Byte)
7
D7
X
X
RX,W
6
D6
X
X
RX,W
5
D5
X
X
RX,W
4
D4
X
X
RX,W
3
D3
X
X
RX,W
2
D2
X
X
RX,W
1
D1
X
X
RX,W
0
D0
X
X
RX,W
bit
Initial value (INIT)
Initial value (RST)
Attribute
(Refer to “■Meaning of Bit Attribute Symbols (Page No.10)” for the attributes.)
• If “A5H” and “5AH” are successively written in the watchdog reset generation postponement register and
immediately after writing “5AH” the 1-bit counter used to detect the watchdog is set to “0” to postpone the
generation of a watchdog reset.
Although there are no restrictions on the write timings for “A5H” and “5AH”, if “A5H” and a value other than
“5AH” are written, “A5H” must be written again. If not, writing “5AH” does not set the 1-bit counter to “0”.
• The read value is indefinite.
• Both “A5H” and “5AH” must be written within the specified interval as shown below to prevent the watchdog reset
from being generated. The intervals are shown in the following table according to the watchdog interval time
selection bit (RSRR.WT[1:0]).
WT1
WT0
Minimum interval required for writing data in WPR
0
0
Within Φ × 216 (Initial value)
0
1
Within Φ × 218
1
0
Within Φ × 220
1
1
Within Φ × 222
4.3 CTBR: Timebase Counter Clear Register
This register is used to initialize the timebase counter.
• CTBR: Address 0483h (Access: Byte)
For more information, refer to “Chapter 13 Timebase Timer (Page No.135)”.
148
Chapter 14 Watchdog Timer
5.Operation
5. Operation
This section describes the watchdog operation.
5.1 Watchdog (Detecting Runaway)
Count value of
the timer counter
(11)
(8)
(1)
Interval period
selection
(6)
(3)
(3)
(8)
(6)
Bit output of
the timer counter
(Bits 15, 17, 19 and 21)
Watchdog timer
Reading from the RSRR
register
Periodically writing
“A5” and “5A” in the
WPR register
Watchdog
startup
(12) Runaway
(3) (4)
(7) (8)
(5) (6)
detection
(2)
(4)
(5)
Clear by
software
Clear by
software
WDOG bit
(7)
Clear by
software
(10)
With
no clear
Setting initialization reset
(INIT)
(13)
Normal operation
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(12)
(9) Runaway
Reset
Setting interval time
Watchdog startup (Watchdog timer clear)
Interval signal output from the timebase counter. The watchdog timer counts.
Within the interval time, by software periodic writing to the WPR register with “A5” and “5A” has been performed. The
watchdog timer clears.
Within the interval time, by software periodic writing to the WPR register with “A5” and “5A” has been performed. The
watchdog timer clears.
Interval signal output from the timebase counter. The watchdog timer counts.
Within the interval time, by software periodic writing to the WPR register with “A5” and “5A” has been performed.
Watchdog timer clears.
Interval signal output from the timebase counter. The watchdog timer counts.
MCU runs away (the runaway of MCU is assumed).
Within interval time, by software writing to the WPR register with “A5” and “5A” has not been performed.
Interval signal output from the timebase counter. The watchdog timer counts.
Runaway is detected, WODOG flag has been changed to “1”.
Watchdog reset (INIT) has been generated.
149
Chapter 14 Watchdog Timer
5.Operation
5.2 Starting the Watchdog Timer and Setting the Watchdog Timer Period
The watchdog timer starts once it first writes data to the RSRR (Reset cause register/Watchdog timer control register)
after the reset (RST). At this time, Bits 9 and 8 (WT1 and WT0 bits) set the watchdog timer interval time. Only the
setting for the interval time executed first after the reset is valid, and the other settings executed at a later time are invalid.
5.3 Postponing the Generation of a Watchdog Reset
Once watchdog timer is started, it is necessary that the WPR (watchdog reset generation postponement register) should be
written periodically with {A5H} and {5AH} in this order by software. This operation is used to set the 1-bit counter for
detecting the watchdog reset to “0”.
5.4 Confirming that the Watchdog Reset has been Generated
The 1-bit counter for detecting the watchdog reset is set at the falling edge of the output of the timebase counter where an
interval is set. In addition, if the second falling edge is detected while the 1-bit counter is set, the request for the setting
initialization reset (INIT) is generated as the watchdog reset.
5.5 Temporarily Stopped Watchdog Timer (Automatic Generation Postponement)
The watchdog timer resets the 1-bit counter used for detecting the watchdog reset to “0” as initialization while CPU
program operation is stopped. In this state, the generation of the watchdog reset is postponed. The states where programs
stop running are concretely shown below.
• Sleep
• Stop
• Oscillation stability wait RUN
• DMA is transferred for D-bus (data bus)
• Is in break when using the emulator debugger and monitor debugger
• Period between the time when executing the INTE command and when executing RETI
• Step trace trap (break per each command with PS register T flag=“1”)
In addition, clearing the timebase counter simultaneously initializes the 1-bit counter used for detecting the watchdog
reset, thus causing the reset timing of the watchdog to be postponed.
5.6 Stopping the Watchdog Timer
Once the watchdog timer is started, the watchdog timer operation cannot be stopped until the initialization reset (RST) is
generated.
The watchdog timer is stopped under these states shown below where the operation initialization reset (RST) is generated
until it is restarted by software.
• Operation initialization reset (RST)
• Setting initialization reset (INIT)
• Oscillation stability wait reset
150
Chapter 14 Watchdog Timer
6.Setting
6. Setting
Table 6-1 Setting Required for Using the Watchdog Timer
Setting
Interval time setting
Startup of the watchdog
Setting register
Watchdog timer control register (RSRR)
Setting method
Refer to 7.1
Refer to 7.2
*: Refer to the number for more information on the setting method.
Table 6-2 Setting Required for Delaying the Generation of the Watchdog
Setting
Setting required for delay the generation of the
watchdog reset
Setting register
Watchdog reset generation delay register
(WPR)
Setting method
Refer to 7.3
*: Refer to the number for more information on the setting method.
Table 6-3 Setting Required for Checking the Generation of the Watchdog
Setting
Watchdog generation check
Setting register
Watchdog timer control register (RSRR)
Setting method
Refer to 7.5
*: Refer to the number for more information on the setting method.
151
Chapter 14 Watchdog Timer
7.Q & A
7. Q & A
7.1 What are the types of watchdog interval time and how are they selected?
There are four types of the interval period, and they are set using the interval selection bit (RSRR.WT[1:0]).
Watchdog
Interval time
To select Φ × 216
To select Φ × 218
To select Φ × 220
To select Φ × 222
Interval
Selection bit
(WT[1:0])
Set the value to
“00”
Set the value to
“01”
Set the value to
“10”
Set the value to
“11”
Example) Interval Time
FΦ =32.0MHz
FΦ = 2.00MHz
FΦ = 32.768kHz
2.04 ms
32.76 ms
2.00 s
8.19 ms
0.131 s
8.00 s
32.7 ms
0.524 s
32.0 s
0.131 s
2.097 s
128. s
Note: • Φ: Base clock. (Refer to “Chapter 11 Clock Control (Page No.103)”.)
• Only the data sets first written after the reset (INIT pin input, watchdog reset, software
reset) are valid, and the other data sets are invalid.
7.2 How is the watchdog operation started (set to valid)?
Writing data in the watchdog timer control register RSRR causes the watchdog timer to be started (set to valid). Writing
data in the interval selection bit (RSRR.WT[1:0]) causes the watchdog to be started.
7.3 How can we check that the watchdog reset has been generated?
If the watchdog reset flag (RSRR.WDOG) is set to “1”, the watchdog reset has been generated.
7.4 How is the watchdog stopped?
The watchdog cannot be stopped by the software.
The watchdog can be stopped only with the reset (INIT pin input, watchdog reset).
7.5 How do I clear the watchdog timer (1-bit counter)?
Successively writing “A5H” and “5AH” in the watchdog reset generation postponement register WPR causes the 1-bit
counter used for detecting the watchdog to be cleared immediately after writing “5AH”. In this state, the reset timing of
the watchdog can be postponed.
In addition, if the timebase timer is cleared, the 1-bit counter used for detecting the watchdog is simultaneously reset.
152
Chapter 14 Watchdog Timer
8.Sample Program
8. Sample Program
Setting procedure 1
Determining the cause of a reset, and setting the watchdog
<Determining the cause of a reset>
1
• Reset cause flag check
Confirming the reset cause register
INIT flag>>
Watchdog flag>>
Software reset flag>>
Program 1
_ _ start:
viod stsrt_program_initial_sample(void)
Register name .Bit name
RSRR
. INIT
. WDG
. SRST
Reset_Value(char)= IO_RSRR.byte;
if (Reset_Value & 0x08(char) )
Operation_for_SRST()
else if (Reset_Value & 0x20(char) )
Operation_for_WDG()
else if (Reset_Value & 0x80(char) )
Operation_for_INIT()
else
Operation_for_PROG()
………
/* Reset cause check */
/*
*/
/* Reset cause check, flag clear */
/* bit7
INIT
INIT flag */
/* bit5
WDOG
Watchdog flag */
/* bit3
SRST
Software reset flag */
/* Conditional
*/
branch
/* To the service after a software reset */
/* To the service after resetting the Watchdog */
/* To the service after inputting data to the INIT terminal */
/* To the service after program jump */
/* Arbitrary service */
}
<Watchdog setting>
• Watchdog timer
Interval selection (Startup)
Register name .Bit name
RSRR. WT[1:0]
void Set_Watchdog(void)
{
IO_RSRR.bit. WT = 3 ;
}
==== Variety of services ====
<Return service after inputting data to the INIT terminal>
/* Watchdog setting */
/*
*/
/* Interval selection */
void Operation_for_INIT(void)
/*Service after inputting data to the INIT terminal */
……
/* Arbitrary service */
void Operation_for_WDOG(void)
/*Service after inputting data to the WDOG */
……
/* Arbitrary service */
void Operation_for_SRST(void)
/*Service after SRST */
……
/* Arbitrary service */
void Operation_for_PROG(void)
/*Service after program jump */
……
/* Arbitrary service */
{
}
<Return service after the watchdog>
{
}
<Return service after a software reset>
{
}
<Return service after program jump>
{
}
Notice: Clock-associated settings and __set_il(Numeric value) settings are
required in advance. Refer to Chapters “Clock” and “Interrupt”.
/* For the types of register description, refer to “FRLite Family MB91230 Series Sample I/O Register File Usage
Guide”. */
153
Chapter 14 Watchdog Timer
9.Caution
9. Caution
• Although the watchdog interval time corresponds to the one twice as long as the watchdog 1-bit counter, the watchdog
timer clear operation only clears the 1-bit counter used for detecting the watchdog. As a result, the time margin to clear
the watchdog timer is different from the interval time.
Watchdog interval time selection
Time margin to clear the watchdog timer
Interval time during which the watchdog
reset is generated
00
Φ × 216 (Initial value)
Φ × 216 to Φ × 217
01
Φ × 218
Φ × 218 to Φ × 219
10
Φ×2
20
Φ × 220 to Φ × 221
11
Φ × 222
Φ × 222 to Φ × 223
WT1-WT0
• The watchdog timer is started once data is written in the watchdog timer control register.
• The watchdog timer control register is also the reset cause register, and the status (INIT,WDOG,SRST) is set to “0”
when it is read.
• The watchdog reset holds the oscillation stability wait time.
(Refer to “Chapter 12 Timebase Counter (Page No.119)”.)
• The watchdog reset from the main RUN or the sub-RUN where the main clock oscillation is in process cannot have the
oscillation stability wait time because the main clock is oscillating.
• Refer to “9. Caution (Page No.144)” for the method of clearing the timebase counter that is the count source for the
watchdog timer.
• Clearing the timebase counter causes the watchdog reset timing to be postponed once.
154
Chapter 15 Main Clock Oscillation Stability Wait Timer
1.Overview
Chapter 15
Main Clock Oscillation Stability Wait Timer
1. Overview
The main clock oscillation stability wait timer is a 23-bit counter that counts the main clock. (This timer does not affect
the selection of clock source operated by MCU/dividing setting.)
This timer is mainly used for acquiring main clock oscillation stability wait time to resume main clock oscillation after
the main clock oscillation has been stopped (OSCCR.OSCDS1=1) while the subclock is being operated.
In addition, this timer is best suited for interval timers or system clocks for real time OS.
ƒEƒHƒbƒ`ƒhƒbƒO
Watchdog
control section
§Œä•”
Timebase
ƒ^ƒCƒ
ƒx [ƒX
ƒJƒEƒ“ƒ^
counter
Base
ƒx
[ƒX
clock
ƒNƒ ƒbƒN
(φ)
iƒ³ j
ƒEƒHƒbƒ`ƒhƒbƒOƒ^ƒCƒ}
Watchdog
timer
ƒZƒŒƒNƒ^
Selector
ƒJƒEƒ“ƒ^
Counter
Watchdog
ƒEƒHƒbƒ`
ƒhƒbƒO
reset
ƒŠƒZƒbƒg
26 ƒrƒbƒgƒJƒEƒ“ƒ^
26-bit
counter
ƒ^ƒCƒ ƒx [ƒXƒ^ƒCƒ}
Timebase
timer
2. Features
• Type
• Quantity
• Clock source
: 23-bit free run counter
:1
: Main clock (source oscillation) --- Period = 1/FCL-MAIN
• Interval time
•
•
•
•
: 3 types
Period = 212/FCL-MAIN, 217/FCL-MAIN, 223/FCL-MAIN,
(1.0ms, 32.7ms, 2s / main clock 4MHz)
Cause of timer clear : (Software, overflow, reset (INIT))
Operation start/stop : Can be operated/stopped by the software.
Interrupt
: Main clock oscillation stability wait interrupt (Interval interrupt)
Count value
: Cannot read/write. (Clear only)
155
Chapter 15 Main Clock Oscillation Stability Wait Timer
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Main clock oscillation stability wait timer
Interval time
0
0
1
1
0
1
OSCR:bit 5
Operation stop
Operation enable
Edge detection
WEN
OSCR:bit 2-1
Setting disable
2 12 / FCL-MAIN
2 17 / FCL-MAIN
2 23 / FCL-MAIN
Selector
Timer operation enable
WS1-0
0
1
0
1
WIE
0
1
OSCR:bit 6
Interrupt disable
Interrupt enable
0
WIF
0
1
OSCR:bit 7
READ:
Without interrupt request
0
1
With interrupt request
WRITE
Flag clear
Main clock
1
Oscillation stability
wait interrupt (#46)
Not affected
23-bit free run timer
0
Main clock
(Source oscillation)
1
2
3
4
5
6 7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23
Timer clear
WCL
OSCR:bit 2
0
Timer clear
1
Does not affect the operation
Figure 3-2 List of Registers
Note: Refer to “Chapter 20 Interrupt Control (Page No.207)” for the ICR register and the interrupt vector.
156
Chapter 15 Main Clock Oscillation Stability Wait Timer
4.Register
4. Register
4.1 OSCR: Control Register for the Main Clock Oscillation Stability Wait Timer
This register is used to select the interval time, clear the timer, control the interrupt, control the timer such as stop, and
confirm the state of the timer.
• OSCR: Address 0490h (Access: Byte)
7
WIF
6
WIE
5
WEN
4
–
3
–
2
WS1
1
WS0
0
WCL
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
R(RM1),W
R/W
R/W
R0/W0
R0/W0
R/W
R/W
R1,W
bit
Initial value
(INIT terminal input,
watchdog reset)
Initial value
(Software reset)
Attribute
(For the attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• Bit7: Timer interrupt request flag
WIF
0
1
Read Operation
Without interrupt request
With interrupt request
Write Operation
Clears interrupt request flags
Writing does not affect operation
• The timer interrupt request flag bit is set to “1” at the falling edge of the selected interval period output.
• Bit6: Interrupt request enable
WIE
0
1
Operation
Interrupt request disable
Interrupt request enable
• If the timer interrupt request flag (WIF) is set to “1” while the interrupt request enable (WIE) is “1” an interrupt
request is immediately generated.
• Bit5: Timer operation enable
WEN
0
1
Operation
Stops timer operation
Enables timer operation
• Bit4-3: Reserved bit Be sure to write “0”. The read value is “0”.
• Bit2-1: Interval period selection
WS1
0
WS0
0
Interval period (At 4MHz)
0
1
212/FCL-MAIN (1.0ms)
1
0
217/FCL-MAIN (32.7ms)
1
1
223/FCL-MAIN (2.0s)
Setting disable
• The reset does not initialize. Be sure to set it after the startup.
• Bit0: Timer clear
WCL
0
1
Operation
Clears the main clock oscillation stability wait timer
Writing does not affect operation
(Refer to “9. Caution (Page No.165)”.)
157
Chapter 15 Main Clock Oscillation Stability Wait Timer
5.Operation
5. Operation
This section describes the main clock oscillation stability wait timer operation.
5.1 Main Clock Oscillation Stability Wait
158
(1)
Selects the interval time. (WS[1:0]) (In this example, 217/FCL-MAIC is selected.)
(2)
(3)
(4)
(5)
(6)
(7)
Sets timer clear (WCL=“0”) by the software.
Sets flag clear (WIF=“0”) and interrupt request enable (WIE=“1”) by the software.
Sets timer count enable (WEN=“1”) by the software.
Releases main clock stop (OSCCR.OSCDS1=“0”) while the subclock is in operation by the software, and starts main clock
oscillation.
Starts counting (The timer counts up using the main clock (source oscillation).)
Stabilizes the main clock oscillation.
(8)
(9)
(10)
(11)
The selected interval time is used. (Detects the falling edge of the dividing 217.)
Generates a main clock oscillation stability wait interrupt.
Processing caused by an interrupt (Software): Operation clock switching (Sub-RUN => main RUN)
Disables interrupt request (WIE=“0”) and clears interrupt request (WIF=“0”).
Chapter 15 Main Clock Oscillation Stability Wait Timer
5.Operation
(12) Stops counting (WEN=“0”).
5.2 Interval Interrupt
(1)
Selects an interval time (WS[1:0]). (In this example, 217/FCL-MAIC is selected.)
(2)
(3)
Clears the timer (WCL=“0”), clears flags (WIF=“0”), enables interrupt request (WIE=“1”), enables timer count (WEN=“1”)
by the software.
The timer counts up using the main clock (source oscillation).
(4)
(5)
(6)
Generates interval interrupt at the selected interval time (Falling of the dividing 217).
Processing caused by an interrupt (Software): Clears interrupt request (WIF=“0”).
Repeats Items (3) to (5)
159
Chapter 15 Main Clock Oscillation Stability Wait Timer
6.Setting
6. Setting
Figure 6-1 Settings Required for Using the Main Clock Oscillation Stability Wait Timer
Setting
Setting interval time
Count clear
Counting operation start
Setting register
Main clock oscillation stability wait
timer control register (OSCR)
Setting
method*
7.1
7.4
7.3
*: Refer to the number for more information on the setting method.
Figure 6-2 Settings Required for Enabling the Main Clock Oscillation Stability Wait Timer Interrupt
Setting register
Setting
method*
Refer to “Chapter 20 Interrupt Control (Page No.207)”.
7.5
The main clock oscillation stability
wait timer control register (OSCR)
7.7
Setting
Sets the main clock oscillation stability wait timer
interrupt vector and
Sets free run timer interrupt level
Sets the main clock oscillation stability wait timer interrupt
Clears interrupt request
Enables interrupt request
*: Refer to the number for more information on the setting method.
Figure 6-3 Settings Required for Stopping the Main Clock Oscillation Stability Wait Timer
Setting
Sets the main clock oscillation stability wait timer stop
Setting register
The main clock oscillation stability
wait timer control register (OSCR)
*: Refer to the number for more information on the setting method.
160
Setting
method*
7.8
Chapter 15 Main Clock Oscillation Stability Wait Timer
7.Q & A
7. Q & A
7.1 What are the types of interval time (wait time) and how are they selected?
There are 3 types of interval time, and they are set with the interval selection bit (OSCR.WS[0:1]).
Count period
Interval selection bit (WS[1:0])
Interval (Wait time) Example
At FCLKP = 4.00MHz
CL-MAIN
Set the value to “01”
1.00ms
CL-MAIN
Set the value to “10”
32.7ms
To set the value to223/FCL-MAIN
Set the value to “11”
2.00 s
Interval time
To set the value to
212/F
To set the value to
217/F
Note: Setting (WS[1:0]=“00”) is prohibited.
7.2 How do I select the count clock?
The count clock is the main clock (source oscillation). (Cannot be selected.)
7.3 How is the main clock oscillation stability wait timer count operation enabled/
disabled?
Sets with the timer operation enable bit (OSCR.WEN).
Operation
To stop the main clock oscillation stability wait timer
To start the main clock oscillation stability wait timer
Timer operation enable bit (WEN)
Set the value to “0”
Set the value to “1”
7.4 How is the main clock oscillation stability wait timer cleared?
The following methods are used to clear the main clock oscillation stability wait timer.
• Sets with the clear bit (OSCR.WCL).
Operation
To clear the main clock oscillation stability wait timer
Clear bit (WCL)
Writes “1”
• Performs a reset.
Clears the free run timer with the operation initialization reset (INIT terminal input, watchdog reset).
(Value is held without being cleared even if a software reset is performed.)
• The overflow (Next of “FFFFFFh”) of the main clock oscillation stability wait timer causes the count value to be reset
to “000000 H”.
7.5 What happens with the interrupt-associated registers?
Setting the interrupt vector and interrupt level of the main clock oscillation stability wait timer
The relationship between the interrupt level and the interrupt vector is shown in the following table.
Refer to “Chapter 20 Interrupt Control (Page No.207)” for the interrupt level and interrupt vector.
Interrupt vector (Default)
#46
Address: 0FFF44h
Interrupt level setting bit (ICR4-ICR0)
Interrupt level register (ICR30)
Address: 0045Eh
As the interrupt request flag (OSCR.WIF) is not automatically cleared, clear it before returning to interrupt processing by
the software. (Writes “0” in the WIF bit.)
161
Chapter 15 Main Clock Oscillation Stability Wait Timer
7.Q & A
7.6 What are the types of interrupt?
There is one type of interrupt called the main clock oscillation stability wait timer interrupt.
(Selection is unnecessary.)
7.7 how is an interrupt enabled?
Interrupt request enable and interrupt request flag
Setting the interrupt enable is performed with the interrupt request enable bit (OSCR.WIE).
Interrupt disable
Interrupt enable
Interrupt request enable bit (WIE)
Set the value to “0”
Set the value to “1”
Clearing an interrupt request is performed with the interrupt request bit (OSCR.WIF).
Interrupt request clear
Interrupt request bit (WIF)
Writes “0”
7.8 How is the main clock oscillation stability wait timer stopped counting?
Sets with the timer operation enable bit (OSCR.WE). Refer to 7.3.
In addition, if the MCU stops the main clock while the subclock is being operated, the main clock oscillation stability
wait timer also stops counting.
162
Chapter 15 Main Clock Oscillation Stability Wait Timer
8.Sample Program
8. Sample Program
Setting procedure 1
Main clock oscillation stability wait (Switches from sub to main.)
void MCSW_sample_()
{
main_clock_start();
MCST_initial();
MCST_start();
}
Initial setting (MCST_initial)
⏐
Startup (MCST_start)
⏐
Interrupt
<Main clock oscillation>
• Main clock oscillation
Oscillation control register
<Main clock stabilization timer initial setting>
1
• Setting
Setting control register
Timer interrupt request flag>>
Timer interrupt disable>>
Timer stopped>>
Reserved bit
Interval time>>
Timer clear>>
2
•Interrupt-associated
Main clock oscillation stability wait
interrupt level
Setting I flag
Program 1
Register name .Bit name
OSCCR. OSCDS1
void main_clock_start(void)
{
IO_CLK.IO_OSCCR.bit.OSCDS1 = 0;
}
/* Main clock oscillation start
*/
/*
*/
/* Main clock oscillation while the subclock is in operation */
viod MCST_initial(void)
/* Main clock oscillation stability wait timer initialization */
/*
*/
/* Setting value = 0000_0100 */
/* bit7=0
WIF
Timer flag clear */
/* bit6=0
WIE
Timer interrupt disable */
/* bit5=0
TBC
Timer stopped */
/* bit4-3 =00
-Reserved bit */
/* bit1=10
WS
Interval time */
/* bit0=0
WCL
Timer clear */
Register name .Bit name
OSCR
. WIF
. WIE
. WEN
IO_OSCR = 0x09;
. WS
. WCL
ICR30
IO_ICR[30].bit. ICR =0x10;
/* Sets interrupt level in a range of 16 to 31 */
(CCR)
__EI();
/* Interrupt enable */
}
<Main clock stabilization timer startup>
• Main clock oscillation stability wait
Register name .Bit name
timer
Clearing the timer
OSCR. WCL
Starting the timer
OSCR. WEN
• Timer interrupt enable
Timer interrupt request flag clear>>
OSCR. WIF
Timer interrupt enable>>
OSCR. WIE
void MCST_start(void)
/* Main clock oscillation stability wait timer startup */
{
/*
*/
IO_OSCR.bit. WCL = 0 ;
IO_OSCR.bit. WEN = 1 ;
/* Timer clear */
/* Timer startup */
IO_OSCR.bit. WIF = 0;
IO_OSCR.bit. WIE = 1;
/* bit7=0
/* bit6=0
WIF
WIE
Clearing the timer flag */
Timer interrupt enable */
}
<Main clock oscillation stability wait interrupt>
• Clock switching processing
Register name .Bit name
Clock switching (1/2 main)
CLKR. CLKS
Timer interrupt disable>>
OSCR. TBIE
Timer interrupt request flag clear>>
__interrupt void MCST_int()
{
IO_CLK.IO_CLKR.bit.CLKS = 1;
IO_OSCR.bit.WIE = 0;
OSCR. TBIF
IO_OSCR.bit.WIF = 0;
/* Interrupted if the interval time has elapsed */
/* bit6=0
CLKS
TBIE
/* bit7=0
TBIF
Main clock /2 from sub
Timer interrupt disable */
Timer interrupt request flag clear */
}
<Interrupt vector>
Vector table setting
/* Interrupt routine needs to be specified with the vector table */
#pragma intvect MCST_int 46
Notice: Clock-associated settings and __set_il(Numeric value) settings are
required in advance. Refer to Chapters “Clock” and “Interrupt”.
/* For the description types of the registers, refer to “FRLite Family MB91230 Series Sample I/O Register File Usage
Guide”. */
163
Chapter 15 Main Clock Oscillation Stability Wait Timer
8.Sample Program
Setting procedure 2
Interval interrupt using the main clock oscillation stability wait timer
Program 2
void MCSW_Interval_sample_()
{
MCST_initial();
MCST_start();
}
Initial setting (MCST_initial)
⏐
Startup (MCST_start)
⏐
Interrupt
<Main clock oscillation stability wait timer initial setting>
1
• Setting
Register name .Bit name
Setting the control register
OSCR
Timer interrupt request flag>>
. WIF
Timer interrupt disable>>
. WIE
Timer stopped>>
. WEN
Reserved bit
Interval time>>
. WS
Timer clear>>
. WCL
2
• Interrupt-associated
Main clock oscillation stability wait interrupt
ICR30
level
Setting I flag
(CCR)
viod MCST_initial(void)
IO_OSCR.byte = 0x09;
/* Main clock oscillation stability wait timer initialization */
/*
*/
/* Setting value = 0000_0100 */
/* bit7=0
WIF
Timer flag clear */
/* bit6=0
WIE
Timer interrupt disable */
/* bit5=0
TBC
Stopping the timer */
/* bit4-3 =00
-Reserved bit */
/* bit1=11
WS
Interval time 2.0s */
/* bit0=0
WCL
Timer clear */
IO_ICR[30].bit. ICR =0x10;
/* Sets the interrupt level in a range of 16 to 31 */
__EI();
/* Interrupt enable*/
}
<Main clock oscillation stability wait timer startup>
• Main clock oscillation stability wait timer
Clearing the timer
Starting the timer
• Timer interrupt enable
Timer interrupt request flag clear>>
Timer interrupt enable>>
Register name .Bit name
OSCR. WCL
OSCR. WEN
void MCST_start(void)
{
IO_OSCR.bit. WCL = 0 ;
IO_OSCR.bit. WEN = 1 ;
OSCR. WIF
OSCR. WIE
IO_OSCR.bit. WIF = 0;
IO_OSCR.bit. WIE = 1;
/* Main clock oscillation stability wait timer startup */
/*
*/
/* Timer clear */
/* Timer startup*/
/* bit7=0
/* bit6=0
WIF
WIE
Timer flag clear */
Timer interrupt enable */
}
<Main clock oscillation stability wait interrupt>
• Clock switching processing
Timer interrupt request flag clear>>
Register name .Bit name
__interrupt void MCST_Interval_int()
{
……
OSCR. TBIF
IO_OSCR.bit.WIF = 0;
/* Interrupted if the interval time has elapsed */
/* Arbitrary processing
/* bit7=0
TBIF
*/
Timer interrupt request flag clear */
}
<Interrupt vector>
Setting vector table
/* Interrupt routine needs to be specified with the vector table */
#pragma intvect MCST_Interval_int 46
Notice: Clock-associated settings and __set_il(Numeric value) settings are
required in advance. Refer to Chapters “Clock” and “Interrupt”.
/* For the description types of the registers, refer to “FRLite Family MB91230 Series Sample I/O Register File
Usage Guide”. */
164
Chapter 15 Main Clock Oscillation Stability Wait Timer
9.Caution
9. Caution
• To wait until the main clock oscillation stability is attained while the subclock is in operation, it is necessary to acquire
wait time using the main clock oscillation stability wait timer.
(An unstable clock may be supplied to the entire device, and normal operation is not guaranteed if the MCU operation
mode is switched from the sub-RUN to the main RUN mode without waiting until the main clock oscillation becomes
stable.)
• The value for the oscillation stability wait time is an estimated value because the oscillation period of the main clock
oscillation is unstable for the beginning immediately after the oscillation has started.
• If the main clock oscillation stops, the main clock oscillation stability wait interrupt (interval interrupt) is not generated
either because the main clock oscillation stability wait timer stops. The main clock oscillation should be enabled for
processing that uses the main clock oscillation stability wait interrupt (interval interrupt).
• The flag is set to “1” (flag setting preference) if the timer interrupt request (WIF=“1”) and the writing operation where
“0” is written by software in the flag occur simultaneously.
• The main clock oscillation stability wait timer is counted up with the main clock. As a result, in the following state, the
counting of the timer used to stop the main clock oscillation also stops.
• If the timer operation enable bit (OSCR.WEN) is “0”, the timer stops counting.
• If the main clock is set to stopped in the stop mode (STCR.OSCD1=“1”), the timer stops counting from the moment
the stop mode is activated.
• If the main clock oscillation is specified for Stopped (OSCCR.OSCDS1=“1”) during subclock operation, the timer
stops while the subclock is in operation.
• If you want to enable (WIE=“1”) the interrupt request after the reset is released, and the interval time to be modified, be
sure to simultaneously set the interrupt request flag (WIF) and the clear bit (WCL) to “0” beforehand.
• The timer interrupt request bit (WIF), timer interrupt request enable bit (WIE), timer enable bit (WEN) and timer clear
bit (WCL) are initialized to “0” using the setting initialization reset (INIT terminal input, watchdog reset).
• Be sure to set the interval selection bit (WS[1:0]) after startup (after setting initialization reset) by the software.
• The main clock oscillation stability wait timer control register should be initialized (to set the initial value) only with
the setting initialization reset (INIT terminal input, watchdog reset) because the software reset does not initialize the
register and the current value is held.
• If the counter clear (WPCR.WCL=“0”) and the overflow for the selected bit occur simultaneously, the interrupt request
flag (WIF) is not set to “1”.
165
Chapter 15 Main Clock Oscillation Stability Wait Timer
9.Caution
166
Chapter 16 Clock Timer
1.Overview
Chapter 16 Clock Timer
1. Overview
The clock timer is a 15-bit counter that is counted up with the subclock. This clock timer does not affect the selection/
dividing setting of the MCU operating clock.
This clock timer is used to acquire subclock oscillation stability wait time if the subclock oscillation is resumed mainly
when the subclock oscillation is stopped while the main clock is in operation.
However, this timer is best suitable for MB91230 interval timers for clock counting since the subclock does not stop.
Main clock
(Source oscillation)
Up-counter
Selector
Interrupt
2. Features
• Type
• Quantity
• Clock source
: 15-bit free run counter
:1
: Subclock (source oscillation) --- Period = 1/FCL-SUB = 1/32.768kHz
• Interval time
: 4 types
Period = 210/FCL-SUB, 213/FCL-SUB, 214/FCL-SUB, 223/FCL-SUB,
•
•
•
•
Timer clear cause
Interrupt
Count value
Other
(31.25ms, 0.25s, 0.50s, 1.00s)
: (Software, overflow, reset (INIT))
: clock interrupt (interval interrupt)
: Cannot read and write (Clear only)
: Always in operation while the power supply (Vcc3) is supplied.
167
Chapter 16 Clock Timer
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Clock timer
Interval time
0
0
1
1
WS1-0
0
1
0
1
WPCR:bit 2-1
2 10 /
2 13 /
2 14 /
2 25 /
FCL-SUB
FCL-SUB
FCL-SUB
FCL-SUB
WIE
0
1
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
Edge detection
Selector
Clock timer
(14-bit free run timer)
WPCR:bit 6
Interrupt disable
Interrupt enable
0
WIF
0
1
WPCR:bit 7
Clock timer
Without interrupt request
With interrupt request
WRITE; 0: Flag clear
1
Interrupt (#49)
Sub-clock
(Source oscillation)
2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15
32.768 kHz
Timer clear
WCL
0
1
WPCR:bit 2
Timer clear
Does not affect the operation
Figure 3-2 List of Registers
Note: For the ICR register and interrupt vector, refer to “Chapter 20 Interrupt Control (Page No.207)”.
168
Chapter 16 Clock Timer
4.Register
4. Register
4.1 WPCR: Clock Timer Control Register
This register is used to select interval time, clear the timer, control interrupt, control timer stop etc., and confirm the
states.
• WPCR: Address 048Ch (Access: Byte)
7
WIF
0
R(RM1),W
6
WIE
0
R/W
5
–
0
R0/W0
4
–
0
R0/W0
3
–
0
R0/W0
2
WS1
0
R/W
1
WS0
0
R/W
0
WCL
0
R1,W
bit
Initial value (At INIT) *1
Attribute
(For the attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
(Refer to “9. Caution (Page No.178)”.)
• Bit7: Clock timer interrupt request flag
WIF
0
1
Read Operation
Without interrupt request
With interrupt request
Write Operation
Clears the interrupt request flag
Writing does not affect operation
• The clock timer interrupt request flag bit is set to “1” at the falling edge of the selected interval period output.
• Bit6: Interrupt request enable
WIE
0
1
Operation
Interrupt request is prohibited
Interrupt request enable
• If the interrupt request enable bit is set to “1” an interrupt request is enabled.
• If the clock timer interrupt request flag is (WIF=“1”), and if the interrupt request enable bit (WIE) is set to “1”, an
interrupt request is immediately generated.
• Bit5-3: Reserved bit Be sure to write “0”. The read value is “0”.
• Bit2-1: Interval period selection
Interval period (FCL-SUB= 4MHz)
WS1
WS0
0
0
210/FCL-SUB (31.25ms)
0
1
213/FCL-SUB (0.25s)
1
0
214/FCL-SUB (0.50s)
1
1
215/FCL-SUB (1.00s)
• Bit0: Timer clear
WCL
0
1
Operation
Clears the clock timer.
Writing does not affect write operation.
Notes 1: Initial value can be set using the setting initialization reset (INIT terminal input,
watchdog reset), but the operation initialization reset (Software reset) holds the current
value instead of initializing it.
2: If you set the interrupt request enable (WIE=“1”), and the interval period selection
(WS[1:0]) after canceling the reset, be sure to simultaneously set the timer interrupt
request flag (WIF) and the timer clear (WCL) “0”.
169
Chapter 16 Clock Timer
5.Operation
5. Operation
5.1 Subclock Oscillation Stability Wait Interrupt
The following operation is not required for the MB91230 series because the subclock does not stop.
Figure 5-1 Reference
(7)
(5)
Subclock
oscillation example
(The oscillation does not
stop in the MB91230.)
Clock timer
counting
(8)
0400h
(6)
0000h
Time
(1) 2 10 (Bit 9)
(8)
Subclock stop bit
(There is no subclock
stop bit in the MB91230.)
WCL
(4)
(2)
WIF
(3)
WIE
(3)
Operation clock mode
(9)
(11)
(11)
Subclock
Main clock
(10)
170
(1)
Selects the interval (WS[1:0]) (In this example, 210/FCL-MAIC is selected.)
(2)
(3)
(4)
(5)
(6)
(7)
Sets the timer so that it is cleared (WCL=“0”) by software.
Sets the flag clear (WIF=“0”) and the interrupt request enable (WIE=“1”) by software.
Sets the subclock stop release (OSCCR.OSCDS1=“0”) while the subclock is in operation by software.
The subclock oscillation starts (The subclock used in the MB91230 series always oscillates.)
Counts up with the subclock (source oscillation).
Make the subclock oscillation stable.
(8)
(9)
(10)
(11)
Makes the interval time be the selected time. (Detects the falling of 210dividing.)
If the flag (WIF) becomes “1”, the subclock oscillation stability wait interrupt request is generated.
Processing cause by an interrupt (Software): Switching the operation clock (Sub-RUN => main RUN)
Interrupt request disable (WIE=“0”) and the interrupt request clear (WIF=“0”).
Chapter 16 Clock Timer
5.Operation
5.2 Interval Interrupt (Clock Interrupt)
Clock timer
counting
(4)
4000h
(4)
2000h
(3)
(3)
0000h
(2)
Time
(1) 213 (Bit12)
WCL
(4)
(4)
(2)
WIF
(2)
WIE
(2)
(5)
(6)
(5)
(6)
(1)
Selects the interval time. (WS[1:0]) (In this example, 213/FCL-SUB is selected.)
(2)
(3)
Sets the timer clear (WCL=“0”), flag clear (WIF=“0”) and interrupt request enable (WIE=“1”) by the software.
The timer counts up with the subclock (Source oscillation).
(4)
(5)
(6)
Makes the interval time be the selected time. (Detects the fall of 213.)
If the flag (WIF) is set to “1”, interval interrupt request (Clock interrupt request) is generated.
Processing caused by an interrupt (Software): The interrupt request clear (WIF=“0”)
(Arbitrary processing such as clock counting)
Repeats Items (3) to (6).
(7)
171
Chapter 16 Clock Timer
5.Operation
5.3 Returning from the Stop Mode due to Interval Operation (Clock Interrupt)
Clock timer
counting
7FFFh
4000h
(2)
0000h
(3) 2 14 (Bit 13)
(7)
Interval time
WCL
(1)
(10)
WIF
(8)
(4)
WIE
(5)
MCU state
Main
RUN
SubRUN
(6)
STOP
(9)
SubRUN
STOP
SubRUN
STOP
SubRUN
STOP
SubRUN
STOP
SubRUN
Oscillation stability wait time
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Sets so that the clock timer is cleared by software. (Writes “0” to WCL.)
Counts up the clock timer with the subclock.
Selects the interval time. (In this example, 0.5 second: Selects WS[1:0]=“10”.)
Sets the flag clear (WIF=“0”) and clock timer interrupt enable (WIE=“1”) by the software.
Switches the MCU operation from the main RUN to sub-RUN.
Switches to the stop mode.
Makes the interval time be the selected time. (0.5 second)
The interrupt request flag (WIF) is set to “1”.
As the interrupt request is enabled (WIE=“1”), returns from the stop mode to sub-RUN.
(In the MB91230 series, the subclock always oscillates, but the subclock oscillation stability wait time is acquired. Initial
value=122µs). Refer to “Chapter 12 Timebase Counter (Page No.119)”.
(10) Clears the interrupt request flag by software. (Writes “0” to the WIF.)
(11) Repeats Items (6) from (10).
172
Chapter 16 Clock Timer
6.Setting
6. Setting
Table 6-1 Settings Required for Using the Clock Timer
Setting
Setting the interval time
Count clear
Setting register
Clock timer control register (WPCR)
Setting
method*
Refer to 7.1.
Refer to 7.4.
*: Refer to the number for more information on the setting method.
Table 6-2 Items Required for Enabling the Clock Timer Interrupt
Setting register
Setting
method*
Refer to “Chapter 20 Interrupt Control
(Page No.207)”.
Refer to 7.5.
Clock timer control register (WPCR)
Refer to 7.7.
Setting
Setting the interrupt vector and the free run timer level of
the clock timer
Setting the clock timer interrupt
Clearing the interrupt request
Enabling the interrupt request
*: Refer to the number for more information on the setting method.
173
Chapter 16 Clock Timer
7.Q & A
7. Q & A
7.1 What are the types of interval time (wait time) and how are they selected?
There are three types of interval time, and they are set with the interval selection bit (WPCR.WS[1:0]).
Interval selection bit (WS[1:0])
Interval (Wait time) Example
FCL-SUB = 32.768kHz
To set the interval time to
210/FCL-SUB
Set the value to “00”.
31.25ms
To set the interval time to
213/FCL-SUB
Set the value to “01”.
0.25s
To set the interval time to
214/FCL-SUB
Set the value to “10”.
0.50s
To set the interval time to
215/FCL-SUB
Set the value to “11”.
1.00s
Interval time
Count period
7.2 How is the count clock selected?
The count clock is the subclock (source oscillation).
7.3 How does the clock timer count up?
As the MB91230 subclock does not stop, the clock timer is always counting.
7.4 How is the clock timer cleared?
The following methods are available to clear the clock timer.
• Sets the clear bit (WPCR.WCL).
Operation
To clear the clock timer
Clear bit (WCL)
Writes “1”
• Performs a reset.
Clears the 14-bit free run timer with the initialization reset (INIT terminal input, watchdog reset).
Note: The operation initialization reset (Software reset) holds the count of a 14-bit free run timer.
• The overflow of the clock timer (Next count-up for “FFFFh”) causes the count value to be reset to
“0000 H”.
7.5 What are interrupt-associated registers?
Setting the interrupt vector and the interrupt level of the clock timer
The relationship between the interrupt level and the vector is shown in the following table.
Refer to “Chapter 20 Interrupt Control (Page No.207)” for more information on the interrupt level and the interrupt
vector.
Interrupt vector (Default)
#46
Address: 0FFF44h
Interrupt level setting bit (ICR[4:0])
Interrupt level register (ICR30)
Address: 0045Eh
As the interrupt request flag (WPCR.WIF) is not automatically cleared, clear it before returning from the interrupt
processing by the software. (Writes “0” to the WIF bit.)
174
Chapter 16 Clock Timer
7.Q & A
7.6 What are the types of interrupt?
There is one type for the interrupt, and it is generated with the interval time (Subclock oscillation stability wait).
175
Chapter 16 Clock Timer
7.Q & A
7.7 How is the interrupt enabled?
The interrupt request enable and the interrupt request flag
The interrupt enable is set with the interrupt request enable bit (WPCR.WIE).
Interrupt disable
Interrupt enable
Interrupt request enable bit (WIE)
Set the value to “0”
Set the value to “1”
The interrupt request is cleared with the interrupt request bit (WPCR.WIF).
Interrupt request clear
Interrupt request bit (WIF)
Writes “0”
7.8 How is the clock timer stopped counting?
The MB91230 has no control bit to stop the clock timer.
As a result, the clock timer cannot be stopped.
Note: However, the clock timer can stop accidentally if an element such as vibrator is defective and the subclock
consequently stops.
176
Chapter 16 Clock Timer
8.Sample Program
8. Sample Program
Setting procedure 1
Interval interrupt at the clock timer
Program 1
void WATCH_Interval_sample_()
{
MCST_initial();
MCST_start();
}
Initial setting (WATCH_initial)
¾
Startup (WATCH_start)
Interrupt
<Clock timer initial setting>
1
• Setting
Setting the control register
Timer interrupt request flag>>
Timer interrupt disable>>
Reserved bit
Interval time>>
Timer clear>>
2
• Interrupt-associated
Clock timer interrupt level
Setting the I flag
Register name .Bit name
WPCR
. WIF
. WIE
viod WATCH_initial(void)
Åo
IO_WPCR.byte = 0x09;
. WS
. WCL
ICR33
(CCR)
IO_ICR[33].bit. ICR =0x15;
__EI();
/* Clock timer initialization */
/*
/* Setting value = 0000_0100 */
/* bit7=0
WIF
/* bit6=0
WIE
/* bit5-3 =000
-/* bit2-1=10
WS
/* bit0=0
WCL
*/
Timer flag clear */
Timer interrupt disable */
Reserved bit */
Interval time 0.5s */
Timer clear */
/* Setting the interrupt level in a range of 16 to 31 setting */
/* Interrupt enable*/
}
<Clock timer startup>
• Clock timer
Clearing the timer
Starting the timer
• Timer interrupt enable
Timer interrupt request flag clear>>
Timer interrupt enable>>
Register name .Bit name
WPCR. WCL
WPCR. WEN
void WATCH_start(void)
{
IO_WPCR.bit. WCL = 0 ;
IO_WPCR.bit. WEN = 1 ;
WPCR. WIF
WPCR. WIE
IO_WPCR.bit. WIF = 0;
IO_WPCR.bit. WIE = 1;
/* Clock timer startup */
/*
*/
/* Timer clear */
/* Timer startup */
/* bit7=0
/* bit6=0
WIF
WIE
Timer flag clear */
Timer interrupt enable */
}
<Clock timer interrupt>
• Clock switching processing
Timer interrupt request flag clear>>
Register name.Bit name
__interrupt void WATCH_int()
{
……
WPCR. TBIF
IO_WPCR.bit.WIF = 0;
/* An interrupt is enabled when the interval time has elapsed */
/* Arbitrary processing
/* bit7=0
TBIF
*/
Timer interrupt request flag clear
*/
}
<Interrupt vector>
Setting the vector table
/* The interrupt routine needs to be specified with the vector table */
#pragma intvect WATCH_int 49
Notice: Clock-associated settings and __set_il(Numeric value) settings are
required in advance. Refer to Chapters “Clock” and “interrupt”.
/* For the description types of the registers, refer to “FRLite Family MB91230 Series Sample I/O Register File Usage
Guide”. */
177
Chapter 16 Clock Timer
9.Caution
9. Caution
• While the clock timer supplies VCC3, and supplies the subclock, the clock timer continues operating including the stop
mode.
• If the setting request (WIF=“1”) of the timer interrupt request flag and the writing timing where “0” is written to the
flag by the software occur simultaneously, the flag is set to “1”. (The flag is set preferentially.)
• If the interrupt request is enabled (WIE=“1”) after defeating a reset, and if the interval time is changed, be sure to
simultaneously set “0” to the interrupt request enable flag (WIF) and the clear bit (WCL).
• Read-modify-write
The interrupt request flag (WIF) is always read as “1” with the Read-modify-write.
• The setting initialization reset (INIT terminal input, watchdog reset) initializes the values of the timer interrupt request
bit (WIF), timer interrupt request enable bit (WIE), timer enable bit (WEN) and timer clear bit (WCL) to “0”, but
cannot initialize the interval period selection bit (WS[1:0]). Be sure to set it by the software.
• Setting the initial value of the clock timer control register is possible using the initialization reset (INIT terminal input,
watchdog reset), but the operation initialization reset (Software reset) holds the current value instead of initializing the
value of the clock timer control register.
• The value for the oscillation stability wait time is an estimated value because the oscillation period of the main clock
oscillation is unstable for the beginning immediately after the oscillation has started.
Note: The subclock used in the MB91230 does not stop. As a result, operation associated with subclock
oscillation stability wait with the clock timer is unnecessary for the MB91230.
As a conclusion, disregard the following notice.
• An unstable clock may be supplied to the entire device, and normal operation is not guaranteed if the subclock is made
to oscillate starting from subclock stopped state, and if the MCU operation mode is switched from the main RUN to the
sub-RUN mode without waiting until the subclock oscillation becomes stable. Be sure to acquire the subclock
oscillation stability wait time using the clock timer, etc. (If the main clock is selected as the clock source, the
oscillation stability wait time for the subclock may not be acquired.)
• The value for the oscillation stability wait time is an estimated value because the oscillation period of the subclock is
unstable for the beginning immediately after it has started.
• As the clock timer stops while the subclock stops oscillating, a clock interrupt (interval interrupt) is not generated,
either. If processing using the clock interrupt (interval interrupt) is performed, enable the subclock oscillation. (Do not
stop the subclock oscillation).
• The clock timer counts up with the subclock. As a result, the timer stops counting because the subclock stops
oscillating under the following conditions.
• If the subclock is set so that it stops in the stop mode (Subclock oscillation enable bit* =“1”), and then the mode is
switched to the stop mode, the clock timer stops counting while in the stop mode.
• If you want the clock timer to continue counting while in stop mode, set the subclock oscillation enable bit* to “0”
before switching the mode to the stop mode.
(*: No control bit of this kind is available in the MB91230 series.)
• If the subclock stop bit** =“1” while in the subclock, and if the subclock is specified so that it stops oscillating
while the subclock is in operation, the clock timer stops, too, while the subclock is in operation.
(**: The MB91230 series has no control bit to stop the clock timer.)
178
Chapter 17 Delayed Interrupt
1.Overview
Chapter 17 Delayed Interrupt
1. Overview
Delayed interrupt, or the delayed interrupt module is used to generate an interrupt used for task switching.
Delay interrupt
control circuit
Software request
Interrupt request (#63)
2. Features
• Type: Interrupt request bit (There is no interrupt request enable bit)
• Quantity: 1
• Other:
• The software generates/releases interrupt request.
• Real time OS uses the delayed interrupt for task switching.
3. Configuration
Figure 3-1 Configuration Diagram
Delay interrupt
Delay interrupt control bit
DLYI
DICR: bit 0
Read
Write
0
Without interrupt
0
Delay interrupt release
1
With interrupt
1
Delay interrupt request
Delay interrupt control circuit
Interrupt request (#63)
Figure 3-2 List of Registers
179
Chapter 17 Delayed Interrupt
4.Register
4. Register
4.1 DICR: Delay Control Register
This register controls to generate/release the delayed interrupt.
• DICR: Address 0044h (Access: Byte)
7
–
–
6
–
–
5
–
–
4
–
–
RX/WX
RX/WX
RX/WX
RX/WX
3
–
–
RX/
WX
2
–
–
1
–
–
0
WCL
0
bit
Initial value
RX/WX
RX/WX
R/W
Attribute
(Refer to “■Meaning of Bit Attribute Symbols (Page No.10)” for the attributes.)
• Bit7-1: Undefined: Writing does not affect operation. The read value is indefinite.
• Bit0: Delayed interrupt control bit
WIF
0
1
Read operation
With no delayed interrupt request
With delayed interrupt request
Write operation
Delayed interrupt request release
Delayed interrupt request generation
5. Operation
Delayed interrupt service
Preference interrupt
(4)
Delay
(5)
Delay interrupt
(6) (7)
Task A
OS
Task B
(1) A task dispatch request is generated.
(2) Setting for the dispatch destination (Delay return destination)
(3) Setting for the delay interrupt request (Generating)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
180
In OS, a request for task B dispatch is generated
OS sets the delayed interrupt return destination (dispatch destination)
OS sets the delayed interrupt (delayed interrupt generation)
When OS returns, the interrupt with the highest priority sequence takes place, because an interrupt service is
prohibited in OS
When the interrupt with the highest priority is completed, delayed interrupt takes place
In delayed interrupt, delayed interrupt is released
Returned from the delayed interrupt (dispatched to task B)
Chapter 17 Delayed Interrupt
6.Setting
6. Setting
Table Setting required for the delay interrupt generation/release
Table 6-1 Setting required for the delay interrupt generation/release
Setting
Setting for delay interrupt vector and free run timer interrupt
level
Setting register
Refer to “Chapter 20 Interrupt Control (Page No.207)”
Setting method*
Delay interrupt setting
Generating interrupt request/Releasing interrupt request
Clock timer control register (WPCR)
Refer to 7.2
Refer to 7.1
*: Refer to the number for the setting method.
7. Q & A
7.1 What are interrupt-associated registers?
Setting for the delay interrupt vector and interrupt level
The relationship between the delay interrupt level and the delay interrupt vector is shown in the following table.
Refer to “Chapter 20 Interrupt Control (Page No.207)” for more information on the interrupt level and interrupt vector.
Interrupt vector (default)
#63
Address: 0FFF00h
Interrupt level setting bit (ICR[4:0])
Interrupt level register (ICR47)
Address: 0046Fh
The interrupt request bit (DICR.DLTI) cannot automatically be released, and it should be released by the software before
returning from an interrupt service. (“0” is written for DLTI bit)
7.2 How interrupt request is generated/released?
Delay the interrupt request bit (DICR.DLTI) performs this function.
Generating an interrupt request
Releasing an interrupt request
Interrupt request enable bit (WIE)
Sets the value to “0”
Sets the value to “1”
The delayed interrupt does not have the interrupt request enable bit that is designed for other periphery macros.
8. Sample Program
Set_delayed_intrrupu()
{
IO_DICR.bit.DLYI = 1; delayed interrupt call
}
9. Caution
• The delay interrupt request bit is the same as general interrupt request flags. It should be used to clear delayed interrupt
request bit in an interrupt routine in addition to switching tasks.
• The delayed interrupt function can use real time OS (REALOS). As a result, the delayed interrupt function is prohibited
in a piece of user software when using real time OS.
181
Chapter 17 Delayed Interrupt
9.Caution
182
Chapter 18 Bit Search
1.Overview
Chapter 18 Bit Search
1. Overview
The bit search module is used to detect 0, 1 or changing point for data written in specific registers.
Detection
circuit
(0-point,
1-point and
changing
point)
0-point register
1-point register
Result register
Changing-point register
2. Features
• Function: Detects the first changing point by scanning data written in data register from MSB to LSB.
• 0 detection
Detects the first ‘0’ changing point.
• 1 detection
Detects the first ‘1’ changing point.
• Changing point detection
Detects the point where data first changes.
• Quantity: 1
• Other: Can read internal data.
(This can be used to restore the previous state when it is used for bit search during interrupt service or handler.)
183
Chapter 18 Bit Search
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Detection mode selection
Bit search
Address decoder
0-/1-/Changing-point-detection
data register
Write only
Lowest four bits
of the address
Operation selection
for BSD0/BSD1/BSDC
0000
0100
0-detection
1000
Changing-point-detection
1-detection
BSD0/ BSD1/ BSDC
Detection result
Run only
Detection data (BSD1)
Detection circuit
(0-/1-/Changing-points)
Figure 3-2 List of Registers
Bit search
184
BSRR
Chapter 18 Bit Search
4.Register
4. Register
4.1 BSD0: 0 Detection Register / BSD1:1 Detection Register / BSDC: Changing Point
Detection Data Register
This is a register for setting the bit search detection data.
• BSD0: Address 03F0H (Access: Word)
• BSD1: Address 03F4H (Access: Word)
• BSDC: Address 03F8H (Access: Word)
31
0
BSD0
Indefinite
W
31
bit
Initial value
Attribute
0
BSD1
Indefinite
R,W
31
bit
Initial value
Attribute
0
BSDC
Indefinite
W
bit
Initial value
Attribute
(For the attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• Write data used to detect 0, 1 and changing point in each of the registers BSD0, BSD1 and BSDC.
• The result is stored in the detection result register BSRR.
• During 0 detection, the position where “0” is first detected is stored for data written in the order of MSB(bit31) to
LSB(bit0).
• During 1 detection, the position where “1” is first detected is stored for data written in the order of MSB(bit31) to
LSB(bit0).
• During change point detection, the position where a value different from MSB(bit31) is first detected is stored for
data written in the order of bit30 to LSB(bit0).
• The register BSD0 used for 0 detection and the BSRC register used for changing point detection are write-only. The
value during read operation is indefinite.
• Data saved in the bit search can be read if the register BSR1 used to detect 1 is read.
Previous detection result can be restored by re-writing previously read data in the BSR1 used for detecting 1. This
applies to the processes for the 0 detection and the changing point detection.This function can be used to restore a
specific state when using a bit search in processing such as interrupt handler.
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Chapter 18 Bit Search
4.Register
4.2 BSRR: Detection Result Register
This register is used to read a bit search result.
• BSRR: Address 03FCH (Access: Word)
31
0
BSRR
Indefinite
R
bit
Initial value
Attribute
(For the attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• Detection result for data written in the 0 detection register BSD0, the 1-detection register BSD1 and the changingpoint-detection register BSDC can be read. Data last written can be read. However, the type of result cannot be
identified: Information on 0 detection,1 detection or changing point detection is not included.
A 0 can be read at detection position bit31(MSB), and continues reading 31 at detection position bit0(LSB) by adding 1
at the next position toward bit0(LSB). A value of 32 is read when not detected.
• The detection result register is read-only, and a write operation is invalid.
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Chapter 18 Bit Search
5.Operation
5. Operation
5.1 Zero detection
Bit position from MSB
Data
11111111111 111 11 2
0123456 789 ABCDEF0123456789AB CDEF 0
1111111 111 000 000 0000000000 000 000
Scan
>>>>>>>>>> 0
Detection result
AH (10 Decimal)
(1) Bit position from MSB
(2) Written data (Starts to search once data is written.)
(3) Detects “0” by scanning from MSB.
(4) Detected bit position
(5) Detection result
If ‘0’ does not exist (That is, numeric value is FFFFFFFFH), ‘32’ is returned as detection result.
• Execution example
Write data
11111111111111111111000000000000B (FFFFF000H)
11111000010010011110000010101010B (F849E0AAH)
10000000000000101010101010101010B (8002AAAAH)
11111111111111111111111111111111B (FFFFFFFFH)
Read value
→
→
→
→
(Decimal notation)
20
5
1
32
5.2 One Detection
Bit position from MSB
Data
1111111111 111 111 2
0123456789 AB CDEF0123456789ABCDEF 0
0000000000 000 000 001111111111 11 11
Scan
>> >>>>>>>>>>>>>>>>1
Detection result
12 H (18Decimal)
(1) Bit position from MSB
(2) Written data (Detection operation starts once data is written.)
(3) Detect “1” scan starting with the MSB.
(4) Detected bit position
(5) Detection result
If ‘1’ does not exist (That is, if numeric value is 00000000H), value of ‘32’ is returned as detection result.
• Execution example
Write data
00100000000000000000000000000000B (20000000H)
00000001001000110100010101100111B (01234567H)
00000000000000111111111111111111B (0003FFFFH)
00000000000000000000000000000001B (00000001H)
00000000000000000000000000000000B (00000000H)
Read value
→
→
→
→
→
(Decimal notation)
2
7
14
31
32
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Chapter 18 Bit Search
5.Operation
5.3 Changing Point Detection
11111111111 11 111 2
0123456789 AB CDEF0123456789ABCDEF 0
Bit position from MSB
0000000000 00 000 111000000000 00 000
Data
>>>>>>>>>>>>>>>*
Scan
Detection result
F H (15Decimal)
(1) Bit position from MSB
(2) Written data (Detection starts once data is written.)
(3) Detects the changing point by scanning from MSB.
(4) Detected bit position
(5) Detection result
A value of ‘32’ is returned as detection result if changing point does not exist.
A value of ‘0’ is not returned as detection result for changing point detection.
• Execution example
Write data
00100000000000000000000000000000B (20000000H)
00000001001000110100010101100111B (01234567H)
00000000000000111111111111111111B (0003FFFFH)
00000000000000000000000000000001B (00000001H)
00000000000000000000000000000000B (00000000H)
11111111111111111111000000000000B (FFFFF000H)
11111000010010011110000010101010B (F849E0AAH)
10000000000000101010101010101010B (8002AAAAH)
11111111111111111111111111111111B (FFFFFFFFH)
Read value
→
→
→
→
→
→
→
→
→
(Decimal notation)
2
7
14
31
32
20
5
1
32
Table 5-1 The Relationship Between the Bit Position and the Value to be Returned (Decimal Notation)
Detected
bit position
31
30
29
28
27
26
25
24
188
Return
value
0
1
2
3
4
5
6
7
Detected
bit position
23
22
21
20
19
18
17
16
Return
value
8
9
10
11
12
13
14
15
Detected
bit position
15
14
13
12
11
10
9
8
Return value
16
17
18
19
20
21
22
23
Detected
bit position
7
6
5
4
3
2
1
0
Nonexistent
Return value
24
25
26
27
28
29
30
31
32
Chapter 18 Bit Search
6.Setting
6. Setting
Table 6-1 Settings Required for Zero Point Detection
Setting
Data write & scan start
Converted value read
Setting register
Zero point detection data register (BSD0)
Detection result register (BSRR)
Setting
method *
Refer to 7.1.
Refer to 7.2.
*: For detailed description contents, refer to the reference destination number.
Table 6-2 Setting Required for Using One Point Detection
Setting
Data write & scan start
Converted value read
Setting register
One point detection data register (BSD1)
Detection result register (BSRR)
Setting
method *
Refer to 7.1.
Refer to 7.2.
*: For detailed description contents, refer to the reference destination number.
Table 6-3 Setting Required for Using Changing Point Detection
Setting
Data write & scan start
Converted value read
Setting register
Changing point detection data register (BSDC)
Detection result register (BSRR)
Setting
method *
Refer to 7.1.
Refer to 7.2.
*: For detailed description contents, refer to the reference destination number.
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Chapter 18 Bit Search
7.Q & A
7. Q & A
7.1 How is data written?
Writes data with the detection data registers (BSD0, BSD1, BSDC).
Operation mode
Zero point detection write
One point detection write
Changing point detection write
Detection data register
Writes data in (BSD0)
Writes data in (BSD1)
Writes data in (BSDC)
7.2 How is scanning started?
Scanning is started once data is written in the detection data registers (BSD0, BSD1, BSDC).
7.3 How is a result read?
The detection result register (BSRR) is read.
7.4 How is the previous bit search state restored?
The following restoration processes are performed.
If you need to restore the previous bit search state after a bit search has been executed in an interrupt handler.
1) Reads data from the one detection data register, and saves the contents. (evacuation)
2) The Bit search is used.
3) Writes data evacuated in Item 1) in the one detection data register. (restoration)
Using the above procedures, the value to be read next from the detection result register is the one that was written in the
bit search executed in 1) or before.
The bit search state can be correctly restored using the above procedures even if the 0-detection, 1-detection or changingpoint-detection data register has been written last.
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Chapter 18 Bit Search
8.Sample Program
8. Sample Program
Setting procedure Example 1
Program Example 1
Zero point detection is performed.
void BIT_SARCH_sample_1()
{
Bit_0_(void);
}
<Setting>
(1)
(2)
Bit_0_()
• Data write & search
Register name
Data write, Search start
BSD0
{
IO_BSD0 = 0xF8;
/* Zero point detection data write*/
result= IO_BSRR
/* Detection result read
• Detection result read
Detection result read
BSRR
*/
}
Notice: Clock-associated settings and __set_il(Numeric value) settings are
required in advance.
Note: For the description types of the registers, refer to “FRLite Family MB91230 Series Sample I/O
Register File Usage Guide”.
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Chapter 18 Bit Search
9.Caution
9. Caution
The following are the remarks on using the bit search module.
• The macros are for REALOS(OS), and the user cannot use them when using REALOS.
• If the relevant detection is not found, a detection result of 32(decimal), 10(hexadecimal) or 10000(binary) is returned.
• A value of “0” is not returned for the changing point detection.
• The data registers (0-detection/1-detection/ changing-point-detection) is a write-only, and accessed by word.
However, the 1-detection read address is assigned to an internal data register for restoration so that you can restore
previous bit search state. (Refer to “7.3 How is a result read? (Page No.190)”.)
• The 0-detection register BS0, 1-detection register BSD1 and changing-point-detection register BSDC are included in
one register in terms of the structure. The operation is selected with the lowest four bits of the accessing address.
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Chapter 19 I/O Port
1.Overview
Chapter 19 I/O Port
1. Overview
The I/O port consists of four registers that control the switching between the multipurpose and peripheral functions and
the switching between the input and output.
Multi-purpose port read
Input to the peripheral function
Output from
the peripheral function
Port data
Data direction
Port function
Pull-up resistor control
Control
circuit
Terminal
2. Features
• Number of ports: 96
• Multipurpose port function and peripheral function are combined (All Port)
Peripheral function output: 61 (among them, 2 analog outputs)
Peripheral function input : 35 (among them, 8 analog outputs)
Selectable pull-up resistor: 16
• Open drain output
: 4 (P64-P67)
IOL=20mA(max) of current drive is possible.
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Chapter 19 I/O Port
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
I/O port
PCRx: bity
Pxy
Pull-up resistor
0
Without pull-up resistors
1
With pull-up resistors
Input to the peripheral function (@@@)
0
PDR read
1
1
Terminal
Output from the periphery function (***)
Write
Pxy
Multi-purpose port data
PDRx: bity
0
“L”
1
“H”
0
***
Peripheral function
PFRx: bity
0
Peripheral function input and
the selection of the multi-purpose port
1
Peripheral function output
Pxy
Data direction
Pxy/***/@@@
OR
DDRx: bity
0
Input
1
Output
Pxy: Multi-purpose name
***: Peripheral function output terminal name
@@@: Peripheral function input terminal name
Refer to the terminal function table in Chapter “Basic Information” for the peripheral function terminal name.
Figure 3-2 Configuration Diagram
I/O port (A/D-AN terminal and UART-SCK terminal)
Input to the peripheral function (AN and SCK)
1
0
0
PDR read
1
Output from the peripheral function (SCK)
Multi-purpose port data
(Read)
Pxy
1
Terminal
0
P26/SCK2
P31/SCK3
P02/SCK0
P05/SCK1
PC0/AN0
PC1/AN1
PC2/AN2
PC3/AN3
PC4/AN4
PC5/AN5
PC6/AN6
PC7/AN7
PDRx: bity
0
“L”
1
“H”
Peripheral function
PFRx: bity
***
0
Peripheral port selection
1 Peripheral function input/output
Data direction
(Write)
Pxy
DDRx: bity
0
Input
1
Output
Pxy: Multi-purpose name
***: Peripheral function input/output terminal name
Refer to the terminal names on the right for the terminal names.
194
OR
Chapter 19 I/O Port
3.Configuration
Figure 3-3 List of Registers
195
Chapter 19 I/O Port
3.Configuration
196
Chapter 19 I/O Port
4.Register
4. Register
4.1 PDR: Port Data Register
This register is to store data that is output from the multi-purpose port.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PDR0 (Port0): Address 0000h (Access: Byte)
PDR1 (Port1): Address 0001h (Access: Byte)
PDR2 (Port2): Address 0002h (Access: Byte)
PDR3 (Port3): Address 0003h (Access: Byte)
PDR4 (Port4): Address 0004h (Access: Byte)
PDR5 (Port5): Address 0005h (Access: Byte)
PDR6 (Port6): Address 0006h (Access: Byte)
PDR7 (Port7): Address 0007h (Access: Byte)
PDR8 (Port8): Address 0008h (Access: Byte)
PDR9 (Port9): Address 0009h (Access: Byte)
PDRA (PortA): Address 000Ah (Access: Byte)
PDRB (PortB): Address 000Bh (Access: Byte)
PDRC (PortC): Address 000Ch (Access: Byte)
PDRD (PortD): Address 000Dh (Access: Byte)
--------------------------------------------------------------------• PDRF (PortF): Address 000Fh (Access: Byte)
7
P07
P17
P27
P37
P47
P57
P67
–
P87
P97
PA7
–
PC7
–
–
–
0
R, RM/W
6
P06
P16
P26
P36
P46
P56
P66
–
P86
P96
PA6
–
PC6
–
–
–
0
R, RM/W
5
P05
P15
P25
P35
P45
P55
P65
–
P85
P95
PA5
–
PC5
–
–
–
0
R, RM/W
4
P04
P14
P24
P34
P44
P54
P64
–
P84
P94
PA4
–
PC4
–
–
PF4
0
R, RM/W
3
P03
P13
P23
P33
P43
P53
–
P73
P83
P93
PA3
PB3
PC3
–
–
PF3
0
R, RM/W
2
P02
P12
P22
P32
P42
P52
–
P72
P82
P92
PA2
PB2
PC2
–
–
–
0
R, RM/W
1
P01
P11
P21
P31
P41
P51
–
P71
P81
P91
PA1
PB1
PC1
PD1
–
–
0
R, RM/W
0
P00
P10
P20
P30
P40
P50
–
P70
P80
P90
PA0
PB0
PC0
PD0
–
–
0
R, RM/W
bit
Initial value
Attribute
(For the attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• While writing: Register used to write data that is output from the Multi-purpose port.
Bit
0
1
Operation
In the port output mode, outputs “L”.
In the port output mode, outputs “H”.
• While reading:
Bit
0
1
Port input mode
Level on the terminal(Pxx) is at “L”
Level on the terminal(Pxx) is at “H”
Meaning
Port output mode
PDR value is “0”
PDR value is “1”
Peripheral output mode
Peripheral function output value is “L”
Peripheral function output value is “H”
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Chapter 19 I/O Port
4.Register
• While in Read-modify Operation:
While in Read-modify operation: The value of the port data register PDR can be read.
• Be sure to access it on a byte basis (8bit). Read/Write may not be correct if it is accessed on a half-word/
word basis.
• The bit name is the same as the terminal name.
• Undefined bit “–”: Writing does not affect the operation. The read value is indefinite.
• The port output from P64, P65, P66 or P67 cannot be at “H”. (N-channel open drain terminal)
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Chapter 19 I/O Port
4.Register
4.2 DDR: Data Direction Register
This register is to select the input or output in the state of the multi-purpose port.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DDR0 (Port0): Address 0400h (Access: Byte)
DDR1 (Port1): Address 0401h (Access: Byte)
DDR2 (Port2): Address 0402h (Access: Byte)
DDR3 (Port3): Address 0403h (Access: Byte)
DDR4 (Port4): Address 0404h (Access: Byte)
DDR5 (Port5): Address 0405h (Access: Byte)
DDR6 (Port6): Address 0406h (Access: Byte)
DDR7 (Port7): Address 0407h (Access: Byte)
DDR8 (Port8): Address 0408h (Access: Byte)
DDR9 (Port9): Address 0409h (Access: Byte)
DDRA (PortA): Address 040Ah (Access: Byte)
DDRB (PortB): Address 040Bh (Access: Byte)
DDRC (PortC): Address 040Ch (Access: Byte)
DDRD (PortD): Address 040Dh (Access: Byte)
--------------------------------------------------------------------• DDRF (PortF): Address 040Fh (Access: Byte)
7
P07
P17
P27
P37
P47
P57
P67
–
P87
P97
PA7
–
PC7
–
–
–
0
R/W
6
P06
P16
P26
P36
P46
P56
P66
–
P86
P96
PA6
–
PC6
–
–
–
0
R/W
5
P05
P15
P25
P35
P45
P55
P65
–
P85
P95
PA5
–
PC5
–
–
–
0
R/W
4
P04
P14
P24
P34
P44
P54
P64
–
P84
P94
PA4
–
PC4
–
–
PF4
0
R/W
3
P03
P13
P23
P33
P43
P53
–
P73
P83
P93
PA3
PB3
PC3
–
–
PF3
0
R/W
2
P02
P12
P22
P32
P42
P52
–
P72
P82
P92
PA2
PB2
PC2
–
–
–
0
R/W
1
P01
P11
P21
P31
P41
P51
–
P71
P81
P91
PA1
PB1
PC1
PD1
–
–
0
R/W
0
P00
P10
P20
P30
P40
P50
–
P70
P80
P90
PA0
PB0
PC0
PD0
–
–
0
R/W
bit
Initial value
Attribute
(For the attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• If the multi-purpose port is in the input/output state, select the input or output.
• If the port is in the multi-purpose port input/output state
(If the target bit of the port function register PFR = “0” or there is no target bit)
Bit
0
1
Port status
Multi-purpose port input and the peripheral function input
Multi-purpose port output
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Chapter 19 I/O Port
4.Register
• If the port is in the peripheral function output (If the target bit of the port function register PFR = “1”)
Bit
0
1
Port status
Peripheral function output
• While reading: Can read the value of the data direction register DDR.
• Be sure to access it on a byte basis (8bit).
• Read/Write may not be correct if it is accessed on a half-word/word basis.
• The bit name is the same as the terminal name.
• Undefined bit “–”: Writing does not affect the operation. The read value is indefinite.
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Chapter 19 I/O Port
4.Register
4.3 PFR: Port Function Register
This register is to set whether the output from the peripheral function is enabled or disabled.
• PFR0 (Port0): Address 0420h (Access: Byte)
-------------------------------------------------------------------•
•
•
•
•
•
•
•
•
•
•
•
PFR2 (Port2): Address 0422h (Access: Byte)
PFR3 (Port3): Address 0423h (Access: Byte)
PFR4 (Port4): Address 0424h (Access: Byte)
PFR5 (Port5): Address 0425h (Access: Byte)
PFR6 (Port6): Address 0426h (Access: Byte)
PFR7 (Port7): Address 0427h (Access: Byte)
PFR8 (Port8): Address 0428h (Access: Byte)
PFR9 (Port9): Address 0429h (Access: Byte)
PFRA (PortA): Address 042Ah (Access: Byte)
PFRB (PortB): Address 042Bh (Access: Byte)
PFRC (PortC): Address 042Ch (Access: Byte)
PFRD (PortD): Address 042Dh (Access: Byte)
---------------------------------------------------------------------
• PFRF (PortF): Address 042Fh (Access: Byte)
Name
PFR0
–
PFR2
PFR3
PFR4
PFR5
PFR6
PFR7
PFR8
PFR9
PFRA
PFRB
PFRC
PFRD
–
PFRF
7
–
–
–
–
CKOT
–
SEG31
–
SEG7
SEG15
SEG23
–
AN7
–
–
–
6
–
–
SCK2
–
TOT2
–
SEG30
–
SEG6
SEG14
SEG22
–
AN6
–
–
–
5
SCK1
–
SOT2
–
TOT1
–
SEG29
–
SEG5
SEG13
SEG21
–
AN5
–
–
–
4
SOT1
–
–
–
TOT0
PPG5
SEG28
–
SEG4
SEG12
SEG20
–
AN4
–
–
–
3
–
–
OP3
–
PPG3
PPG4
–
COM3
SEG3
SEG11
SEG19
SEG27
AN3
–
–
TOT3
2
SCK0
–
OP2
–
PPG2
–
–
COM2
SEG2
SEG10
SEG18
SEG26
AN2
–
–
–
1
SOT0
–
OP1
SCK3
PPG1
–
–
COM1
SEG1
SEG9
SEG17
SEG25
AN1
DA1
–
–
0
–
–
OP0
SOT3
PPG0
–
–
COM0
SEG0
SEG8
SEG16
SEG24
AN0
DA0
–
–
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Initial
value
Attribute
(For the attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
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Chapter 19 I/O Port
4.Register
• Sets enable/disable for the peripheral function output.
Bit
0
1
Port status
Peripheral function output is prohibited.(Input status) Refer to 9. Caution.
Peripheral function output is enabled.
(Operation is not affected by the value in the data direction register except for some parts of the peripheral function.)
• When reading: Can read the value of the port function register PFR.
• Be sure to access it on a byte basis (8bit).
Read/Write may not be correct if it is accessed on a half-word/word basis.
• The bit name is the same as the peripheral function output name.
• Undefined bit “–”: Writing does not affect the operation. The read value is indefinite.
• Be sure to write “0” in the bit positions that are not used by the peripheral function.
• Refer to “Table 1-1 Pin Function Table (Page No.25)” for the peripheral function terminal names.
4.4 PCR: Pull-up Resistor Control Register
This register controls the pull-up resistor function for the corresponding multi-purpose port.
• PCR1 (Port1): Address 0501h (Access: Byte)
• PCR3 (Port3): Address 0503h (Access: Byte)
Name
PCR1
PCR3
7
P17
P37
6
P16
P36
5
P15
P35
4
P14
P34
3
P13
P33
2
P12
P32
1
P11
P31
0
P10
P30
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(For the attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• Sets whether or not the pull-up resistor function is enabled.
Bit
0
1
Port status
The pull-up resistor function is not enabled (Without the pull-up resistor)
The pull-up resistor function is enabled.
• When reading: Can read the value of the pull-up resistor control register PFR.
• Be sure to access it on a byte basis (8bit).
Read/Write may not be correct if it is accessed on a half-word/word basis.
• The bit name is the same as the terminal name.
• Refer to “2. I/O Circuit Type (Page No.29)” for the pull-up resistor value.
202
bit
Initial
value
Attribute
Chapter 19 I/O Port
5.Operation
5. Operation
This section describes the operation mode as follows.
a) Port input mode
b) Port output mode
c) Peripheral function output mode
***
(PFR)
a)
Pxy
(DDR)
Pxy
(PDR)
0
0
0
0
0
1
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
b)
c)
Terminal state
Multi-purpose Port
input
(Pxy),
Peripheral function
input
(@@@)
Multi-purpose Port
output “L”
Multi-purpose Port
output “H”
Peripheral function
output
(***)
PDR read value
PDR read value with Readmodify-write
PDR register value of “0”
Terminal(Pxy) level
PDR register value of
“0”
PDR register value of
“1”
Peripheral function
output value
(Note: The value is not at
the terminal level.)
PDR register value of “1”
PDR register value of “0”
PDR register value of “1”
PDR register value of “0”
PDR register value of “1”
PDR register value of “0”
PDR register value of “1”
Note: Refer to “Table 1-1 Pin Function Table (Page No.25)” for the peripheral function terminal name (***/
@@@).
203
Chapter 19 I/O Port
6.Setting
6. Setting
Table 6-1 Settings Required for Setting the I/O Port
Setting
Multi-purpose port output value
I/O terminal setting
Peripheral function terminal setting
Setting register
Port data register (PDR)
Data direction register (DDR)
Port function register (PFR)
Setting method*
Refer to 7.1.
Refer to 7.2.
Refer to 7.3.
*: Refer to the number for more information on the setting method.
7. Q & A
7.1 How are multi-purpose port output values set?
They are set using the port data register PDR.
When multi-purpose port
Set the value to “L”.
Set the value to “H”.
Port data register (PDR)
Set the corresponding bit to “0”
Set the corresponding bit to “1”.
7.2 How are the multi-purpose port input/output set?
They are set with the data direction register (DDR) and the port function register (PFR).
Terminal
Multi-purpose port input
Multi-purpose port output
Data direction register (DDR)
Sets the corresponding bit to “0”.
(Specifies the input.)
Sets the corresponding bit to “1”.
(Specifies the output.)
Port function register (PFR)
Sets the corresponding bit to “0”
(Specifies the input.)
Sets the corresponding bit to “0”.
(Specifies the Multi-purpose port.)
7.3 How are the peripheral function output/input set?
They are set with the data direction register DDR and the port function register (PFR).
Terminal
Peripheral function input
Peripheral function output
Data direction register (DDR)
Sets the corresponding bit to “0”.
(Specifies the input.)
Not affected by the corresponding bit
value.
Port function register (PFR)
Sets the corresponding bit to “0”.
(Specifies the input.)
Sets the corresponding bit to “1”.
(The peripheral function output is
specified.)
7.4 How are the pull-up resistors built in the port used?
They are set with the pull-up resistor control register (PCR).
Pull-up resistor
Without using pull-up resistors
Using pull-up resistors
204
Pull-up resistor control register (PCR)
Sets the corresponding bit to “0”.
Sets the corresponding bit to “1”.
Chapter 19 I/O Port
8.Sample Program
8. Sample Program
• Multi-purpose input port:
void P20_input_port(void)
{
IO_PORT1.IO_PFR2.bit.P20=0; /* Selects the multi-purpose port.*/
IO_PORT1.IO_DDR2.bit.P20=0; /* Selects the input.
*/
}
• Multi-purpose output port:
void P20_output_port(void)
{
IO_PORT1.IO_PFR2.bit.P20=0; /*Selects the multi-purpose port.*/
IO_PORT1.IO_PDR2.bit.P20=1; /*Sets the output to “1”. */
IO_PORT1.IO_DDR2.bit.P20=0; /* Selects the output.
*/
}
• Peripheral function output (input) port:
Refer to each chapter of the peripheral functions.
9. Caution
The following are the remarks on using the I/O port.
• Access the following registers on an 8-bit basis (byte): the port data register (PDR), data direction register (DDR), port
function register (PFR) and pull-up resistor control register (PCR).
Accessing on a 16-bit (Half-Word) or 32-bit (Word) basis may have problems with read/write.
• The method of input control is different, depending on the peripheral function: the data direction register (DDR) or the
port function register (PFR) is used. If the peripheral function input is set, we recommend that the target bits for the
data direction register (DDR) and the port function register (PFR) be set to “0” However, only the A/D converter port
function selection bit (PFR.AN[7:0]) should be set to “1” for the peripheral function input setting.
• If the multi-purpose port is selected, Terminals P64 to P67 can drive with a drive current of IOL=20mA(max) for open
drain output.
• Be sure to write “0” in the unused peripheral function bit positions for the port function register (PFR).
205
Chapter 19 I/O Port
9.Caution
206
Chapter 20 Interrupt Control
1.Overview
Chapter 20 Interrupt Control
1. Overview
Interrupt control manages interrupt reception and arbitration.
NMI
Wakeup
Priority judging circuit
Interrupt level/
interrupt vector
generator
NMI processing
Interrupt requests
(peripheral function,
INT instruction, and
delayed interrupt)
Level
HLDREQ
cancel
request
Interrupt
priority
judging circuit
HALT
To the CPU
Vector number
2. Features
• Functions
• Detection of interrupt requests
• Priority determination (determined by level and number)
• Interrupt level propagation of the factor of the priority to the CPU
• Interrupt number propagation of the factor of the priority to the CPU
• Request (to the CPU) to return from stop mode by a legitimate interrupt (Wakeup)
• Interrupt level
• Reserved for System: Level 0 to 14
• MNI
: level 15 (Not supported in MB19230)
• Interrupt
: level 16 to 31
• Interrupt disable
: level 32
(As the interrupt level goes up, the number goes down.)
• Interrupt: The number of factors
• MNI: 1 (Not supported in MB19230)
• Interrupt from a peripheral function: 59
External interrupt (16), reload timer (4), UART reception (4), UART transmission (4), A/D (2), real-time clock (1),
main clock oscillation stabilization timer (1), timebase timer (1), clock timer (1), up/down counter (2), PPG (3),
free-run timer (2), input capture (2), output compare (4)
• Delayed interrupt
:1
• Reserved for system (for REALOS): 2
• INT instruction
:176
207
Chapter 20 Interrupt Control
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Priority judging circuit
The enabled interrupt request
NMI
Wakeup
Interrupt
request
enable bit
Interrupt
cause
NMI processing
Interrupt
request
flag
Interrupt priority
judging circuit
External interrupt ( 16)
Reload timer ( 4)
UART receive ( 4)
UART transmit ( 4)
A/D ( 2)
Real-time clock ( 1)
Main clock oscillation
stabilization timer ( 1)
Timebase timer ( 1)
Clock timer ( 1)
Up/down counter ( 2)
PPG ( 3)
Free-run Timer ( 2)
Input capture ( 2)
Output compare ( 4)
Delayed interrupt ( 1)
Level
Interrupt level
/interrupt
number
generator
HLDREQ
cancel
request
To the CPU
HALT
Number
Interrupt control register
ICR (4-0)
ICR0-ICR47: bit4-0
00000
Cannot be set.
01111
10000
Higher interrupt
11110
Lower interrupt
11111
Disable interrupts
Reserved for system [REALOS] ( 2)
INT instruction (
176)
Figure 3-2 Configuration Diagram
RAM
Interrupt control (CPU side)
(PS, PC)
The inside of the CPU
Interrupt level mask register
ILM (4-0)
-0)
00000
l
01111
ILM register in CPU
System processing
I flag
Prioritization
10000
l
11110
Interrupt processing
11111
Initial level
Interrupt level [ICRxx: ICR (4-0)]
Interrupt
control
circuit
SSP
Rewrite
0
Disable
1
Enable
PS
PC
Table base register
TBR
Initial value: FFC00
Interrupt number (#)
Interrupt number (#) x 4 + TBR
Address
208
Vector table
(1k Bytes)
Chapter 20 Interrupt Control
3.Configuration
Figure 3-3 Register List
209
Chapter 20 Interrupt Control
3.Configuration
Figure 3-4 Interrupt vector list
Figure 3-5 Vector Table (INT)
210
Chapter 20 Interrupt Control
3.Configuration
211
Chapter 20 Interrupt Control
4.Registers
4. Registers
4.1 ICR: Interrupt Control Register
The register that specifies the interrupt level of an interrupt request.
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
ICR16
ICR17
ICR18
ICR19
ICR20
ICR21
ICR22
ICR23
ICR24
ICR25
ICR26
ICR27
ICR28
ICR29
ICR30
ICR31
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
ICR39
ICR40
ICR41
ICR42
ICR43
ICR44
ICR45
ICR46
ICR47
212
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
#37
#38
#39
#40
#41
#42
#43
#44
#45
#46
#47
#48
#49
#50
#51
#52
#53
#54
#55
#56
#57
#58
#59
#60
#61
#62
#63
(External interrupt 0)
(External interrupt 1)
(External interrupt 2)
(External interrupt 3)
(External interrupt 4)
(External interrupt 5)
(External interrupt 6)
(External interrupt 7)
(Reload timer 0)
(Reload timer 1)
(Reload timer 2)
(UART0 receive)
(UART0 transmit)
(UART1 receive)
(UART1 transmit)
(UART2 receive)
(UART2 transmit)
(UART3 receive)
(UART3 transmit)
(A/D0)
(A/D1)
(External interrupt 8)
(External interrupt 9)
(External interrupt 10)
(External interrupt 11)
(External interrupt 12)
(External interrupt 13)
(External interrupt 14)
(External interrupt 15)
(Real-time clock)
(Main clock oscillation stabilization timer)
(Timebase timer)
(Reload timer 3)
(Clock timer)
(Up/down counter 0)
(Up/down counter 1)
(PPG0/1)
(PPG2/3)
(PPG4/5)
(Free-run Timer 0)
(Free-run Timer 1)
(Input capture 0)
(Input capture 1)
(Output compare 0)
(Output compare 1)
(Output compare 2)
(Output compare 3)
(Delayed interrupt)
: Address 0440H
: Address 0441H
: Address 0442H
: Address 0443H
: Address 0444H
: Address 0445H
: Address 0446H
: Address 0447H
: Address 0448H
: Address 0449H
: Address 044AH
: Address 044BH
: Address 044CH
: Address 044DH
: Address 044EH
: Address 044FH
: Address 0450H
: Address 0451H
: Address 0452H
: Address 0453H
: Address 0454H
: Address 0455H
: Address 0456H
: Address 0457H
: Address 0458H
: Address 0459H
: Address 045AH
: Address 045BH
: Address 045CH
: Address 045DH
: Address 045EH
: Address 045FH
: Address 0460H
: Address 0461H
: Address 0462H
: Address 0463H
: Address 0464H
: Address 0465H
: Address 0466H
: Address 0467H
: Address 0468H
: Address 0469H
: Address 046AH
: Address 046BH
: Address 046CH
: Address 046DH
: Address 046EH
: Address 046FH
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
(Access: Byte)
Chapter 20 Interrupt Control
4.Registers
ICR (Interrupt Control Register) is a register in the interrupt controller, and it specifies the interrupt level for each
interrupt request. ICR corresponds to each of interrupt request input. ICR is mapped to the I/O space.
• ICR00 – ICR47
7
–
6
–
5
–
4
ICR4
3
ICR3
2
ICR2
1
ICR1
0
ICR0
–
–
–
1
1
1
1
1
RX/WX
RX/WX
RX/WX
R/WX
R/W
R/W
R/W
R/W
bit
Initial
value
Attribute
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• Bit 7-5: Undefined. Writing does not affect the operation. The read value is indeterminate.
• Bit 4-0: Interrupt level setting bits
ICR4-ICR0 bits
0000-01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Interrupt level
0-14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Description
Reserved for system (cannot to be set)
NMI (Does not exist in MB91230)
The highest level
(High)
(Low)
The lowest level
Disable interrupts
• The interrupt level setting bit specifies the interrupt level of the corresponding interrupt request.
• When the interrupt level set to the interrupt control register is the same as, or higher than the level mask value set to
the ILM register of the CPU, the interrupt request is masked by the CPU side.
213
Chapter 20 Interrupt Control
4.Registers
4.2 Interrupt Vector
Interrupt vector that corresponds to a vector number (#).
#00
#01
#07
: Address
: Address
: Address
: Address
~
~
~
#63
FFFBCh (fixed address)
FFFB8h (fixed address)
FFFE0h (henceforth, the value of TBR register is 0FFC00h (initial value))
FFF00h
32 bits
• Set the address of each interruption handling routine to the corresponding vector.
• The address of a vector = TBR (table vector register) + {3FCH - 4 x vector number (#)}
• EIT used by system (#0-#14)
Interrupt number
#0
#1
#2-#6
#7
#8
#9
#10
#11
#12
#13
#14
#15
214
Interrupt level (fixed)
0
1
–
7
8
9
10
11
12
13
14
15
Factor
Reset vector
Mode vector
Reserved for system
Coprocessor absence trap
Coprocessor error trap
INTE instruction
Instruction break exception
Operand break trap
Step trace trap
MNI request (TOOL)
Undefined-instruction exception
NMI request (not supported in MB91230)
Chapter 20 Interrupt Control
5.Operation
5. Operation
The following section explains priority determination operation of interrupt control.
The Flow of the Interrupt Process
Interrupt cause generated
The interrupt request flag is set to “1”.
CPU processing
Is the interrupt level higher than
the interrupt mask level?
NO
NO
(ICR) < (ILM)
Are interrupt requests enabled?
YES
YES
Priority determination
The interrupt request is transmitted to
the interrupt control circuit.
Are interrupts enabled?
I flag = 1
NO
Interrupt control circuit
Is not the corresponding interrupt disabled?
(ICR) < 31?
Interrupt level = 31
Interrupt number
= indeterminate
YES
Wait until the executed instructions finish
YES
Which interrupt has the lowest level
among the interrupt requests?
The lowest interrupts
Which interrupt has the lowest
number (#) among the lowest
interrupt requests?
Transition processing to interrupts
- Save to the system stack (PS and PC)
- Set an interrupt level to ILM
- System stack enabled
- Branch to the interrupt routine
(PC <= interrupt vector)
The interrupt with
the lowest number
The interrupt level and the interrupt number
are transmitted to the CPU.
■ Priority determination
• The interrupt control circuit selects the highest priority factor from those that have been generated simultaneously, and
outputs the factor's interrupt level (ICR) and interrupt number (#) to the CPU.
• The priority level criteria of an interrupt cause are the following conditions.
• The value of the interrupt level is not 31. (31 is “interrupt disable”)
• The factors with the smallest interrupt level.
• Among these, the factor that has the smallest interrupt number.
• If nothing is applicable by the above-mentioned criteria, interrupt level 31 (11111B) is sent to the CPU. In this case, the
interrupt number is indeterminate.
215
Chapter 20 Interrupt Control
6.Setting
6. Setting
Table 6-1 Setting Required to Use Interrupts
Setting
Setting Registers
Setting the interrupt level
Setting of interrupt vectors
Clearing the interrupt request flags
Enabling interrupt requests
I flag setting
Interrupt control registers (ICR00 to ICR47)
See sample programs.
See the corresponding chapter for each peripheral function.
See the corresponding chapter for each peripheral function.
CCR register
Setting
Procedure
See 7.1
See 7.4
–
–
See 7.5
*: For the setting procedure, refer to the section indicated by the number.
Table 6-2 Setting that Requires the Setting within Interrupt Processing
Setting
Setting Registers
Clearing the interrupt request flags
See the corresponding chapter for each peripheral function.
Setting
Procedure
–
7. Q & A
7.1 How can I set interrupt levels?
Set by Interrupt control registers (ICR00 to ICR47).
It is necessary to set interrupt levels in advance to the control registers of the applicable interrupts.
How to specify the highest level
How to specify a level
How to specify the lowest level
When interrupt is not used
Interrupt control registers ICR00 to ICR47
Set 16.
Set any level (from 16 to 30).
Set 30.
Set 31 (interrupt disable).
• Since the bit of the interrupt control register (ICR4) is fixed to “1”, 0 to 15 cannot be set to a register.
7.2 How do I enable interrupts?
To enable interrupts, all of the following three settings should be set:
• Set the value 16 to 30 to the applicable register in the interrupt control registers (ICR00-ICR47).
• Set the interrupt request enabling bit of the applicable peripheral function to “1” (enable) (See the chapter for the
corresponding peripheral function).
• Set the interrupt enabling flag (I) to “1.”
7.3 How do I disable interrupts?
To disable interrupts, at least one of the following three settings should be set:
• Set the value 31 to the applicable register in the interrupt control registers (ICR00-ICR47).
• Set the interrupt request enabling bit of the applicable peripheral function to “0” (disable).
• Set the interrupt enabling flag (I) to “0” (disable all interrupts.)
7.4 How can I set interrupt vectors?
See “• Vector table (Page No.218)”.
216
Chapter 20 Interrupt Control
7.Q & A
7.5 How can I set an I flag?
−>In C:
I flag is set to “1” (interrupt enable) by writing __EI();.
I flag is set to “0” (interrupt disable) by writing __DI();.
Two underscores
217
Chapter 20 Interrupt Control
8.Sample Programs
8. Sample Programs
• Interrupt process routine
Write with __interrupt type qualifier.
/* Interrupt routine block */
_ _ interrupt void OCU3_int(void){
(Any programs)
}
(Etc.)
No arguments or return value.
Function name
• Vector table
Write in pragma section
/* SECTION setting */
#pragma section INTVECT, locate=0x0ffc00
extern __interrupt void OCU3_int(void);
(Etc. )
Function name
Write in pragma intvect
/*
Function name
Vector No.
Interrupt number (#)
/*
#pragma intvect
#pragma intvect
Instruct_int
Delayd_int
80
63
/*_ INT instruction
/* Delayed interrupt request bit
*/
*/
#pragma intvect
#pragma intvect
OCU3_int
OCU2_int
62
61
/* OCU3 (compare)
/* OCU2 (compare)
*/
*/
#pragma Intvect
#pragma intvect
OCU1_int
OCU0_int
60
59
/* OCU1 (compare)
/* OCU0 (compare)
*/
*/
#pragma intvect
#pragma intvect
ICU1_int
ICU0_int
58
57
/* ICU1 (capture)
/* ICU0 (capture)
*/
*/
(Etc.)
#pragma intvect
Ext_3_int
19
/* INT 3
*/
#pragma intvect
#pragma intvect
Ext_2_int
Ext_1_int
18
17
/* INT 2
/* INT 1
*/
*/
#pragma intvect
#pragma Intvect
Ext_0_int
16
_Dummy_int 15
/* INT 0
/* no NMI in MB91230
*/
*/
#pragma intvect
#pragma intvect
_rei_int
_abt_int
14
13
/* reserved instruction exception */
/* abort handler(tool)
*/
#pragma intvect
#pragma intvect
_str_int
_opr_int
12
11
/* step trace trap
/* operand trace trap
*/
*/
#pragma intvect
#pragma intvect
_brake_int
_inte_int
10
9
/* exception of instruction brake
/* INTE instruction
*/
*/
#pragma intvect
#pragma intvect
_cpe_int
_cpn_int
8
7
/* coprocessor error trap
*/
/* coprocessor absence exception */
#pragma defvect
_Dummy_int
218
/* Dummy routine
*/
}
Fixed comments.
Chapter 20 Interrupt Control
9.Caution
9. Caution
The following is the points you should know when using interrupts.
Interrupt request flags are not cleared automatically. Make sure to clear them in the interrupt process.
(They are usually cleared by writing “0” to the bit of the interrupt request flag, however, there are some exceptions
depending on the type of peripheral functions. See the chapter for the corresponding peripheral function.)
219
Chapter 20 Interrupt Control
9.Caution
220
Chapter 21 External Interrupt
1.Overview
Chapter 21 External Interrupt
1. Overview
External interrupt detects a signal input to an external interrupt input pin, and generates an interrupt request.
Pins
Edge
detection
circuit
Interrupt requests
2. Features
• Quantity
: 16 (INT input -- 16 channels: INT0-INT15)
• Interrupt levels: 4 levels
• “L” level
• “H” level
• Rising edge
• Falling edge
221
Chapter 21 External Interrupt
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
External interrupts 0 - 7
Detect level setting
External interrupt request enable flag
LB0,
LB1,
LB2,
LB3,
LB4,
LB5,
LB6,
LB7,
LA0
LA1
LA2
LA3
LA4
LA5
LA6
LA7
ELVR0 : bit 1-0,
ELVR0 : bit 3-2,
ELVR0 : bit 5-4,
ELVR0 : bit 7-6,
ELVR0 : bit 9-8,
ELVR0 : bit 11-10,
ELVR0 : bit 13-12,
ELVR0 : bit 15-14,
External interrupt request flag
INT0/P10
INT1/P11
INT2/P12
INT3/P13
INT4/P14
INT5/P15
INT6/P16
INT7/P17
0
0
Detect at “L” level
0
1
1
0
Detect at “H” level
Detect at the rising edge
1
1
Detect at the falling edge
ER0,
ER1,
ER2,
ER3,
ER4,
ER5,
ER6,
ER7
Pins
Edge detection circuit
0
1
EIRR0: bit
EIRR0: bit
EIRR0: bit
EIRR0: bit
EIRR0: bit
EIRR0: bit
EIRR0: bit
EIRR0: bit
n0
n1
n2
n3
n4
n5
n6
n7
EN0,
EN1,
EN2,
EN3,
EN4,
EN5,
EN6,
EN7
0
ENIR0 : bit
ENIR0 : bit
ENIR0 : bit
ENIR0 : bit
ENIR0 : bit
ENIR0 : bit
ENIR0 : bit
ENIR0 : bit
0
1
2
3
4
5
6
7
Disable interrupts
1
Enable interrupts
0
No interrupt requests
1
Interrupt request present
Interrupt request
(#16, #17, #18, #19,
#20, #21, #22, #23)
WRITE 0: Flag clear
Read of the port
From the port data register
Register number
P10, DDR1: bit0,
P11, DDR1: bit1,
P12, DDR1: bit2,
P13, DDR1: bit3,
P14, DDR1: bit4,
P15, DDR1: bit5,
P16, DDR1: bit6,
P17 DDR1: bit7
Input only
0
1 Enable output
222
External
interrupt
External interrupt
request level
setting bit
0
1
LB0, LB0
LB1, LB1
LB2, LB2
LB3, LB3
LB4, LB4
LB5, LB5
LB6, LB6
LB7, LB7
2
3
4
5
6
7
External Enable external Interrupt
interrupt
interrupt
number
request bit
requests
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7
EN0
EN1
EN2
EN3
EN0
EN1
EN2
EN3
#16
#17
#18
#19
#20
#21
#22
#23
The data
direction bit
Pins
P10
P11
P12
P13
P14
P15
P16
P17
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
Chapter 21 External Interrupt
3.Configuration
Figure 3-2 Configuration Diagram
External interrupts 8 - 15
Detect level setting
LB8, LA8
LB9, LA9
LB10, LA10
LB11, LA11
LB12, LA12
LB13, LA13
LB14, LA14
LB15, LA15
External interrupt request enable flag
ELVR1 : bit 1-0,
ELVR1 : bit 3-2,
ELVR1 : bit 5-4,
ELVR1 : bit 7-6,
ELVR1 : bit 9-8,
ELVR1 : bit 11-10,
ELVR1 : bit 13-12,
ELVR1 : bit 15-14
External interrupt request flag
0
0
Detect at “L” level
0
1
1
0
Detect at “H” level
Detect at the rising edge
1
1
Detect at the falling edge
INT8/P50
INT9/P51
Pins
INT10P52
INT11/P53/PPG4
INT12/P54/PPG5
INT13/P55/TIN2
INT14/P56/TIN1
INT15/P57/TIN0/ADTG0
ER0,
ER1,
ER2,
ER3,
ER4,
ER5,
ER6,
ER7
Edge detection circuit
0
1
(Inputs of other peripheral
function macros)
EIRR1: bit
EIRR1: bit
EIRR1: bit
EIRR1: bit
EIRR1: bit
EIRR1: bit
EIRR1: bit
EIRR1: bit
n0
n1
n2
n3
n4
n5
n6
n7
EN0,
EN1,
EN2,
EN3,
EN4,
EN5,
EN6,
EN7
ENIR1 : bit
ENIR1 : bit
ENIR1 : bit
ENIR1 : bit
ENIR1 : bit
ENIR1 : bit
ENIR1 : bit
ENIR1 : bit
0
1
2
3
4
5
6
7
0
Disable interrupts
1
Enable interrupts
Interrupt request
(#37, #38, #39, #40
#41, #42, #43, #44)
No interrupt requests
Interrupt request present
WRITE 0: Flag clear
Read of the port
1
(Outputs of other peripheral function macros)
From the port data register
Register number
0
PPG4 PFR5: bit3
PPG5 PFR5: bit4
0 General-purpose port
OP0
1
P50, DDR5: bit0,
P51, DDR5: bit1,
P52, DDR5: bit2,
P53, DDR5: bit3,
P54, DDR5: bit4,
P55, DDR5: bit5,
P56, DDR5: bit6,
P57 DDR5: bit7
Input only
0
1 Enable output
External
interrupt
External interrupt
request level
setting bit
8
9
LB8, LB8
LB9, LB9
LB10, LB10
LB11, LB11
LB12, LB12
LB13, LB13
LB14, LB14
LB15, LB15
10
11
12
13
14
15
External Enable external Interrupt
interrupt
interrupt
number
request bit
requests
ER8
ER9
ER10
ER11
ER12
ER13
ER14
ER15
EN8
EN9
EN10
EN11
EN12
EN13
EN14
EN15
#37
#38
#39
#40
#41
#42
#43
#44
The data
direction bit
P50
P51
P52
P53
P54
P55
P56
P57
Port
function
PPG4
PPG5
Pins
INT8
INT9
INT10
INT11
INT12
INT13
INT14
INT15
Figure 3-3 Register List
223
Chapter 21 External Interrupt
3.Configuration
Figure 3-4 Register List
Note: See “Chapter 20 Interrupt Control (Page No.207)” about ICR register and interrupt vectors.
224
Chapter 21 External Interrupt
4.Registers
4. Registers
4.1 ELVR: Interrupt Eequest Level Register
The register that selects request detection of external interrupts.
• ELVR0 (INT0-INT7): Address 042H (access: Half-word, Word)
15
14
13
12
11
10
9
8
Bit
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
7
6
5
4
3
2
1
0
Bit
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
Bit
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• ELVR1 (INT8-INT15): Address 0D2H (access: Half-word, Word)
15
14
13
12
11
10
9
8
LB15
LA15
LB14
LA14
LB13
LA13
LB12
LA12
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
7
6
5
4
3
2
1
0
Bit
LB11
LA11
LB10
LA10
LB9
LA9
LB8
LA8
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
Interrupt request level bits (LBn, LAn) are registers that select request detection.
2 bits (LBn, LAn) are assigned to each external interrupt INTn.
LBn
0
0
1
1
LAn
0
1
0
1
Description
Detect “L” level and generate an interrupt request.
Detect “H” level and generate an interrupt request.
Detect the rise and generate an interrupt request.
Detect the fall and generate an interrupt request.
When the request input is a level (LAn, LBn = “00” or “01”), and when the INTn pin input is the valid level, the
corresponding bit (ERn) will be re-set to “1” even if the external interrupt request bit (ERn) is set to “0”.
When you use an external interrupt to return from the stop status, make sure to set it as a level (LAn, LBn = “00” or
“01”).
Note: n = 0 to 15
225
Chapter 21 External Interrupt
4.Registers
4.2 EIRR: Interrupt Request Register
Status bit of a request of an external interrupt.
• EIRR0 (INT0-INT7): Address 040H (access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
0
0
0
0
0
R (RM1), W
0
R (RM1), W
Initial value
Attribute
Bit
0
0
R (RM1), W
R (RM1), W
R (RM1), W R (RM1), W
R (RM1), W R (RM1), W
Bit
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• EIRR1 (INT8-INT15): Address 0D0H (access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
ER15
ER14
ER13
ER12
ER11
ER10
ER9
ER8
0
0
0
0
0
0
R (RM1), W
R (RM1), W
R (RM1), W
R (RM1), W
R (RM1), W
R (RM1), W
0
0
R (RM1), W R (RM1), W
Initial value
Attribute
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
An external interrupt request bit (ERn) indicates the corresponding external interrupt request.
Description
ERn
Read value
No external interrupt request present
External interrupt request present
0
1
Write value
Clear external interrupt factor bits
No effect on operation
Note: n = 0 to 15
4.3 ENIR: Interrupt Request Enable Register
Enable bit of external interrupt requests.
• ENIR0 (INT0-INT7): Address 041H (access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
Bit
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
Bit
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• ENIR1 (INT8-INT15): Address 0D1H (access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
EN15
EN14
EN13
EN12
EN11
EN10
EN9
EN8
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
An external interrupt request enable bit (ENn) enables the corresponding external interrupt request.
ERn
0
1
Note: n = 0 to 15
226
Description
External interrupt request output disable
External interrupt request output enable
Chapter 21 External Interrupt
5.Operation
5. Operation
Level detection
(2)
(1)
INT (“H”)
(“L”)
(1)
(2)
(3)
Valid edge
Clear by software
(4)
Interrupt request (ER)
(5)
Edge detection
Internal clock
(CLKP divided by two)
(2)
INT (rising)
(fallling)
Required to maintain the level more than
before and after the edge (3 x CLKP)
(1)
(1)
(2)
Valid edge
(3)
Interrupt requests (ER)
(4)
Clear by software
(5)
(1) External interrupt signal (INT) input
(2) Detect interrupt signals (level/edge).
(3) Valid edge signal (3xCLKP above required)
(4) An interrupt request generated.
(5) The interrupt request is cleared with software.
227
Chapter 21 External Interrupt
6.Setting
6. Setting
Table 6-1 Setting Required in Order to Use External Interrupts
Setting
Setting
Procedures*
Setting Registers
External interrupt request level setting register
(ELVR0 - ELVR1)
Data direction register (DDR1, DDR5)
Port function register (PFR5)
External inputs
→Inputs the signal to INT0 - INT15 pins.
Setting of detect level
Set INT pin as the input.
External interrupt
See 7.1
See 7.2
–
Note: For the setting procedure, refer to the section indicated by the number.
7. Q & A
7.1 What are the types and setting procedures of detect levels?
There are 4 types of detect levels: “L” level, “H” level, rise, and fall
Carry out in Detection level bit (ELVR0. LBx, LAx) x = 0-7, and (ELVR1. LBx, LAx) x = 8-15.
Operation mode
Use as “L” level detection
Use as “H” level detection
Use as rise detection
Use as fall detection
Detection level bit (LBn, LAn) n = 0-15
Sets to “00”
Sets to “01”
Sets to “10”
Sets to “11”
7.2 How do I set INT pin as the input?
Use data direction registers (0DDR1, DDR5).
Use port function register (PFR5).
228
Operation
Direction bits (P10P17), (P50-P57)
Setting
To use INT0 pin input
To use INT1 pin input
To use INT2 pin input
To use INT3 pin input
To use INT4 pin input
To use INT5 pin input
To use INT6 pin input
To use INT7 pin input
To use INT8 pin input
To use INT9 pin input
To use INT10 pin input
To use INT11 pin input
To use INT12 pin input
To use INT13 pin input
To use INT14 pin input
To use INT15 pin input
DDR1. P10
DDR1. P11
DDR1. P12
DDR1. P13
DDR1. P14
DDR1. P15
DDR1. P16
DDR1. P17
DDR5. P50
DDR5. P51
DDR5. P52
DDR5. P53
DDR5. P54
DDR5. P55
DDR5. P56
DDR5. P57
Sets to “0”
Sets to “0”
Sets to “0”
Sets to “0”
Sets to “0”
Sets to “0”
Sets to “0”
Sets to “0”
Sets to “0”
Sets to “0”
Sets to “0”
Sets to “0”
Sets to “0”
Sets to “0”
Sets to “0”
Sets to “0”
Function bit
(PPG4),
(PPG5)
---------------------------------PFR5.PPG4
PFR5.PPG5
----------
Setting
---------------------------------Sets to “0”
Sets to “0”
----------
Chapter 21 External Interrupt
7.Q & A
7.3 What interrupt registers are used?
Setting of interrupt vectors of external interrupts, and interrupt levels
The relationship among external interrupt numbers, interrupt levels, and vectors is shown in the table below.
See “Chapter 20 Interrupt Control (Page No.207)” about the details of interrupt levels and interrupt vectors.
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
INT10
INT11
INT12
INT13
INT14
INT15
Interrupt vectors (default)
#16
Address: 0FFFBCh
#17
Address: 0FFFB8h
#18
Address: 0FFFB4h
#19
Address: 0FFFB0h
#20
Address: 0FFFACh
#21
Address: 0FFFA8h
#22
Address: 0FFFA4h
#23
Address: 0FFFA0h
#37
Address: 0FFF68h
#38
Address: 0FFF64h
#39
0FFF60h
#40
Address: 0FFF5Ch
#41
Address: 0FFF58h
#42
Address: 0FFF54h
#43
Address: 0FFF50h
#44
Address: 0FFF4Ch
Interrupt level setting bits (ICR[4:0])
Interrupt level register (ICR00)
Address: 00440h
Interrupt level register (ICR01)
Address: 00441h
Interrupt level register (ICR02)
Address: 00442h
Interrupt level register (ICR03)
Address: 00443h
Interrupt level register (ICR04)
Address: 00444h
Interrupt level register (ICR05)
Address: 00445h
Interrupt level register (ICR06)
Address: 00446h
Interrupt level register (ICR07)
Address: 00447h
Interrupt level register (ICR21)
Address: 00455h
Interrupt level register (ICR22)
Address: 00456h
Interrupt level register (ICR23)
Address: 00457h
Interrupt level register (ICR24)
Address: 00458h
Interrupt level register (ICR25)
Address: 00459h
Interrupt level register (ICR26)
Address: 0045Ah
Interrupt level register (ICR27)
Address: 0045Bh
Interrupt level register (ICR28)
Address: 0045Ch
7.4 Interrupt types
Interrupt causes are limited to external interrupts. There is no bit for selection.
229
Chapter 21 External Interrupt
8.Sample Programs
7.5 How do I enable, disable, and clear interrupts?
Enable flag for interrupt requests, interrupt request flag
Use interrupt enabling bits (ENIR0.ENx. x = 0-7) and (ENIR1.ENx. x = 8-15) to enable interrupts.
Interrupt enabling bit (En [n = 0-15])
Sets to “0”
Sets to “1”
To disable interrupt requests
To enable interrupt requests
Use interrupt request bits (EIRR0.ERx. x = 0-7) and (EIRR1.ERx. x = 8-15) to clear interrupt requests.
Interrupt request bit (Ern [n = 0-15])
Writes “0”
To clear interrupt requests
8. Sample Programs
Setting Procedure Example 1
Program Example 1
Generate an external interrupt at the rising edge of the signal from INT0.
void EX_INT_sample_1()
{
EX_INT0_initial();
}
<Initial settings>
void EX_INT0_initial(void)
(1) • Port
Input selection at INT0 port
(2) • INT0 Control
Selection of external interrupt detection
(3) • Interrupt settings 1
Setting of INT0 interrupt level
I flag setting
(4) • Interrupt settings 2
Enable INT0 interrupts
<register name>. <bit
name>
DDR0 . P10
{
IO_DDR1= 0x01;
/* INT0 only. INT0 input */
<register name>. <bit
name>
ELVR0
LB7,LA7 - LB1,LB1
.LB0, LA0
IO_ELVR0.hword= 0x0001;
/* Value: 00000001 (bit) */
/* Bit7-2= “000000” */
/* Bit1-0= “01” H level detection */
ICR19
(CCR)
IO_ICR[00].bit.ICR = 20;
__EI();
/* The values are arbitrary. */
/* Enable interrupts. */
EIRR0. ER0
ENIR0. EN0
IO_EIRR0.bit.ER0= 0;
IO_ENIR0.bit.EN0= 0;
/* ER0 Clear interrupt flag */
/* EN0 Enable interrupts. */
}
<Interrupt>
• Read conversion value
Clears interrupt request flags
• User processing
__interrupt void INT0_int()
<register name>. <bit
name>
EIRR0. ER0
/*
*/
{
IO_EIRR0.bit.ER0= 0;
/* ER0 Clear interrupt flag */
}
<Interrupt vector>
Setting the vector table
The interrupt routine must be specified in the vector table.
#pragma intvect INT0_int 16
Caution: Clock setup and setting of the level of running programs “__set_il”
(value) must have been performed beforehand.
Note: For the convention of registers, see “FRLite Family MB91230 Series Sample I/O
Register File Usage Guide”.
230
Chapter 21 External Interrupt
9.Caution
9. Caution
The following is the points to note when you use external interrupts.
• When the request input is a level (LAn, LBn = “00” or “01”), and when the INT pin input is the valid level, the
corresponding bit (ERn) will be re-set to “1” even if the external interrupt request bit (ERn) is set to “0.”
Note: n = 0 to 15
• When you use an external interrupt to return from the stop status, make sure to set interrupt request level bit to “level”
(LAn, LBn = “00” or “01”).
Note: n = 0 to 15
• An edge request will not trigger the return from the stop status.
• Before going into standby, make sure to disable unused external interrupts (ENn = “0”).
Note: n = 0 - 15
• Minimum 3CLKP (peripheral clock) is required for the pulse width to detect the edge presence when the request level
is set to the edge request.
• The interrupt request to the interrupt controller remains active even if an external interrupt request is input from the
external interrupt pin INTn and canceled afterward, since the interrupt request flag (ERn) is present. To cancel the
interrupt request to the interrupt controller, the interrupt request flag must be cleared (ERn = “0”) with software. (See
the diagram in “5. Operation (Page No.227)”)
Note: n = 0 to 15
231
Chapter 21 External Interrupt
9.Caution
232
Chapter 22 U-timer
1.Overview
Chapter 22 U-timer
1. Overview
U-timer is a timer to generate the baud rate of UART.
Any baud rate can be set by the combination of the chip operating frequency and the U-timer reload value.
Reload value
Peripheral clock
(CLKP)
Down counter
Underflow
Latch
UART
2. Features
•
•
•
•
•
•
Timer
: 16-bit reload timer
Quantity
: 4 (paired with UART)
Operation mode: asynchronous mode/synchronous mode (based on the setting of UART)
Operation clock : Peripheral clock (CLKP)
Count format : 2n + 2, 2n + 3
Baud rate
: Synchronous mode FCLKP/(2n+2), FCLKP/(2n+3)
Asynchronous mode F CLKP/{(2n+2) × 16}, FCLKP/{(2n+3) × 16}
• Possible to stop operation (valid at sleep)
233
Chapter 22 U-timer
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
U-timer 0 - 3
Register number
Reload
register
UTMR0
UTMR1
UTMR2
UTMR3
U-timer
0
1
2
3
Reload register (write only)
Down counter
(U-timer)
UTIM0
UTIM1
UTIM2
UTIM3
U-timer
control
UTIMC0
UTIMC1
UTIMC2
UTIMC3
UART
UART 0
UART 1
UART 2
UART 3
UTIMER n
Load
UT ST UT IMC: bit 1
0
Stop counting
1
Start counting
Reload control
Reload
Activation
Underflow
Peripheral clock
(CLKP)
UCC1
UT IMC: bit 7
0
2 (n+1) period
1
2 (n+1) + 1 period
Control circuit
(+1)
UTIM
Reverse
Latch
(n+1 )
Down counter
Clear
UT CR UT IMC: bit 0
0 Clears the timer
1
Disabled
UNDR UT IMC: bit 3
No underflow
1 Underflow present
WRITE 0: Flag clear
Figure 3-2 Register List
234
2n+2
or
2n+3
UART 0-UART3
for both transmit
and receive
Chapter 22 U-timer
4.Registers
4. Registers
4.1 UTIM: U-timer Register
Register to read the count value of the timer (UTIM).
• UTIM0 (U-timer 0): address 064h (access: Half-word)
• UTIM1 (U-timer 1): address 06Ch (access: Half-word)
• UTIM2 (U-timer 2): address 074h (access: Half-word)
• UTIM3 (U-timer 3): address 0C4h (access: Half-word)
15
b15
0
R/WX
14
B14
0
R/WX
13
b13
0
R/WX
12
b12
0
R/WX
11
b11
0
R/WX
10
b10
0
R/WX
9
b9
0
R/WX
8
b8
0
R/WX
7
b7
0
R/WX
6
b6
0
R/WX
5
b5
0
R/WX
4
b4
0
R/WX
3
b3
0
R/WX
2
b2
0
R/WX
1
b1
0
R/WX
0
b0
0
R/WX
bit
Initial value
Attribute
bit
Initial value
Attribute
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
You can acquire the count value of the timer by reading the U-timer register.
4.2 UTIMER: Reload Register
Register for setting up the reload value (UTIMER) of the timer.
• UTIMER0 (U-timer 0): address 064h (access: Half-word)
• UTIMER1 (U-timer 1): address 06Ch (access: Half-word)
• UTIMER2 (U-timer 2): address 074h (access: Half-word)
• UTIMER3 (U-timer 3): address 0C4h (access: Half-word)
15
b15
0
RX/W
14
b14
0
RX/W
13
b13
0
RX/W
12
b12
0
RX/W
11
b11
0
RX/W
10
b10
0
RX/W
9
b9
0
RX/W
8
b8
0
RX/W
7
b7
0
RX/W
6
b6
0
RX/W
5
b5
0
RX/W
4
b4
0
RX/W
3
b3
0
RX/W
2
b2
0
RX/W
1
b1
0
RX/W
0
b0
0
RX/W
bit
Initial value
Attribute
bit
Initial value
Attribute
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• When you write to the reload register, you can set up the reload value of the timer.
• When the write to the reload register and the reload operation occur simultaneously, the counter loads the value before
the write takes place.
235
Chapter 22 U-timer
4.Registers
4.3 UTIMC: U-timer Control Register
Register for controlling the operation of the U-timer.
• UTIMC0 (U-timer 0): address 067h (access: Byte)
• UTIMC1 (U-timer 1): address 06Fh (access: Byte)
• UTIMC2 (U-timer 2): address 077h (access: Byte)
• UTIMC3 (U-timer 3): address 0C7h (access: Byte)
7
UCC1
0
R/W
6
–
–
RX/WX
5
–
–
RX/WX
4
Reserved
0
R0/W0
3
UNDR
0
R (RM1), W
2
Reserved
0
R0/W0
1
UTST
0
R/W
0
UTCR
1
R1,W
bit
Initial value
Attribute
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit7: Count control
UCC1
0
1
Operation
Normal operation (output clock period to UART = 2n + 2)
+1 mode (output clock period to UART = 2n + 3)
n: U-timer register value
• bit 6-5: Undefined
• Writing does not affect the operation.
• The read value is indeterminate.
• bit4: Reserved Always write “0”. The read value is “0”.
• bit3: Underflow flag
UNDR
0
1
Status
Read
No underflow of the U-timer
Underflow of the U-timer present
Write
Clears the flag
No effect on operation
• When the timing of the flag is set to “1” by the underflow and the write of “0” is simultaneous, the flag is set to “1.”
(Setting the flag has priority)
• bit2: Reserved. Always write “0”. The read value is “0”.
• bit1: Operation enable
UTST
0
1
Operation
Disabling the U-timer
Enabling the U-timer (Start counting)
• When the operation enable bit is “0”, setting “1” reloads the value of the U-timer register to the counter, and starts
counting. When “0” write to the clear bit (UTCR) is simultaneously performed at this time, the counter is cleared,
and an underflow flag is set at the following timing.
• bit0: Clear
UTCR
0
1
Operation
Clear the U-timer
No effect on operation.
• The counter will be cleared to “0000h” when “0” is written to the clear bit.
• Do not write “1” to the clear bit when the U-timer is working.
236
Chapter 22 U-timer
4.Registers
• When write “0” operation to the clear bit (counter clear) and the reload operation of the counter occur
simultaneously, the counter is cleared. (Counter clear has priority)
237
Chapter 22 U-timer
5.Operation
5. Operation
The operation of the U-timer is explained below.
5.1 Operations: In the case of (2n+2):
(1)
UTIMER
Reload data
(3) [Set value of the reload register + 1]
(7)
counts
Count clock
(= CLKP)
(5) Start the count
Load
data
UTIM
(down counter)
UTST bit
Data load
-1
0000
-1
0000
Reload
data
-1
(2)
(3)
(7)
(6)
Underflow
The signals
to UART
Reload
data
(4)
Toggle output
(8)
Synchronous mode: 1 bit
Asynchronous mode: 1/16 bit
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Set reload value in reload register.
Enable
Load the reload value
Start TOT toggle output
Down count of the counter
Underflow generation
Reload the reload value
Reverse of the output level (toggle output)
Repeat operations from (5) to (7).
(See “9. Caution (Page No.242)”.)
5.2 Formula of the clock rate
■ Period (when UCC1= 0) = {Reload value (UTIMER) + 1} × count clock (CLKP) x 2
Example 1. Synchronous mode: (1666 + 1) × 31.25 ns × 2 = 104.18 µ s (9598 bps)
Example 2. Asynchronous mode: (103 + 1) × 31.25 ns × 2 × 16 = 104 µ s (9615 bps)
• If UCC1= 1, the count increments by one for every period.
• When UART is asynchronous, the time divided by 16 is the transfer time for 1 bit.
■ When shown in baud rate (bps):
Asynchronous mode, when UCC1 = 0: bps = FCLKP/ {(2 x reload value + 2) × 16}
when UCC1 = 1: bps = FCLKP/ {(2 × reload value +3) × 16}
Synchronous mode, when UCC1 = 0: bps = FCLKP/ (2 × reload value + 2)
when UCC1 = 1: bps = FCLKP/ (2 × reload value +3)
238
Chapter 22 U-timer
6.Setting
5.3 Operation after reset release
The U-timer stops counting.
6. Setting
Table 6-1 Setting Required to Operate the U-timer (Internal Clock Operation)
Setting
Setting Registers
Setting the reload value
Count control bit
Enable
Reload register (UTIMER0 - UTIMER3)
U-timer control register (UTIMC0 - UTIMC3)
Setting
Procedures *
See 7.1
See 7.3
See 7.4
*: For the setting procedure, refer to the section indicated by the number.
Table 6-2 Setting Required to Stop the U-timer
Setting
Setting Registers
Setting of the U-timer stop bit
U-timer control register (UTIMC0 - UTIMC3)
Setting
Procedures *
See 7.5
For the setting procedure, refer to the section indicated by the number.
7. Q & A
7.1 How do I set (rewrite) a reload value?
The reload value is set to the reload register (UTIMER0 - UTIMR3).
Below is the formula for the value to be set.
• Formula
UTIMER register value = {reload interval / count clock} - 1
• Allowed range
UTIMER register value = 0 - FFFFh (65535)
Table 7-1 Example of set value (synchronous mode)
Ideal rate
2n + 2
2n + 3
Synchronous: When CLKP =
32MHz
Actual rate [bps]
1220800
610400
n = 12
n = 25
---
1230769
615384
0.81
0.81
305200
152600
-n=104
n = 51
--
304761
152380
0.14
0.14
n=415
76923 / 76738
38369 / 38415
0.16/0.08
0.08/0.03
n=1665
19207 / 19184
9598.0 / 9600.9
0.03/0.08
0.02/0.01
Setting value
76800
38400
19200
9600
n=207
n=416
n=832
n=1666
Error [%]
Note: This error does not include the error of the clock oscillator or PLL oscillation.
239
Chapter 22 U-timer
7.Q & A
Table 7-2 Example of set value (asynchronous mode)
Ideal rate
2n + 2
2n + 3
Asynchronous: When CLKP =
32MHz
Actual rate [bps]
152600
76800
-n = 12
n=5
--
153846
76923
0.81
0.16
38400
19200
n = 25
n = 51
---
38461
19230
0.16
0.16
9600
4800
n = 103
-n = 207
9615
4807 / 4819
0.15
0.16/0.08
2400
1200
n=416
2398 / 2400.9
1201 / 1199
0.07/0.04
0.016/0.019
Setting value
n=415
n=832
Error [%]
Note: This error does not include the error of the clock oscillator or PLL oscillation.
7.2 What are the types of count clock?
The count clock is the peripheral clock (CLKP) only.
7.3 What are operation modes?
There are two methods of counting with the following settings.
Use count control bits (UTIMC0.UUC1) - (UTIMIC3.UUC1).
Operation
To use 2n+2 count:
To use 2n+3 count:
Count control bit (UUC1)
Sets to “0”
Set to “1”
7.4 How do I enable / disable the count operation of the U-timer?
Use operation enable bits (UTIMC0.UTST) - (UTIMIC3.UTST).
Control details
To disable the U-timer:
To enable (start) the count operation of the U-timer:
Operation enable bit (UTST)
Sets to “0”
Set to “1”
When you enable the counter while in the idle state, it loads the value of the reload register and starts the down count.
When you enable the counter while it is counting, the counter simply continues counting.
7.5 How do I initialize the U-timer?
Stop the U-timer, and clear bits (UTIMC0.UTCR) - (UTIMC3.UTCR).
Do not clear it while counting.
240
Chapter 22 U-timer
8.Sample Programs
8. Sample Programs
241
Chapter 22 U-timer
9.Caution
9. Caution
• When you start the U-timer from the idle status (UTST=“1”), it automatically reloads the reload value UTIMER to the
counter.
• When you set the clear bit (UTCR=“0”) while counting, the counter is cleared to “0”. In this case, a hazard may be
outputted to the output waveform and the upper-side U-TIMER may malfunction. For this reason, do not perform the
initialization by the clear bit while counting.
• When you set the clear bit (UTCR=“0”) and the start bit (UTST=“1”) simultaneously from the U-timer idle status, the
counter will be cleared to “0” and an underflow will be generated at the next countdown.
With this underflow, the underflow flag (UNDR) is set to “1”, and the internal baud rate clock becomes "H" level at the
same time.
• If the underflow flag (UNDR) is set to “1” and the underflow flag (UNDR) is set to “0” by software at the same time,
the former operation (UNDR=“1”) has priority and the clear request is ignored.
• When the writing of the new reload value to the reload registers (UTIMER0-UTIMER3) and the reloading to the
counter occur simultaneously, the old reload value is loaded to the counter, and the reloading of the new reload value
will be done at the next reload.
• When the timer clearing (UTCR=“0”) and the timer count / reload occur simultaneously, the former has priority.
• The initial value of the reload register (UTIMER0-UTIMER3) is “0000 0000h”. Since this value is write-only, you
cannot read and confirm the reload register.
• The reload register and the counter are located at the same address. The reading operation accesses the reload register
(UTIM0-UTIM3), and the writing operation accesses the U-timer (UTIMER0-UTIMER3).
• When you need to stop the count of the U-timer (UTST=“0”), do so after the transmit/receive operation of UART is
completed. However, since the completion of the transmit operation cannot be determined from the transmit buffer
empty flag (SODR=“1”), we recommend you to allow sufficient time before stopping the U-timer, or use it without
stopping except at the low-power mode.
242
Chapter 23 UART
1.Overview
Chapter 23 UART
1. Overview
UART is a serial communication interface for asynchronous communications (start-stop synchronization) and clock
synchronous communications.
Transmit buffer
Operation clock
(U-timer or external)
Transmit shifter
Pins
Receive shifter
Pins
Receive buffer
2. Features
Operation mode: Select one from the following three modes:
• Mode 0: Asynchronous - normal mode
• Mode 1: Asynchronous - multiprocessor mode
• Mode 2: Synchronous mode
7-8 bits
Mode 0
0
1 1
Stop
Start
7-8 bits
1
0
Parity
Start
Stop
8 bits
Mode 1
1
A/D Stop
0
Start
Mode 2
8 bits
Quantity : 4 (input: four channels - SIN0, SIN1, SIN2, and SIN3)
(output: four channels - SOT0, SOT1, SOTN2, and SOT3)
Mode : signal format: NRZ (Non Return to Zero)
With full-duplex double buffer
Generation of the baud rate: fully programmable transfer rate setting
• Any baud rates can be set using the U-timer.
• The transfer rate can be set by the external clock.
Error status:
• Parity error
• Framing error
• Overrun error
Interrupt:
• Interrupt by transmit buffer empty
243
Chapter 23 UART
3.Configuration
• Interrupt due to the completion of receive or an error
• Eight independent interrupt processes (four UART × 2 (transmit, receive))
3. Configuration
Figure 3-1 Block Diagram (Mode 0)
UART 0 - 3 (mode 0, asynchronous receive)
MD1
SMR: bi t 7
0 Asynchronous mode
MD0
0
Operation mode
S MR:: bit 6
Normal mode
SCKE
SMR: bit 1
0
(Initial value)
1
Disabled
RXE SCR: bit 1
0 Disable receives
1 Enable receives
CL
SCR: bit 4
0
7-bit data
1
8-bit data
BDS SSR: bit 2
0 Transmit from LSB
1 Transmit from MSB
SBL
SCR: bit 5
0
1 stop bit
1
2 stop bit
* The clock is the same at
receive and transmit.
Clock
(U-TIMER)
SCK0/P02
SCK1/P05
SCK2/P26
SCK3/P31
SCK0 PFR0: bit 2
SCK1 PFR0: bit 5
SCK2 PFR2: bit 6
SCK3 PFR3: bit 1
0 General-purpose output
1 Operation clock output
P
0
1
Error detection
Clear error flags
REC
SCR: bit 2
0 Clear PE, ORE, and FRE
1
Disabled
PE
SSR: bit 7
0 No parity error
1 Parity error(s) present
SCR: bit 6
Even parity
Odd parity
ORE
SSR: bit 6
0 No overrun error
1 Overrun error present
FRE
SSR: bit 5
0 No framing error
1 Framing error present
CS0 SMR: bit 1
0
U-timer
1 External clock
0
Operation
Clock (F)
Control circuit and Receive
state judging circuit
1
Read of the port
1
(Operation clock)
From the port data
register
0
P02
P05
P26
P31
0
1
SCKE
SMR: bit 5,4
0
Disabled
1 Only 1 can be written.
SCKE
SMR: bit 2,0
0 Only 0 can be written.
1
Disabled
244
PEN SCR: bit 7
0
No parity
1
With parity
RIE
SSR: bit 1
0 Disable interrupts
1 Enable interrupts
Receive shifter
0
DDR0: bit 2
DDR0: bit 5
DDR2: bit 6
DDR3: bit 1
Input
Output
SIN0/P00
SIN1/P03
SIN2/P24
SIN3/P27
Shift clock
(F/16)
Register full
Receive data register
RDRF
SIDR
0
1
Read of the port
SSR: bit 4
Can read
(receive completed)
From the port data register
P00
P03
P24
P27
0
1
DDR0: bit 0
DDR0: bit 3
DDR2: bit 4
DDR2: bit 7
Input
Output
OR
1
Cannot read
(not received or
still receiving)
Register number
UART0 receive interrupt (#27)
UART1 receive interrupt (#29)
UART2 receive interrupt (#31)
UART3 receive interrupt (#33)
UART
Mode
Serial
control
Input
Output
Status
Internal
clock
Pins
0
1
2
3
SMR0
SMR1
SMR2
SMR3
SCR0
SCR1
SCR2
SCR3
SIDR0
SIDR1
SIDR2
SIDR3
SODR0
SODR1
SODR2
SODR3
SSR0
SSR1
SSR2
SSR3
U-timer0
U-timer1
U-timer2
U
U-timer3
U
SIN0, SOT0, SCK0
SIN1, SOT1, SCK1
SIN2, SOT2, SCK2
SIN3, SOT3, SCK3
Chapter 23 UART
3.Configuration
Figure 3-2 Block Diagram (Mode 0)
UART0 - 3 (Mode 0, asynchronous transmit)
MD1
SMR: bi t 7
0 Asynchronous mode
Operation mode
MD0
0
S MR:: bit 6
Normal mode
SCKE
SMR: bit 1
0
(Initial value)
1
Disabled
* The clock is the same at
receive and transmit.
Clock
(U-TIMER)
SCK0/P02
SCK1/P05
SCK2/P26
SCK3/P31
SCK0 PFR0: bit 2
SCK1 PFR0: bit 5
SCK2 PFR2: bit 6
SCK3 PFR3: bit 1
0 General-purpose output
1 Operation clock output
TXE SCR: bit 0
0 Disable transmits
1 Enable transmits
CL
SCR: bit 4
0
7-bit data
1
8-bit data
PEN SCR: bit 7
0
No parity
1
With parity
BDS SSR: bit 2
0 Transmit from LSB
1 Transmit from MSB
SBL
SCR: bit 5
0
1 stop bit
1
2 stop bit
0
1
P
SCR: bit 6
Even parity
Odd parity
CS0 SMR: bit 1
0
U-timer
1 External clock
0
Operation
clock (F)
Control circuit
Read of the port
1
Read of the port
P02
P05
P26
P31
0
1
1
(Operation clock)
0
From the port
data register
DDR0: bit 2
DDR0: bit 5
DDR2: bit 6
DDR3: bit 1
Input
Output
Shift clock
(F/16)
Transmit shifter
1
Transmit data register
SIDR
SCKE
SMR: bit 5,4
0
Disabled
1 Only 1 can be written.
SCKE
SMR: bit 2,0
0 Only 0 can be written.
1
Disabled
0
From the port
data register
TIE
SSR: bit 0
0 Disable interrupts
1 Enable interrupts
Register empty
0
TDRE
SSR: bit 3
0 Disable the write to SODR
1 Enable the write to SODR
1
SOT0 PFR0: bit 1
SOT1 PFR0: bit 4
SOT2 PFR2: bit 5
SOT3 PFR3: bit 0
0 General-purpose port output
1
UART output
SOT0/P01
SOT1/P04
SOT2/P25
SOT3/P30
* Write only
UART0 transmit interrupt (#28)
UART1 transmit interrupt (#30)
UART2 transmit interrupt (#32)
UART3 transmit interrupt (#34)
Register number
UART
Mode
0
1
2
3
SMR0
SMR1
SMR2
SMR3
Serial
control
SCR0
SCR1
SCR2
SCR3
Input
Output
Status
SIDR0
SIDR1
SIDR2
SIDR3
SODR0
SODR1
SODR2
SODR3
SSR0
SSR1
SSR2
SSR3
Internal
clock
U-timer0
U-timer1
U-timer2
U-timer3
Pins
SIN0, SOT0, SCK0
SIN1, SOT1, SCK1
SIN2, SOT2, SCK2
SIN3, SOT3, SCK3
245
Chapter 23 UART
3.Configuration
Figure 3-3 Block Diagram (Mode 1)
UART 0 - 3 (mode 1, asynchronous receive)
MD1
SMR: bi t 7
0 Asynchronous mode
MD0
Operation mode
RXE SCR: bit 1
0 Disable receives
1 Enable receives
CL
SCR: bit 4
0
Disabled
1
8-bit data
PEN SCR: bit 7
0
No parity
1
Disabled
BDS SSR: bit 2
0 Transmit from LSB
1 Transmit from MSB
SBL
SCR: bit 5
0
1 stop bit
1
2 stop bit
A/D
SCR: bit 3
0 Data frame
1 Address frame
S MR: bit 6
1 Multiprocessor mode
SCKE
SMR: bit 1
0
(Initial value)
1
Disabled
* The clock is the same at
receive and transmit.
Clock
(U-TIMER)
SCK0/P02
SCK1/P05
SCK2/P26
SCK3/P31
REC
SCR: bit 2
0 Clear PE, ORE, and FRE
1
Disabled
ORE
SSR: bit 6
0 No overrun error
1 Overrun error present
FRE
SSR: bit 5
0 No framing error
1 Framing error present
CS0 SMR: bit 1
0
U-timer
1 External clock
0
Clear error flags
Error detection
Operation
clock (F)
Control circuit and Receive
state judging circuit
1
Read of the port
1
SCK0 PFR0: bit 2
SCK1 PFR0: bit 5
SCK2 PFR2: bit 6
SCK3 PFR3: bit 1
0 General-purpose output
1 Operation clock output
(Operation clock)
From the port data
register
0
P02
P05
P26
P31
0
1
Shift clock
(F/16)
RIE
SSR: bit 1
0 Disable interrupts
1 Enable interrupts
Receive shifter
0
DDR0: bit 2
DDR0: bit 5
DDR2: bit 6
DDR3: bit 1
Input
Output
Register full
Receive data register
1
SCKE
SMR: bit 5,4
0
Disabled
1 Only 1 can be written.
Read of the port
SIN0/P00
SIN1/P03
SIN2/P24
SIN3/P27
SCKE
SMR: bit 2,0
0 Only 0 can be written.
1
Disabled
P00
P03
P24
P27
0
1
From the port
data register
OR
RDRF SSR: bit 4
Cannot read
0 (not received or
still receiving)
SIDR
Can read
(receive completed)
DDR0: bit 0
DDR0: bit 3
DDR2: bit 4
DDR2: bit 7
Input
Output
1
UART0 receive interrupt (#27)
UART1 receive interrupt (#29)
UART2 receive interrupt (#31)
UART3 receive interrupt (#33)
Register number
UART
Mode
0
1
2
3
SMR0
SMR1
SMR2
SMR3
Serial
control
SCR0
SCR1
SCR2
SCR3
Input
Output
SIDR0
SIDR1
SIDR2
SIDR3
SODR0
SODR1
SODR2
SODR3
Internal
clock
U-timer0
U
timer0
U-timer1
U-timer2
U
timer2
U-timer3
Status
SSR0
SSR1
SSR2
SSR3
Pins
SIN0, SOT0, SCK0
SIN1, SOT1, SCK1
SIN2, SOT2, SCK2
SIN3, SOT3, SCK3
Figure 3-4 Block Diagram (Mode 1)
UART 0 - 3 (mode 1, asynchronous transmit)
MD1
SMR: bi t 7
0 Asynchronous mode
MD0
Operation mode
S MR: bit 6
1 Multiprocessor mode
SCKE
SMR: bit 1
(Initial value)
0
1
Disabled
* The clock is the same at
receive and transmit.
Clock
(U-TIMER)
SCK0/P02
SCK1/P05
SCK2/P26
SCK3/P31
SCK0 PFR0: bit 2
SCK1 PFR0: bit 5
SCK2 PFR2: bit 6
SCK3 PFR3: bit 1
0 General-purpose output
1 Operation clock output
TXE SCR: bit 0
0 Disable transmits
1 Enable transmits
CL
SCR: bit 4
0
Disabled
1
8-bit data
PEN SCR: bit 7
0
No parity
1
Disabled
BDS SSR: bit 2
0 Transmit from LSB
1 Transmit from MSB
A/D
SCR: bit 3
0 Data frame
1 Address frame
SBL
SCR: bit 5
0
1 stop bit
1
2 stop bit
CS0 SMR: bit 1
0
U-timer
1 External clock
0
Operation
clock (F)
Control circuit
Read of the port
P02
P05
P26
P31
0
1
1
(Operation clock)
0
From the port
data register
DDR0: bit 2
DDR0: bit 5
DDR2: bit 6
DDR3: bit 1
Input
Output
Shift clock
(F/16)
SCKE
SMR: bit 2,0
0 Only 0 can be written.
1
Disabled
0
From the port
data register
Transmit shifter
1
Transmit data register
TIE
SSR: bit 0
0 Disable interrupts
1 Enable interrupts
SIDR
SCKE
SMR: bit 5,4
0
Disabled
1 Only 1 can be written.
246
Read of the port
1
Register empty
0
TDRE
SSR: bit 3
0 Distable the write to SODR
1 Enable the write to SODR
1
SOT0 PFR0: bit 1
SOT1 PFR0: bit 4
SOT2 PFR2: bit 5
SOT3 PFR3: bit 0
0 General-purpose port output
1 UART (output)
SOT0/P01
SOT1/P04
SOT2/P25
SOT3/P30
* Write only
UART0 transmit interrupt (#28)
UART1 transmit interrupt (#30)
UART2 transmit interrupt (#32)
UART3 transmit interrupt (#34)
Register number
UART
Mode
0
1
2
3
SMR0
SMR1
SMR2
SMR3
Serial
control
SCR0
SCR1
SCR2
SCR3
Input
Output
Status
SIDR0
SIDR1
SIDR2
SIDR3
SODR0
SODR1
SODR2
SODR3
SSR0
SSR1
SSR2
SSR3
Internal
clock
U-timer0
U-timer1
U-timer2
U-timer3
Pins
SIN0, SOT0, SCK0
SIN1, SOT1, SCK1
SIN2, SOT2, SCK2
SIN3, SOT3, SCK3
Chapter 23 UART
3.Configuration
Figure 3-5 Block Diagram (Mode 2)
UART 0 - 3 (mode 2, synchronous transmit/receive)
MD1
Operation mode
SMR: bi t 7
P00
P03
P24
P27
0
1
SIN0/P00
SIN1/P03
SIN2/P24
SIN3/P27
DDR0: bit 0
DDR0: bit 3
DDR2: bit 4
DDR2: bit 7
Input
Output
PEN SCR: bit 7
0
No parity
1
Disabled
RDRF
SIDR
0
SCK0/P02
SCK1/P05
SCK2/P26
SCK3/P31
SCK0 PFR0: bit 2
SCK1 PFR0: bit 5
SCK2 PFR2: bit 6
SCK3 PFR3: bit 1
0 General-purpose output
1 Operation clock output
DDR0: bit 2
DDR0: bit 5
DDR2: bit 6
DDR3: bit 1
Input
Output
Cannot read SIDR
(not received or
still receiving)
Receive status n
judging circuit n
Control circuit
Shift clock
From the port
data register
Shifter
UART
Mode
0
1
2
3
SMR0
SMR1
SMR2
SMR3
Serial
control
SCR0
SCR1
SCR2
SCR3
0
SOT0 PFR0: bit 1
SOT1 PFR0: bit 4
SOT2 PFR2: bit 5
SOT3 PFR3: bit 0
0 General-purpose port output
1 UART output
* Write only
Transmit data register
Register empty
1
TDRE
SSR: bit 3
0 Distable the write to SODR
1 Enable the write to SODR
Register number
Input
Output
Status
Internal
clock
SIDR0
SIDR1
SIDR2
SIDR3
SODR0
SODR1
SODR2
SODR3
SSR0
SSR1
SSR2
SSR3
U-timer0
U-timer1
U-timer2
U-timer3
REC
SCR: bit 2
0 Clear PE, ORE, and FRE
No effect
1
1
SODR
SCKE
SMR: bit 1
0 Disable clock outputs
1 Enable clock outputs
Clearing the error flag
Read of the port
From the port
data register
0
0
1
Error detection
ORE
SSR: bit 6
0 No overrun error
1 Overrun error present
Operation
clock
Pins
SIN0, SOT0, SCK0
SIN1, SOT1, SCK1
SIN2, SOT2, SCK2
SIN3, SOT3, SCK3
1
OR
Can read SIDR
CS0 SMR: bit 1
0
U-timer
1 External clock
1
Read of the por
1
SSR: bit 4
1 (received completed)
Shifter
0
RIE
SSR: bit 1
0 Disable interrupts
1 Enable interrupts
Register full
Receive data register
From the port
data register
Read of the port
UART0 receive interrupt (#28)
UART1 receive interrupt (#30)
UART2 receive interrupt (#32)
UART3 receive interrupt (#34)
CL
SCR: bit 4
Disabled
0
1
8-bit data
TXE SCR: bit 0
0 Disable transmits
1 Enable transmits
Clock
(U-TIMER)
P02
P05
P26
P31
0
1
BDS
SSR: bit 2
0 Transmit from LSB
1 Transmit from MSB
RXE SCR: bit 1
0 Disable receives
1 Enable receives
1 Synchronous mode
0
SOT0/P01
SOT1/P04
SOT2/P25
SOT3/P30
UART0
UART1
UART2
UART3
TIE
SSR: bit 0
0 Disable interrupts
1 Enable interrupts
Figure 3-6 Register List
247
Chapter 23 UART
3.Configuration
Note: See “Chapter 20 Interrupt Control (Page No.207)” about ICR register and interrupt vectors.
248
Chapter 23 UART
4.Registers
4. Registers
4.1 SMR: Serial Mode Register
Used for UART operation mode control
•
•
•
•
SMR0
SMR1
SMR2
SMR3
(UART0): Address
(UART1): Address
(UART2): Address
(UART3): Address
063h (access: Byte, Half-word, Word)
06Bh (access: Byte, Half-word, Word)
073h (access: Byte, Half-word, Word)
0C3h (access: Byte, Half-word, Word)
7
MOD1
6
MOD0
5
–
4
–
3
CS0
2
–
1
SCKE
0
–
0
0
–
–
0
–
0
–
R/W
R/W
RX, W1
RX, W1
RX, W
RX, W0
R/W
RX, W0
bit
Initial
value
Attribute
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit 7-6: Mode selection
MOD1
0
0
1
1
MOD0
0
1
0
1
Operation mode
Mode 0: Asynchronous (start-stop synchronization) normal mode
Mode 1: Asynchronous (start-stop synchronization) multiprocessor mode
Mode 2: Synchronous mode
Disabled
• The multiprocessor mode is the mode where two or more slaves are connected to one master.
Only the master is supported in this UART. Since the parity check function cannot be used in the multiprocessor
mode, make sure to set “0” to parity enable bits (SCR0.PEN) - (SCR3.PEN).
• bit5-4: UndefinedThe write value should always be “1”. The read value is indeterminate.
• bit3: Operation clock selection
CS0
0
1
Operation
Built-in timer (U-timer)
External clock
• Since the setting change of the operation clock selection bit takes effect immediately, make sure to stop UART
before changing the value.
• bit2: UndefinedThe write value should always be “0”. The read value is indeterminate.
• bit1: SCK pin control
SCKE
0
1
Operation
The SCK pin functions as a clock input pin.
The SCK pin functions as a clock output pin.
• The setting is enabled in the synchronous mode (mode 2).
• When you use the clock input pin (SCK=“0”), remember to set the operation clock selection bit as the external
clock (CS0=“1”).
• If using the asynchronous mode (mode 0 and 1), set the SCK pin control bit to “0”.
• bit0: UndefinedThe write value should always be “0”. The read value is indeterminate.
Note: Do not use the read/modify/write commands on SMR register. Make sure to write the value that take
account of the restriction bits (Bit-0, -2, -4, and -5) in Byte, Half-word, or Word.
249
Chapter 23 UART
4.Registers
4.2 SCR: Serial Control Register
This register sets up the transfer protocol of the serial communication of UART.
•
•
•
•
SCR0
SCR1
SCR2
SCR3
(UART0): Address
(UART1): Address
(UART2): Address
(UART3): Address
062h (access: Byte, Half-word, Word)
06Ah (access: Byte, Half-word, Word)
072h (access: Byte, Half-word, Word)
0C2h (access: Byte, Half-word, Word)
7
PEN
6
P
5
SBL
4
CL
3
A/D
2
REC
1
RXE
0
TXE
0
0
0
0
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R1,W
R/W
R/W
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit7: Parity setting
PEN
0
1
Operation
No parity
With parity
• Parity can only be used in the asynchronous normal mode (mode 0).
• Set “0” in the other modes (mode 1 and 2).
• bit6: Parity selection
P
0
1
Operation
Even parity
Odd parity
• The setting is enabled when using parity (PEN=“1”).
• bit5: Stop bit length
SBL
0
1
Operation
1 stop bit
2 stop bit
• The setting is enabled in the asynchronous mode (mode 0 and 1).
• bit4: Frame data length
CL
0
1
Operation
7 bits / frame
8 bits / frame
• 7 bits can only be used in the asynchronous normal mode (mode 0).
• Make sure to set “1” in the other modes (mode 1 and 2).
• bit3: Frame data format
A/D
0
1
Operation
Data frame
Address frame
• The setting is enabled in the asynchronous multiprocessor mode (mode 1).
• bit2: Clearing the error flag
REC
0
250
Operation
Clearing the error flag
bit
Initial
value
Attribute
Chapter 23 UART
4.Registers
1
No effect on operation.
• When the error flag clear bit is set to “0”, the error flag (PE, ORE, and PRE) will be set to “0”.
• bit1: Receive operation enable
RXE
0
1
Operation
Disable the receive operation (stop request).
Enable the receive operation.
• When the receive operation is disabled while the data is being received, it stops after completing the receive
operation.
• bit0: Transmit operation enable
TXE
0
1
Operation
Disable the transmit operation (stop request).
Enable the transmit operation.
• When the transmit operation is disabled while the data is transmitted, it stops after completing the transmit
operation.
251
Chapter 23 UART
4.Registers
4.3 SSR: Serial status register
This register indicates the status of UART.
•
•
•
•
SSR0
SSR1
SSR2
SSR3
(UART0): Address
(UART1): Address
(UART2): Address
(UART3): Address
060h (access: Byte, Half-word, Word)
068h (access: Byte, Half-word, Word)
070h (access: Byte, Half-word, Word)
0C0h (access: Byte, Half-word, Word)
7
PE
6
ORE
5
FRE
4
RDRF
3
TDRE
2
BDS
1
RIE
0
TIE
0
0
0
0
1
0
0
0
R/WX
R/WX
R/WX
R/WX
R/WX
R/W
R/W
R/W
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit7: Parity error flag
PE
0
1
Status
No parity error
Parity error present
• When a parity error occurs at receive, the parity error flag is set to “1”. (enabled in mode 0)
• When the parity error flag is “1”, the value of received data (SIDR) is invalid.
• bit6: Overrun error flag
ORE
0
1
Status
No overrun error
Overrun error present
• When an overrun error occurs at receive, the overrun error flag is set to “1”.
• When the overrun error flag is “1”, the value of received data (SIDR) is invalid.
• bit5: Framing error flag
FRE
0
1
Status
No framing error
Framing error present
• When an framing error occurs at receive, the framing error flag is set to “1”.
• When the flag is “1”, the data of the serial input data register (SIDR) becomes invalid.
252
bit
Initial
value
Attribute
Chapter 23 UART
4.Registers
• bit4: Receive data flag
RDRF
0
1
Status
No receive data
Receive data present
• When the data is received normally, the receive data flag will be set to “1”.
• The receive data flag is set to “0” by reading the serial input data register (SIDR).
• bit3: Transmit buffer (SODR) empty flag
TDRE
0
1
Status
Data present in the transmit buffer (write of the transmit data disabled)
Data not present in the transmit buffer (write of the transmit data enabled)
• When the transmit buffer becomes empty, the transmit buffer empty flag will be set to “1”.
• The transmit buffer empty flag is set to “0” by writing data in the serial output data register (SODR).
• The writing to the serial output data register (SODR) should be done after the transmit buffer empty flag is set to
“1”.
• bit2: Direction of transfer
BDS
0
1
Operation
Transfer starting at the Least Significant Bit (LSB)
Transfer starting at the Most Significant Bit (MSB)
• Specifies the direction of transfer. (Separate settings for the transmit and the receive is not possible.)
• When the direction-of-transfer bit is changed after the update of the data register (SIDR and SODR), the value of
data (SODR) becomes invalid.
• bit1: Enable receive interrupts
RIE
0
1
Operation
Disables reception interrupts
Enable receive interrupts
• Receive interrupts include the parity error (PE), the overrun error (ORE), the framing error (FRE), and the data
receiving (RDRF).
• bit0: Enable transmit interrupts
TIE
0
1
Operation
Disable transmit interrupts.
Enable transmit interrupts.
The transmit interrupt is the transmit buffer empty (TDRF).
By setting error flag clear bits (SCR0.REC) - (SCR3.REC) to “0”, all error flags (parity / overrun / framing) are set to
“0”.
253
Chapter 23 UART
4.Registers
4.4 SIDR: Serial Input Data Register / SODR: Serial Output Data Register
The buffer of the UART transmit/receive data.
•
•
•
•
SIDR0/SODR0
SIDR1/SODR1
SIDR2/SODR2
SIDR3/SODR3
(UART0): Address
(UART1): Address
(UART2): Address
(UART3): Address
061h
069h
071h
0C1h
(access: Byte, Half-word, Word)
(access: Byte, Half-word, Word)
(access: Byte, Half-word, Word)
(access: Byte, Half-word, Word)
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
X
X
X
X
X
X
X
X
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R, W
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• When it is read, it becomes the serial input data register (SIDR).
• When it is written, it becomes the serial output data register (SODR).
• When frame data length is the 7 bits, the bit 7 (D7) becomes invalid.
• Write operation should be done after enabling the write of the transmit data.
(When the transmit data empty flag (SSR0.TDRE) - (SSR3.TDRE) is “1”)
254
bit
Initial
value
Attribute
Chapter 23 UART
5.Operation
5. Operation
This product has four UARTs, and the transmit/receive operations work independently.
The operation in each mode is described below:
5.1 Mode 0/1: Asynchronous mode (normal/multiprocessor)
Receive operation
(5) (5)'
(4)
Take a sample at the middle
(2)
Take a sample at the middle
(3)
1 2 3 4 5 6 7 8 9
Internal
operation
timing
Parity,
D0
START
Receive data
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A/D or STOP
7 8 9 10
(3)
(1)
Enable transmits (TXE)
Receive data
S
T
(6) (8)
A (4) (4) (4) (4) (4) (4) (4) (4) (5)
P
R
S S
0 1 2 3 4 5 6 7 A
T
T T
R
O O
I
Mode 0
P P
T
S
T
A
R
T
(9)
Stop receive operations
(9)
Disable
(5)'
0 1
2
3
4
Mode 1
5
6
7
A
/
D
S
T
O
P
(5) Y
(PE)
Error flag set timing
(6)
(ORE/FRE)
(ORE/FRE)
Clear error flags
(write "0" to REC)
(7)
Receive buffer full (RDRF)
SIDR read
: Interrupt
• Mode 0
(1) Enable receive operations (RXE=“1”)
(2) Detect the fall of the receive data.
(3) The count starts at the internal operation timing, and the START bit is detected at the LOW width for the 1/2 bit.
(4) Take in the data for 1 bit near the rising of each 9th clock (the shifter is one bit shift).
(Repeat for the specified bits)
(5) With parity
Confirm the parity near the rising of the next 9th clock, and if an error is found, set the parity error flag (PE) to “1”.
(6) Confirm the STOP bit near the rising of the next 9 clock (H).
a) If the STOP bit is not detected, set the framing error flag (FRE) to “1”.
b) Although the STOP bit is detected, if the last receive flag is not cleared yet (RDRF=“1”), set the overrun error flag
(ORE) to “1”.
(7) When the STOP bit is detected, transmit the receive data from the shifter to the serial input data register (SIDR), and
set the receive completed flag (RDRF) to “1”.
(8) Do nothing to the 2nd STOP bit.
(9) When operations are disabled during the receive (RXE = 0), the operation stops when the receiving frame is
completed, and the receive data is stored in the serial input data register (SIDR), and the receive completed flag
(RDRF) is set to “1”.
• Mode 1
(1)-(4) Same as the operation in the mode 0.
(5)’ Do nothing to the A/D bit.
(6)-(7) Same as the operation in the mode 0.
255
Chapter 23 UART
5.Operation
5.2 Mode 0/1: Asynchronous mode (normal/multiprocessor)
Transmit operation
(1)
B
A
SODR write
Empty
C
(2)
(2)
(2)
SODR
(10)
Stop transmit operations
(10)
Disable
Enable transmits
(TXE)
(2)
(2)
(2)
Data A
Empty
Empty
Data B
(4)
Shifter
Data A
Transmit buffer
empty (TDRE)
(2)
(5)
(4)
Data C
Data B
(2)
S
T
A (5) (6) (6) (6)
R
1 2 3
T 0
(3)
Data example A
Transmit data
Empty
Data C
(4)
(5)
(5)
S
T
(6) (6) (7) (8) (9)
(5)
A
P S
R
S
6 7
0 1 2 3 4 5 6
A T
T T
R
O O
Data example B
I
P
T P
(7)'
7
A
/
D
S
T
O
P
S
T
(5)
A
R
0 1
T
(7)'
2
3
4
5
6
7
A
/
D
S
T
O
P
Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Internal operation
clock
Data 1
(3)
Transmit data
START
Data A
Data B
: Interrupt
• Mode 0
(1) Enable transmit operations (RXE=“1”)
(2) When data is written in the serial output data register (SODR), the transmit buffer empty flag (TDRE) is set to “0”.
(3) Transmit the START bit (L) and count the clock.
(4) Transmit data from the serial output data register (SODR) to the shifter.
(5) After 16 counts, the shifter shifts near the next 1st clock rising, and the first bit data is outputted, then the transmit
buffer empty flag (TDRE) is set to “1”.
(6) The shifter shifts and the data for 1 bit is outputted near the rising of the next 1st clock.
((6) is repeated for the specified bits.)
(7) With parity
The parity bit is outputted near the rising of the next 1st clock.
(8) The STOP bit (H) is outputted near the rising of the next 1st clock.
(9) When the STOP bit is specified by 2 bits, extend the output of the STOP bit by 1 more bit.
(10) When the operation is disabled during the transmit (TXE=“0”), it stops when the last transmit data is transmitted
after the transmit buffer has become empty, and it has transmitted the STOP bit.
• Mode 1
(1)-(6) Same as the operation in the mode 0.
(7)’ The A/D bit is outputted at the fall of the next 1st clock.
(8)-(9) Same as the operation in the mode 0.
256
Chapter 23 UART
5.Operation
5.3 Mode 2: Clock synchronous mode
Transmit/receive operations
(1)
(8)
(8)
Enable operations
(TXE/RXE)
(2)
C
B
A
Operation stop
Disable
SODR write (start)
Transmit
buffer empty (TDRE)
(2)
(3)
Data A
Transmit data
(SOT)
0 1
2
3
Data C
Data B
4
5
6
0 1
7
2
3
4
5
6
0 1
7
2
3
4
5
6
7
(4)
Transmit
Operation clock
(SCK: internal/external)
= shift clock
Sampling
(5)
Receive data (SIN)
0 1
2
3
4
5
6
7
0 1
2
3
Data Y
Data X
4
5
6
7
0 1
2
3
4
5
6
7
Data Z
(6)
Error flag (ORE)
set timing
Clear error flags
(write "0" to REC)
Receive buffer full
(RDRF)
(7)
SIDR read
: Interrupt
In the synchronous mode, transmit and receive operations work in synchronized manner.
(1) Enable operations (TXE=“1”, RXE=“1”)
(2) Data is written in the serial output data register (SODR). The transmit buffer empty flag (TDRE) is set to “0”.
(3) Transmit data from the serial output data register (SODR) to the shifter.
(4) The shifter shifts at the fall of the clock, and the first bit data is outputted, then the transmit buffer empty flag
(TDRE) is set to “1”.
(5) The first bit data are taken in at the rising of the clock.
((4) and (5) are repeated for 8 bits.)
(6) When the last bit is received at the fall of the clock and the last receive flag has not been cleared yet (RDRF=“1”),
the overrun error flag (ORE) is set to “1”.
(7) When all bits are received without errors
Transmit the receive data from the shifter to the serial input data register (SIDR), and set the receive completed flag
(RDRF).
(8) When operations are disabled during the receive (settings of both of RXE=“0”, TXE=“0” are required), the
operation stops when the last transmit/receive frame is completed, and the receive data is stored in the serial input
data register (SIDR), and the receive completed flag (RDRF) is set to “1”.
257
Chapter 23 UART
6.Setting
6. Setting
■ Required setting for operating in the asynchronous-normal mode
Table 6-1 Basic Setting
Setting
To use the U-timer, its setting is required.
Selection of operation modes (mode 0)
Selection of the operation clock (U-timer/outside)
SCK pin control bit = “0”
Setting Registers
See “Chapter 22 U-timer (Page
No.233)”.
Serial mode register
(SMR0-SMR3)
Port function register (PFR0,
PFR2, and PFR3)
Data direction register (DDR0,
DDR2)
SOT pin output setting
SIN pin input setting
Enable operations (enable receive operations /enable transmit
operations).
Setting of parity
Selection of the type of parity (odd/even)
Selection of the data length (7 / 8 bits)
Selection of the stop bit length (1 / 2 bits)
(Clearing the error flag
Serial control register
(SCR0-SCR3)
Transfer direction setting
Serial status register
(SSR0-SSR3)
Setting
Procedures *
–
See 7.2
See 7.3
See 7.4
See 7.4
See 7.4
See 7.5
See 7.6
See 7.6
See 7.7
See 7.8
See 7.9
See 7.10
*: For the setting procedure, refer to the section indicated by the number.
Table 6-2 Receive Setting
Setting
Clearing the error flag
Clear of the receive completed flag/receive preparation
(-> Dummy read of the receive data)
Checking of the receive completed flag
Storing of the receive data
(-> Read the receive data, clear the flag, and prepare for the next
receive)
Setting Registers
Setting
Procedures *
Serial control register
(SCR0-SCR3)
Serial input data register
(SIDR0-SIDR3)
Serial status register
(SSR0-SSR3)
See 7.11
Serial input data register
(SIDR0-SIDR3)
See 7.13, 7.18
See 7.9
See 7.12
*: For the setting procedure, refer to the section indicated by the number.
Table 6-3 Transmit Setting
Setting
Check the transmit buffer empty flag
Setting of the transmit data (→writing of the transmit data)
Setting Registers
Serial status register
(SSR0-SSR3)
Serial input data register
(SIDR0-SIDR3)
*: For the setting procedure, refer to the section indicated by the number.
258
Setting
Procedures *
See 7.14
See 7.15, 7.18
Chapter 23 UART
6.Setting
Table 6-4 In Case of an Error
Setting
Setting Registers
Serial status register
(SSR0-SSR3)
Checking of the error flag
Setting
Procedures *
See 7.12
*: For the setting procedure, refer to the section indicated by the number.
■ Required setting for operating with the master in the asynchronous-multiprocessor mode
Basically the same as the normal mode.
Table 6-5 Basic Setting (points differ from the normal mode)
Setting
Setting register
Setting
Procedures *
Setting of operation modes (mode 1)
Serial mode register
(SMR0-SMR3)
See 7.2
The setting of no parity
The setting of the data length (8 bits only)
Serial control register
(SCR0-SCR3)
See 7.6
See 7.7
*: For the setting procedure, refer to the section indicated by the number.
Table 6-6 Transmit Setting (points differ from the normal mode)
Setting
Switching of the frame data format
(Address/data)
Setting register
Serial control register
(SCR0-SCR3)
Setting
Procedures *
See 7.17
*: For the setting procedure, refer to the section indicated by the number.
• Receive setting (same as the normal mode)
• In case of an error (same as the normal mode)
259
Chapter 23 UART
6.Setting
■ The settings required to operate in the synchronous mode
Table 6-7 Basic Setting
Setting
(To use the U-timer, its setting is required.)
Selection of operation modes (mode 2)
Selection of the operation clock (U-timer/outside)
Clock input/output setting of the SCK pin
Enable operations (enable receive operations /
enable transmit operations).
The setting of no parity
The setting of 8 bits data length
(Clearing the error flag)
Transfer direction setting
SOT pin output setting
SIN pin input setting
Clearing of the receive completed flag
(-> Dummy read of the receive data = start)
Setting of the transmit data
(-> The write of the transmit data/start the
transmit)
Checking of the receive completed flag
Storing of the receive data
(-> Read the receive data, clear the flag, and
prepare for the next receive)
Setting register
See “Chapter 22 U-timer (Page No.233)”.
Serial mode register (SMR0-SMR3)
Setting
Procedures *
–
See 7.2
See 7.3
See 7.4
See 7.5
Serial control register
(SCR0-SCR3)
Serial status register (SSR0-SSR3)
Port function register (PFR0, PFR2, and PFR3)
Data direction register (DDR0, DDR2)
Serial input data register
(SIDR0-SIDR3)
See 7.6
See 7.7
See 7.9
See 7.10
See 7.4
See 7.4
See 7.11
Serial output data register (SIDR0-SIDR3)
See 7.15
Serial status register (SSR0-SSR3)
See 7.12
Serial input data register
(SIDR0-SIDR3)
See 7.13, 7.18
*: For the setting procedure, refer to the section indicated by the number.
Table 6-8 In Case of an Error
Setting
Checking of the error flag
Setting register
Serial status register (SSR0-SSR3)
Setting
Procedures *
See 7.12
*: For the setting procedure, refer to the section indicated by the number.
Table 6-9 The Setting Required to Enable UART Interrupts
Setting
Setting register
Setting
Procedures *
Setting of interrupt vectors and interrupt levels
See “Chapter 20 Interrupt Control (Page
No.207)”.
See 7.22
Interrupt setting
Clearing interrupt requests
Enabling interrupt requests
Serial status register (SSR0-SSR3)
*: For the setting procedure, refer to the section indicated by the number.
260
See 7.24
Chapter 23 UART
7.Q & A
7. Q & A
7.1 What are the possible combinations of the settings?
The following are the possible combinations.
Operation mode
(MD[1: 0])
Data length
(CL)
7 bit
(0)
0
Asynchronous Normal mode
(00)
Parity
(PEN)
Parity
Selection
(P)
None
(0)
–
Yes
(1)
Yes
(1)
2 bit
(1)
2 bit
(1)
2 bit
(1)
2 bit
(1)
1 bit
(0)
2 bit
(1)
Address
(1)
1 bit
(0)
2 bit
(1)
Data
(0)
1 bit
(0)
2 bit
(1)
Odd (1)
–
–
Even (0)
Odd (1)
1
Asynchronous Multiprocessor mode
(01)
8 bit
(1)
None
(0)
–
2
Synchronous mode
(10)
8 bit
(1)
None
(0)
–
STOP bit
length
selection
(SBL) Note 1
1 bit
2 bit
(0)
(1)
1 bit
(0)
1 bit
(0)
1 bit
(0)
1 bit
(0)
Even (0)
None
(0)
8 bit
(1)
Data
Format
(AD)
–
Presence of an error flag
Overrun
(ORE)
Framing
(FRE)
Parity
(PE)
O
O
O
O
O
–
O
–
–
–
Selection of the STOP bit is possible only at the transmit. At the receive, only the 1st bit is detected (the 2nd bit is
ignored).
7.2 How do I select an operation mode?
Use operation mode bits (SMR0.MOD [1:0]) - (SMR3.MOD [1:0]).
Operation mode
Mode 0
Mode 1
Mode 2
Asynchronous - normal mode
Asynchronous - multiprocessor mode
Synchronous mode
————
The operation mode bit (MOD [1:0])
Set to “00”.
Set to “01”.
Set to “10”.
Do not set “11”.
7.3 The types and the selection methods of the operation clock
There are 2 types of operation clock: the built-in timer and the external clock.
Use operation clock selection bits (SMR0.CS0) - (SMR3.CS0) to set.
Control details
To select the built-in timer UTIMER
To select the external clock
Operation clock selection bit (CS0)
Set to “0”.
Set to “1”.
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7.Q & A
7.4 How do I control the SCK pin, the SIN pin, and the SOT pin?
Uses the following setting.
How do I set SCK pin as the input?
How do I set SCK pin as the output?
To set the SIN pin as the input
How do I set SOT pin as the output?
UART0
DDR0.P02 = “0”
PFR0.SCK0 = “0”
SMR0.SCKE = “0”
PFR0.SCK0 = “1”
SMR0.SCKE = “0”
DDR0.P00 = “0”
PFR0.SOT0 = “1”
UART1
DDR0.P05 = “0”
PFR0.SCK1 = “0”
SMR1.SCKE = “0”
PFR0.SCK1 = “1”
SMR1.SCKE = “0”
DDR0.P03 = “0”
PFR0.SOT1 = “1”
UART2
DDR2.P26 = “0”
PFR2.SCK2 = “0”
SMR2.SCKE = “0”
PFR2.SCK2 = “1”
SMR2.SCKE = “0”
DDR2.P24 = “0”
PFR2.SOT2 = “1”
UART3
DDR3.P31 = “0”
PFR3.SCK3 = “0”
SMR3.SCKE = “0”
PFR3.SCK3 = “1”
SMR3.SCKE = “0”
DDR3.P27 = “0”
PFR3.SOT3 = “1”
7.5 How do I enable/stop the operation of UART?
Use receive operation control bits (SCR0.RXE) - (SCR3.RXE).
Control details
Disabling of the receive operation (stop)
Receive operation enable
Receive operation control bit (RXE)
Set to “0”.
Set to “1”.
Use transmit operation control bits (SCR0.TXE) - (SCR3.TXE).
Control details
Disabling of the transmit operation (stop)
Transmit operation enable
Transmit operation control bit (TXE)
Set to “0”.
Set to “1”.
7.6 How do I set the parity?
Use parity setting bits (SCR0.PEN) - (SCR3.PEN) and parity selection bits (SCR0.P) - (SCR3.P).
Operation
To not use parity
To use even parity
To use odd parity
Parity setting, the selection bit (PEN, P)
Set to “00” or “01”.
Set to “10”.
Set to “11”.
7.7 How do I set a data length?
Use data length selection bits (SCR0.CL) - (SCR3.CL).
Operation
To use 7-bit length
To use 8-bit length
Data length selection bit (CL)
Set to “0”.
Set to “1”.
7.8 How do I select the STOP bit length?
Use STOP bit length selection bits (SCR0.SBL) - (SCR3.SBL).
Operation
To set the STOP bit to 1 bit length
To set the STOP bit to 2 bit length
262
STOP bit length selection bit (SBL)
Set to “0”.
Set to “1”.
Chapter 23 UART
7.Q & A
7.9 How do I clear the error flag?
Use error flag clear bits (SCR0.REC) - (SCR3.REC).
Control details
To clear the error flags (PE, OFE, and PRE)
Error flag clear bit (REC)
Set to “0”.
7.10 How do I set the transfer direction?
Use set direction selection bits (SSR0.BDS) - (SSR3.BDS).
Any operation mode can select either LSB/MSB as the transfer direction.
Control details
To use the LSB transfer (from the least significant bit)
To use the MSB transfer (from the most significant bit)
Set direction selection bit (BDS)
Set to “0”.
Set to “1”.
7.11 How do I clear the receive completed flag?
Uses the following setting.
Control details
To clear the receive completed flag
Read the SIDR register.
The first read of the SIDR register starts the receive.
7.12 What are the types and the meanings of error flags?
There are 3 types of error flags and they have following meanings.
Error flags
Parity error (PE)
Overrun error (ORE)
Framing error (FRE)
Description
The received value (numeric value) has an error(s).
The next data arrived before finishing reading the receive data.
The format of the received data has an error(s).
7.13 Where is the receive data stored?
The receive data is stored in the receive data register (SIDR0-SIDR3).
7.14 Which is the status to check the timing to write the transmit data?
You can confirm it in transmit buffer empty flags (SSR0.TDRE) - (SSR3.TDRE).
7.15 Where are the transmit data written to?
The transmit data is written in transmit data registers SODR0-SODR3.
7.16 How do I clear the transmit buffer empty flag?
Uses the following setting.
Control details
To clear the transmit buffer empty flag
Write in the SODR register.
The first write of the SODR register starts the transmit.
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Chapter 23 UART
7.Q & A
7.17 How do I select a data format (address/data)?
Use data length selection bits (SCR0.AD) - (SCR3.AD).
Operation
To use bit-8 as data (low level)
To use bit-8 as address (high level)
Data length selection bit (AD)
Set to “0”.
Set to “1”.
Valid only at the transmit The A/D bit is ignored at the receive.
7.18 How do I start the receive/transmit?
Follow the following procedures. (See 7.5.)
• Mode 0/1, the transmit:
1. Enable the transmit operation.
2. Write data in the transmit data registers (SODR0-SODR3) (= start the transmit).
• Mode 0/1, the receive:
1. Enable the receive.
2. Read the receive data registers (SIDR0-SIDR3) (dummy read = start the receive).
• Mode 2, the transmit/receive: 1. Enable the transmit (the receive enable is optional).
2. Write data in the transmit data registers (SODR0-SODR3) (= start the transmit/
receive).
(The write to transmit data registers (SODR0-SODR3) is required even in the case of the receive operation only.)
7.19 How do I stop the operation?
Perform the following operations. (See 7.5.)
• Mode 0/1, the transmit:
If you disable the transmit operation,
after the transmit buffer empties, the operation is stopped when the last transmit data is
transmitted and the STOP bit has been sent.
• Mode 0/1, the receive:
If you disable the receive operation,
after the completion of the receive (after receiving the stop bit), the operation is stopped
when the receive data has been transmitted from the shifter to the register.
• Mode 2, the transmit/receive: disable both of the receive and the transmit operation.
The operation is stopped after completing the transmit/receive of data, and the receive
data has transmitted from the shifter to the register.
7.20 How do I confirm the operation completion?
Perform the following operations.
• Mode 0/1, the transmit:
check the SODR register empty flag after writing in the next transmit data.
(The completion can be confirmed by transmitting the next transmit data from the register
to the shifter, and seeing the empty flag of the transmit data register is set to “1”.)
• Mode 0/1, the receive:
check the register full flag.
(The completion can be confirmed by seeing the full flag of the receive data register is set
to “1”.)
• Mode 2, the transmit/receive :check the register full flag.
(The completion can be confirmed by seeing the full flag of the receive data register is set
to “1”.)
7.21 How do I set the baud rate?
See “Chapter 22 U-timer (Page No.233)”.
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Chapter 23 UART
7.Q & A
7.22 What interrupt registers are used?
Setting of the UART interrupt vector and UART interrupt level
The relationship among the UART number, interrupt levels and vectors is shown in the table below.
See “Chapter 20 Interrupt Control (Page No.207)” about the details of interrupt levels and interrupt vectors.
The UART0
receive
The UART0
transmit
The UART1
receive
The UART1
transmit
The UART2
receive
The UART2
transmit
The UART3
receive
The UART3
transmit
Interrupt Vectors (default)
#27
Address: 0FFF90h
#28
Address: 0FFF8Ch
#29
Address: 0FFF88h
#30
Address: 0FFF84h
#31
Address: 0FFF80h
#32
Address: 0FFF7Ch
#33
Address: 0FFF78h
#34
Address: 0FFF74h
Interrupt level setting bits (ICR[4:0])
Interrupt level register (ICR11)
Address: 0044Bh
Interrupt level register (ICR12)
Address: 0044Ch
Interrupt level register (ICR13)
Address: 0044Dh
Interrupt level register (ICR14)
Address: 0044Eh
Interrupt level register (ICR15)
Address: 0044Fh
Interrupt level register (ICR16)
Address: 00450h
Interrupt level register (ICR17)
Address: 00451h
Interrupt level register (ICR18)
Address: 00452h
7.23 Interrupt Types
There are four types of interrupt causes for the receiving side and one type for the transmitting side.
UART Reception
UART Transmission
The completion of receive (receive data register full), parity error
An interrupt request is generated by the factor occurs first among the overrun errors and the
framing errors.
An interrupt request is generated by the transmit buffer empty.
7.24 How do I enable, disable, and clear interrupts?
Enable flag for interrupt requests, interrupt request flag
Use the interrupt request enable bits (SSR0.RIE) - (SSR3.RIE) and (SSR0.TIE) - (SSR3.TIE) to enable the interrupts.
UART Reception
To disable interrupt requests
To enable interrupt requests
UART Transmission
Interrupt request enable bit (RIE)
Interrupt request enable bit (TIE)
Set to “0”.
Set to “1”.
Use the following setting to clear interrupt requests.
UART Reception
UART Transmission
Clear the receive completed flag (RDRF) by reading the
receive data register SIDR.
To clear interrupt requests
The error flags (PE, ORE, and FRE) are set to “0” by
writing “0” in the error flag clear bit (REC).
The transmit buffer empty flag
(TDRE) is set to “0” by writing
data in the transmit data register
(SODR).
(See “9. Caution (Page No.269)”.)
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Chapter 23 UART
7.Q & A
7.25 What is an example of the system construction in the mode 1?
The following is an example of the system construction when using the mode 1.
SOT
SIN
Master CPU
SOT SIN
SOT SIN
Slave CPU #0
Slave CPU #1
7.26 What is the flow chart in the mode 1?
The communication flow chart when using the mode 1 (the master side only)
(Master CPU)
START
Set the transfer
mode to 1
Set the data to select
Slave CPUs to D0-D7,
set "1" to A/D, and
transmit 1 byte
Set "0" to A/D
Receive operation
enable
Communicate with
slave CPUs
Communication
finished?
NO
YES
Communication
finished?
NO
YES
Disable receive
operations
END
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Chapter 23 UART
8.Sample Programs
8. Sample Programs
Setting Procedure Example 1
Program Example 1
Transmit 1 byte of data by UART0,
receive by UART1.
Asynchronous - normal mode
void Asynch_uart_sample(void)
{
U-Timer_initial();
Asynch_uart_initial();
Uart_start();
Initial settings
(1)
• Control of the U-timers 0 and 1
Control register settings
Select the count method >>
Underflow flag >>
Enable setting >>
Clear the U timer >>
Setting the timer value
(2)
(3)
(4)
• Interrupt settings
Setting the interrupt level
Setting the interrupt level
I flag setting
• Port
Port SOT0 Output setting
Port SIN1 input setting
• Control of UART 0 and 1
Setting of the mode register
Set the operation mode >>
}
void UÅ]Timer_initial(void)
{
IO_UTIMC0.byte = 0x00;
IO_UTIMC1.byte = 0x00;
UTIMC0
UTIMC1
UCC1
.UNDR
.UTST
.UTCR
UTIM0
UTIM1
IO_UTIM0 = 0x0067;
IO_UTIM1 = 0x0067;
ICR12
ICR13
(CCR)
IO_ICR[12].byte = 0x10;
IO_ICR[13].byte = 0x10;
__EI();
<register name>.<bit name>
PFR0. SOT0
DDR0
.P03
.CS0
SCK pin setting >>
.SCKE
/* UART0 transmit completion interrupt level setting (any value) */
/* UART1 receive completion interrupt level setting (any value) */
/* Enable interrupts. */
}
void Asynch_uart_initial(void)
{
IO_PORT1.IO_PFR0.bit.SOT0 = 1; /* SOT0 (P01) output */
IO_PORT1.IO_DDR0.bit.P03 = 0;
/* SIN1 (P03) input */
IO_SMR0.byte = 0x30;
IO_SMR1.byte = 0x30;
SMR0
SMR1
.MD1, MD0
Setting the operation clock >>
/* Value = 0000_0000 */
/* Value = 0000_0000 */
/* bit7 = 0
UUC1 Normal operation */
/* bit6-4 = 000
Undefined bit */
/* bit3 = 0
UNDR Underflow flag */
/* bit2 = 0
Undefined bit */
/* bit1 = 0
UTST Stop the U-timer. */
/* biÇî0 = 0
UTCR Clear the U-timer */
/* Initialization of the timer value (any value) */
Control register settings
SCR0
SCR1
Setting of parity >>
.PEN
Setting of even/odd parity >>
.P
Setting of a stop bit length
.SBL
Setting of 1 frame data length >>
.CL
Setting of the frame data format >>
.A/D
Error flags >>
.REC
Receive operation enable setting >>
.RXE
Transmit operation enable setting >>
.TXE
Interrupt control
SSR0
.TIE
SSR1
.RIE
IO_SCR0.byte = 0x10;
IO_SCR1.byte = 0x10;
IO_SSR0.bit.TIE = 1;
IO_SSR1.bit.RIE = 1;
/* Value = 0011_0000 */
/* Value = 0011_0000 */
/* bit7-6 = 00
MD1 and MD0 Asynchronous normal
mode */
/* bit5-4 = 11
Undefined bit */
/* bit3 = 0
CS0 Built-in timer (U-timer) */
/* bit2 = 0
Undefined bit */
/* bit1 = 0
SCKE Clock input pin */
/* bit0 = 0
Undefined bit */
/* Value = 0001_0000 */
/* Value = 0001_0000 */
/* bit7 = 0
PEN No parity */
/* bit6 = 0
P Even parity */
/* bit5 = 0
SBL 1 stop bit */
/* bit4 = 1
CL 8 bit data */
/* bit3 = 0
A/D Data frame */
/* bit2 = 0
REC Error flag clear (REC) */
/* bit1 = 0
RXE Disable the receive operation */
/* bit0 = 0
TXE Disable the transmit operation */
/* bit0 = 1
TIE Enable transmit interrupts */
/* bit1 = 1
RIE Enable receive interrupts */
}
Activation
• Start the U-timer and UART
Start U timer 0
Start the U-timer 1
Start the UART1 receive operation
Start the UART0 transmit operation
<register name>.<bit name>
UTIMC0 .UTST
UTIMC1 .UTST
SCR1
.RXE
SCR0. TXE
Interrupt
• Transmit interrupt processing
Transmit arbitrary data.
Disable transmit interrupts.
<register name>.<bit name>
SIDR0
SSR0 .TIE
• Receive interrupt processing
Receive the data
Disables reception interrupts
SIDR1
SSR1
.RIE
Interrupt vector
Setting the vector table
Caution: Requires clock-related setting and __set_il (numeric values) setting to
be made in advance. See the clock and interrupt chapters.
void Uart_start(void)
{
IO_UTIMC0.bit.UTST = 1;
IO_UTIMC1.bit.UTST = 1;
IO_SCR1.bit.RXE = 1;
IO_SCR0.bit.TXE = 1;
}
__interrupt void uart0_tx_int(void)
{
IO_SIDR0 = 0xaa;
IO_SSR0.bit.TIE = 0;
}
__interrupt void uart1_rx_int(void)
{
UART_DATA = IO_SIDR1;
IO_SSR1.bit.RIE = 0;
}
/* bit1 = 1
/* bit1 = 1
/* bit1 = 1
/* bit0 = 1
UTST Enables the U timer. */
UTST Enables the U timer. */
RXE Enable the receive operation */
TXE Enable the transmit operation */
/* Transmit arbitrary data values. */
/* bit0 = 0
TIE Disable transmit interrupts */
/* Store the received data value in the UART_DATA. */
/* bit1 = 1
RIE Disable receive interrupts */
The interrupt routine must be specified in the vector table.
#pragma intvect uart0_tx_int 28
#pragma intvect uart1_rx_int 29
Note: For the convention of registers, see “FR60Lite Family MB91230 Series Sample I/O Register
Files Usage Guide”.
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Chapter 23 UART
8.Sample Programs
Setting Procedure Example 2
Program Example 2
Transmit 1 byte of data by UART0,
receive by UART1.
CLK synchronous mode
void Synch_uart_sample(void)
{
U-Timer_initial();
Synch_uart_initial();
Uart_start();
}
void UTimer_initial(void)
{
IO_UTIMC0.byte = 0x00;
1. Initial Setting
(1) • Control of the U-timer 0
Control register settings
Select the count method >>
Underflow flag >>
Enable setting >>
Clear the U timer
Setting the timer value
(2) • Interrupt settings
Setting the interrupt level
Setting the interrupt level
I flag setting
(3) • Port
Port SOT0 Output setting
Port SCK0 Output setting
Port SIN1 input setting
Port SCK1 input setting
(4) • Control of UART 0 and 1
Setting of the UART0 mode register
Set the operation mode >>
Setting the operation clock >>
SCK pin setting >>
Setting of the UART1 mode register
Set the operation mode >>
UTIMC0
.UCC1
.UTST
.UTCR
UTIM0
IO_UTIM0 = 0x0681;
/* Value = 0000_0000 */
/* bit7 = 0
UUC1 Normal operation */
/* bit6-4 = 000
Undefined bit */
/* bit3 = 0
UNDR Underflow flag */
/* bit2 = 0
Undefined bit */
/* bit1 = 0
UTST Stop the U-timer. */
/* biÇî0 = 0
UTCR Clear the U-timer */
/* Initialization of the timer value (any value) */
ICR12
ICR13
(CCR)
IO_ICR[12].byte = 0x10;
IO_ICR[13].byte = 0x10;
__EI();
/* UART0 transmit completion interrupt level setting (any value) */
/* UART1 receive completion interrupt level setting (any value) */
/* Enable interrupts. */
.UNDR
<register name> .<bit name>
PFR0. SOT0
PFR0. SCK0
DDR0
.P03
DDR0
.P05
void Synch_uart_initial(void)
{
IO_PORT1.IO_PFR0.bit.SOT0 = 1;
IO_PORT1.IO_PFR0.bit.SCK0 = 1;
IO_PORT1.IO_DDR0.bit.P03 = 0;
IO_PORT1.IO_DDR0.bit.P05 = 0;
SMR0
.MD1, MD0
IO_SMR0.byte = 0xB2;
.CS0
.SCKE
SMR1
.MD1, MD0
Setting the operation clock >>
.CS0
SCK pin setting >>
.SCKE
IO_SMR1.byte = 0xB8;
Control register settings
SCR0
SCR1
Setting of parity >>
.PEN
Setting of even/odd parity >>
.P
Setting of a stop bit length
.SBL
Setting of 1 frame data length >>
.CL
Setting of the frame data format >>
.A/D
Error flags >>
.REC
Receive operation enable setting >>
.RXE
Transmit operation enable setting >>
.TXE
Interrupt control
SSR0 .TIE
SSR1
.RIE
SIDR1 setting
SIDR1
IO_SCR0.byte = 0x10;
IO_SCR1.byte = 0x10;
IO_SSR0.bit.TIE = 1;
IO_SSR1.bit.RIE = 1;
IO_SIDR1 = 0x10;
/* SOT0 (P01) output */
/* SCK0 (P02) output */
/* SIN1 (P03) input */
/* SCK1 (P05) input */
/* Value = 1011_0010 */
/* bit7-6 = 10
/* bit5-4 = 11
/* bit3 = 0
/* bit2 = 0
/* bit1 = 1
/* bit0 = 0
/* Value = 1011_1000 */
/* bit7-6 = 10
/* bit5-4 = 11
/* bit3 = 1
/* bit2 = 0
/* bit1 = 0
/* bit0 = 0
/* Value = 0001_0000 */
/* Value = 0001_0000 */
/* bit7 = 0
/* bit6 = 0
/* bit5 = 0
/* bit4 = 1
/* bit3 = 0
/* bit2 = 0
/* bit1 = 0
/* bit0 = 0
/* bit0 = 1
/* bit1 = 1
/* Set any value */
MD1, MD0 CLK synchronous mode */
Undefined bit */
CS0 Built-in timer (U-timer) */
Undefined bit */
SCKE Clock output pin */
Undefined bit */
MD1, MD0 CLK synchronous mode */
Undefined bit */
CS0 External clock */
Undefined bit */
SCKE Clock input pin */
Undefined bit */
PEN No parity */
P Even parity */
SBL 1 stop bit */
CL 8 bit data */
A/D Data frame */
REC Error flag clear */
RXE Disable the receive operation */
TXE Disable the transmit operation */
TIE Enable transmit interrupts */
RIE Enable receive interrupts */
}
2. Activation
• Start the U-timer and UART
Start the U-timer 0
Start the UART1 receive operation
Start the UART0 transmit operation
<register name> .<bit name>
UTIMC0 .UTST
SCR1 .RXE
SCR0 . TXE
3. Interrupt
• Transmit interrupt processing
Transmit arbitrary data.
Disable transmit interrupts.
<register name> .<bit name>
SIDR0
SSR0 .TIE
• Receive interrupt processing
Receive the data
Disables reception interrupts
SIDR1
SSR1
.RIE
void Uart_start(void)
{
IO_UTIMC0.bit.UTST = 1;
IO_SCR1.bit.RXE = 1;
IO_SCR0.bit.TXE = 1;
__interrupt void uart0_tx_int(void)
{
IO_SIDR0 = 0xaa;
IO_SSR0.bit.TIE = 0;
}
_interrupt void uart1_rx_int(void)
{
UART_DATA = IO_SIDR1;
IO_SSR1.bit.RIE = 0;
}
/* bit1 = 1
/* bit1 = 1
/* bit0 = 1
UTST Enables the U timer. */
RXE Enable the receive operation */
TXE Enable the transmit operation */
/* Transmit arbitrary data values. /
/* bit0 = 0
TIE Disable transmit interrupts */
/* Store the received data value in the UART_DATA. */
/* bit1 = 1
RIE Disable receive interrupts */
4. Interrupt Vector
Setting the vector table
The interrupt routine must be specified in the vector table.
#pragma intvect uart0_tx_int 28
#pragma intvect uart1_rx_int 29
Caution: Requires clock-related setting and __set_il (numeric values)
setting to be made in advance. See the clock and interrupt chapters.
Note: For the convention of registers, see “FR60Lite Family MB91230 Series Sample I/O Register Files
Usage Guide”.
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Chapter 23 UART
9.Caution
9. Caution
• Mode 1 (asynchronous-multiprocessor) is a mode to connect several slave CPUs to a master CPU. This UART does not
distinguish the data format of the receive data. Therefore, it supports only the master side of the multiprocessor mode.
Since parity check function cannot be used in the mode 1, parity setting bits (SCR0.PEN) - (SCR3.PEN) should always
be set to “0”.
• Since the switching of internal/external baud rate clock by operation clock selection bits (SMR0.CS0) - (SMR3.CS0)
takes effect immediately, perform this operation when the UART is in the idle state.
• To use the SCK pin as a clock input, you need to set operation clock selection bits (SMR0.CS0) - (SMR3.CS0) to “1”,
and select the external clock.
• You can add parity only in the mode 0 (asynchronous - normal). Parity cannot be added in the mode 1 (asynchronousmultiprocessor) and the mode 2 (clock synchronization).
• 7 bit data can be handled only in the mode 0 (asynchronous - normal).Use 8 bit data in the mode 1 (asynchronousmultiprocessor) and the mode 2 (clock synchronization).
• The write operation to the serial input data register (SIDR) means the write to the serial output data register (SODR).
• When transfer direction selection bits (SSR0.BDS) - (SSR0.BDS) are changed after the update of the serial input data
register/serial output data register (SIDR/SODR), the updated input data / output data become invalid.
• The types of receive interrupt causes include the errors (PE, ORE, and FRE) other than the normal receive (RDRF).
The transmit interrupt cause is set to the transmit buffer empty (TDRE).
• In the mode 2 (clock synchronization), the transmit and the receive operations are synchronized, and even if it is only
the receive operation, the write of the value (dummy) to the transmit enable (TXE = 1) and the serial output register
(SODR) is required to start.
• At the reset
The initial values of the serial input register (SIDR) and the serial output data register (SODR) are indeterminate.
• The read/modify/write instructions cannot be used for the serial mode register (SMR). Make sure to write the value that
takes account of the restriction bits (Bit-0, -2, -4, and -5)in Byte, Half-word, or Word.
• Set the communication mode while operation is halted. When the mode setting is performed during operation, the
integrity of transmit/receive data is not guaranteed.
• Do not stop the U-timer during UART operation. Should you stop the U-timer, do so after setting the operation stop
(RXE= “0”, TXE= “0”) and when the operation comes to a complete stop.
• In the synchronous mode, the fastest operation baud rate is the clock at the CLKP divided by 4.
269
Chapter 23 UART
9.Caution
270
Chapter 24 Free-run Timer
1.Overview
Chapter 24 Free-run Timer
1. Overview
The free-run timer consists of a 16-bit timer (up counter) and control circuits.
The free-run timer can be used with the input capture and the output compare.
Internal clock
or
External clock
Clear
Up counter
Overflow
2. Features
•
•
•
•
•
Format: 16-bit up counter
Quantity: 2 (free-run timer 0 and free-run timer 1)
Clock source: 4 internal clocks (1/4, 1/16, 1/32, and 1/64 of CLKP)
External clock (CKI)
Clear factor of the count:
• Software
• Reset
• Compare-match (match of the compare-register value and the count value of the free-run timer)
• Operation start/stop: operations can be started/stopped with software.
• Interrupt:
• Overflow interrupt
• An interrupt generated when the compare clear register value and the count value of the free-run timer match.
• Count value: Readable/writable (write is only possible when the counting stops)
• Others: Operates from immediately after reset.
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Chapter 24 Free-run Timer
3.Configuration Diagram
3. Configuration Diagram
Figure 3-1 Configuration Diagram
Free-run Timer 0
Count clock
0
0
1
1
CLK1-0
0
1
0
1
TCCS0: bit 1-0
CLKP / 4
CLKP / 16
CLKP / 32
CLKP / 64
STOP
0
1
TCCS0: bit 4
Input capture 0-1
IVFE
Count operation
Stop the count operation
0
1
Count value
0
Overflow flag
0
Peripheral clock
CLKP
Timer data register 0
Divider
IVF
TCDT0
Synchronization
circuit
CKI0 /OP0/ P20
1
Free-run Timer 0
interrupt (#55)
TCCS0: bit 6
0
No interrupt requests
1 Interrupt request present
WRITE 0: Flag clear
External clock
External clock
T CCS0: bit 5
Disable interrupts
Enable interrupts
Clear
1
The clock selection
ECLK
0
OR
TCCS0:bit 7
Count value
From the divider
From the outside
1
Output compare 0-1
1
Read of the port
The timer clear request by the
compare value match of the
output compare 0
0
From the port
data register
0
1 (From the output
of the output
compare 0)
OP0 PFR2: bit0
0 General-purpose port
1
OP0
CLR
P21 DDR2: bit0
0
Input only
1 Enable output
TCCS0:bit 2
0
1
No effect
Clears the timer
TCCS0: bit 3
MODE
0
Disable the clear by the compare-match
1
Enable the clear by the compare-match
Notes: When using the output (OP0), the external clock (CKI0) cannot be used because the port is shared.
Figure 3-2 Configuration Diagram
Free-run Timer 1
Count clock
CLK1-0
0 0
0 1
1 0
1 1
STOP
0
1
TCCS1: bit 4
IVFE
Count operation
Stop the count operation
0
Peripheral clock
CLKP
PWC0
PWC1
TCCS1: bit 1-0
CLKP / 4
CLKP / 16
CLKP / 32
CLKP / 64
0
1
Timer data register 1
Divider
IVF
TCDT 1
Synchronization
circuit
External clock
0
1
1
TCCS1: bit 7
OR
From the divider
From the outside
Output compare 2-3
1
Read of the port
The timer clear request by the
compare value match of the
output compare 2
0
From the port
data register
0
1 (From the output
of the output
compare 1)
OP1 PFR2: bit1
0 General-purpose port
1
OP0
P21 DDR2: bit1
Input only
0
1 Enable output
CLR
0
1
TCCS1:bit 2
No effect
Clears the timer
MODE
TCCS1: bit 3
0
Disable the clear by the compare-match
1
Enable the clear by the compare-match
Notes: When using the output (OP1), the external clock (CKI1) cannot be used because the port is shared.
272
Free-run timer 1
interrupt (#56)
1
Count value
ECLK
0
1
TCCS1: bit 6
No interrupt requests
Interrupt request present
WRITE 0: Flag clear
Clear
The clock selection
CKI1/OP1 /P21
0
Overflow
External clock
TCCS1: bit 5
Disable interrupts
Enable interrupts
Chapter 24 Free-run Timer
3.Configuration Diagram
Figure 3-3 Register List
Note: See “Chapter 20 Interrupt Control (Page No.207)” about ICR register and interrupt vectors.
273
Chapter 24 Free-run Timer
4.Registers
4. Registers
4.1 TCCS: Timer Control Register
A register for controlling the operation of the free-run timer.
• TCCS0 (free-run timer 0): Address 0D7h (access: Byte, Half-word, Word)
• TCCS1 (free-run timer 1): Address 0DBh (access: Byte, Half-word, Word)
7
ECLK
0
R/W
6
IVF
0
R (RM1), W
5
IVFE
0
R/W
4
STOP
0
R/W
3
MODE
0
R/W
2
CLR
0
R/W
1
CLK1
0
R/W
0
CLK0
0
R/W
bit
Initial value
Attribute
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit7: Select the count clock
ECLK
0
1
Select the count clock
Internal clock (the peripheral clock divided by n)
External clock (CKI0 and CKI1 pins)
• When you change the setting of the count clock selection bit, do so when other peripheral modules (the output
compare, input capture, etc.) using the output of the free-run timer are stopped.
• When using the external clock, the period of the external clock must be more than double of the peripheral clock
(CLKP). When using the output compare, in order to allow the compare-match output and interrupt generation, the
external clock input of at least 1 clock is required after the compare-match.
• bit6: Interrupt request flag
Status
IVF
Read
Write
0
No interrupt request present
Clear the flag (IVF).
1
Interrupt request present
(Overflow or compare-match)
No effect on operation
• When the count value of the free-run timer overflows, or the clear mode bit (MODE) is “1”, the interrupt request
flag is set to “1” if the count values of the free-run timer and the compare register (OCCP) match and the counter is
cleared.
• To enable the interrupt request, the interrupt enabling bit must be set to do so (IVFE=“1”).
• When the interrupt request flag is set to “1”, and “0” is written at the same time, the interrupt request flag is set to
“1”. (Setting the flag has priority.)
• bit5: Enable interrupt requests
IVFE
0
1
Operation
Disable interrupts
Enable interrupts
• When the interrupt request enabling bit is set to “1”, the interrupt request (IVF) is enabled.
• bit4: Stop counting
STOP
0
1
Operation
Enable counting
Disable count (stop)
• When the count stop bit is set to “1”, the free-run timer stops.
• When the output compare is being used, if the free-run timer stops, the output compare also stops.
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Chapter 24 Free-run Timer
4.Registers
• bit3: Clear mode
MODE
Clear mode
0
Clear the free-run timer by the reset and the clear bit (CLR).
1
Clear the free-run timer by the match with the reset, the clear bit (CLR), and the compare register value
of the output compare (OCCP).
• Set the clear mode of the free-run timer.
• If the clear mode bit is set to “1”, when the count value of the free-run timer and the compare-register value (OCCP)
match, the count value of the free-run timer is cleared to “0000h”.
• The reset and writing “1” to the clear bit (CLR) cause to clear the count value of the free-run timer to “0000h”,
regardless of the setting of the clear mode bit.
• The count value of the free-run timer is only cleared when the free-run timer is running. When the free-run timer is
stopped, clear it by writing “0000h” to the timer data register (TCDT).
• bit2: Clear
CLR
0
1
Operation
No effect on operation
Clear the free-run timer.
• When the clear bit is set to “1”, the count value of the free-run timer is cleared to “0000h”. The clear bit is read as
“1” until the free-run timer is completely cleared.
When the free-run timer is completely cleared, the clear bit is also cleared to “0”.
• When the clear operation of the free-run timer and writing “1” to the clear bit is occurred at the same time, the clear
bit keeps “1”, and after the next time the free-run timer is cleared, it is cleared.
• bit1-bit0: Count clock division ratio selection (when the internal clock is selected)
CLK1
0
0
1
1
CLK0
0
1
0
1
The division ratio of the count clock
Peripheral clock (CLKP) divided by 4
Peripheral clock (CLKP) divided by 16
Peripheral clock (CLKP) divided by 32
Peripheral clock (CLKP) divided by 64
• Select the division ratio of the count clock of the free-run timer.
• Change the division ratio when the setting of the count clock division ratio selection bit is changed. When the
internal clock is selected as the count clock of the free-run timer (count clock selection bit ECLK=“0”), change the
setting when other peripheral modules (output compare, input capture, etc.) using the output of the free-run timer
are stopped.
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Chapter 24 Free-run Timer
4.Registers
4.2 TCDT: Timer Data Register
This register can read 16-bit free-run timer count values.
• TCDT0 (free-run timer 0): Address 0D4h (access: Half-word, Word)
• TCDT1 (free-run timer 1): Address 0D8h (access: Half-word, Word)
15
T15
14
T14
13
T13
12
T12
11
T11
10
T10
9
T9
8
T8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
T7
6
T6
5
T5
4
T4
3
T3
2
T2
1
T1
0
T0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(About attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• When the timer data register is read, the count value of the free-run timer is also obtained.
276
bit
Initial
value
Attribute
bit
Initial
value
Attribute
Chapter 24 Free-run Timer
5.Operation
5. Operation
5.1 Count Operation of the Free-run Timer
By writing to the timer data register, the timer value can be written in the free-run timer. When it is written, make sure that the free-run timer is in the idle state (the count stop bit (TCCS.STOP= 1”)).
(Internal clock)
( (External clock FCLKP
FCLKP/2/2))
External pin
(CKI)
Peripheral
clock (CLKP)
Internal clock
(FCLKP/2)
Count
timing
Count
timing
The count of the
free-run timer
(7 )
The count of the
free-run timer
(8)
FFFFh
The count of
the free-run
timer
(3)
0000 h
Reset
(2)
(5)
(1)
The overflow and the
interrupt request
(2)
Clearing the
free-run timer
Time
Clear by software
Clear by software
(4)
(5)
(1) Reset
(2) Clearing of the free-run timer by reset. (Count value “0000”)
(3) Count-up of the free-run timer
(4) Overflow and interrupt of the free-run timer.
(5) Clearing of the free-run timer by overflow. (Count value “0000”)
(6) Repeat (3) to (5)
(7) The free-run timer counts up at the count clock (the internal clock divided by n).
(8) The free-run timer counts up at the count clock (the external clock synchronized with the internal clock).
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Chapter 24 Free-run Timer
5.Operation
5.2 Various Clear Operations of the Free-run Timer
The count of
the free-run
timer
0000 h
(2)
(3)
(1)
Time
(4)
Reset
Write "0000"
Clear
Clear by software or the
compare-match.
The enable/disable
of the operation
(software)
Operation
stop
Operation stop
Timing of the clear by the compare-match
(Internal clock)
Peripheral
clock (CLKP)
Count
timing
Count value N-1
-
N
Compare value
"0000"
Compare value = N
Compare-match
Clearing the free-run timer
The request of interrupt
Clear operations of the free-run timer (4 types)
(1) Reset
(2) Clear by software
(3) Clear by the compare-match
(4) Writing “0000”
278
"0001"
Chapter 24 Free-run Timer
6.Setting
6. Setting
Table 6-1 Setting Required in Order to Use the Free-run Timer
Setting
Setting of the initialization conditions of the timer
Setting of the count clock
Selection of the internal clock
Selection of the external clock
Start the count operation
In the case of the external clock
Set the clock input pin (CKI) as the input.
Setting Registers
Timer control register (TCCS0-TCCS1)
Setting
Procedures *
See 7.4
See 7.1
See 7.2
See 7.3
Port function register (PFR2)
Data direction register (DDR2)
See 7.2
*: For the setting procedure, refer to the section indicated by the number.
Table 6-2 Setting Required to Enable the PPG Interrupt
Setting
Setting of the free-run timer interrupt vector,
and the free-run timer interrupt level
Setting of the free-run timer interrupt
Clearing interrupt requests
Enabling interrupt requests
Setting Registers
Setting
Procedures *
See “Chapter 20 Interrupt Control (Page
No.207)”.
See 7.5
Timer control register (TCCS0-TCCS1)
See 7.7
*: For the setting procedure, refer to the section indicated by the number.
Table 6-3 Setting Required to Stop the PPG
Setting
Setting of the free-run timer stop bit
Setting Registers
Timer control register (TCCS0-TCCS1)
Setting
Procedures *
See 7.8
*: For the setting procedure, refer to the section indicated by the number.
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Chapter 24 Free-run Timer
7.Q & A
7. Q & A
7.1 What are the types of the internal clock, and how do I select?
There are 4 types of internal clocks, and these are set by the clock selection bits (TCCS0.ECLK), and (TCCS1.ECLK),
and the count clock bits (TCCS0.CLK [1:0]) and (TCCS1.CLK [1:0]).
Setting
Count period
FCLKP =
FCLKP = 16MHz
32MHz
Internal clock
Clock selection
Bit (ECLK)
Count clock bit
(CLK [1:0])
To select FCLKP/4
Set to “0”
Sets to “00”
125 ns
250 ns
To select FCLKP/16
Set to “0”
Set to “01”
0.5 µs
1 µs
To select FCLKP/32
Set to “0”
Set to “10”
1 µs
2 µs
To select FCLKP/64
Set to “0”
Set to “11”
2 µs
4 µs
7.2 How do I select the external clock?
Set with clock selection bits (TCCS0.ECLK), (TCCS1.ECLK), data direction bits, and port function bits.
To use the external
clock input
Free-run Timer 0
Setting
The clock
selection
bit (ECLK)
to “1”
Free-run Timer 1
The data direction
bit
(DDR2.P20)
to “0”
The data direction
bit
(DDR2.P21)
to “0”
Pins
The port function bit CKI0
(PFR2.OP0)
to “0”
Count
Cycle
Over 2/FCLKP
The port function bit CKI1
(PFR2.OP1)
to “0”
7.3 How do I enable / disable the count operation of the free-run timer?
Set with count operation bits (TCCS0.STOP), (TCCS1.STOP).
Operation
To enable the free-run timer
To stop the free-run timer
280
Count operation bit (STOP)
Set to “0”
Set to “1”
Chapter 24 Free-run Timer
7.Q & A
7.4 How do I clear the free-run timer?
You can clear the free-run timer by performing the following operations:
• Set with clear bits (TCCS0.CLR), (TCCS1.CLR).
Operation
Clear bit (CLR)
To clear the free-run timer
Write “1”
• How to clear the free-run timer when the free-run timer value and the compare-register value match
Set with the timer initialization condition bit (TCCS0.MODE).
Operation
To clear the free-run timer at the compare-match
Timer initialization condition bit (MODE)
Set to “1”
The setting of the output compare is also required. (See “Chapter 26 Output Compare (Page No.297)”.)
• Reset.
When you reset (the INIT pin input, the watchdog reset, the software reset), the free-run timer is cleared.
• Write “0000H” while the free-run timer is stopped.
The count value will be set to “0000 H”, when “0000 H” is written while the free-run timer is stopped.
• With the overflow of the free-run timer, the count value returns to “0000 H”.
7.5 What interrupt registers are used?
Setting of the free-run timer interrupt vector and the free-run timer interrupt level
The relationship among the free-run timer number, interrupt levels and vectors is shown in the table below.
See “Chapter 20 Interrupt Control (Page No.207)” about the details of interrupt levels and interrupt vectors.
Number
Free-run Timer 0
Free-run Timer 1
Interrupt Vectors (default)
#55
Address: 0FFF20h
Interrupt level setting bits (ICR[4:0])
Interrupt level register (ICR39)
Address: 00467h
#56
Address: 0FFF1Ch
Interrupt level register (ICR40)
Address: 00468h
Since the interrupt request flags (TCCS0.IVF) and (TCCS1.IVF) are not cleared automatically, make sure to clear them
with software before returning from the interrupt process. (Write “0” in the IVF bit)
7.6 Interrupt Types
There is only one type of interrupt, and it is generated at the overflow of the free-run timer. (Selection is not required)
7.7 How do I enable interrupts?
Enable interrupt requests, interrupt request flag
Use interrupt request enable bits (TCCS0.IVFE) and (TCCS1.IVFE) to enable interrupts.
Interrupt request permission bit (IVFE)
Disable interrupts
Enable interrupts
Set to “0”
Set to “1”
Use interrupt request bits (TCCS0.IVF) and (TCCS1.IVF) to clear interrupt requests.
Clear interrupt requests
Interrupt request bit (IVF)
Write “0”
7.8 How do I stop the free-run timer?
Set with count operation bits (TCCS0.STOP), (TCCS1.STOP).
See “7.3 How do I enable / disable the count operation of the free-run timer? (Page No.280)”.
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Chapter 24 Free-run Timer
8.Sample Programs
8. Sample Programs
Setting Procedure Example 1
Program Example 1
The free-run timer 0, clock = CLKP / 2^6,
Count the number of overflows in the interrupt process.
<Initial settings>
1
• Control of free-run timer ch0
Control register settings
The clock selection>>
Interrupt request flag>>
Enable interrupt requests>>
Count operation >>
Whether timer is initialized >>
Clear TCDT >>
Count clock >>
Setting the timer data value
2
• Interrupt settings
Setting the interrupt level
I flag setting
3
void FREE_RUN_TIMER0_sample(void)
{
FREERUN0_initial();
FREERUN0_start();
}
void FREERUN0_initial(void)
{
IO_TCCS0.byte = 0x33;
TCCS0
.ECLK
.IVF
.IVFE
.STOP
.MODE
.CLR
.CLK1-0
TCDT0
IO_TCDT0 = 0x0000;
ICR39
IO_ICR[39].byte = 0x10;
(CCR)
__EI();
•Setting of variables
/* Value = 0011_0011 */
/* bit7 = 0
ECLK Internal clock source */
/* bit6 = 0
IVF Interrupt request flag */
/* bit5 = 1
IVFE Enable interrupts. */
/* bit4 = 1
STOP Disable count */
/* bit3 = 0
MODE Initialized by reset and clear bit. */
/* bit2 = 0
CLR Initialize the free-run timer value (to zero). */
/* bit1-0 = 11
CLK1-0 Count clock CLKP/64 */
/* Initialize timer data value */
/* Free-run timer 0 Interrupt level setting (any value) */
/* Enable interrupts.
*/
count = 0;
}
<Activation>
• Activate free-run timer ch0
Activates the count operation
void FREERUN0_start(void)
<register name>. <bit
name>
TCCS0 .STOP
{
IO_TCCS0.bit.STOP = 0;
/* bit4 = 0
STOP Enable count */
}
<Interrupt>
• Interrupt processing
Clearing the interrupt request flags
(User program)
The count of the variables
__interrupt void FREE_RUN_TIMER0_int(void)
<register name>. <bit
name>
TCCS0 .IVF
{
IO_ICCS0.bit.IVF = 0;
/* bit6 = 0
IVF Clear the overflow flag */
count++;
}
<Interrupt vector>
Setting the vector table
The interrupt routine must be specified in the vector table.
#pragma intvect FREE_RUN_TIMER0_int 55
Caution: Requires clock-related setting and __set_il (numeric values)
setting to be made in advance. See the clock and interrupt chapters.
Note: For the convention of registers, see “FR60Lite Family MB91230 Series Sample I/O Register Files Usage Guide”.
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Chapter 24 Free-run Timer
9.Caution
9. Caution
• Clearing the free-run timer
• When you reset (the INIT pin input, the watchdog reset, the software reset), the counter is initialized to “0000” and
the counting is stopped.
• When the free-run timer is cleared by software, the counter is cleared and the clear request is generated almost at
the same time. If the counter is cleared by the compare-match, it is cleared when it is counted up.
• After writing “1” in the clear bit (CLR), this request (CLR=“1”) is cleared at the same clear timing of the free-run
timer. When the clear operation of this CLR and writing “1” to the clear bit is occurred at the same time, the clear
bit (CLR) keeps “1”, and after the next time the timer is cleared, it is cleared. (As a result, the free-run timer is
cleared twice.)
• The counter clear operation (the software, the overflow, and the compare-match) of the free-run timer is enabled
while the free-run timer is counting. To clear while the free-run timer is stopped, write 0000H in the timer count
data register.
• Write to the timer data register
When writing the value in the free-run timer, make sure to do so while the free-run timer is stopped (STOP=“0”), and
with the word access.
• External clock operation
• The pulse width required for the external clock is 2/FCLKP minimum.
• When using the external clock, the timing of the compare-match output and the interrupt occurrence is as the same
as the next count clock timing after the compare-match. Therefore, to allow the compare-match output and interrupt
generation, the external clock input of at least 1 clock is required after the compare-match.
• Read/modify/write
The interrupt request flag (IVF) can always read “1” in read/modify/write.
• Interrupt request flag
If the interrupt request flag set timing and clear timing are simultaneous, the flag setting operation overrides the flag
clearing operation.
283
Chapter 24 Free-run Timer
9.Caution
284
Chapter 25 Input Capture
1.Overview
Chapter 25 Input Capture
1. Overview
Input Capture records the free-run timer count value using timing detected from an external signal. It is then possible to
calculate the time between signals using the record of the repeated count.
Free-run timer 0
pin
Edge
detection
circuit
Capture
Buffer
2. Features
•
•
•
•
•
Format: Edge detection circuit + 16 bit buffer (capture register)
Quantity: 2 (Input capture 0, input capture 1)
Edge Detection: Rising/falling/both edges
Interrupt: Edge detection
Capture value: Timer count value (0000H-FFFFH)
• Timer: Uses free-run timer 0
• Precision: 4/FCLKP, 16/FCLKP, 32/FCLKP, 64/FCLKP (Free-run timer count clock)
Captured signal
Free-run
timer
count value
A
t
Buffer value
A
285
Chapter 25 Input Capture
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Input capture 0-1
Edge detection polarity
From port
data register
EG01-00
ICS01:bit 1-0
0 0
No edge detection
0 1
Rising edge detection
1 0
Falling edge detection
1 1
Both edges detection
P06 DDR0: bit 6
Input only
0
1 Enable Output
ICE0
Capture data register 0
0
1
ICS01:bit 4
Disable interrupts
Enable interrupts
IPCP0 (CP15-CP0)
Edge detection circuit
IC0 / P06
Port read
ICP0
Capture
Free-run timer 0
0
ICS01:bit 6
0 Interrupt request not present
1
Interrupt request present
WRITE 0: Flag clear
Input capture 0
Interrupt (#57)
1
TCDT
Port read
Edge detection circuit
IC1 / P07
P07 DDR0: bit 7
Input only
0
1 Enable Output
Capture
ICP1
IPCP1 (CP15-CP0)
Edge detection polarity
From port
data register
EG11-10
ICS01: bit 3-2
0 0
No edge detection
0 1
Rising edge detection
1 0
Falling edge detection
1 1
Both edges detection
0
ICS01:bit 7
0 Interrupt request not present
1
Interrupt request present
WRITE 0: Flag clear
Capture data register 1
Input capture 1
Interrupt (#58)
1
ICE1
0
1
ICS01:bit 5
Disable interrupts
Enable interrupts
Figure 3-2 Register List
Note: For information about ICR registers and interrupt vectors, see “Chapter 20
No.207)”.
286
Interrupt Control (Page
Chapter 25 Input Capture
4.Register
4. Register
4.1 IPCP: Input Capture Data Register
A register that, using changes in an external signal as a trigger, stores the free-run timer count and can read it out later.
• IPCP0 (Input capture 0): Address 0DEh (Access: Half-word, Word)
• IPCP1 (Input capture 1): Address 0DCh (Access: Half-word, Word)
15
CP15
X
R/WX
14
CP14
X
R/WX
13
CP13
X
R/WX
12
CP12
X
R/WX
11
CP11
X
R/WX
10
CP10
X
R/WX
9
CP9
X
R/WX
8
CP8
X
R/WX
7
CP7
X
R/WX
6
CP6
X
R/WX
5
CP5
X
R/WX
4
CP4
X
R/WX
3
CP3
X
R/WX
2
CP2
X
R/WX
1
CP1
X
R/WX
0
CP0
X
R/WX
bit
Initial value
Attribute
bit
Initial value
Attribute
(For information on attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• Stores the free-run timer 0 count value for the input signal from external pins (IC0,IC1) using the signal change (edge)
selected by active edge selection bits (ICS01.EG[01:00]), (ICS01.EG[11:10]).
• Input capture 0 and input capture 1 store the count value of the free-run timer.
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Chapter 25 Input Capture
4.Register
4.2 ICS01: Input Capture Control Register
A register for controlling input capture
• ICS01 (Input capture 0-1): Address 0E3h (Access: Byte)
7
ICP1
0
R(RM1),W
6
ICP0
0
R(RM1),W
5
ICE1
0
R/W
4
ICE0
0
R/W
3
EG11
0
R/W
2
EG10
0
R/W
1
EG01
0
R/W
0
EG00
0
R/W
bit
Initial value
Attribute
(For information on attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit7: Input capture 1 interrupt request flag
Status
ICP1
0
1
Read
Write
No interrupt request
Interrupt request present (edge detection present)
Clear flag
No effect on operation
• When the signal change (edge) selected by the active capture edge selection bit (EG[11:10]) is detected on the input
from an external pin, the flag becomes “1”.
• To activate the interrupt request, the interrupt request permission setting (ICE1=“1”) is necessary.
• If the timing of the interrupt request flag becoming “1” and the writing of “0” occur simultaneously, the interrupt
request flag will become “1”.
• bit6: Input capture 0 interrupt request flag
Status
ICP0
0
1
Read
No interrupt request
Interrupt request present
Write
Clear flag
No effect on operation
• When the signal change selected by the active capture edge selection bit (EG[01:00]) is detected on the input from
an external pin (CS0), the flag becomes “1”.
• To activate the interrupt request, the interrupt request permission setting (ICE1=“1”) is necessary.
• If the timing of the interrupt request flag becoming “1” and the writing of “0”occur simultaneously, the interrupt
request flag will become “1”.
• bit5: Input capture 1 interrupt request permission
ICE1
0
1
Operation
Interrupt disabled
Interrupt enabled
• If input capture 1 interrupt request permission bit is set to “1”, input capture 1 interrupt request ICP1 will be
enabled.
• bit4: Input capture 0 interrupt request permission
ICE0
0
1
Operation
Interrupt disabled
Interrupt enabled
• If input capture 0 interrupt request permission bit is set to “1”, input capture 0 interrupt request ICP0 will be
enabled.
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Chapter 25 Input Capture
4.Register
• bit3-bit2: Input capture 1 active edge selection
EG11
0
0
1
1
EG10
0
1
0
1
Edge selection
Stop input capture
Rising edge
Falling edge
Both edges (rising edge and falling edge)
• Select the active capture edge for the input capture signal from external pin (CS1)
• If the active edge selection bit is “00”, input capture 1 is stopped.
• bit1-bit0: Input capture 0 active edge selection
EG01
0
0
1
1
EG00
0
1
0
1
Edge selection
Stop input capture
Rising edge
Falling edge
Both edges (rising edge and falling edge)
• Select the active capture edge for the input capture signal for external pin (CS0).
• When the active edge selection bit is “00”, input capture 0 is stopped.
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Chapter 25 Input Capture
5.Operation
5. Operation
The input capture operation is described below.
5.1 Capture Timing, Interrupt Timing
Input capture
(1)
Peripheral
clock (CLKP)
(2)
Active edge
Free-run timer 0
N
N+1
(3)
Capture register
Interrupt
request
N+1
(4)
FFFFh
Free-run
timer 0
count
0000 h
Reset
Input
capture
Interrupt
request
(1)
(2)
(3)
(4)
290
Rising edge of input signal
Internal signal generated by edge detection (synchronous with peripheral clock)
Store free-run timer value in capture register (capture)
Input capture interrupt generation (ICP(0-1)=“1”)
Time
Chapter 25 Input Capture
5.Operation
5.2 Input Capture Edge Specification and Operation
Overflow
(IVF)
FFFFh
Count value C
Free-run
timer 0
count value
Count value B
Count value A
Count value D
0000 h
Time
Reset
Input capture
Rising
edge
Capture data
register
(1)
(2)
Indeterminate
Interrupt
request
Count value A
(3)
Input capture
Falling
edge
(4)
Capture data
register
(5)
Count value C
Indeterminate
Interrupt
request
(6)
Input capture
Both
edges
Capture data
register
7)
(7)
(11)
(8)
Indeterminate
Interrupt
request
Count value B
Clearing of flags in software
(9)
(12)
Count value D
(13)
(10)
• When specifying rising edge
(1)
(2)
(3)
Detection of rising edge of input signal
Storage of free-run timer value in capture register (capture)
Input capture interrupt generation
• When specifying falling edge
(4)
(5)
(6)
Detection of input signal falling edge
Storage of free-run timer value in capture register (capture)
Input capture interrupt generation
• Both edges
(7)
(8)
(9)
(10)
(11)
(12)
(13)
Detection of input signal rising edge
Storage of free-run timer value in capture register (capture)
Input capture interrupt generation
Clear interrupt request flag (ICS01.ICP0), (ICS01.ICP1) in software
Detection of input signal falling edge
Storage of free-run timer value in capture register (capture)
Input capture interrupt generation
291
Chapter 25 Input Capture
6.Settings
6. Settings
Table 6-1 Settings Necessary for Using Input Capture
Settings
Free-run timer settings
Free-run timer activation
Input pin IC0-IC1 settings
Active edge polarity selection for external input
Setting register
See “Chapter 24 Free-run Timer (Page No.271)”
Data direction register (DDR0)
Input capture control register (ICS01)
Setting
procedure*
–
7.1
7.2
*: For the setting procedure, refer to the section indicated by the number.
Table 6-2 Required Settings for PPG Interrupt
Settings
Input Capture interrupt vector,
Input capture interrupt level settings
Input capture interrupt settings
Interrupt request clear
Interrupt request permission
Settings register
Setting
procedure*
See “Chapter 20 Interrupt Control (Page No.207)”
7.3
Input capture control register (ICS01)
7.5
*: For the setting procedure, refer to the section indicated by the number.
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Chapter 25 Input Capture
7.Q&A
7. Q&A
7.1 What are the varieties of active edge polarity for external input, and how do I select
them?
The active edge polarity varieties consist of rising, falling, and both, for a total of 3, and
are set using the external input active edge selection bit (ICS01.EG[01:00]) and (ICS01:EG[11:10]).
External input active edge polarity bit
(EG[01:00]), (EG[11:10])
Select “00”
Select “10”
Select “11”
Operation
To select rising edge
To select falling edge
To select both edges
7.2 What about setting the external input pins (IC0, IC1)?
Use the data direction bit (DDR0.P06), (DDR0.P07).
Operation
To set it to the external input pins (IC0, IC1)
Data direction bit (P06),([P07])
Set to “0”
7.3 What about interrupt-related registers?
Input capture interrupt vector and input capture interrupt level settings
The relationship between input capture number, interrupt level, and vector is explained in the following table.
For more information on interrupt level and interrupt vectors, see “Chapter 20 Interrupt Control (Page No.207)”.
Number
Input
Capture 0
Interrupt vector (Default)
#57
Address: 0FFF18h
Interrupt level setting bit (ICR[4:0])
Interrupt level register (ICR41)
Address: 00469h
Input
Capture 1
#58
Address: 0FFF14h
Interrupt level register (ICR42)
Address: 0046Ah
Interrupt request flags (ICS01.ICP0), (ICS01.ICP1) are not automatically cleared, so please set the input capture interrupt
request flag (ICP1, ICP0) to “0” to clear them before returning from interrupt processing.
7.4 What are the types of interrupts?
There is only one kind of interrupt, and it is generated by input signal edge detection.
7.5 How do I enable interrupts?
Interrupt request permission, interrupt request flag
Interrupts are enabled via interrupt request permission bit (ICS01.ICE0), (ICS01.ICE1).
Disable interrupts
Enable interrupts
Interrupt request permission bit (ICE0), (CE1)
Set to “0”
Set to “1”
Clearing of interrupt requests is done using interrupt request bit (ICS01.ICP0), (ICS01.ICP1).
Interrupt request clear
Interrupt request bit (ICP0), (ICP1)
Write “0”
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Chapter 25 Input Capture
7.Q&A
7.6 How do I measure the pulse width of the input signal?
• "H" Width measurement:
Specify both edges for edge detection.
First detect the rising edge, then detect the falling edge.
Pulse width = {value recorded during falling (input capture register value)
+ “10000h” × Overflow frequency
– value recorded during rising (input capture register value)}
× Count clock width of free-run timer
Example: value recorded during falling = 2320h, Value recorded during rising = A635h,
Overflow frequency = 1, count clock = 125ns
==> pulse width = (2320h+10000h-A635h) × 125ns = 3997.375µs
• Cycle measurement:
Specify rising (or falling) for edge detection.
Detect edge 2 times.
Cycle = {Second recorded value (input capture register value)
+ “10000h” × Overflow frequency
– First recorded value (input capture register value)}
× Count clock width of free-run timer
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Chapter 25 Input Capture
8.Sample Programs
8. Sample Programs
Setting procedure example 1
Program example 1
Detect rising edge of IC0 input pulse and record free-run timer value.
Do this twice and measure the time from trigger to trigger. However, the read
out of the capture value and the calculation process are interrupt processes.
void INPUT0_sample_1(void)
{
freerun0_initial();
INPUT0_initial();
INPUT0_start();
freerun0_start();
}
1. Initial value
• Control of Free-run timer ch0
Control register settings
Clock selection>>
Interrupt request flag>>
Interrupt request enabled>>
Count operation>>
Timer initialization conditions>>
TCDT clear>>
Count clock>>
Timer data value settings
void freerun0_initial(void)
{
IO_TCCS0.byte = 0x10;
TCCS0
.ECLK
.IVF
.IVFE
.STOP
.MODE
.CLR
.CLK1-0
TCDT0
IO_TCDT0 = 0x0000;
/* Set value=0001_0000 */
/* bit7 = 0
ECLK Internal clock source */
/* bit6 = 0
IVF Interrupt request flag */
/* bit5 = 0
IVFE Interrupt disabled*/
/* bit4 = 1
STOP count disabled */
/* bit3 = 0
MODE reset, clear bit initialization */
/* bit2 = 0
CLR Free-run timer value initialization (none) */
/* bit1-0 = 00
CLK1-0 Count clock CLKP/4=32MHz/4 */
/* Timer data value initialization */
}
• Port
Port IC0 input settings
•Input capture control
Control register settings
Interrupt request flag>>
Interrupt request enabled>>
ch1 active edge polarity selection>>
ch0 active edge polarity selection>>
• Interrupt settings
Interrupt level settings
I flag settings
• Variable settings
void INPUT0_initial(void)
{
IO_PORT1.IO_DDR0.byte = 0x00;
Register name . Bit name
DDR0 .P22
/* DDR0 IC0(P06) input */
ICS01
.ICP1,ICP0
.ICE1,ICE0
.EG11,EG10
.EG01,EG00
IO_ICS01.byte = 0x01;
/* Set value=0000_0001 */
/* bit7-6 = 00
ICP1 C0 No active edge detection */
/* bit5-4 = 00
ICE1 C0 Interrupt disabled */
/* bit3-2 = 00
EG11 CEG10 ch1 no edge detection */
/* bit1-0 = 01
EG01 CEG00 ch0 rising edge detection */
ICR41
(CCR)
IO_ICR[41].byte = 0x10;
__EI();
count = 0;
/* Input capture ch0 interrupt level setting (any value) */
/* Interrupt enabled */
}
2. Activation
• Activating input capture ch0
Interrupt control
• Activating Free-run timer ch0
Activating count operation
void INPUT0_start(void)
{
IO_ICS01.bit.ICE0 = 1;
}
void freerun0_start(void)
Register name . bit name
ICS01 .ICE0
Register name . bit name
TCCS0 .STOP
/* bit4 = 1
ICE0 ch0 interrupt enabled */
/* bit4 = 0
STOP count enabled */
{
IO_TCCS0.bit.STOP = 0;
}
3. Interrupts
• Interrupt processing
Clear interrupt request flag
(User program)
••••••••••
4. Interrupt vector
Vector table settings
__interrupt void INPUT0_int(void)
{
IO_ICS01.bit.ICP0 = 0;
/* bit6 = 0
ICP0 Clear active edge detection flag */
if(count==0)
data1 = IO_IPCP0;
/* Record free-run timer value (first) */
else if(count==1) {
data2 = IO_IPCP0;
/* Record free-run timer value (second) */
cycle = (data2-data1)*125;
/* Measure time.*/
}
count++;
}
Interrupt routine must be specified in vector table.
#pragma intvect INPUT0_int 57
Note: Clock related settings and __set_il(numeric values) settings must be
done beforehand. See the sections on the clock and on interrupts.
Note: For information on register conventions, refer to the “FR60Lite Family MB91230 Series Sample I/O Register Files
Usage Guide”.
Register name . bit name
ICS01 .ICP0
295
Chapter 25 Input Capture
9.Caution
9. Caution
• Input capture register
The value of the input capture register during reset is indeterminate.
Read out of the input capture register must always be done using 16 or 32 bit access.
• Read modify write
Input capture interrupt request bit (ICP0), (ICP1) will be read as “1” when read with read modify write.
296
Chapter 26 Output Compare
1.Overview
Chapter 26 Output Compare
1. Overview
Output compare is a feature that compares the value set to the compare register with the count value of the free-run timer,
and reverses the level of the pins when they are equal.
Pin 0 0
Match
Compare00
Compare
Latch
Toggle
Output
Clear
Free-run Timer
Latch
Pin 1 1
Compare
Compare11
Match
2. Features
• Output wave form: Toggle output 4 channel
T1 or T(max.)
T1
(OP0 Pin/OP2 Pin)
(OP1 Pin/OP3 Pin)
T2
PWM Output
2 channel
(OP1/OP3)
T2
T1
• Type:
16 bit compare register × 2 + Comparison circuit
• Compatible timers: Compare register 0 and compare register 1 use free-run timer 0
Compare register 2 and compare register 3 use free-run timer 1
• Quantity:
2 groups (compare register (0-1) and compare register (2-3))
• Operation on compare match:
• Reversal of pin output value (toggle output)
• Free-run timer clear (0,2 only)
• Interrupt generation
• Count precision:
4/FCLKP, 16/FCLKP, 32/ FCLKP, 64/ FCLKP (dependent on free-run timer)
• Toggle change width (T): 1 x count precision - 10000H x count precision
• Interrupt:
• Other:
Compare-match interrupt
• Setting of initial output level value is possible (“H”/“L”)
• Pins not used for OP output can be used as general-use ports
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Chapter 26 Output Compare
3.Configuration Diagram
3. Configuration Diagram
Figure 3-1 Configuration Diagram
Output Compare 0-1
ICE0 OCS01: bit4
0 Disable interrupts
1 Enable interrupts
ICP0 OCS01: bit6
0 Interrupt request not present
1 Interrupt request present
Write 0: Flag clear
CST 0 OCS01: bit0
0 Disable compare operation
1 Enable compare operation
Compare register 0
OT D0 OCS01: bit8
0
Low fixed
1
High fixed
* Compare operation only
writable when stopped
OCCP0
IVF
TCCS0: bit6
0 Overflow not present
Overflow present
1
OCU0 Interrupt (#59)
External clock (for free-run timer 0)
General-use port read
OP0 PFR2: bit0
0 General-use Port
1
OP0
0
From general-use
port register
Compare
0
Free-run timer 0
TCDT0
0
OP0/CKI0/P20
1
CMOD
OCS01: bit12
0
OCCP1 match alone inverts OP1 latch.
1
OCCP0 or OCCP1 match inverts OP1 latch.
1
1
CLR TCCS0: bit2
0
No effect
1
Clear
Latch
Match -> Latch
reversal
0
Match -> Latch reversal
Compare
1
OR
OP1/CKI1/P21
Latch
From general-use
port register
Compare register 0
0
OP1 PFR2: bit1
0 General-use Port
1
OP1
OT D1 OCS01: bit9
0 Low fixed 1c
1
High fixed
* Compare operation only
writable when stopped
OCCP1
CST 1 OCS01: bit1
0 Disable compare operation
1 Enable compare operation
General-use port read
External clock (for free-run timer 1)
0
ICP1 OCS01: bit 7
0 Interrupt request not present
1 Interrupt request present
Write 0: Flag clear
T CCS0 : bit 3
MODE
0
No clear on compare-match
1
Clear on compare-match
OCU1 Interrupt (#60)
1
ICE1 OCS01: bit5
0 Disable interrupts
1 Enable interrupts
Figure 3-2 Configuration Diagram
Output Compare 2-3
ICE0 OCS23: bit4
0 Disable interrupts
1 Enable interrupts
0
ICP0 OCS23: bit6
0 Interrupt request not present
1 Interrupt request present
Write 0: Flag clear
OCU2 Interrupt (#61)
1
To PWC0
General-use port read
CST 0
OCS23: bit0
0 Disable compare operation
1 Enable compare operation
Compare register 2
OT D0 OCS23: bit8
0
Low fixed
1
High fixed
* Compare operation only
writable when stopped
OCCP2
IVF
TCCS1: bit6
0 Overflow not present
Overflow present
1
OP0 PFR2: bit2
0 General-use Port
OP0
1
0
From general-use
port register
Compare
0
Match -> Latch
reversal
0
Free-run timer 1
TCDT1
1
1
CLR TCCS1: bit2
No effect
0
Clear
1
0
Compare
1
Compare register 3
OCCP3
CST 1 OCS23: bit1
0 Disable compare operation
1 Enable compare operation
Latch
1
Match -> Latch reversal
OR
OP2/PWI0/P22
CMOD
OCS23: bit12
0
OCCP1 match alone inverts OP1 latch.
1
OCCP0 or OCCP1 match inverts OP1 latch.
1
Latch
From general-use
port register
OT D1 OCS23: bit9
Low fixed
0
High fixed
1
* Compare operation only
writable when stopped
OP3/PWI1/P23
0
OP1 PFR2: bit3
0 General-use Port
1
OP1
General-use port read
To PWC1
0
T CCS: bit 3
MODE
No clear on compare-match
0
Clear on compare-match
1
298
ICP1 OCS23: bit7
0 Interrupt request not present
1 Interrupt request present
Write 0: Flag clear
1
ICE1 OCS23: bit5
0 Disable interrupts
1 Enable interrupts
OCU3 Interrupt (#62)
Chapter 26 Output Compare
3.Configuration Diagram
Figure 3-3 Register List
Note: For information ICR about registers and interrupt vectors, see “Chapter 20
No.207)”.
Interrupt Control (Page
299
Chapter 26 Output Compare
4.Registers
4. Registers
4.1 OCS01: Output Control Register 01
A register for controlling the operation of output compare 01.
• OCS01 (Output compare 0-1): Address 0EEh (Access: Byte, Half-word, Word)
15
–
1
R1/W1
14
–
1
R1/W1
13
–
1
R1/W1
12
CMOD
0
R/W
11
–
1
R1/W1
10
–
1
R1/W1
9
OTD1
0
R/W
8
OTD0
0
R/W
7
ICP1
0
R(RM1),W
6
ICP0
0
R(RM1),W
5
ICE1
0
R/W
4
ICE0
0
R/W
3
–
1
R1/W1
2
–
1
R1/W1
1
CST1
0
R/W
0
CST0
0
R/W
bit
Initial Value
Attribute
bit
Initial Value
Attribute
(For information on attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit15-bit13: undefined Writing does not affect the operation. The read out value is “1”.
• bit12: Reverse Mode
CMOD
0
1
Operation Mode
Independent operation (the output level reversal operation of pins OP0-OP1 is independent)
Combined operation
(OP1 output pin level is inverted when output compare 0 or output compare 1 is matched in the
compare operation.)
• Specifies the output level reversal operation of pin OP1 when free-run timer count value TCDT0 matches compare
registers OCCP0, OCCP1.
• When the reverse mode bit is set to “1”, the operation is as follows.
OP0 pin: output reverses when matches compare register 0 (OCCP0)
OP1 pin: output reverses when matches compare register 1 (OCCP1)
• When the reverse mode bit is set to “0”, the operation is as follows.
OP0 pin: output reversal when matches compare register 0(OCCP0)
OP1 pin: output reversal when matches compare register 0 (OCCP0) or compare register 1 (OCCP1)
Note: Reversal mode does not allow interrupts, even with cooperative operation (CMOD=“1”).
• For output from pins OP0-OP1, port PFR2 must be set.
• bit11-bit10: Undefined Writing does not affect the operation. The read value is “1”.
• bit9: Pin-level settings (output compare 1)
OTD1
0
1
Operation
Set the output level of pin OP1 to “L”
Set the output level of pin OP1 to “H”
To perform output on pin OP1, general-purpose port settings must be performed.
• bit8: Pin-level settings (output compare 0)
OTD0
0
1
Operation
Set the output level of pin OP0 to “L”
Set the output level of pin OP0 to “H”
• To perform output on pin OP0, general-purpose port settings must be performed.
300
Chapter 26 Output Compare
4.Registers
• bit7: Interrupt request flag (output compare 1)
ICP1
0
1
Status
Read
Interrupt request not present
Interrupt request present
Write
Clear flag (ICP1)
No effect on operation
• If free-run timer count value TCDT0 matches the output compare register OCCP1, it becomes “1”.
• Interrupt request is enabled when the interrupt permission bit (ICP1) is set to “1”.
• If the timing of the interrupt request flag becoming “1” and the writing of “0” are the same, the interrupt request
flag will become “1” (flag setting is given priority).
• When using an external clock as the free-run timer operation clock, at least one external clock input is necessary
after compare match for output compare-match output and interrupt generation.
• bit6: Interrupt request flag (output compare 0)
ICP0
0
1
Status
Read
Interrupt request not present
Interrupt request present
Write
Clear flag (ICP0)
No effect on operation
• If free-run timer count value TCDT0 matches output compare register OCCP0, it becomes “1”.
• Interrupt request is enabled when the interrupt permission bit (ICP0) is “1”.
• When the timing of the interrupt request flag becoming “1”, and the writing of “0” are simultaneous, the interrupt
request flag becomes “1” (flag setting is given priority).
• When using an external clock as the free-run timer operation clock, at least one external clock input is necessary
after compare match for output compare-match output and interrupt generation.
• bit5: Interrupt request enabled (output compare 1)
ICE1
0
1
Status
Disable output compare 1 interrupt requests
Enable output compare 1 interrupt requests
• bit4: Enable interrupt requests (output compare 0)
ICE0
0
1
Status
Disable output compare 0 interrupt requests
Enable output compare 0 interrupt requests
• bit3-bit2: Undefined Writing does not affect the operation. The read value is always “1”.
• bit1: Enable operation requests (output compare 1)
CST1
0
1
Operation
Stop operation of output compare 1
Enable operation of output compare 1
• A bit that enables a comparison operation between the free-run timer count value and the output compare register
(TCDT0 and OCCP1).
• Before enabling the operation, always set a value to compare register OCCP1.
• If you stop the free-run timer, output compare also stops.
301
Chapter 26 Output Compare
4.Registers
• bit0: Enable operation requests (output compare 0)
CST0
0
1
Operation
Disable output compare 0 operation
Enable output compare 0 operation
• A bit that enables a comparison operation between the free-run timer count value and the output compare register
(TCDT0 and OCCP0).
• Before enabling the operation, always set a value to compare register OCCP0.
• If you stop the free-run timer, output compare also stops.
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Chapter 26 Output Compare
4.Registers
4.2 OCS23: Output Control Register 23
A register for controlling the operation of output compare 2-3.
• OCS23 (Output compare 2-3): Address 0ECh (Access: Byte, Half-word, Word)
15
–
1
R1/W1
14
–
1
R1/W1
13
–
1
R1/W1
12
CMOD
0
R/W
11
–
1
R1/W1
10
–
1
R1/W1
9
OTD3
0
R/W
8
OTD2
0
R/W
7
ICP3
0
R(RM1),W
6
ICP2
0
R(RM1),W
5
ICE3
0
R/W
4
ICE2
0
R/W
3
–
1
R1/W1
2
–
1
R1/W1
1
CST3
0
R/W
0
CST2
0
R/W
bit
Initial Value
Attribute
bit
Initial Value
Attribute
(For information on attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit15-bit13: UndefinedWriting does not affect the operation.
• The read value is always “1”.
• bit12: Reverse mode
CMOD
0
1
Operation mode
Independent operation (the output reversal operation of pins OP2 and OP3 is independent)
Cooperative operation
(OP3 output pin level is inverted when output compare 2 or output compare 3 is matched in the
compare operation.)
• Specifies the OP3 pin output reversal operation when the free-run timer count value TCDT1 matches the compare
registers OCCP2 and OCCP3.
• When the reversal mode bit is set to “1”, the operation is as follows.
OP2 pin: Reverses output when matches compare register 2 (OCCP2)
OP3 pin: Reverses output when matches compare register 3 (OCCP3)
• When the reversal mode bit is set to “0”, the operation is as follows.
OP2 pin: Reverses output when matches compare register 2 (OCCP2)
OP3 pin: Reverses output when matches compare register 2 (OCCP2) or compare register 3 (OCCP3)
Note: Reversal mode does not allow interrupts, even with the cooperative operation (CMOD=“1”).
• It is necessary to set port PFR2 to conduct output for pins OP2 - OP3.
• bit11-bit10: Undefined Writing does not affect the operation. The read value is always “1”.
• bit9: Pin level setting (output compare 3)
OTD3
0
1
Operation
Set the output level for OP3 pin to “L”
Set the output level for OP3 pin to “H”
• General-use port setting is necessary to conduct output for pin OP3.
• bit8: Pin level setting (output compare 2)
OTD2
0
1
Operation
Set the output level for OP2 pin to “L”
Set the output level for OP2 pin to “H”
• General-use port setting is necessary to conduct output for pin OP2.
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Chapter 26 Output Compare
4.Registers
• bit7: Interrupt request flag (output compare 3)
ICP3
0
1
Status
Read
Interrupt request not present
Interrupt request present
Write
Clear flag (ICP3)
No effect on operation
• When the free-run timer count value TCDT1 matches the output compare register OCCP3, it becomes “1”.
• Interrupt requests are enabled when the interrupt permission bit (ICP3) is “1”.
• If the timing of the interrupt request flag becoming “1” and the writing of “0” occur simultaneously, the interrupt
request flag will become “1”. (Flag setting is given priority)
• When using an external clock as the free-run timer operation clock, at least one external clock input is necessary
after compare match for output compare-match output and interrupt generation.
• bit6: Interrupt request flag (output compare 2)
ICP2
0
1
Status
Read
Interrupt request not present
Interrupt request present
Write
Clear flag (ICP2)
No effect on operation
• If free-run timer count value TCDT1 matches output compare register OCCP2, it becomes “1”.
• Interrupt request is enabled when the interrupt permission bit (ICP2) is “1”.
• When the timing of the interrupt request flag becoming “1” and the writing of “0” are simultaneous, the interrupt
request flag becomes “1” (flag setting is given priority).
• When using an external clock as the free-run timer operation clock, at least one external clock input is necessary
after compare match for output compare-match output and interrupt generation.
• bit5: Enable interrupt requests (output compare 3)
ICE3
0
1
Status
Disable output compare 3 interrupt requests
Enable output compare 3 interrupt requests
• bit4: Enable interrupt requests (output compare 2)
ICE2
0
1
Status
Disable output compare 2 interrupt requests
Enable output compare 2 interrupt requests
• bit3-bit2: Undefined Writing does not affect the operation. The read value is always “1”.
• bit1: Enable operation requests (output compare 3)
CST3
0
1
Operation
Disable output compare 3 operation
Enable output compare 3 operation
• A bit that enables a comparison operation between the free-run timer count value and the output compare register
(TCDT1 and OCCP3).
• Before enabling the operation, always set a value to compare register OCCP3.
• If you stop the free-run timer, output compare also stops.
304
Chapter 26 Output Compare
4.Registers
• bit0: Enable operation requests (output compare 2)
CST2
0
1
Operation
Disable output compare 2 operation
Enable output compare 2 operation
• A bit that enables a comparison operation between the free-run timer count value and the output compare register
(TCDT1 and OCCP2).
• Before enabling the operation, always set a value to compare register OCCP2.
• If you stop the free-run timer, output compare also stops.
305
Chapter 26 Output Compare
4.Registers
4.3 OCCP: Compare Register
A register the sets the value to be compared to the 16 bit free-run timer count value.
• OCCP0 (Compare0): Address 0E6h (Access: Half-word, Word)
• OCCP1 (Compare1): Address 0E4h (Access: Half-word, Word)
• OCCP2 (Compare2): Address 0EAh (Access: Half-word, Word)
• OCCP3 (Compare3): Address 0E8h (Access: Half-word, Word)
15
C15
14
C14
13
C13
12
C12
11
C11
10
C10
9
C9
8
C8
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
C7
6
C6
5
C5
4
C4
3
C3
2
C2
1
C1
0
C0
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(For information on attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• Compares the compare registers OCCP0, OCCP1 to free-run timer 0 count value TCD0.
• Compares the compare registers OCCP2, OCCP3 to free-run timer 1 count value TCD1.
306
bit
Initial
Value
Attribute
bit
Initial
Value
Attribute
Chapter 26 Output Compare
5.Operation
5. Operation
5.1 Output Compare Output (Independent Reversal) CMODE=“0”
Peripheral
clock (CLK)
(6)
Free-run timer 0
Compare register value
BFFEh
BFFFh
0000
0001
BFFFh
(5)
Compare-match signal
(7)
OP pin output
(8)
Interrupt
request
BFFFh
Free-run
timer 0
count
(4)
0000 h
(6)
Free-run timer 0 clear
(1)
Time
Compare-match clear
Compare-match clear
(2)
Compare register value
CST
OP Output
Interrupt request
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
BFFFh
(3)
(7)
(8)
Clear in
software
Free-run timer clear/reset
Compare value setting
Enable compare operation (CST=“1”)
Free-run timer count up (example of 1 clock in 4)
Compare free-run timer value and compare value and match (compare match).
Free-run timer clear from compare match (free run timer 0, free-run timer 1 only)
OP output level reversal
Compare match interrupt request generation
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Chapter 26 Output Compare
5.Operation
5.2 Output Compare Output (Cooperative Reversal) CMODE=“1”
(9)
BFFFh
Free-run
timer 0
count
(8)
(5)
4000h
(4)
0000h
Free-run timer 0 clear
Compare-match clear
(1)
(10)
(2)
Compare register 0
BFFFh
(2)
Compare register 1
4000h
CST 0
(3)
CST 1
(3)
(11)
OP0 output
CMOD=“0”
0
OP1 output
(6)
(11)
OP0 output
CMOD=“1”
OP1 output
(6)
(11)
Interrupt request 0
Interrupt request 1
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(7)
Clear in software
Free-run timers clear/reset
Compare 0 and compare 1 value settings
Enable compare operation
Free-run timer count up
Compare 1 match
OP(1) output level reversal
Compare 1 match interrupt
Free-run timer count up
Compare 0 match
OP(0) output level reversal
When CMOD=“1”, OP1 output level also reverses
(11) Compare 0 match interrupt
308
Clear in software
Compare-match clear
Time
Chapter 26 Output Compare
6.Settings
6. Settings
Table 6-1 Settings Necessary for Using Output Compare
Settings
Free-run timer setting
Compare value setting
Setting Register
See “Chapter 24 Free-run Timer (Page No.271)”
Compare register (OCCP0 - OCCP3)
Compare mode setting
Stop compare operation
Set initial level of compare pin output
Set OP0-OP3 pins to output
Clear free-run timer
Enable compare operation (activate)
Output control register
(OCS01, OCS23)
Port function register (PFR)
Timer control register
(TCCS0 - TCCS1)
See “Chapter 24 Free-run Timer (Page No.271)”
Output control register
(OCS01, OCS23)
Setting
Procedure*
--See 7.1
See 7.2
See 7.3
See 7.4
See 7.5
See 7.6
See 7.7
*: For the setting procedure, refer to the section indicated by the number.
Table 6-2 Item Necessary to Clear the Free-run Timer upon Compare-match.
Setting
Setting Register
Setting
Procedure*
Select free-run timer clear mode
Timer control register
(TCCS0 - TCCS1)
See “Chapter 24 Free-run Timer (Page No.271)”
See 7.8
*: For the setting procedure, refer to the section indicated by the number.
Table 6-3 Item Necessary for Performing Interrupts
Setting
Output compare interrupt vector,
output compare interrupt level setting
Output compare interrupt setting
Clear interrupt request
Enable interrupt request
Setting register
Setting
Procedure*
See “Chapter 20 Interrupt Control (Page No.207)”
See 7.9
Output control register
(OCS01, OCS23)
See 7.11
*: For the setting procedure, refer to the section indicated by the number.
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Chapter 26 Output Compare
7.Q & A
7. Q & A
7.1 How do I set the compare value?
Write the compare value to compare registers OCCP0 - OCCP3.
7.2 How do I set the compare mode? (for OC1,OC3 input)
This is done using compare mode bits (OCS01.CMOD), (OCS23.CMOD).
Operation
To reverse OC 1 output using a compare-match from only free-run timer 0
and compare register 1
To reverse OC 3 output using a compare-match from only free-run timer 1
and compare register 3
To reverse OC1 output using a compare-match from free-run timer 0 and
compare register 0, as well as free-run timer 0 and compare register 1
To reverse OC3 output using a compare-match from free-run timer 1 and
compare register 2, as well as free-run timer 1 and compare register 3
Compare mode bit
Set (OCS01.CMOD) bit to “0”
Set (OCS23.CMOD) bit to “0”
Set (OCS01.CMOD) bit to “1”
Set (OCS23.CMOD) bit to “1”
With no relation to CMOD bit,
OC0 output is reversed by a compare-match between free-run timer 0 and compare register 0 only.
OC2 output is reversed by a compare-match between free-run timer 1 and compare register 2 only.
7.3 How do I enable/disable the compare operation?
Set it via the compare operation permission bit (OCS01.CST[1:0]), (OCS23.CST[1:0]).
Operation
To stop (disable) the compare operation
To enable compare operation
Compare
Compare 0
Compare 1
Compare 2
Compare 3
Compare 0
Compare 1
Compare 2
Compare 3
Compare operation permission bit
Set (OCS01.CST[0]) to “0”
Set (OCS01.CST[1]) to “0”
Set (OCS23.CST[0]) to “0”
Set (OCS23.CST[1]) to “0”
Set (OCS01.CST[0]) to “1”
Set (OCS01.CST[1]) to “1”
Set (OCS23.CST[0]) to “1”
Set (OCS23.CST[1]) to “1”
7.4 How do I set the initial level of the compare pin output?
Set it with compare pin output specification bit (OCS01.OTD[1:0]), (OCS23.OTD[1:0]).
Operation
To set compare 0 pin to “L”
To set compare 0 pin to “H”
To set compare 1 pin to “L”
To set compare 1 pin to “H”
To set compare 2 pin to “L”
To set compare 2 pin to “H”
To set compare 3 pin to “L”
To set compare 3 pin to “H”
310
Compare pin output specification bit
Set (OCS01.OTD0) to “0”
Set (OCS01.OTD0) to “1”
Set (OCS01.OTD1) to “0”
Set (OCS01.OTD1) to “1”
Set (OCS23.OTD0) to “0”
Set (OCS23.OTD0) to “1”
Set (OCS23.OTD1) to “0”
Set (OCS23.OTD1) to “1”
Chapter 26 Output Compare
7.Q & A
7.5 How do I set the output for compare pins OP0-OP3?
Set it with port function register (PFR2.OP[0:3]).
Operation
To set compare 0 pin (OP0) to output
To set compare 1 pin (OP1) to output
To set compare 2 pin (OP2) to output
To set compare 3 pin (OP3) to output
Port function bit
Set OP0 bit to “1”
Set OP1 bit to “1”
Set OP2 bit to “1”
Set OP3 bit to “1”
7.6 How do I clear the free-run timer?
Set it with clear bits (TCCS0.CLR), (TCCS1.CLR).
Operation
To clear the free-run timer
Clear Bit (CLR)
Write “1”
For other methods, see “Chapter 24 Free-run Timer (Page No.271)”.
7.7 How do I enable the compare operation?
Enable it with compare operation permission bit (OCS01.CST[1:0]), (OCS23.CST[1:0]).
See “7.4 How do I set the initial level of the compare pin output? (Page No.310)”.
7.8 How do I compare the free-run timer value with the compare register value and clear
the free-run timer when they match?
Do this with timer initialization condition bit (TCCS0.MODE), (TCCS1.MODE).
Operation
To clear free-run timer upon compare 0 match
To clear free-run timer upon compare 2 match
Timer initialization condition bit (MODE)
Set (TCCS0.MODE) to “1”
Set (TCCS1.MODE) to “1”
7.9 What are the interrupt-related registers?
Set the output compare interrupt vector and output compare interrupt level.
The relationship between output compare number, interrupt level, and vector is shown in the following table.
For detailed information on interrupt levels and interrupt vectors, see “Chapter 20 Interrupt Control (Page No.207)”.
Number
Output
Compare 0
Output
Compare 1
Output
Compare 2
Interrupt vector (default)
#59
Address: 0FFF10h
#60
Address: 0FFF0Ch
#61
Address: 0FFF08h
Interrupt level setting bit (ICR[4:0])
Interrupt level register (ICR43)
Address: 0046Bh
Interrupt level register (ICR44)
Address: 0046Ch
Interrupt level register (ICR45)
Address: 0046Dh
Output
Compare 3
#62
Address: 0FFF04h
Interrupt level register (ICR46)
Address: 0046Eh
Interrupt request flags (OCS01. ICP[1:0]), (OCS23. ICP[3:2]), are not automatically cleared, so write “0” to the ICP[3:0]
bit before returning from interrupt processing to clear them.
7.10 What are the types of interrupts?
There is only one type of interrupt, generated upon a compare-match.
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Chapter 26 Output Compare
7.Q & A
7.11 How do I enable interrupts?
Enabling of interrupts is done with interrupt request permission bit (OCS01. ICE[1:0]), (OCS23. ICE[3:2]).
Interrupt request permission bit (ICE0, ICE1, ICE2, ICE3)
Set to “0”
Set to “1”
Interrupt disabled
Enable interrupts
Interrupt requests are clear with interrupt request bits (OCS01. ICP[1:0]), (OCS23. ICP[3:2]).
Interrupt request bit (ICP0, ICP1, ICP2, ICP3)
Write “0”
Interrupt request clear
7.12 Compare value calculation procedure
• Toggle output pulse
(Example) To output a period: A, phase difference1/4 2phase pulse
A
OP0
OP1
Phase difference
1/4 1/4
Formula: Compare 0 value = (A/2) / count clock
Compare 1 value = (A/4) / count clock
(Count clock: time set with free-run timer)
Note: The clear free-run timer 0 on compare 0 match setting (TCCS0.MODE=“1”) and CMOD=“0” setting are
necessary.
Calculation example: A=1024µs, count clock =125ns
Compare 0 value = (1024000 / 2) / 125 - 1 = 4095 = FFFh
Compare 1 value = (1024000 / 4) / 125 - 1 = 1023 = 7FFh
• PWM output
(Example) To output a period: A, duty 1/4 - 3/4 (“L”) PWM,
A
OP1
1/4-3/4
Formula: Compare 0 value = A / count clock
Compare 1 value = (A/4) / count clock (when duty 1/4)
(A × 3/4) / count clock (when duty 3/4)
(count clock: time set with free-run timer)
Note: The clear free-run timer 0 on compare 0 match setting (TCCS0.MODE=“1”) and CMOD=“1” setting are
necessary.
Calculation example: A=1024µs, count clock =125ns
Compare 0 value = 1024000 / 125 - 1 = 8191 = 1FFFh
Compare 1 value = (1024000 / 4) / 125 - 1 = 1023 = 7FFh (when duty 1/4)
(1024000 × 3 / 4) / 125 - 1 = 1023 = BFFh (when duty 3/4)
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Chapter 26 Output Compare
8.Sample Program
8. Sample Program
Setting Procedure Example 1
Program Example 1
.2 channel independent output
compare operation (7FFF,BFFFF)
Interrupt generation No compare clear
1. Initial Value
• Free-run timer ch0 control
Control register setting
clock selection>>
Interrupt request flag>>
Enable interrupt requests>>
Count operation>>
Timer initialization condition>>
TCDT clear
Count clock>>
Timer data value setting
TCCS0
.ECLK
.IVF
.IVFE
.STOP
.MODE
.CLR
.CLK1-0
TCDT0
void OUTPUT01_sample(void)
{
freerun0_initial();
OUTPUT01_initial();
OUTPUT01_start();
freerun0_start();
}
void freerun0_initial(void)
{
IO_TCCS0.byte = 0x10;
IO_TCDT0 = 0x0000;
/* Setting value =0001_0000 */
/* bit7 = 0
ECLK Internal clock source */
/* bit6 = 0
IVF Interrupt request flag */
/* bit5 = 0
IVFE Disable interrupts */
/* bit4 = 1
STOP Disable count */
/* bit3 = 0
MODE Initialization via reset, clear bit */
/* bit2 = 0
CLR Free-run timer value initialization (none) */
/* bit1-0 = 00
CLK1-0 count clock CLKP/4=32MHz/4 */
/* Timer data value initialization */
}
void OUTPUT01_initial(void)
• Port
Port OP0 output setting
Port OP1 output setting
• Output compare control
Control register setting
Register name .Bit name
PFR2 .OP0
PFR2 .OP1
OCS01
IO_PORT1.IO_PFR2.bit.OP0 = 1;
IO_PORT1.IO_PFR2.bit.OP1 = 1;
/* PFR2 OP0(P20) output */
/* PFR2 OP1(P21) output */
IO_OCS01.hword = 0xEC0C;
.CST1.CST0
OCCP0
OCCP1
IO_OCCP0 = BFFF;
IO_OCCP1 = 7FFF;
/* Setting value=1110_1100_0000_1100 */
/* bit15-13 = 111 Undefined bit*/
/* bit12 = 0
CMOD ch0, ch1 level reversal */
/* bit11-10 = 11
Undefined bit */
/* bit9-8 = 00
OTD1,OTD0 compare pin output 0 */
/* bit7-6 = 00
ICP1, ICP0 No output compare-match */
/* bit5-4 = 00
ICE1, ICE0 Disable output compare interrupts */
/* bit3-2 = 11
Undefined bit */
/* bit1-0 = 00
CST1, CST0 Disable compare operation */
/* Compare register ch0 setting */
/*Compare register ch1 setting */
ICR43
ICR44
(CCR)
IO_ICR[43].byte = 0x10;
IO_ICR[44].byte = 0x10;
__EI();
/* Output compare ch0 interrupt level setting (any value) */
/* Output compare ch1 interrupt level setting (any value) */
/* Enable interrupts */
Pin output level reversal operation>>
.CMOD
Pin output level specification>>
Interrupt request flag>>
Enable interrupt requests>>
.OTD1, OTD0
.ICP1, ICP0
.ICE1, ICE0
Operation permission setting>>
Compare value ch0 setting
Compare value ch1 setting
• Interrupt Settings
Interrupt level setting
Interrupt level setting
I flag setting
{
}
2. Activation
• Output compare activation
Interrupt control
Compare operation activation
• Free-run timer ch0 activation
Count operation activation
void OUTPUT01_start(void)
{
IO_OCS01.hword = 0xEC3C;
IO_OCS01.hword = 0xEC3F;
}
void freerun0_start(void)
Register name .Bit name
OCS01 .ICE1.ICE0
OCS01 .CST1.CST0
Register name .Bit name
TCCS1 .STOP
/* bit5-4 = 11
/* bit1-0 = 11
ICE1,ICE0 Enable output compare interrupts */
CST1,CST0 Compare operation enabled */
/* bit4 = 0
STOP count enabled */
/* bit6 = 0
ICP0 Interrupt flag clear */
/* bit7 = 0
ICP1 Interrupt flag clear */
{
IO_TCCS0.bit.STOP = 0;
}
3. Interrupt
• Interrupt processing
Interrupt request flag clear
(User program)
Register name .Bit name
OCS01 .ICP0
••••••••••
Interrupt request flag clear
(User program)
••••••••
OCS01 .ICP1
4. Interrupt Vectors
• Vector table setting
Caution: Clock-related settings and __set_il(numeric value) settings must
be done beforehand. See the clock and interrupt sections.
__interrupt void OUTPUT0_int(void)
{
IO_OCS01.bit.ICP0 = 0;
••••••••
}
__interrupt void OUTPUT1_int(void)
{
IO_OCS01.bit.ICP1 = 0;
••••••••
}
Interrupt routine specification via the vector table is necessary
#pragma intvect OUTPUT0_int 59
#pragma intvect OUTPUT1_int 60
* For information on register conventions, refer to the “FR60Lite Family MB91230 Series Sample I/O Register
Files Usage Guide”.
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Chapter 26 Output Compare
8.Sample Program
Setting Procedure Example 2
Program Example 2
void OUTPUT23_sample(void)
{
2 group compare
ch3 output
Compare operation (7FFF,BFFFF)
Compare clear the larger compare value as period.
Interrupt generation (increase/decrease duty ratio within interrupt)
freerun1_initial();
OUTPUT23_initial();
OUTPUT23_start();
freerun1_start();
}
1. Initial Value
void freerun1_initial(void)
• Free-run timer ch1 control
Control register setting
Clock selection>>
{
TCCS1
.ECLK
IO_TCCS1.byte = 0x18;
/* Setting value =0001_1000 */
/* bit7 = 0
ECLK Internal clock source */
Interrupt request flag>>
.IVF
/* bit6 = 0
IVF Interrupt request flag */
Enable interrupt requests >>
.IVFE
/* bit5 = 0
IVFE Disable interrupts */
Count operation>>
.STOP
/* bit4 = 1
STOP Disable count */
Timer initialization condition>>
.MODE
/* bit3 = 1
MODE Initialization by compare register */
TCDT clear>>
Count clock >>
.CLR
.CLK1-0
/* bit2 = 0
/* bit1-0 = 00
CLR Free-run timer value initialization (none) */
CLK1-0 count clock CLKP/4=32MHz/4 */
Timer data value setting
TCDT1
IO_TCDT1 = 0x0000;
/* Timer data value initialization */
}
void OUTPUT23_initial(void)
• Port
Register name .Bit name
Port OP3 output setting
PFR2 .OP3
{
IO_PORT1.IO_PFR2.bit.OP3 = 1; /* PFR2 OP3(P22) output */
• Output compare control
Control Register Settings
IO_OCS23.hword = 0xFC0C;
OCS23
/* Setting value =1111_1100_0000_1100 */
/* bit15-13 = 111 Undefined bit*/
Pin output level reversal
operation>>
.CMOD
/* bit12 = 1
CMOD Level reversal by compare register 2 and 3
match */
Pin output level specification>>
.OTD1,OTD0
/* bit9-8 = 00
OTD1,OTD0 compare pin output 0 */
Interrupt request flag>>
.ICP1,ICP0
/* bit7-6 = 00
ICP1,ICP0 No output compare-match */
Enable interrupt requests
.ICE1,ICE0
/* bit5-4 = 00
/* bit3-2 = 11
ICE1,ICE0 Disable output compare interrupts */
Undefined bit */
/* bit1-0 = 00
CST1,CST0 Disable compare operation */
/* bit11-10 = 11 Undefined bit*/
Operation enable settings>>
.CST1.CST0
Compare value ch2 settings
OCCP2
IO_OCCP2 = BFFF;
/* Compare register ch2 settings */
Compare value ch3 settings
OCCP3
IO_OCCP3 = 7FFF;
/* Compare register ch3 settings */
Interrupt Level Settings
ICR46
IO_ICR[46].byte = 0x10;
/* Output compare ch3 interrupt level settings (any value) */
I Flag Settings
(CCR)
__EI();
/* Enable interrupts */
• Interrupt Settings
}
2. Activation
void OUTPUT23_start(void)
• Output compare activation
Register name .Bit name
{
Interrupt control
OCS23 .ICE1
IO_OCS23.bit.ICE1 = 1;
/* bit5 = 1
ICE1 Enable output compare interrupts */
Compare operation activation
OCS23 .CST1
OCS23 .CST0
IO_OCS23.bit.CST1 = 1;
IO_OCS23.bit.CST0 = 1;
/* bit1-0 = 11
CST1,CST0 Enable compare operation */
/* bit4 = 0
STOP Enable count */
}
void freerun1_start(void)
• Free-run timer ch1 activation
Register name .Bit name
Count operation activation
TCCS1 .STOP
{
IO_TCCS1.bit.STOP = 0;
}
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Chapter 26 Output Compare
8.Sample Program
(Continued)
3. Interrupts
•Interrupt Processing
Interrupt request flag clear
(User program)
•••••••••••••••••••••••
__interrupt void OUTPUT3_int(void)
Register name .Bit name
OCS23 .ICP1
{
IO_OCS23.bit.ICP1 = 0;
/* bit7 = 0
ICP1 Interrupt flag clear */
if(IO_OCCP3 == 0x0fff){
/* Increase/decrease duty ratio */
m = 0;
IO_OCCP3 = IO_OCCP3 + 0x1000;}
else if(IO_OCCP3 == 0x7fff){
m = 1;
IO_OCCP3 = IO_OCCP3 - 0x1000;}
else if(m)
IO_OCCP3 = IO_OCCP3 - 0x1000;
else if(!m)
IO_OCCP3 = IO_OCCP3 + 0x1000;
}
4. Interrupt Vectors
Vector Table Settings
Caution: Clock-related settings and __set_il(numeric valu2
settings must be done beforehand. See the clock and interrupt
sections.
Interrupt routine specification via the vector table is
necessary
#pragma intvect OUTPUT3_int 62
Note: For information on register conventions, refer to the “FR60Lite Family MB91230 Series Sample
I/O Register Files Usage Guide”.
315
Chapter 26 Output Compare
9.Caution
9. Caution
• Compare stop space during compare operation
As shown below, for one count directly after the compare value is written to the compare register, the compare
operation cannot be used.
Compare
timing
Free-run timer count value
N-2
N-1
N
N+1
N+2
N+3
Write to compare register
Compare register value
X
N
Compare stop space
In this case, a match signal
will not be generated!
• When CMOD=“1” and OCCP0=OCCP1 setting, if a compare match is generated, the port will only reverse once.
• Compare registers (OCCP0 - OCCP3) are set to the initial values. Always set a value before activating them.
• When specifying the output level of compare pins (OTP0, OTP1), first stop the compare operation.
• Output compare is synchronous with the free-run timer, so if you stop the free-run timer the compare operation also
stops.
• Even when reversal mode specification (CMOD) is set to “1” and the compare operation is in cooperative mode,
interrupts are generated independently.
• When using an external clock as the free-run timer, compare-matches and interrupts are generated with the following
clock. To generate compare match output and interrupts, at least “1 clock division” must be input to the external clock
free-run timer after the compare-match.
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Chapter 27 Reload Timer
1.Overview
Chapter 27 Reload Timer
1. Overview
The reload timer uses a 16 bit down counter to detect the input signal trigger and perform a count down.
The count length is 16 bits.
Reload value
Soft trigger
Reload
External event
Internal clock
or
External event
Down counter
Underflow
Reversal
Latch
Output value
Pin
ToPPG
PPG
ToA/D
A/D
2. Features
Operation: 2 kinds of operation are possible
• One-shot Operation
Initial output level
Reversed output level
• Reload Operation
Initial output level
Reversed output level
Quantity: 4 (Output: 4 channels TOT0, TOT1, TOT2, TOT3)
Clock mode: Select from two modes
• Internal clock mode
Count clock:
Reload 0-Reload timer 2: (3 types) 2 divisions, 8 divisions, 32 divisions of CLKP
Reload 3only
: (5 types) 2 divisions, 8 divisions, 32 divisions, 64 divisions, 128 divisions of CLKP
Activation triggers (4 types)
• External event clock mode
Count clock
: External event (TIN0 pin, TIN1 pin, TIN2 pin, TIN3 pin)
Count active edge : Rising/falling/both edges of external event
Activation trigger : Software trigger
Cycle
: Cycle = count clock x (reload value + 1)
(Example) When count clock = 16MHz, reload value = 15999
Cycle = 62.5ns x (15999+1) = 1.0ms
Count active edge: When in external event mode, choose from 3 types.
• External trigger (rising /falling/both edges)
Interrupt: Request generated by underflow
Other 1: Counter stop in software/can be reopened
Other 2: Control of other peripheral functions possible
• A/D convertor activation trigger source (reload timer 2 → A/D0, reload timer 3 → A/D1)
• PPG activation trigger source (reload timer 0, reload timer 1 → PPG0, PPG1, PPG2, PPG3)
317
Chapter 27 Reload Timer
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Reload Timer 0 - Reload Timer 3 (Internal clock count)
Register number
From general-purpose
port output
Trigger selection
MOD2-0
TMCSRx: bit9-7
0 0 0
Software trigger
0 0 1 External trigger rising edge
0 1 0 External trigger falling edge
0 1 1 External trigger both edges
1 X X
Disabled
Reload
register
TMRLR0
TMRLR1
TMRLR2
TMRLR3
Control
register
TMCSR0
TMCSR1
TMCSR2
TMCSR3
Internal
Trigger Output
Interrupt connection
pin
pin
TOT0 IRQ#24 PPG0-3
TIN0
TOT1 IRQ#25 PPG0-3
TIN1
TOT2 IRQ#26
TIN2
AD0
TOT3 IRQ#48
TIN3
AD1
16 bit reload register
TMRLR0/1/2/3
TMCSR:bit5, bit4
OUTL RELD
0
0
1
1
Trigger (load + counter activation)
Reload/activation/stop
/
/
control circuit
0
1
0
1
One-shot mode
Reload mode
"L" square wave during count
"H" square wave during count
"L" toggle output on count start
"H" toggle output on count start
Ch0-Ch1 -> PPG0-PPG3
CH2 -> AD0
CH3 -> AD1
Reload
Stop
CNTE
TMCSRx:bit1
0 Stop count (disable output)
1
Enable count
Counter
activation
.
TOT0/
TOT1/
TOT2/
TOT3
Stop
Underflow
CLKP /25
CLKP /26
Selector
CLKP /23
16 bit down counter (=timer)
CLKP /27
Latch,
output
change
From general-purpose
port output
PFR4: bit4/
PFR4: bit5/
PFR4: bit6/
PFRF: bit3
0 Disable resource output
1 Enable resource output
Reload
Clock source
CLKP /2
1
TO T0/P44
TO T1/P45
TO T2/P46
TO T3/PF3
To general-purpose
port input
CSL2-0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
TMCSRx: bit12-10
Internal clock CLKP/2
Internal clock CLKP/23
Internal clock CLKP /25
(External event) *
Disabled
Internal clock CLKP /26
Internal clock CLKP /27
Disabled
* For external events, see the next chart.
318
Down
counter
TMR0
TMR1
TMR2
TMR3
INTE TMCSRx:bit3
0 Disable interrupts
1 Enable interrupts
UF
TMCSRx:bit2
0 Underflow not present
1 Underflow generation
1
WRITE 0: Flag clear
0
TRG TMCSRx:bit0
No effect
0
1
Soft trigger
Reload
timer
0
1
2
3
Input only
Enable Output
0
1
Selector
TIN0/ P57INT15/ ADTG0
TIN1/P56/INT14/
TIN2/ P55/INT13
TIN3/ PF4/ADTG1
DDR5: bit7/
DDR5:bit6/
DDR5:bit5/
DDRF:bit4
0
To general-purpose
port input
P57/
P56/
P55/
PF4
Timer interrupt
(underflow)
IRQ #24 /
IRQ,#25 /
IRQ #26 /
IRQ,#48
Chapter 27 Reload Timer
3.Configuration
Figure 3-2 Configuration Diagram
Reload timer 0 - Reload timer 3 (External event count)
Register number
16 bit reload register
TMRLR0/1/2/3
TRG TMCSR:bit0 Trigger (reload + counter activation)
0
No effect
1
Soft trigger
0
1
DDR5: bit7/
DDR5:bit6/
DDR5:bit5/
DDRF:bit4
Down
counter
TMR0
TMR1
TMR2
TMR3
Reload
register
TMRLR0
TMRLR1
TMRLR2
TMRLR3
Control
register
TMCSR0
TMCSR1
TMCSR2
TMCSR3
OUTL RELD
TMCSR: bit5, bit4
0
0
"L" square wave during count
One-shot mode
0
"H" square wave during count
1
0
1
Reload mode "L" toggle output on count start
1
1
"H" toggle output on count start
Stop
Counter
activation
.
CNTE TMCSR:bit1
0
Stop count
1 Enable count
Ch0-Ch1 -> PPG0-PPG3
CH2 -> AD0
CH3 -> AD1
Reload
Stop
TOT0/ PFR4: bit4/
TOT1/ PFR4: bit5/
TOT2/ PFR4: bit6/
TOT3 PFRF: bit3
0 Disable resource output
1 Enable resource output
Input only
Enable Output
To general-purpose
port input
From general-purpose
port output
Reload
Event source
TMR0/1/2/3
16 bit down counter
CSL2-0 TMCSR:bit12-10
0 1 1 External event *
* For internal clock, see the previous chart.
Active edge
MOD2-0
0 0 0
0 0 1
0 1 0
0 1 1
1 X X
TMCSR:bit9-7
---------Rising edge
Falling edge
Both edges
Disabled
Latch,
output
change
From general-purpose
port output
1
TO T0/P44
TO T1/P45
TO T2/P46
TO T3/Pf 3
0
Underflow
Selector
TIN0/ P57INT15/ ADTG0
TIN1/P56/INT14/
TIN2/ P55/INT13
TIN3/ PF4/ADTG1
Event Output
Internal
Interrupt connection
pin
pin
TOT0 IRQ#24 PPG0-1
TIN0
TOT1 IRQ#25 PPG0-1
TIN1
TOT2 IRQ#26 AD0
TIN2
TOT3 IRQ#48 AD1
TIN3
To general-purpose
port input
INTE TMCSR:bit3
0 Disable interrupts
1 Enable interrupts
UF
TMCSRx:bit2
0 Underflow not present
1 Underflow generation
WRITE
0: Flag clear
1
0
P57/
P56/
P55/
PF4
Reload/activation/stop
/
/
control circuit
Reload
timer
0
1
2
3
Timer interrupt
(underflow)
IRQ #24 /
IRQ,#25 /
IRQ #26 /
IRQ,#48
Figure 3-3 Register List
319
Chapter 27 Reload Timer
3.Configuration
Note: For information about ICR registers and interrupt vectors, see “Chapter 20
No.207)”.
320
Interrupt Control (Page
Chapter 27 Reload Timer
4.Registers
4. Registers
4.1 TMCSR: Reload Timer Control Status Register
The control status register controls the operation mode of the reload timer and interrupts.
•
•
•
•
TMCSR0
TMCSR1
TMCSR2
TMCSR3
(Reload timer 0): Address: 004EH (Access: Byte, Half-word)
(Reload timer 1): Address: 0056H (Access: Byte, Half-word)
(Reload timer 2): Address: 005EH (Access: Byte, Half-word)
(Reload timer 3): Address: 00CEH (Access: Byte, Half-word)
15
–
0
TMCSR0-2 R0/WX
TMCSR3 R0/WX
14
13
12
–/Reserved –/CSL2
–
0
0
0
R0/WX R0/WX R0/WX
R0/WX R0/W0
R/W
11
CSL1
0
R/W
R/W
10
CSL0
0
R/W
R/W
9
MOD2
0
R/W0
R/W0
8
MOD1
0
R/W
R/W
bit
Initial Value
Attribute
×
×
×
×
×
×
×
×
Rewrite during
operation
7
MOD0
0
R/W
6
–
0
R/W
5
OULT
0
R/W
4
RELD
0
R/W
3
INTE
0
R/W
2
UF
0
R(RM1),W
1
CNTE
0
R/W
0
TRG
0
R0/W
bit
×
–
×
×
×
Ο
Ο
Ο
Initial Value
Attribute
Rewrite during
operation
(Ο: can be rewritten, ×: cannot be rewritten)
(For information on attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit15-14: Undefined
Writing has no effect on the operation. The read value is “0”.
• bit13: Undefined (reload timer 0 - reload timer 2)
Writing has no effect on the operation. The read value is “0”.
Reserved (reload timer 3)
Always write “0”. The read value is “0”.
• bit12-10: Count clock selection
CSL2
0
0
0
0
1
1
CSL1
0
0
1
1
0
1
CSL0
0
1
0
1
1
0
Count clock
Internal clock CLKP/2
Internal clock CLKP/8
Internal clock CLKP/32
External event (external clock)
Internal clock CLKP/64
Internal clock CLKP/128
CLKP: peripheral clock
Remarks
Only valid for reload timer 3
Notes:• The CSL2 bit within the count clock selection bit is only valid for reload timer 3, and
allows selections of peripheral clock divisions up to 64 or 128. The CSL2 bit has no
effect on operation of reload timers 0-2.
• Depending on whether an internal clock or an external event is selected, the meaning of
the operation mode selection bit (MOD[2:0]) changes.
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Chapter 27 Reload Timer
4.Registers
• bit9-7: Operation mode selection
Reload trigger when internal clock is selected
MOD2
0
0
0
0
MOD1
0
0
1
1
MOD0
0
1
0
1
Reload trigger
Software trigger
External trigger (rising edge)
External trigger (falling edge)
External trigger (both edges)
When the selected reload trigger is input, the value of reload register TMRLR is loaded to the down counter and the count
operation is started.
Count trigger when external event is selected
MOD2
0
0
0
0
MOD1
0
0
1
1
MOD0
0
1
0
1
Count trigger
-------External trigger (rising edge)
External trigger (falling edge)
External trigger (both edges)
Counts an external event using the selected count trigger.
Always set MOD2 to “0”. The read value is the written value.
• bit6: Undefined
Writing has no effect on the operation. The read value is “0”.
• bit5: Output level setting
OUTL
0
1
One-shot mode (RELD=“0”)
During count “H” square wave
During count “L” square wave
Reload mode (RELD=“1”)
During count start “L” toggle output
During count start “H” toggle output
• During one-shot mode, a pulse is output during the count, and during reload mode a toggle is output.
• For output level setting bit “0” and “1” the output level is reversed.
• bit4: Enable reload
RELD
0
1
Enable reload
One-shot mode (reload disabled)
Reload mode (reload enabled)
• In reload mode, down counter underflow (0000H -> FFFFH) causes the value set to reload register (TMRLR) to be
loaded to the down counter, and the count operation continues.
• In one-shot mode, down counter underflow (0000H -> FFFFH) causes the count operation to stop.
• bit3: Enable timer interrupt requests
INTE
0
1
Enable timer interrupt requests
Disable interrupt requests
Enable interrupt requests
When timer interrupt requests are enabled, the timer interrupt request flag (UF) becomes “1” and interrupt requests are generated.
• bit2: Timer interrupt request flag
UF
0
1
Timer interrupt request flag
When read
Underflow not present
Underflow present
When write
Clear interrupt requests
No effect
Upon down counter underflow (0000H -> FFFFH) generation, the timer interrupt request flag becomes “1” and the interrupt
request-enabling (INTE=“1”) and an interrupt request are generated.
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Chapter 27 Reload Timer
4.Registers
• bit1: Enable timer count
CNTE
0
1
Enable timer count
Stop count operation
Enable count operation (waiting for activation trigger)
If timer count is enabled, it waits for an activation trigger, and when an activation trigger is generated, the count operation starts.
The activation trigger can be a software trigger or an external trigger.
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Chapter 27 Reload Timer
4.Registers
• bit0: Software trigger
TGR
0
1
Software trigger
No effect. (The read value is “0”.)
Start count operation after data load.
If the count operation is enabled (CNTE=“1”) and the software trigger bit is set to “1”, the value of reload register (TMRLR) is
loaded to the down counter and the count operation starts.
If the count operation is not enabled (CNTE=“0”), the software trigger has no effect.
4.2 TMR: Timer Register
•
•
•
•
TMR0
TMR1
TMR2
TMR3
(Reload timer 0): Address: 004AH (Access: Half-word)
(Reload timer 1): Address: 0052H (Access: Half-word)
(Reload timer 2): Address: 005AH (Access: Half-word)
(Reload timer 3): Address: 00CAH (Access: Half-word)
15
D15
X
R/WX
14
D14
X
R/WX
13
D13
X
R/WX
12
D12
X
R/WX
11
D11
X
R/WX
10
D10
X
R/WX
9
D9
X
R/WX
8
D8
X
R/WX
7
D7
X
R/WX
6
D6
X
R/WX
5
D5
X
R/WX
4
D4
X
R/WX
3
D3
X
R/WX
2
D2
X
R/WX
1
D1
X
R/WX
0
D0
X
R/WX
bit
Initial Value
Attribute
bit
Initial Value
Attribute
(For information on attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
The reload timer count value can be read out through the timer register TMR.
Please perform the read out using half-word access.
4.3 TMRLR: Reload register
• TMRLR0 (Reload timer 0): Address: 0048H (Access: Half-word)
• TMRLR1 (Reload timer 1): Address: 0050H (Access: Half-word)
• TMRLR2 (Reload timer 2): Address: 0058H (Access: Half-word)
• TMRLR3 (Reload timer 3): Address: 00C8H (Access: Half-word)
15
D15
X
RX/W
14
D14
X
RX/W
13
D13
X
RX/W
12
D12
X
RX/W
11
D11
X
RX/W
10
D10
X
RX/W
9
D9
X
RX/W
8
D8
X
RX/W
7
D7
X
RX/W
6
D6
X
RX/W
5
D5
X
RX/W
4
D4
X
RX/W
3
D3
X
RX/W
2
D2
X
RX/W
1
D1
X
RX/W
0
D0
X
RX/W
(For information on attributes, see “■Meaning of Bit Attribute Symbols (Page No.10)”.)
The reload value for the down counter is stored in reload register TMRLR.
Please write using half-word access.
324
bit
Initial Value
Attribute
bit
Initial Value
Attribute
Chapter 27 Reload Timer
5.Operation
5. Operation
5.1 Internal Clock/Reload Mode
In reload mode, a pulse with a 50% duty ratio is output.
(1)
Reload data
TMRLR
[Reload register setting value + 1] Count
Count clock
(5)
Load
data
FFFF
Down counter
Count start
(7) -1
0000
(10)
Reload
data
-1
0000
Reload
data
-1
(2)
CNTE bit
0 (Min)
Activation trigger
(Soft or external event)
(4)
T = CLKP
(10)
(5)
Data load
(8)
Underflow
TOT output waveform
OUTL=0
(3)
(6)
Toggle output
(9)
OUTL=1
When RELD=1
Repeat
(1)
Set reload value to reload register
(2)
Enable reload timer count operation
(3)
TOT pin output
(4)
Generate reload trigger (activation): soft trigger or external event trigger
(5)
Load reload value
(6)
TOT toggle output start
(7)
Counter count down (internal clock synchronous)
(8)
Generate counter underflow
(9)
TOT pin output level reversal (toggle output)
(10)
Reload reload value
(11)
Repeat steps (7) to (10)
(See “9. Caution (Page No.339)”.)
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Chapter 27 Reload Timer
5.Operation
5.2 Internal Clock/One-shot Mode
In one-shot mode, a one-shot pulse is output.
(1)
Reload data
TMRLR
[Reload register setting value + 1] Count
Count clock
FFFF
Counter
(5)
Count start
Reload
data (7) -1
0000
(10) FFFF
Reload
data
(2)
CNTE bit
(4)
Activation trigger
(Soft or external event)
T = CLKP
(5)
Data load
(8)
Underflow
TOT output waveform
OUTL=0
(6)
(9)
(3)
(10)
OUTL=1
Output only once
When RELD=0
(1)
Set reload value to reload register
(2)
Enable reload timer count operation
(3)
TOT pin output
(4)
Generate reload trigger (activation): soft trigger or external event trigger
(5)
Load reload value
(6)
Square wave output (during count, “H” output/OUTL=“0”)
(7)
Counter count down (internal clock synchronous)
(8)
Generate counter underflow
(9)
Return TOT pin output level
(10)
Count stop, wait for next activation trigger
(See “9. Caution (Page No.339)”.)
326
-1
Chapter 27 Reload Timer
5.Operation
5.3 External Event Clock Reload Mode
External event reload mode counts external events and outputs a pulse with a 50% duty ratio.
(1)
Reload data
TMRLR
[Reload register setting value + 1] Count
External event (clock)
(5)
Counter
FFFF
Count start
Reload (7)
-1
data
(10)
Load
data
0000
-1
0000
Reload
data
-1
(2)
CNTE bit
0 (Min)
Activation trigger
(Soft only)
(4)
T = CLKP
(10)
(5)
Data load
(8)
Underflow
TOT output waveform
OUTL=0
(3)
(6)
Toggle output
(9)
OUTL=1
When RELD=1
Repeat
(1)
Set reload value to reload register
(2)
Enable reload timer count operation
(3)
TOT pin output
(4)
Generate reload trigger (activation): software trigger only
(5)
Load reload value
(6)
TOT pin output (initial value)
(7)
Counter count down (external event synchronous)
(9)
TOT pin output level reversal
(10)
Reload reload value
(11)
Repeat steps (6) to (9)
(See “9. Caution (Page No.339)”.)
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Chapter 27 Reload Timer
5.Operation
5.4 External Event Clock/One-shot Mode
In external event one-shot mode, external events are counted and a one-shot pulse is output.
(1)
Reload data
TMRLR
[Reload register setting value + 1] Count
External event clock
(5)
Counter
CNTE bit
Count start
Reload
data (7) -1
FFFF
0000
(10) FFFF
Reload
data
-1
(2)
(4)
Activation trigger
(Soft only)
T = CLKP
(5)
Data load
(8)
Underflow
(6)
TOT output waveform
OUTL=0
(9)
(3)
(10)
OUTL=1
When RELD=0
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
Output only once
Set reload value to reload register
Enable reload timer count operation
TOT pin output
Generate reload trigger (activation): soft trigger only
Load reload value
TOT pin output (during count, output “H”/OUTL=“0”)
Counter count down (via external events)
Generate counter underflow
TOT pin output reversal
Stop counter, wait for next activation trigger
Note: The first reload will be delayed by a maximum of 1 T (T: count clock).
5.5 Operation during Reset
A reset (reset on INITX signal, watchdog reset, software reset) will cause the registers in the reload timer to be initialized.
The initial value of reload registers is indeterminate.
For detailed information on initial values, see the explanation of registers.
5.6 Operation during Sleep Mode
Even after making the transition to sleep mode, the operation of the reload timer will continue.
5.7 Operation during Stop Mode
When the transition is made to stop mode, the operation of the reload timer stops.
Afterwards, when returning from stop mode, it will return to the state it was in before the transition to stop mode.
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Chapter 27 Reload Timer
5.Operation
5.8 Operation when Returning from Stop Mode
When returning due to an external interrupt, the reload timer will continue operation from its stopped state.
When returning from a reset (INITX), it will return to the initial state (down counter stopped, no TOT pin output).
5.9 Status Transition
The status of the counter is decided by the CNTE bit of the reload timer control register and the internal WAIT signal.
Settable statuses are:
STOP status: Stopped (CNTE=“0”, WAIT=“1”)
WAIT status: Waiting for activation trigger (CNTE=“1”, WAIT=“1”)
RUN status : Count operation running (CNTE=“1”, WAIT=“0”)
LOAD status: Loading value to counter (from RUN/WAIT, TRG=“1” or underflow: CNTE=“1”, WAIT=“0”)
Figure 5-1 Status Transition Diagram
Status Transition from Hardware
Reset
Status Transition from Register Access
STOP CNTE=0,WAIT=1
Counter: Retains value
when stopped
Indeterminate after reset
CNTE="1"
TRG="0"
WAIT CNTE=1,WAIT=1
Counter: Retains value
when stopped
Indeterminate until load
after reset
CNTE="1"
TRG="1"
RUN CNTE=1,WAIT=0
RELD . UF
TRG="1"
Counter: Operation
TRG="1"
LOAD CNTE=1,WAIT=0
RELD-UF
Load reload register
content to counter
Finish load
329
Chapter 27 Reload Timer
6.Setting
6. Setting
Table 6-1 Settings Necessary for Moving the Reload Timer (Internal Clock Operation)
Setting
Reload value settings
Setting Registers
Setting
Procedure*
Reload (TMRLR0-TMRLR3)
See7.1
Count clock selection (internal clock selection)
See 7.2
Enable reload timer count operation
See 7.3
Mode selection (reload /one-shot)
Output reversal specification
See 7.4
Reload timer control status
(TMCSR0-TMCSR3)
Reload trigger selection (activation selection)
Soft trigger
External trigger
(Rising edge/falling edge/both edges)
See 7.5
See 7.6
TOT pin output
Port function register (PFR4,FPRF)
Generate activation trigger
–
Soft trigger
-> Software trigger bit setting
Reload timer control status
(TMCSR0-TMCSR3)
External trigger
-> Input trigger to TIN pin
External input
See 7.8
See 7.10
*: For the setting procedure, refer to the section indicated by the number.
Table 6-2 Settings Necessary for Moving the Reload Timer (External Event Operation)
Setting
Reload value setting
Setting Registers
Reload (TMRLR0-TMRLR3)
See 7.1
Count clock selection (external event clock selection)
See 7.2
Enable reload timer count operation
See 7.3
Mode selection (reload /one-shot)
Output reversal specification
Reload timer control status
(TMCSR0-TMCSR3)
External event clock active edge selection
(Rising edge/falling edge/both edges)
See 7.4
See 7.5
See 7.7
TOT pin output
Port function register (PFR4,FPRF)
See 7.8
TIN pin external event input
Data direction register
(DDR5,DDRF)
See 7.9
Generate activation trigger
Soft trigger
-> Software trigger bit setting
Reload timer control status
(TMCSR0-TMCSR3)
See 7.10
*: For the setting procedure, refer to the section indicated by the number.
330
Setting
Procedure*
Chapter 27 Reload Timer
6.Setting
Table 6-3 Items Necessary for Performing Reload Timer Interrupts
Setting
Setting Registers
Setting
Procedure*
Reload timer interrupt vector
Reload timer interrupt level setting
See “Chapter 20 Interrupt Control
(Page No.207)”
See 7.11
Reload timer interrupt settings
Interrupt request clear
Enable interrupt requests
Reload timer control status
(TMCSR0-TMCSR3)
See 7.12
*: For the setting procedure, refer to the section indicated by the number.
Table 6-4 Settings Necessary for Stopping the Reload Timer
Setting
Reload timer stop bit setting
Setting Registers
Reload timer control status
(TMCSR0-TMCSR3)
Setting
Procedure*
See 7.13
*: For the setting procedure, refer to the section indicated by the number.
331
Chapter 27 Reload Timer
7.Q & A
7. Q & A
7.1 What is the reload value setting (rewriting) procedure?
The reload value is set by the 16 bit reload registers TMRLR0, TMRLR1, TMRLR2, TMRLR3.
The equation for the values to be set is as follows.
• Formula
TMRLR register value = {reload interval/count clock}-1
• Allowed Range
TMRLR register value = 0~FFFh (65535)
7.2 What are the kinds of count clocks and how are they selected?
The count clock is chosen from the 4 types in the table below.
Selection is done via the count clock selection bit.
Table 7-1 TMCSR0.CSL[1:0], TMCSR1.CSL[1:0], TMCSR2.CSL[1:0]
Count
Clock
CLKP/2
CLKP/8
CLKP/32
External event
Counter clock selection
bit
CSL1
CSL0
0
0
1
1
0
1
0
1
Count clock example
When CLKP= 32MHz When CLKP= 16MHz
62.5ns
250ns
1.0µs
125ns
500ns
2.0µs
Pulse width: 2/CLKP min
When CLKP=
8MHz
250ns
1.0µs
4.0µs
Table 7-2 TMCSR3.CSL[2:0]
Count
Clock
CLKP/2
CLKP/8
CLKP/32
External event
CLKP/64
CLKP/128
Disabled *
Counter clock selection bit
CSL2
CSL1
CSL0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
When CLKP=
32MHz
62.5ns
250ns
1.0µs
2.0µs
4.0µs
Count clock example
When CLKP=
When CLKP= 8MHz
16MHz
125ns
250ns
500ns
1.0µs
2.0µs
4.0µs
Pulse width: 2/CLKP min
4.0µs
8.0µs
8.0µs
16.0µs
---------
(*: See “9. Caution (Page No.339)”.)
7.3 How to I enable/disable the reload timer count operation?
Use the timer count enable bit (TMCSRn.CNTE).
Note: n=0 - 3
Control Details
To stop the reload timer
To enable the reload timer’s count operation
PPG operation permission bit (CNTE)
Set to “0”
Set to “1”
Cannot be reopened from the stopped state. Enable before activation or simultaneous with activation.
332
Chapter 27 Reload Timer
7.Q & A
7.4 How do I set the reload timer mode (reload/one-shot)?
Use mode selection bit (TMCSRn.RELD).
Note: n=0~3
Operation Mode
To set to one-shot mode
To set to reload
Mode selection bit (RELD)
Set to “0”
Set to “1”
7.5 How do I reverse the output level?
The settings for the output level are detailed in the following table.
The setting is done via timer output level bit (TMCSRn.OUTL).
Note: n=0 - 3
Output level
Reload mode, Initial value “L” level output
Timer output level bit (OUTL)
Set to “0”
Reload mode, initial value “H” level output (reversed)
Set to “1”
One-shot mode, counting “H” level output
Set to “0”
One-shot mode, counting “L” level output (reversed)
Set to “1”
333
Chapter 27 Reload Timer
7.Q & A
7.6 What are the kinds of triggers, and how do I select them?
• Selection is done via the trigger selection bit (TMCSRn.MOD[2:0]).
Note: n=0~3
There are 4 types of reload triggers when an internal clock is selected.
Trigger
Software trigger (TRG bit set)
External trigger from TINx pin (rising edge)
External trigger from TINx pin (falling edge)
External trigger from TINx pin (both edges)
——————
Trigger specification bit (MOD[2:0])
Set to “000”
Set to “001”
Set to “010”
Set to “011”
“100”, “101”, “110”, “111” are disabled *
Reload is repeated on down counter underflow.
(*: See “9. Caution (Page No.339)”.)
• The reload trigger (activation) when an external event is selected is a software trigger.
Reload is repeated on down counter underflow.
7.7 What are the types of external event clock active edges and how do I select them?
The setting is done via the trigger selection bit (TMCSRn.MOD[1:0]).
Note: n=0 - 3
There are three types of active edges.
Active edge
Rising edge
Falling edge
Both edges
Trigger selection bit (MOD1-MOD0)
Set to “01”
Set to “10”
Set to “11”
MOD2 settings have no meaning, no matter if they are set to “0” or “1”.
7.8 How do I make a pin a TOT output pin?
Write “1” to the TOT output selection bit (PFR4.TOTn) to change the port to a TOT pin output.
Note: n=0~3
Pin
TOT0 pin
TOT1 pin
TOT2 pin
TOT3 pin
Control bit
Port function register PFR4
Port function register PFRF
TOT0 output selection bit (TOT0)
TOT1 output selection bit (TOT1)
TOT2 output selection bit (TOT2)
TOT3 output selection bit (TOT3)
7.9 How do I make the TIN pin into an external event input pin, or an external trigger
input pin?
Set the data direction specification bit (DDR4.P44), (DDR4.P45), (DDR4.P46), (DDRF.PF3) to “0”.
Pin
TIN0 pin
TIN1 pin
TIN2 pin
TIN3 pin
334
Control bit
Data direction specification bit (P57)
Data direction register DDR5
Data direction specification bit (P56)
Data direction specification bit (P55)
Data direction register
Data direction specification bit (PF4)
Chapter 27 Reload Timer
7.Q & A
7.10 How do I generate an activation trigger?
• Generating a soft trigger
The setting is done via the software trigger bit (TMCSRn.TRG).
When the software trigger bit (TGR) is set to“1”, a trigger is generated.
To enable operation and activate at the same time, set the count permission bit (TMCSRn.CNTE) and the soft trigger bit
(TMCSRn.TRG) simultaneously.
Note: n=0~3
• Generating an external trigger
By inputting the edge specified by the trigger selection bit to the trigger pin corresponding to each reload timer, a trigger is
generated.
Timer
Reload timer 0
Reload timer 1
Reload timer 2
Reload timer 3
Trigger pin
TIN0
TIN1
TIN2
TIN3
7.11 What are the interrupt-related registers?
The relationship between reload timer numbers, interrupt level, vector, control register, etc is outlined in the following
table.
For details on interrupt level and interrupt vectors, see “Chapter 20 Interrupt Control (Page No.207)”.
Reload timer 0
Reload timer 1
Reload timer 2
Reload timer 3
Interrupt vector (default)
Interrupt level setting bit (ICR[4:0])
#24
Address: 0FFF9Ch
#25
Address: 0FFF98h
#26
Address: 0FFF94h
#48
Address: 0FFF3Ch
Interrupt level register (ICR08)
Address: 00448h
Interrupt level register (ICR09)
Address: 00449h
Interrupt level register (ICR10)
Address: 0044Ah
Interrupt level register (ICR32)
Address: 00460h
Interrupt request flag (TMCSR0.UF) ~ (TMCSR3.UF) is not automatically cleared, so before returning from interrupt
processing, set the UF bit to “0” to reset it.
7.12 How do I enable interrupts?
Enabling interrupts, interrupt request flag
Enabling of interrupts is done via the interrupt request permission bit (TMCSR0.INTE) ~ (TMCSR3.INTE).
To disable interrupt requests
To enable interrupt requests
Interrupt request permission bit (INTE)
Set to “0”
Set to “1”
Clearing of interrupt requests is done via the interrupt request bit (TMCSR0.UF) ~ (TMCSR3.UF).
To disable interrupt requests
Interrupt request bit (UF)
Set to “0”
7.13 How do I stop the reload timer?
This setting is done via the reload timer stop bit.
See “7.3 How to I enable/disable the reload timer count operation? (Page No.332)”.
335
Chapter 27 Reload Timer
8.Sample Programs
8. Sample Programs
Setting Procedure 1
Program 1
Pulse output from TOT0 Soft trigger (duty1/2) Normal polarity
Initial Settings (RT0_initial)
void RT_sample_1(void)
{
⏐
RT0_initial();
Activation (RT0_start)
RT0_start();
}
Interrupt
<Initial Settings>
1
2
Register name .Bit name
Port TOT output setting
PFR4
IO_PORT1.IO_PFR4.byte = 0x10 ;
/* PFR4,TOT0 output port control */
TMRLR0
IO_TMRLR0 = 0xAA ;
/* Input any value for reload value */
TMCSR0
IO_TMCSR0.hword = 0x0010;
• Reload timer 0 control
Control register settings
4
{
• Settings
Reload value setting
3
RT0_initial()
• Port
Clock source selection>>
.CSL
Trigger selection>>
.MOD
/* Setting value =0000_0000_0001_0000 */
/* bit15-13=000
Undefined bit*/
/* bit12-10=000
CSL internal clock CLKP/2 */
/* bit9-7=000
MOD Software trigger */
/* bit6=0
Undefined bit */
Output level selection>>
.OUTL
/* bit5=0
OUTL External output level Low */
Operation mode selection>>
.RELD
/* bit4=1
RELD Enable reload */
Disable interrupts>>
.INTE
/* bit3=0
INTE Disable interrupts */
Interrupt flag clear>>
.UF
/* bit2=0
UF Interrupt request flag clear */
Count stop>>
.CNTE
/* bit1=0
CNTE Count stop */
Soft trigger (not processed)>>
.TRG
/* bit0=0
TRG Software trigger */
• Interrupt Settings
Reload timer 0 interrupt level
ICR8
IO_ICR[8].byte =0x14;
/* Set interrupt level from 16~31 */
I flag setting
(CCR)
__EI();
/* Enable interrupts */
}
<Activation>
RT0_start()
• Reload timer 0 activation
Register name .Bit name
PPG4 activation
TMCSR0
{
IO_TMCSR0.hword = 0x001B;
Interrupt flag clear>>
.UF
/* bit2=0
UF Interrupt request flag clear */
Enable interrupts>>
.INTE
/* bit3=1
INTE Enable interrupts */
Enable count>>
.CNTE
/* bit1=1
CNTE start count */
Soft trigger (activation)>>
.TRG
/* bit0=1
TRG Software trigger */
}
<Interrupts>
__interrupt void RT0_int(void)
• Interrupt Processing
User Program
Interrupt request flag clear
/* Interrupt generated when underflow is generated */
{
TMCSR0.UF
........
/* User program operation */
IO_TMCSR0.hword = 0x0013;
/* bit2=0
UF Interrupt request flag clear */
}
<Interrupt Vector>
Vector table settings
Caution: Clock-related settings and __set_il(numeric value) settings must
be done beforehand. See the clock and interrupt sections.
336
/* Specification of an interrupt routine via the vector table is necessary. */
#pragma intvect RT0_int 24
/* For information on register coding conventions, refer to the "FR60Lite Family MB91230 Series Sample I/O
Register Files User’s Guide". */
Chapter 27 Reload Timer
8.Sample Programs
Setting Procedure 2
Program 2
Square wave output from TOT1, external trigger, normal polarity
void RT1_sample_2()
Initial Settings (RT1_initial)
{
⏐
RT1_initial();
Activation (RT1_start)
RT1_start();
}
Interrupts
<Initial Settings>
1
Register name .Bit name
RT1_initial()
{
IO_PORT1.IO_PFR4.byte = 0x20 ;
IO_PORT1.IO_DDR5.byte = 0x40 ;
2
• Port
Port TOT1 output settings
Port TIN1 output settings
• Settings
Reload value settings
• Reload timer 1 control
TMRLR0
IO_TMRLR1 = 0xAA ;
/* Input any value for the reload value */
3
Control register settings
TMCSR0
IO_TMCSR1.hword = 0x0040;
/* Initial value =0000_0000_0100_0000 */
PFR4
DDR5
/* PFR4,TOT1 output port control */
/* External trigger port settings */
/* bit15-13=000
Clock source selection>>
.CSL
Reload trigger selection>>
.MOD
Undefined bit */
/* bit12-10=000
CSL
Internal clock CLKP/2 */
/* bit9-7=001
MOD
Rising edge */
/* bit6=0
4
Output level selection>>
.OUTL
Operation mode selection>>
.RELD
Disable interrupts>>
.INTE
Interrupt flag clear>>
.UF
Count stop>>
.CNTE
Soft trigger (not processed)>>
.TRG
Undefined bit */
/* bit5=0
OUTL
External output level Low */
/* bit4=0
RELD
One-shot mode */
/* bit3=0
INTE
Disable interrupts */
/* bit2=0
UF
Interrupt request flag clear */
/* bit1=0
CNTE
Count stop */
/* bit0=0
TRG
*/
• Interrupt Settings
Reload timer 1 interrupt level
I flag settings
ICR9
(CCR)
IO_ICR[9].bit.ICR =0x14;
__EI();
/*Set the interrupt level to 16~31*/
/*Enable interrupts*/
}
<Waiting for Activation>
• Reload timer 1 activation
PPG4 Activation
Enable interrupts>>
Interrupt flag clear>>
Register name .Bit name
TMCSR0
.INTE
RT1_start()
{
IO_TMCSR1.hword = 0x004A;
.UF
Enable count>>
.CNTE
Soft trigger (not processed)>>
.TRG
/* bit3=1
INTE
Enable interrupts */
/* bit2=0
UF
Interrupt request flag clear */
/* bit1=1
CNTE
Enable count */
/* bit0=0
TRG
*/
}
<Interrupts>
__interrupt void RT1_int()
• Interrupt Processing
User program
Interrupt request flag clear
/* Interrupt is generated on underflow generation */
{
........
TMCSR0.UF
IO_TMCSR1.hword = 0x004A;
/* User program operation */
/* bit2=0
UF
Interrupt request flag clear */
}
<Interrupt Vector>
Vector table settings
Caution: Clock-related settings and __set_il(numeric value) settings must
be done beforehand. See the clock and interrupt sections.
/* Specification of an interrupt routine via the vector table is necessary. */
#pragma intvect RT1_int 25
/* For information on register coding conventions, refer to the "FR60Lite Family MB91230 Series Sample I/O
Register Files User’s Guide". */
337
Chapter 27 Reload Timer
8.Sample Programs
Setting Procedure 3
Program 3
Pulse output from TOT3, external clock, soft trigger, normal polarity
void RT_sample_3()
Initial Settings (RT3_initial)
{
⏐
RT3_initial();
Activation (RT3_start)
RT3_start();
}
Interrupts
<Initial Settings>
1
2
3
RT3_initial()
{
IO_PORT1.IO_PFRF.byte = 0x08 ;
• Port
Port TOT3 output settings
• Settings
Register name .Bit name
Reload value settings
TMRLR0
IO_TMRLR3 = 0xAA ;
/*Input any value for the reload value */
TMCSR0
IO_TMCSR3.hword = 0x0D10;
/*Setting value =0000_1101_0001_0000 */
PFRF
/*PFRF,TOT3 output port control*/
• Reload timer 3 control
Control register settings
/* bit15-13=000
External clock selection>>
.CSL
Count edge selection>>
.MOD
Undefined bit*/
/* bit12-10=011
CSL
External event*/
/* bit9-7=010
MOD
Rising edge*/
/* bit6=0
4
Output level selection>>
.OUTL
Operation mode selection>>
.RELD
Disable interrupts>>
.INTE
Interrupt flag clear>>
.UF
Count stop>>
.CNTE
Soft trigger
(not processed)>>
• Interrupt Settings
Reload timer 1 interrupt level
I flag settings
Undefined bit*/
/* bit5=0
OUTL
External output level Low*/
/* bit4=1
RELD
Enable reload*/
/* bit3=0
INTE
Disable interrupts*/
/* bit2=0
UF
Interrupt request flag clear*/
/* bit1=0
CNTE
Count stop*/
/* bit0=0
TRG
Software trigger*/
.TRG
ICR32
(CCR)
IO_ICR[32].bit.ICR =20;
__EI();
/*Set interrupt level to 16~31 */
/*Enable interrupts*/
}
<Activation>
• Reload timer 3 activation
PPG4 activation
Enable interrupts>>
Interrupt flag clear>>
Register name .Bit name
TMCSR0
.INTE
RT2_start()
{
IO_TMCSR3.hword = 0x0D1B;
.UF
Enable count>>
.CNTE
Soft trigger (activation)>>
.TRG
/* bit2=0
UF
Interrupt request flag clear */
/* bit3=1
INTE
Enable interrupts */
/* bit1=1
CNTE
Stop count */
/* bit0=1
TRG
Software trigger */
}
<Interrupts>
__interrupt void RT2_int()
• Interrupt Processing
{
User program
Interrupt request flag clear
/*User program processing*/
TMCSR0.UF
<Interrupt Vector>
Vector table settings
Caution: Clock-related settings and __set_il(numeric value) settings must
be done beforehand. See the clock and interrupt sections.
338
/* Interrupt is generated on underflow generation */
IO_TMCSR3.hword = 0x0D1A;
/* bit2=0
UF
Interrupt request flag clear */
/* Specification of an interrupt routine via the vector table is necessary. */
#pragma intvect RT2_int 48
/* For information on register coding conventions, refer to the "FR60Lite Family MB91230 Series Sample I/O
Register Files Use’s Guide". */
Chapter 27 Reload Timer
9.Caution
9. Caution
• Count source select bit (TMCSR3.CSL[2:0]) settings not in the table: “100”, “111” are disabled.
If they are set, disable the reload timer operation before resetting the count source select bit.
• Operation mode bit (TMCSR0.MOD2), (TMCSR1.MOD2), (TMCSR1.MOD2), (TMCSR3.MOD2) must be set to “0”.
If it is set to “1”, disable the reload timer count operation before resetting it. Also the value written during read/modify/
write access may be read.
• Control bits (Count source select, operation mode, reload permission) must not be rewritten during operation.
If they are set during operation, disable the reload timer count operation before resetting them.
• From activation timing, it takes T cycle for the reload value to be loaded to the down counter. (Cycle = 1/CLKP, CLKP
= peripheral clock)
• About output signal internal connections
• Reload timer (0-1) TOT0, TOT1 outputs are connected in the LSI to PPG(0-3) internal trigger inputs.
• Reload timer 2 TOT2 output is connected in the LSI to A/D converter 0 trigger input.
• Reload timer 3 TOT3 output is connected in the LSI to A/D converter 1 trigger inputs.
• Rewriting of the count clock selection bit (CSL[2:0]), operation mode selection bit (MOD[2:0]), output level setting bit
(OUTL), reload permission bit (RELD), and timer interrupt request permission bit (INTE) should be done when the
reload timer is stopped (TMCSR.CNTE=“0”).
• The internal prescaler is enabled activating it when the timer count permission bit (TMCSR.CNTE) is set to “1”.
• If interrupt request flag set timing and clear timing overlap, the flag setting will be given priority and the clear
operation will be made invalid.
• When writing to the reload register and the reload timing overlap, the old data will be loaded to the counter. The new
data will be loaded during the next reload timing.
• If the loading and counting of the timer register overlap, the load (reload) operation is given priority.
• If you want to enable the count at the same time as you start the count operation, set both the timer count permission bit
(TMCSR.CNTE) and the software trigger bit (TMCSR.TRG) to “1”.
339
Chapter 27 Reload Timer
9.Caution
340
Chapter 28 Programmable Pulse Generators (PPGs)
1.Overview
Chapter 28 Programmable Pulse Generators (PPGs)
1. Overview
Programmable Pulse Generators (PPGs) are used to gain one-shot (rectangular wave) output or pulse width modulation
(PWM) output. With their software-programmable cycle and duty capability, the PPGs comfortably fit into broad
applications.
Period value
Down counter
Count clock
Reload
Borrow
Match
Invert
Output
value
Pin
Latch
Buffer
Duty value
2. Features
• Output waveforms: The PPGs can generate the following six kinds of waveforms:
• PWM waveform
Normal polarity:
Inverted polarity:
L
H
L
L
H
H
L
H
H
L
• One-shot waveform (Rectangular wave)
Normal polarity:
L
H
L
Inverted polarity:
H
L
H
• Clamped output
Normal polarity: “L” Clamped output
Inverted polarity: “H” Clamped output
• Quantity: 6 (Output: 6 channels PPG0, PPG1, PPG2, PPG3, PPG4, and PPG5)
• Count clock: Choose from four choices.
×1, ×1/4, ×1/16, ×1/64 of the peripheral clock (CLKP)
• Period: Setting range = Duty value ~ 65535 (specified with a 16-bit register)
Period = Count clock × (PCSR register value + 1)
(Example) Count clock = 32MHz(31.25ns), PCSR value = 63999
Period = 31.25ns × (63999+1) = 2ms
• Duty: Setting range = 0 ~ Period value (specified with a 16-bit register)
Duty = Count clock × (PDUT register value + 1)
341
Chapter 28 Programmable Pulse Generators (PPGs)
2.Features
• Interrupt: Choose from four choices:
• Software trigger
• Counter borrow (cycle match)
• Duty match
• Counter borrow (cycle match) or duty match
• Activation trigger: Choose from seven choices.
• Software trigger (Software trigger bit setting)
• Internal trigger Trigger input bit setting × 4
Reload timer output × 2
342
Chapter 28 Programmable Pulse Generators (PPGs)
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
PPG (0-3)
MDSE
PCNH: bit13
0
PWM operation
1
One shot
Period value
Only write
enabled
PCSR
PDUT
Buffers
Buffers
Count clock
CKS1,0
0
0
0
1
1
0
1
1
PGMS OSEL
0
0
0
1
1
0
1
1
From Port
Data register
Duty match
OR
Output level
(Latch)
Compare
Read-only
down counter
1
Enable operation/Stop
TSEL03-00
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 1 - - -
GCN10: bit3-0
GCN20 EN0 bit
GCN20 EN1 bit
GCN20 EN2 bit
GCN20 EN3 bit
16-bit reload timer ch0
16-bit reload timer ch1
Disabled
Disabled
EN0 GCN20: bit0
EN2 GCN20: bit2
EN3 GCN20: bit3
Reload timer ch0
Reload timer ch1
Selector
EN1 GCN20: bit1
Control
circuit
RTRG PCNH: bit12
0 Restart disabled
1 Restart enabled
Duty
match
Borrow
Trigger
Trigger
OR
Edge
selection
Edge selection
EGS1,0
PCNL: bit7,6
0
0 Operation unaffected
0
1
Rising edge
1
0
Falling edge
1
1
Both edges
Selector
Trigger selection
CNTE PCNH: bit15
Stop
0
1 Enable operation
PPG0/P40
PPG1/P41
PPG2/P42
PPG3/P43
0
PPG0 PFR4: bit0
PPG1 PFR4: bit1
PPG2 PFR4: bit2
PPG3 PFR4: bit3
0 General-purpose port
1
PPG output
Borrow
PTMR
Prescaler
PCNH: bit9,PCNL:bit0
Normal output
Inverted output
Clamped L output
Clamped H output
Port read
Reload
PCNH: bit11,10
CLKP
CLKP/4
CLKP/16
CLKP/64
Peripheral
clock
(CLKP)
Only write
enabled
Duty value
IRQF PCNL: bit4
1
0 No interrupt request
1 Interrupt request
Write 0: Flag clear PPG0
interrupt 0
request
IRS1,0
PCNL: bit3,2
0 0 Software trigger, or trigger input available
0 1
Counter borrow
Duty match
1 0
1 1
Counter borrow or duty match
Register number
PPG
Timer
0
1
2
3
PTMR0
PTMR1
PTMR2
PTMR3
Period
setting
PCSR0
PCSR1
PCSR2
PCSR3
Duty
setting
PDUT0
PDUT1
PDUT2
PDUT3
Control
status H
PCNH0
PCNH1
PCNH2
PCNH3
OR
PPG0/1
interrupt
(#52)
OR
PPG2/3
interrupt
(#53)
PPG1
interrupt
request
Interrupt cause selection
STGR PCNH: bit14
0 Operation unaffected
1 Software trigger
Read: Always '0'
IREN PCNL: bit5
0 Interrupt disabled
1 Interrupt enabled
Controls
status L
PCNL0
PCNL1
PCNL2
PCNL3
PPG2
interrupt
request
PPG3
interrupt
request
Pin
PPG0
PPG1
PPG2
PPG3
343
Chapter 28 Programmable Pulse Generators (PPGs)
3.Configuration
Figure 3-2 Configuration Diagram
PPG (4-5)
MDSE
PCNH: bit13
0
PWM operation
1
One shot
Period value
PCSR
PDUT
Buffers
Buffers
Count clock
CKS1,0
0 0
0 1
1 0
1 1
PGMS OSEL
0
0
0
1
1
0
1
1
From Port
Data register
Duty
match
OR
Compare
Read-only
down counter
Output level
(Latch)
0
PPG4/P53/INT11
PPG5/P54/INT12
1
PPG4 PFR5: bit3
PPG5 PFR5: bit4
0 General-purpose port
1 PPG4 output
Borrow
PTMR
Prescaler
PCNH: bit9,PCNL:bit0
Normal output
Inverted output
Clamped L output
Clamped H output
Port read
Reload
PCNH: bit11,10
CLKP
CLKP/4
CLKP/16
CLKP/64
Peripheral
clock
(CLKP)
Only write
enabled
Only write
Duty value
enabled
Enable operation/Stop
Control
circuit
RTRG PCNH: bit12
0 Restart disabled
1 Restart enabled
Duty
match
Borrow
Trigger
Trigger
STGR
PCNH: bit14
0 Operation unaffected
1
Software trigger
Read: Always '0'
IRQF PCNL: bit4
0 No interrupt request
1 Interrupt request
Selector
CNTE PCNH: bit15
0
Stop
1
Enable operation
Timer
4
5
PTMR4
PTMR5
Period
setting
PCSR4
PCSR5
PPG4 0
interrupt
request
Interrupt cause selection
IRS1,0
PCNL: bit3,2
0 0 Software trigger, or trigger input available
0 1
Counter borrow
1 0
Duty match
1 1
Counter borrow or duty match
Duty
setting
PDUT4
PDUT5
Control
status H
PCNH4
PCNH5
Controls
status L
PCNL4
PCNL5
Pin
PPG4
PPG5
Figure 3-3 Register List
344
1
WRITE 0: Flag clear
Register number
PPG
IREN PCNL: bit5
0 Interrupt disabled
1 Interrupt enabled
PPG5
interrupt
request
OR
PPG4/5
interrupt
(#54)
Chapter 28 Programmable Pulse Generators (PPGs)
3.Configuration
Note: For more information about the ICR register and interrupt vector, see “Chapter 20 Interrupt Control (Page
No.207)”.
Figure 3-4 Register List
Note: For more information about the ICR register and interrupt vector, see “Chapter 20 Interrupt Control (Page
No.207)”.
345
Chapter 28 Programmable Pulse Generators (PPGs)
4.Registers
4. Registers
4.1 PCSR: PPG Cycle Setting Register
Controls the cycle of the PPG.
•
•
•
•
•
•
PCSR0 (PPG0): Address 0122h (Access: Half-word)
PCSR1 (PPG1): Address 012Ah (Access: Half-word)
PCSR2 (PPG2): Address 0132h (Access: Half-word)
PCSR3 (PPG3): Address 013Ah (Access: Half-word)
PCSR4 (PPG4): Address 0142h (Access: Half-word)
PCSR5 (PPG5): Address 014Ah (Access: Half-word)
15
D15
X
RX, W
14
D14
X
RX, W
13
D13
X
RX, W
12
D12
X
RX, W
11
D11
X
RX, W
10
D10
X
RX, W
9
D9
X
RX, W
8
D8
X
RX, W
7
D7
X
RX, W
6
D6
X
RX, W
5
D5
X
RX, W
4
D4
X
RX, W
3
D3
X
RX, W
2
D2
X
RX, W
1
D1
X
RX, W
0
D0
X
RX, W
Bit
Initial value
Attribute
Bit
Initial value
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
• The PPG Period Setting registers come with buffers. Transfers from the buffers to the counter take place
automatically upon counter borrow.
• After the PPG Period Setting registers have been written, be sure to set PPG Duty Setting registers PDUT.
• Always access the PPG Period Setting registers in a half-word (16-bit) format.
(See “9. Caution (Page No.367)”.)
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Chapter 28 Programmable Pulse Generators (PPGs)
4.Registers
4.2 PDUT: PPG Duty Setting Register
Sets the duty of the PPG output waveform.
•
•
•
•
•
•
PDUT0 (PPG0): Address 0124h (Access: Half-word)
PDUT1 (PPG1): Address 012Ch (Access: Half-word)
PDUT2 (PPG2): Address 0134h (Access: Half-word)
PDUT3 (PPG3): Address 013Ch (Access: Half-word)
PDUT4 (PPG4): Address 0144h (Access: Half-word)
PDUT5 (PPG5): Address 014Ch (Access: Half-word)
15
D15
X
RX, W
14
D14
X
RX, W
13
D13
X
RX, W
12
D12
X
RX, W
11
D11
X
RX, W
10
D10
X
RX, W
9
D9
X
RX, W
8
D8
X
RX, W
7
D7
X
RX, W
6
D6
X
RX, W
5
D5
X
RX, W
4
D4
X
RX, W
3
D3
X
RX, W
2
D2
X
RX, W
1
D1
X
RX, W
0
D0
X
RX, W
Bit
Initial value
Attribute
Bit
Initial value
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
• The PPG Duty Setting registers come with buffers. Transfers from the buffers to the counter take place automatically
upon counter borrow.
• Set a value smaller than the setting of PPG Period Setting register PCSR in a PPG Duty Setting register. (See “9.
Caution (Page No.367)”.)
• If the same value as set in PPG Period Setting register PCSR is set in a PPG Duty Setting register,
• “H” is always output to (OSEL=”0”) at normal polarity time.
• “L” is always output to (OSEL=”1”) at inverted polarity time.
(The OSEL bit is an output polarity specification bit of the PPG control register PCN.)
• Always access the PPG Duty Setting registers in a half-word (16-bit) format.
(See “9. Caution (Page No.367)”.)
347
Chapter 28 Programmable Pulse Generators (PPGs)
4.Registers
4.3 PCN: PPG Control Status register
Controls the operations and status of PPGs.
•
•
•
•
•
•
PCN0 (PPG0): Address 0126h (Access: Byte, Half-word)
PCN1 (PPG1): Address 012Eh (Access: Byte, Half-word)
PCN2 (PPG2): Address 0136h (Access: Byte, Half-word)
PCN3 (PPG3): Address 013Eh (Access: Byte, Half-word)
PCN4 (PPG4): Address 0146h (Access: Byte, Half-word)
PCN5 (PPG5): Address 014Eh (Access: Byte, Half-word)
15
CNTE
0
R/W
14
STGR
0
R0/W
13
MDSE
0
R/W
12
RTRG
0
R/W
11
CKS1
0
R/W
10
CKS0
0
R/W
9
PGMS
0
R/W
8
–
X
RX/WX
O
O
×
×
×
×
×
–
7
EGS1
0
R/W
6
EGS0
0
R/W
5
IREN
0
R/W
4
IRQF
0
R(RM1), W
3
IRS1
0
R/W
2
IRS0
0
R/W
1
–
X
RX/WX
0
OSEL
0
R/W
×
×
O
O
×
×
–
×
Bit
Initial value
Attribute
Rewrite during
operation
Bit
Initial value
Attribute
Rewrite during
operation
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
O: Rewritable, ×: Not writable (See “9. Caution (Page No.367)”.)
• Bit 15: Timer enable operation
CNTE
0
1
Operation
Stop
Operation
This bit enables the operation of the PPG.
• Bit 14: Software trigger
STGR
0
1
Operation
The operation is unaffected by writing (The read value always equals “0”).
Software trigger activation
When the Software Trigger bit is set to “1”, a software trigger is generated to activate the PPG, separately from the generation of an
internal trigger (EN bit, reload timer output).
• Bit 13: Mode selection
MDSE
0
1
Mode
PWM operation
One-shot operation
• When the Mode Selection bit is set to “0”, a PWM operation is enabled to generate pulses in sequence.
• When the Mode Selection bit is set to “1”, pulse output takes place only once.
• Bit 12: Restart enable
RTTG
0
1
348
Operation
Disable restart.
Enable restart.
Chapter 28 Programmable Pulse Generators (PPGs)
4.Registers
When the Enable Restart bit is set to “1”, a trigger (software/internal) is generated to enable a restart.
• Bits 11-10: Counter clock selection
CKS1
0
0
1
1
CKS0
0
1
0
1
Down Counter Count Clock Selection
Peripheral clock (CLKP)
Peripheral clock divided by 4
Peripheral clock divided by 16
Peripheral clock divided by 64
• Bit 9: PPG output mask selection
PGMS
0
1
Operation
No output mask
Output mask (Output “L” level latched:OSEL=“0”)
• When the PPG Output Mask Selection bit is set to “1”, the PPG output can be clamped at “L” or “H” regardless of
the mode, cycle, and duty settings.
• The output level can be specified using the Output Polarity Specification bit (PCNn.OSEL).
• Bit 8: Undefined.The operation is unaffected by writing. The read value is indeterminate.
• Bits 7-6: Trigger input edge selection
EGS1
0
0
1
1
EGS0
0
1
0
1
Selected Edge
The operation is unaffected by writing.
Rising edge
Falling edge
Both edges (rising edge, or, falling edge)
Select an edge to trigger the activation of the trigger input selected with the Trigger Specification bits (GCN10.TSEL[03:00]),
(GCN10.TSEL[13:10]), (GCN10.TSEL[23:20]), and (GCN10.TSEL[33:30]) of PPG0 to PPG3, using the Trigger Input Edge
Selection bit (EGS1:0).
• Bit 5: Interrupt request enable
IREN
0
1
Operation
Interrupt request disable
Enable interrupt requests.
• Bit 4: interrupt request flag
IRQF
0
1
Read Operation
No interrupt request
Interrupt request
Write Operation
Clear the Interrupt Request flag.
The operation is unaffected by writing.
If the Interrupt Request flag (IRQF) equals “1” and writing “0” to the flag take place at the same time, the setting of the Interrupt
Request flag (IRQF=“1”) overrides.
• Bit 3-2: Interrupt cause selection
IRS1
0
0
1
1
IRS0
0
1
0
1
Selection
Software trigger, or, trigger input
Counter borrow
The counter matches the duty value.
Counter borrow, or the counter equals the duty value.
• Select the operation in which to generate an interrupt request.
• Bit 1: Undefined.The operation is unaffected by writing. The read value is indeterminate.
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Chapter 28 Programmable Pulse Generators (PPGs)
4.Registers
• Bit 0: PPG output polarity specification
OSEL
0
1
Operation
Normal polarity
Inverted polarity
When the PPG Output Mask Selection bit (PCNn.PGMS) has been set to “1”, if the Output Polarity Specification bit (OSEL) is set
to “0”, the output is clamped at “L”; if the Output Polarity Specification bit is set to “1”, the output is clamped at “H”.
Note: n= 0 ~ 5
4.4 GCN10: General Control register 10
Selects a trigger input to PPG0 to PPG3.
• GCN10: Address 0118h (Access: Half-word)
15
TSEL33
0
R/W
14
TSEL32
0
R/W
13
TSEL31
1
R/W
12
TSEL30
1
R/W
11
TSEL23
0
R/W
10
TSEL22
0
R/W
9
TSEL21
1
R/W
8
TSEL20
0
R/W
7
TSEL13
0
R/W
6
TSEL12
0
R/W
5
TSEL11
0
R/W
4
TSEL10
1
R/W
3
TSEL03
0
R/W
2
TSEL02
0
R/W
1
TSEL01
0
R/W
0
TSEL00
0
R/W
Bit
Initial value
Attribute
Bit
Initial value
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
•
•
•
•
Bits 15-12
Bits 11-8
Bits 7-4
Bits 3-0
0
0
0
0
0
0
: PPG3 trigger specification
: PPG2 trigger specification
: PPG1 trigger specification
: PPG0 trigger specification
TSEL[03:00] (PPG0)
TSEL[13:10] (PPG1)
TSEL[23:20] (PPG2)
TSEL[33:30] (PPG3)
0
0
0
0
0
1
0
1
1
0
1
0
None of the above
Activation trigger specification
0
1
0
1
0
1
EN0 bit (GCN20 register)
EN1 bit (GCN20 register)
EN2 bit (GCN20 register)
EN3 bit (GCN20 register)
16-bit reload timer 0
16-bit reload timer 1
Disabled (See “9. Caution (Page No.367)”.)
• PPG0 to PPG3 as selected are activated when the edge specified by the Trigger Input Edge Selection bits
(PCN0.EGA[1:0]), (PCN1.EGA[1:0]), (PCN2.EGA[1:0]), and (PCN3.EGA[1:0]) are detected during the specified
activation trigger.
• PPG4 and PPG5 support a software trigger (STGR bit) only and not this function.
(See “9. Caution (Page No.367)”.)
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Chapter 28 Programmable Pulse Generators (PPGs)
4.Registers
4.5 GCN20: General Control Register 20
Generates PPG0 to PPG3 internal trigger levels using software.
• GCN20: Address 011Bh (Access: Byte)
7
–
0
R/W0
6
–
0
R/W0
5
–
0
R/W0
4
–
0
R/W0
3
EN3
0
R/W
2
EN2
0
R/W
1
EN1
0
R/W
0
EN0
0
R/W
bit
Initial value
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
•
•
•
•
•
Bits 7-4: Undefined.Always write “0”. The read value is the value as written. (See “9. Caution (Page No.367)”.)
Bit 3: EN3 trigger input
Bit 2: EN2 trigger input
Bit 1: EN1 trigger input
Bit 0: EN0 trigger input
EN0, EN1, EN2, and EN3
Internal Triggers EN0, EN1, EN2, and EN3
0
Set the level to “L”.
1
Set the level to “H”.
• Set the levels of internal triggers EN0, EN1, EN2, and EN3.
• If any of the EN trigger inputs (EN0, EN1, EN2, EN3) is selected with the trigger specification bits (TSEL[03:00],
TSEL[13:10], TSEL[23:20], and TSEL[33:30]) of PPG0, PPG1, PPG2, of PPG3, then the selected EN serves as a
PPG trigger input bit.
• If the state selected with the trigger input edge selection bit (EGS[1:0]) is generated by software using the trigger
input bit (selected EN0, EN1, EN2, or EN3), the choice serves as an activation trigger to activate the PPG.
4.6 PTMR: PPG Timer Register
Reads the counts of PPG0 to PPG5.
•
•
•
•
•
•
PTMR0 (PPG0): Address 0120h (Access: Half-word)
PTMR1 (PPG1): Address 0128h (Access: Half-word)
PTMR2 (PPG2): Address 0130h (Access: Half-word)
PTMR3 (PPG3): Address 0138h (Access: Half-word)
PTMR4 (PPG4): Address 0140h (Access: Half-word)
PTMR5 (PPG5): Address 0148h (Access: Half-word)
15
D15
1
R/WX
14
D14
1
R/WX
13
D13
1
R/WX
12
D12
1
R/WX
11
D11
1
R/WX
10
D10
1
R/WX
9
D9
1
R/WX
8
D8
1
R/WX
7
D7
1
R/WX
6
D6
1
R/WX
5
D5
1
R/WX
4
D4
1
R/WX
3
D3
1
R/WX
2
D2
1
R/WX
1
D1
1
R/WX
0
D0
1
R/WX
Bit
Initial value
Attribute
Bit
Initial value
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
• The count of the 16-bit down counter can be read.
• Be sure to access the PPG Timer register PTMR in half words (16 bits).
• The register would not be read correctly if it is byte-accessed.
351
Chapter 28 Programmable Pulse Generators (PPGs)
5.Operation
5. Operation
The MB91230 comes with six programmable pulse generators (PPGs), which provide programmable pulse output
independently or jointly.
The individual modes of operation are described below.
5.1 PWM Operation
In PWM operation, variable-duty pulses are generated from the PPG pin.
(3)
Enable count
CNTE
Activation trigger
(4)
(1)
PCSR 8000
PDUT
8000
0007
0005
(6) Rewrite
(2) Write
8000
Buffer
(Cycle value)
8000
0007
Buffer
(Duty value)
Down count
value
(PTMR)
0007
(13) Load
(5) Load
Reload
0005
Reload
(13) Load
(5) Load
(7) Down count
(8) Match
(10) Down count
Borrow
(11) Borrow
PPG pin output
Normal
polarity
Inverted
polarity
Interrupt
cause
(1)
(2)
(3)
(4)
(5)
(6)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(9) Invert
(12) Clear
Invert
Clear
Duty
Cycle
Effective edge
Duty match
Counter borrow
Duty match
Write a cycle value.
Write a duty value and transfer the cycle value to buffers.
Enable PPG operation.
Generate an activation trigger.
Load the cycle and duty values.
Rewrite the duty value and transfer the cycle value to buffers.
Counter down count
The down counter equals the duty value.
Inverses the PPG pin output level.
Counter down count
Counter borrow
Clear the PPG pin output level (return to normal).
Reload the cycle value.
Reload the duty value.
Steps from (6) to (13) are iterated.
(See “9. Caution (Page No.367)”.)
352
Match
Match
0005
Counter borrow
Invert
Chapter 28 Programmable Pulse Generators (PPGs)
5.Operation
• Equation
Period = {Period value (PCSR) + 1} ¥ Count clock
Duty = {Duty value (PDUT) + 1} ¥ Count clock
Width up to pulse output = {Period value (PCSR) – Duty value (PDUT)} ¥ Count clock
5.2 One-Shot Operation
In one-shot operation, one-shot pulses are generated from the PPG pin.
(3)
Enable count
CNTE
(4)
Activation trigger
PCSR
(1)
8000
PDUT
0007
(2)
Buffer
(Cycle value)
8000
(5) Load
0007
Buffer
(Duty value)
Down count
value
(PTMR)
(5) Load
(6) Down count
(7) Match
0007
(8) Down count
(10) Borrow
(9) Invert
PPG pin output
Normal
polarity
Duty
Cycle
Inverted
polarity
Interrupt
cause
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(11) Clear
Effective edge
Duty match
Counter borrow
Write a cycle value.
Write a duty value and transfer the cycle value to buffers.
Enable PPG operation.
Generate an activation trigger.
Load the cycle and duty values.
Counter down count
Down counter value and duty value
Inverse the PPG pin output level.
Counter down count
Counter borrow
Clear the PPG pin output level (return to normal).
The operating sequence is now completed.
(See “9. Caution (Page No.367)”.)
353
Chapter 28 Programmable Pulse Generators (PPGs)
5.Operation
5.3 Restart Operation
The restart operation is described below.
• Restart available in PWM operation:
Rising edge detection
Restarted by the trigger
Trigger
m
n
0
PPG
N
T
N = duty, T = cycle
• Restart available in one-shot operation:
Rising edge detection
Restarted by the trigger
Trigger
m
n
0
PPG
N
T
If a restart is not available, the second and subsequent triggers have no effect in both PWM and one-shot operations.
(The second and subsequent triggers following a shutdown of the down counter are functional.)
354
Chapter 28 Programmable Pulse Generators (PPGs)
6.Setting
6. Setting
Table 6-1 Settings Needed to Start the PPG
Setting
Period and duty value settings
Enable PPG operation.
Operation mode selection (PWM/one-shot)
Enable restart.
Count clock selection
PPG output mask selection
Trigger selection
Software
Internal trigger
(Reload timer, GCN20.EN bit)
Output polarity specification
PPG pin output setting
Trigger generation (software trigger)
(Reload timer)
(GCN20.EN bit)
Setting Registers
Setting
Procedure*
PPG cycle settings (PCSR0-PCSR5)
PPG duty settings (PDUT0-PDUT5)
7.1
PPG control status (PCN0-PCN5)
7.2
7.3
7.4
7.5
7.6
General Control 10 (GCN10)
Port functions (PFR4, PFR5)
PPG Control Status (PCN0-PCN5)
See “Chapter 27 Reload Timer (Page
No.317)”.
General Control 20 (GCN20)
7.7
7.8
7.9
7.10
* For refer to the section indicated by the number.
Table 6-2 Settings Needed to Stop the PPG
Setting
PPG stop bit setting
Setting Registers
PPG control status (PCN0-PCN5)
Setting
Procedure*
7.11
*For the setting procedure, refer to the section indicated by the number.
Table 6-3 Settings Needed to Clamp the Output Level
Setting
Output polarity specification
PPG output mask selection
Period value = Duty value setting
Setting Registers
PPG control status (PCN0-PCN5)
PPG duty settings (PDUT0-PDUT5)
Setting
Procedure*
7.8
7.6
7.6
*For the setting procedure, refer to the section indicated by the number.
Table 6-4 Settings Needed to Implement PPG Interrupts
Setting
PPG interrupt vector, PPG interrupt level setting
Setting Registers
See “Chapter 20 Interrupt Control (Page
No.207)”.
Setting
Procedure*
7.12
355
Chapter 28 Programmable Pulse Generators (PPGs)
6.Setting
Table 6-4 Settings Needed to Implement PPG Interrupts
PPG interrupt cause selection
(Generate an activation trigger, borrow, and duty
match)
PPG interrupt setting
Clear interrupt requests.
Enable interrupt requests.
7.13
PPG control status (PCN0-PCN5)
*:For the setting procedure, refer to the section indicated by the number.
356
7.14
Chapter 28 Programmable Pulse Generators (PPGs)
7.Q & A
7. Q & A
7.1 How do I set (rewrite) a cycle and a duty?
Period and duty value settings
• Set each cycle value in PPG Period Setting Register PCSRn.
Note: n= 0 - 5
• Set each duty value in PPG Duty Setting Register PDUTn.
Note: n= 0 - 5
• The PPG Period Setting and the PPG Duty Setting registers each have a buffer to allow the user ignorant of the write
timing.
• Equation
PCSR register value = {Cycle/Count clock} –1
PDUT register value = {“H” width (duty)*/Count clock} –1
*: Normal polarity (OSEL= 0)
• Allowed range
PCSR register value = PCSR register value - FFFFh (65535)
PDUT register value = 0 - PCSR register value
Note: Be sure to set a cycle following the setting of a cycle. (See “9. Caution (Page No.367)”.)
7.2 How do I enable or disable PPG operations?
Enabling the PPG operation
Use the PPG operation enable bit (PCNn.CNTE).
Note: n= 0 - 5
Control
To stop a PPG operation
To enable a PPG operation
PPG Operation Enable Bit (CNTE)
Set “0”.
Set “1”.
Enable PPG operation before starting the PPG.
(See “9. Caution (Page No.367)”.)
7.3 How do I set the PPG operation mode (PWM operation/one-shot operation)?
Operation mode selection
Use the mode selection bit (PCNn.MDSE).
Note: n= 0 - 5
Operation Mode
To implement a PWM operation
To implement a one-shot operation
Mode Selection Bit (MDSE)
Set “0”.
Set “1”.
(See “9. Caution (Page No.367)”.)
7.4 How do I get it restarted?
Enable restart.
A restart of a PPG can be enabled while the PPG is in operation.
Use the Enable Restart bit (PCNn.RTRG) to set.
Note: n= 0 - 5
(See “9. Caution (Page No.367)”.)
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Chapter 28 Programmable Pulse Generators (PPGs)
7.Q & A
7.5 What count clocks are available and how are they selected?
Count clock selection
The count clock is selectable from the four choices listed below.
Use the count clock selection bit (PCNn.CKS[1:0]).
Note: n= 0 - 5
Count Clock Selection Bit
Count
Clock
CKS1
0
0
1
1
CLKP
CLKP/4
CLKP/16
CLKP/64
CKS0
0
1
0
1
(Example) CLKP = 32 MHz
Count Clock
32MHz
8MHz
2MHz
500kHz
Period (1 - FFFFh)
62.5ns - 2.048µs
250ns - 8.192µs
1µs - 32.76ms
4µs - 131.0ms
(See “9. Caution (Page No.367)”.)
7.6 How do I clamp the PPG pin output level?
PPG output mask selection
The level of PPG pin output can be clamped.
Use the PPG Output Mask Selection bit (PCNn.PGMS) and the duty value (PDUT) to set.
Note: n= 0 - 5
PPG Pin Output
PPG Output Polarity
Specification
Bit (OSEL)
To clamp the “L” level under normal polarity
When “0”
To clamp the “H” level under normal polarity
When “0”
To clamp the “H” level under inverted polarity
When “1”
To clamp the “L” level under inverted polarity
When “1”
Setting Procedure
Set the PPG Output Mask Selection bit
(PGMS) to “1”.
Period value (PCSR) =
Set a duty value (PDUT).
Set the PPG Output Mask Selection bit
(PGMS) to “1”.
Period value (PCSR) =
Set a duty value (PDUT).
PPG pin output can be set to all “L”. (when OSEL=“0”)
PPG
Reduce
the duty
value
Write "1" to PGMS (mask bit) on occurrence
of an interrupt caused by a borrow.
If "0" is written to PGMS on occurrence of
an interrupt caused by a borrow, a PWM
waveform can be generated without
incurring hazard output.
PPG pin output can be set to all “H”. (when OSEL=“0”)
PPG
Reduce
the duty value
358
Write the same value as the cycle setting
register value to the duty setting register
on occurrence of an interrupt caused by
a compare match.
Chapter 28 Programmable Pulse Generators (PPGs)
7.Q & A
PPG output will also equal all “H” if “0” is set in both the PPG Period Setting Register (PCSR) and PPG Duty Setting
Register (PDUT). (when OSEL=“0”)
7.7 What activation triggers are available and how are they selected?
• Internal trigger selection
• Activation triggers are broadly grouped into software triggers and internal triggers (six types).
• Software triggers work at all times.
• Internal triggers are available only with PPG0, PPG1, PPG2, and PPG3 and not with PPG4 and PPG5.
An internal trigger is set using the internal trigger specification bits (GCN10.TSEL[03:00]), (GCN10.TSEL [13:10]),
(GCN10.TSEL[23:20]), and (GCN10.TSEL[33:30]).
Internal triggers are selectable for PG0, PPG1, PPG2, and PPG3 independently.
PPG0
Internal Trigger
To select the EN0 bit of the GCN20 register
To select the EN1 bit of the GCN20 register
To select the EN2 bit of the GCN20 register
To select the EN3 bit of the GCN20 register
To select reload timer 0
To select reload timer 1
PPG1
PPG2
PPG3
Internal Trigger Specification Bit
TSEL[03:00]
Set “0000”.
Set “0001”.
Set “0010”.
Set “0011”.
Set “0100”.
Set “0101”.
TSEL[13:10]
TSEL[23:20]
TSEL[33:30]
The same trigger can be specified for a group of PPGs to activate all these PPGs simultaneously. (See “9. Caution (Page
No.367)”.)
• Internal trigger edge selection
Internal trigger edges are set using trigger input edge selection bits (PCN0.EG[1:0]) - (PCN3.EG[1:0]).
Internal Trigger Edge Selection
When not detected (software trigger only)
“L” -> “H” Trigger generated on the rising edge
“H” -> “L” Trigger generated on the falling edge
Trigger generated on both edges
Trigger Input Edge Selection Bits (EG1-EG0)
Set “00”.
Set “01”.
Set “10”.
Set “11”.
(See “9. Caution (Page No.367)”.)
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Chapter 28 Programmable Pulse Generators (PPGs)
7.Q & A
7.8 How do I invert the output polarity?
Output polarity specification
The polarity in the normal state can be specified as follows:
Use the PPG Output Polarity Specification bit (PCNn.OSEL) to set.
Note: n= 0 - 5
(“Normal state” means the state in which pulse output is not executed.)
Output Level in Normal State
To enable “L” level output (normal polarity)
PPG Output Polarity Specification Bit (OSEL)
Set “0”.
To enable “H” level output (inverted polarity)
Set “1”.
(See “9. Caution (Page No.367)”.)
7.9 How do I program a pin as a PPG output pin?
-> PPG pin output setting
Software programming allows ports to be switched to PPG pin output.
Write “1” to the Output Specification bit (PPGn) to set.
Note: n= 0 - 5
Pin
PPG0 pin
PPG1 pin
PPG2 pin
PPG3 pin
PPG4 pin
PPG5 pin
360
Control Bit Location
PPG0 Output specification bit (PPG0)
PPG1 Output specification bit (PPG1)
In Port Function register PFR4
PPG2 Output specification bit (PPG2)
PPG3 Output specification bit (PPG3)
PPG4 Output specification bit (PPG4)
In Port Function register PFR5
PPG5 Output specification bit (PPG5)
Chapter 28 Programmable Pulse Generators (PPGs)
7.Q & A
7.10 How do I generate an activation trigger?
Generating a trigger
Methods of generating an activation trigger are descried below.
• Activating a software trigger
Use the Software Trigger bit (PCNn.STGR) to set.
Note: n= 0 - 5
Write “1” to the Software Trigger bit (STGR) to generate an activation trigger.
Always functional, regardless of the internal trigger.
• Activating PPGs with reload timers 0 and 1
The reload timers need to be set up and activated. For more information, see “Chapter 27 Reload Timer (Page No.317)”.
An activation trigger is generated when the edge specified by the reload timer output signal is generated with the reload timer
underflow.
• Activating a PPG with the EN trigger input bits (GCN20.EN0) - (GCN20.EN3)
An activation trigger can be generated by rewriting the level of the EN trigger input bits (GCN20.EN0) - (GCN20.EN3).
Edge
Rising edge
Falling edge
Software-Based Setting Procedure (EN0, EN1, EN2, EN3)
First, set the EN bit to “0”, then the EN bit to “1”.
First, set the EN bit to “1”, then to “0”.
• Activating multiple PPGs concurrently
The same trigger (trigger input bit) can be specified with the PPG trigger specification bits to activate all the PPGs simultaneously
when the trigger is generated.
• Even if an activation trigger is generated before the operation of a PPG is enabled, that PPG would not be activated. Be
sure to enable the operation of a PPG before generating a trigger to activate it. (See “7.2 How do I enable or disable
PPG operations? (Page No.357)”.)
7.11 How do I stop a PPG operation?
PPG stop bit setting (See “7.2 How do I enable or disable PPG operations? (Page No.357)”.)
7.12 What interrupt registers are used?
PPG interrupt vector, PPG interrupt level setting
The table below summarizes the relationships among the PPG number, interrupt level and interrupt vector.
For more information about the interrupt levels and interrupt vectors, see “Chapter 20 Interrupt Control (Page No.207)”.
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
Interrupt Vector (Default)
Interrupt Level Setting Bit (ICR[4:0])
#52
Address: 0FFF2Ch
Interrupt Level register (ICR36)
Address: 00464h
#53
Address: 0FFF28h
Interrupt Level register (ICR37)
Address: 00465h
#54
Address: 0FFF24h
Interrupt Level register (ICR38)
Address: 00466h
The Interrupt Request flag (PCNn.IRQF) does not clear itself automatically. Use software to clear it before returning from the
interrupt handler. (Write “0” to the IRQF bit.)
Note: n= 0 - 5
361
Chapter 28 Programmable Pulse Generators (PPGs)
7.Q & A
7.13 What interrupts are available and how are they selected?
Interrupt cause selection
Four kinds of interrupts are selectable as follows:
Use the Interrupt Cause Setting bit (PCNn.IRS[1:0]) to set.
Note: n= 0 - 5
Interrupt Cause
Interrupt Cause Setting Bit (IRS[1:0])
Software trigger or Internal trigger generation (PPG0-PPG3)
Software trigger (PPG4, PPG5)
Down counter borrow (cycle match)
Duty match
Down counter borrow (cycle match) or Duty match
Set “00”.
Set “01”.
Set “10”.
Set “11”.
7.14 How do I enable, disable and clear interrupts?
Interrupt Request Enable flag, Interrupt Request flag
Use the interrupt request enable bit (PCNn.IREN) to enable interrupts.
Note: n= 0 - 5
To disable interrupt requests
To enable interrupt requests
Interrupt Request Enable Bit (IREN)
Set “0”.
Set “1”.
Use the interrupt request bit (PCNn.IRQF) to clear interrupt requests.
To select interrupt request
(See “9. Caution (Page No.367)”.)
362
Interrupt Request Bit (IRQF)
Write “0”.
Chapter 28 Programmable Pulse Generators (PPGs)
8.Sample Program
8. Sample Program
Setting Procedure 1
Program 1
PWM output from PPG4 Software trigger (duty 1/4) Normal polarity
Initial setting (PPG4)
void PPG_sample_1(void)
{
PPG4_initial();
Activation (PPG4)
PPG4_start();
}
<Initial settings>
1.
2.
void PPG4_initial(void)
• Port
Port PPG output setting
• PPG4 control
Register name and bit name
PFR5.PPG4
IO_PORT1.IO_PFR5.bit.PPG4 = 1;
/* PFR5.PPG4 output */
Control register setting
Enable timer operation>>
Software trigger
(not processed)>>
Operation mode selection>>
PCN4
.CNTE
IO_PCN4.hword = 0x8000;
/* Setting = 1000_0000_0000_0000 */
/* Bit 15 = 1
CNTE timer enable */
Disable restart>>
{
.STGR
/* Bit 14 = 0
.MDSE
/* Bit 13 = 0
STGR Software trigger */
MDSE PWM operation */
.RTRG
/* Bit 12 = 0
RTRG Disable restart.*/
CKS1, 0 _ */
Clock source selection>>
.CKS1-0
/* Bits 11-10 = 00
Output mask selection>>
.PGMS
/* Bit 9 = 0
PGMS PPG output mask */
/* Bit 8 = 0
Undefined bit */
EGS1, 0 Edge selection: Disabled */
Edge selection>>
.EGS1-0
Interrupt disabled>>
.IREN
/* Bit 5 = 0
IREN Interrupt request enable */
Interrupt flag clear>>
.IRQF
/* Bit 4 = 0
.IRS1-0
/* Bit 3-2 = 00
/* Bit 1 = 0
IRQF Interrupt request flag*/
IRS1, 0 interrupt cause:
trigger */
Undefined bit */
.OSEL
/* Bit 0 = 0
OSEL Normal polarity */
Output polarity selection>>
3.
• Period setting
PPG4 cycle setting
• Duty setting
PCSR4
4.
PPG4 duty setting
PDUT4
/* Bits 7-6 = 00
IO_PCSR4 = 0x0909;
/* PPG cycle setting */
IO_PDUT4 = 0x0241;
/* PPG duty ratio (1/4) setting */
Software
}
<Activation>
• PPG4 activation
PPG4 activation
void PPG4_start(void)
Register name and bit name
{
PCN4.STGR
IO_PCN4.bit.STGR = 1;
/* Bit 14 = 1
STGR Software trigger */
}
<Others>
Caution: Clock setup and __set_il (numeric parameter) must have
been performed beforehand. See the chapters entitled "Clock" and
"Interrupt".
Note: For the register coding format, refer to "FR60Lite Family MB91230 Series Sample I/O Register File User's
Guide."
363
Chapter 28 Programmable Pulse Generators (PPGs)
8.Sample Program
Setting Procedure 2
PPG one-shot output from PPG2
polarity
Initial setting (PPG2)
Program 2
Reload timer ch0 (duty 1/2) Normal
void PPG2_sample_2(void)
{
PPG2_initial();
Initial setting
(Reload timer 0)
RTIM0_initial();
RTIM0_start();
Activation (PPG2)
}
<Initial setting (PPG2)>
1.
2.
void PPG2_initial(void)
Port
Port PPG2 output setting
• PPG2 control
Register name and bit name
PFR4.PPG2
IO_PORT1.IO_PFR4.bit.PPG2 = 1; /* PFR4.PPG2 output */
Control register setting
Enable timer operation>>
Software trigger (not
processed)j>>
Operation mode selection>>
PCN2
.CNTE
IO_PCN2.hword = 0x8040;
{
/* Setting = 1000_0000_0100_0000 */
/* Bit 15 = 1
CNTE timer enable */
.STGR
/* Bit 14 = 0
STGR Software trigger */
.MDSE
/* Bit 13 = 0
MDSE PWM operation */
Disable restart.>>
.RTRG
/* Bit 12 = 0
RTRG Disable restart.*/
Clock source selection>>
.CKS1-0
/* Bit 11-10 = 00
CKS1, 0 _ */
Output mask selection>>
.PGMS
/* Bit 9 = 0
PGMS PPG output mask not present */
/* Bit 8 = 0
Undefined bit */
Edge selection>>
.EGS1-0
/* Bits 7-6 = 01
Edge selection: rising edge */
Interrupt disabled>>
.IREN
/* Bit 5 = 0
IREN Interrupt request enable */
Interrupt flag clear>>
.IRQF
/* Bit 4 = 0
IRQF Interrupt request flag*/
.IRS1-0
/* Bits 3-2= 00
IRS1, 0 interrupt cause: Software trigger */
/* Bit 1 = 0
Undefined bit */
/* Bit 0 = 0
OSEL Normal polarity */
Output polarity selection>>
.OSEL
3.
• Period setting
PPG2 cycle setting
• Duty setting
PCSR2
IO_PCSR2 = 0x0909;
/* PPG cycle setting */
4.
PPG2 duty setting
• Trigger selection
PDUT2
IO_PDUT2 = 0x0484;
/* PPG duty ratio (1/2) setting */
5.
PPG2 trigger selection
GCN10.TSEL2
IO_GCN10.bit.TSEL2 = 4;
/* Bit 11-8 = 0100
TSEL23-20 Reload timer ch0 */
}
<Initial setting (Reload timer 0)>
void RTIM0_initial(void)
1.
{
• Reload timer 0 control
Control register setting
IO_TMCSR0.hword = 0x0012;
/* Setting = 0000_0000_0001_0010 */
/* Bit 15-13 = 000
Undefined bit */
Internal clock selection>>
.CSL2-0
/* Bit 12-10 = 000
CSL2-0 Internal clock CLKP/2 */
Trigger selection>>
.MOD2-0
/* Bits 9-7 = 000
MOD2-0 Software trigger */
/* Bit 6 = 0
Undefined bit */
.OUL
/* Bit 5 = 0
OUTL External output level low */
Enable reload>>
.RELD
/* Bit 4 = 1
RELD Enable reload */
Interrupt disabled>>
Interrupt flag clear>>
.INTE
/* Bit 3 = 0
INTE Interrupt request disabled */
.UF
/* Bit 2 = 0
UF Interrupt request flag*/
.CNTE
/* Bit 1 = 1
CNTE Count enable */
.TRG
/* Bit 0 = 0
TRG Software trigger */
Output level selection>>
Count enable>>
2.
TMCSR0
Software trigger
(not processed)>>
• Count value
Count value setting
TMRLR0
IO_TMRLR0 = 0xffff;
/* Count initial value */
}
<Activation>
• Reload timer 0, when activated, inputs a trigger to PPG2.
Software trigger generation
void rtim0_start(void)
{
TMCSR0.TRG
IO_TMCSR0.bit.TRG = 1;
/* Bit 0 = 1 TRG Software trigger */
}
<Others>
Caution: Clock setup and __set_il (numeric parameter) must have been
performed beforehand. See the chapters entitled "Clock" and "Interrupt."
364
Note: For the register coding format, refer to "FR60Lite Family MB91230 Series Sample I/O Register File
User's Guide."
Chapter 28 Programmable Pulse Generators (PPGs)
8.Sample Program
Setting Procedure 3
PPG one-shot output from PPG1
(GCN20:EN1)
Program 3
High output
Activation trigger
void PPG_sample_3(void)
{
Initial setting (PPG1)
PPG1_initial();
Activation (PPG1)
PPG1_start();
}
<Initial settings>
1.
2.
• Port
Port PPG output setting
• PPG1 control
void PPG1_initial(void)
Register name and bit name
{
PFR4.PPG1
IO_PORT1.IO_PFR4.bit.PPG1 = 1; /* PFR4.PPG1 output */
Control register setting
PCN1
Enable timer operation>>
.CNTE
Software trigger
.STGR
(not processed)>>
Operation mode selection>>
.MDSE
IO_PCN1.hword = 0xa040;
/* Setting = 1010_0000_0100_0000 */
/* Bit 15 = 1
CNTE timer enable */
/* Bit 14 = 0
STGR Software trigger */
/* Bit 13 = 1
MDSE one-shot operation */
/* Bit 12 = 0
RTRG Disable restart.*/
CKS1, 0 _ */
Disable restart.>>
.RTRG
Clock source selection>>
.CKS1-0
/* Bits 11-10 = 00
Output mask selection>>
.PGMS
/* Bit 9 = 0
PGMS PPG output mask */
/* Bit 8 = 0
Undefined bit */
EGS1, 0 rising edge */
Edge selection>>
.EGS1-0
/* Bits 7-6 = 01
Interrupt disabled>>
.IREN
/* Bit 5 = 0
IREN Interrupt request enable */
Interrupt flag clear>>
.IRQF
/* Bit 4 = 0
.IRS1-0
Output polarity selection>>
.OSEL
/* Bit 3-2 = 00
IRQF Interrupt request flag*/
IRS1, 0 interrupt cause :
/* Bit 1 = 0
Undefined bit */
/* Bit 0 = 0
OSEL Normal polarity */
3.
• Period setting
PPG4 cycle setting
• Duty setting
PCSR1
IO_PCSR1 = 0x0909;
/* PPG cycle setting */
4.
PPG4 duty setting
• Trigger selection
PDUT1
IO_PDUT1 = 0x0484;
/* PPG duty ratio (1/2) setting */
5.
PPG2 trigger selection
• Trigger signal level
GCN10.TSEL1
IO_GCN10.bit.TSEL1 = 1;
/* Bit 3-0 = 0001
TSEL03-00 GCN20 EN1 bit */
6.
Trigger level = "L"
GCN20.EN1
IO_GCN20 = 0x00;
/* Bit 1 = 0
EN1 GNC20 EN1 bit */
IO_PCN4.bit.STGR = 1;
/* Bit 14 = 1
STGR Software trigger */
IO_GCN20 = 0x02;
/* Bit 1 = 1
EN1 GNC20 EN1 bit */
Software trigger */
}
<Activation>
1.
2.
void PPG1_start(void)
• PPG4 activation
PPG4 activation
• Trigger signal level
Register name and bit name
Trigger level = "H"
GCN20.EN1
{
PCN4.STGR
}
<Others>
Caution: Clock setup and __set_il (numeric parameter) must have
been performed beforehand. See the chapters entitled "Clock" and
"Interrupt."
Note:For the register coding format, refer to "FR60Lite Family MB91230 Series Sample I/O Register File User's
Guide."
365
Chapter 28 Programmable Pulse Generators (PPGs)
8.Sample Program
Setting Procedure 4
Program 4
Interval interrupt
[PPG output from PPG4 Software trigger (duty 1/4) Normal polarity]
Initial setting (PPG4)
void PPG_sample_4(void)
{
PPG4_initial();
Activation (PPG4)
PPG4_start();
}
Interrupt
<Initial settings>
1.
2.
void PPG4_initial(void)
• Port
Port PPG output setting
• PPG4 control
Register name and bit name
PFR5.PPG4
IO_PORT1.IO_PFR5.bit.PPG4 = 1;
/* PFR5.PPG4 output */
Control register setting
Enable timer operation>>
Software trigger
(not processed)>>
Operation mode selection>>
PCN4
.CNTE
IO_PCN4.hword = 0x8004;
/* Setting = 1000_0000_0000_0000 */
/* Bit 15 = 1
CNTE timer enable */
{
.STGR
/* Bit 14 = 0
STGR Software trigger */
.MDSE
/* Bit 13 = 0
MDSE PWM operation */
Disable restart>>
.RTRG
/* Bit 12 = 0
RTRG Disable restart.*/
Clock source selection>>
.CKS1-0
/* Bits 11-10 = 00
CKS1, 0 _ */
Output mask selection>>
.PGMS
/* Bit 9 = 0
PGMS PPG output mask */
/* Bit 8 = 0
Undefined bit */
EGS1, 0 Edge selection: Disabled */
Edge selection>>
.EGS1-0
/* Bits 7-6 = 00
Interrupt disabled>>
.IREN
/* Bit 5 = 0
IREN Interrupt request enable */
Interrupt flag clear>>
.IRQF
/* Bit 4 = 0
.IRS1-0
Output polarity selection>>
.OSEL
/* Bit 3-2 = 01
IRQF Interrupt request flag*/
IRS1, 0 interrupt cause: cycle match */
/* Bit 1 = 0
Undefined bit */
/* Bit 0 = 0
OSEL Normal polarity */
3.
• Period setting
PPG4 cycle setting
• Duty setting
PCSR4
IO_PCSR4 = 0x0909;
/* PPG cycle setting */
4.
PPG4 duty setting
• Interrupts
PDUT4
IO_PDUT4 = 0x0241;
/* PPG duty ratio (1/4) setting */
5.
PPG4 interrupt level setting
I flag setting
ICR38
(CCR)
IO_ICR[38].byte = 0x10;
__EI();
/* Interrupt level (optional value) */
/* Enable interrupt */
}
<Activation>
• PPG4 activation
Enable interrupt
PPG4 activation
void PPG4_start(void)
Register name and bit name
{
PCN4.REN
PCN4.STGR
IO_PCN4.bit.IREN = 1;
IO_PCN4.bit.STGR = 1;
/* Bit 5 = 1
/* Bit 14 = 1
IREN Interrupt request enable */
STGR Software trigger */
}
<Interrupt>
__interrupt void PPG4_int(void)
• Interrupt handling
{
Optional processing
Interrupt Request flag clear
PCN4.IRQF
IO_PCN4.bit.IRQF = 0;
/* Optional processing
*/
/* Bit 14 = 0
IRQF Interrupt request flag*/
}
<Interrupt vector>
An interrupt routine must be specified in the vector table.
Vector table setting
<Others>
#pragma intvect PPG4_int 54
Caution: Clock setup and __set_il (numeric parameter) must have been
performed beforehand.
See the chapters entitled "Clock" and
"Interrupt."
Note: For the register coding format, refer to "FR60Lite Family MB91230 Series Sample I/O Register File User's
Guide."
366
Chapter 28 Programmable Pulse Generators (PPGs)
9.Caution
9. Caution
• If the Interrupt Request flag (PCNn.IRQF) equals “1” and the Interrupt Request flag is set to “0” at the same timing, the
setting of the Interrupt Request flag to “1” overrides the flag clear request.
Note: n= 0 - 5
• The first load comes with a maximum delay of 2.5T after the activation trigger. (T: Count clock)
If the down counter is loaded and counts at the same time, the load operation overrides.
Trigger
Maximum 2.5T
Load
Clock
Count value
X
0003
0002
0001
0000
0003
0002
PPG
Interrupt
Effective edge
Duty match
Counter borrow
• Be sure to write duty value PDUTn after cycle PCSRn has been initialized and rewritten.
(Always write in the order of (1)PCSRn and (2)PDUTn.)
Only the PDUT can be written for rewriting the duty. * n= 0 - 5
• Set a value smaller than cycle value PCSRn in setting duty value PDUTn. If any larger value has been set, disable the
operation of the PPG before replacing the duty with a smaller value.
Note: n= 0 - 5
• Always access PPG Period Setting registers PCSRn and PPG Duty Setting registers in a half-word (16-bit) format. If
these registers are byte-accessed, no values would be written to their upper and lower bit positions.
Note: n= 0 - 5
• To activate a PPG, it is necessary to set the Timer Operation Enable bits (PCN0.CNTE), (PCN1.CNTE),
(PCN2.CNTE), (PCN3.CNTE) to “1” before or concurrently with the activation to enable the PPG operation.
• The values of mode (MDSE), restart enable (RTRG), count clock (CKS[1:0]), trigger input edge (EGS[1:0]), interrupt
cause (IRS), internal trigger (TSEL), and output polarity specification (OSEL) may not be changed while the PPG is
operating.
If any of these values has been changed while the PPG was operating, disable the operation of the PPG before reloading
the register.
• Whenever writing a value to GCN20, be sure to write “0” to any undefined part of the upper 4 bits.
If “1” is written, disable the operation of the PPG before reloading the register.
• If any value outside the specified range (0110, 0111, 1000 - 1111) is set in Activation Trigger Specification bits
(TSEL[03:00]), (TSEL[13:10]), (TSEL[23:20]), (TSEL[33:30]) has been set, disable the operation of the PPG and then
write the specified value to let the register return to normal.
• PPG4 and PPG5 can be activated only with the Software Trigger bit (STGR).
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Chapter 28 Programmable Pulse Generators (PPGs)
9.Caution
• If the Timer Operation Enable bit (PCNn.CNTE) is set to “0” to disable PPGn while it is operating, the PPG stops, with
its status (count and output level) being latched.
If the Timer Operation Enable bit is subsequently set to (PCNn.CNTE) “1” to enable the PPG, it restarts from the point
of interruption.
Note: n= 0 - 5
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Chapter 29 A/D Converter
1.Overview
Chapter 29 A/D Converter
1. Overview
The A/D converter is a 4-input, four-buffer, 10-bit serial A/D converter.
Two conversion modes are supported: single conversion and scan conversion.
In both conversion modes, activation triggers are selectable from among software triggers/external triggers/reload timers.
Level
generation
(D/A)
Comparator
Switch
AN input
Software, external
trigger, reload timer
Buffers
Sample hold
Activation trigger
2. Features
• Conversion method: Serial-parallel conversion with a sample hold circuit (Sub-Ranging Type)
• Quantity: 2 (A/D converter 0 input -- 4 channels AN0, AN1, AN2, AN3
A/D converter 1 Input -- 4 channels AN4, AN5, AN6, AN7)
• Conversion time:
Minimum 1.47us/1 channel (including sample hold time)
Conversion time = Sampling + Conversion + 3-cycle conversion time adjustable
• Resolution: 10-bit resolution (8-bit selectable)
• Conversion mode: Single conversion mode: Converts a selected channel once.
Scan conversion mode: Scans and converts up to four channels.
• Activation Trigger:
• Software trigger (ADCSL0:STAR, ADCSL1:STAR)
• External trigger, falling edge (ADTG0 pin, ADT0 pin)
• Reload timer, rising edge (Reload timer 2, Reload timer 3)
Note: Can be specified separately for A/D converter 0 and A/D converter 1.
•Buffer: One buffer is available for each channel.
• Interrupt: Conversion end interrupt (independent for the A/D converter 0 and the A/D converter 1 each)
• Function stop: The A/D conversion operation can be forced to a stop.
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Chapter 29 A/D Converter
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
A/D converter 0
P57 DDR5: bit 7
0
Input only
1 Output enabled
ADTG0/ TIN0/
INT15/P57
From Port Data register
STAR
ADCSL0: bit 1
Operation unaffected
0
1
A/D activation
*: Always set the BUSY bit to 1.
Pin
0
0
1
1
STS1-0
ADCSL0: bit 3-2
0
Software activation
1 Software activation/external trigger (falling edge)
0
Software activation/reload timer (rising edge)
1
Software activation/external trigger/reload timer
Read
BUSY ADCSL0: bit7
0 During stop mode
0
Forced stop
1 Operation unaffected 1 During operation mode
Port read
INTE ADCSL0: bit5
Interrupt disable
0
Interrupt enable
1
Stop
1
0
Software activation
From Port
Data register
Pin
External trigger
From
reload timer 2
AN0/PC0
Selector
AN0 PFRC: bit 0
0 General-purpose port output
1 AN input only
INT
Activation
0
1
1
0
1
0
Sample
hold
1
AD0 interrupt
(#35)
ADT00 / ADTL00
Comparator
Control
circuit
#0
Selector
Port read
Selector
AN1/PC1
AN2 PFRC: bit 2
0 General-purpose port output
1
AN input only
0
Conversion data buffers
From Port
Data register
Pin
Conversion end interrupt request
Write
0 Interrupt request clear
1 Operation unaffected
Port read
AN1 PFRC: bit 1
0 General-purpose port output
1 AN input only
ADCSL0: bit6
Read
No interrupt request
D/A
ADT01 / ADTL01
ADT02 / ADTL02
ADT03 / ADTL03
From Port
Data register
Pin
AN2/PC2
Port read
AN3 PFRC: bit 3
0 General-purpose port output
1 AN input only
Pin
1
CREG ADCSH0: bit 1
0
10-bit display
1
8-bit display
0
From Port
Data register
ADCSH0 : bit 6-4, Bit 0
SCAN
AN3/PC3
Port read
ACS2-0
0 0 0
0 0 1
0 1 0
0 1 1
0 X X
0= Single-shot conversion mode
1= Multi-shot conversion mode
AN0, ADT00
AN1, ADT01
AN2, ADT02
AN3, ADT03
Disabled
AN0 > AN1 >AN2 > AN3
AN1 > AN2 > AN3
AN2 > AN3
AN3
Disabled
SMP3-0
ADCT0 : bit 15-12, 11-8, 7-4, 3-0
CV1 3-0
CV2 3-0
CV0 3-0
Sampling time Conversion
Conversion Conversion
(400 ns or
time A (245 time B (245
time (350
longer)
ns or longer) ns or longer) ns or longer)
Time = {(Setting x 2) + 1} x CKLP
}A/D conversion time = Sampling time + Conversion time
(A + B + C) + 3
Note: For a detailed description of the A/D pin circuit, see the “2. I/O Circuit Type (Page No.29)” - Category E.
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Chapter 29 A/D Converter
3.Configuration
Figure 3-2 Configuration Diagram
A/D converter 1
PF4 DDRF: bit 4
0
Input only
1 Output enabled
ADTG1/ TIN3/PF4
From Port Data register
STAR
ADCSL1: bit 1
Operation unaffected
0
1
A/D activation
*: Always set the BUSY bit to 1.
Pin
0
0
1
1
STS1-0
ADCSL1: bit 3-2
0
Software activation
1 Software activation/external trigger (falling edge)
0
Software activation/reload timer (rising edge)
1
Software activation/external trigger/reload timer
Read
BUSY ADCSL1: bit7
0 During stop mode
0
Forced stop
1 Operation unaffected 1 During operation mode
Port read
INTE ADCSL0: bit5
Interrupt disable
0
Interrupt enable
1
Stop
1
0
Software activation
From Port
Data register
Pin
External trigger
From
reload timer 3
AN4/PC4
Selector
AN4 PFRC: bit 4
0 General-purpose port output
1 AN input only
INT
Activation
0
1
1
0
1
0
Sample
hold
1
AD1 interrupt
(#36)
ADT10 / ADTL10
Comparator
Control
circuit
#1
Selector
Port read
Selector
AN5/PC5
AN6 PFRC: bit 6
0 General-purpose port output
1
AN input only
0
Conversion data buffers
From Port
Data register
Pin
Conversion end interrupt request
Write
0 Interrupt request clear
1 Operation unaffected
Port read
AN5 PFRC: bit 5
0 General-purpose port output
1 AN input only
ADCSL1: bit6
Read
No interrupt request
D/A
ADT11 / ADTL11
ADT12 / ADTL12
ADT13 / ADTL13
From Port
Data register
Pin
AN6/PC6
Port read
AN7 PFRC: bit 7
0 General-purpose port output
1 AN input only
Pin
1
CREG ADCSH1: bit 1
0
10-bit display
1
8-bit display
0
From Port
Data register
ADCS1 : bit 6-4, Bit 0
SCAN
AN7/PC7
Port read
ACS2-0
0 0 0
0 0 1
0 1 0
0 1 1
0 X X
0= Single-shot conversion mode
AN4, ADT10
AN5, ADT11
AN6, ADT12
AN7, ADT13
Disabled
1= Multi-shot conversion mode
AN0 > AN1 >AN2 > AN3
AN1 > AN2 > AN3
AN2 > AN3
AN3
Disabled
SMP3-0
ADCT1 : bit 15-12, 11-8, 7-4, 3-0
CV1 3-0
CV2 3-0
CV0 3-0
Sampling time Conversion
Conversion Conversion
(400 ns or
time A (245 time B (245
time (350
longer)
ns or longer) ns or longer) ns or longer)
Time = {(Setting x 2) + 1} x CKLP
A/D conversion time = Sampling time + Conversion time
(A + B + C) + 3
Note: For a detailed description of the A/D pin circuit, see the “2. I/O Circuit Type (Page No.29)” - Category E.
371
Chapter 29 A/D Converter
3.Configuration
Figure 3-3 Register List
Note: For information about the ICR registers and interrupt vectors, see “Chapter 20 Interrupt Control (Page
No.207).”
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Chapter 29 A/D Converter
4.Register
4. Register
4.1 ADCSH: A/D Control Register (upper)
Controls the A/D converter.
• ADCSH0 (A/D converter0): Address 078H (Access: Byte, half-word, word)
• ADCSH1 (A/D converter1): Address 084H (Access: Byte, half-word, word)
7
6
5
4
3
2
1
0
Bit
---
ACS2
ACS1
ACS0
---
---
CREG
SCAN
--RX/WX
0
R0/W0
0
R/W
0
R/W
--RX/WX
--RX/WX
0
R/W
0
R/W
Initial value
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
• Bits 1-7: Undefined.The operation is unaffected by writing. The read value is indeterminate.
• Bits 6-4: Analog channel selection/Scan channel selection
ACS2
0
0
0
0
1
ACS1
0
0
1
1
X
ACS0
0
1
0
1
X
Selected
Channel
AN0/AN4
AN1/AN5
AN2/AN6
AN3/AN7
Disabled
Scan
Number of
Channels
Associated Buffer
ADT00/ADT10
ADT01/ADT10
ADT02/ADT10
ADT03/ADT10
4
3
2
1
Scan Channel
0>1>2>3/4>5>6>7
1>2>3/5>6>7
2>3/6>7
3/7
• Converts the channel specified by the analog channel selection bit when in single conversion mode.
• Starts converting from a specified channel, scanning as far as the last channel (AN3 or AN7) when in scan
conversion mode.
• A software-activated A/D conversion process (STAR=“1”) allows those bits to be rewritten at the same time.
• Always write “0” to ACS2. The read value is the value as written.
Writing “1” to ACS2 would make the successful operation unpredictable. Write “0” to let the converter return to
normal.
• Bits 3-2: Undefined.The operation is unaffected by writing. The read value is indeterminate.
• Bit 1: Conversion result storage bit length specification
CREG
0
1
Bit Length
10 bits
8 bits
Description
Converts the conversion result in the buffer in a 10-bit format.
Converts the conversion result in the buffer in an 8-bit format.
• Bit 0: Conversion mode selection
SCAN
0
1
Mode
Single-shot conversion
Scan conversion
Description
Converts only the channels specified by ACS1 and ACS0.
Scans from the channel specified by ACS1, ACS0 to the last channel.
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Chapter 29 A/D Converter
4.Register
4.2 ADCSL: A/D Control Register (lower)
Controls the A/D converter and verifies its status.
• ADCSL0 (A/D converter0): Address 079H (Access: Byte, half-word, word)
• ADCSL1 (A/D converter1): Address 085H (Access: Byte, half-word, word)
7
6
5
4
3
2
1
0
BUSY
INT
INTE
---
STS1
STS0
STAR
Reserved
0
R (RM1), W
0
R, W
0
R/W
--RX/WX
0
R/W
0
R/W
0
R0, W
0
R/W0
Bit
Initial value
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
• Bit 7: Forced Stop Specification bit/Operation Verification bit
BUSY
0
1
When Written
The A/D converter is forced to a stop.
The operation is unaffected.
When Read
The A/D converter is stopped.
The A/D converter is operating.
When writing “1” to the Software Trigger Activation (STAR bit), be sure to write “1” to the Forced Stop Specification
bit as well. (Activation won’t work unless “1” is set at the same time.)
• Bit 6: A/D conversion end flag/Interrupt request
INT
0
1
When Read
No interrupt request
Interrupt request (A/D conversion and all scan conversion completed)
When Written
Flag clear
The operation is
unaffected.
The A/D conversion end bit (INT) is also set to “0” when an A/D conversion is activated.
• Bit 5: A/D interrupt request enabled
INTE
0
1
Description
Disable interrupt requests.
Enable interrupt requests.
An interrupt occurs when the Interrupt Request Enable bit (INTE) and the Interrupt Request flag (INT) are “1”.
• Bit4: Undefined.
The operation is unaffected by writing. The read value is indeterminate.
• Bits 3-2: A/D conversion activation trigger selection
STS1
0
0
1
1
STS0
0
1
0
1
Activation Trigger
Software trigger
External trigger (falling edge) or software trigger
Reload timer output (rising edge) or software trigger
External trigger (falling edge) or reload timer output (rising edge) or software trigger
• If multiple activation triggers are specified, the converter is activated on the first instance of any one of them.
• All activation triggers arising during the A/D conversion are ignored. (Restarts are not possible.)
• To restart the conversion, stop the A/D conversion operation once first (BUSY=“0”).
• Bit1: A/D conversion software trigger
STAR
0
1
Function
The operation is unaffected.
Activates the A/D converter.(Software trigger)
• When activating the converter with a software trigger, be sure to set the Forced Stop Specification bit (BUSY) to
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Chapter 29 A/D Converter
4.Register
“1” as well. The A/D converter would not be activated if the Forced Stop Specification bit (BUSY) is set to “0” at
the same time.
• Software triggers arising during the A/D conversion are ignored.
• Bit 0: Reserved.
• Always write 0. The read value is the value as written.
• Writing “1” would make the successful A/D operation unpredictable. Write “0” to let the register return to normal.
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Chapter 29 A/D Converter
4.Register
4.3 ADCT: Conversion Time Setting Register
Sets the durations of the sampling time and conversion time (a,b,c).
• ADCT0 (A/D converter0): Address 07AH (Access: Half-word, word)
• ADCT1 (A/D converter1): Address 086H (Access: Half-word, word)
15
14
13
12
11
10
9
8
Bit
SMP3
SMP2
SMP1
SMP0
CV03
CV02
CV01
CV00
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
Initial value
Attribute
7
CV13
X
R/W
6
CV12
X
R/W
5
CV11
X
R/W
4
CV10
X
R/W
3
CV23
X
R/W
2
CV22
X
R/W
1
CV21
X
R/W
0
CV20
X
R/W
Bit
Initial value
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
Sampling time
Conversion
time a
Conversion
time b
Conversion
time c
3 cycles (fixed)
Conversion end
(Interrupt request arising)
A/D
activation
• Bits 15-12: Sampling time duration setting
SMP3-SMP0
Sampling time = {(n × 2) + 1} × Machine cycle (CLKP) ≥ 400ns
n: Sampling time duration setting bit value
• Bits 11-8: Conversion time a duration setting
CV03-CV00
Conversion time a = {(na × 2) + 1} × Machine cycle (CLKP) ≥ 245ns
na: Conversion time a duration setting bit value
• Bits 7-4: Conversion time b duration setting
CV13-CV10
Conversion time a = {(nb × 2) + 1} × Machine cycle (CLKP) ≥ 245ns
nb: Conversion time b duration setting bit value
• Bits 3-0: Conversion time c duration setting
CV23-CV20
Conversion time a = {(nc × 2) + 1} × Machine cycle (CLKP) ≥ 350ns
nc: Conversion time c duration setting bit value
Use Conversion Time Setting Registers to set the sampling and conversion times (a, b, c).
The width of each cycle can be represented by (register setting value × 2 + 1) × 62.5ns.
The contents of the Conversion Time Setting registers are undefined when they are reset. Be sure to set them before
activating the A/D converter.
• Setting (fastest):
When CLKP = 32Hz,: n = 6, na = 4, nb = 4, nc=6 (total: F1.47)
When CLKP = 16MHz,: n = 3, na=2, nb=2, nc=3 (total: 1.69)
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Chapter 29 A/D Converter
4.Register
4.4 ADT: Data Buffer register
Stores a conversion value.
The Data Buffer register is loaded with a digital value that results from an A/D conversion.
The format of conversion result storage can be selected depending on the value of the conversion result storage bit length
specification (CREG). (8-bit/10-bit).
The value of the Data Buffer register is updated each time 1 cycles of the conversion process are completed.
The Data Buffer register normally holds the final conversion value.
■ With an 10-bit length (CREG = “0”)
• A/D converter0
•
•
•
•
ADT00 (AN0): Address 08CH (Access: Half-word, word)
ADT01 (AN1): Address 08EH (Access: Half-word, word)
ADT02 (AN2): Address 080H (Access: Half-word, word)
ADT03 (AN3): Address 082H (Access: Half-word, word)
• A/D converter1
•
•
•
•
ADT10 (AN4): Address 088H (Access: Half-word, word)
ADT11 (AN5): Address 08AH (Access: Half-word, word)
ADT12 (AN6): Address 08CH (Access: Half-word, word)
ADT13 (AN7): Address 08EH (Access: Half-word, word)
15
14
13
12
11
10
9
8
Bit
0
0
0
0
0
0
D9
D8
0
R0/WX
0
R0/WX
0
R0/WX
0
R0/WX
0
R0/WX
0
R0/WX
X
R/WX
X
R/WX
Initial value
Attribute
7
6
5
4
3
2
1
0
Bit
D7
D6
D5
D4
D3
D2
D1
D0
X
R/WX
X
R/WX
X
R/WX
X
R/WX
X
R/WX
X
R/WX
X
R/WX
X
R/WX
Initial value
Attribute
Bit
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
■ With an 8-bit length (CREG = “1”)
• A/D converter0
•
•
•
•
ADTL00 (AN0): Address 07DH (Access: Byte, Half-word, word)
ADTL01 (AN1): Address 07FH (Access: Byte, Half-word, word)
ADTL02 (AN2): Address 081H (Access: Byte, Half-word, word)
ADTL03 (AN3): Address 083H (Access: Byte, Half-word, word)
• A/D converter1
•
•
•
•
ADTL10 (AN4): Address 089H (Access: Byte, Half-word, word)
ADTL11 (AN5): Address 08BH (Access: Byte, Half-word, word)
ADTL12 (AN6): Address 08DH (Access: Byte, Half-word, word)
ADTL13 (AN7): Address 08FH (Access: Byte, Half-word, word)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
X
R/WX
X
R/WX
X
R/WX
X
R/WX
X
R/WX
X
R/WX
X
R/WX
X
R/WX
Initial value
Attribute
377
Chapter 29 A/D Converter
4.Register
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)
If read in half-words, the value of the upper 8 bits is read out as “00H”.
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Chapter 29 A/D Converter
5.Operation
5. Operation
The modes of A/D operation are described below.
5.1 Single-shot conversion mode
AN input
(1)
Channel
selection
(2)
Activation
(trigger)
(4)
Internal level
Sample
hold
Conversion
value
Conversion Conversion Conversion
a
b
c
Conversion in progress
Previous conversion value
Flag clear on A/D conversion activation
(3)
BUSY
Conversion time
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Finalized
(7)
Buffer
(ADT)
Conversion end
(INT)
(5)
New conversion value
(8)
(6) Flag clear
(A/D conversion
activation,
or software)
Channel selection
A/D conversion activation (Trigger input: Software trigger/Reload timer/External trigger)
INT flag clear, BUSY flag set
Sample hold
Conversion (Conversion a + Conversion b + Conversion c)
Conversion end, INT flag set, BUSY flag clear
Buffers the conversion value. Buffered data storage
Software-based INT flag clear
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Chapter 29 A/D Converter
5.Operation
5.2 Scan conversion mode
AN input
Scan start
channel
selection
(1)
Activation (2)
(trigger)
Buffers
ADT0
AN0
(4)
AN1
Sample hold
AN2
(6)
AN0
AN3
(9)
(7)
(5)
a, b, c
AN0 conversion value
ADT1
AN1 conversion value
ADT2
AN2 conversion value
ADT3
AN3 conversion value
Conversion end
(INT)
(3)
AN1
(8)
(10)
BUSY
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
380
Activation channel selection
A/D activation (Trigger: Software trigger/Reload timer/External trigger)
INT flag clear, BUSY flag set
AN0 conversion
a. Sample hold, conversion (conversion a + conversion b + conversion c)
b. Conversion end
c. Buffers the conversion value.
AN1 conversion
AN2 conversion
AN3 conversion
INT flag set, BUSY flag clear
Next A/D activation
INT flag clear, BUSY flag set
AN2
AN3
Chapter 29 A/D Converter
6.Setting
6. Setting
Table 6-1 Settings Needed to Use A/D - Single-Shot Conversion Mode
Setting
Mode selection (Single-shot conversion)
Bit length selection
Channel selection
Conversion time setting
To program the AN pin as an input
A/D activation trigger selection
A/D activation trigger generation
Software trigger
-> Software trigger bit setting
Setting Registers
A/D control (ADCSH0-ADCSH1)
Conversion time setting (ADCT0-ADCT1)
Port Function (PFRC)
Setting
Procedure*
See 7.1
See 7.2
See 7.3
See 7.4
See 7.5
See 7.6
A/D control (ADCSL0-ADCSL1)
See 7.7
Reload timer
-> Reload timer rising output
External trigger
-> Inputs a trigger to the ADTG(0, 1) pin.
Conversion end flag check
Conversion value read
See “Chapter 27 Reload Timer (Page No.317)”.
External input
A/D control (ADCSL0-ADCSL1)
Data buffers (ADT0-ADT3)
See 7.8
See 7.9
*: For the setting procedure, refer to the section indicated by the number.
Table 6-2 Settings Needed to Use A/D - Scan Conversion Mode
Setting
Mode selection (Scan conversion)
Bit length selection
Starting channel selection
Conversion time setting
Program the AN pin as an input.
A/D activation trigger selection
A/D activation trigger generation
Software trigger
-> Software trigger bit setting
Setting Registers
A/D control (ADCSH0-ADCSH1)
Conversion time setting (ADCT0-ADCT1)
Port function (PFRC)
Setting
Procedure*
See 7.1
See 7.2
See 7.3
See 7.4
See 7.5
See 7.6
A/D control (ADCSL0-ADCSL1)
See 7.7
Reload timer
-> Reload timer falling output
External trigger
-> Inputs a trigger to the ADTG(0, 1) pin.
Conversion end flag check
Conversion value read
See “Chapter 27 Reload Timer (Page No.317)”.
External input
A/D control (ADCSL0-ADCSL1)
Data buffers (ADT0-ADT3)
See 7.8
See 7.9
*: For the setting procedure, refer to the section indicated by the number.
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Chapter 29 A/D Converter
6.Setting
Table 6-3 Forcing A/D Operations to a Stop
Setting
Forced stop
Setting Registers
A/D control (ADCSL0-ADCSL1)
Setting Procedure*
See 7.10
*: For the setting procedure, refer to the section indicated by the number.
Table 6-4 Items Needed to Enable A/D Interrupts
Setting
A/D interrupt vector and A/D interrupt level settings
PPG interrupt cause selection
(A/D conversion end)
PPG interrupt setting
Clear interrupt requests.
Enable interrupt requests.
Setting Registers
See “Chapter 20 Interrupt Control (Page
No.207)”.
See 7.11.
See 7.12
A/D control registers (ADCSL0-ADCSL1)
*: For the setting procedure, refer to the section indicated by the number.
382
Setting
Procedure*
See 7.13.
Chapter 29 A/D Converter
7.Q & A
7. Q & A
7.1 What conversion modes are available and how are they selected?
Two modes of conversion are available:
• Single-shot conversion mode, in which the conversion takes place only once.
• Scan conversion mode, in which a specified sequence of channels are converted.
Mode selection is made using the conversion mode selection bits (ADCSH0.SCAN), (ADCSH1.SCAN).
Operation Mode
To enable single-shot conversion mode
To scan conversion mode
Conversion Mode Selection Bit (SCAN)
Set “0”.
Set “1”.
7.2 How do I specify a bit length?
Configure the conversion result storage bit length setting (ADCSH0.CREG), (ADCSH1.CREG).
Operation Mode
To store conversion results in the A/DT register in 10 bits
To store conversion results in the A/DT register in 8 bits
Conversion Result Storage Bit Length (CREG)
Set “0”.
Set “1”.
7.3 How do I select channels?
• In single-shot conversion mode
Specify the channel to convert using the A/D Conversion Channel bits (ADCSH0.ACS[2: 0]), (ADCSH1.ACS[2: 0]).
Conversion Channel (AD0)
To specify AN0
To specify AN1
To specify AN2
To specify AN3
Conversion Channel (AD1)
To specify AN4
To specify AN5
To specify AN6
To specify AN7
Channel Selection Bit (ACS[2: 0])
Set “000”.
Set “001”.
Set “010”.
Set “011”.
“100” to “111” cannot be set.
• In scan conversion mode
Specify the conversion starting channel using A/D Conversion Channel bits (ADCSH0.ACS[2: 0]), (ADCSH1.ACS[2:
0]).
Conversion Channel (AD0)
To convert AN3 from AN0
To convert AN3 from AN1
To convert AN3 from AN2
To convert AN3 from AN3
Conversion Channel (AD1)
To convert AN7 from AN4
To convert AN7 from AN5
To convert AN7 from AN6
To convert AN7 from AN7
Channel Selection Bit (ACS[2: 0])
Set “000”.
Set “001”.
Set “010”.
Set “011”.
“100” to “111” cannot be set.
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Chapter 29 A/D Converter
7.Q & A
7.4 How do I set a conversion time?
Use Conversion Time Setting registers ADCT0-ADCT1 to set.
(Equation1) Width of one cycle ={Setting (3 bits) × 2 + 1} × 1/CLKP (peripheral clock)
Example {3x2+1}/16MHz = 437.5ns
(Equation2) Conversion time (total) = Sampling time + Conversion time a + Conversion time b +
Conversion time c + 3 cycles
Example 1: (3x2+1) + (2x2+1) + (2x2+1) + (3x2+1) + 3 = 27 cycles = 1.687 µs (CLKP = 16MHz)
Example 2: (6x2+1) + (4x2+1) + (4x2+1) + (6x2+1) + 3 = 47 cycles = 1.468 µs (CLKP = 32MHz)
Setting Item
Control Bit
To set a sampling time
To set conversion time a
To set conversion time b
To set conversion time c
(SMP[3: 0])
(CV[03: 00])
(CV[13: 10])
(CV[23: 20])
Recommended
Value (CLKP =
16MHz)
3 (437.5 ns)
2 (312.5 ns)
2 (312.5 ns)
2 (437.5 ns)
Remarks
Set 400ns or more. *
Set 245ns or more.
Set 245ns or more.
Set 350ns or more.
*: If sampling takes long due to an external impedance, set a somewhat longer cycle. (CLKP = 32MHz)
7.5 How do I enable analog pin input?
Use Port Function register PFRC.
Operation
To program the AN0 pin as an input
To program the AN1 pin as an input
To program the AN2 pin as an input
To program the AN3 pin as an input
To program the AN4 pin as an input
To program the AN5 pin as an input
To program the AN6 pin as an input
To program the AN7 pin as an input
Control Bit
(PFRC.AN0)
(PFRC.AN1)
(PFRC.AN2)
(PFRC.AN3)
(PFRC.AN4)
(PFRC.AN5)
(PFRC.AN6)
(PFRC.AN7)
Setting
Set “1”.
Set “1”.
Set “1”.
Set “1”.
Set “1”.
Set “1”.
Set “1”.
Set “1”.
7.6 To select how to activate the A/D converter
Activation triggers available fall into three types as follows:
• Software trigger
• Reload timer rising signal
• External trigger input falling signal
To set an activation trigger, use Activation Trigger Selection bits (ADCSL0.ACS[2: 0]), (ADCSL1.
ACS[2: 0]).
A/D Activation Trigger
To specify a software trigger
To specify an external trigger/software trigger
To specify a reload timer/software trigger
To specify an external trigger/reload timer/software trigger
Activation Trigger Selection bit
(STS[1: 0])
Set “000”.
Set “001”.
Set “010”.
Set “011”.
The converter A/D is activated on the first instance of any one of these causes selected.
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Chapter 29 A/D Converter
7.Q & A
7.7 To activate the A/D converter
• Generating a software trigger
A software trigger is generated using A/D Conversion Software Trigger bits (ADCSL0.STAR), (ADCSL1.STAR).
Operation
To generate a software trigger
A/D Conversion Software Trigger Bit (STAR)
Write “1”.
• Activating PPGs with reload timer 0 and reload timer 1
The reload timers must be setup and activated. For more information, see “Chapter 27 Reload Timer (Page No.317)”
When an underflow of a reload timer causes the reload timer output signal to rise, an activation trigger is generated.
• Activating PPGs with an external trigger
Use external trigger input pins ADTG0, ADTG1 to generate an external trigger.
The external trigger input pin is set using Data Direction bits (DDR5.P57), (DDRF.PF4).
Operation
To program the ADTG0 pin as a trigger input
To program the ADTG1 pin as a trigger input
Setting
Set the (DDR5.P57) bit in the Data Direction register to “0”.
Set the (DDRF.PF4) bit in the Data Direction register to “0”.
7.8 To verify the end of a conversion
There are two ways to verify the end of a conversion, as follows:
• Checking the A/D Conversion End Interrupt Request bits (ADCSL0.INT), (ADCSL1.INT)
(INT)
If the read value is “0”
If the read value is “1”
Description
No A/D conversion end interrupt request
A/D conversion end interrupt request
• Checking the Operation Verification bits (ADCSL0.BUSY), (ADCSL1.BUSY)
(BUSY)
If the read value is “0”
If the read value is “1”
Setting
A/D conversion end (stop)
A/D conversion in progress
7.9 How do I read a conversion value?
The conversion value can be read from Data Buffer register ADT.
Relationships between the pins and buffers are summarized below.
A/D input pin (channel)
Associated buffer
AN0
ADT00
AD0
AN1
AN2
ADT01
ADT02
AN3
ADT03
AN4
ADT10
AD1
AN5
AN6
ADT11
ADT12
AN7
ADT13
7.10 How do I force an A/D conversion operation to a stop?
Use the Forced Stop bits (ADCSL0.BUSY), (ADCSL0.BUSY).
Operation
To force an A/D conversion operation to a stop
Forced Stop Bit (BUSY)
Write “0”.
The operation of the A/D is unaffected by writing “1” to the Forced Stop bit (BUSY).
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Chapter 29 A/D Converter
7.Q & A
7.11 What interrupt registers are used?
A/D interrupt vector, A/D interrupt level setting
The table below summarizes the relationships among the machine cycle, A/D number, interrupt level, and interrupt
vector.
For more information about the interrupt level and interrupt vector, see “Chapter 20 Interrupt Control (Page No.207).”
AD0
AD1
Interrupt Vector (Default)
#35
Address: 0FFF70h
#36
Address: 0FFF6Ch
Interrupt Level Setting Bit (ICR[4:0])
Interrupt Level register (ICR19)
Address: 00453h
Interrupt Level register (ICR20)
Address: 00454h
7.12 What interrupts are available?
A/D Conversion End interrupt only. No interrupt cause selection bit is available.
7.13 How do I enable, disable, clear interrupts?
Interrupt Request Enable flag, Interrupt Request flag
Interrupts are enabled using the Interrupt Request Enable bits (ADCSL0.INTE), (ADCSL0.INTE).
To disable interrupt requests
To enable interrupt requests
Interrupt Request Enable Bit (INTE)
Set “0”.
Set “1”.
Interrupt request are cleared using the Interrupt Request bits (ADCSL0.INT),(ADCSL1.INT).
To clear interrupt requests
(See “9. Caution (Page No.389)”.)
386
Interrupt Request Bit (INT)
Write “0”
or activate A/D. (See “7.7 To activate the A/D converter (Page No.385)”.)
Chapter 29 A/D Converter
8.Sample ProgramS
8. Sample ProgramS
Setting Procedure Example 1
Program Example 1
Example of converting the input level from AN0 from analog to digital (single-shot
conversion, software trigger)
<Initial setting>
(1) • Port
Port A/D input selection
(2) • A/D conversion time
Conversion time setting
(3) • A/D0 control
AN0 ~ AN3 control
Channel selection >>
Bit length selection >>
Conversion mode selection >>
Clear the Interrupt Request flag >>
Interrupt disable >>
Activation trigger selection >>
(4) • Interrupts
A/D interrupt level setting
I flag setting
Register name and bit name
PFRC. AN7-0
void AD_sample_1()
{
AD0_INITIAL();
AD0_ch0_start();
}
AD0_INITIAL()
{
IO_PFRC = 0x01;
ADCT0
.SMP3-0
.CV03-00
.CV13-10
.CV23-20
Register name and bit name
ADCS0
.--.ACS2
.ACS1-0
.--.CREG
.SCAN
.BUSY
.INT
.INTE
.Reserved bit
.STS
.START
.Reserved bit
ICR19
(CCR)
/* AN0 only A/D input */
IO_ADCT0 = 0x3223;
/* Recommended value */
/* 0011 */
/* 0010 */
/* 0011 */
/* 0011 */
IO_ADCS0.hword= 0x0080;
/* Setting:00000000 10000000 (bit) */
/* Bit 15 = 0: */
/* Bit 14 = 0: Write "0" */
/* Bits 13-12 = 00: AN0 */
/* Bits 11-10 = 00: */
/* Bit 9 = 0: 10 bits */
/* Bit 8 = 0: Single-shot conversion */
/* Bit 7 = 1: (no effect)*/
/* Bit 6 = 0: Interrupt request clear */
/* Bit 5 = 0: Interrupt disable */
/* Bit 4 = 0: */
/* Bits 3-2 = 00: Software trigger */
/* Bit 1 = 0: */
/* Bit 0 = 0: Write "0" */
IO_ICR[19].bit. ICR = 20;
__EI();
/* Values are optional */
/* Enable interrupt */
}
<A/D activation>
(1) • A/D0 control
A/D0 interrupt enable
Register name and bit name
ADCS0
.INT
.INTE
AD0_ch0_start()
{
IO_ADCS0.hword = 0x00A0;
/* Bit 6 = 0: Clear AD0 interrupt flag */
/* Bit 5 = 1: Enable AD0 interrupt */
(2)
A/D0 software activation
ADCS0
.BUSY
.STAR
IO_ADCS0.hword = 0x00A2;
/* Bit 7 = 1: Writing "1" is required */
/* Bit 1 = 1: Software activation */
}
<Interrupt>
(1) • Reading conversion values
Register name and bit name
Disable interrupt and clear the Interrupt
Request flag
ADCS0
.INT
.INTE
(2)
Reading the conversion value
ADTH00 - ADTL00
(3)
Interrupt enable
ADCS0
.INTE
__interrupt void AD0_ch0_int()
{
/*
*/
ADCS0.hword = 0x0080;
/* Bit 6 = 0: Clear AD0 interrupt flag */
/* Bit 5 = 0: Disable AD0 interrupt */
[Optional storage location] = ADT0;
/* Store the conversion value */
IO_ADCS0.hword = 0x00A0;
/* Bit 5 = 1: Enable AD0 interrupt */
}
<Interrupt vector>
Vector table setting
An interrupt routine must be specified in the vector table.
#pragma intvect AD0_ch0_int 35
Caution: Clock setup and executing program level setup “__set_il (value)” must
have been performed beforehand.
Note: For the register coding format, refer to FR Lite Family MB91230 Series Sample I/O Register File
User's Guide.
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Chapter 29 A/D Converter
8.Sample ProgramS
Setting Procedure Example 2
Program Example 2
Example of converting the input level AN1 to AN3 from analog to digital
(scan conversion, external trigger).
(ADTG0 requires an external trigger (falling edge) input.)
Initial setting
• Port
Port A/D input selection
External trigger port setting
• A/D conversion time
Conversion time setting
• A/D0 control
AN0 ~ N3 control
Channel selection >>
Bit length selection >>
Conversion mode selection >>
Clear the Interrupt Request flag >>
Interrupt disable >>
Activation trigger selection >>
• Interrupts
A/D interrupt level setting
I flag setting
Register name and bit name
PFRC. AN7-0
DDR5. P57
(Condition: CLKP = 16MHz)
void AD_sample_2()
{
AD0_1to3_INITIAL();
AD0_ch1to3_start();
}
AD0_1to3_INITIAL()
{
IO_PFRC = 0x0E;
IO_PORT1.IO_DDR5.bit. P57 = 0;
/* From AN1 to AN3 only A/D input */
/* Program DDR5.P57 as an input */
ADCT0
.SMP3-0
.CV03-00
.CV13-10
.CV23-20
IO_ADCT0 = 0x3223;
/* Recommended values */
/* 0011*/
/* 0010 */
/* 0011*/
/* 0011*/
ADCS0
.--.ACS2
.ACS1-0
.--.CREG
.SCAN
.BUSY
.INT
.INTE
.Reserved bit
.STS
.START
.Reserved bit
IO_ADCS0.hword= 0x1184;
/* Setting = 00010001 10000100 (bit) */
/* Bit 15 = 0: */
/* Bit 14 = 0: Write "0" */
/* Bits 13-12 = 01: AN1 to AN3 */
/* Bits 11-10 = 00: */
/* Bit 9 = 0: 10 bits */
/* Bit 8 = 1: Scan conversion */
/* Bit 7 = 1: */
/* Bit 6 = 0: Interrupt request clear */
/* Bit 5 = 0: Interrupt disable */
/* Bit 4 = 0:
/* Bits 3-2 = 00: External trigger */
/* Bits 1 = 0: */
/* Bit 0 = 0: Write "0" */
ICR19
(CCR)
IO_ICR[19].bit.ICR = 20;
__EI();
/* Optional values */
/* Disable interrupt */
}
2. A/D interrupt disable
• A/D0 interrupt enable
A/D0 interrupt enable
Register name and bit name
ADCS0
.INT
.INTE
AD0_ch1to3_start()
{
IO_ADCS0.hword = 0x20A4;
/* Bit 6 = 0: Clear AD0 Interrupt Request flag */
/* Bit 5 = 1: Enable AD0 interrupt */
}
3. Interrupts
• Reading the conversion value
Register name and bit name
Disable interrupts and clear the Interrupt
Request flag.
ADCS0
.INT
.INTE
__interrupt void AD0_ch1to3_int()
{
/* An interrupt occurs at the completion of the AN3 conversion. */
ADCS0.hword = 0x2084;
/* Bit 6 = 0: Clear the AD0 Interrupt flag */
/* Bit 5 = 0: Disable AD0 interrupt */
Reading the conversion value
ADT01
ADT02
ADT03
[Optional storage location] = ADT01;
[Optional storage location] = ADT02;
[Optional storage location] = ADT03;
Interrupt enable
ADCS0
.INTE
IO_ADCS0.hword = 0x20A4;
/* Store the AN1 conversion value */
/* Store the AN2 conversion value */
/* Store the AN3 conversion value */
/* Bit 5 = 1: Enable AD0 interrupt */
}
4. Interrupt vectors
Vector table setting
An interrupt routine must be specified in the vector table.
#pragma intvect AD0_ch1to3_int 35
Caution: Clock setup and __set_il (numeric parameter) must have been
performed beforehand.
Note: For the register coding format, refer to FR Lite Family MB91230 Series Sample I/O Register File User's
Guide.
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Chapter 29 A/D Converter
9.Caution
9. Caution
Tips on using the A/D converter are summarized as follows:
• Power-on sequence
Be sure to turn on the MCU power (Vcc, VCC3) before turning on the power to the A/D converter (AVcc, AVRH) and
applying a voltage to the analog input.
• Observe the relation VCC > VCC3 ≥ Avcc ≥ AVRH
Avcc ≥ AN (analog input voltage) ≥ Vss.
• Because the buffer register ADT does not allow for byte access, use half-word or word access instructions to access it
even if the 8-bit format has been selected.
• Input impedance of the analog input pin
The A/D converter has a built-in sample hold circuit to receive the voltage present on the analog input pin in the sample
hold capacitor after the activation of an A/D conversion. Therefore, if the analog input external circuit has a high output
impedance, it may happen that analog input voltage fails to get stabilized within the sampling cycle. For this reason,
keep the output impedance of the external circuit sufficiently low.
If the output impedance of the external circuit cannot be kept sufficiently low, lengthen the sampling time fully.
• As ⏐AVR-AVSS⏐ decreases, an error grows in proportion.
Equivalent Circuit
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Chapter 29 A/D Converter
9.Caution
■ Definitions of A/D Converter Terms
• Resolution
Analog change identifiable to an A/D converter.
• Linearity error
Deviation between the straight line connecting zero transition point
(00 0000 0000 <- -> 00 0000 0001) and full-scale transition point
(11 1111 1110 <- -> 11 1111 1111) from actual conversion characteristics
• Differential linearity error
Deviation of the input voltage required for changing the output by one LSB, from its ideal value
1LSB
VFST - VOT
1022
=
[V]
VOT : Voltage at which digital output transit from (000)H to (001)H
VVFST: Voltage at which digital output transit from (3FE)H to (3FF)H
VNT - {1LSB × (N-1) + VOT}
Digital output N
=
Linearity error
Digital output N
Differential linearity =
error
[LSB]
1LSB
V(N+1)T - VNT
-1
1LSB
[LSB]
VNT: Voltage at which digital output transit from (N+1) to N
Differentional linearity error
Linearity error
3FF
Actual conversion characteristics
Actual conversion characteristics
N+1
3FE
{1LSB (N-- 1)+VOT}
VFST
(Measurement
value)
3FD
VNT
(Measurement
value)
Actual conversion characteristics
003
Digital output
Digital output
004
N
N-1
VNT
002
VFST
(Measurement
value)
Ideal characteristics
N-2
2
001
Actual conversion characteristics
VOT (Measurement value)
AVss
390
Analog input
AVRH
AVss
Analog input
AVRH
Chapter 29 A/D Converter
9.Caution
• Overall error
Difference between an actual vale and a theoretical value, containing a zero transition error/full transition error/linearity
error
1LSB’(Ideal value) =
AVRH - AVSS
1024
[V]
VOT’ (Ideal value) =
VFST’ (Ideal value) =
AVSS + 0.5LSB’
AVRH - 1.5LSB’
[V]
[V]
Overall error of digital output N =
VNT - {1LSB’ × (N - 1) + 0.5LSB’}
1LSB’
VNT: Voltage at which digital output transit from (N+1) to N
Overall error
3FF
1.5 LSB’
3FE
Actual conversion characteristics
3FD
{1LSB (N-- 1)+0.5LSB}
Digital output
004
VNT
(Measurement
value)
Actual conversion characteristics
003
002
Ideal characteristics
001
0.5 LSB’
AVss
Analog input
AVRH
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Chapter 29 A/D Converter
9.Caution
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Chapter 30 D/A Converter
1.Overview
Chapter 30 D/A Converter
1. Overview
The D/A converter converts digital values to analog output values on an R-2R type conversion basis.
Pin
Digital value
D/A converter
Analog output
2. Features
Method: R-2R type conversion
3.3 V interface
Quantity
: 2 (Output: DA0 is the DA0 pin and the DA1 is the DA1 pin.)
Conversion time: 0.6µs (Typ) (Load capacitance = 20pF)
3.0µs (Typ) (Load capacitance = 100pF)
Resolution
: 8-bit resolution
Output range : From AVSS (0V) to 255/256 × AVCC
Interrupt
Others
: None
: Power-down feature available (fixed 0 V output).
Useful for saving current consumption when in sleep mode.
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Chapter 30 D/A Converter
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
D/A converter (0-1)
Register number (:bit)
DAE
0
1
DADR0/
DADR1
DACR0: bit 0
DACR1: bit 0
D/A output disable (0 V output)
D/A output enable
D/A
0
1
Data
DADR0
DADR1
2R
R
Pin
DA0
DA1
1
R
From Port
Data register
AVcc
DACR0
DACR1
Port
function
PFRD:DA0
PFRD:DA1
DA0
PFRD: bit 0
DA1
PFRD: bit 1
0 General-purpose port output
1
D/A output only
2R
2R
Control
2
2R
R
2R
R
0
DA0/PD0
DA1/PD1
Port read
AVss
For a detailed description of the D/A pin circuit, see the “Input Circuit Type - Category F” section of the chapter entitled
“Basic Information”.
Figure 3-2 Register List
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Chapter 30 D/A Converter
4.Registers
4. Registers
4.1 DADR: D/A Data Register
The D/A Data Register sets the output voltage of the D/A converter.
• DADR0(ch0): Address 097H (Access: Byte, Half-word)
• DADR1(ch1): Address 096H (Access: Byte, Half-word)
7
DA7
X
R/W
6
DA6
X
R/W
5
DA5
X
R/W
4
DA4
X
R/W
3
DA3
X
R/W
2
DA2
X
R/W
1
DA1
X
R/W
0
DA0
X
R/W
Bit
Initial value
Attributes
(For the attributes, refer to the “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• The D/S Data Register is not initialized on a reset.
• The setting is “00H” - “FFH”.
4.2 DACR: D/A Control Register
The D/A Control Register controls whether D/A converter output is enabled or disabled.
• DACR0(ch0): Address 093H (Access: Byte, Half-word)
• DACR1(ch1): Address 092H (Access: Byte, Half-word)
7
–
–
RX, W0
6
–
–
RX, W0
5
–
–
RX, W0
4
–
–
RX, W0
3
–
–
RX, W0
2
–
–
RX, W0
1
–
–
RX, W0
0
DAE
0
R/W
bit
Initial value
Attributes
(For the attributes, refer to the “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit7-1: Undefined
At write, always write “0”. At read, the read value is indeterminate.
• bit0: D/A output control
DAE
0
1
Operation
D/A output disabled
D/A output enabled
• Enables a converted analog level to be output from the DA pin.
(To place the DA pin in the output state, it is necessary to set PFRD.DA0=“1” and PFRD.DA1=“1”.)
• The D/A output equals 0.0 V when the D/A output control bit is “0”.
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Chapter 30 D/A Converter
5.Operation
5. Operation
The operations of the D/A converter are described below.
(5)
(1)
DADR0/DADR1
A0h
A0h
60h
(3)
DAE
(7)
PA0/PA1
output level
(4)
(2)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
396
(8)
Digital value setting (software-programmable)
D/A conversion in progress
Output enabled (software-programmable)
Analog value output
Digital value rewrite (software-programmable)
D/A conversion in progress
Output level finalized
Output disabled (software-programmable)
Fixed 0 V output
(6)
(9)
Chapter 30 D/A Converter
6.Setting
6. Setting
Table 6-1 Settings Needed to Use D/A
Setting
Digital value settings
Pin settings
Output enabled
Setting Registers
D/A Data Registers (DADR0-DADR1)
Port Function Register (PFRD)
D/A Control Registers (DACR0-DACR1)
Setting
Procedure*
See 7.1.
See 7.2.
See 7.3.
*:For the setting procedure, refer to the section indicated by the number.
Table 6-2 Settings Needed to Stop D/A Output
Setting
Output halted
Setting Registers
D/A Control Registers (DACR0-DACR1)
Setting
Procedure*
See 7.3.
*:For the setting procedure, refer to the section indicated by the number.
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Chapter 30 D/A Converter
7.Q & A
7. Q & A
7.1 Where should I set digital values?
Write digital values to the D/A Data Registers (DADR0 to DADR1).
Access in a byte or halfword format.
D/A conversion begins immediately on writing.
7.2 How do I program the D/A pins for D/A output?
DA Pin output setting
Setting is accomplished by writing “1” to the output specification bits (PFRD.DA0), (PFRD.DA1).
(Switch the port to DA pin output by software programming.)
Pins
DA0 pin
DA1 pin
Control bit location
DA0 Output specification bit (DA0)
Port Function Register
In PFRD
DA1 Output specification bit (DA1)
7.3 How do I enable or disable D/A output?
Use the D/A output control bits (DACR0.DAE), (DACR1.DAE).
Operations
To disable output
To enable output
D/A output control bit (DAE)
Set “0”.
Set “1”.
O V (= AVss) is output when disabled. This is functional even while in a stopped state.
7.4 How do I activate a D/A conversion?
A conversion begins on writing a digital value. See 7.1.
7.5 What is the formula used to work out the value necessary to produce an expected
voltage?
Equation
Value = [{V (Expected analog value) × 256} / (AVCC)]
To output 2.8 V from the pin with AVCC = 3.3V, for example.
(2.8V × 256) / 3.3V = 217.212 ∴Value = 217
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Chapter 30 D/A Converter
8.Sample Program
8. Sample Program
399
Chapter 30 D/A Converter
9.Caution
9. Caution
• The table below lists the output voltages of the D/A converter.
DADR Settings
D/A Converter Output Voltage Value
00H
0V (AVss=0.0V)
01H
1/256 x AVCC V
02H
2/256 x AVCC V
~
FDH
~
253/256 x AVCC V
FEH
254/256 x AVCC V
FFH
255/256 x AVCC V
When stopped
0V (Avss=0.0V)
• The conversion speed depends on the line load capacitance.
Indicates the conversion speed of the D/A converter.
Load
Capacitance
20pF
100pF
Conversion
Speed (TYP)
0.6µs
3.0µs
• Power supply
• The power supply of the analog circuit in the D /A converter is AVCC.
• The port power requirement for using DA0 and DA1 as general-purpose ports (PD0, PD1) is VCC3IO.
• Use of a power supply within the limits of “Recommended Power Supply Operation Conditions” in the chapter
entitled “Chapter 1 Introduction (Page No.1)” is recommended.
400
Chapter 31 PWC
1.Overview
Chapter 31 PWC
1. Overview
The PWC records the count of the 8-bit counter at the timing of external signal detection.
The signal-to-signal time can be calculated from iterative recordings of the count.
Pin
Rising edge
detection
circuit
8-bit counter
Capture
Buffer
2. Features
•
•
•
•
•
•
Type: Rising edge detection circuit + 8-bit counter (capture register)
Quantity: 2 (PWC0, PWC1)
Edge detection: Rising edge only
Capture value: 8-bit counter count value
Count source: Free-run timer 1 count clock
Interrupt: None
401
Chapter 31 PWC
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
PWC 0-1
Register number
Free-run timer count clock
0
0
1
1
CLK1-0
0
1
0
1
Peripheral clock
CLKP
PWC
0
1
TCCS : bit 1-0
CLKP / 22
CLKP / 24
CLKP / 25
6
CLKP / 2
Count clock
Clock selection
Free-run timer 0
TCCS0
Free-run timer 1
TCCS1
Control
PWCC0
PWCC1
Data
PWCD0
PWCD1
Port direction
DDR2:P22
DDR2:P23
Count stop
Count
Divider
FF H
8-bit counter
From general-purpose
port register
P22 DDR2: bit2
P23 DDR2: bit3
0
Input only
1 Output enable
Count start/
stop
Count start/
stop and capture disable
Control circuit
Disable
Capture
enable/
disable
Capture
enable
Pin read
Clear
Stop
ST
PWCC: bit0
PWC stop and
capture disable
1 PWC activation
0
To OP2/OP3
PWI0/OP2/P22
PWI1/OP3/P23
Capture
Edge detection
(rising edge)
Capture
flag
Capture enable
flag clear
CAPE
0
1
PWCC: bit3
Unaffected
Capture enable
CAPF bit clear
CAPF
Flag
clear
0
1
Flag
set
PWCC: bit2
No data,
capture enable state
Captured and data available
PWCD
Data register
(capture disabled state)
* CAPF="0" is set on CAPE="1."
CAPF="1" is set on a capture operation or ST="0."
Figure 3-2 Register List
402
Pin
PWI0
PWI1
Chapter 31 PWC
4.Registers
4. Registers
4.1 PWCC: PWC Control Register
Controls the operation of the PWC.
• PWCC0 (PWC0): Address 0F0H (Access: Byte, Half-word, Word)
• PWCC1 (PWC1): Address 0F2H (Access: Byte, Half-word, Word)
7
Reserved
6
–
5
–
4
–
3
CAPE
2
CAPF
1
Reserved
0
ST
0
–
–
–
0
0
–
0
R/W0
RX/WX
RX/WX
RX/WX
RX,W
R/WX
R/W0
R/W
Bit
Initial
value
Attributes
(For the attributes, refer to the “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• Bit 7: Reserved: Be sure to write “0”. The read value is the value written.
• Bits 6-4: Undefined
The operation is unaffected by writing. The read value is indeterminate.
• Bit 3: Capture enable
CAPE
0
1
Operation
The operation is unaffected by writing.
Enables the capture operation and sets the Capture flag (CAPF) to “0”.
If the PWC is stopped (ST = “0”), the Capture flag cannot be cleared to “0”.
• Bit 2: Capture flag
CAPF
0
1
Flag Contents
No capture data available (Capture enabled state)
Capture data available (Capture disabled state)
• If the capture flag bit (CAPF) is “1”, captured data can be read from the PWC Data Register (PWCD). A new
capture operation cannot be launched while the capture is disabled (halted).
• If the Capture Flag bit (CAPF) is “0”, the capture is enabled, allowing a new capture operation to be launched.
• The Capture Flag bit (CAPF) is set to “0” by writing “1” to the Capture Enable bit (CAPE).
• If the PWC is halted (the PWC start bit is “0”), “1” can always be read from the Capture Flag bit (CAPF).
• Bit 1: Reserved: Always write “0”.
The read value is the value written.
• Bit 0: PWC start
ST
0
1
Operation
PWC stop
PWC operation start
• This bit controls the operation of the PWC.
• Write “1” to the PWC Start bit (ST) to get the PWC started.
403
Chapter 31 PWC
4.Registers
4.2 PWCD: PWC Data Register
Reads the measurement value of the pulse width.
• PWCD0(PWC0): Address 0F1H (Access: Byte, Half-word, Word)
• PWCD1(PWC1): Address 0F3H (Access: Byte, Half-word, Word)
7
D7
X
R/WX
6
D6
X
R/WX
5
D5
X
R/WX
4
D4
X
R/WX
3
D3
X
R/WX
2
D2
X
R/WX
1
D1
X
R/WX
0
D0
X
R/WX
Bit
Initial value
Attributes
(For the attributes, refer to the “■Meaning of Bit Attribute Symbols (Page No.10)”.)
If the PWC Data register is read in words (Address 0f0h), the bit position of PWCD0 will change from bit 23 to bit 16.
404
Chapter 31 PWC
5.Operation
5. Operation
The operations of the PWC are described below.
(9)
PWI signal
Peripheral clock
(CLKP)
(10)
Detection signal
(Effective edge)
(12)
Counter
B-1
00h
B
(11)
Capture
register
B
(15)
FFh
A
Counter
count value
(2)
B
C
00h
ST
PWI signal
(12)
(9)
(10)
(19)
(20)
(21)
(22)
B
B
(8)
Write CAPE="1"
with software.
Write ST="0" with software.
(16)
(23)
(17)
(24)
(18)
(11)
PWCD
(Buffers)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(21)
Write ST="1" with software.
(3)
(5)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(19)
Time
(1)
Detection signal (Effective edge)
(4)
(= Counter clear)
CAPF
(21)
(13)
(7)
(6)
(24)
FFh
(14)
(20)
(22)
PWC operations are enabled (ST = “1”) by software.
Start incrementing the counter.
PWI signal input (rising edge)
Generate an internal signal on detection of a rising edge.
Counts are not captured because of CAPF = “1” (capture disabled).
Clear the counter on edge detection.
Increment the counter.
The Capture flag is cleared (CAPF = “0”) because capture is enabled by software (CAPE = “1” written).
PWI signal input (rising edge)
Generation of an internal signal on detection of a rising edge
The count is captured in the PWC Data register and the Capture flag is set when an edge is detected and CAPF = “0” is set
(capture enabled) (CAPF = “1”).
Clear the counter on edge detection.
Increment the counter.
The Capture flag is cleared (CAPF = “0”) because capture is enabled by software (CAPE = “1” written).
The counter equals “FFh”, when it stops counting (with the captured value being latched).
PWI signal input (rising edge)
Generate an internal signal on detection of a rising edge.
The count is captured in the PWC Data register and the Capture flag is set when an edge is detected and CAPF = “0” is set
(capture enabled) (CAPF = “1”).
Clear the counter on edge detection.
The count is not captured even though an edge is detected, because of CAPF = “1” (Capture disabled).
The counter stops counting as PWC operations are disabled (ST = “0”) by software.
The Capture flag is set as PWC operations are disabled (ST = “0”) (CAPF = “1”).
405
Chapter 31 PWC
6.Setting
(23) PWI signal input (rising edge)
(24) ST=“0” suppresses rising edge detection, counter clear, and count capture.
6. Setting
Table 6-1 Settings Needed to Use PWC
Setting
Count clock setting of free-run timer 1
Input pin PWI0, PWI1 setting
Enable PWC operations (Count start)
Capture enable (Capture flag clear)
Setting Registers
See “Chapter 24 Free-run Timer (Page
No.271)”.
Data Direction register DDR2
PWC Control Register PWCC
*: For the setting procedure, refer to the section indicated by the number.
406
Setting
Procedure*
–
See 7.1.
See 7.2.
See 7.3.
Chapter 31 PWC
7.Q & A
7. Q & A
7.1 How do I program input pins (PWI, PWI1)?
Use the Data Direction bit (DDR2. P22, DDR2. P23).
Operation
How do I set input pin (PWI0, PWI1)?
Data Direction Bits (P22, P23)
Set “0”.
7.2 How do I enable or disable PWC operations?
Use the PWC Start bit (PWCC0. ST, PECC1. ST).
Operation
To stop the PWC
To start the PWC
(To start counting)
PWC Start Bit (ST)
Set “0”.
Set “1.”
7.3 How do I enable PWC capture operations?
Use the Capture Enable bit (PWCC0. CAPE, PWCC1. CAPE).
Operation
To enable the capture operation of the PWC
(To clear the Capture flag)
Capture Enable Bit (CAPE)
Set “1”.
The operation of the PWC is not affected by writing “0” to the Capture Enable bit.
7.4 How do I clear the counter?
If a rising edge is input to the PWI pin with both the PWC operation and capture being enabled, the counter is cleared on
detection of the edge.
7.5 How do I clear the capture flag?
See 7.3.
7.6 How do I calculate the input signal period?
Edge detection
Period = {Recorded value (PWC Data register value) + 1} × Free-run timer 0 counter clock width
407
Chapter 31 PWC
8.Sample Program
8. Sample Program
Setting Procedure Example 1
Program Example 1
Start counting on the first instance of the input signal,
Capture the count on the next input signal, then
check the CAPF flag and retrieve the value, calculating the average of three
measurements.
void PWC0_sample_1(void)
{
freerun1_initial();
PWC0_initial();
PWC0_start();
freerun1_start();
average();
}
1. Initial settings
• Free-run timer ch1 control
Control register setting
Clock selection >>
Interrupt request flag >>
Enable interrupt request >>
Count operation>>
Whether timer is initialized>>
Clear TCDT>>
Count clock>>
Timer data value setting
• Port
Port PWI0 input setting
• PWC ch0 control
Control register setting
Unused bit>>
Capture Enable bit>>
Capture flag>>
Unused bit>>
PWC Start bit>>
TCCS1
.ECLK
.IVF
.IVFE
.STOP
.MODE
.CLR
.CLK1-0
TCDT1
Register name and bit name
DDR2 .P22
void freerun1_initial(void)
{
IO_TCCS1.byte = 0x12;
IO_TCDT1 = 0x0000;
}
void PWC0_initial(void)
{
IO_PORT1.IO_DDR2.byte = 0x00;
PWCC0
IO_PWCC0.byte = 0x08;
.CAPE
.CAPF
.ST
/*Setting = 0001_0010 */
/* Bit 7 = 0
ECLK Internal clock source */
/* Bit 6 = 0
IVF Interrupt request flag */
/* Bit 5 = 0
IVFE Disable interrupt */
/* Bit 4 = 1
STOP Disable count */
/* Bit 3 = 0
MODE Initialize by reset and clear bit */
/* Bit 2 = 0
CLR Initialize the free-run timer value (None) */
/* Bits 1-0 = 10
CLK1-0 Count clock CLKP/2^5 */
/* Initialize the timer data value */
/* DDR2 PWI0(P22) input*/
/*Setting = 0000_1000 */
/* Bits 7-4 = 0000
Undefined bit */
/* Bit 3 = 1
CAPE Capture enabled state */
/* Bit 2 = 0
CAPF Capture enabled state */
/* Bit 1 = 0
Undefined bit */
/* Bit 0 = 0
ST PWC stop */
}
2. Activation
• Start PWC ch0
Start the PWC operation
• Start free-run timer ch1
Activates the count operation
Register name and bit name
PWCC0 .ST
Register name and bit name
TCCS1 .STOP
3. Calculation
• Calculation
(Optional)
••••••
Check the Capture flag.
••••••
void PWC0_start(void)
{
IO_PWCC0.bit.ST = 1;
}
void freerun1_start(void)
{
IO_TCCS1.bit.STOP = 0;
}
/* Bit 0 = 1
ST PWC operation */
/* Bit 4 = 1
STOP Enable count */
void average(void)
{
for(count = 0; count<4; count++)
{
while(!IO_PWCC0.bit.CAPF){}
data = IO_PWCD0;
if(count = = 1) a = data;
else if(count = = 2) b = data;
else if(count = = 3) {
c = data;
av = (a+b+c)/3;
}
IO_PWCC0.bit.CAPE = 1;
}
Clear the Capture flag and start the capture operation.
/* Check the Capture flag */
/* Calculate the average value */
/* Bit 3 = 1
CAPE Clear the CAPF bit and sets the capture */
state */
}
Caution: Clock setup must have been performed beforehand. See the
chapter entitled "Clock."
408
Note: For the register coding format, refer to "FR60Lite Family MB91230 Series Sample I/O Register File User's Guide".
Chapter 31 PWC
9.Caution
9. Caution
• When the counter equals “FFH”, it stops counting and latches the count until the next instance of edge detection.
• When the PWC Start bit (ST) is “0”, the counter does not count.
• When the capture flag (CAPF) is “1”, the capture operation is not functional.
• If the count is captured at the first input edge, the captured value would be indeterminate.
• Be sure to write “0” to bit 7 of the PWC Control register PWCC.
If “1” has been written to the register, write “0” to it after its operation has stopped to let the register return to normal.
• Be sure to write “0” to bit 1 of PWC Control register PWCC.
If “1” has been written to the register, write “0” to it to let the register return to normal.
• The Capture flag (CAPF) cannot be cleared when the PWC operation is stopped (ST = “1”). Be sure to clear the
Capture flag (CAPF) in the (ST = “0”) state.
409
Chapter 31 PWC
9.Caution
410
Chapter 32 Up/Down Counter
1.Overview
Chapter 32 Up/Down Counter
1. Overview
Triggered by an input signal, 16-bit Up/Down Counter counts up or down within the range of 0 to 65535. Specifically,
Up/Down Counter running in the phase difference count mode is suitable for counting the encoder pulse of motors and
other equipment. When encoder's output signals of phase A, phase B and phase Z are applied, the counter can achieve
precise counting of rotation angles or number of revolutions.
Reload/Compare
value
/
Edge detection
External input
A/B/Z
Selection
Internal clock
Compare-match
Underflow
Reload
Up/Down Counter
Clear
2. Feature
• Format: 16 bit length or 8 bit × 2
• Quantity: 1 For 16 bit (Input: AIN0/BIN0/ZIN0)
2 For 8 bit (Input: AIN0/BIN0/ZIN0, AIN1/BIN1/ZIN1)
• Count mode: Four types
• Timer mode
Count down the internal clock.
• Up/down count mode
Counting up is triggered by an AIN pin signal.
Counting down is triggered by a BIN pin signal.
• Phase difference count mode (Multiply by 2
Counting is triggered by the rising edge of a BIN pin signal. Up/Down Counter counts up or down, depending on
the AIN pin signal level.
• Phase difference count mode (Multiply by 4
•
•
•
•
Counting is triggered by the rising edge of AIN and BIN pin signals. Up/Down Counter counts up or down,
depending on the ZIN pin signal level.
Count Source
Internal clock (Timer mode): Peripheral clock (CLKP) divided by 2 or 8
External trigger (Up/down count mode): Edge detection (Rising/falling/both edges/no detection)
Counting range: Any value between 0 and 65535 can be set.
Interrupt: Select from the following four types:
(1) Compare-match interrupt
(2) Underflow interrupt
(3) Overflow interrupt
(4) Count direction change interrupt
Others:
Whether counting is performed or not can be controlled based on the pin input level.
The software can activate or deactivate the counter.
The ZIN pin has two functions: Counter clear and gate.
The count direction flag allows identification of the previous count direction.
411
Chapter 32 Up/Down Counter
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Up/Down Counter 0 (8 Bit Mode)
8 bit mode
M16E
0
CFIE CCR0: bit 13
0 Disable interrupts
1 Enable interrupts
CCR0 : bit15
8 bit mode
CDCF CCR0: bit14
0 No change direction
1 Direction changed
WRITE 0: Flag clear
CMS1-0
CCR0: bit11-10
0 0 Timer mode (Countdown only)
0 1
Up/down count mode
1 0 Phase difference count mode (Multiply by 2)
1 1 Phase difference count mode (Multiply by 4)
Peripheral clock
CLKP
0
0
1
1
CSTR CSR0: bit7
0 Stop counting
1 Start counting
Activation
0
1
0
1
UDC0 interrupt
(#50)
OR
CSR0: bit 1-0
-
Write: Disabled, Read only
No input
Countdown
Countup
Both countdown and countup
Up/Down Counter (Read only)
OVFF CSR0: bit3
No overflow
0
Overflowed
1
UDIE CSR0: bit5
0 Disable interrupts
1 Enable interrupts
WRITE 0: Flag clear
Selector/Count Control
CLKS CCR0: bit 12
0 CLKP divided by 2
1 CLKP divided by 8
P32 DDR3: bit2
0 Input only
1 Enable output
Read from port
AIN0/P32
Edge
detection
BIN0/P33
UDCR0
Read
from
port
ZIN0/P34
P34 DDR3: bit4
Input only
0
1 Enable output
UDFF CSR0: bit2
0 No underflow
1 Underflowed
1
Counter clear
Reload
CTUT CCR0: bit6
0
No impact
1
Data transfer
* Only 16 bit transfer is enabled
while counting stops.
0
RLDE CCR0: bit4
0 Disable reload
1 Enable reload
CES1-0 CCR0: bit 9-8
0 0 Disable edge detection
0 1 Enable falling edge detection
1 0 Enable rising edge detection
1 1 Enable both edge detection
From port data
register
0
0
CMPF CSR0: bit4
0 Compare match
1 No compare match
Compare
1
CITE CSR0: bit6
0 Disable interrupts
1 Enable interrupts
RCR0
UDCC CCR0: bit2
Clear
0
Disabling
1
Edge
detection
1
WRITE 0: Flag clear
Reload/compare register (Write only)
Read from
port
OR
WRITE 0: Flag clear
OR
Gate
From port data
register
412
1
UDF1-0
-
Prescaler
From port data
register
P33 DDR3: bit3
0 Input only
1 Enable output
0
CCR0: bit1-0, bit 2
CGSC
CGE1-0 0: Counter clear function 1: Gate function
0 0 Disable edge detection Disable level detection
0 1 Enable falling edge detection Enable LOW level detection
1 0 Enable rising edge detection Enable HIGH level detection
Disable setting
Disable setting
1 1
0
1
UCRE
CCR0:bit5
Disable counter clear
0
Enable counter clear
1
Chapter 32 Up/Down Counter
3.Configuration
Figure 3-2 Configuration Diagram
Up/Down Counter 1 (8 Bit Mode)
CFIE CCR1: bit 13
0 Disable interrupts
1 Enable interrupts
8 bit mode
M16E CCR0 : bit15
0
CDCF CCR1: bit14
0 No change direction
1 Direction changed
WRITE 0: Flag clear
8 bit mode
CMS1-0
CCR1: bit11-10
Timer mode (Countdown only)
0 0
0 1
Up/down count mode
1 0 Phase difference count mode (Multiply by 2)
1 1 Phase difference count mode (Multiply by 4)
Peripheral clock
CLKP
CLKS CCR1: bit 12
0 CLKP divided by 2
1 CLKP divided by 8
Read from port
AIN1/P35
Edge
detection
BIN1/P36
Read
from
port
From port data
register
ZIN1/P37
P37 DDR3: bit7
Input only
0
1 Enable output
0
1
0
1
Write: Disabled, Read only
No input
Countdown
Countup
Both countdown and countup
OVFF CSR1: bit3
No overflow
0
Overflowed
1
1
Clear
Reload
CTUT CCR1: bit6
No impact
0
Data transfer
1
0
RLDE CCR1: bit4
0 Disable reload
1 Enable reload
UDFF CSR1: bit2
0 No underflow
1 Underflowed
0
Reload/compare register (Write only)
UDCC CCR1: bit2
0
Clear
1
Disabling
Edge
detection
1
WRITE 0: Flag clear
CITE CSR1: bit6
0 Disable interrupts
1 Enable interrupts
RCR1
Read from
port
1
0
CMPF CSR1: bit4
0 Compare match
1 No compare match
Compare
* Only 16 bit transfer is enabled
while counting stops.
-0 CCR1: bit 9-8
CES1-0
0 0 Disable edge detection
0 1 Enable falling edge detection
1 0 Enable rising edge detection
1 1 Enable both edge detection
OR
WRITE 0: Flag clear
OR
From port data
register
UDIE CSR1: bit5
0 Disable interrupts
1 Enable interrupts
WRITE 0: Flag clear
UDCR1
Gate
P36 DDR3: bit6
Input only
0
1 Enable output
0
0
1
1
UDC1 interrupt
(#51)
OR
CSR1: bit 1-0
-0
Up/Down Counter (Read only)
Selector/Count Control
P35 DDR3: bit5
Input only
0
1 Enable output
UDF1-0
-
CSTR CSR1: bit7
0 Stop counting
1 Start counting
Activation
Prescaler
From port data
register
0
1
0
1
UCRE
CCR1:bit5
0 Disable counter clear
1 Enable counter clear
CCR1: bit 2-0
CGSC
1: Gate function
CGE1--0 0: Counter clear function
0 0 Disable edge detection Disable level detection
0 1 Enable falling edge detection Enable LOW level detection
1 0 Enable rising edge detection Enable HIGH level detection
Disable setting
Disable setting
1 1
413
Chapter 32 Up/Down Counter
3.Configuration
Figure 3-3 Configuration Diagram
Up/Down Counter (16 Bit Mode)
16 bit mode
M16E
1
CFIE
CCR0: bit 13
0
Disable interrupts
Enable interrupts
1
CCR0 : bit15
16 bit mode
0
1
CDCF CCR0: bit14
0 No change direction
1 Direction changed
WRITE 0: Flag clear
0
0
1
1
CMS1-0
CCR0: bit11-10
0 Timer mode (Countdown only)
Up/down count mode
1
0 Phase difference count mode (Multiply by 2)
1 Phase difference count mode (Multiply by 4)
Peripheral clock
CLKP
UDF1-0
CSR0: bit 1-0
Write: Disabled, Read only
No input
0
1
Countdown
0
Countup
1 Both countdown and countup
0
0
1
1
Activation
CSTR CSR0: bit7
0 Stop counting
1 Start counting
Read from port
AIN0/P32
UDCR0
Reload
CTUT CCR0: bit6
No impact
0
Data transfer
1
* Only 16 bit transfer is enabled
while counting stops.
Edge
detection
OR
BIN0/P33
UDFF CSR0: bit2
0 No underflow
1 Underflowed
1
Counter clear
Selector
P32 DDR3: bit2
0 Input only
1 Enable output
CLKS CCR0: bit 12
0 CLKP divided by 2
1 CLKP divided by 8
UDIE CSR0: bit5
0 Disable interrupts
1 Enable interrupts
WRITE 0: Flag clear
UDCR1
From port data
register
OVFF CSR0: bit3
No overflow
0
Overflowed
1
Up/Down Counter (Read only)
Prescaler
UDC0 interrupt
(#50)
OR
RCR1
1
0
0
WRITE 0: Flag clear
0
RLDE CCR0: bit4
0
Disable reload
1
Enable reload
OR
CMPF CSR0: bit4
Compare match
0
1 No compare match
Compare
1
WRITE 0: Flag clear
CITE CSR0: bit6
0 Disable interrupts
1 Enable interrupts
RCR0
Reload/compare register (Write only)
Gate
P33 DDR3: bit3
Input only
0
1 Enable output
Read
from
port
From port data
register
ZIN0/P34
P34 DDR3: bit4
0
Input only
1 Enable output
0
CES1-0
CCR0: bit 9-8
Disable edge detection
0 0
0 1 Enable falling edge detection
1 0 Enable rising edge detection
1 1 Enable both edge detection
Read from
port
0
1
Edge
detection
From port data
register
1
UCRE
CCR0:bit5
Disable counter clear
0
Enable counter clear
1
CCR0: bit2
Counter clear
No impact
CCR0: bit1-0, bit 2
CGSC
- 0: Counter clear function
1: Gate function
CGE1-0
0
0
1
1
0
1
0
1
Disable edge detection Disable level detection
Enable falling edge detection Enable LOW level detection
Enable rising edge detection Enable HIGH level detection
Disable setting
Disable setting
Figure 3-4 Register List
Note: For ICR registers and interrupt vectors, refer to “Chapter 20 Interrupt Control (Page No.207)”.
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Chapter 32 Up/Down Counter
3.Configuration
Figure 3-5 Register List
Note: For ICR registers and interrupt vectors, refer to “Chapter 20 Interrupt Control (Page No.207)”.
Figure 3-6 Register List
Note: For ICR registers and interrupt vectors, refer to “Chapter 20 Interrupt Control (Page No.207)”.
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Chapter 32 Up/Down Counter
4.Register
4. Register
4.1 CCR: Counter Control Register
This register is used to control behaviors of Up/Down Counter.
• CCR0 (Up/Down Counter0): Address 00B4H (Access: Byte, Half-word, Word)
• CCR1 (Up/Down Counter1): Address 00B8H (Access: Byte, Half-word, Word)
15
M16E/
Reserved
0
R/W *
7
Reserved
0
R/W0
14
13
12
11
10
9
8
CDCF
CFIE
CLKS
CMS1
CMS0
CES1
CES0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value
Attribute
4
RLDE
0
R/W
3
UDCC
1
R1,W
2
CGSC
0
R/W
1
CGE1
0
R/W
0
CGE0
0
R/W
bit
6
CTUT
0
R/W
5
UCRE
0
R/W
bit
Initial value
Attribute
(For attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit15: Enable 16 bit mode (Up/Down Counter 0 only)
M16E
0
1
Enable 16 bit mode
8 bit × 2 channel operation mode (8 bit mode)
16 bit × 1 channel operation mode (16 bit mode)
Note: Reserved bit (Up/Down Counter0). Be sure to write “0”. The read value is the value written.
• bit14: Count direction change flag (Interrupt request flag)
CDCF
0
1
Direction change detection
When read:
When written:
A direction change has not made.
Clear the flag.
Direction change has been made once or more.
Writing does not affect the operation.
• When the count direction has been changed during count operation, the count direction change flag (CDCF) is set to
“1”.
• Since the count direction is set to countdown immediately after a reset, the count direction change flag (CDCF) is
set to “1” on counting up following the reset.
• To enable interrupt requests, the interrupt request permission bit must be set (CFIE=“1”).
• bit13: Enable count direction change interrupt request
CFIE
0
1
Direction change interrupt request
Disable direction change interrupt requests.
Enable direction change interrupt requests.
When the interrupt request permission bit is set to “1”, the interrupt request flag (CDCF) is enabled.
• bit12: Select internal prescaler
CLKS
Internal clock frequency
0
FCLKP/2
1
FCLKP/8
FCLKP: Frequency of Peripheral clock (CLKP)
This setting is enabled only in the timer mode, in which only countdown is performed.
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Chapter 32 Up/Down Counter
4.Register
• bit11,10: Select count mode
CMS1
0
0
1
1
CMS0
0
1
0
1
Count mode
Timer mode (Countdown)
Up/down count mode
Phase difference count mode (Multiply by 2)
Phase difference count mode (Multiply by 4)
• bit9,8: Select count clock edge
CES1
0
0
1
1
CES0
0
1
0
1
Edge selection
Disable edge detection.
Detect a falling edge.
Detect a rising edge.
Detect both rising and falling edges.
This bit is used in the up/down count mode (CMS1,CMS0= “01”) to select the edge, to be detected, of an AIN and
BIN pin signal. This setting is disabled in modes other than the up/down count.
• bit7: Reserved.
Be sure to write “0”. The read value is the value written.
• bit6: Counter write
CTUT
0
1
Data transfer
No impact on operation
Transfer data from the RCR register to UDCR.
During count operation (CSR.CSTR=“1”), the counter write bit must not be set to “1”.
• bit5: Enable compare-match clear
UCRE
0
1
Compare-match counter clear
Disable counter clear due to compare-match.
Enable counter clear due to compare-match.
This setting does not affect clear operations other than compare-match, such as ZIN pin clear.
• bit4: Enable reload
RLDE
0
1
Reload function
Disable reload function.
Enable reload function.
If the reload enable bit is set to “1”, the reload/compare value (RCR) is transferred to Up/Down Counter (UDCR)
when Up/Down Counter is underflowed.
• bit3: Clear UDCR
UDCC
0
1
Counter clear
Set (Clear) Up/Down Counter (UDCR) to “0000H”.
No impact on operation
• bit2: Select counter clear/gate
CGSC
0
1
ZIN pin function
Counter clear function
Gate function
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Chapter 32 Up/Down Counter
4.Register
• bit1,0: Select counter clear/gate edge
418
CGE1
CGE0
0
0
1
1
0
1
0
1
Edge detection/level selection
When the counter clear function is selected
When the gate function is selected
(CGSC=“0”)
(CGSC=“1”)
Disable edge detection.
Disable level detection. (Disable count.)
Detect a falling edge.
Detect a “L” level.
Detect a rising edge.
Detect a “H” level.
Disable setting.
Disable setting.
Chapter 32 Up/Down Counter
4.Register
4.2 CSR: Count Status Register
This register is used to control Up/Down Counter and to indicate the status of the counter.
• CSR0 (Up/Down Counter 0): Address 00B7H (Access: Byte, Word)
• CSR1 (Up/Down Counter 1): Address 00BBH (Access: Byte, Word)
7
CSTR
0
R/W
6
CITE
0
R/W
5
UDIE
0
R/W
4
CMPF
0
R/W0
3
OVFF
0
R/W0
2
UDFF
0
R/W0
1
UDF1
0
R/WX
0
UDF0
0
R/WX
bit
Initial value
Attribute
(For attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit7: Enable count operation
CSTR
0
1
Count operation
Disable count operation.
Enable count operation. (Activate counter.)
• bit6: Enable compare interrupt requests
CITE
0
1
Compare interrupt request
Disable compare interrupt requests.
Enable compare interrupt requests.
Setting the interrupt request permission bit to “1” enables the interrupt request flag (CMPF).
• bit5: Enable overflow/underflow interrupt requests
UDIE
0
1
Overflow/underflow interrupt request
Disable overflow/underflow interrupt requests.
Enable overflow/underflow interrupt requests.
Setting the interrupt request permission bit to “1” enables the interrupt request flag (OVFF or UDFF).
• bit4: Compare detection flag
CMPF
0
1
Compare detection
When read:
Comparison results do not agree.
Comparison results agree.
When written:
Clear the flag.
Disable setting.
To enable interrupt requests, the interrupt request permission bit must be set (CITE= “1”).
• bit3: Overflow detection flag
OVFF
0
1
Overflow detection
When read:
No overflow
An overflow has occurred.
When written:
Clear the flag.
Disable setting.
To enable interrupt requests, the interrupt request permission bit must be set (UDIE= “1”).
• bit2: Underflow detection flag
UDFF
0
1
Underflow detection
When read:
No Underflow
An underflow has occurred.
When written:
Clear the flag.
Disable setting.
To enable interrupt requests, the interrupt request permission bit must be set (UDIE= “1”).
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Chapter 32 Up/Down Counter
4.Register
• bit1,0: Up/down flag
UDF1
0
0
1
1
420
UDF0
0
1
0
1
Previous count operation
No input
Count down
Count up
Both of count up and count down
Chapter 32 Up/Down Counter
4.Register
4.3 UDCR: Up/Down Counter Register
This register is used to read the count value of Up/Down Counter.
Depending on the setting of the 16-bit mode enable bit (CCR.M16E), this register behaves differently.
■ 16 Bit Mode (M16E= “1”)
In the 16 bit mode, this register functions as 16-bit up/down counter register.
• UDCR (Up/Down Counter): Address 00B2H (Access: Half-word)
15
D15
0
R/WX
14
D14
0
R/WX
13
D13
0
R/WX
12
D12
0
R/WX
11
D11
0
R/WX
10
D10
0
R/WX
9
D09
0
R/WX
8
D08
0
R/WX
7
D07
0
R/WX
6
D06
0
R/WX
5
D05
0
R/WX
4
D04
0
R/WX
3
D03
0
R/WX
2
D02
0
R/WX
1
D01
0
R/WX
0
D00
0
R/WX
bit
Initial value
Attribute
bit
Initial value
Attribute
(For attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
For the 16 bit mode, be sure to read by half-word access.
■ 8 Bit Mode (M16E=“0”)
In the 8 bit mode, this register functions as a 8-bit up/down counter register 0 and a 8-bit up/down counter register 1.
• UDCR1 (Up/Down Counter 1): Address 00B2H (Access: Byte, Half-word)
• UDCR0 (Up/Down Counter 0): Address 00B3H (Access: Byte, Half-word)
7
D07
6
D06
5
D05
4
D04
3
D03
2
D02
1
D01
0
D00
0
0
0
0
0
0
0
0
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
bit
Initial
value
Attribute
(For attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
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Chapter 32 Up/Down Counter
4.Register
4.4 RCR: Reload/Compare Register
This register is used to reload a value to Up/Down Counter and for comparison.
This register is also used to write to Up/Down Counter.
Depending on the setting of the 16 bit mode enable bit (CCR.M16E), this register behaves differently.
■ 16 Bit Mode (M16E=“1”)
In the 16 bit mode, this register functions as 16-bit reload/compare register.
• RCR (Reload compare): Address 00B0H (Access: Byte, Half-word)
15
D15
0
RX, W
14
D14
0
RX, W
13
D13
0
RX, W
12
D12
0
RX, W
11
D11
0
RX, W
10
D10
0
RX, W
9
D09
0
RX, W
8
D08
0
RX, W
bit
7
D07
0
6
D06
0
5
D05
0
4
D04
0
3
D03
0
2
D02
0
1
D01
0
0
D00
0
Initial value
RX, W
RX, W
RX, W
RX, W
RX, W
RX, W
RX, W
RX, W
Attribute
Initial value
Attribute
bit
(For attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• The reload and compare values are same.
When Up/Down Counter counts up, the value in RCR is used as a compare value.
When Up/Down Counter counts down, underflow is generated and the value in RCR is used as a reload value for
reloading.
(Up/Down Counter counts between 0000H and the reload/compare value.)
• In the 16 bit mode, be sure to write by half-word access.
■ 8 Bit Mode (M16E=“0”)
In the 8 bit mode, this register functions as 8-bit reload/compare register 0 and 8-bit reload/compare register 1.
• RCR1 (reload compare 1): Address 00B0H (Access: Byte, Half-word)
• RCR0 (reload compare 0): Address 00B1H (Access: Byte, Half-word)
7
D07
0
RX, W
6
D06
0
RX, W
5
D05
0
RX, W
4
D04
0
RX, W
3
D03
0
RX, W
2
D02
0
RX, W
1
D01
0
RX, W
0
D00
0
RX, W
bit
Initial value
Attribute
(For attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• The reload and compare values are same.
When Up/Down Counter counts up, the value in RCR is used as a compare value.
When Up/Down Counter counts down, underflow is generated and the value in RCR is used as a reload value for
reloading.
(Up/Down Counter counts between 0000H and the reload/compare value.)
• Perform the following procedure to write to Up/Down Counter.
(1) Stop counting.
(2) Write a value to the reload/compare register.
(3) Write “1”to the counter write bit (CCR.CTUT).
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Chapter 32 Up/Down Counter
5.Operation
5. Operation
This section describes each operation mode for Up/Down Counter.
5.1 Timer Mode CMS[1:0]=“00”
Reload value
Reload value
FCLKP divided by 2
Interrupt
request
Countdown
FCLKP divided by 8
(5)
Reload value
(8)
(3)
CLKS, RLDE
(1)
CGSC
(2)
CSTR
(9)
(3)
(6)
Underflow
(Interrupt request)
Interrupt request enabled
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(4)
Cleared by
software
(10)
(9)
Cleared by
software
Cleared by
software
(7)
An appropriate bit (Reload enable (RLDE)) is set.
Up/Down Counter is cleared (“0” is written to (CGSC).)
(The software) activates Up/Down Counter.
An underflow occurs.
The reload value is reloaded to Up/Down Counter.
The software clears the underflow flag.
The software enables interrupts.
Up/Down Counter counts down.
An underflow occurs. (An interrupt request has been made.)
The software clears the underflow flag.
Repeat (8) to (10).
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Chapter 32 Up/Down Counter
5.Operation
5.2 Up/Down Count Mode CMS[1:0]=“01”
Reload value
Reload value
FCLKP divided by 2
Interrupt
request
enabled
Countdown
FCLKP divided by 8
(5)
Reload value
(8)
(3)
CLKS, RLDE
(1)
CGSC
(2)
CSTR
(3)
Underflow
(Interrupt request)
(4)
(9)
(6)
Interrupt request enabled
Cleared by
software
(10)
(9)
Cleared by
software
Cleared by
software
(7)
Up/Down Counter clear control using the ZIN pin
(1)
Appropriate bits (Counting enable (CSTR), Reload enable (RLDE), Clear enable (UCRE)) are set.
(2)
When pulse input to the AIN pin is detected, Up/Down Counter counts up.
(3)
The count direction change flag is set to “1”.
(4)
When an edge is applied to the ZIN pin, Up/Down Counter is cleared.
(5)
Continuous pulse input to the AIN pin causes Up/Down Counter to count up.
(6)
The Up/Down Counter's count value agrees with the compare value (compare-match) and the compare-match
flag is set to “1”.
(7)
Compare-match clears Up/Down Counter.
(8)
Continuous pulse input to the AIN pin causes Up/Down Counter to count up.
(9)
When pulse input to the AIN pin stops, Up/Down Counter stops counting.
(10) When pulse input to the BIN pin is detected, Up/Down Counter counts down.
(11) The count direction change flag is set to “1”.
(12) Continuous pulse input to the BIN pin causes Up/Down Counter to count down.
(13) Up/Down Counter is underflowed and the underflow flag is set to “1”.
(14) The underflow causes the reload value to be reloaded to Up/Down Counter.
(15) Next time when Up/Down Counter counts down, the compare-match flag is set to “1”.
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Chapter 32 Up/Down Counter
5.Operation
5.3 Up/Down Count Mode CMS[1:0]=“01”
ZIN=Gate control
(12)
(6)
(7)
(2)
(11)
(8)
CS TR, RLDE, UCRE
UDCC
AIN
(1)
(2)
(3)
(6)
(7)
BIN
CGE[1:0]=“10”
(12)
(9)
(4)
“H”
(8)
(10)
“H”
(13)
ZIN (Gate)
Countgate at the ZIN pin
(1)
Appropriate bits (Counting enable [CSTR], Reload enable [RLDE] and Clear enable [UCRE]) are set.
(2)
Up/Down Counter is cleared. (“0” is written to [CGSC].)
(3)
Neither pulse input to the AIN pin nor counting at the ZIN pin being enabled, Up/Down Counter neither counts
up nor down.
(4)
Counting is enabled at the ZIN pin.
(5)
Up/Down Counter counts up.
(6)
When pulse input to the AIN pin stops, Up/Down Counter stops counting.
(7)
When a pulse input to the BIN pin is detected, Up/Down Counter counts down.
(8)
When counting is disabled at the ZIN pin, Up/Down Counter stops counting.
(9)
Neither pulse input to the AIN pin nor counting at the ZIN pin being enabled, Up/Down Counter neither counts
up nor down.
(10) Counting is enabled at the ZIN pin.
(11) Up/Down Counter counts up.
(12) When pulse input to the AIN pin stops, Up/Down Counter stops counting.
(13) Counting is disabled at the ZIN pin.
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Chapter 32 Up/Down Counter
5.Operation
5.4 Phase Difference Count Mode (Multiply by 2) CMS[1:0]=“10”
Frequency multiplied by 2 in phase difference count mode:
On the rising and falling edges at the BIN count pin, Up/Down Counter counts up or down, depending on the
voltage level at the AIN pin.
Count value
Time
AIN
BIN
• Count up Conditions:
• When the voltage level at the AIN pin detected on the rising edge at the BIN pin is “H”
• When the voltage level at the AIN pin detected on the falling edge at the BIN pin is “L”
• Count down Conditions:
• When the voltage level at the AIN pin detected on the rising edge at the BIN pin is “L”
• When the voltage level at the AIN pin detected on the falling edge at the BIN pin is “H”
When this count mode is selected, selection of the edge to be detected using CES1 or CES0 is disabled.
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Chapter 32 Up/Down Counter
5.Operation
5.5 Phase Difference Count Mode (Multiply by 4) CMS[1:0]=“11”
Frequency multiplied by 4 in phase difference count mode:
On the rising and falling edges at the BIN pin, Up/Down Counter counts up or down, depending on the voltage
level at the AIN pin, and on the rising and falling edges at the AIN pin, Up/Down Counter counts up or down,
depending on the voltage level at the BIN pin.
Count value
Time
AIN
BIN
• Count up Conditions:
• When the voltage level at the AIN pin detected on the rising edge at the BIN pin is “H”
• When the voltage level at the AIN pin detected on the falling edge at the BIN pin is “L”
• When the voltage level at the BIN pin detected on the rising edge at the AIN pin is “L”
• When the voltage level at the BIN pin detected on the falling edge at the AIN pin is “H”
• Count down Conditions:
• When the voltage level at the AIN pin detected on the rising edge at the BIN pin is “L”
• When the voltage level at the AIN pin detected on the falling edge at the BIN pin is “H”
• When the voltage level at the BIN pin detected on the rising edge at the AIN pin is “H”
• When the voltage level at the BIN pin detected on the falling edge at the AIN pin is “L”
When Up/Down Counter is used to count encoder output, high precise counting of rotation angles and number of
revolutions, as well as detecting of rotation directions, can be achieved by applying encoder output signals of phase A,
phase B and phase Z to the AIN, BIN and ZIN pins, respectively.
Note that when this count mode is selected, selection of the edge to be detected using CES1 or CES0 is disabled.
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Chapter 32 Up/Down Counter
5.Operation
5.6 Clear Timing
(1) When a clear request (Compare-match, ZIN edge detection and writing “0” to the clear bit (UDCC)) is made, clear is
performed next time when Up/Down Counter counts up.
Compare value
0066
H
Count value
0065
H
0066
H
0001
H
0000
H
Clear request
Countup
Clear timing
(2) Even if a clear request (Compare-match, ZIN edge detection and writing “0” to the clear bit (DCC)) is made, clear is
not performed when UP/Down Counter counts neither up nor down.
Compare value
0066
H
Count value
0065
H
0066
H
0065
H
Clear request
Countup
Countdown
Clear timing (None)
(3) If Up/Down Counter does not count up after a clear request (Compare-match, ZIN edge detection and writing “0” to
the clear bit (DCC)) is made, the counter is cleared when counting is disabled (CSTR=“0”).
Compare value
0066
H
Count value
0065
H
0066
H
0000
H
Clear request
Countup
CSTR or ZIN gate function
(4) When Up/Down Counter exceeds the maximum count, the overflow flag is set to “1” and the counter value is
returned to “0000”.
Count value
Countup
Overflow
428
FFFEH
FFFFH
0000
H
Chapter 32 Up/Down Counter
5.Operation
5.7 Reload Timing
The next time when Up/Down Counter counts down below “0000”, an underflow occurs (an interrupt request is made)
and then reloading is performed.
Compare value
0066
H
Count value
0001
H
0000
H
0066
H
0065
H
0064
H
Countdown
Underflow
Reload timing
Note: If clear and reload operations occur at the same time, clear takes precedence.
5.8 Writing a Value to Counter
(2)
RCR
XXH
67 H
67 H
Up/Down Counter
(4)
CSTR
CTUT
(1)
(2)
(3)
(4)
(1)
(3)
Counting of Up/Down Counter is disabled.
A value is written to PCR.
“1” is written to the count write bit (CTUT).
A value is transferred from the reload/compare register (RCR) to Up/Down Counter.
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Chapter 32 Up/Down Counter
6.Setting
6. Setting
Table 6-1 Required Settings to Run Up/Down Counter in Timer Mode
Setting registers
Setting
procedure*
Set the reload value.
Reload/compare register (RCR0,RCR1)
See 7.16.
(Optional)
Set a value to Up/Down Counter
or
Clear the count value of Up/Down Counter.
Reload/compare register (RCR0,RCR1)
See 7.5.
Count control register (CRL0,CCR1)
See 7.8.
Setting
Set a bit length.
See 7.1.
Set the count mode to timer mode.
See 7.2.
Select a count source.
Count control register (CCR0,CCR1)
Enable reloading at the time of underflow.
See 7.7.
See
7.9 and 7.10
Enable count control (clear/gate) using the ZIN pin.
Activate Up/Down Counter.
See 7.3.
Count status register (CSR0,CSR1)
See 7.11.
*: For the setting procedure, refer to the section indicated by the number.
Table 6-2 Required Settings to Run Up/Down Counter in Up/Down Count Mode
Setting registers
Setting
procedure*
Set the reload value/compare value.
Reload/compare register (RCR0,RCR1)
See 7.16.
(Optional)
Set a value to Up/Down Counter
Or
Clear the count value of Up/Down Counter.
Reload/compare register (RCR0,RCR1)
See 7.5.
Count control register (CCR0,CCR1)
See 7.8.
Setting
Set a bit length.
See 7.1.
Set the count mode to up/down count mode.
See 7.2.
Select the edge, to be detected, of a signal (AIN or BIN),
for which counting is performed.
Enable clearing of Up/Down Counter at the time of the
counting following a compare-match.
Enable reloading at the time of underflow.
Count control register (CCR0,CCR1)
See 7.6.
See 7.7.
See
7.9 and 7.10
Enable count control (clear/gate) using the ZIN pin.
Activate Up/Down Counter.
Count status register (CSR0,CSR1)
*: For the setting procedure, refer to the section indicated by the number.
430
See 7.4.
See 7.11.
Chapter 32 Up/Down Counter
6.Setting
Table 6-3 Required Settings to Run Up/Down Counter in Phase Difference Count Mode (Multiply by 2 or 4)
Setting
Set the reload value/compare value.
(Optional)
Set a value to Up/Down Counter
or
Clear the count value of Up/Down Counter.
Setting registers
Setting
procedure*
Reload/compare register
(RCR0,RCR1).
See 7.16
Reload/compare register (RCR0,RCR1)
See 7.5
Count control register (CCR0,CCR1)
See 7.8
Set a bit length.
See 7.1
Set the count mode to phase difference count mode
(Multiply by 2 or 4).
Enable clearing of Up/Down Counter at the time of the
counting following a compare-match.
Enable reloading at the time of underflow.
See 7.2
Count control register (CCR0,CCR1)
See 7.7
See
7.9 and 7.10
Enable count control (clear/gate) using the ZIN pin.
Activate Up/Down Counter.
See 7.6
Count status register (CSR0,CSR1)
See 7.11
*: For the setting procedure, refer to the section indicated by the number.
Table 6-4 Required Settings for Up/Down Counter Interrupt
Setting
Set Up/Down Counter interrupt vectors and Up/Down
Counter interrupt levels.
Set Up/Down Counter interrupts.
Clear interrupt requests.
Enable interrupt requests.
Setting registers
Setting
procedure*
Refer to “Chapter 20 Interrupt Control
(Page No.207)”.
See 7.17
Count control register (CCR0,CCR1)
Count status register (CSR0,CSR1)
See 7.19
*: For the setting procedure, refer to the section indicated by the number.
Table 6-5 Required Settings to Deactivate Up/Down Counter
Setting
Deactivate Up/Down Counter
(Controlled through the ZIN pin)
Deactivate Up/Down Counter.
Setting registers
Setting
procedure*
Count control register (CCR0,CCR1)
See 7.10
Count status register (CSR0,CSR1)
See 7.11
*: For the setting procedure, refer to the section indicated by the number.
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Chapter 32 Up/Down Counter
7.Q&A
7. Q&A
7.1 How do I select a bit length (8 or 16) of Up/Down Counter?
Use the 16 bit mode enable bit (CCR0.M16E).
Up/Down Counter's bit length
To set the bit length to 8
To set the bit length to 16 bit
16 bit mode enable bit (M16E)
Set the bit to “0”.
Set the bit to “1”.
7.2 What types of count modes are available and how are they set?
There are four types of count modes:
Timer, Up/down count, Phase difference count (Multiply by 2 or 4)
Use the count mode selection bits (CCR0.CMS[1:0]) and (CCR1.CMS[1:0]) to set a count mode.
Count mode
To set the count mode to timer
To set the count mode to up/down count
To set the count mode to phase difference count
(Multiply by 2)
To set the count mode to phase difference count mode
(Multiply by 4)
Count mode selection bit (CMS[1:0])
Set the bit to “00”.
Set the bit to “01”.
Set the bit to “10”.
Set the bit to “11”.
7.3 How do I select a count source for Up/Down Counter running in the timer mode?
Use the internal prescaler select bits (CCR0.CLKS) and (CCR1.CLKS).
Count source for timer mode
To obtain the FCLKP divided by 2
Internal prescaler select bit (CLKS)
To obtain the FCLKP divided by 8
Set the bit to “1”.
Set the bit to “0”.
7.4 How do I select the edge with which Up/Down Counter running in the Up/down count
mode detects an input signal (AIN or BIN)?
Use count clock edge select bits (CCR0.CES[1:0]) and (CCR1.CES[1:0]).
Edge to be detected by counter
To disable detection
To enable detection of a falling edge
To enable detection of a rising edge
To enable detection of both edges
Count clock edge select bit (CES[1:0])
Set the bit to “00”.
Set the bit to “01”.
Set the bit to “10”.
Set the bit to “11”.
7.5 How do I set a value to Up/Down Counter?
A value can be set to Up/Down Counter by writing the value to the reload/compare register (RCR) and then writing “1”
to the counter write bits (CCR0.CTUT) and (CCR1.CTUT).
7.6 When the Up/Down Counter's count-up value agrees with the compare value
(RCR[0:1]), how do I enable clearing of Up/Down Counter the next time when the
counter counts up?
Use the up/down counter clear enable bits (CCR0.UCRE) and (CCR1.UCRE).
When the count-up value agrees with the compare
value and then Up/Down Counter counts up:
To disable clearing of Up/Down Counter
To enable clearing of Up/Down Counter
432
Up/down counter clear enable bit (UCRE)
Set the bit to “0”.
Set the bit to “1”.
Chapter 32 Up/Down Counter
7.Q&A
7.7 How do I enable reloading of the reload value (RCR[1:0]) to Up/Down Counter when
Up/Down Counter is underflowed?
Use the reload enable bits (CCR0.RLDE) and (CCR1.RLDE).
When the count-up value agrees with the compare
value:
To disable reloading of the reload value (RCR) to Up/
Down Counter
To enable reloading of the reload value (RCR) to Up/Down
Counter
Reload enable bit (RLDE)
Set the bit to “0”.
Set the bit to “1”.
7.8 How do I clear Up/Down Counter?
Up/Down Counter can be cleared in any of the following ways:
• Writing “0” to the up/down counter clear bits (CCR0.UDCC) and (CCR1.UDCC).
• Applying an edge to the ZIN pin (For details, refer to 7.9.)
• When the compare value agrees with the Up/Down Counter's count-up value.
• When Up/Down Counter tries to count up after reaching the maximum count.
• Reset input (INIT pin input, watchdog reset, software reset)
7.9 How do I clear Up/Down Counter using the ZIN pin?
Use counter clear gate bits (CCR0.CGSC) and (CCR1.CGSC) and counter clear gate edge select bits (CCR0.CGE[1:0])
and (CCR1.CGE[1:0]). (These bits are enabled in the up/down count mode.)
ZIN pin input
Counter clear gate bit
(CGSC)
To disable edge detection (clear)
To clear Up/Down Counter on the falling edge
To clear Up/Down Counter on the rising edge
Set the bit to “0”.
Set the bit to “0”.
Set the bit to “0”.
Counter clear gate
edge select bit
(CGE[1:0])
Set the bit to “00”.
Set the bit to “01”.
Set the bit to “10”.
GCE[1:0]=“11” indicates that setting is disabled.
7.10 How do I control Up/Down Counter's count operation using the ZIN pin?
Use counter clear gate bits (CCR0.CGSC) and (CCR1.CGSC) and counter clear gate edge select bits (CCR0.CGE[1:0])
and (CCR1.CGE[1:0]). (These settings are enabled for all the count modes.)
ZIN pin input
To disable level detection (counting)
To start counting up or down at the “L” level
To stop counting up or down at the “H” level
To stop counting up or down at the “L” level
To start counting up or down at the “H” level
Set the bit to “1”.
Counter clear gate
edge select bit
(CGE[1:0])
Set the bit to “00”.
Set the bit to “1”.
Set the bit to “01”.
Set the bit to “1”.
Set the bit to “10”.
Counter clear gate bit
(CGSC)
GCE[1:0]= “11” indicates that setting is disabled.
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Chapter 32 Up/Down Counter
7.Q&A
7.11 How do I enable/disable Up/Down Counter's count operation?
Use the count activate bits (CSR0.CSTR) and (CSR1.CSTR).
When the count-up value agrees with the compare value:
To disable Up/Down Counter's count operation
To enable Up/Down Counter's count operation
(To activate count operation)
Count activate bits (CSR0.CSTR) and
(CSR1.CSTR)
Set the bit to “0”.
Set the bit to “1”.
• How do I start counting?
Timer mode
Up/down count mode
→ Counting starts using the internal clock (See 7.3.)
→ Counting starts when the edge of an AIN or BIN pin input signal is detected. (See
7.4.)
Phase difference count mode → Counting starts when a phase difference between AIN and BIN pins is detected.
Note that the count operation enable level must be detected, before the ZIN pin's gate function can be selected.
7.12 How do I know the previous count direction (the current rotation direction)?
Use the up/down flags (CSR0.UDF[1:0]) and (CSR1.UDF[1:0]).
Up/down flag (UDF[1:0])
“00” indicates that no counting is performed after resetting.
“01” indicates that counting down is performed.
“10” indicates that counting up is performed.
“11” indicates that both counting up and down are performed, resulting in no change in the count value.
This flag has nothing to do with interrupts. So, use the count direction change flags (CCR0.CDCF) and (CCR1.CDCF)
for interrupt processing.
7.13 How do I know count direction changes?
Use the count direction change flags (CCR0.CDCF) and (CCR1.CDCF).
Count direction change flag (CDCF)
“0” indicates that no direction change has been made after clearing the flag.
“1” indicates that a direction change has been made once or more after clearing the flag.
7.14 How do I know that a compare-match has occurred?
Use the compare detection flags (CSR0.CMPF) and (CSR1.CMPF).
Compare detection flag (CMPF)
“0” indicates that the Up/Down Counter's count value does not agree with the compare value.
“1” indicates that the Up/Down Counter's count value agrees with the compare value.
Regardless of counter operations (counting up/down, or a value being set or reloaded), the compare detection flags are set
to “1” when the count value agrees with the compare value.
434
Chapter 32 Up/Down Counter
7.Q&A
7.15 How do I know that an overflow or underflow has occurred?
Use the overflow detection flags (CSR0.OVFF) and (CSR1.OVFF) and the underflow detection flags (CSR0.UDFF) and
(CSR1.UDFF).
(OVFF)=“1” indicates that Up/Down Counter has been overflowed.
(UDFF)=“1” indicates that Up/Down Counter has been underflowed.
7.16 How do I set the reload/compare value?
Set a value to the reload/compare registers [RCR0][RCR1]. (This value is used as a compare or reload value.)
7.17 What are interrupt-related registers?
Configure the up/down counter interrupt vectors and up/down counter interrupt level settings.
The following table shows the relationship among the up/down counter number, interrupt levels and vectors:
For details on interrupt levels and interrupt vectors, refer to “Chapter 20 Interrupt Control (Page No.207)”.
Interrupt vector
(Default)
Interrupt level set bit (ICR[4:0])
Up/Down Counter (16 bit)
Up/Down Counter 0 (8 bit)
#50
Address: 0FFF34h
Interrupt level register (ICR34) Address:
00462h
Up/Down Counter 1 (8 bit)
#51
Address: 0FFF30h
Interrupt level register (ICR35) Address:
00463h
The following interrupt request flags are not automatically cleared:
• Count direction change: (CCR0.CDCF) and (CCR1.CDCF)
• Compare detection: (CSR0.CMPF) and (CSR1.CMPF)
• Overflow: (CSR0.OVFF) and (CSR1.OVFF)
• Underflow: (CSR0.UDFF) and (CSR1.UDFF)
So, the software must write “0” to the interrupt request flag before control is returned from interrupt processing.
7.18 What interrupts are available and how are they selected?
There are three interrupt causes:
• Count direction change
• compare-match
• overflow/underflow
An interrupt request is made by ORing these three interrupt causes; each interrupt cause cannot be isolated.
Use the interrupt request permission bit to enable a desired interrupt.
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Chapter 32 Up/Down Counter
7.Q&A
7.19 How do I enable (select), disable or clear interrupts?
Interrupt request enable and interrupt request flags
To enable (select) interrupts, use the following interrupt request permission bits:
• Count direction change interrupt request permission bits : (CCR0.CFIE) and (CCR1.CFIE)
• Compare interrupt request permission bits
: (CSR0.CITE) and (CSR1.CITE)
• Overflow/underflow interrupt request permission bits
:(CSR0.UDIE) and (CSR1.UDIE)
To disable interrupt requests
To enable interrupt requests
Interrupt request permission bits (CFIE, CITE and UDIE)
Set the bit to “0”.
Set the bit to “1”.
To clear interrupt requests, use the following interrupt request bits:
• For count direction changes
: (CCR0.CDCF) and (CCR1.CDCF)
• For compare detection
: (CSR0.CMPF) and (CSR1.CMPF)
• For overflow
: (CSR0.OVFF) and (CSR1.OVFF)
• For underflow
: (CSR0.UDFF) and (CSR1.UDFF)
To clear interrupt requests
436
Interrupt request bits (CDCF, CMPF, OVFF and UDFF)
Write “0”.
Chapter 32 Up/Down Counter
8.Sample Programs
8. Sample Programs
Setting procedure Example 1
Sample Program 1
16 bit mode
Timer mode (Countdown)
Count clock=Divided by 8
Generate an interval timer interrupt by reloading a count value.
Interrupt cause = underflow
void UD0_sample_1 (void)
{
UD0_initial ();
UD0_start ();
}
1. Initial Settings
• Controlling Up/Down Counter ch0
Control register setting
Enable 16 bit mode>>
Change count direction>>
Enable count direction change interrupts>>
Select internal prescaler>>
Select count mode>>
Select the count clock edge>>
Counter write>>
UDCR clear enable>>
Enable reload function>>
Clear UDCR>>
Counter clear/gate selection>>
Counter clear/gate edge selection>>
• Setting the reload value/compare value
Reload value setting
CCR0
.M16E
.CDCF
.CFIE
.CLKS
.CMS1-0
.CES1-0
void UD0_initial (void)
{
IO_CCR0.hword = 0x9018;
.CTUT
.UCRE
.RLDE
.UDCC
.CGSC
.CGE1-0
/* Setting=1001_0000_0001_1000 */
/* bit15 = 1
M16E 16 bit x 1 ch operation mode */
/* bit14 = 0
CDCF Count direction change flag */
/* bit13 = 0
CFIE Disable direction change interrupt output. */
/* bit12 = 1
CLKS 8 machine cycles */
/* bit11-10 = 00
CMS1,0 Timer mode */
/* bit9-8 = 00
CES1,0 Disable edge detection. */
/* bit7 = 0
Undefined bit */
/* bit6 = 0
CTUT Disable counter write. */
/* bit5 = 0
UCRE Disable counter clear. */
/* bit4 = 1
RLDE Enable reload function.*/
/* bit3 = 1
UDCC Disable UDCR clear. */
/* bit2 = 0
CGSC ZIN counter clear function */
/* bit1-0 = 00
CGE1,0 Disable ZIN edge detection.
, Disable level detection. */
/* 16 bit mode Set reload value (any value). */
RCR0
RCR1
IO_RCR0 = 0x f f;
IO_RCR1 = 0xvf f;
• Interrupt settings
Interrupt level setting for UD counter 0
ICR34
IO_ICR[34].byte = 0x10;
/* Set interrupt level (any value). */
I flag setting
(CCR)
__EI ();
/* Enable interrupts */
}
2. Activation
• Activating Up/Down Counter ch0
Underflow interrupt control
Data transfer from RCR to UDCR
Activating the count operation
register name . bit name
CSR0 .UDIE
CCR0 .CTUT
CSR0 .CSTR
3. Interrupt
• Interrupt processing
Checking of underflow detection flags
Clearing of the interrupt request flags
(User processing)
CSR0 .UDFF
4. Interrupt Vector
Set the vector table.
Caution: Clock setup and __set_il (numeric parameter) must have been performed
beforehand. For details, refer to the “Clock” and “Interruption” sections.
void UD0_start (void)
{
IO_CSR0.bit.UDIE = 1;
IO_CCR0.bit.CTUT = 1;
IO_CSR0.bit.CSTR = 1;
}
/* bit5 = 1
/* bit6 = 1
/* bit7 = 1
__interrupt void UD0_int (void)
{
if (IO_CSR0.bit.UDFF)
{
IO_CSR0.bit.UDFF = 0;
/* bit2 = 0
.....
}
}
The interrupt routine must be specified in the vector table.
#pragma intvect UD0_int 50
UDIE Enable underflow interrupts. */
CTUT Write to counter. */
CSTR Start count. */
UDFF Clear the underflow detection flags. */
* For register formats, refer to “FR60Lite Family MB91230 Series Sample I/O Register File User's Guide”.
437
Chapter 32 Up/Down Counter
8.Sample Programs
Setting procedure Example 2
Sample Program 2
8 bit mode (ch1)
Use the up/down count mode; Count up on the rising edge of a signal of phase A;
Count down on the rising edge of a signal of phase B.
Interrupt cause = compare and underflow
void UD1_sample_2 (void)
{
UD1_initial ();
UD1_start ();
}
1. Initial Settings
• Port
AIN1 and BIN1 port input setting
void UD1_initial (void)
{
IO_PORT1.IO_DDR3.byte = /* DDR3.AIN1 (P35),BIN (P36) Input */
0x00;
• Controlling Up/Down Counter ch1.
Control register setting
Change count direction>>
Enable count direction change interrupts>>
Select internal prescaler>>
Select count mode>>
Select the count clock edge>>
Counter write>>
UDCR clear enable>>
Enable reload function>>
Clear UDCR>>
Counter clear/gate selection>>
Counter clear/gate edge selection>>
• Setting the reload value/compare value
Reload value setting
• Interrupt settings
Interrupt level setting for UD counter 1
I flag setting
register name .bit name
DDR3 .P35,.P36
CCR1
IO_CCR1.hword = 0x0638;
RCR1
IO_RCR1 = 0x03;
/* Setting=0000_0110_0011_1000 */
/* bit15 = 0
Undefined bit */
/* bit14 = 0
CDCF Count direction change flag */
/* bit13 = 0
CFIE Disable direction change interrupt output. */
/* bit12 = 0
CLKS 2 machine cycles */
/* bit11-10 = 01
CMS1,0 Up/down count mode */
/* bit9-8 = 10
CES1,0 Detect the rising edge. */
/* bit7 = 0
Undefined bit */
/* bit6 = 0
CTUT Disable counter write. */
/* bit5 = 1
UCRE Enable counter clear. */
/* bit4 = 1
RLDE Enable reload function. */
/* bit3 = 1
UDCC Disable UDCR clear. */
/* bit2 = 0
CGSC ZIN counter clear function */
/* bit1-0 = 00
CGE1,0 Disable ZIN edge detection.
, Disable level detection. */
/* 8 bit mode Set reload value (any value). */
ICR35
(CCR)
IO_ICR[35].byte = 0x10;
__EI ();
/* Set interrupt level (any value). */
/* Enable interrupts */
.CDCF
.CFIE
.CLKS
.CMS1-0
.CES1-0
.CTUT
.UCRE
.RLDE
.UDCC
.CGSC
.CGE1-0
}
2. Activation
• Activating Up/Down Counter ch1
Underflow interrupt control
Compare interrupt control
Data transfer from RCR to UDCR
Activating the count operation
register name .bit name
CSR1 .UDIE
CSR1 .CITE
CCR1 .CTUT
CSR1 .CSTR
3. Interrupt
• Interrupt processing
Checking of underflow detection flags
Clearing of the interrupt request flag
(User processing)
CSR1 .UDFF
Checking of the compare detection flag
Clearing of the interrupt request flags
(User processing)
CSR1 .CMPF
4. Interrupt Vector
Set the vector table.
Caution: Clock setup and __set_il (numeric parameter) must have been performed
beforehand. For details, refer to the “Clock” and “Interruption” sections .
438
void UD1_start (void)
{
IO_CSR1.bit.UDIE = 1;
IO_CSR1.bit.CITE = 1;
IO_CCR1.bit.CTUT = 1;
IO_CSR1.bit.CSTR = 1;
}
/* bit5 = 1
/* bit6 = 1
/* bit6 = 1
/* bit7 = 1
__interrupt void UD1_int (void)
{
if (IO_CSR1.bit.UDFF & IO_CSR1.bit.UDIE)
{
IO_CSR1.bit.UDFF = 0;
/* bit2 = 0
.....
}
else if (IO_CSR1.bit.CMPF & IO_CSR1.bit.CITE)
{
IO_CSR1.bit.CMPF = 0;
/* bit4 = 0
.....
}
}
The interrupt routine must be specified in the vector table.
#pragma intvect UD1_int 51
UDIE Enable underflow interrupts. */
CITE Enable compare interrupts. */
CTUT Write to counter. */
CSTR Start count.*/
UDFF Clear the underflow detection flags. */
CMPF Clear the compare detection flag. */
Note: For register formats, refer to “FR60Lite Family MB91230 Series Sample I/O Register File User's Guide”.
Chapter 32 Up/Down Counter
8.Sample Programs
Setting procedure Example 3
Sample Program 3
8 bit mode (ch0)
Phase difference count mode (Multiply by 2)
Clear the count on the rising edge of a signal of phase Z.
void UD0_sample_3 (void)
{
UD0_initial ();
UD0_start ();
}
1. Initial Settings
• Port
AIN0,BIN0 and ZIN0 port input setting
• Controlling Up/Down Counter ch0
Control register setting
void UD0_initial (void)
{
IO_PORT1.IO_DDR3.byte = 0x00; /* DDR3.AIN0 (P32),BIN0 (P33),ZIN0 (P34) input */
register name .bit name
DDR3 .P32,.P33,.P34
CCR0
Change count direction>>
Enable count direction change
interrupts>>
.CDCF
.CFIE
Select internal prescaler>>
Select count mode>>
Select the count clock edge>>
.CLKS
.CMS1-0
.CES1-0
Counter write>>
UDCR clear enable>>
Enable reload function>>
Clear UDCR>>
Counter clear/gate selection>>
Counter clear/gate edge selection>>
• Setting the reload value/compare value
Reload value setting
• Interrupt settings
Interrupt level setting for UD counter 0
I flag setting
IO_CCR0.hword = 0x082a;
/* Setting=0000_1000_0010_1010 */
/* bit15 = 0
Undefined bit */
/* bit14 = 0
CDCF Count direction change flag */
/* bit13 = 0
CFIE Disable direction change interrupt output. */
/* bit12 = 0
/* bit11-10 = 10
/* bit9-8 = 00
/* bit7 = 0
/* bit6 = 0
/* bit5 = 1
/* bit4 = 0
/* bit3 = 1
/* bit2 = 0
/* bit1-0 = 10
RCR0
IO_RCR0 = 0xÇÜÇÜ;
CLKS 2 machine cycles */
CMS1,0 Phase difference count mode (Multiply by 2) */
CES1,0 Disable edge detection. */
Undefined bit */
CTUT Disable counter write. */
UCRE Enable counter clear. */
RLDE Enable reload function. */
UDCC Disable UDCR clear. */
CGSC ZIN counter clear function */
CGE1,0 When counter clear is enabled,
, rising edge */
/* 8 bit mode Set reload value (any value). */
ICR34
(CCR)
IO_ICR[34].byte = 0x10;
__EI ();
/* Set interrupt level (any value). */
/* Enable interrupts */
.CTUT
.UCRE
.RLDE
.UDCC
.CGSC
.CGE1-0
}
2. Activation
• Activating Up/Down Counter ch0
Overflow/underflow interrupt control.
Compare interrupt control
Data transfer from RCR to UDCR
Activating the count operation
register name .bit name
CSR0 .UDIE
void UD0_start (void)
{
IO_CSR0.bit.UDIE = 1;
CSR0 .CITE
CCR0 .CTUT
CSR0 .CSTR
IO_CSR0.bit.CITE = 1;
IO_CCR0.bit.CTUT = 1;
IO_CSR0.bit.CSTR = 1;
/* bit5 = 1
UDIE Enable overflow/underflow interrupts. */
/* bit6 = 1
/* bit6 = 1
/* bit7 = 1
CITE Enable compare interrupts. */
CTUT Write to counter. */
CSTR Start count.*/
}
3. Interrupt
• Interrupt processing
Checking of underflow detection flags
Clearing of the interrupt request flags
(User processing)
CSR0 .UDFF
Checking of the compare detection flag
Clearing of the interrupt request flags
(User processing)
CSR0 .CMPF
Checking of the overflow detection flag
Clearing of the interrupt request flags
(User processing)
CSR0 .OVFF
4. Interrupt Vector
Set the vector table.
Caution: Clock setup and __set_il (numeric parameter) must have been
performed beforehand. For details, refer to the “Clock” and “Interruption”
sections .
__interrupt void UD0_int (void)
{
if (IO_CSR0.bit.UDFF & IO_CSR0.bit.UDIE)
{
IO_CSR0.bit.UDFF = 0;
/* bit2 = 0
.....
}
else if (IO_CSR0.bit.CMPF & IO_CSR0.bit.CITE)
{
IO_CSR0.bit.CMPF = 0;
/* bit4 = 0
.....
}
else if (IO_CSR0.bit.OVFF & IO_CSR0.bit.UDIE)
{
IO_CSR0.bit.OVFF = 0;
/* bit3 = 0
.....
}
}
The interrupt routine must be specified in the vector table.
#pragma intvect UD0_int 50
UDFF Clear the underflow detection flags. */
CMPF Clear the compare detection flag. */
OVFF Clear the overflow detection flag. */
* For register formats, refer to “FR60Lite Family MB91230 Series Sample I/O Register File User's Guide”.
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Chapter 32 Up/Down Counter
9.Caution
9. Caution
• The count direction is set to “countdown” immediately after resetting the counter. So, when the counter counts up
immediately after resetting, the count direction change bits (CCR0.CDCF) and (CCR1.CDCF) are set to “1” to indicate
a direction change has been made.
• When the up/down counter register UDCR has reached the maximum count, the overflow flag is set to 1 and counting
continues. This time UDCR is cleared.
• The minimum pulse width for AIN, BIN and ZIN signals is 2xT (T=1/CLKP: Period of a peripheral clock)
• If you determine whether a change has been made to the count direction change interrupt and count direction flags, you
must take it into consideration that when several direction changes have been made continuously in a short period of
time, the count direction flag may be returned to the original value, which looks as if no change has been made.
• The compare detection flags (CSR0.CMPF) and (CSR1.CMPF) are set to “1” when
• Up/Down Counter's count value agrees with the compare value during both counting up and down. These flags are also
set to 1 when:
• The reload value is reloaded to Up/Down Counter; or
• The Up/Down Counter's count value agrees with the compare value when Up/Down Counter is activated.
• The Up/Down Counter's count value is cleared by a clear request which is generated:
• On the edge of a signal input from the ZIN pin;
• By writing “0” to the up/down counter clear bits (CCR0.UDCC) and (CCR1.UDCC); or
• When the compare value agrees with the count value.
In addition,
• On reset input (INITX, RST and watchdog reset); or
• When the counter counts up from the maximum account,
the count value is also set to “0000H”.
• When Up/Down Counter clear and reload requests are made at the same time, the former takes precedence over the
latter.
• When Up/Down Counter is counting up, writing to the counter is disabled.
{Writing “1” to the counter write bits (CCR0.CTUT) and (CCR1.CTUT) after writing to the RCR register is disabled.}
Should the software perform a reload operation during counting, the reload takes precedence and the event that should
have taken place no longer occurs.
• The software cannot clear the up/down flags (CSR0.UDF[1:0]) and (CSR1.UDF[1:0]) to “0”. Only reset (initialization)
can clear the flag to “0”.
440
Chapter 33 LCD Controller
1.Overview
Chapter 33 LCD Controller
1. Overview
LCD allows display of up to 128 cells and selection of a duty cycle from 1/2, 1/3 and 1/4.
LCD has many applications.
Internal Divided Resistors
or
External Divided Resistors
Driver
Bit3
7
2
6
1
5
0
4
Segment
VRAM1
VRAM2
Common
Driver
Timing Circuit
Sub-clock
Prescaler
Peripheral
clock
AC Circuit
VRAM15
2. Features
•
•
•
•
•
•
•
•
•
•
•
Quantity: 1 (4 common × 32 segment)
Display: Up to 218 cells (for 1/4 duty cycle)
Duty cycle: Selectable from options: 1/2, 1/3 and 1/4.
Bias: Fixed at 1/3
Frame period: Selectable from four options. (For clock, peripheral clock or subclock is selectable.)
Driver: Built-in (for internal divided resistors), or external divided resistors can be connected to the V0 - V3 pins.
Data memory: Built-in 16-byte data memory for display
Stop mode: Enable LCD display in the sub-stop mode.
Blank display: Selectable.
Pin: The SEG0-31 of COM0-4 pin usage can be switched between general and specialized purposes.
Other: External divided resistors can be also used to shut off the current when LCD is deactivated.
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Chapter 33 LCD Controller
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
LCD Controller
FP1,0
LCR0: bit1,0
0
0
0
1
1
0
1
1
LCR0: bit7
1
Subclock
FCL-SUB /(2 3
FCL-SUB /(2 4
FCL-SUB /(2 5
FCL-SUB /(2 6
LCDCMR
MS1,0 LCR0: bit3,2
0 0 Deactivate
0 1 1/2 duty cycle
1 0 1/3 duty cycle
1 1 1/4 duty cycle
N)
N)
N)
N)
From port data
register
COM0
0
Timing
Control Circuit
Prescaler
Sub
clock
COM0 PFR7: bit0
:
:
COM3 PFR7: bit3
0 General-purpose ports
1 COM output
LCDCMR
---- 0000 Initial value
00001111 Setting
Common Driver
Peripheral
clock
CSS
0
Main clock
FCLKP/(2 13 N)
FCLKP/(2 14 N)
FCLKP/(2 15 N)
FCLKP/(2 16 N)
1
V0
Internal
Divided
Resistors
V1
V2
VRAM 0
VRAM 1
VRAM 2
VRAM 3
VRAM 4
VRAM 5
VRAM 6
VRAM 7
COM3
LCR0: bit5
Disconnect internal divided resistors.
Connect internal divided resistors.
SEG0
VRAM 8
VRAM 9
VRAM 10
VRAM 11
VRAM 12
VRAM 13
VRAM 14
VRAM 15
Segment Driver
VSEL
COM2
AC Circuit
V3
0
1
COM1
SEG1
SEG2
SEG30
1
LCEN
LCR0: bit6
0 Disable display in watch mode.
1 Enable display in watch mode.
SEG31
Control Section
BK
0
1
LCR0: bit4
Display
Blank
From
general-purpose
port register
LCR1
00000000 Initial value
11111111 Setting
0
SEG0 PFR8: bit0 SEG16 PFRA: bit0 SEG28 PFR6: bit4
:
:
:
:
:
:
SEG7 PFR8: bit7 SEG23 PFRA: bit7 SEG31 PFR6: bit7
SEG8 PFR9: bit0 SEG24 PFRB: bit0 0 General-purpose port
:
:
:
:
SEG output
SEG15 PFR9: bit7 SEG27 PFRB: bit3 1
Note: For details on ports, refer to “Chapter 19 I/O Port (Page No.193)” and “Chapter 3 Basic Information (Page
No.25)”.
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Chapter 33 LCD Controller
3.Configuration
Figure 3-2 Register List
443
Chapter 33 LCD Controller
4.Registers
4. Registers
4.1 LCR0: LCDC Control Register 0
This register is used to select a frame period and its clock and the display mode, to enable/disable LCD display and the operation
in the watch mode, and to control the drive power source.
• LCR0: Address 09AH (Access: Byte)
7
CSS
0
R/W
6
LCEN
0
R/W
5
VSEL
0
R/W
4
BK
1
R/W
3
MS1
0
R/W
2
MS0
0
R/W
1
FP1
0
R/W
0
FP0
0
R/W
bit
Initial value
Attribute
(For attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)” chapter.)
• bit7: Select the frame period generation clock
CSS
0
1
Operation
Peripheral clock (CLKP)
Subclock
When the peripheral clock is selected, LCD does not operate if the main clock stops (that is, LCD is in the subclock
mode in which the main clock stops, or in the sub-stop mode).
• bit6: Enable operation in sub-stop
LCEN
0
1
Operation
Disable LCD display in the sub-stop mode.
Enable LCD display in the sub-stop mode.
To enable LCD display, the frame period generation clock select bit (CCS) must be also set to “1”.
• bit5: Control LCD drive power supply
VSEL
0
1
Operation
Disconnect internal divided resistors.
Connect internal divided resistors.
To connect external divided resistors, the LCD drive power supply control bit (VSEL) must be set to “1”.
• bit4: Select blanking
BK
0
1
Operation
Enable LCD display.
Disable (blank) LCD display.
• bit3-2: Select a display mode
MS1
0
0
1
1
MS0
0
1
0
1
Display mode
Deactivate LCD.
1/2 duty cycle output mode (Time division number: N=2, COM0-COM1)
1/3 duty cycle output mode (Time division number: N=3, COM0-COM2)
1/4 duty cycle output mode (Time division number: N=4, COM0-COM3)
If the display mode select bit (MS[1:0]) is set to “00”, LCD Controller ceases to operate.
A “L” level is output through common/segment pins.
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Chapter 33 LCD Controller
4.Registers
• bit1-0: Frame period
Frame period
When peripheral clock is selected:
When subclock is selected:
FP1
FP0
0
0
FCLKP/(213 × N)
FCL-SUB/(23 × N)
0
1
FCLKP/(214 × N)
FCL-SUB/(24 × N)
1
0
FCLKP/(215 × N)
FCL-SUB/(25 × N)
1
1
FCLKP/(216 × N)
FCL-SUB/(26 × N)
FCLKP
FCL-SUB
N
Peripheral clock (CLKP) frequency
Subclock frequency
Time division number (Selected with the display mode select bits, MS1 and MS0.)
Select an appropriate value in accordance with the frame frequency of your LCD panel.
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Chapter 33 LCD Controller
4.Registers
4.2 VRAM: Data Memory for Display
Memory area (VRAM) for setting display data
• VRAM0 (SEG0, SEG1): Address 09CH (Access: Byte)
• VRAM1 (SEG2, SEG3): Address 09DH (Access: Byte)
• VRAM2 (SEG4, SEG5): Address 09EH (Access: Byte)
• VRAM3 (SEG6, SEG7): Address 09FH (Access: Byte)
• VRAM4 (SEG8, SEG9): Address 0A0H (Access: Byte)
• VRAM5 (SEG10, SEG11): Address 0A1H (Access: Byte)
• VRAM6 (SEG12, SEG13): Address 0A2H (Access: Byte)
• VRAM7 (SEG14, SEG15): Address 0A3H (Access: Byte)
• VRAM8 (SEG16, SEG17): Address 0A4H (Access: Byte)
• VRAM9 (SEG18, SEG19): Address 0A5H (Access: Byte)
• VRAM10 (SEG20, SEG21): Address 0A6H (Access: Byte)
• VRAM11 (SEG22, SEG23): Address 0A7H (Access: Byte)
• VRAM12 (SEG24, SEG25): Address 0A8H (Access: Byte)
• VRAM13 (SEG26, SEG27): Address 0A9H (Access: Byte)
• VRAM14 (SEG28, SEG29): Address 0AAH (Access: Byte)
• VRAM15 (SEG30, SEG31): Address 0ABH (Access: Byte)
7
D07
X
R/W
6
D06
X
R/W
5
D05
X
R/W
4
D04
X
R/W
3
D03
X
R/W
2
D02
X
R/W
1
D01
X
R/W
0
D00
X
R/W
(For attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
Regardless of the operation of LCD Controller/V driver, RAM can be read and written any time.
446
bit
Initial value
Attribute
Chapter 33 LCD Controller
4.Registers
• Correspondence between VRAM and Common/Segment Pins
RAM area and common pins used in
1/2 duty cycle output mode
RAM area and common pins used in
1/3 duty cycle output mode
RAM area and common pins used in
1/4 duty cycle output mode
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Chapter 33 LCD Controller
4.Registers
4.3 LCR1: LCDC Control Register 1
• LCR1: Address 09BH (Access: Byte, Half-word, Word)
7
Reserved
0
R/W
6
Reserved
0
R/W
5
Reserved
0
R/W
4
Reserved
0
R/W
3
Reserved
0
R/W
2
Reserved
0
R/W
1
Reserved
0
R/W
0
Reserved
0
R/W
bit
Initial value
Attribute
(For attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit7-0: Reserved.
When LCD is used, always set this register to “11111111B”.
4.4 LCDCMR: Common Pin Switching Register
• LCDCMR: Address 098H (Access: Byte, Half-word, Word)
7
–
–
RX/WX
6
–
–
RX/WX
5
–
–
RX/WX
4
–
–
RX/WX
3
Reserved
0
R/W
2
Reserved
0
R/W
1
Reserved
0
R/W
(For attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit7-4: Undefined (Read: Indeterminate, Write: “0” is always written.)
• bit3-0: Reserved.
Always set to “1111B” when LCD is used.
448
0
Reserved
0
R/W
bit
Initial value
Attribute
Chapter 33 LCD Controller
5.Operation
5. Operation
This section describes operation.
5.1 LCD Controller/Driver (LCDC) Operation
(1) Set values to the display data memory (VRAM) in advance.
(2) Make necessary settings to each register.
(3) When the frame period generation clock oscillates, LCD drive waveform is output through common/segment output
pins (COM0 - COM3, SEG0 - SEG31).
(4) More detailedly,
VRAM contents are automatically read in synchronization with common signals to be output through segment output
pins.
(If the bit is set to “1”, the selected waveform is output through the segment output pins.
If the bit is set to “0”, non-selected waveform is output through the segment output pins.)
If the display mode is set to 1/2 duty cycle, non-selected waveform is output through the COM2 and COM3 pins. For
the 1/3 duty cycle, the COM3 pin is used to output non-selected waveform.
(5) This output waveform is a 2-frame AC waveform in accordance with the duty cycle setting, and drives LCD.
(6) When MS[1:0] = “00” is used to deactivate LCD, a “L” level is output through both common and segment pins.
(7) If LCD operation is enabled in the sub-stop mode (LCEN=“1”), LCD display is displayed.
Note that frame period generation clock signals must be supplied at this time.
(8) LCD display can be blanked by selecting “blank” (BK=“1”) in blanking selection.
Note that non-selected waveform continues to be output.
(9) When LCD deactivation (MS[1:0]=“00”) is selected with the display mode, LCD ceases to operate.
5.2 1/2 Duty Cycle Output Waveform
Only COM0 and COM1 outputs are used for LCD display. Neither COM2 nor COM3 output is used.
• Example of 1/3 Bias Output Waveform
LCD cells with the maximum voltage difference between common and segment outputs are lit.
Table 5-1 Example of Data Memory Contents for display
Segment
SEG 2n output
SEG2n+1 output
COM3 output
-
Contents of data memory for display
COM2 output
COM1 output
0
0
COM0 output
0
1
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Chapter 33 LCD Controller
5.Operation
COM0 output
V3
V2
V1
V0
COM1 output
V3
V2
V1
V0
COM2 output
V3
V2
V1
V0
COM3 output
V3
V2
V1
V0
SEG 2n output
V3
V2
V1
V0
SEG 2n+1 output
V3
V2
V1
V0
LCD cell corresponding to SEG 2n, COM0 output
ON
OFF
LCD cell corresponding to SEG 2n, COM1 output
ON
OFF
LCD cell corresponding to SEG 2n+1, COM0 output
ON
OFF
LCD cell corresponding to SEG 2n+1, COM1 output
ON
OFF
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Chapter 33 LCD Controller
5.Operation
5.3 1/3 Duty Cycle Output Waveform
In the 1/3 duty cycle output mode, COM0, COM1 and COM2 outputs are used for LCD display. COM3 output is not
used.
• Example of 1/3 Bias Output Waveform
LCD cells with the maximum voltage difference between common and segment outputs are lit.
Table 5-2 Example of Data Memory Contents for Display
Segment
SEG 2n output
SEG2n+1 output
COM3 output
-
Contents of data memory for display
COM2 output
COM1 output
1
0
1
0
COM0 output
0
1
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Chapter 33 LCD Controller
5.Operation
COM0 output
V3
V2
V1
V0
COM1 output
V3
V2
V1
V0
COM2 output
V3
V2
V1
V0
COM3 output
V3
V2
V1
V0
SEG 2n output
V3
V2
V1
V0
SEG 2n+1 output
V3
V2
V1
V0
LCD cell corresponding to SEG 2n, COM0 output
ON
OFF
LCD cell corresponding to SEG 2n, COM1 output
ON
OFF
LCD cell corresponding to SEG 2n, COM2 output
ON
OFF
LCD cell corresponding to SEG 2n+1, COM0 output
ON
OFF
LCD cell corresponding to SEG 2n+1, COM1 output
ON
OFF
LCD cell corresponding to SEG 2n+1, COM2 output
ON
OFF
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Chapter 33 LCD Controller
5.Operation
5.4 1/4 Duty Cycle Output Waveform
In the 1/4 duty cycle output mode, COM0, COM1, COM2, and COM3 outputs are all used for LCD display.
• Example of 1/3 Bias Output Waveform
LCD cells with the maximum voltage difference between common and segment output are lit.
Table 5-3 Example of Data Memory Contents for Display
Segment
COM3 output
SEG 2n
output
SEG2n+1
output
Contents of data memory for display
COM2 output
COM1 output
COM0 output
0
1
0
0
0
1
0
1
COM 0 out put
V3
V2
V1
V0
COM 1 out put
V3
V2
V1
V0
COM 2 out put
V3
V2
V1
V0
COM 3 out put
V3
V2
V1
V0
S E G 2n out put
V3
V2
V1
V0
S E G 2n+ 1 out put
V3
V2
V1
V0
LCD c el l c orres pondi ng t o SEG 2 n , C OM0 o u tp u t
ON
OFF
LCD c el l c orres pondi ng t o SEG 2 n , C OM1 o u tp u t
ON
OFF
LCD c el l c orres pondi ng t o SEG 2 n , C OM2 o u tp u t
ON
OFF
LCD c el l c orres pondi ng t o SEG 2 n , C OM3 o u tp u t
ON
OFF
LCD c el l c orres pondi ng t o SEG 2 n +1 , C OM0 o u tp u t
ON
OFF
LCD c el l c orres pondi ng t o SEG 2 n +1 , C OM1 o u tp u t
ON
OFF
LCD c el l c orres pondi ng t o SEG 2 n +1 , C OM2 o u tp u t
ON
OFF
LCD c el l c orres pondi ng t o SEG 2 n +1 , C OM3 o u tp u t
ON
OFF
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Chapter 33 LCD Controller
6.Setting
6. Setting
Table 6-1 Required Setting to Use LCD
Setting
Setting register *
Presetting
Common pin switching register (LCDCMR)
LCD control register 1 (LCR1)
Set divided resistors.
LCD control register 0 (LCR0)
Set ports
Set display data.
Select the frame period generation clock.
Set a frame period.
Select a duty cycle. (Activation)
Enable LCD display.
Port function register (PFR)
Display data memory (VRAM)
Setting
procedure
–
See
7.8 and 7.9
See 7.1
See 7.2
See 7.3
LCD control register 0 (LCR0)
See 7.4
See 7.6
* :For the setting procedure, refer to the section indicated by the number.
Table 6-2 Required Setting to Disable LCD display
Setting
Disable (blank) LCD display.
Setting register *
LCD control register 0 (LCR0)
Setting
procedure
See 7.6
* :For the setting procedure, refer to the section indicated by the number.
Table 6-3 Required Setting to Deactivate LCD
Setting
Deactivate LCD.
Setting register *
LCD control register 0 (LCR0)
Setting
procedure
See 7.5
*:For the setting procedure, refer to the section indicated by the number.
Table 6-4 Required Setting to Enable LCD Display in Sub-Stop Mode
Setting
Enable LCD display in the sub-stop mode.
Select the frame period generation clock.
Switch to subclock operation.
Change to the stop mode.
Setting register *
LCD control register 0 (LCR0)
See “Chapter 11 Clock Control (Page No.103)”.
See “Chapter 10 Standby (Page No.91)”.
* :For the setting procedure, refer to the section indicated by the number.
454
Setting
procedure
See 7.7
See 7.3
–
–
Chapter 33 LCD Controller
7.Q&A
7. Q&A
7.1 How do I specify pins as COM or SEG output pins?
Use COM and SEG output settings.
Software can switch ports to COM or SEG output ports.
To do so, write “1” to the output designation bit (COM[3:0], SEG[31:0]).
Pin
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
Register
Port function register
PFR7
Port function register
PFR8
Port function register
PFR9
Port function register
PFRA
Port function register
PFRB
Port function register
PFR6
Output designation bit
(COM0)
(COM1)
(COM2)
(COM3)
(SEG0)
(SEG1)
(SEG2)
(SEG3)
(SEG4)
(SEG5)
(SEG6)
(SEG7)
(SEG8)
(SEG9)
(SEG10)
(SEG11)
(SEG12)
(SEG13)
(SEG14)
(SEG15)
(SEG16)
(SEG17)
(SEG18)
(SEG19)
(SEG20)
(SEG21)
(SEG22)
(SEG23)
(SEG24)
(SEG25)
(SEG26)
(SEG27)
(SEG28)
(SEG29)
(SEG30)
(SEG31)
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Chapter 33 LCD Controller
7.Q&A
7.2 How do I set VRM?
The following tables show the relationship between pins and the bit positions of VRAM(n). (n=0 to 15)
Table 7-1 1/2 duty cycle
Pin
SEG 2n
SEG 2n+1
COM1
bit 1
Bit 5
COM0
bit 0
Bit 4
Table 7-2 1/3 duty cycle
pin
SEG 2n
SEG 2n+1
COM2
bit 2
Bit 6
COM1
bit 1
Bit 5
COM0
bit 0
Bit 4
COM2
bit 2
Bit 6
COM1
bit 1
Bit 5
Table 7-3 1/4 duty cycle
pin
SEG 2n
SEG 2n+1
COM3
bit 3
bit 7
COM0
bit 0
Bit 4
(Non-selected waveform is output through the pins other than the above.)
Example: 1/4 duty cycle
When “1” is set to the bit6 of VRAMn, selected waveform is output through the SEG2n+1 of COM2.
If a bit is set to “0”, non-selected waveform is output through the corresponding pin.
7.3 How do I set a frame period?
Use the frame period generation clock select bit (LCR0.CSS) and the frame period bit (LCR0.FP[1:0]). The following
settings are available:
Frame period
Selected value
Frame period generation clock
Frame period bit
select bit (CSS)
(FP[1:0])
Peripheral clock (FCLKP)/(213 × N)
Set to “0”.
Set to “00”.
Peripheral clock (FCLKP)/(214 × N)
Set to “0”.
Set to “01”.
Peripheral clock (FCLKP)/(215 × N)
Set to “0”.
Set to “10”.
Peripheral clock (FCLKP)/(216 × N)
Set to “0”.
Set to “11”.
Subclock (FCL-SUB)/(23 × N)
Set to “1”.
Set to “00”.
Subclock (FCL-SUB)/(24 × N)
Set to “1”.
Set to “01”.
Subclock (FCL-SUB)/(25 × N)
Set to “1”.
Set to “10”.
Subclock (FCL-SUB)/(26 × N)
Set to “1”.
Set to “11”.
N (Time division number) = MS[1:0] value + “1”
Set an appropriate frame period that corresponds to the frame frequency of your CLD panel.
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Chapter 33 LCD Controller
7.Q&A
7.4 How do I set a duty cycle?
Use the display mode select bit (LCR0.MS[1:0]).
Controlled operation
To deactivate LCD (Pin output: “L”)
To set the 1/2 duty cycle output mode
To set the 1/3 duty cycle output mode
To set the 1/4 duty cycle output mode
Display mode select bit
(MS[1:0])
Set to “00”.
Set to “01”.
Set to “10”.
Set to “11”.
N (Time division number)
N/A
2
3
4
The display mode select bit also serves as an operation start/stop control bit.
7.5 How do I control starting and stopping of LCD?
Use the display mode select bit (LCR0. MS[1:0]) to control start and stop of operation.
See (4).
7.6 How do I enable or disable LCD display?
Use either of the following methods:
• Use the blanking select bit (LCR0. BK).
Controlled operation
To enable LCD display
To disable (blank) LCD display
(Non-selected waveform is output through segment pins.)
Blanking select bit (BK)
Set to “0”.
Set to “1”.
• The LCD display can be blanked by using the display mode select bit (LCR0. MS[1:0]) to select LCD deactivation.
Controlled operation
To deactivate LCD
(A “L” level is output through common and segment pins.)
Display mode select bit (MS[1:0])
Set to “00”.
7.7 How do I enable LCD display even in the sub-stop mode?
Use the sub-stop operation enable bit (LCR0. LCEN).
Controlled operation
To disable LCD display during sub-stop
To enable LCD display during sub-stop
To enable LCD display when the main clock stops and the
subclock operates
Frame period
generation clock
select bit (CSS)
–
Set to “1”.
Sub-stop operation enable bit
(LCEN)
Set to “1”.
Set to “0”.
Set to “1”.
–
7.8 How do I select internal or external divided resistors?
Use the LCD drive power supply control bit (LCR0. VSEL).
Controlled operation
To use external divided resistors
(Internal divided resistors disconnected)
To use internal divided resistors
(Internal divided resistors connected)
LCD drive power supply control bit (VSEL).
Set to “0”.
Set to “1”.
Since MB91V230 does not have internal divided resistors, be sure to select “0” (external divided resistors).
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Chapter 33 LCD Controller
7.Q&A
7.9 How do I select internal or external divided resistors?
• When using internal divided resistors:
V3
V3
V2
V1
V0
R
V2
R
V1
R
V0
N-ch
LCDC operation
enabled
• When using external divided resistors:
The LCD driving voltage can be generated by connecting external divided resistors to the LCD drive power supply
pins (V0 to V3).
V3
V3
V2
V1
V0
LCDC operation
enabled
R
V2
R
V1
R
V0
VR
RX
RX
RX
N-ch
To avoid the effect of internal divided resistors, the resistors must be disconnected by setting “0” to the LCD drive power
supply control bit (LCR0.VSEL).
7.10 How do I use external divided resistors to shut off the current when LCD is
deactivated?
The V0 pin is internally connected to Vss (GND) via a transistor. For this reason, the current generated on deactivating
LCD controller can be shut off by connecting external divided resistors to the V0 pin on the Vss side. To shut off the
current, use the display mode select bit (MS[1:0]= “00”).
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Chapter 33 LCD Controller
8.Sample Programs
8. Sample Programs
Setting Procedure 1
Program 1
Use the 1/2 duty cycle drive method to display “0 1 2 3” and a four-digit
numeric value.
Initial setting (LCDC)
<Initial setting>
1.
• Port
Register name
Output setting of COM and SEG ports PFR7
PFR8
PFR9
PFRA
PFRB
PFR6
2..
• VRAM setting
Register name
VRAM setting
VRAM00-VRAM07
void LCD_sample_1(void)
{
LCDC_initial();
}
void LCDC_initial(void)
{
IO_PORT1.IO_PFR7.byte = 0x03;
IO_PORT1.IO_PFR8.byte = 0xFF;
IO_PORT1.IO_PFR9.byte = 0xFF;
IO_PORT1.IO_PFRA.byte = 0x00;
IO_PORT1.IO_PFRB.byte = 0x00;
IO_PORT1.IO_PFR6.byte = 0x00;
/* COM0-1 = 1, COM2-3 = 0 */
/* SEG0-7 = 1 */
/* SEG8-15 = 1 */
/* SEG16-23 = 0 */
/* SEG24-27 = 0 */
/* SEG28-31 = 0 */
IO_VRAM00 = 0x31;
IO_VRAM01 = 0x32;
IO_VRAM02 = 0x00;
IO_VRAM03 = 0x22;
IO_VRAM04 = 0x32;
IO_VRAM05 = 0x30;
IO_VRAM06 = 0x22;
IO_VRAM07 = 0x32;
3.
• Control register setting
Fixed value
Fixed value
Control register setting
Register name
LCR1
LCDCMR
LCR0
. CSS
. LCEN
. VSEL
. BK
. MS[1:0]
. FP[1:0]
IO_LCR1.byte = 0xFF;
IO_LCDCMR. byte = 0x0F;
IO_LCR0.byte = 0x04;
/* Set to FF. */
/* Setting=0000_0100 */
/* bit7 = 0
CSS Clock oscillation */
/* bit6 = 0
LCEN Disable LCD display in the watch mode. */
/* bit5 = 0
VSEL Internal divided resistors are connected */
/* bit4 = 0
BK Blanking select bit */
/* bit3-2 = 01 MS[1:0] 1/2 duty cycle mode */
/* bit1-0 = 00 FP[1:0] */
}
<Others>
Caution: Clock setup and __set_il (numeric parameter) must have been
performed beforehand. See the “Clock” and “Interrupt” sections.
Note: For register formats, refer to “FR60Lite Family MB91230 Series Sample I/O Register File User's
Guide”.
Example: Values (in parenthesis) used to display 0
COM1
COM0
*0
*6
SEG 4n+3
*1
n: 0 - 3
*5
*2
*3
-
-
*1(0)
*0(1) SEG0
-
-
*3(1)
*2(1) SEG1
-
-
*5(1)
*4(0) SEG2
-
-
*7(1)
*6(1) SEG3
*7
SEG 4n
SEG 4n+1
COM3 COM2 COM1 COM0
*4
SEG 4n+2
459
Chapter 33 LCD Controller
8.Sample Programs
Setting Procedure 2
Program 2
Use the 1/3 duty cycle drive method to display “0 1 2 3” and a four-digit numeric value.
void LCD_sample_1(void)
{
LCDC_initial();
}
Initial setting (LCDC)
<Initial setting>
1.
• Port
Output setting of COM and SEG ports
2..
3.
• VRAM setting
VRAM setting
• Control register setting
Fixed value
Fixed value
Control register setting
Register name
PFR7
PFR8
PFR9
PFRA
PFRB
PFR6
Register name
VRAM00-VRAM15
void LCDC_initial(void)
{
IO_PORT1.IO_PFR7.byte = 0x07;
IO_PORT1.IO_PFR8.byte = 0xFF;
IO_PORT1.IO_PFR9.byte = 0x0F;
IO_PORT1.IO_PFRA.byte = 0x00;
IO_PORT1.IO_PFRB.byte = 0x00;
IO_PORT1.IO_PFR6.byte = 0x00;
/* COM0-2 = 1, COM3 = 0 */
/* SEG0-7 = 1 */
/* SEG8-11 = 1, SEG12-15 = 0 */
/* SEG16-23 = 0 */
/* SEG24-27 = 0 */
/* SEG28-31 = 0 */
IO_VRAM00 = 0x53;
IO_VRAM01 = 0x03;
IO_VRAM02 = 0x30;
IO_VRAM03 = 0x72;
IO_VRAM04 = 0x01;
IO_VRAM05 = 0x37;
Register name
LCR1
LCDCMR
LCR0
. CSS
. LCEN
. VSEL
. BK
. MS[1:0]
. FP[1:0]
IO_LCR1.byte = 0xFF;
IO_LCDCMR. byte = 0x0F;
IO_LCR0.byte = 0x08;
/* Set to FF. */
/* Setting=0000_1000 */
/* bit7 = 0 CSS Clock oscillation */
/* bit6 = 0 LCEN Disable LCD display in the watch mode. */
/* bit5 = 0 VSEL Internal divided resistors are connected */
/* bit4 = 0 BK Blanking select bit */
/* bit3-2 = 10 MS[1:0] 1/3 duty cycle mode */
/* bit1-0 = 00 FP[1:0] */
}
<Others>
Caution: Clock setup and __set_il (numeric parameter) must have been performed
beforehand. See the “Clock” and “Interrupt” sections.
Note: For register formats, refer to “FR60Lite Family MB91230 Series Sample I/O Register File User's Guide”.
Example: Values (in parenthesis) used to display 2
COM0
COM1
COM2
*0
*3
*6
*4
SEG 3n
*7
*1
*5
SEG 3n+1
460
COM3 COM2 COM1 COM0
-
(-)
*1(1)
*0(0) SEG0
-
*5(1)
*4(1)
*3(1) SEG1
-
*8(0)
*7(0)
*6(1) SEG2
-
-
1
0
SEG3
*8
-
1
1
1
SEG4
SEG 3n+2
-
0
0
1
SEG5
First digit
Second digit
Chapter 33 LCD Controller
8.Sample Programs
Setting Procedure 3
Program 3
Use the 1/4 duty cycle drive method to display “0 1 2 3” and a four-digit numeric value.
void LCD_sample_1(void)
{
LCD_initial();
}
Initial setting (LCD)
<Initial setting>
1.
• Port
Output setting of COM and SEG ports
2..
3.
void lcdc_initial(void)
{
IO_PORT1.IO_PFR7.byte = 0x0F;
IO_PORT1.IO_PFR8.byte = 0xFF;
IO_PORT1.IO_PFR9.byte = 0x0F;
IO_PORT1.IO_PFRA.byte = 0x00;
IO_PORT1.IO_PFRB.byte = 0x00;
IO_PORT1.IO_PFR6.byte = 0x00;
Register name
PFR7
PFR8
PFR9
PFRA
PFRB
PFR6
Register name
VRAM00-VRAM15
• VRAM setting
VRAM setting
• Control register setting
Fixed value
Fixed value
Control register setting
/* COM0-3 = 1 */
/* SEG0-7 = 1 */
/* SEG8-15 = 0 */
/* SEG16-23 = 0 */
/* SEG24-27 = 0 */
/* SEG28-31 = 0 */
IO_VRAM00 = 0x9F;
IO_VRAM01 = 0x88;
IO_VRAM02 = 0xB6;
IO_VRAM03 = 0xBC;
register name . bit name
LCR1
LCDCMR
LCR0
. CSS
. LCEN
. VSEL
. BK
. MS[1:0]
. FP[1:0]
IO_LCR1.byte = 0xFF;
IO_LCDCMR. byte = 0x0F;
IO_LCR0.byte = 0x04;
/* Set to FF. */
/* Setting=0000_0100 */
/* bit7 = 0 CSS Clock oscillation */
/* bit6 = 0 LCEN Disable LCD display in the watch mode. */
/* bit5 = 0 VSEL Internal divided resistors are connected */
/* bit4 = 0 BK Blanking select bit */
/* bit3-2 = 11 MS[1:0] 1/4 duty cycle mode */
/* bit1-0 = 00 FP[1:0] */
}
<Others>
Caution: Clock setup and __set_il (numeric parameter) must have been performed
beforehand. See the “Clock” and “Interrupt” sections.
Note: For register formats, refer to “FR60Lite Family MB91230 Series Sample I/O Register File User's Guide”.
Example: Values (in parenthesis) used to display 3
COM3
COM0
COM1
COM2
*0
*4
COM3 COM2 COM1 COM0
*7
SEG 2n
*5
*1
*2
*3(1)
*2(1)
*1(0)
*0(1) SEG0
*7(0)
*6(0)
*5(1)
*4(1) SEG1
*3
*6
SEG 2n+1
461
Chapter 33 LCD Controller
9.Caution
9. Caution
• To access VRAM, be sure to use byte-by-byte access.
• Switching the frame period generation clocks:
Frame period generation clocks (LCR0:CSS) can be switched even during LCD display. However, switching may
cause some screen flicker. To avoid such flicker, be sure to set the blanking select bit (LCR0:BK) to “1” (blank
display) before switching.
• Depending on your LCD, different external divided resistors are used. Use appropriate resistor values.
• When the display mode is set to 1/2 duty cycle, non-selected waveform is output through the COM2 and COM3 pins.
For 1/3 duty cycle, the COM3 pin is used to output non-selected waveform.
• Inappropriate selection or setting of frame period generation clock (CSS), LCD drive power supply control (VSEL),
duty cycle (MS[1:0]) and frame period (FP[1:0]) results in inappropriate LCD display.
• LCD display is disabled in the main stop mode. To enable LCD display in the stop mode, use the sub-stop mode. (See 6
“Setting procedure”.)
462
Chapter 34 Clock Monitor
1.Overview
Chapter 34 Clock Monitor
1. Overview
Clock Monitor is a macro that outputs peripheral clock signals to a terminal to externally monitor them. Clock Monitor provides
a function to divide the frequency of a clock signal before it outputs to the terminal, thus allowing the clock signal to be used as
an event at which external circuits act in synchronization with a MCU peripheral function.
Terminal
Peripheral
(CLKP
) clock
(CLKP)
Prescaler
Selector
2. Features
•
•
•
•
•
Format: Divide a peripheral clock signal to output it to a terminal.
Channel: 1 (CKOT)
Division ratio: 8 types (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128 and 1/256)
Enable output: Capture value: 8-bit counter value
Interrupt: None
463
Chapter 34 Clock Monitor
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Clock Monitor
CKEN
CKR: bit3
0
Disable clock monitor output
1
Enable clock monitor output
Peripheral clock
(CLKP)
1
CKOT/P4
7
Selector
Prescaler
From Port
Data register
Read from port
CKR: bit 2-0
φ =16MHz
φ =8MHz
Clock Output
Frequency Period Frequency Period Frequency
FRQ2-0
125 ns
8MHz
250 ns
4MHz
0 0 0
φ /21
500 ns
0 0 1
φ /22
250 ns
4MHz
2MHz
500 ns
2MHz
1.0 µs
1MHz
0 1 0
φ /23
1.0 µs
1MHz
2.0 µs 500KHz
φ /24
0 1 1
2.0 µs 500KHz
4.0 µs 250KHz
1 0 0
φ /25
4.0 µs 250KHz
8.0 µs 125KHz
1 0 1
φ /26
8.0 µs 125KHz 16.0 µs 62.5KHz
φ /27
1 1 0
16.0 µs 62.5KHz 32.0 µs 31.25KHz
φ /28
1 1 1
φ =4MHz
Period Frequency
500 ns
2MHz
1.0 µs
1MHz
2.0 µs 500KHz
4.0 µs 250KHz
8.0 µs 125KHz
16.0 µs 62.5KHz
32.0 µs 31.25KHz
64.0 µs 15.625KHz
Figure 3-2 Register List
464
CKOT
PFR4: bit7
0
General-purpose port output
1 Clock Monitor dedicated output
0
Chapter 34 Clock Monitor
4.Register
4. Register
4.1 CKR: Clock Output Enable Register
A register for output settings of an internal clock signal
• CKR: Address 0ACH (Access: Byte)
7
–
–
RX/WX
6
–
–
RX/WX
5
–
–
RX/WX
4
–
–
RX/WX
3
CKEN
0
R/W
2
FRQ2
0
R/W
1
FRQ1
0
R/W
0
FRQ0
0
R/W
bit
Initial value
Attributes
(For attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit7-4: Undefined
Writing does not affect an operation. The read value is indeterminate.
• bit3: Enable output.
CKEN
0
1
Operation
Disable clock output to a clock monitor terminal.
Enable clock output to a clock monitor terminal.
Control clock output to a clock monitor terminal.
• bit2-1: Select an output frequency
FRQ2
0
0
0
0
1
1
1
1
FRQ1
0
0
1
1
0
0
1
1
FRQ0
0
1
0
1
0
1
0
1
Clock Frequency Output to a Clock Monitor Terminal
CLKP divided by 2
CLKP divided by 4
CLKP divided by 8
CLKP divided by 16
CLKP divided by 32
CLKP divided by 64
CLKP divided by 128
CLKP divided by 256
Specify the frequency of a clock signal output to a clock monitor terminal.
465
Chapter 34 Clock Monitor
5.Operation
5. Operation
The following diagram shows output waveforms of Clock Monitor.
Peripheral
clock
(CLKP)
1/2
1/4
1/8
1/16
1/32
1/62
1/128
1/256
((2)
PFR4 :P47
(4)
CKEN
(6)
(5)
CKOT
(Example
of 1/8
(1)
(3)
(7)
(1) A terminal (port) is in the general-purpose input status.
(2) The software sets the terminal to Clock Monitor Output (CKOT). (PFR4.P47=“1”)
(3) The terminal is in the “L” status.
(4) The software enables clock output. (CKEN=“1”)
(5) Output a clock signal with the frequency selected with the Output Frequency Select bit (FRQ[2:0]).
(6) The software disables clock output. (CKEN=“0”)
(7) The terminal is in the “L” status.
466
Chapter 34 Clock Monitor
6.Settings
6. Settings
Table 6-1 Settings for Using Clock Monitor
Settings
Setting Registers
Set a terminal (CKOT).
Select a clock frequency.
Enable clock monitor output.
Port Function register (PFR4)
Clock Output Enable register (CKR)
Setting
Procedure*
See 7.1
See 7.2
See 7.3
*:For each setting procedure, refer to an appropriate section.
7. Q&A
7.1 How do I set an output terminal (CKOT)?
Use the Port Function bit (PFR4.CKOT)
Operation
To set an output terminal (CKOT)
Port Direction Bit (CKOT)
Set to “1”.
7.2 How do I select an output frequency?
Use the Output Frequency Select bit (CKR.FRQ[2:0]).
Clock Division
Ratio
1/2
1/4
1/8
1/16
1/32
1/64
1/128
1/256
Output Frequency (Example)
CLKP=32MHz
CLKP=16MHz
16MHz
8MHz
8MHz
4MHz
4MHz
2MHz
2MHz
1MHz
1MHz
500KHz
500KHz
250KHz
250KHz
125KHz
125KHz
62.5KHz
Output Frequency Select Bit(FRQ[2:0])
Set to “000”.
Set to “001”.
Set to “010”.
Set to “011”.
Set to “100”.
Set to “101”.
Set to “110”.
Set to “111”.
7.3 How do I enable/disable clock monitor output?
Use the Output Enable bit (CKR.CKEN).
Operation
To disable clock monitor output
(To set the terminal to the Hi-z status)
Enable clock monitor output.
Output Enable Bit (CKR.CKEN)
Set to “0”.
Set to “1”.
467
Chapter 34 Clock Monitor
8.Sample Program
8. Sample Program
468
Chapter 35 Real-Time Clock
1.Overview
Chapter 35 Real-Time Clock
1. Overview
Real-time Clock (RTC) continues to count elapsed time even in the STOP mode to provide the current real time (HH/
MM/SS). In addition, Real-time Clock continues to operate when power supply other than Vcc3B, and clock supply other
than from the 32KHz oscillator are cut off.
This allows precise time counting without a return from an interrupt during stand by periods.
Sub-Second
h)
(004000h)
Reload
Subclock
(32.768 KHz)
1/2
21 Bit
Down Counter
Counter
Second Minute Hour
Update
Second Minute Hour
2. Features
•
•
•
•
•
•
•
Information: Time count (HH/MM/SS). (This clock continues to operate even in the STOP mode.)
Operational only with Vcc3B and the 32kHz oscillator.
Quantity: 1
Time unit: Subclock (32kHz) divided by 2
Power supply/Operation clock:
For register access: Vcc/CLKP
For time count:
VCC3B /Subclock
• Time: Initial setting and adjustment are possible.
• Interrupt: Interrupts can be generated at any of the four intervals: 1 second, 1 minute, 1 hour and 1 day.
• Others: By changing the value of the sub-second register, interrupts can be generated at any interval (from short to
long).
469
Chapter 35 Real-Time Clock
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Real-Time Clock
RUN WT CR: bit 3
Read only
0 RTC
RT C inactive
1 RTC
RT C active
"0x0400" = 1 second
(Initial value indeterminate)
WTBR
Reload
Subclock
32.768kHz
32.768kHz
Every second
0
INT0 WT CR: bit8
0 Clear interrupt requests
Disable
1
21 Bit Counter
Prescaler: 1/2
INTE0 WT CR: bit9
0 Disable interrupts
1 Enable interrupts
1
Read: 1=Interrupt request has been made
ST WT CR: bit 0
0 Stop after reset
1
Start
Every minute
0
1
INT1 WT CR:
CR: bit10
bit10
0 Clear interrupt requests
1
Disable
Read:
1=Interrupt request
Read:
1= has been made
OR
0
Every hour
INT2 WT CR:
CR: bit12
bit12
0 Clear interrupt requests
1
Disable
Read:
1=Interrupt request
Read:
1= has been made
INTE1 WT CR:
CR: bit11
bit11
0 Disable interrupts
1 Enable interrupts
1
INTE2 WT CR:
CR: bit13
bit13
0 Disable interrupts
1 Enable interrupts
Overflow
Overflow
Every 24 hour (Everyday)
INT3 WT CR:
CR: bit14
bit14
0 Clear interrupt requests
1
Disable
Read:
1=Interrupt request
Read:
1= has been made
Hour Counter
Minute Counter
Second Counter
RTC
interrupt
(#45)
Overflow
0
1
INTE3 WT CR: bit15
0 Disable interrupts
1 Enable interrupts
OR
WTSR (W)
UPDT WT CR: bit 2
0 No impact on operation
1
Update
WTMR (W)
WTSR (R)
WTMR (R)
Second
Minute
WTHR (W)
DBL WTDBL: bit 0
0 Supply clock signals
1 Stop supplying clock signals
WTHR (R)
Hour
Internal clock (CLKP)
(for register access)
Figure 3-2 Register List
Note: For ICR registers and interrupt vectors, refer to “Chapter 20 Interrupt Control (Page No.207)”.
470
Chapter 35 Real-Time Clock
4.Registers
4. Registers
4.1 WTDBL: Clock Disable Register
This register is used to supply peripheral clock (CLKP) signals to the Real-time Clock module.
• WTDBL: Address 0F5H (Access: Byte)
7
–
–
–
RX/WX
6
–
–
–
RX/WX
5
–
–
–
RX/WX
4
–
–
–
RX/WX
3
–
–
–
RX/WX
2
–
–
–
RX/WX
1
–
–
–
RX/WX
0
DBL
0
0
R/W
bit
Initial value
When reset
Attribute
(For attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit7-1: Undefined.The read value is indeterminate. Writing does not affect the operation.
• bit0: Stop supplying peripheral clock (CLKP) signals
DBL
0
1
Operation
Continue to supply peripheral clock (CLKP) signals to Real-time Clock.
Enable access to Real-time Clock.
Stop supplying peripheral clock (CLKP) signals to Real-time Clock.
Disable access to Real-time Clock (other than DBL bit).
• If the peripheral clock supply disable bit is set to “1”, peripheral clock (CLKP) signals are no longer supplied to the
Real-time Clock module.
This disables access to the Real-time Clock module's registers, such as WTCR, WTBR, WTSR, WTMR and
WTHR, other than the clock disable register (WTDBL).
If an attempt to read from WTCR, WTBR, WTSR, WTMR and WTHR is made in this situation, indeterminate
values are read; these values do not reflect writing operation.
• “0” can be written to the peripheral clock supply disable bit when the bit is set to “1”.
(See “9. Caution (Page No.483)”.)
471
Chapter 35 Real-Time Clock
4.Registers
4.2 WTCR: RTC Control Register
This register is used to control behavior of the Real-time Clock module.
• WTCR: Address 0F6H
(Access: Byte, Half-word)
15
INTE3
0
0
R/W
14
INT3
0
0
R(R1),W
13
INTE2
0
0
R/W
12
INT2
0
0
R(R1),W
11
INTE1
0
0
R/W
10
INT1
0
0
R(R1),W
9
INTE0
0
0
R/W
8
INT0
0
0
R(R1),W
7
Reserved
0
0
R/W0
6
Reserved
0
0
R/W0
5
Reserved
0
0
R/W0
4
–
–
–
RX/WX
3
RUN
0
0
R/WX
2
UPDT
0
0
R(R0)/W
1
–
–
–
RX/WX
0
ST
X
X
R/W
(For attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
• bit15: Enable interrupt requests at 1-day intervals
INTE3
0
1
Operation
No interrupt requests
Generate interrupt requests at 1-day (24 hour) intervals.
When the hour counter overflows, this flag is set to “1”.
• bit14: 1-day interrupt request flag
INT3
0
1
Status
Read
Write
No interrupt requests
Generate interrupt requests at 1-day (24 hour)
intervals.
Clear the flag.
Writing does not affect the operation.
• bit13: Enable interrupt requests at 1-hour intervals
INTE2
0
1
Operation
No interrupt requests
Generate interrupt requests at 1-hour intervals.
When the minute counter overflows, this flag is set to “1”.
• bit12: 1-hour interrupt request flag
INT2
0
1
Status
Read
Write
Clear the flag.
Writing does not affect the operation.
No interrupt requests
Generate interrupt requests at 1-hour intervals.
• bit11: Enable interrupt requests at 1-minute intervals
INTE1
0
1
Operation
No interrupt requests
Generate interrupt requests at 1-minute intervals.
When the minute counter overflows, this flag is set to “1”.
472
bit
Initial value
When reset
Attribute
bit
Initial value
When reset
Attribute
Chapter 35 Real-Time Clock
4.Registers
• bit10: 1-minute interrupt request flag
INT1
0
1
Operation
Read
No interrupt requests
Generate interrupt requests at 1-minute intervals.
Write
Clear the flag.
Writing does not affect the operation.
• bit9: Enable interrupt requests at 1-second intervals
INTE0
0
1
Operation
No interrupt requests
Generate interrupt requests at 1-second intervals.
When the 21 bit down counter is set to “0”, this flag is set to “1”.
• bit8: 1-second interrupt request flag
INT0
0
1
Status
Read
No interrupt requests
Generate interrupt requests at 1-second intervals.
Write
Clear the flag.
Writing does not affect the operation.
• bit7-5: Reserved
Be sure to write “0”. The read value is the value written.
• bit4: Undefined
Writing does not affect the operation. The read value is indeterminate.
• bit3: Operation status
RUN
0
1
Status
The Real-time Clock module is inactive.
The Real-time Clock module is active.
• bit2: Update
UPDT
0
1
Status/Operation
The update has been completed. (Writing “0” does not affect the operation.)
Update the hour/minute/second counters with the values of the hour/minute/second registers,
respectively.
Before writing “1” to the update bit (UPDT), the hour/minute/second registers must be set to the values with which to
update the hour/minute/second counters. The hour/minute/second registers are updated on reloading to the 21 bit down
counter.
• bit1: Undefined
Writing does not affect the operation. The read value is indeterminate.
• bit0: Start
ST
0
1
Operation
The Real-time Clock module ceases to operate, and the 21 bit down counter and the hour/minute/second
counters are cleared.
The settings of the hour/minute/second registers are loaded to the hour/minute/second counters, and the
Real-time Clock module starts to operate.
The ST bit is not initialized on reset.(See “9. Caution (Page No.483)”.)
473
Chapter 35 Real-Time Clock
4.Registers
4.3 WTBR: Sub-Second Registers
These registers are used to hold values to be reloaded to the 21 bit down counter.
• WTBR0: Address 0F9H (Access: Byte)
• WTBR1: Address 0FAH (Access: Byte)
• WTBR2: Address 0FBH (Access: Byte)
WTBR0
7
–
–
–
RX/WX
6
–
–
–
RX/WX
5
–
–
–
RX/WX
4
3
2
1
0
D20
D19
D18
D17
D16
X
X
X
X
X
Unchanged Unchanged Unchanged Unchanged Unchanged
R/W
R/W
R/W
R/W
R/W
WTBR1
7
6
5
4
3
2
1
0
D15
D14
D13
D12
D11
D10
D9
D8
X
X
X
X
X
X
X
X
Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WTBR2
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit
Initial value
When reset
Attribute
bit
Initial value
When reset
Attribute
bit
Initial value
When reset
Attribute
(For attributes, refer to “■Meaning of Bit Attribute Symbols (Page No.10)”.)
The sub-second registers, WTBR, holds values to be reloaded to the 21 bit down counter. When the 21 bit down counter
value becomes “0”, the settings of WTBR are reloaded to the 21 bit down counter.
(See “9. Caution (Page No.483)”.)
474
Chapter 35 Real-Time Clock
4.Registers
4.4 WTHR/WTMR/WTSR: Hour/Minute/Second Registers
These registers hold time information (HH/MM/SS) for Real-time Clock.
• WTHR (Hour register): Address 0FCH
• WTMR (Minute register): Address 0FDH
(Access: Byte, Half-word)
(Access: Byte, Half-word)
• WTSR (Second register): Address 0FEH (Access: Byte)
WTHR
7
–
–
–
RX/WX
6
–
–
–
RX/WX
WTMR
7
–
–
–
RX/WX
6
–
–
–
RX/WX
5
4
3
2
1
0
bit
M5
M4
M3
M2
M1
M0
X
X
X
X
X
X
Initial value
Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged When reset
R,W
R,W
R,W
R,W
R,W
R,W
Attribute
WTSR
7
–
–
–
RX/WX
6
–
–
–
RX/WX
5
4
3
2
1
0
bit
S5
S4
S3
S2
S1
S0
X
X
X
X
X
X
Initial value
Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged When reset
R,W
R,W
R,W
R,W
R,W
R,W
Attribute
5
–
–
–
RX/WX
4
3
2
1
0
bit
H4
H3
H2
H1
H0
X
X
X
X
X
Initial value
Unchanged Unchanged Unchanged Unchanged Unchanged When reset
R,W
R,W
R,W
R,W
R,W
Attribute
• The values written to the hour/minute/second registers are the initial values to be loaded to the hour/minute/second
counters.
By setting “1” to the update bit (WTCR.UPDT) or the start bit (WTCR.ST), the hour/minute/second register values
are written to the hour/minute/second counters.
• The hour/minute/second counter values are saved to the hour/minute/second registers every time when the second
counter overflows, that is, at intervals of one minute. When the hour/minute/second counters are read, the saved
count values, not written ones, are read.
• The hour/minute/second registers consist of two separate sets of registers: one for reading and the other for writing.
(See “9. Caution (Page No.483)”.)
475
Chapter 35 Real-Time Clock
5.Operation
5. Operation
This section describes Real-time Clock operation.
(1)
(4)
(19)
ST
4000 h
21 bit down counter
(8)
(9)
(6)
Clear
0000 h
(20)
(2)
(10)
59S
Second
S
(5)
Clear
Hour/
Minute/
Second
counters
(10)
(2)
(20)
(11)
59M
Minute
M
(5)
Clear
(11)
(20)
(2)
(5)
Clear
WTSR
WTMR
WTHR
WTBR(0 -2)
RUN
DBL
STOP
23H
(12)
H
Hour
(2)
(20)
(3) Hour/Minute/Second
register values
(
(3) Sub-second values
(7)
(20)
(13)
(14)
Power supply (other than VCC3B)
(18)
During STOP
Inactive other than RTC (Indeterminate)
(15)
(16)
(17)
(17)
INIT pin input
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
476
The start bit (ST) is set to “1” and then “0”. (Register initialization operation)
This (ST=“0”) resets to 0 and stops the 21 bit down counter and the hour/minute/second timers.
• The software writes hour, minute, and second values to the hour/minute/second registers, WTHR/WTMR/
WTSR.
• The software writes “00H”, “40H”, and “00H” to the sub-second registers, WTBR0/WTBR1/WTBR2.
• The interrupt request bits (INT0, INT1, INT2 and INT3) are initialized, and the interrupt request enable bits
(INTE0, INTE1, INTE2, and INTE3) are set to “interrupts enabled”.
The start bit (ST) is set to “1”.
This (ST=“1”) causes the values of the hour/minute/second registers, WTHR/WTMR/WTSR, to be loaded to the
hour/minute/second timers.
The 21 bit down counter value being “000000H”, the values of the sub-second registers, WTBR0/WTBR1/
WTBR2, are loaded to the 21 bit down counter.
The run flag (RUN) is set to “1”.
The 21 bit down counter begins counting at the subclock divided by 2 (32.768/2 KHz).
When the 21 bit down counter reaches “000000H”, the value of the sub-second registers “004000H” is loaded to
the 21 bit down counter. The second counter counts up, generating a 1-second interrupt request.
When the second counter counts up to “59”, the counter is cleared next time when the counter counts up, at
Chapter 35 Real-Time Clock
5.Operation
(15)
which the minute counter counts up, generating a 1-minute interrupt request.
When the minute counter counts up to “59”, the counter is cleared next time when the counter counts up, at
which the hour counter counts up, generating a 1-hour interrupt request.
When the hour counter counts up to “23”, the counter is cleared next time when the counter counts up, at which a
1-day interrupt request is generated.
The software sets the peripheral clock supply disable bit (WTDBL.DBL) to “1”.
The software changes the status of Real-time Clock to STOP. (Set the stop bit (STCR.STOP) to “1”.)
Real-time Clock continues to operate in the STOP state.
Power supply other than VCC3B is cut off.
(16)
(17)
(18)
(19)
(20)
The power supply cut off resumes.
INIT signal input from a pin activates CPU.
The software sets the peripheral clock supply disable bit (WTDBL.DBL) to “0”.
The start bit (ST) is set to “0”.
This (ST=“0”) resets and stops the 21 bit down counter and the hour/minute/second counters.
(11)
(12)
(13)
(14)
477
Chapter 35 Real-Time Clock
6.Setting
6. Setting
Table 6-1 Required Settings to Run Real-time Clock
Setting
Set a reload value to the sub-second registers.
Initialize Real-time Clock.
Set time (hour/minute/second).
Activate Real-time Clock.
Setting Registers
Setting
Procedure *
Sub-second registers
(WTBR0,WTBR1 and WTBR2)
RTC control register (WTCR)
Hour/minute/second registers
(WTHR/WTMR/WTSR)
RTC control register (WTCR)
See 7.1.
See 7.2.
See 7.3.
See 7.4.
*: For the setting procedure, refer to the section indicated by the number.
Table 6-2 Required Settings to Know Time
Setting
Setting Registers
Setting
Procedure *
Hour/minute/second registers
(WTHR/WTMR/WTSR)
Read time.
See 7.6.
*: For the setting procedure, refer to the section indicated by the number.
Table 6-3 Required Settings to Stop Real-Time Clock
Setting
Stop Real-time Clock.
Setting Registers
RTC control register (WTCR)
Setting
Procedure *
See 7.7.
*: For the setting procedure, refer to the section indicated by the number.
Table 6-4 Required Settings to Generate Interrupts to Real-time Clock
Setting
Setting Registers
Setting
Procedure *
Set a RTC interrupt vector and RTC interrupt level.
See “Chapter 20 Interrupt Control (Page
No.207)”.
See 7.10.
Enable RTC interrupts.
Clear interrupt requests.
Enable interrupt requests.
RTC control register (WTCR)
See 7.11.
*: For the setting procedure, refer to the section indicated by the number.
Table 6-5 Required Settings to Further Save Current Consumption in the STOP mode
Setting
Stop supplying peripheral clock signals.
Setting Registers
Clock disable register (WTDBL)
Setting
Procedure *
See 7.8.
*: For the setting procedure, refer to the section indicated by the number.
Table 6-6 Required Setting to Resume Supplying Peripheral Clock Signals Once Stopped
Setting
478
Setting Registers
Setting
Procedure *
Chapter 35 Real-Time Clock
6.Setting
Table 6-6 Required Setting to Resume Supplying Peripheral Clock Signals Once Stopped
Resume supplying peripheral clock signals.
Clock disable register (WTDBL)
See 7.8.
*: For the setting procedure, refer to the section indicated by the number.
479
Chapter 35 Real-Time Clock
7.Q&A
7. Q&A
7.1 How do I set the count period of 1 second?
Stop Real-time Clock and then set the sub-second register, WTBR, to “004000H”.
7.2 How do I initialize Real-time Clock?
Use the start bit (WTCR.START).
Changing the start bit from “1” to “0” resets the hour/minute/second counters and the 21 bit down counter
to “0” (initialization), and stops count operation.
7.3 How do I set or update time (hour/minute/second)?
Write values to the hour/minute/second registers, WTHR/WTMR/WTSR, and set the update bit (UPDT).
Operation
To update the hour/minute/second counters
Update bit (UPDT)
Set the bit to “1”.
7.4 How do I start or stop Real-time Clock's counting?
Use the start bit (WTCR.START).
Operation
To stop Real-time Clock's counting
To start Real-time Clock's counting
Start bit (START)
Set the bit to “0”.
Set the bit to “1”.
7.5 How do I confirm that Real-time Clock is active?
Use the run flag (WTCR.RUN).
Operation
Real-time Clock is inactive.
Real-time Clock is active.
Run flag (RUN)
The flag is set to “0”.
The flag is set to “1”.
7.6 How do I know time?
Read the hour/minute/second registers, WTHR/WTMR/WTSR.
Note that only byte-access is allowed to these register. So, when these registers are read at the very timing of changing
over the hour or minute boundary as shown below, there is a possibility of misjudging the time. So, read several times to
get a logically consistent value.
Example: Read begins at the second register: 02:59:59 (SS) => 03:59:59 (SS) => 03:00:00
Read begins at the hour register: 02:59:59 => 02:00:00 => 03:00:00
7.7 How do I stop Real-time Clock?
See 7.4.
480
Chapter 35 Real-Time Clock
7.Q&A
7.8 How do I save current consumption or resume Real-time Clock in the STOP mode?
Use the peripheral clock supply disable bit (WTDBL.DBL).
Operation
To resume supplying peripheral clock signals and allow
access to a register when clock supply stops (Resume)
To stop peripheral clock signals in the STOP mode to
save current consumption (Stop)
Peripheral clock supply disable bit (DBL)
Resume power supply other than Vcc3B=>Restore from
STOP=>Set the DBL bit to “0”.
Set the DBL bit to “1”=>Transit to STOP=>Cut off power
supply other than Vcc3B.
7.9 What are interrupt-related registers?
RTC interrupt vector and level settings.
The following table shows the relationship between interrupt levels and vectors.
For details on interrupt levels and vectors, refer to “Chapter 20 Interrupt Control (Page No.207)”.
Interrupt vectors (Default)
#45 (0FFF48h)
Interrupt level set bit (ICR[4.0])
Interrupt level register ICR29 (0045Dh)
The interrupt request flags (INT0,INT1,INT2,INT3) are not automatically cleared, so the software must clear them by
writing “0” to these flags before control is returned from interrupt processing.
7.10 What interrupts are available and how are they selected?
There are four interrupt causes:
Interrupt cause
Interrupt request bit
On counting seconds
On counting minutes
On counting hours
On counting days
INT0
INT1
INT2
INT3
Interrupt request enable
bits
INTE0
INTE1
INTE2
INTE3
An interrupt request is made by ORing these four interrupt causes. Each cause can be selected with the corresponding
interrupt request enable bit.
7.11 How do I enable interrupts?
Use the interrupt request enable bits (WTCR.INTE0, WTCR.INTE1, WTCR.INTE2, and WTCR.INTE3).
To disable interrupts
To enable interrupts
Setting Procedure
Interrupt request enable bits (INTE0, INTE1, INTE2, and INTE3)
Set the bit to “0”.
Set the bit to “1”.
To clear interrupt requests,
Use the interrupt request bits (WTCR.INT0, WTCR.INT1, WTCR.INT2 and WTCR.INT3).
To clear interrupt requests
Setting Procedure
Interrupt request bits (INT0, INT1, INT2 and INT3)
Write “0”.
481
Chapter 35 Real-Time Clock
8.Sample Programs
8. Sample Programs
Setting Procedure 1
Program 1
Start Real-time Clock's counting at 10:10:00. Enable detection of "H" level
external interrupts (INT0). Change the clock's status to STOP. Restore the
clock from STOP on detecting another external interrupt. Read time from Realtime Clock.
RTC initialization
void RTC_sample2 (void)
{
RTC_initial () ;
RTC_start () ;
RTC activation and interrupt level setting
External interrupt setting
EX_INT0_initial () ;
Transition to STOP mode
STOP_Hiz_no_clock () ;
After restoration from STOP mode,
reading from RTC
(See “Chapter 10 Standby (Page No.91)”.)
RTC_read () ;
}
void RTC_initial (void)
{
<RTC initial setting>
• RTC
register name .bit name
1.
Register initialization
WTCR. ST
IO_WTCR.bit.ST = 1;
IO_WTCR.bit.ST = 0;
/* Prepare initialization.
*/
/* Stop (Register initialization) */
2.
3.
Interval time setting (1 second)
Time initial value setting
WTBR
WTSR
IO_WTBR.word = 0x04000;
IO_WTSR.byte = 00;
/* Set a count value. 32.768k/2/2^14=1 second */
/* Set second.
*/
WTMR
IO_WTMR.byte = 10;
/* Set minute.
WTHR
IO_WTHR.byte = 10;
/* Set hour.
WTCR
IO_WTCR.hword = IO_WTCR.hword & 0x00FF;
4.
Initial setting for RTC interrupts
*/
*/
/* Clear the interrupt flag. Disable interrupts */
}
<RTC activation and interrupt level setting>
void RTC_start (void)
register name .bit name
{
Starting RTC
WTCR . ST
IO_WTCR.bit.ST = 1;
/* Start RTC. */
Disabling access to RTC registers
WTDBL . DBL
IO_WTDBL.bit = 1;
/* Disable access to the RTC registers. */
Interrupt level setting (RTC)
ICR29
IO_ICR[29].bit.ICR = 18;
/* The value is arbitrary. */
Interrupt level setting (INT0)
ICR00
IO_ICR[00].bit.ICR = 20;
/* The value is arbitrary. */
I flag setting
(CCR)
__EI () ;
/* Enable interrupts */
}
<Preparing for reading RTC time (Interrupt setting)>
RTC interrupt setting
RTC_read (void)
WTCR
{
. INT0
IO_WTCR.bit.INT0 = 0;
/* RTC Clear the second interrupt request flag. */
. INTE0
IO_WTCR.bit.INTE0 = 1;
/* RTC Enable second interrupt requests */
}
<External interrupt setting>
EX_INT0_initial (void)
<register name. bit name>
INT0 port input selection
External
selection
interrupt
detection
}
DDR
level ELVR0
IO_DDR1= 0x01;
/* INT0 only. INT0 input */
IO_ELVR0.hword= 0x0001;
/* Setting: 00000001 (bit) */
/* Bit7-2= "000000": */
/* Bit1-0= "01" H level detection */
INT0 Interrupt enabling
EIRR0. ER0
IO_EIRR0.bit.ER0= 0;
/* ER0 Clear the interrupt flag. */
EIRR0. EN0
IO_ENIR0.bit.EN0= 1;
/* EN0 Enable interrupts */
}
<RTC interrupts>
__intrrupt void RTC_read_int (void)
/* ★ */
{
Enabling access to RTC registers
WTDBL . DBL
IO_WTDBL . DBL = 0;
Reading time
WTHR
JIKAN (char) = IO_WTHR.byte & 0x1F;
/*Hour*/
WTMR
FUNN (char) = IO_WTMR.byte & 0x3F;
/*Minute*/
WTSR
BYOU (char) = IO_WTSR.byte & 0x3F;
/*Second*/
WTCR . INTE0
IO_WTCR.bit.INTE0 = 0;
/*RTC Disable interrupts */
Interrupts disabling
/* Enable access to the RTC registers. */
}
<RTC interrupts>
__interrupt void INT0_int ()
/* */
{
Interrupt request flag clear
EIRR . ER0
IO_EIRR0.bit.ER0= 0;
/* ER0 Clear the second interrupt request flag. */
}
<Interrupt vectors>
Vector table setting
The interrupt routine must be specified in the vector table.
#pragma intvect RTC_read_int 45
#pragma intvect INT0_int 16
Caution: Clock setup and __set_il (numeric parameter) must have been
performed beforehand. See the "Clock" and "Interrupt" section.
482
Note: For register formats, refer to "FR60Lite Family MB91230 Series Sample I/O Register File User's Guide".
Chapter 35 Real-Time Clock
9.Caution
9. Caution
• To access the registers in Real-time Clock, such as WTCR, WTBR, WTSR, WTMR and WTHR, the peripheral clock
supply disable bit (WTDBL.DBL) must be set to “0”. However, only the clock disable register (WTDBL) can be
accessed even if (WTDBL.DBL) is set to “1”.
• Real-time Clock can operate only with VCC3B. However, before cutting off power supply other than VCC3B, be sure to
set the peripheral clock supply disable bit (WTDBL.DBL) to “1”.
• Setting the interrupt request flags (WTCR.INT0, WTCR.INT1, WTCR.INT2, and WTCR.INT3) to “1” due to
overflow, and writing “0” to that bit have occurred at the same time, the flag is set to “1”. (Flag setting takes
precedence.)
• Writing “1” to the update bit (ETCR.UPDT) and update completion have occurred at the same time, the update bit
(UPDT) is set to “0”.
• When the second counter holds the value of 59, even if “1” is written to the update bit (WTCR.UPDT), the hour/
minute/second counters are not updated, leaving the update bit to remain “0”.
In order to update the hour/minute/second counters, it is recommended that “0” should be written to the start bit
(WTCR.ST), the hour/minute/second counters be cleared to “0”, and then “1” be written to the start bit (ST).
• If you stop the peripheral clock (CLKP) after updating the hour/minute/second counters using the update bit
(WTCR.UPDT), read the hour/minute/second registers to confirm that they have been updated before stopping the
peripheral clock.
• When you start to use the Real-time Clock module, change the start bit (ST) from “1” to “0”, and clear the hour/minute/
second counters and the 21 bit down counter to “0”.
• If a reload has occurred during updating the sub-second registers, WTBR0 to WTBR2, an unexpected value may be
reloaded to the 21 bit down counter. Therefore, it is recommended that the sub-second register, WTBR, should be
updated with the start bit (WTCR.ST) set to “0”.
• If all the sub-second registers, WTBR0 to WTBR2, are set to “0”, the 21 bit down counter does not operate, resulting in
the Real-time Clock module to be inoperational.
• If a carry has occurred during reading from the hour/minute/second registers, WTHR/WTMR/WTSR, inappropriate
values may be read. To avoid this, it is recommended that interrupts (INT0) should be used to read time (HH/MM/SS).
• In order for the Real-time Clock module to function properly, the frequency of the subclock must be much lower than
that of the peripheral clock (CLKP). If not, correct values cannot be read from WTHR/WTMR/WTSR.
• Note that only byte-access is allowed to these register. So, when these registers are read at the very timing of changing
over the hour or minute boundary as shown below, there is a possibility of misjudging the time. So, read several times
to get a logically consistent value.
Example: Read begins at the second register: 02:59:59=> 03:59:59 => 03:00:00
Read begins at the hour register: 02:59:59 => 02:00:00 => 03:00:00
In this case, the current time should be interpreted as 3 o'clock.
483
Chapter 35 Real-Time Clock
9.Caution
484
Chapter 36 Flash Memory
1.Overview
Chapter 36 Flash Memory
This chapter describes the use of built-in flash memory from the CPU.
1. Overview
The MB91F233 and MB91F233L each have built-in Flash memory with a capacity of 256 KBytes (2 Mbits), capability
of batch-erasing all sectors or erasing on the sector level via single +3.3 V power supply, and writing to the FR-CPU at
the half-word (16-bit) level.
2. Features
•
•
•
•
Capacity: 256 KBytes (2 Mbits)
Power: Single +3.3 V supply
Basic specification: Same as MBM29LV400TC (except size and part of sector configuration)
Additional specifications: Faster device operation by enabling commands/data reads at word (32-bit) level.
(When CPU’s built-in ROM operating)
• External writers: Available via ROM writer
• Operation modes:
(1) CPU-ROM mode
(CPU accesses Flash memory, read only, Byte/Half-word/Word access.)
(2) CPU-Programming mode
(CPU accesses Flash memory. Read, Half-word access only.)
(3) Flash memory mode (external access to Flash memory enabled)
• Features (Through combination of Flash memory macro and FR-CPU interface circuit):
• Functions as CPU program/data storage memory.
• Enables access to 32-bit bus width when used as ROM.
• Enables read/write/erase by CPU (auto program algorithm *).
• Functions equivalent to MBM29LV400TC stand-alone Flash-memory product.
• Enables read/write/erase by ROM (auto program algorithm *).
*: Auto program algorithm = Embedded Algorithm TM
485
Chapter 36 Flash Memory
3.Configuration
3. Configuration
Figure 3-1 Block Diagram
CPU
CPU core
FLASH interface
FLASH memory
Control signal
Control signal
Control signal
A0 to A17
A0 to A17
Address
DQ0 to DQ15
DQ0 to DQ15
Data
Control
signal
Interface
with
FLASH
writer
(when in
FLASH
mode)
Address
Data
Figure 3-2 Address Map (when accessing from FR-CPU)
000 F_FFFFH
FFFF_FFFFH
SAA4 (16KB)
SAA9 (16KB)
SAA3 (8KB)
SAA8 (8KB)
SAA2 (8KB)
SAA7 (8KB)
SAA1 (32KB)
SAA6 (32KB)
SAA0 (64KB)
SAA5 (64KB)
000 F_8000H
000 F_7FFFH
00 0F_4000H
000F_3FFFH
0010_0000H
000F_FFFFH
000C_0000H
FLASH
memory
256KB
000F_0000H
000E_FFFFH
000E_0000H
000D_FFFFH
000C_0000H
0000_0000H
Bit 31
Byte positions when
accessing in CPU mode
486
16 15
0
1
0
2
3
Chapter 36 Flash Memory
3.Configuration
Table 3-1 Address map (Sector addresses, when accessing from FR-CPU)
Sector address
Corresponding bit position
Sector capacity
SAA9
Address range
F_FFFFH to F_8000H
Bit 15 to 0
16 KB
SAA8
F_7FFFH to F_4000H
Bit 15 to 0
8 KB
SAA7
F_3FFFH to F_0000H
Bit 15 to 0
8 KB
SAA6
E_FFFFH to E_0000H
Bit 15 to 0
32 KB
SAA5
D_FFFFH to C_0000H
Bit 15 to 0
64 KB
SAA4
F_FFFFH to F_8000H
Bit 31 to 15
16 KB
SAA3
F_7FFFH to F_4000H
Bit 31 to 15
8 KB
SAA2
F_3FFFH to F_0000H
Bit 31 to 15
8 KB
SAA1
E_FFFFH to E_0000H
Bit 31 to 15
32 KB
SAA0
D_FFFFH to C_0000H
Bit 31 to 15
64 KB
Flash memory's address mapping is different depending on whether it is being accessed from the FR-CPU or ROM
writer.
Figure 3-3 Address Map (when accessing from ROM writer)
F_FFFFH
SAA9(16KB)
F_C000H
F_BFFFH
SAA8(8KB)
F_A000H
F_9FFFH
SAA7(8KB)
F_8000H
F_7FFFH
SAA6(32KB)
F_0000H
E_FFFFH
SAA5(64KB)
E_0000H
D_FFFFH
SAA4(16KB)
D_C000H
D_BFFFH
SAA3(8KB)
D_A000H
D_9FFFH
SAA2(8KB)
D_8000H
D_7FFFH
SAA1(32KB)
D_0000H
C_FFFFH
SAA0(64KB)
C_0000H
15
0 Bit position
1
0
Byte position (When writing with writer)
0
1
When CPU is reading
487
Chapter 36 Flash Memory
3.Configuration
Table 3-2 Sector addresses (when accessing from ROM writer)
Sector address
488
Corresponding bit position
Sector capacity
SAA9
Address range
F_FFFFH to F_C000H
Bit 15 to 0
16 KB
SAA8
F_BFFFH to F_A000H
Bit 15 to 0
8 KB
SAA7
F_9FFFH to F_8000H
Bit 15 to 0
8 KB
SAA6
F_7FFFH to F_0000H
Bit 15 to 0
32 KB
SAA5
E_FFFFH to E_0000H
Bit 15 to 0
64 KB
SAA4
D_FFFFH to D_C000H
Bit 15 to 0
16 KB
SAA3
D_BFFFH to D_A000H
Bit 15 to 0
8 KB
SAA2
D_9FFFH to D_8000H
Bit 15 to 0
8 KB
SAA1
D_7FFFH to D_0000H
Bit 15 to 0
32 KB
SAA0
C_FFFFH to C_0000H
Bit 15 to 0
64 KB
Chapter 36 Flash Memory
4.Registers
4. Registers
4.1 FLCR: FLASH Memory Control Status Register
This register indicates the operating status of Flash memory.
• FLCR: Address 07000H (Access: Byte)
7
0
R/W0
6
1
R/W1
5
BIRE
1
R/W
4
0
RX/WX
3
RDY
X
R/WX
2
0
R/W0
1
WE
0
R/W
0
0
R/W0
bit
Initial value
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details about attributes.)
• bit 7-6: Reserved: Always write “0”.
The read value is the value written: “0”.
• bit 5: Burn in ROM permission
BIRE
0
1
Functions
Burn in ROM access denied
Burn in ROM access granted. (Specify for serial writing to Flash memory.)
• In Burn in ROM mode, it is possible to access Burn in ROM rather than Flash memory.
• The startup command for Flash memory serial writing is normally written inside Burn in ROM. For this reason, “1”
is normally specified when serial-writing to Flash memory.
• bit 4: Reserved: The read value is indeterminate.
Writing does not effect the operation.
• bit 3: Auto Algorithm flag
RDY
0
1
Flag description
Do not accept data write, read, or erase commands (during read/write).
Accept data write, read, and erase commands.
Indicates the Auto Algorithm operating status.
• bit 2: Reserved: Always write “0”.
The read value is the value written: “0”.
• bit 1: Data/command write control
WE
0
1
Functions
Write to Flash memory prohibited and 32-bit read mode
Write to Flash memory permitted and 16-bit read mode
• Controls writing of data and commands to Flash memory in CPU mode.
• While the Data/command write control bit is “0”, all data and commands written to Flash memory are invalid.
Additionally, data reads from Flash memory are performed with 32-bit access.
• While the Data/command write control bit is “1”, data and commands written to Flash memory are avoid, and Auto
Algorithm launch is enabled.
• Note, however, that data reads from, and writes to, Flash memory are performed with 16-bit access. Only access
Flash memory with 16-bit access. 32 and 8-bit access are prohibited.
• Make sure that the Auto Algorithm is halted via the RDY bit before overwriting the Data/command write control
bit.
• While the RDY bit is “0”, the Data/command write control bit may not be overwritten.
• bit 0: Reserved: Always write “0”.
The read value is the value written: “0”.
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Chapter 36 Flash Memory
4.Registers
4.2 FLWC: FLASH Memory Wait Register
This register controls Flash memory waiting.
• FLWC: Address 07004H (Access: Byte)
7
6
0
R/W0
0
R/W0
5
FAC1
0
R/W
4
FAC0
0
R/W
3
0
R/W0
2
WTC2
0
R/W
1
WTC1
1
R/W
0
WTC0
1
R/W
bit
Initial value
Attribute
(See “■Meaning of Bit Attribute Symbols (Page No.10)” for details about attributes.)
• bit 7-6: Reserved: Always write “0”.
The read value is the value written: “0”.
• bit 5-4: Control pulse width of internal write signal.
FAC1
0
0
1
1
FAC0
0
1
0
1
ATDIN
0.5 Clock
1 Clock
1.5 Clock
2 Clock
EQIN
1 Clock (Initial value)
1.5 Clock
2 Clock
2.5 Clock
Note: ATDIN and EQIN are internal write signals. The default settings should normally be used.
• bit 3: Reserved: Always write “0”.
The read value is the value written: “0”.
• bit 2-0: Wait cycle control
WTC
2
0
0
0
0
1
1
1
1
WTC
1
0
0
1
1
0
0
1
1
WTC
0
0
1
0
1
0
1
0
1
Wait cycle
1
2
3
When reading
Disabled
Operable up to 33 MHz.
Operable up to 33 MHz.
Operable up to 33 MHz.
Disabled
Disabled
Disabled
Disabled
When writing
Disabled
Disabled
Operable up to 33 MHz (initial value).
Note: • Set to at least the cycle set via FAC1/0.
• Set for writing by default. When performing reads (FLCR WE set to 0), set the wait
cycle to 1 (WTC2, 1, 0=001) to enable reading at the maximum speed.
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Chapter 36 Flash Memory
5.Access Modes
5. Access Modes
This section describes the Flash memory access modes.
5.1 Access from the FR-CPU
The following two types of access mode are available:
■ CPU-ROM mode (32/16/8 bit, read-only)
This mode functions as the CPU’s built-in ROM. Although word (32-bit) length data can be read in a single operation in
this mode, it is not possible to write to Flash or start up an Auto Algorithm.
• Specifying the mode
Set to this mode by setting the “WE” bit of the FLASH Memory Control Status Register to “0”.
Flash memory always goes to this mode after a reset is cleared, when the CPU is running.
Flash memory cannot be put into this mode if the CPU is not running.
• Description of operation
When reading from the Flash memory area, data is read from memory in word (32-bit) length units.
Reading takes two cycles per word (1 wait). This makes it possible to supply commands to the FR-CPU without wait.
■ CPU-Programming mode (16 bit, read/write)
This mode allows data erase/write. Data can only be accessed in lengths of half words (16 bits).
Programs cannot be executed in Flash memory while this mode is enabled.
• Specifying the mode
Set to this mode by setting the “WE” bit of the FLASH Memory Control Status Register (FLCR) to “1”.
After a reset is cleared while the CPU is running, the “WE” bit is set to “0”. Write “1” to this bit in order to switch to this mode.
Flash memory will return to ROM mode if “0” is written to the “WE” bit again, or if it is set to “0” via a reset.
The “WE” bit cannot be overwritten while the "RDY" bit of the FLASH Memory Control Status Register (FLCR) is set to “0”.
Make sure the “RDY” bit is set to “1” before overwriting the “WE” bit.
• Description of operation
When reading from the Flash memory area, data is read from memory in half-word (16-bit) length units.
Reading takes four cycles per half word (3 waits).
Auto Algorithms can be run by writing commands to Flash memory. It is possible to erase/write to Flash memory by running an
Auto Algorithm. See “6. Auto Algorithms (Page No.493)” for details about Auto Algorithms.
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Chapter 36 Flash Memory
5.Access Modes
5.2 Flash Memory Mode
Resetting after setting the MD2, 1, and 0 pins to “1”, “1”, and “1” will halt CPU functioning. At this time, the Flash
memory's interface circuit functions to enable direct control of the Flash memory unit from external pins, by directly
linking some of the signals of ports 2 through B to the Flash memory unit's control signal. In this mode, the Flash
memory appears to the external pins as a stand-alone unit. This mode is generally set when writing/erasing using the
Flash memory writer. In this mode, all operations of the 2 Mbit Flash memory's Auto Algorithms are available.
Table 5-1 Correspondence between MBM29LV400TC and Flash Memory Control Signal
MBM29LV400TC
External pins
492
FR-CPU mode
RESET
INIT
RY/BY
None
BYTE
WE
OE
CE
A16 to A10
A9
A8 to A0
A-1
DQ15 to DQ8
DQ7 to DQ0
Internally fixed to “H”
MB91F233/L external control pins
Flash memory mode
Normal operation
VID application pin
INIT
RY/BY
BYTEX
WEX
Internal control signal
OEX
+ control via interface circuit
CEX
A17 to A11
A10
Internal address bus
A9 to A1
A0
None
Internal data bus
D7 to D0
MD1
MD2
MD0
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Chapter 36 Flash Memory
6.Auto Algorithms
6. Auto Algorithms
Writes and erases to Flash memory are performed by launching the Flash memory's own Auto Algorithms.
6.1 Command Operation
Auto Algorithms are launched by writing one to six half words (16 bits) to the Flash memory in succession. This is called
a “command.” Writing an illegal address or data, or writing them in the incorrect order, will reset the Flash memory to
read mode.
Table 6-1 List of Commands
Bus
Write
Cycle
Command
Sequence
1st Bus
Write cycle
Address
Data
2nd Bus
Write cycle
Address
Data
4th Bus
Read/write
cycle
3rd Bus
Write cycle
Address
Data
Address
Data
5th Bus
Write cycle
Address
Data
6th Bus
Write cycle
Address
Data
Read/
reset
1
XXXXH
F0H
---
---
---
---
---
---
---
---
---
---
Read/
Reset
4
D5557H
AAH
CAAABH
55H
D5557H
F0H
RA
RD
---
---
---
---
Writing
4
D5557H
AAH
CAAABH
55H
D5557H
A0H
PA
PD
---
---
---
---
Chip erase
6
D5557H
AAH
CAAABH
55H
D5557H
80H
D5557H
AAH
CAAABH
55H
D5557H
10H
Sector erase
6
D5557H
AAH
CAAABH
55H
D5557H
80H
D5557H
AAH
CAAABH
55H
SA
30H
Sector erase suspend
Suspend erase during sector erase with input of Address= “XXXXH”, data = “B0H”
Sector erase resume
Resume erase after Sector erase suspend, with input of Address= “XXXXH”, data = “30H”
Auto Select
3
D5557H
AAH
CAAABH
55H
D5557H
90H
---
---
---
---
---
---
Continuous
mode
3
D5557H
AAH
CAAABH
55H
D5557H
20H
---
---
---
---
---
---
Continuous
writing
2
XXXXH
A0H
PA
PD
---
---
---
---
---
---
---
---
Continuous
mode
Reset
2
XXXXH
90H
XXXXH
F0H
or
00H
---
---
---
---
---
---
---
---
Both word mode and half-word mode are the same for commands. Any data can be set in the non-specified bits.
RA: Read address
PA: Write address
SA: Sector address (Specify any address in the sector)
RD: Read data
PD: Write data
• Auto Algorithm Execution Status
If an Auto Algorithm is started in CPU-Programming mode, it is possible to learn the operational state of the Auto
Algorithm via the internal ready signal (RDY). The level of the ready signal can be read from the “RDY” bit of the
FLASH Memory Control Status Register.
While the “RDY” bit is set to “0”, data read is the hardware sequence flag indicating Flash memory status (see
Hardware sequence flag in (3) and (4)).
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Chapter 36 Flash Memory
6.Auto Algorithms
6.2 Auto Algorithm Commands
■ Read/reset command
Issue a Read/reset command sequence to recover to read mode after a timing limit has been exceeded. Data is read from
Flash memory via the read cycle. Flash memory stays in a read state until another command is input.
When powered up, Flash memory is automatically set to read/reset. In this case, commands are not required for data
reading.
■ Program (write)
In CPU programming mode, writes are performed in basic units of half words. Writes are performed in 4 bus operations.
The command sequence as two “unlock” cycles, followed by a write setup command and write data cycle. Then, in the
final write cycle, writing to memory starts.
After the auto write algorithm command sequence is executed, Flash memory no longer requires external control. Flash
memory generates appropriate write pulses that it has automatically created internally, and validates the margins of
written cells. Auto write operation ends when the bit 7 data matches the data written to this bit via data polling (see (3)
Hardware sequence flag). Flash memory then returns to read mode, and no longer accepts write addresses. As a result, at
this time Flash memory requests the next valid address. Thus, data polling indicates that writing is ongoing.
During writing, all commands written to Flash memory are ignored. If a hardware reset is started during writing, the data
in addresses that have been written is not guaranteed. Data can be written to addresses in any order, and may also cross
sector boundaries. Writing cannot return data “0” to data “1”. If data “1” is written to data “0”, then either the data polling
algorithm will determine that the device is bad, or it will appear that data “1” has been written, but in reset/read mode,
when the data is read, it will still be read as “0”. Only erase operation can change “0” data to “1” data.
Figure 6-1 The Writing Sequence Using Write Commands
Start write
Write command sequence
Device data polling
Next address
No
Last address?
YES
Write finished
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Chapter 36 Flash Memory
6.Auto Algorithms
■ Chip erase
Chip erase (erase all sectors at once) is performed via six accesses. First, there are two “unlock” cycles, after which a
setup command is written. This is then followed by two more “unlock” commands before the chip erase command.
The user does not have to write to Flash memory before a chip erase can be performed. While the auto erase algorithm is
executing, Flash memory automatically validates each cell before erasing it by writing a “0” pattern (preprogram). During
this operation, the Flash memory does not require external control.
Auto erase begins with a write during the command sequence, and ends when “1” is written to bit 7, at which point the
Flash memory returns to read mode. The time for chip erase is equal to [sector erase time] x [number of sectors] + [chip
write time (preprogram)].
The figure below shows the chip erase sequence using the chip erase command.
■ Sector erase
Sector erase is performed via six accesses. There are two “unlock” cycles, after which a “setup” command is written,
followed by another two “unlock” cycles. On the sixth cycle, a sector erase command is input, starting the sector erase.
From the time that the last sector-erase command is written until the timeout of 50µs, the next sector-erase command will
be accepted.
It is possible to submit multiple sector erases simultaneously by writing the six bus cycles described above. This sequence
is performed by writing the addresses of sectors to erase in succession after the sector-erase command (30H). After a
timeout of 50µs since the last sector-erase command was written, sector erase begins. In other words, to erase multiple
sectors simultaneously, each sector must be entered within 50µs of the other, after which commands may no longer be
accepted. It is possible to monitor whether successive sector-erase commands are valid via bit 3 (see (3) Hardware
sequence flag). After finishing, Flash memory returns to read mode. Other commands are ignored. Data polling works on
any address in an erased sector. The time for multiple-sector erase is equal to ([sector erase time] + [sector write time
(preprogram)]) x [number of sectors erased].
Figure 6-2 Chip Erase Sequence Using the Chip erase Command
Start erase
Chip/sector
/ erase
command sequence
Device data polling or
toggle bit complete
Write finished
■ Erase suspend
The erase suspend command allows the user to pause the Flash memory’s Auto Algorithm during sector erase, and read
data from/write data to sectors not being erased. This command is only valid during sector erase. It is ignored during chip
erase and write operations. The erase suspend command (B0H) is only valid during sector-erase operation, including the
timeout period after a sector-erase command (30H). Entering this command during the timeout period immediately ends
the timeout, and interrupts the erase operation. When the erase resume command is written, the erase operation resumes.
Any address can be used for erase suspend and erase resume command input.
If a erase suspend command is input during sector-erase operation, it will take up to 20µs for the Flash memory to halt the
erase operation. When the Flash memory goes into erase suspend mode, it outputs ready/busy and bit 7 outputs “1”, and
bit-6 toggling is halted. It is possible to confirm whether the erase operation has halted, by entering the address of an
erased sector, and monitoring the values read from bits 6 and 7. Additionally, writes of erase-suspend commands are
ignored. When erasing is halted, the Flash memory goes into erase-suspend read mode. In this mode, data reads from
sectors where erase has not been paused are enabled, but for other sectors, it is the same as standard reading. While in
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Chapter 36 Flash Memory
6.Auto Algorithms
erase-suspend read mode, when data is read sequentially from an erase-suspended sector, bit 2 is toggled (see (3)
Hardware sequence flag for details).
After entering erase-suspend read mode, the user can write to the Flash memory by writing a write command sequence.
This mode is called “erase-suspend write mode”. In this mode, data writes to sectors where erase has not been paused are
enabled, but for other sectors, it is the same as normal byte writing. While in erase-suspend write mode, when data is read
sequentially from an erase-suspended sector, bit 2 is toggled. This mode can be detected via the erase-suspend bit (bit 6).
A word of caution is required for using this mode: Although bit 6 can be read from any address, bit 7 must be read from a
write address. To resume sector erase, a resume command must be entered (30H). At this point, further resume commands
will be ignored. Conversely, it is possible to enter a erase-suspend command after the Flash memory resumes erasing.
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Chapter 36 Flash Memory
6.Auto Algorithms
6.3 Hardware Sequence Flag
This Flash memory performs the write/erase sequence via Auto Algorithms. It thus has hardware for informing the
outside world when it has finished internal operations.
Hardware sequence flag
The hardware sequence flag can be obtained as data by reading any address (an odd address during byte access) from the
Flash memory while an Auto Algorithm is executing. Five of the retrieved bits of data are valid, each indicating the status
of its corresponding Auto Algorithm.
Figure 6-3 Hardware Sequence Flag Format
bit 15
When reading from hardware
8 7
Hardware sequence flag
(Indeterminate)
bit
7
bit
0
Hardware sequence flag
When reading from byte (Odd address only)
During
half-word
byte access
0
7
6
5
DPOLL TOGGLE TLOVER
4
(Indeterminate)
3
2
SETIMR TOGGL2
1
0
(Indeterminate) (Indeterminate)
Note that these flags are meaningless in FR-CPU ROM mode. Read this data as a half-word or byte, and only in FR-CPU
programming mode.
Table 6-2 List of Hardware Sequence Flag States
DPOLL
(Bit 7)
Auto write
Inverted data
Write/erase during auto-erase 0
Read (sectors being
Executing
1
erased)
Erase Read (sectors not
Data
suspended
being erased)
(paused)
Write (sectors not
Inverted data
being erased)
Time
Auto write
Inverted data
limit
Write/erase during auto-erase 0
exceeded
Status
TOGGLE
(Bit 6)
Toggles
Toggles
TLOVER
(Bit 5)
SETIMR
(Bit 3)
TOGGL2
(Bit 2)
0
0
0
1
1
Toggles
1
0
0
Toggles
Data
Data
Data
Data
Toggles
0
0
1 (*1)
Toggles
1
0
1
Toggles
1
1
(*2)
*1: During erase-suspend write mode, when an address that has been written to is read, bit 2 outputs logical
“1”.
When data is read sequentially from an erase-suspended sector, however, bit 2 is toggled.
*2: When bit 5 is set to “1” (time limit exceeded), sequential reads of sectors being written to/erased toggle
bit 2, while reads from other sectors will not toggle bit 2.
• Ready/busy signal (RDY/BUSYX)
In addition to the hardware sequence flag, the Flash memory has a ready/busy signal for indicating whether an
internal Auto Algorithm is executing. This ready/busy signal can be connected to the Flash memory interface circuit,
and read as the “RDY” bit of the FLASH Memory Control Status Register. Additionally, by starting up the ready/busy
signal, it is possible to issue interrupt requests to the CPU
(See “4. Registers (Page No.489)” for more information).
Value “0” read from “RDY” bit: Flash memory is currently writing or erasing. At this time, write and
erase commands are not accepted.
Value “1” read from “RDY” bit: Flash memory is currently on standby for read/write or erase.
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Chapter 36 Flash Memory
6.Auto Algorithms
6.4 FLCR: Hardware Sequence Flag
• FLCR: Address. Any address in Flash memory. (Access: Byte or half-word)
7
DPOLL
R
6
TOGGLE
R
5
TLOVER
R
4
RX
3
SETIMR
R
2
TOGGL2
R
1
RX
0
RX
bit
Initial value
Attribute
• bit 7: Data polling (DPOLL)
• Auto write under way
If data is read while the auto write algorithm is executing, the Flash memory outputs the data with the last value
written to bit 7 inverted. If a read access is performed after the auto-write algorithm finishes, the Flash memory
outputs the bit 7 of the address indicated by the address signal for the read data.
• Auto erase under way
If a read is performed while the auto-erase algorithm is executing, the Flash memory outputs “0”, regardless of the
address indicated by the address signal. Similarly, upon termination it outputs “1”.
• Sector erase suspend mode
If a read is performed while in sector erase suspend mode, the Flash memory outputs “1” if the address indicated by
the address signal belongs to a sector being erased. If it does not belong to the sector being erased, bit 7 of the value
read from the address indicated by the address signal is output. Referring to this value while toggling bit 6
(described below) makes it possible to determine whether the current sector is in sector erase-suspend state, and
which sectors are being erased.
• Note that when the operation of an Auto Algorithm approaches termination, the value of bit 7 (data polling) changes
asynchronously. This means that Flash memory sends the operating status to bit 7, then sends this data next. When
the Flash memory terminates the Auto Algorithm, and also when it outputs data set in bit 7, the other bits are still
undefined.
• The defined data for other bits can be read by successfully executing reads.
• bit 6: Toggle bit (TOGGLE)
• Auto write/erase under way
If successive reads are performed while the auto-write or erase algorithm is executing, the Flash memory outputs
the result of toggling between “1” and “0” to bit 6. After the auto write or erase algorithm terminates, bit 6 stops
toggling in response to successive reads, and outputs valid data.
The toggle bit becomes effective after the final write cycle of the command sequence in question.
Note that when writing, if an attempt is made to write to an overwrite-protected sector, toggling is performed for
about 2µs, after which toggling ends; the data is not overwritten. When erasing, if all selected sectors are writeprotected, the toggle bit toggles for about 100µs, the returns to read mode; the data is not overwritten.
• Sector erase suspend mode
If a read is performed while in sector erase suspend mode, the Flash memory outputs “1” if the address indicated by
the address signal belongs to a sector being erased. If it does not belong to the sector being erased, bit 6 of the value
read from the address indicated by the address signal is output.
• bit 5: Timing limit exceeded (TLOVER)
• Auto write/erase under way
Bit 5 indicates that the Auto Algorithm has exceeded the length of time stipulated internally by the Flash memory
(internal pulse count). In this state, bit 5 outputs “1”. In other words, if this flag outputs “1” while an Auto
Algorithm is running, it means that the write or erase has failed.
Attempts to write to bit 5, or an unerased non-flag area, will fail. When this happens, it will not be possible to read
set data from bit 7 (data polling), and bit 6 (toggle bit) will remain toggled. If the time limit is exceeded while in
this state, bit 5 outputs “1”. Note that this means that the Flash memory was not used properly; it does not mean that
something is wrong with the Flash memory. If the Flash memory reaches this state, execute the reset command.
• bit 4: Undefined:
The read value is indeterminate.
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Chapter 36 Flash Memory
6.Auto Algorithms
• bit 3: Sector erase timer (SETIMR)
• During sector erase
After executing the first sector-erase command sequence, Flash memory goes into standby for sector erase. During
this time, bit 3 is “0”. After the sector-erase wait period ends, it outputs “1”. The data-polling and toggle bits
become enabled after the first sector-erase command sequence is executed.
If the data-polling and toggle-bit functions set this flag to “1” while the erase algorithm is executing, it indicates that
internally controlled erasing has begun. Until the data-polling or toggle bit indicates that the erase is finished,
subsequent command writes are ignored (only the erase-suspend code is accepted). If this flag is “0”, the Flash
memory will accept additional sector erase-code writes. It is recommended that you check this flag via the software
before writing subsequent sector-erase codes, in order to confirm this. If the flag is “1” on the second status check,
it is possible that additional sector-erase codes will not be accepted. If a read is performed while in sector erase
suspend mode, the Flash memory outputs “1” if the address indicated by the address signal belongs to an erased
sector. If it does not belong to an erased sector, bit 3 of the value read from the address indicated by the address
signal is output.
• bit 2: Toggle bit 2 (TOGGL2)
• During sector erase
This toggle bit is used in addition to the bit-6 toggle bit, in order to detect whether the Flash memory is performing
auto erase, or erase is suspended. Bit 2 toggles if data is read repeatedly from an erased sector during auto erase. If
Flash memory is in erase-suspend read mode, bit 2 will toggle if data is read repeatedly from a sector for which
erase is suspended.
If Flash memory is in erase-suspend write mode, “1” will be read from bit 2 if addresses are read repeatedly from a
sector for which erase is not suspended. Unlike bit 2, bit 6 only toggles during normal writing and erasing, and
erase-suspend write mode.
For example, bits 2 and 6 are used together in order to detect erase-suspend read mode (bit 2 toggles, but bit 6 does
not). Bit 2 is also used to detect erased sectors. When Flash memory is performing erase operation, this bit toggles if
data is read from an erased sector.
• bit 1-0: Undefined
The read value is indeterminate.
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Chapter 36 Flash Memory
6.Auto Algorithms
6.5 Sample Use of Hardware Sequence Flag
It is possible to determine the state of the Flash memory’s internal Auto Algorithms using the hardware sequence flag
mentioned above. As an example, the figures below show the write/erase determination sequence when the data-polling
function is used, and when the toggle-bit function is used.
Figure 6-4 Write/erase Determination Sequence Using Data-polling Function
Start write/erase
VA = write address
= Erased sector address during
sector erase
= Non-protected sector address
during chip erase
* : Since D7 changes at the same time
as D5, even if D5 = "1", D7 must
be rechecked.
Read (D0 to D7)
address = VA
YES
D7 = Data?
NO
NO
D5 = 1?
YES
Read (D0 to D7)
address = VA
YES
D7 = Data?
*
NO
Write/erase Pass
Write/erase Fail
Figure 6-5 Write/erase Determination Sequence Using Toggle-bit Function
Start write/erase
Read (D0 to D7)
address = "H" or "L"
D6 = Toggle?
NO
YES
NO
D5=1 ?
YES
Read (D0 to D7)
address = "H" or "L"
D6 = Toggle?
*
NO
YES
Write/erase Fail
Write/erase Pass
* When D5 changes to "1", D6 stops toggling, so even if
D5 = "1", D6 must be rechecked.
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Chapter 36 Flash Memory
7.Sector Protection
7. Sector Protection
This Flash memory has a sector-protection function that protects from illegal writes/erases at the sector level. Once a
sector has been protected, that setting is permanent as long as the device is not broken. It is, however, possible to release
the protection temporarily and perform write/erase. These actions are performed via sector-protection operations.
Sector-protection operations do not have Auto Algorithms for writing or erasing. They also do not support normal mode;
they can only be used in Flash memory mode.
Thus, they should chiefly be used via external-pin control using a Flash memory writer.
7.1 List of Sector Protection Operations
There are three different sector protection operations.
• Enable sector protection
• Verify sector protection
• Temporary sector-protection release
Table 7-1 Pin Settings
Operation
Enable
Sector Protection
Verify
Sector Protection
Temporary Sector
Protection Release
CEX OEX WEX
A1
A2
A7
L
H
L
L
H
L
L
L
H
L
H
L
-
-
-
-
-
-
A17 to
A13
Sector
Address
Sector
Address
-
D0 to D15 RSTX MD2
MD1
MD0
-
H
VID
H
VID
Code
Output *
H
H
H
VID
-
H
H
VID
H
*: When sector protection is active, 01H is output; when it is inactive, 00H is output.
7.2 Enable Sector Protection
Enable sector protection writes to the Flash memory's internal protection circuit.
This operation can disable writing and erasing for any combination of 10 sectors. Note that the MB91F233/L ships with
protection off for all sectors. In order to perform this operation, it is first necessary to set the addresses of the sectors to be
protected (A17, A16, A15, A14, A13) in the address signal.
The table shows the correspondence between sectors and sector addresses.
To write to the protection circuit, apply VID (=12 V) to MD2 and MD0, then after setting CEX= “0”, start with a falling
WEX pulse, and end with a rising WEX pulse. Note that the sector addresses must be kept between the WEX pulses.
Once sector protection has been set, it cannot be undone. Writes/erases are disabled for protected sectors.
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Chapter 36 Flash Memory
7.Sector Protection
7.3 Verify Sector Protection
Verify sector protection verifies the Flash memory's internal protection circuit. For this operation, first set CEX and OEX
to “0”, then apply VID to MD0 with WEX left at “1” (margin mode). Performing a read with the address signal set to a
given address and the following conditions met: (A7, A2, A1) = (0, 1, 0), protected sectors output “1” to output DQ0. For
unprotected sectors, 00H is read.
Figure 7-1 Sector Protection Algorithm Using Enable Sector Protection and Verify Sector Protection
Start
Sector address setup
A17 to A13
PLSCNT=1
MD2=MD0=VID, MD1=H
A1=CEX=WEX=L
OEX=RSTX=H
WEX pulse applied
Timeout 100 µs
WEX=MD2=H
CEX=OEX=L
(MD0 stays VID)
Read sector address SA
(Address = SA, A1=L,
A2=H, A7=L)
NO
Data = 01h?
YES
NO
PLSCNT=50 ?
YES
Release MD0 VID
Write reset command
Fail
Protect
other sectors?
NO
Release MD0 VID
Write reset command
Sector protection
complete
502
YES
Chapter 36 Flash Memory
7.Sector Protection
7.4 Temporary Sector-protection Release
As long as the device is functional, sectors protected via enable sector protection cannot be written to or erased. However,
it is possible to temporarily lift the sector protection setting via the temporary sector-protection release operation. This
operation is performed by continually applying VID to MD1. During this time, any sector-protection settings are ignored,
and it is possible to write to/erase all sectors. When MD1 is returned to “1” (=3.3 V), this operation is turned off, and
previous protection settings are restored for all sectors.
Figure 7-2 The Temporary Sector-protection Release Algorithm
Start
MD1=VID
(*1)
Execute erase/write
MD1=H
Finish sector
(*2)
protection release
(*1): Unprotect all protected sectors
(*2): Previously protected sectors are protected again.
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Chapter 36 Flash Memory
8.Caution
8. Caution
• Please review the MBM29LV400TC data sheet in conjunction with this document.
• FLASH Memory Control Status Register
When overwriting the FLASH Memory Control Status Register FLCR write control bit (WE), and burn-in ROM
authorization bit (BIRE), always execute the sequence below on the FBUS-RAM (built in RAM on the CPU).
Additionally, when overwriting the FLASH Memory Control Status Register FLCR, do not perform DMA operations
(not installed on the MB91230 series), or interrupt or standby operations.
Command sequence:
1:
NOP
2:
NOP
3:
NOP
4:
NOP
5:
NOP
6:
MUL
R2,R3
//32-bit dummy multiplication
7:
STB
R11,@R12 //Overwrite register
8:
MUL R2,R3 //32-bit dummy multiplication
9:
NOP
• CPU-ROM mode
When in CPU-ROM mode, the endianness of the address-allocation method is different than when writing via a ROM
writer. It is also not possible to write Flash memory commands/data.
• CPU- programming mode
When in CPU- programming mode, the endianness of the address-allocation method is different than when writing via
a ROM writer.
In this mode, reading data in lengths of words (32 bits) is prohibited.
When switching to programming access mode, overwrite the WE bit in accordance with “b. FLASH Memory Control
Status Register”.
• Flash memory mode (writing via ROM writer)
This Flash memory allows writing via an external device, by means of the ROM writer. In this state, pin functions
equivalent to the stand-alone product MBM29LV400TC are assigned to the device's external pins, and operation of the
CPU halts.
In Flash memory mode, the address line connections are changed from CPU mode, to mapping within the memory area.
• See the section in your ROM writer manual concerning the MBM29LV400TC or MB91230 for details about using
Flash memory from a ROM writer.
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Chapter 37 Flash On-Board Serial Writing
1.Overview
Chapter 37 Flash On-Board Serial Writing
This chapter describes Fujitsu standard on-board serial writing for MB91F233/MB91F233L built-in flash memory.
1. Overview
Fujitsu standard on-board serial writing uses the Yokogawa Digital Computer AF220/AF210/AF120/AF110 Flash
microcomputer programmer.
Below is described the (Fujitsu standard) on-board serial writing connection when using the Yokogawa Digital Computer
AF220/AF210/AF120/AF110 Flash microcomputer programmer.
2. Features
Setting up the simple circuit configuration on the system as shown in the sample serial-writing connection enables onboard writing to the built-in Flash memory from the Flash microcomputer programmer.
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Chapter 37 Flash On-Board Serial Writing
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Basic configuration for MB91F233 / MB91F233L serial-writing connection
Host interface cable
Standard interface cable (AZ210)
RS232C
AF220/AF210/
AF120/AF110 CLK dynamic serial
MB91F233
Flash
User system
microcomputer
programmer +
Memory card
Can operate as stand-alone device
Please contact Yokogawa Digital Computer for details about the AF220/AF210/AF120/AF110 Flash microcomputer
programmer's functions, operating instructions, and standard interface cable (AZ210) and connectors.
4. Pin Description
Table 4-1 Functions of Pins Used for Fujitsu Standard On-board Serial Writing
MCU pin
Functions
MD2, MD1,
MD0
Mode pin
P10, P11
INIT
SIN0
SOT0
SCK0
Writer program startup pin
Reset pin
Serial data input pin
Serial data output pin
Serial clock input pin
VCC
Power supply voltage pin
VSS
GND pin
Details
Sets to write mode.
Flash serial write mode: MD2, MD1, MD0=1, 0, 0
Reference:
Single chip mode: MD2, MD1, MD0=0, 0, 0
Pin setting during Flash serial overwrite: P10=0, P11=1
Uses UART channel 0 resource as clock synchronous mode.
Supply write voltage from the user system.
Ensure that voltage does not short-circuit with user-side power supply
upon connection.
Set the GND to the same as the Flash microcomputer programmer.
If the user system is also using the P10, P11, SIN0, SOT0, and SCK0 pins,
the following control circuit is needed:
(You can use the Flash microcomputer programmer's /TICS signal to detach the user circuit while performing serial
writing. Make sure that the user power is off for the connection with the AF220/AF210/AF120/AF110.)
Figure 4-1 Control Circuit when Using User System
AF220/AF210/
AF120/AF110
Write control pin
10kΩ
AF220/AF210/
AF120/AF110/
TICS pin
506
MB91F233
Write control pin
User
Chapter 37 Flash On-Board Serial Writing
5.Sample Serial Write Connection
5. Sample Serial Write Connection
Figure 5-1 Sample MB91F233 / MB91F233L Serial-writing Connection
User system
Flash microcomputer
programmer
TAUX3
Connector DX10-28S
(19)
MB91F233/MB91F233L
Serial overwrite 1
Serial overwrite 0
10 kΩ
TMODE
MD2
87
MD1
88
MD0
89
P10
103
P11
104
90
10 kΩ
(12) Serial overwrite 0
10 kΩ
User circuit
Serial overwrite 0
WDT
(18) Serial overwrite 1
10 kΩ
/TICS
(10)
/TRES
(5)
INIT
TTXD
(13)
(27)
SIN0 95
SOT0 96
(6)
SCK0 97
TRXD
TCK
User circuit
Vcc3
(15,17,36,
37,48)
Vcc*
(75,105)
Vss
(16,38,47,
76,106)
User power (3.0V)
TVcc
GND
(2)
User power (5.0V)
(14,15,
1,28)
14 Pin
1 Pin
DX10-28S
Pins 3, 4, 9, 11, 16, 17,
18, 20, 23, 24, 25, and
26 OPEN
DX10-28S: Right-angle type
28 Pin
15 Pin
Connector (manufactured by Hirose) pin layout
:10 kΩ pullup
*: Vcc value of MB91F233L : 3V
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Chapter 37 Flash On-Board Serial Writing
6.Flash Microcomputer Programmer System Configuration
6. Flash Microcomputer Programmer System Configuration
This is the Flash microcomputer programmer system configuration.
Direct inquiries regarding the system configuration of the AF220/AF210/AF120/AF110 (Yokogawa Digital Computer
Corporation) to the contact shown below:
Model
AF220
/AC4P
AF210
/AC4P
Functions
Ethernet interface model/100 to 220V power adapter
Standard model
/100V to 220V power adapter
Main
Single-key Ethernet interface model
unit AF120
/AC4P
/100 to 220V power adapter
AF110
/AC4P
Single-key model
/100V to 220V power adapter
AZ221
Dedicated writer PC-AT RS-232C cable
AZ210
Standard target probe (a) Length: 1 m
FF201
Fujitsu FR Flash microcomputer control module
AZ290
Remote controller
/P2
2 MB PC Card (Option) Flesh memory capacity: 128 KB max
/P4
4 MB PC Card (Option) Flesh memory capacity: 512 KB max
/P5
4 MB PC Card (Option) Flesh memory capacity: 768 KB max/DOS: 3 MB
/E6
4 MB PC Card (Option) Flesh memory capacity: 2 MB max/DOS: 1.5 MB
/P8
8 MB PC Card (Option) Flesh memory capacity: 1 MB max/DOS: 6.8 MB
Direct inquiries to Devices Division, Yokogawa Digital Computer Corporation.
7. Caution
Precautions for making MB91F233 / MB91F233L serial-writing connection
• Source oscillation clock frequency
A source-oscillation clock of between 4.0 and 12.0 MHz can be used when writing to Flash memory.
• Port status when writing to Flash memory
With the exception of the pin used for writing, the port status when writing to Flash memory using a serial writer is
the same as reset status.
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Chapter 38 FUJITSU FLASH MCU Programmer
1.Overview
Chapter 38 FUJITSU FLASH MCU Programmer
This chapter describes the Fujitsu on-board overwrite software for writing to the MB91F233/MB91F233L (built-in flash
memory).
1. Overview
Using the FUJITSU FLASH MCU programmer for FR onboard overwrite software, it is possible to overwrite the flash
memory in the onboard microcontroller of the FLASH implemented on the user system, from a (Windows) PC.
Note that this requires an RS-232C driver to be installed on the user system, and for communication with the
microcontroller's UART to be enabled.
PC(Windows)
“FUJITSU FLASH MCU programmer for FR
RS-232C driver
User system
RS232C
Communications via UART
MB91F233/MB91F233L
2. Features
Setting up the simple circuit configuration on the system as shown in the sample onboard overwrite connection enables
onboard overwrite of the MCU’s onboard Flash memory from the PC via an RS-232C cable, using Fujitsu's onboard
overwrite software.
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Chapter 38 FUJITSU FLASH MCU Programmer
3.Pin Description
3. Pin Description
Table 3-1 Pins Used for Onboard Overwriting
Pin
510
Functions
Details
MD2, MD1,
MD0
Mode pin
Control during flash overwrite.
Set MD2=‘H’, MD1=MD0=‘L’ to go to Flash overwrite
mode.
P10, P11
Writer program startup pin
When in Flash overwrite mode, set to P10=P11=‘L’.
INIT
Reset pin
SIN0
Serial data input pin
Set the MD2, MD1, and MD0 pins and the P10 and P11
pins to Flash overwrite mode before releasing the reset.
UART0 is used.
SOT0
Serial data output pin
UART0 is used.
Power supply voltage
Connect 3.3 V to Vcc3, and 5.0 V to Vcc.
Chapter 38 FUJITSU FLASH MCU Programmer
4.Sample Onboard Overwriting Connection
4. Sample Onboard Overwriting Connection
Figure 4-1 Connection Diagram Sample Onboard Overwriting Connection for MB91F233 and MB91F233L
User system
10kΩ
MB91F233 / MB91F233L
1
Serial overwrite 1
MD2
0
Serial overwrite 0
1
MD1
0
1
MD0
Serial overwrite 0
0
10
10kΩ
1
Serial overwrite 0
P00, P01
Writer program
startup pin
0
User circuit
Oscillator
RS232C
driver
INIT
SIN0
SOT0
Communications via UART
RS232C
The MD2, MD1, and MD0 pins and the P00 and P01 pins (Writer program startup pins) cannot be controlled from the
PC. Thus, they should be set on the user system. During serial overwriting, after setting the MD2, MD1, and MD0 pins
and the P00 and P01 pins, change INIT from “L” to “H” to switch to serial overwrite mode. Thus, it is possible to
perform serial overwriting from the PC.
After finishing serial overwriting, set the MD2, MD1, and MD0 pins to the normal mode in which they are used, and the
P00 and P01 pins to the user-circuit side; then set INIT from “L” to “H” to execute a user program.
Recommended If you plan to perform mass-production writing in the future using a Yokogawa Digital Computer serial
programmer, then we recommend you pull the serial clock pin pattern onto the pcb, making reference to the sample serial
writing connection in the hardware manual in question.
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Chapter 38 FUJITSU FLASH MCU Programmer
5.Pin Timing Charts
5. Pin Timing Charts
Perform input on each of the microcontroller pins as follows, based on the INIT pin input.
H
5t cp
IN IT
L
MD0
H
t cp
L
H
MD1
t cp
L
H
MD2
t cp
L
H
P00,
P01
t cp
t cp
250
L
H
SIN0
t cp
3500 ( min)
Data
L
Minimum setup time and hold time for each signal corresponding to INIT startup:
P00 and P01 indicate writer-program startup pins, and SIN indicates the serial-data input pin.
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Chapter 38 FUJITSU FLASH MCU Programmer
6.Software Installation and Execution
6. Software Installation and Execution
• The installation of the “FUJITSU FLASH MCU programmer for FR” software is described here
If you have previously installed an older version of the software, first uninstall it.
Launch the installer (PCWFRsetup.exe), and complete the installation following the onscreen instructions. Note that the
software may not function if it is installed too deeply in the file hierarchy.
After installation, launch the software by selecting Windows Start => Programs or All Programs => FUJITSU FLASH
MCU Programmer => FR.
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Chapter 38 FUJITSU FLASH MCU Programmer
7.Programmer Functions
7. Programmer Functions
The following actions can be performed on the microcontroller's onboard Flash memory: Erase, Blank Check, Program &
Verify, Read & Compare, and Copy.
• Main dialog box
When the programmer application launches, the dialog box shown below opens.
• Overview of procedures
First, complete the configuration of the user system (microcontroller card) to write to (see “Chapter 3 Basic
Information (Page No.25)”).
When launching the software, and after you have changed the settings, it is first necessary to perform the download
(described below).
If the download was successful, you will next carry out the procedures for erasing, writing, and the like.
7.1 Download procedure
Below are described the download procedure and program behavior.
(1) Under “Target Microcontroller”, specify the type of microcontroller you are using as the user system.
MB91F233
Note: To select a microcontroller, use the up and down arrow keys to select a “Target Microcontroller” item, then
press enter, or use the mouse to drag-select a “Target Microcontroller”.
(2) Under “Crystal Frequency”, specify the frequency of the crystal oscillator input to the microcontroller.
Oscillator frequency (MHz)
2, 4, 8, 16
Note: This program (FUJITSU FLASH MCU programmer for FR) will not operate properly if an oscillator
frequency other than one listed in the table above is used for the microcontroller's base oscillation.
(3)
(4)
514
Specify the COM port of the PC connected to the user system.
Click Set Environment. In the window that appears, click the COM PORT tab. A tab for specifying the COM port
appears. Specify one of the following:
COM1, COM2, COM3, COM4, COM5, COM6, COM7, COM8
Perform download
Click Download. Download begins, and the “Downloading” window appears. Immediately after this, another dialog
opens, as shown in the figure below.
Chapter 38 FUJITSU FLASH MCU Programmer
7.Programmer Functions
When this dialog appears, enter a reset into the microcontroller, start Flash writing mode, then click OK in this
dialog.
Continue with the download. After the download is complete, the message box shown below appears.
Click OK in the message box above. The Erase, Blank Check, Program & Verify, Read & Compare, and Copy
buttons become active.
Note: You can perform the download by selecting the Download button via the Tab key, then clicking Enter, or by
pressing Alt + D.
7.2 Procedure for erasing and writing
Below is described how to specify a Hex File, and the processing/behavior when the Erase, Blank Check, Program &
Verify, Read & Compare, Copy, and Full Operation(D+E+B+P) buttons are clicked.
You can perform each action by typing the underlined letter on each button, while holding down the Alt key (To specify a
Hex File, press Alt + O to specify the Open button).
(1) Hex File: Specify write file
Specify a Motorola S format file to write to the microcontroller's Flash memory. Drag and drop a file directly from
Explorer or the like, or click Open, and specify a file using the Open dialog.
A Hex File is required when executing the Program & Verify, Read & Compare, and Full Operation(D+E+B+P)
commands.
Note: Direct specification of network drives is not supported.
(2)
Erase: Erase the entire Flash memory area.
In order to write a new program to the Flash memory, the entire memory area must first be erased (set to 0xff).
Click Erase to erase the memory. While the action is being performed, the “Erasing” message box appears. When
the operation is complete, a message box will inform you of the results (if the action was successful, “Erase OK!”
appears).
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Chapter 38 FUJITSU FLASH MCU Programmer
7.Programmer Functions
(3)
(4)
Blank Check: Check the entire Flash memory for blanks.
Check whether the entire Flash memory area has been erased (0xff). While the action is being performed, the
“Blank Checking” message box appears. When the operation is complete, a message box will inform you of the
results (if the action was successful, “Blank Check OK!” appears).
Program & Verify: Write to the Flash memory.
Write the Motorola S-format file specified by Hex File to the microcontroller's memory, verifying it at the same time. While the
erase is being performed, the “Programming” message box appears. When the operation is complete, a message box will inform
you of the results (if the action was successful, “Program OK!” appears). You can cancel the write operation by clicking Cancel.
Note: Before performing the write, a temporary file with the BIN extension is created with the same file name and
in the same folder as the Motorola S-format file. If a file of that name already exists, it will be overwritten.
After the write is complete, you can delete the temporary file manually if you like.
(5)
(6)
(7)
Read & Compare: Compare the Hex File with the Flash memory in the microcontroller.
Compare the Motorola S-format file specified by Hex File with the content written to the microcontroller's Flash
memory. As with the Program & Verify command, a temporary file is created before processing starts, after which
the microcontroller's Flash memory is read and compared. While the action is being performed, the “Reading and
Comparing” message box appears. When the operation is complete, a message box will inform you of the results (if
the content is identical, “Read & Compare OK!” appears). You can cancel the memory comparison by clicking
Cancel.
Copy: Save the microcontroller's Flash memory to a file.
Read the data written to the microcontroller's Flash memory, and save it as a Motorola S-format file. Specify a
location and name for the file, and click Save to start the save process. While the action is being performed, the
“Copying” message box appears. When the operation is complete, a message box will inform you of the results (if
the action was successful, “Copy OK!” appears). You can cancel the save operation by clicking Cancel.
Full Operation(D+E+B+P): Auto write.
Perform the operations for Download, Erase, Blank Check, and Program & Verify in a single action. While the
action is being executed, message box appears, and actions are performed/messages displayed in the order shown in
the table below. After all operations have completed successfully, “Full Operation OK!” is displayed.
Action
Create temporary file
Download
Erase
Blank Check
Program & Verify
516
Message
Full Operation – Making binary file
Full Operation – Downloading
Full Operation – Erasing
Full Operation – Blank Checking
Full Operation – Programming
Chapter 38 FUJITSU FLASH MCU Programmer
7.Programmer Functions
7.3 Continuous Write Mode
Continuous write mode is intended to be used to write the same program to multiple chips. Please avoid using this feature
for other purposes. Doing so could cause the no override to the chip, even after you have changed the write file.
When continuous write mode is enabled, temporary write files are no longer updated, which reduces the amount of time
required for the process. If, however, for some reason the contents of the temporary file and specified write file fail to
match, there is a danger that the wrong data will be written, because the program cannot determine whether the files
match.
It is recommended that you obey the following guidelines, in order to ensure safe continuous writing.
(1) After launching the software, perform Full Operation or the like in normal mode at least once, to create/update a
temporary file.
(2) Right click, and from the context menu that appears, select the bottom item (Contiuously Write Mode). This enables
continuous write mode.
(3) Click Full Operation or the like, and write to multiple chips. The temporary file will not be updated at this time, so
the same content is written.
(4) When you are finished, exit the software to ensure that continuous write mode is disabled. At this point, it would be
best to delete the temporary file you created in step 1.
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Chapter 38 FUJITSU FLASH MCU Programmer
8.Caution
8. Caution
Precautions for using the “FUJITSU FLASH MCU Programmer for FR onboard overwrite software”:
• We bear no liability for any problems relating to the use of this software.
• This software is not guaranteed to run on an NEC PC98 series PC.
• This software is not meant to support mass-production writing.
To write during mass production, use a Yokogawa Digital Computer serial programmer.
• There are limitations on the base oscillation frequency that can be input to the microcontroller using this software. See
7.(1).(b) for details.
• Contact the Sunhayato special devices division regarding the board supporting Sunhayato PC serial writers compatible
with the FUJITSU FLASH MCU Programmer for FR.
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Chapter 39 I/O Register Files
1.Overview
Chapter 39 I/O Register Files
1. Overview
Fujitsu Limited offers I/O Register Files in order to allow you to write programs and check sample programs, without
writing a new register header.
You can use an I/O Register File to save the trouble of creating a new register header file.
You can also write the sample programs listed in each chapter based on these I/O Register Files.
See the user's reference (ioregj.txt) for details about I/O Register Files.
2. Configuration
• I/O Register Files available
Included with the Softune V6/FR software tool.
■ Specify the location for the I/O Register Files when installing Softune.
\\{FETOOL}\lib\911\include\sample\mb91230
■ The following I/O Register Files are included:
● I/O register declaration file ( _fr.h )
This file declares variables corresponding to the I/O registers.
Include this file if you write an application that manipulates the I/O register variables.
● MB91230 series I/O register declaration file ( _mb91230.h )
This file declares variables corresponding to the MB91230 series' I/O registers.
● MB91230 series I/O register structure declaration file ( _r91230.h )
This file declares structures (union/struct declarations) corresponding to each of the I/O registers of the MB91230 series.
● I/O register definition files ( *.c )
These files define each of the I/O register variables in the MB91230 series.
● User's reference ( ioregj.txt )
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Chapter 39 I/O Register Files
3.Sample I/O Register Declaration
3. Sample I/O Register Declaration
Content of MB91230 series I/O register file declaration
3.1 I/O Register Variables and Bit-field Members
The file declares the following I/O register variables and bit-field members, corresponding to the I/O register and bit
names described in the hardware manual.
• I/O register variables that can be accessed at the bit and byte/half-word/word level are declared as unions (some are
declared as struct's for access reasons).
• I/O register variables that only support the writing of all bits, or for which bit-level access has no meaning, are declared
as integers.
• As a rule, I/O register variable names are declared with the name of the I/O register, preceded by "IO_" (in some cases,
multiple I/O registers are declared with the same variable name, or the variable names are changed slightly, due to
issues with variable declarations in the C language, or access issues).
• Bit-field members are declared with the corresponding bit names.
(In some cases, multiple bits are declared with the same member name, for access reasons.)
3.2 Declarations
Sample declaration corresponding to I/O register PDR0
• I/O register configuration
7
P07
•
6
P06
5
P05
4
P04
3
O03
2
P02
1
P01
0
P00
bit No.
PDR0
Declaration
union io_pdr0 {
unsigned char byte;
struct {
unsigned char P07:1;
unsigned char P06:1;
unsigned char P05:1;
unsigned char P04:1;
unsigned char P03:1;
unsigned char P02:1;
unsigned char P01:1;
unsigned char P00:1;
} bit;
;
extern __io union io_pdr0 IO_PDR0;
• Sample usage:
Available variable and member names
I/O register name
PDRn
For Byte/Half-word/Word access
IO_PDRn.byte
For bit access
IO_PDRn.bit.Pnx(x:0 - 7)
(n:0-D,F)
Example 1: IO_PDR0.byte = 0x56 ; /* Write “0x56” to register DR0
Example 2: IO_PDR0.bit.P03 = 1 ; /* Set bit 3 of DR0 to “1”. */
520
*/
Chapter 39 I/O Register Files
4.I/O Register File Usage
4. I/O Register File Usage
Usage of MB91230 series I/O register files
(1) Specify the -cpu option for the product you will use. After compiling all I/O register definition files, create a load
module with the corresponding format using the linker.
Example:> fcc911s -cpu mb91*** -c *.c
> flnk911s -cpu mb91*** -r -o io91***.rel *.obj
(2) Include the common I/O register declaration file if you write an application that references the I/O register variables.
Example:#include "_fr.h"
void func(){
.....
IO_TCCS.bit.MODE = 1;
.....
}
(3) Specify the -cpu option of the product you wish to use, and compile an application program.
Example:> fcc911s -cpu mb91*** -c sample.c
Note: If the I/O register file cannot be used with product specified in the CPU option, the following compiler error
will appear:
#error “The I/O register file of the specified CPU option
does not exist”
(4) Specify the -cpu option of the product you wish to use, and link the load module with the corresponding format
created in (1) with the application program object file created in (3).
Example:> flnk911s -cpu mb91*** -o sample.abs io91***.rel sample.obj
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Chapter 39 I/O Register Files
5.Caution
5. Caution
• I/O Register Files Code that performs bit-level access on registers declared in structures at the Half-word (unsigned
short) level will not be converted into bit commands. If you need to use bit commands, write to the structure at the Byte
(unsigned char) level.
The following registers correspond to the I/O Register Files.
• TMCSRn (reload timer)
• ADCSm (A/D converter)
• CCRn (up-down counter)
• OCSn (output compare)
• WTCR (real-time clock)
• PCNn (PPG)
• If you write a program that manipulates the I/O registers using the I/O Register Files, please consult the user's manual
for necessary system-level considerations, such as I/O register access order, timing, and the like.
• The I/O Register Files are sample programs created to help you develop MB91230 series application programs. Strictly
speaking, various modifications may be required depending on your system. Please evaluate this fully before use.
• Fujitsu Limited may bear no liability for any errors in the I/O Register Files, and may not be able to correct any errors
discovered immediately.
• Please check with Fujitsu technical support for the latest versions before using the I/O Register Files.
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CM71-10118-1E
FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL
FR60Lite
32-BIT MICROCONTROLLER
MB90230 Series
User's Manual
April 2004 the first edition
Published
FUJITSU LIMITED
Edited
Business Promotion Dept.
Electronic Devices