FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16307-1E
32-Bit RISC Microcontroller
CMOS
FR Family MB91110 Series
MB91110/MB91V110
■ DESCRIPTION
The MB91110 series is a standard single-chip micro controller featuring various I/O resources and bus control
mechanisms to incorporate the control with required for high performance high-speed CPU processes, having a
32-bit RISC CPU (FR30 series) in its core. Although external bus access is the basis for supporting a large address
space accessible by a 32-bit CPU, a 1-KB instruction cache memory has been built-in to increase the instruction/
execution speed of the CPU.
This unit features the optimal specifications for incorporating applications that require high performance CPU
processing power such as navigation systems, high performance facsimile systems, printer control, etc.
■ FEATURES
FR30CPU
• 32-bit RISC, load / store architecture, 5-level pipeline
• Operating frequency : external 25 MHz, internal 50 MHz
• Multi-purpose register : 32 bits × 16
• 16-bit fixed length instructions (basic instruction) , 1 instruction per cycle
• Instructions for barrel shift, bit processing and inter memory transfers : Instructions suited to loading purposes
• Function entry / exit instruction, multi load / store instruction of register details : Instruction capable of handling
High level language instruction.
• Register Interlock function : Simplification of assembler description
(Continued)
■ PACKAGE
144-pin plastic LQFP
(FPT-144P-M08)
MB91110 Series
(Continued)
• Branch instruction with delay slot : Reduction in overheads in case of branching
• Multiplier is built-in / Supported at instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interruption (saving PC and PS) : 6 cycles, 16 priority levels
Bus Interface
• 24-bit address bus (16 MB space)
• Operating frequency : 25 MHz
• 16- / 8-bit data bus
• Basic external bus cycle : 2 clock cycles
• Chip select output that can be set to a minimum 64-Kbyte units
• Interface support for various memories
DRAM interface (areas 4, 5)
• Automatic waiting cycle : Can be randomly set from 0 to 7 cycles per area
• Unused data and address pins can be used as input/output ports.
• Supports “little endian” mode (One area is selected from areas 1 to 5)
DRAM Interface
• 2-bank individual control (area 4, 5)
• Normal mode / high speed page mode
• Basic bus cycles : normally 5 cycles, 1 cycle access is possible in high-speed page mode.
• Programmable waveform : 1 cycle waiting can be inserted automatically in RAS and CAS.
• DRAM refresh
CBR refresh (Interval is randomly set using the 6-bit timer.)
Self refresh mode
• Supports addresses for 8, 9, 10 and 12 columns
• 2CAS/1WE or 2WE/1CAS can be selected.
Cache Memory
• 1 KB instruction cache
• 2 way set associative
• 32 blocks / way, 4 entries (4 words) / block
• Lock function : Residing in the specified program codes at cache
DMA Controller (DMAC)
• 5 channels
• External → external 2.5 access cycles / transfer (if 2 clock cycles are defined as 1 access cycle)
• Internal → external 1.5 access cycles / transfer (if 2 clock cycles are defined as 1 access cycle)
• Address register (inc, dec, or reload are possible) : 32 bits × 5 channels
• Transfer count register (reload possible) : 16 bits × 5 channels
• Transfer factors : external pin / built-in resources interruption request / software
• Transfer sequence
Step transfer / block transfer
Burst / consecutive transfer
• Transfer data length : 8-bit, 16-bit or 32-bit can be selected
• Suspension is possible using NMI / interruption request
UART
• Fully duplicated double buffer
• Data length : 7 to 9 bits (without parity) , 6 to 8 bits (with parity)
2
MB91110 Series
•
•
•
•
•
•
Asynchronous (start-stop synchronization) or CLK synchronized communication can be selected.
Multiprocessor mode
Dedicated baud rate generator is built-in.
External clock can be used as the transfer clock
Baud rate clock can be output
Error detection : parity, frame, overrun
PPG Timer
• 16 bits, 6 channels (frequency setting register / duty setting register)
• PWM function or one-shot function can be selected
• Initiation : Software or external trigger can be selected
A/D Converter (sequential conversion type)
• 10-bit resolution, 8 channels
• Sequential comparison conversion : 5.6 µs in the case of 25 MHz
• Sample & hold circuit is built-in.
• Conversion mode : Single, scan or repeat conversion can be selected.
• Initiation : Software, external trigger or built-in timer can be selected.
Reloading Timer
• 16-bit timer : 2 channels
• Internal clock : 2 clock cycle resolutions, 2, 8 or 32 cycles can be selected.
• Pin input : event counter input / gate function
• Rectangular wave output
Other Interval Timer
• Watchdog timer : 1 channel
Bit Search Module
• Searches the first “1” / “0” change bit positions within 1 cycle from MSB in 1 word.
Interruption Controller
• External interruption input : Mask impossible interruption (NMI) , normal interruption × 8 (INT0 to INT7)
• Internal interruption factors : UART, DMAC, A/D, reloading timer, PPG timer, delay interruption
• Priority levels are programmable except for mask impossible interruption (16 levels)
Reset Factors
• Power-on reset / hardware standby / watchdog timer / software reset / external reset
Low Power Consumption Mode
• Sleep / stop mode
Clock Control
• Gear functions : Operating clock frequencies peripheral to the CPU can be set randomly and independently.
Gear locks can be selected from 1/1, 1/2, 1/4 or 1/8 (or 1/2, 1/4, 1/8, or 1/16) .
Others
• Package : LQFP-144
• CMOS technology : 0.35 µm
• Power : 5.0 V ± 10%, 3.3 V ± 5%
3
MB91110 Series
■ PRODUCT LINEUP
4
MB91V110
(For evaluation)
MB91110
(I-RAM mounted version)
I-RAM
16 Kbyte
16 Kbyte
RAM
5 Kbyte
5 Kbyte
ROM
I-$
1 Kbyte
1 Kbyte
DSU3
evaluation function
Mounted
MB91110 Series
■ PIN ASSIGNMENT
75
80
85
90
95
100
110
70
115
65
120
60
125
55
130
50
135
45
140
INDEX
35
30
25
20
15
10
5
1
40
NMI
DW1/PB7
CS1H/PB6
CS1L/PB5
RAS1/PB4
VSS
VCC5
DW0/PB3
CS0H/PB2
CS0L/PB1
RAS0/PB0
CLK/PA6
CS5/PA5
CS4/PA4
CS3/PA3
CS2/PA2
CS1/PA1
CS0
VSS
WR1/P85
WR0
RD
BRQ/P82
BGRNT/P81
RDY/P80
VCC3
VCC5
A23/P67
A22/P66
A21/P65
A20/P64
A19/P63
A18/P62
A17/P61
A16/P60
VSS
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
VSS
D24
D25
D26
D27
D28
D29
D30
D31
VCC5
VSS
A00
A01
A02
A03
A04
A05
A06
A07
VSS
A08
A09
A10
A11
A12
A13
A14
A15
PE3/TRG2, 5
PF0/INT0
PF1/INT1
PF2/INT2
PF3/INT3
PF4/INT4
PF5/INT5
PF6/INT6
PF7/INT7
VSS
PG0/DREQ0
PG1/DACK0
PG2/DEOP0
PG3/DREQ1
PG4/DACK1
PG5/DEOP1
VCC5
VCC3
PH0/DREQ2
PH1/DACK2
PH2/DEOP2
PH3/SI
PH4/SO
PH5/SCK
PH6/TI0
PH7/TO0
VSS
PI0/TI1
PI1/TO1
PI2/PPG0
PI3/PPG1
PI4/PPG2
PI5/PPG3
PI6/PPG4
PI7/PPG5
VSS
105
TRG1, 4/PE2
TRG0, 3/PE1
ATG/PE0
VSS
VCC5
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
AVSS
AVRL
AVRH
AVCC
(OPEN)
(OPEN)
(OPEN)
(OPEN)
(OPEN)
(OPEN)
(OPEN)
(OPEN)
(OPEN)
VCC3
HST
RST
VSS
X1
X0
VCC5
MD2
MD1
MD0
(TOP VIEW)
(FPT-144P-M08)
5
MB91110 Series
■ PIN DESCRIPTIONS
Pin no.
Pin name
I/O*
Circuit type
Function
1
2
3
4
5
6
7
8
D16/P20
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27
I/O
C
These pins use bits 16 to 23 of the external data bus.
They can be used as a port (P20 to P27) if the external bus
width is 8 bits.
10
11
12
13
14
15
16
17
D24
D25
D26
D27
D28
D29
D30
D31
I/O
C
These pins use bits 24 to 31 of the external data bus.
20
21
22
23
24
25
26
27
A00
A01
A02
A03
A04
A05
A06
A07
I/O
C
These pins use bits 00 to 07 of the external address bus.
29
30
31
32
33
34
35
36
A08
A09
A10
A11
A12
A13
A14
A15
I/O
C
These pins use bits 08 to 15 of the external address bus.
38
39
40
41
42
43
44
45
A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67
I/O
C
These pins use bits 16 to 23 of the external address bus.
48
RDY/P80
I/O
C
This is for external ready input. “0” is input if the bus cycle being executed is incomplete. It can be used as a port when not
otherwise used.
49
BGRNT/P81
I/O
H
This is the external bus open reception output. “L” is output if
the external bus is opened. It can be used as a port when not
otherwise used.
(Continued)
6
MB91110 Series
Pin no.
Pin name
I/O*
Circuit type
Function
50
BRQ/P82
I/O
C
This is the external bus open request input. “1” is input if the
external bus is to be opened. It can be used as a port when
not otherwise used.
51
RD
O
G
This is the external bus read strobe.
52
WR0
O
G
This is the external bus write strobe.
53
WR1/P85
55
CS0
56
57
58
59
60
CS1/PA1
CS2/PA2
CS3/PA3
CS4/PA4
CS5/PA5
61
CLK/PA6
62
63
64
65
68
69
70
71
RAS0/PB0
CS0L/PB1
CS0H/PB2
DW0/PB3
RAS1/PB4
CS1L/PB5
CS1H/PB6
DW1/PB7
72
I/O
O
H
16-bit bus width
8-bit bus width
D31-24
WR0
WR0
D23-16
WR1
(Port is possible)
G
Chip select 0 output (Low active)
I/O
H
Chip select 1 output (Low active)
Chip select 2 output (Low active)
Chip select 3 output (Low active)
Chip select 4 output (Low active)
Chip select 5 output (Low active)
They can be used as ports when not otherwise used.
I/O
H
This is the system clock output. The same clock as the standard clock is output. This can be used as a port when not otherwise used.
I/O
H
RAS output with DRAM bank 0.
CASL output with DRAM bank 0.
CASH output with DRAM bank 0.
WE output with DRAM bank 0. (Low active)
RAS output with DRAM bank 1.
CASL output with DRAM bank 1.
CASH output with DRAM bank 1.
WE output with DRAM bank 1. (Low active)
They can be used as ports when not otherwise used.
NMI
I
E
Non Maskable Interrupt (NMI) input. (Low active)
73
74
75
MD0
MD1
MD2
I
I
These are mode pins from 0 to 2.
Basic MCU operation modes are set using these pins.
They should be connected directly to VCC or VSS for use.
77
78
X0
X1
I
O
A
Clock (oscillation) input.
Clock (oscillation) output.
80
RST
I
B
This is the external reset input. (Low active)
81
HST
I
E
This is the hardware standby input. (Low active)
83
(OPEN)
Set this to OPEN.
84
85
86
(OPEN)
(OPEN)
(OPEN)
Set this to OPEN.
(Continued)
7
MB91110 Series
Pin no.
Pin name
I/O*
Circuit type
87
88
89
90
(OPEN)
(OPEN)
(OPEN)
(OPEN)
Set this to OPEN.
91
(OPEN)
Set this to OPEN.
92
AVCC
VCC power supply for the A/D converter.
93
AVRH
A/D converter reference voltage (high potential side).
Be sure to turn on/off this pin with potential higher than AVRH
applied to VCC.
94
AVRL
A/D converter reference voltage (low potential side).
95
AVSS
VSS power supply for the A/D converter.
96
97
98
99
100
101
102
103
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
I
D
[AN0 to 7] A/D converter analog input.
106
ATG/PE0
I/O
H
Function
[ATG] This is the external trigger input for the A/D converter.
This function is always used if selected as the initiation factor
for A/D, so output by other functions should be stopped except when it is carried out intentionally.
[PE0] This is a general-purpose input/output port.
107
108
109
TRG0, 3/PE1
TRG1, 4/PE2
TRG2, 5/PE3
110
111
112
113
114
115
116
117
INT0/PF0
INT1/PF1
INT2/PF2
INT3/PF3
INT4/PF4
INT5/PF5
INT6/PF6
INT7/PF7
119
DREQ0/PG0
[TRG0 to 5] These are external trigger input pins of the PPG.
I/O
I/O
H
F
[PE1 to 3] These are general-purpose input/output ports.
[INT0 to 7] These are external interruption request inputs.
This input is always used while the corresponding external
interruption is permitted, so output using other functions
should be stopped except when carried out intentionally.
[PF0 to 7] These are general-purpose input/output ports.
I/O
H
[DREQ0] This is the DMA external transfer request input (ch
0) . This input is always used if selected as the transfer factor
for DMAC, so outputs from other functions should be
stopped except when carried out intentionally.
[PG0] This is a multi-purpose input/output port.
(Continued)
8
MB91110 Series
Pin no.
120
121
122
Pin name
DACK0/PG1
DEOP0/PG2
DREQ1/PG3
I/O*
I/O
I/O
I/O
Circuit type
C
C
H
Function
[DACK0] This is the DMAC external transfer request reception output (ch 0) . This function is effective if the transfer request reception output specification of DMAC is permitted.
[PG1] This is a multi-purpose input/output port. This function
is effective if the transfer request reception output specification of DMAC is prohibited.
[DEOP0] This is the DMA transfer end signal output (ch 0) .
This function is effective if the transfer end signal output
specification of DMAC is permitted.
[PG2] This is a multi-purpose input/output port. This function
is effective if the transfer end signal output specification of
DMAC is prohibited.
[DREQ1] This is the DMA external transfer request input (ch
1) . This input is always used if selected as the transfer factor
of DMAC, so output using other functions should be stopped
except when carried out intentionally.
[PG3] This is a multi-purpose input/output port.
123
124
127
DACK1/PG4
DEOP1/PG5
DREQ2/PH0
I/O
I/O
I/O
C
C
H
[DACK1] This is the DMAC external transfer request reception output (ch 1) . This function is effective if the transfer request reception output specification of DMAC is permitted.
[PG4] This is a multi-purpose input/output port. This function
is effective if the transfer request reception output specification of DMAC is prohibited.
[DEOP1] This is the DMA transfer end signal output (ch 1) .
This function is effective if the transfer end signal output
specification of DMAC is permitted.
[PG5] This is a multi-purpose input/output port. This function
is effective if the transfer end signal output specification of
DMAC is prohibited.
[DREQ2] This is the DMA external transfer request input (ch
2) . This input is always used if selected as the transfer factor
of DMAC, so output using other functions should be stopped
except when carried out intentionally.
[PH0] This is a multi-purpose input/output port.
128
DACK2/PH1
I/O
C
[DACK2] This is the DMAC external transfer request reception output (ch 2) . This function is effective if the transfer request reception output specification of DMAC is permitted.
[PH1] This is a multi-purpose input/output port. This function
is effective if the transfer request reception output specification of DMAC is prohibited.
(Continued)
9
MB91110 Series
Pin no.
129
130
Pin name
DEOP2/PH2
SI/PH3
I/O*
I/O
I/O
Circuit type
C
H
Function
[DEOP2] This is the DMA transfer end signal output (ch 2) .
This function is effective if the transfer end signal output
specification of DMAC is permitted.
[PH2] This is a multi-purpose input/output port. This function
is effective if the transfer end signal output specification of
DMAC is prohibited.
[SI] This is UART data input. This input is always used while
UART inputs, so outputs from other functions should be
stopped except when carried out intentionally.
[PH3] This is a general-purpose input/output port.
[SO] This is UART data output. This function is effective
when UART data output specification is permitted.
131
SO/PH4
I/O
C
[PH4] This is a general-purpose input/output port. This function is effective when UART data output specification is prohibited.
[SCK] This is UART clock input/output. Clock output is effective when UART clock output specification is permitted.
132
133
SCK/PH5
TI0/PH6
I/O
I/O
H
H
[PH5] This is a general-purpose input/output port. This function is effective when UART clock output specification is prohibited.
[TI0] This is reload timer 0 input. It is always used when reload timer input is permitted, so outputs from other functions
should be stopped except when carried out intentionally.
[PH6] This is a general-purpose input/output port.
134
136
TO0/PH7
TI1/PI0
I/O
I/O
C
H
[TO0] This is reload timer 0 Output. This function is effective
when reload timer specification is permitted.
[PH7] This is a general-purpose input/output port. This function is effective when reload timer specification is prohibited.
[TI1] This is reload timer 1 input. It is always used when reload timer input is permitted, so outputs from other functions
should be stopped except when carried out intentionally.
[PI0] This is a general-purpose input/output port.
[T01] This is the reload timer 1 output. This function is effective if the output specification of the reload timer is permitted.
137
TO1/PI1
I/O
C
[PI1] This is a multi-purpose input/output port. This function
is effective if the output specification of the reload timer is
prohibited.
(Continued)
10
MB91110 Series
(Continued)
Pin no.
Pin name
I/O*
Circuit type
Function
[PPG0 to 5] This is the PPG timer 1 output. This function is
effective if the output specification of the PPG timer is permitted.
138
139
140
141
142
143
PPG0/PI2
PPG1/PI3
PPG2/PI4
PPG3/PI5
PPG4/PI6
PPG5/PI7
I/O
C
18
46
66
76
104
125
VCC5
This provides power for the 5 V digital circuit system.
47
82
126
VCC3
This provides power for the 3 V digital circuit system.
9
19
28
37
54
67
79
105
118
135
144
VSS
This is the earth level for digital circuits.
[PI2 to 7] This is a multi-purpose input/output port. This function is effective if the output specification of the PPG timer is
prohibited.
* : I/O shown above indicates input/output classification.
Note : The I/O port and resource input/outputs for most of the above pins are multiplexed, i.e. Pxx/xxxx. In the event
of both the port and resource outputs were to use the same pins, the resource is given priority.
11
MB91110 Series
■ I/O CIRCUIT TYPE
Type
Circuit types
Remarks
X1
Clock input
A
• Oscillation feedback resistance :
approximately 1 MΩ
• 12.5 MHz oscillation
X0
STANDBY
CONTROL
VCC
P-channel type Tr
B
• CMOS level hysteresis input
Without standby control
With pull-up resistance
VSS
Digital input
Digital output
• CMOS level output
CMOS level input
With standby control
Digital output
C
Digital input
STANDBY
CONTROL
• A/D converter
Analog input pin
D
Analog input
(Continued)
12
MB91110 Series
(Continued)
Type
Circuit types
Remarks
• CMOS level hysteresis input
Without standby control
E
Digital input
Digital output
• CMOS level output
• CMOS level hysteresis input
Without standby control
Digital output
F
Digital input
• CMOS level output
Digital output
G
Digital output
Digital output
• CMOS level output
• CMOS level hysteresis input
With standby control
Digital output
H
Digital input
STANDBY
CONTROL
• CMOS level input
Without standby control
I
Digital input
13
MB91110 Series
■ HANDLING DEVICES
• Preventing Latch-up
The “Latch-up” phenomenon may be generated if a voltage in excess of VCC or lower than VSS is applied to the
input/output pins, or if the voltage exceeds the rating between VCC and VSS. If latch-up is generated, the electrical
current increases significantly and may destroy certain components due to the excessive heat, so great care
must be taken to ensure that the maximum rating is not exceeded during use.
• Handling Unused Input Pins
Input pins that are not used should be pulled up or down as they may cause erroneous operations if they are
left open.
• External Reset Input
“L” level should be input to the RST pin, which is required for at least five machine cycles to ensure the internal
status is reset.
• Using External Clocks
If external clock is used, X0 pin should be provided, and X1 pin should be provided with reverse phase to X0
pin input. If the STOP mode (oscillation stop mode) is used simultaneously, the X1 pin is stopped with the “H”
output. So, when STOP mode is specified, approximately 1 kΩ of resistance should be added externally. An
example of the external clock usage methods is shown in the following circuit.
Example of External Clock Usage (normal case)
X0
X1
MB91110
Note : Resistance must be added to the X1 pin if the STOP mode (oscillation stop mode) is used.
• Power Supply Pins
In products with multiple Vcc or Vss pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However you must connect the pins to an external power and
a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused
by the rise in the ground level, and to conform to the total current rating.
Make sure to connect Vcc and Vss pins via the lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 F between Vcc and Vss pins near the device.
• Crystal Oscillator Circuits
Noise around the X0 or X1 pins may cause erroneous operation. Make sure to provide bypass capacitors via
shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure
that lines of oscillation circuits not cross the lines of other circuit.
A printed circuit board artwork surrounding the X0 and X1 pins with ground area for stabilizing the operation is
highly recommended .
14
MB91110 Series
• N.C. Pins
N.C. pins must be opened for use.
• Mode Pins (MD0 to MD2)
Those pins must be directly connected to VCC or VSS for use.
Pattern length between VCC or VSS and each mode pin on the printed-circuit board should be arranged to be as
short as possible to prevent the test mode being erroneously turned on due to noise, they should also be
connected with low impedance.
• In the Event that Power Is Turned on
The RST pin must be started from “L” level when the power is turned on, and when the power is adjusted to the
VCC level it should be changed to the “H” level after being left for at least five cycles of the internal operation clock.
• Original Oscillation Input in the Event that Power Is Turned on
The clock must be input until the waiting status for oscillation stability is reset in the event that power is turned on.
• Hardware Standby in the Event that Power Is Turned on
Standby is not set in the event that power is turned on while the HST pin is set at “L” level. The HST pin becomes
effective after being reset, but it must first be returned to “H” level.
• Power on Reset
When power is turned on, “Power on reset” must be executed. If the power voltage falls below the guaranteed
operating voltage, “Power on reset” must be executed by turning on power supply again.
• Restrictions for Standby
Programs to be set for stop and sleep must be placed on the ROM in the C-bus or address area of the external
memory. If placed in the ROM address area on the I-bus, operation can not be guaranteed after returning.
• Execution of Programs in I-ROM/RAM Areas
In the event that programs in the I-ROM/RAM areas are executed, enter the I-ROM/RAM areas in accordance
with the JMP system instruction. Conversely, when accessing from programs in the I-ROM/RAM area to those
in other areas, exit in accordance with the JMP system instructions.
15
MB91110 Series
■ BLOCK DIAGRAM
FR30 CPU
(16 bit)
Instruction RAM
16 KB
Bit Search Module
I-bus
Instruction Cache
1 KB
DMAC (5 ch)
DREQ0 DREQ1 DREQ2
DACK0 DACK1 DACK2
DEOP0 DEOP1 DEOP2
Harvard
RAM
5 KB
D-bus (32 bit)
PLL
50 MHz
X0 X1
RST
HST
Prinston
Bus Converter
50 MHz →25 MHz
32 bit
16 bit
Bus Converter
Bus Controller
Clock Control Unit
C-bus
INT0 ∼ INT7
NMI
Interrupt Control Unit
(32 bit)
AN0 ∼ AN7
ATG
AVCC AVSS
AVRH AVRL
A/D Converter (8 ch)
TI0 TI1
TO0 TO1
Reload Timer (2 ch)
Port E ∼ I
R-bus (16 bit)
50 MHz
25 MHz
DRAM Controller
UART
16 bit PPG Timer
(6 ch)
D31 ∼ D16
A23 ∼ A00
RD
WR0 ∼WR 1
RDY
CLK
CS0 ∼ CS5
BRQ BGRNT
RAS0
CS0L
CS0H
DW0
RAS1
CS1L
CS1H
DW1
Port 0 ∼ B
SI
SO
SCK
PPG0 ∼ PPG5
TRG0 ∼ TRG5
Note :
Pins are described per function. Some of the pins are multiplexed.
In the event that REALOS is used, an external interruption or built-in timer should be used to control the time.
16
MB91110 Series
■ MEMORY SPACE
The FR30 series has 4 Gbytes (232 addresses) of logic address space which the CPU accesses linearly.
1. Memory Map
Internal ROM external bus modes
0000 0000H
I/O
0000 0400H
Direct addressing area
(Refer to "I/O MAP")
I/O
0000 0800H
Access is prohibited
0000 1000H
Built-in RAM 5 KB
0000 2400H
Access is prohibited
0001 0000H
External area
0008 0000H
Access is prohibited
000B C000H
I-RAM/ROM 16 KB
000C 0000H
Operating as the internal ROM.
Reading mode only can be accessed
in the case of I-RAM.
External area
0010 0000H
External area
FFFF FFFFH
Note : MB91110 series only supports internal ROM external bus mode.
• Direct addressing area
The following areas of the address space are used for I/O. This area is called the “direct addressing area” and
the address of the operand can be specified directly during instruction. The direct area differs depending on
data size to be accessed.
• Byte data access
: 0-0FFH
• Half-word data access
: 0-1FFH
• Word data access
: 0-3FFH
17
MB91110 Series
2. Registers
There are two types of multi-purpose registers in the FR family. One is a dedicated purpose register that exists
within the CPU and the other is a multi-purpose register that exists in the memory.
• Dedicated Registers
Program Counter (PC)
Program Status (PS)
Table Base Register (TBR)
Return Pointer (RP)
System Stuck Pointer (SSP)
User Stuck Pointer (USP)
Multiplication and Division
Results Resister (MDH/MDL)
: 32-bit length; indicates instruction storage position.
: 32-bit length; stores register pointers and condition codes.
: Holds the starting address of the vector table to be used for Exception, Interruption and Trapping (EIT) .
: Holds the address to which you will return to from the sub-routine.
: Indicates the systems stuck position.
: Indicates the user’s stuck position.
: 32-bit length; These are the registers for multiplication and division.
32 bit
Initial values
PC
Program Counter
PS
Program Status
XXXX XXXXH (Undecided)
Table Base Register
000F FC00H
Return Pointer
XXXX XXXXH (Undecided)
SSP
System Stuck Pointer
0000 0000H
USP
User Stuck Pointer
XXXX XXXXH (Undecided)
MDH
Multiplication and Division
Results Resister
TBR
RP
MDL
XXXX XXXXH (Undecided)
XXXX XXXXH (Undecided)
• Program Status (PS)
PS is the register that holds the program status and is classified into three categories, namely, Condition Code
Register (CCR) , System Condition Code Register (SCR) and Interruption Level Master Register (ILM) .
31 to 21 20
PS
19
18
16 15 to 11 10
9
8
7
6
5
4
3
2
1
0
D0
T
S
I
N
Z
V
C
ILM4 ILM3 ILM2 ILM1 ILM0
ILM
18
17
D1
SCR
CCR
MB91110 Series
• Condition Code Register (CCR)
S flag
: Specifies the stuck pointer to be used as R15.
I flag
: Controls permission and prohibition of user interruption requests.
N flag
: Indicates codes when the computation results are defined as integers that are expressed in
complements of 2.
Z flag
: Indicates if arithmetic results were “0.”
Indicates when operands are used for computation and defined as integers expressed in comV flag
:
plements of 2, and indicates whether or not an overflow is generated as a result of the computation.
C flag
: Indicates whether carrying or borrowing is generated from the highest bit as a result of the computation.
• System Condition Code Register (SCR)
T flag
: Specifies whether or not the step- trace- trap will be valid.
• Interruption Level Mask Register (ILM)
ILM4 to ILM0 : Holds the interruption level mask values, and those values that are held by the ILM are used
for the level mask. Interruption requests can only be accepted when the interruption levels
handled within the interruption requests to be input into the CPU are stronger than the levels
shown by the ILM.
ILM4
ILM3
ILM2
ILM1
ILM0
Interruption level
Strength
0
0
0
0
0
0
Strong
0
1
0
0
0
15
1
1
1
1
1
31
Weak
19
MB91110 Series
■ MULTI-PURPOSE REGISTERS
The multi-purpose registers are CPU registers (R0 to R15) which are used as accumulators for various computations and memory access pointers (field that indicates the address) .
• Register bank configuration
32-bit
R0
Initial value
XXXX XXXXH
R1
R12
R13
AC (Accumulator)
R14
FP (Frame Pointer)
XXXX XXXXH
R15
SP (Stack Pointer)
0000 0000H
Special purposes are assumed for the following three registers out of the 16 registers. Thus, some instructions
are emphasized.
R13 : Virtual accumulator (AC)
R14 : Frame Pointer (FP)
R15 : Stack Pointer (SP)
Initial values for R0 to R14 on resetting are unspecified. The initial value of R15 will be 0000 0000H (SSP value) .
20
MB91110 Series
■ MODE SETTING
1. Pins
• Mode pins and set mode
Mode pins
Mode name
MD2 MD1 MD0
Reset vector
access areas
External data bus
width
Bus modes
0
0
0
External vector
mode 0
External
8-bit
0
0
1
External vector
mode 1
External
16-bit
0
1
0
0
1
1
Internal vector
mode
Internal
(Mode register)
Single chip mode*
1
Usage is prohibited
External ROM external
bus mode
Setting is prohibited
* : MB91110 series is not supported single chip mode.
2. Register
• Mode register (MODR) and set mode
Address
0000 07FFH
M1
M0
*
*
*
*
*
*
Initial value Access
XXXXXXXXB
W
Bus mode set bit
W : Write only
X : Undecided
* : “0” should always be written for bits other than M1 and M0.
• Bus mode set bit and its functions
M1
M0
Functions
0
0
Single chip mode
0
1
Internal ROM external bus mode
1
0
External ROM external bus mode
1
1
Remarks
Not supported
Setting is prohibited
21
MB91110 Series
■ I/O MAP
Register
Address
+0
000000H
000004H
000008H
PDRB
+1
PDR2
(R/W)
XXXXXXXX
PDR6
(R/W)
XXXXXXXX
(R/W)
PDRA
XXXXXXXX
(R/W)
+3
PDR8
- XXXXXX -
Internal resource
(R/W)
- - X - - XXX
Port data register
00000CH
000010H
000014H
+2
PDRG
PDRE
(R/W)
PDRH
- - XXXXXX
(R/W)
PDRF
- - - - XXXX
(R/W)
PDRI
XXXXXXXX
(R/W)
XXXXXXXX
(R/W)
XXXXXXXX
000018H
Reserved
00001CH
Reserved
000020H
000024H
000028H
SSR
(R/W)
00001-00
SCR
(R/W)
(R/W)
(R/W)
00000-00
UART
0--11111
(W)
TMR
(R)
XXXXXXXX XXXXXXXX
TMCSR
TMRLR
SMR
00000100
XXXXXXXX XXXXXXXX
(R/W)
Reload timer 0
- - - -0000 00000000
(W)
TMR
XXXXXXXX XXXXXXXX
(R)
XXXXXXXX XXXXXXXX
TMCSR
ADCR
00003CH
CDCR
TMRLR
000034H
000038H
XXXXXXXX
00002CH
000030H
SIDR/SODR (R/W)
(R/W)
Reload timer 1
----0000 00000000
(R)
ADCS
- - - - - - XX XXXXXXXX
(R/W)
00000000 00000000
A/D converter
(Sequential
comparison type)
Reserved
(Continued)
22
MB91110 Series
Address
Register
+0
+1
000048H
00004CH
000050H
000054H
000058H
00005CH
000060H
000064H
000068H
00006CH
000070H
Internal resource
+3
000040H
000044H
+2
PCSR
Access is prohibited
PDUT
(W)
PCNH
Access is prohibited
(W)
(W)
00000000
PCSR
(W)
(R/W)
PCNL
(R/W)
0000000-
00000000
PCSR
(W)
PCNH
Access is prohibited
(W)
Access is prohibited
(R/W)
PCNL
(R/W)
0000000-
00000000
PCSR
(W)
XXXXXXXX
XXXXXXXX
PCNH
XXXXXXXX XXXXXXXX
(R/W)
PCNL
(R/W)
0000000-
00000000
PCSR
(W)
XXXXXXXX XXXXXXXX
(W)
PCNH
XXXXXXXX XXXXXXXX
Access is prohibited
PDUT
(R/W)
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
PDUT
PCNL
0000000-
PCNH
Access is prohibited
PDUT
(R/W)
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
PDUT
(W)
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
PDUT
Reserved
(R/W)
PCNL
(R/W)
0000000-
00000000
PCSR
(W)
XXXXXXXX XXXXXXXX
(W)
PCNH
XXXXXXXX XXXXXXXX
(R/W)
0000000-
000074H
000078H
PCNL
(R/W)
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
00000000
Reserved
00007CH
000080H
(Continued)
23
MB91110 Series
Register
Address
+0
+1
+2
000084H
000088H
+3
Internal resource
Reserved
00008CH
000090H
000094H
000098H
EIRR
(R/W)
ENIR
(R/W)
00000000
00000000
ELVR
(R/W)
00000000 00000000
00009CH
0000A0H
0000A4H
0000A8H
0000ACH
0000B0H
0000B4H
0000B8H
0000BCH
0000C0H
0000C4H
External interruption/
NMI
Reserved
(Continued)
24
MB91110 Series
Register
Address
+0
+1
+2
Internal resource
+3
0000C8H
Reserved
0000CCH
0000D0H
0000D4H
DDRG
DDRE
(W)
--000000
DDRH
(W)
----0000
(W)
DDRI
00000000
DDRF
(W)
00000000
(W)
00000000
Data direction
register
0000D8H
to
0000FCH
Reserved
000100H
to
0001FCH
Reserved
000200H
000204H
000208H
00020CH
000210H
000214H
000218H
00021CH
DMACS0
0-00-000
(R/W)
00 --0000
XX - 0 0 0 0 0 - - - - XX - X
DMACC0
(R/W)
- - - - XXXX XXXX - XXX XXXXXXXX XXXXXXXX
DMASA0
XXXXXXXX
(R/W)
XXXXXXXX
XXXXXXXX
DMADA0
XXXXXXXX
XXXXXXXX
(R/W)
XXXXXXXX
XXXXXXXX
DMACS1
0-00-000
XXXXXXXX
(R/W)
0 0 - - 0 0 0 0 XX - 0 0 0 0 0 - - - - XX - X
DMACC1
(R/W)
- - - - XXXX XXXX - XXX XXXXXXXX XXXXXXXX
DMASA1
XXXXXXXX
(R/W)
XXXXXXXX
XXXXXXXX
DMADA1
XXXXXXXX
DMA controller
channel 0
DMA controller
channel 1
XXXXXXXX
(R/W)
XXXXXXXX
XXXXXXXX
XXXXXXXX
(Continued)
25
MB91110 Series
Address
000220H
000224H
000228H
00022CH
000230H
000234H
000238H
00023CH
000240H
000244H
000248H
00024CH
000250H
Register
+0
+1
+2
DMACS2
0-00-000
+3
(R/W)
0 0 - - 0 0 0 0 XX - 0 0 0 0 0 - - - - XX - X
DMACC2
(R/W)
- - - - XXXX XXXX - XXX XXXXXXXX XXXXXXXX
DMASA2
XXXXXXXX
(R/W)
XXXXXXXX
XXXXXXXX
DMADA2
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
(R/W)
0 0 - - 0 0 0 0 XX - 0 0 0 0 0 - - - - XX - X
DMACC3
(R/W)
- - - - XXXX XXXX - XXX XXXXXXXX XXXXXXXX
DMASA3
XXXXXXXX
(R/W)
XXXXXXXX
XXXXXXXX
DMADA3
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
(R/W)
0 0 - - 0 0 0 0 XX - 0 0 0 0 0 - - - - XX - X
DMACC4
(R/W)
- - - - XXXX XXXX - XXX XXXXXXXX XXXXXXXX
DMASA4
XXXXXXXX
(R/W)
XXXXXXXX
XXXXXXXX
DMADA4
XXXXXXXX
DMA controller
channel 4
XXXXXXXX
(R/W)
XXXXXXXX
XXXXXXXX
DMACR
--------
DMA controller
channel 3
(R/W)
DMACS4
0-00-000
DMA controller
channel 2
(R/W)
DMACS3
0-00-000
Internal resource
XXXXXXXX
(R/W)
--------
00------
000254H
000258H
-------0
Overall DMA
controller
Reserved
00025CH
000260H
(Continued)
26
MB91110 Series
Register
Address
+0
+1
+2
000264H
000268H
00026CH
000270H
000274H
000278H
to
0002FCH
000300H
to
0003E0H
ICHCR
IRMC
XXXXXXXX
XXXXXXXX
XXXXXXXX
BSD1
(R/W)
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
BSDC
0003F8H
XXXXXXXX
XXXXXXXX
XXXXXXXX
BSRR
(R)
XXXXXXXX
ICR00
(R/W)
---11111
ICR04
(R/W)
---11111
Bit search module
(W)
XXXXXXXX
0003FCH
I-RAM control
(W)
XXXXXXXX
0003F4H
(R/W)
-------0
BSD0
0003F0H
Instruction cache
Reserved
0003ECH
000404H
(R/W)
--0 0 0 0 0 0
0003E8H
000400H
Reserved
0003E4H
Internal resource
+3
XXXXXXXX
ICR01
(R/W)
---11111
ICR05
(R/W)
---11111
XXXXXXXX
ICR02
XXXXXXXX
(R/W)
---11111
ICR06
(R/W)
---11111
ICR03
(R/W)
---11111
ICR07
(R/W)
Interruption controller
---11111
(Continued)
27
MB91110 Series
Register
Address
000408H
00040CH
000410H
000414H
000418H
00041CH
000420H
000424H
000428H
00042CH
000430H
+0
ICR08
+1
(R/W)
---11111
ICR12
(R/W)
---11111
ICR16
(R/W)
---11111
ICR20
(R/W)
---11111
ICR24
(R/W)
---11111
ICR28
(R/W)
---11111
ICR32
(R/W)
---11111
ICR36
(R/W)
---11111
ICR40
(R/W)
---11111
ICR44
(R/W)
---11111
DICR
(R/W)
-------0
ICR09
+2
(R/W)
---11111
ICR13
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
000488H
00048CH
to
0005FCH
ICR23
---11111
(R/W)
ICR30
ICR27
ICR31
ICR35
(R/W)
ICR39
(R/W)
---11111
(R/W)
ICR46
ICR43
(R/W)
---11111
(R/W)
ICR47
(R/W)
---11111
---11111
---11111
1 XXXX - 0 0
GCR
(R/W)
1 1 0 0 1 1-1
PCTR
STCR
(R/W)
0 0 0 1 1 1-WPR
Interruption controller
---11111
(R/W)
ICR42
(R/W)
---11111
(R/W)
ICR38
(R/W)
---11111
(R/W)
ICR34
(R/W)
Delay interruption
RSRR/WTCR (R/W)
000484H
(R/W)
ICR26
(R/W)
000434H
to
00047CH
000480H
ICR22
(R/W)
---11111
---11111
---11111
HRCL
ICR19
---11111
---11111
ICR45
(R/W)
---11111
---11111
ICR41
ICR18
(R/W)
---11111
---11111
---11111
ICR37
ICR15
---11111
---11111
ICR33
(R/W)
---11111
---11111
ICR29
ICR14
(R/W)
---11111
---11111
---11111
ICR25
ICR11
---11111
---11111
ICR21
(R/W)
---11111
---11111
ICR17
ICR10
Internal resource
+3
Reserved
PDRR
(R/W)
CTBR
----0 0 0 0
(W)
(W)
XXXXXXXX
Clock control area
XXXXXXXX
(R/W)
0 0--0--
PLL control register
Reserved
(Continued)
28
MB91110 Series
(Continued)
Register
Address
+0
000600H
000604H
000608H
00060CH
000610H
000614H
000618H
00061CH
000620H
000624H
000628H
00062CH
+1
DDR2
00000000
DDR6
(W)
00000000
DDRB
(W)
DDRA
(W)
+3
Internal resource
Data direction
register
DDR8
(W)
00000000
-000000-
ASR1
(W)
AMR1
(W)
00000000
00000001
00000000
00000000
ASR2
(W)
AMR2
(W)
00000000
00000010
00000000
00000000
ASR3
(W)
AMR3
(W)
00000000
00000011
00000000
00000000
ASR4
(W)
AMR4
(W)
00000000
00000100
00000000
00000000
ASR5
(W)
AMR5
(W)
00000000
00000101
00000000
00000000
AMD0
(R/W)
AMD1
---00111
AMD5
(R/W)
AMD32
0--00000
(R/W)
DSCR
(W)
--0--000
(R/W)
AMD4
00000000
0--00000
RFCR
(R/W)
00000000
- - XXXXXX
0---0000
EPCR0
(W)
EPCR1
(W)
----1100
-1111111
--------
11111111
DMCR4
(R/W)
DMCR5
(R/W)
00000000
0000000-
00000000
0000000-
External bus
interface
(R/W)
0--00000
000630H
to
0007F8H
0007FCH
(W)
+2
Reserved
LER
(W)
MODR
-----000
Note : Do not execute RMW instructions to registers with write-only bits.
RMW instruction (RMW : Read / Modify / Write)
AND
Rj, @Ri
OR
Rj, @Ri
EOR
ANDH
Rj, @Ri
ORH Rj, @Ri
EORH
ANDB
Rj, @Ri
ORB Rj, @Ri
EORB
BANDL #u4, @Ri
BORL #u4, @Ri
BEORL
BANDH #u4, @Ri
BORH #u4, @Ri
BEORH
Data in areas with “ ” or reserved ones is undecided.
(W)
XXXXXXXX
“Little endian” register
Mode register
Rj, @Ri
Rj, @Ri
Rj, @Ri
#u4, @Ri
#u4, @Ri
29
MB91110 Series
■ INTERRUPTION VECTOR
Interruption factor and allocation of interruption vectors / interruption control registers are described in the
interruption vector table.
Interruption number
Interruption vector
Interruption
address to TBR of
Interruption source
Offset
Hexadecilevel *1
Decimal
default *2
mal
Reset
0
00
3FCH
000FFFFCH
System reservation
1
01
3F8H
000FFFF8H
System reservation
2
02
3F4H
000FFFF4H
System reservation
3
03
3F0H
000FFFF0H
System reservation
4
04
3ECH
000FFFECH
System reservation
5
05
3E8H
000FFFE8H
System reservation
6
06
3E4H
000FFFE4H
Coprocessor absence trap
7
07
3E0H
000FFFE0H
Coprocessor error trap
8
08
3DCH
000FFFDCH
INTE instruction
9
09
4 fixed
3D8H
000FFFD8H
System reservation
10
0A
3D4H
000FFFD4H
System reservation
11
0B
3D0H
000FFFD0H
Step trace trap
12
0C
4 fixed
3CCH
000FFFCCH
System reservation
13
0D
3C8H
000FFFC8H
Exceptions to undefined instructions
14
0E
3C4H
000FFFC4H
NMI request
15
0F
15 (FH) fixed
3C0H
000FFFC0H
System reservation
16
10
ICR00
3BCH
000FFFBCH
System reservation
17
11
ICR01
3B8H
000FFFB8H
External interruption 0
18
12
ICR02
3B4H
000FFFB4H
External interruption 1
19
13
ICR03
3B0H
000FFFB0H
External interruption 2
20
14
ICR04
3ACH
000FFFACH
External interruption 3
21
15
ICR05
3A8H
000FFFA8H
External interruption 4
22
16
ICR06
3A4H
000FFFA4H
External interruption 5
23
17
ICR07
3A0H
000FFFA0H
External interruption 6
24
18
ICR08
39CH
000FFF9CH
External interruption 7
25
19
ICR09
398H
000FFF98H
System reservation
26
1A
ICR10
394H
000FFF94H
UART reception completion
27
1B
ICR11
390H
000FFF90H
System reservation
28
1C
ICR12
38CH
000FFF8CH
System reservation
29
1D
ICR13
388H
000FFF88H
UART transmission completion
30
1E
ICR14
384H
000FFF84H
System reservation
31
1F
ICR15
380H
000FFF80H
(Continued)
30
MB91110 Series
Interruption number
Interruption source
Interruption
level *1
Offset
Interruption vector
address to TBR of
default *2
Decimal
Hexadecimal
System reservation
32
20
ICR16
37CH
000FFF7CH
DMAC0 (end, error)
33
21
ICR17
378H
000FFF78H
DMAC1 (end, error)
34
22
ICR18
374H
000FFF74H
DMAC2 (end, error)
35
23
ICR19
370H
000FFF70H
DMAC3 (end, error)
36
24
ICR20
36CH
000FFF6CH
DMAC4 (end, error)
37
25
ICR21
368H
000FFF68H
System reservation
38
26
ICR22
364H
000FFF64H
System reservation
39
27
ICR23
360H
000FFF60H
System reservation
40
28
ICR24
35CH
000FFF5CH
A/D sequential conversion type
41
29
ICR25
358H
000FFF58H
Reload timer 0
42
2A
ICR26
354H
000FFF54H
Reload timer 1
43
2B
ICR27
350H
000FFF50H
16-bit PPG timer 0
44
2C
ICR28
34CH
000FFF4CH
16-bit PPG timer 1
45
2D
ICR29
348H
000FFF48H
16-bit PPG timer 2
46
2E
ICR30
344H
000FFF44H
16-bit PPG timer 3
47
2F
ICR31
340H
000FFF40H
16-bit PPG timer 4
48
30
ICR32
33CH
000FFF3CH
16-bit PPG timer 5
49
31
ICR33
338H
000FFF38H
System reservation
50
32
ICR34
334H
000FFF34H
System reservation
51
33
ICR35
330H
000FFF30H
System reservation
52
34
ICR36
32CH
000FFF2CH
System reservation
53
35
ICR37
328H
000FFF28H
System reservation
54
36
ICR38
324H
000FFF24H
System reservation
55
37
ICR39
320H
000FFF20H
System reservation
56
38
ICR40
31CH
000FFF1CH
System reservation
57
39
ICR41
318H
000FFF18H
System reservation
58
3A
ICR42
314H
000FFF14
System reservation
59
3B
ICR43
310H
000FFF10H
System reservation
60
3C
ICR44
30CH
000FFF0CH
System reservation
61
3D
ICR45
308H
000FFF08H
System reservation
62
3E
ICR46
304H
000FFF04H
Delay interruption factor bit
63
3F
ICR47
300H
000FFF00H
System reservation
(used under REALOS) *3
64
40
2FCH
000FFEFCH
(Continued)
31
MB91110 Series
(Continued)
Interruption number
Interruption source
Interruption
level *1
Offset
Interruption vector
address to TBR of
default *2
Decimal
Hexadecimal
System reservation
(used under REALOS) *3
65
41
2F8H
000FFEF8H
Used under INT instruction
66
to
255
42
to
FF
2F4H
to
000H
000FFEF4H
to
000FFD00H
*1 : ICR sets the interruption level for each interruption request using the register built into the interruption controller.
ICR is prepared in accordance with each interruption request.
*2 : TBR is the register that indicates the starting address of the vector table for EIT.
Addresses with added offset values that are specified per TBR and EIT factor will be the vector addresses.
*3 : REALOS OS/FR uses 0X40, 0X41 interruptions for system codes.
Reference :
The vector area for EIT is 1 KB in accordance with the address shown by TBR.
The size per vector is 4 bytes, and the relationship between the vector numbers and their addresses is shown
as follows.
vctadr = TBR + vctofs
= TBR + (3FCH − 4 × vct)
vctadr : vector address vctofs : vector offset vct : vector number
32
MB91110 Series
■ PERIPHERAL RESOURCES
1. I/O Port
MB91110 series can be used as the I/O port when settings for resources that handle each pin do not to use the
pins for input/output.
• Block diagram
Resource input
Data Bus
0
1
PDR read
pin
0
PDR
Resource
output
1
Resource output
allowed
DDR
PDR : Port Data Register
DDR : Data Direction Register
• I/O Port Registers
I/O port is composed of the Port Data Register (PDR) and Data Direction Register (DDR) .
• In cases where the input mode is DDR = “0”
For PDR reading : Level of external pins to be handled is read out.
For PDR writing : Set value is written in PDR.
• In cases where the output mode is DDR = “1”
For PDR reading : PDR value is read out.
For PDR writing : Set value is written in PDR and the PDR value is simultaneously output to the
externally handled pin.
33
MB91110 Series
2. Port Data Register (PDR)
Port Data Register (PDR2-I) is the input/output data register for the I/O port.
Input/output control is carried out by the handled data direction register (DDR2-I) .
• Port Data Register (PDR)
PDR2
7
6
5
4
3
2
1
0
Initial value
Access
P27
P26
P25
P24
P23
P22
P21
P20
XXXXXXXXB
R/W
7
6
5
4
3
2
1
0
Initial value
Access
P67
P66
P65
P64
P63
P62
P61
P60
XXXXXXXXB
R/W
PDR8
7
6
5
4
3
2
1
0
Initial value
Access
Address : 00000BH
P85
P82
P81
P80
- - X- - XXXB
R/W
PDRA
7
6
5
4
3
2
1
0
Initial value
Access
Address : 000009H
PA6
PA5
PA4
PA3
PA2
PA1
- XXXXXX- B
R/W
PDRB
7
6
5
4
3
2
1
0
Initial value
Access
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
XXXXXXXXB
R/W
PDRE
7
6
5
4
3
2
1
0
Initial value
Access
Address : 000012H
PE3
PE2
PE1
PE0
- - - - XXXXB
R/W
PDRF
7
6
5
4
3
2
1
0
Initial value
Access
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
XXXXXXXXB
R/W
PDRG
7
6
5
4
3
2
1
0
Initial value
Access
Address : 000014H
PG5
PG4
PG3
PG2
PG1
PG0
- - XXXXXXB
R/W
PDRH
7
6
5
4
3
2
1
0
Initial value
Access
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
XXXXXXXXB
R/W
7
6
5
4
3
2
1
0
Initial value
Access
PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0
XXXXXXXXB
R/W
Address : 000001H
PDR6
Address : 000005H
Address : 000008H
Address : 000013H
Address : 000015H
PDRI
Address : 000016H
34
MB91110 Series
3. Data Direction Register (DDR)
The Data Direction Register (DDR2-I) controls the input/output direction of the I/O port per bit.
0 is used for input and 1 is used to execute output control.
• Data Direction Register (DDR)
DDR2
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P63
P62
P61
P60
DDR8
7
6
5
4
3
2
1
0
Address : 00060BH
P85
P82
P81
P80
DDRA
7
6
5
4
3
2
1
0
Address : 000609H
PA6
PA5
PA4
PA3
PA2
PA1
DDRB
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
7
6
5
4
3
2
1
0
Address : 0000D2H
PE3
PE2
PE1
PE0
DDRF
7
6
5
4
3
2
1
0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
DDRG
7
6
5
4
3
2
1
0
Address : 0000D4H
PG5
PG4
PG3
PG2
PG1
PG0
DDRH
7
6
5
4
3
2
1
0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
7
6
5
4
3
2
1
0
PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0
Address : 000601H
DDR6
Address : 000605H
Address : 000608H
DDRE
Address : 0000D3H
Address : 0000D5H
DDRI
Address : 0000D6H
Initial value Access
00000000B
W
Initial value Access
00000000B
W
Initial value Access
- - 0 - - 000B
W
Initial value Access
- 000000 -B
W
Initial value Access
00000000B
W
Initial value Access
- - - - 0000B
W
Initial value Access
00000000B
W
Initial value Access
- - 000000B
W
Initial value Access
00000000B
W
Initial value Access
00000000B
W
35
MB91110 Series
4. Instruction Cache
The instruction cache is a temporary storage memory. In the event that the instruction codes are accessed from
a low speed external memory, it holds the accessed codes internally, and is used to increase the access speed
for all subsequent accesses.
Direct read or write access can not be done by instruction cache or instruction cache tag using software.
• Cacheable area of the instruction cache
Instruction cache allows all space to become a cacheable area.
• Built-in ROM shall also be cacheable for products featuring built-in ROMs.
• It is assumed that instruction access is not carried out to spaces other than external areas and built-in ROMs.
Thus, even if an instruction access is made, it would be cacheable to the control register in the I/O area.
• Even though details of the external memory are updated by DMA transfer, it is not coherent with the cache
details. In this case, coherency should be established by flushing the cache.
•
•
•
•
Instruction cache configuration
Basic instruction length of FR series : 2 bytes
Block layout : 2-way set associative type
Block
1 way is configured of 32 blocks.
1 block is 16 bytes ( = 4 sub blocks)
1 sub block is 4 bytes ( = 1 bus access unit)
The instruction cache configuration is shown in the following figure.
Instruction Cache Configuration
4 bytes
4 bytes
4 bytes
4 bytes
I3
I2
I1
I0
Cache tag
Sub lock 3
Sub lock 2
Sub lock 1
Sub lock 0
Block 0
Cache tag
Sub lock 3
Sub lock 2
Sub lock 1
Sub lock 0
Block 31
Cache tag
Sub lock 3
Sub lock 2
Sub lock 1
Sub lock 0
Block 0
Cache tag
Sub lock 3
Sub lock 2
Sub lock 1
Sub lock 0
Block 31
4 bytes
Way 1
32 blocks
Way 2
32 blocks
36
MB91110 Series
5. Instruction Cache Control Register (ICHCR)
The Instruction Cache Control Register (ICHCR) controls the operation of the instruction cache. Writing to
ICHCR may effect the cache operation of instructions to be retrieved within the next three cycles.
• Instruction Cache Control Register (ICHCR)
Instruction Cache Control Register (ICHCR) is shared for use by ways 1 and 2.
Address : 0000 03E7H
07
06
05
04
03
02
01
00
GBLK
ALFL
EOLK
ELKR
FLSH
ENAB
Initial value Access
- - 000000
R/W
Global lock
Auto lock fail
Entry auto lock
Entry lock release
Flush
Enable
37
MB91110 Series
6. Clock Generator (Low power consumption mechanism)
The clock generation area is a module with the following functions.
• CPU clock generation (including gear function)
• Peripheral clock generation (including gear function)
• Reset generation and holding factors
• Standby function (including hardware standby)
• Restraining DMA request
• PLL (Phase Locked Loop) is built in
• Register list
Address
000480H
000481H
15
14
12
11
10
RSRR/WTCR
000482H
000483H
38
13
PDRR
000484H
000485H
GCR
000488H
PCTR
09
08
07
06
05
04
03
02
01
00
Initial value Access
STCR
1XXXX- 00B
000111 - - B
R/W
R/W
CTBR
- - - - 0000B
XXXXXXXXB
R/W
W
WPR
110011- 1B
XXXXXXXXB
R/W
W
00 - - 0 - - - B
R/W
MB91110 Series
• Block diagram
[ Gear control area ]
R
|
B
U
S
GCR register
CPU gear
CPU clock
Peripheral
gear
Internal
clock
generation
circuit
PCTR register
X0
X1
Oscillation
circuit
PLL
Selection
circuit
Internal
bus clock
External
bus clock
Peripheral
DMA clock
Internal
peripheral clock
1/2
Internal
interruption
Internal reset
[ Stop/sleep control area ]
STCR register
STOP status
CPU hold
Permission
HST pin
DMA request
Status
transfer
control
circuit
SLEEP status
CPU hold request
Reset
generation
F/F
Internal reset
[ DMA blocking circuit ]
PDRR register
[ Reset factor circuit ]
Power on cell
RST pin
RSRR register
[ Watchdog control area ]
WPP register
Watchdog F/F
CTBR register
Time base timer
Count
clock
39
MB91110 Series
7. Bus Interface Outline
The bus interface controls the interface with external memory and external I/O.
• Bus Interface Characteristics
• 24-bit (16 MB) address output
• 6 individual banks using chip selection function
Random positional setting is possible on the logical address space at minimum 64-KB units.
Total 16 MB × 6 areas can be set using the address pin and chip selection pin.
• 16/8-bit bus width can be set per chip selection area.
• Insertion of programmable “automatic memory wait” (maximum of 7 cycles)
• Supports DRAM interface
3 types of DRAM interface
Double CAS DRAM (Normal DRAM I/F)
Single CAS DRAM
Hyper DRAM
2-bank individual control (control signal i.e. RAS and CAS)
DRAM can be selected from 2CAS/1WE or 1CAS/2WE.
Supports high-speed page mode
Supports CBR / self refresh
Programmable corrugation
• Unused addresses / data pins can be used as I/O ports.
• Supports “little endian” mode
• Using clock doubler : Internal 50 MHz, external bus 25 MHz operation
• Chip Selection Area
A total of six types of chip selection areas are prepared for the bus interface. The position of each area can be
randomly arranged per 64 KB at least using area selection registers (ASR1 to 5) and area mask registers (AMR1
to 5) in an area of 4 GB. In the event that access to an external bus is attempted in areas that are specified by
those registers, the supported chip selection signals (CS0 to CS5) become activated to “L”. Such pins other
than CS0 are deactivated to “H” when reset.
Note : The area 0 is allocated to space outside the area specified by ASR1 to ASR5. External areas other than
0001 0000H to 0005 FFFFH are deemed area 0 on resetting.
40
MB91110 Series
• Interface
The bus interface has the following interface types.
• Normal bus interface
• DRAM interface
These interfaces can only be used in predetermined areas. The following table shows each chip selection area
and the usable interface functions.Which interface is to be used is selected in the Area Mode Register (AMD) .
If no selection is made, it defaults to the normal bus interface.
Areas
Chip Selection Area and Selectable Bus Interfaces
Selectable bus interface
Normal bus
Time division
DRAM
0
1
2
3
4
5
Remarks
On resetting
• Block Diagram
A-OUT
ADDRESS BUS DATA BUS
32
32
EXTERNAL
DATA BUS
write buffer
switch
read buffer
switch
MUX
DATA BLOCK
ADDRESS BLOCK
+1or+2
EXTERNAL
ADDRESS BUS
inpage
address buffer
shifter
CS0 ∼ CS5
ASR
AMR
comparator
DRAM control
underflow
DMCR
RAS0, RAS1
CS0L, CS1L
CS0H, CS1H
DW0, DW1
refresh counter
from TBT
External pin control area
Controls all blocks
registers & control
RD
WR0, WR1
BRQ
BGRNT
CLK
RDY
41
MB91110 Series
• Register List
Address
00060CH
00060EH
000610H
000612H
000614H
000616H
000618H
00061AH
00061CH
00061EH
000620H
000622H
000624H
000626H
000628H
00062AH
00062CH
00062EH
31
24 23
16 15
0
Initial value
EPCR0 (External Pin Control 0)
EPCR1 (External Pin Control 1)
DMCR4 (DRAM Control Reg. 4)
DMCR5 (DRAM Control Reg. 5)
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
- - - 00111
00000000
0- - 00000
- -XXXXXX
- - - - 1100
-------00000000
00000000
LER *3
- - - - - - 00
ASR1 (Area Select Reg. 1)
AMR1 (Area Mode Reg. 1)
ASR2 (Area Select Reg. 2)
AMR2 (Area Mode Reg. 2)
ASR3 (Area Select Reg. 3)
AMR3 (Area Mode Reg. 3)
ASR4 (Area Select Reg. 4)
AMR4 (Area Mode Reg. 4)
ASR5 (Area Select Reg. 5)
AMR5 (Area Mode Reg. 5)
AMD0 *1
AMD1 *1
AMD5 *1
DSCR *2
0007FCH
*1 : AMD (Area MoDe register)
*2 : DSCR (DRAM Signal Control Register)
*3 : LER (Little Endian Register)
*4 : MODR (MODe Register)
42
8 7
AMD32 *1
AMD4 *1
RFCR (Refresh Control Register)
MODR *4
00000001 B
00000000 B
00000010 B
00000000 B
00000011 B
00000000 B
00000100 B
00000000 B
00000101 B
00000000 B
0- - 00000 B
0- - 00000 B
00000000 B
0- - - 0000 B
- 0000000 B
11111111 B
0000000- B
0000000- B
XXXXXXXX B
Access
W
W
W
W
W
W
W
W
W
W
R/W
R/W
R/W
R/W
W
W
R/W
R/W
W
MB91110 Series
8. 16-bit Reload Timer
The 16-bit timer is composed of a 16-bit down counter, 16-bit reload register, a pre-scalar for internal count clock
preparation and a control register. Selection of the input clock can be made from three types of internal clock
(machine clocks with 2, 8 and 32 cycles) and an external clock are selectable for input clock.
• Characteristics of the 16-bit reload timer
The Pin Output (TO) outputs a toggle waveform whenever underflow is generated in reload mode, and outputs
rectangular waves indicating that it is counting in the case of one shot mode.
Pin Input (TI) can be used for event input in the case of external event count mode, trigger input or gate input
for internal clock mode.
If the external event count function is used as the reload mode, it can be used as the cycle device for the external
clock.
In this type, a 2-channel timer is built-in.
Channel 0 of the reload timer can start up DMA transfer using the interruption request signal.
The DMA controller clears the interruption flag of the reload timer at the same time as receiving the transfer
request.
The TO output from channel 0 for the reload timer is connected to the A/D converter inside the LSI. Thus, A/D
conversion can be started on a cycle set at the reload register.
43
MB91110 Series
• Block Diagram
16
16-bit reload register
R
|
B
U
S
8
Reload
RELD
16-bit down counter
OUTE
UF
16
OUTL
2
OUT
CTL.
GATE
INTE
2
IRQ
UF
CSL1
CNTE
Clock selector
CSL0
TRG
Retrigger
2
IN CTL.
Port (TI)
EXCK
φ
φ
21 2
φ
3
2
Port (TO)
3
Pre-scalar
Clear
5
MOD2
MOD1
Internal clock
MOD0
3
• Register List
• Control status register (TMCSR)
Address
15
14
13
12
11
10
9
8
Initial value
Access
CSL1
CSL0
MOD2
MOD1
- - - - 0000B
R/W
7
6
5
4
3
2
1
0
MOD0
OUTE
OUTL
RELD
INTE
UF
CNTE
TRG
00000000B
R/W
Initial value
Access
000036H
000037H
• 16-bit timer register (TMR)
Address
15
0
XXXXXXXX
XXXXXXXX
00002AH
000032H
• 16-bit reload register (TMRLR)
Address
15
000028H
000030H
44
0
XXXXXXXXB
XXXXXXXXB
Initial value
XXXXXXXX
XXXXXXXX
XXXXXXXXB
XXXXXXXXB
W
Access
W
MB91110 Series
9. PPG Timer
The PPG timer can output pulses that are synchronized with soft triggers or externally. Also, the cycle and duty
of the output pulses can be changed randomly by replacing the two 16-bit register values. In this type, there
are 6 built-in channels with this function.
• PPG timer function
The PPG timer has two functions as follows.
• PWM function
This can be synchronized to the trigger and is programmable to output pulses while rewriting the above register
values. It can also be used as a D/A converter by using an additional circuit.
• One-shot function
This detects the edge of the trigger input and outputs a single pulse.
• Block Diagram
PDUT
PCSR
Pre-scalar
φ/2
φ/8
φ / 32
φ / 128
cmp
Load
ck
16-bit Down counter
Start
Borrow
PPG mask
S
Q
PPG output
R
Reverse bit
Enable
TRG input
(only channels 0 to 2)
Edge
detection
Interruption
selection
IRQ
Soft trigger
45
MB91110 Series
• Register List
• Cycle setting register (PCSR)
Address
000046H
00004EH
000056H
00005EH
000066H
00006EH
bit 15
Initial value
8 7
0
XXXXXXXX
• Duty setting register (PDUT)
Address
000048H
000050H
000058H
000060H
000068H
000070H
bit 15
XXXXXXXX
46
bit 15
XXXXXXXXB
Initial value
8 7
W
Access
0
• Control/status register (PCNH/PCNL)
Address
00004AH
000052H
00005AH
000062H
00006AH
000072H
XXXXXXXXB
Initial value
8 7
Access
W
Access
0
0000000 -
00000000B
R/W
MB91110 Series
10. External Interruption/NMI Control Area
The external interruption / NMI control area controls the external interruption requests to be input to the NMI
and INT0 to INT7. “H” or “L” and “rising edge” or “falling edge” can be selected as the requested detection level
(except for NMI) . Also, four requests from INT0 to INT3 can be used as the DMA request.
• Block diagram
R BUS
8
Interruption permission register
9
Interruption
requests
Gate
8
9
Edge detection
circuit
Factor F/F
INT0 ∼ INT7
NMI
Interruption factor register
8
Request level setting register
• Register list
• External interruption permission register (ENIR)
Address
bit
7
6
5
4
000095H
EN7
EN6
EN5
3
2
1
0
EN3
EN2
EN1
EN0
11
10
9
8
ER4
ER3
ER2
ER1
ER0
12
11
10
9
8
LA6
LB5
LA5
LB4
LA4
EN4
• External interruption factors register (EIRR)
Address
bit
15
14
13
12
000094H
ER7
ER6
ER5
• Request level setting register (ELVR)
Address
bit
15
14
13
000098H
LB7
bit
000099H
LA7
LB6
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
Initial value Access
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
47
MB91110 Series
11. Delay Interruption Modules
This is a module to generate interruptions to switch tasks. This module can be used with software to generate
/ cancel interruption requests to the CPU.
• Block diagram
WRITE
Resource
request
ICR
IL
CMP
DICR
CMP
ICR
Delay interruption
ILM
Interruption controller
CPU
• Register list
Address
000430H
48
bit
7
6
5
4
3
2
1
0
Initial value
Access
DLYI
- - - - - - - 0B
R/W
MB91110 Series
12. Interruption Controller
The interruption controller carries out interruption reception and arbitration.
• Hardware configuration of the interruption controller
This module is configured for the following items.
• ICR register
• Interruption priority judgement circuit
• Interruption level, interruption number (vector) generation area
• Cancellation request generation area for HOLD request
• Major interruption controller functions
This module has the following functions.
• Detection of NMI request / interruption request
• Priority grade judgement (depending on the level and number)
• Transferring interruption level of factors for the judgement results (to CPU)
• Transferring interruption number of factors for the judgement results (to CPU)
• Recovery instruction from stop mode by generating NMI / interruption
• Cancellation of HOLD request to the bus master
49
MB91110 Series
• Block Diagram
INT0*2
IM
Priority grade judgement
OR
5
NMI
processing
NMI
LEVEL
4∼0
4
LEVEL judgement
ICR00
RI00
VECTOR
judgement
6
Generation of
LEVEL
VECTOR
Cancellation request for
holding
HLDCAN*3
VCT5 ∼ 0
ICR47
RI47
(DLYIRQ)
DLYI*1
R-BUS
*1 : DLYI indicates delay interruption. (Refer to the chapter on delay interruption module for details.)
*2 : INTO is the wake-up signal to the clock control area in case of sleep or stop.
*3 : HLDCAN is the bus vacation request signal to bus masters other than the CPU.
50
MB91110 Series
• Register list
Address
000400H
bit
7
6
5
Initial value
Acces
ICR4 ICR3 ICR2 ICR1 ICR0
4
ICR00
- - - 11111
R/W
000401H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR01
- - - 11111
R/W
000402H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR02
- - - 11111
R/W
000403H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR03
- - - 11111
R/W
000404H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR04
- - - 11111
R/W
000405H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR05
- - - 11111
R/W
000406H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR06
- - - 11111
R/W
000407H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR07
- - - 11111
R/W
000408H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR08
- - - 11111
R/W
000409H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR09
- - - 11111
R/W
00040AH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR10
- - - 11111
R/W
00040BH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR11
- - - 11111
R/W
00040CH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR12
- - - 11111
R/W
00040DH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR13
- - - 11111
R/W
00040EH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR14
- - - 11111
R/W
00040FH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR15
- - - 11111
R/W
000410H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR16
- - - 11111
R/W
000411H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR17
- - - 11111
R/W
000412H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR18
- - - 11111
R/W
000413H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR19
- - - 11111
R/W
000414H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR20
- - - 11111
R/W
000415H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR21
- - - 11111
R/W
000416H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR22
- - - 11111
R/W
000417H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR23
- - - 11111
R/W
000418H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR24
- - - 11111
R/W
000419H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR25
- - - 11111
R/W
00041AH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR26
- - - 11111
R/W
00041BH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR27
- - - 11111
R/W
00041CH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR28
- - - 11111
R/W
00041DH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR29
- - - 11111
R/W
00041EH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR30
- - - 11111
R/W
00041FH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR31
- - - 11111
R/W
000420H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR32
- - - 11111
R/W
000421H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR33
- - - 11111
R/W
000422H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR34
- - - 11111
R/W
000423H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR35
- - - 11111
R/W
000424H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR36
- - - 11111
R/W
000425H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR37
- - - 11111
R/W
000426H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR38
- - - 11111
R/W
000427H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR39
- - - 11111
R/W
000428H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR40
- - - 11111
R/W
000429H
ICR4 ICR3 ICR2 ICR1 ICR0
ICR41
- - - 11111
R/W
00042AH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR42
- - - 11111
R/W
00042BH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR43
- - - 11111
R/W
00042CH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR44
- - - 11111
R/W
00042DH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR45
- - - 11111
R/W
00042EH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR46
- - - 11111
R/W
00042FH
ICR4 ICR3 ICR2 ICR1 ICR0
ICR47
- - - 11111
R/W
HRCL
- - - 11111
R/W
R
000431H
3
R/W
2
R/W
1
R/W
0
R/W
LVL4 LVL3 LVL2 LVL1 LVL0
R
R/W
R/W
R/W
R/W
51
MB91110 Series
13. Interruption Control Register (ICR)
This function is set up per interruption input and sets the interruption level of interruption requests to be handled.
• Register list
bit 7
6
5
4
3
2
1
0
ICR4
ICR3
ICR2
ICR1
ICR0
R
R/W
R/W
R/W
R/W
[bit 4 to 0] ICR4 to 0
The interruption level of the interruption requests that are handled is specified by the interruption level setting
bit. In cases where the interruption level that is set in this register is the same as or more than the level mask
value that is set (has been set) in the ILM register of the CPU, the interruption request is masked at the CPU
side. It is initialized to 11111B on resetting. The settable interruption level setting bit and interruption level are
shown in following Table.
Interruption Level Setting Bit and Interruption Level
ICR2
ICR1
ICR0
Interruption level
ICR4
ICR3
0
0
0
0
0
0
0
1
1
1
0
14
0
1
1
1
1
15
NMI
1
0
0
0
0
16
Maximum settable level
1
0
0
0
1
17
1
0
0
1
0
18
1
0
0
1
1
19
1
0
1
0
0
20
1
0
1
0
1
21
1
0
1
1
0
22
1
0
1
1
1
23
1
1
0
0
0
24
1
1
0
0
1
25
1
1
0
1
0
26
1
1
0
1
1
27
1
1
1
0
0
28
1
1
1
0
1
29
1
1
1
1
0
30
1
1
1
1
1
31
Note: ICR 4 is fixed as “1” and can not be written as “0”.
52
System reservation
(High)
(Low)
Interruption is prohibited
MB91110 Series
14. 10-bit A/D Converter
The A/D converter is the module that converts analog input voltages to a digital value.
•
•
•
•
•
Characteristics of A/D Converter
Minimum converting time : 5.6 µs/channel
Sample & hold circuit is built-in.
Resolution : 10 bits
Selection can be made for analog input from 8 channels.
Single conversion mode
: 1 channel is selected for conversion
Scan conversion mode
: Converts multiple number of consecutive channels.
Maximum 8 channels are programmable.
Consecutive conversion mode : Repeatedly converts the specified channel.
Suspension / conversion mode : Suspends after converting 1 channel and waits until the next one is
started up (synchronization for starting conversion is possible)
• Initiation of DMA transfer by interruption is possible.
• Initiation factor can be selected from software, external trigger (falling edge) or reload timer (rising edge) .
• Block Diagram
AVCC
AVR
AVSS
Internal voltage generator
MPX
AN0
AN2
AN3
AN4
Input circuit
AN1
Sequential comparison
register
R
|
B
U
S
Comparator
AN5
AN6
AN7
Sample & hold circuit
Data register
Decoder
ADCR
A/D control register 1
ATG
ADCS
Starting up External trigger
TIM0 (Internal connection)
(Reload timer channel 0)
Starting up timer
φ
Operation clock
Pre-scalar
(Peripheral system clock)
53
MB91110 Series
• Register List
• Control Status Register (ADCS)
bit
Address
00003AH
Initial value Access
15
14
13
12
11
10
9
8
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
00000000B
R/W
00000000B
R/W
bit
00003BH
7
6
5
4
3
2
1
0
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
15
14
13
12
11
10
9
8
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
• Data Register (ADCR)
bit
Address
000038H
Initial value Access
- - - - - - XXB
R
XXXXXXXXB
R
bit
000039H
54
MB91110 Series
15. UART
UART is the serial I/O port for carrying out asynchronous (start-stop synchronization) or CLK synchronous
communication.
•
•
•
•
•
•
•
•
•
Characteristics of UART
FDX double buffer
Asynchronous (start-stop synchronization) and CLK synchronous communication are possible.
Supports multi processor mode
Dedicated baud rate generator is built-in.
Free baud rate can be set using an external clock.
Error detection function (parity, framing, overrun)
Transfer signal is NRZ code
Initiation of DMA transfer is possible by interruption.
55
MB91110 Series
• Block Diagram
Control signal
Reception interruption
(to CPU)
Dedicated baud
rate generator
SCK
16-bit reload timer
(internal connection)
Transmission
interruption (to CPU)
Transmission clock
Clock selection
circuit
Reception clock
External clock
SI
Reception
control circuit
Transmission
control circuit
Start bit
detection circuit
Transmission
starting circuit
Reception bit
counter
Transmission
bit counter
Reception parity
counter
Transmission
parity counter
SO
Reception status
judgement circuit
Shifter for
transmission
Shifter for reception
End of
reception
Start
transmission
SIDR
SODR
Reception error
generation signal
for DMA (to DMAC)
R - BUS
SMR
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signal
56
MB91110 Series
• Register List
• Serial Mode Register (SMR)
Address
bit
7
6
000023H
MD1
MD0
• Serial Control Register (SCR)
bit
15
14
000022H
PEN
P
4
3
2
1
0
CS2
CS1
CS0
SCKE
SOE
00000 - 00B
R/W
13
12
11
10
9
8
Initial value
Access
SBL
CL
A/D
REC
RXE
TXE
00000100B
R/W
0
Initial value
Access
XXXXXXXXB
R/W
• Serial Input Data Register/Serial Output Data Register (SIDR/SODR)
bit
7
6
5
4
3
2
1
000021H
D6
D5
D4
D3
D2
D1
D0
• Serial Status Register (SSR)
bit
15
14
13
12
11
10
9
8
FRE
RDRF
TDRE
RIE
TIE
000020H
D7
PE
ORE
• Communication Pre-scalar Control Register (CDCR)
bit
7
6
5
4
3
000025H
MD
Initial value Access
5
DIV4
DIV3
2
1
0
DIV2
DIV1
DIV0
Initial value Access
00001 - 00B
R/W
Initial value Access
0 - - 11111B
R/W
57
MB91110 Series
16. DMA Controller (DMAC)
The DMA controller is the module to realize Direct Memory Access (DMA) transfers with FR 30 series devices.
DMA transfers controlled by this module enable quick and direct transfer of all data without using the CPU and
thus system performance is increased.
• Hardware Configuration of DMA Controller
This module is mainly configured of the following items.
• Internal I/O access control circuit
• 32-bit address counters (possible reload specification : 10)
• 16-bit transfer number counters (possible reload specification : 5)
• External transfer request input pin : DREQ0, DREQ1, DREQ2
• External transfer request reception output pin : DACK0, DACK1, DACK2 (external bus synchronization)
• External transfer termination output pin : DEOP0, DEOP1, DEOP2 (external bus synchronization)
• Major Function of DMA Controller
There are the following functions for data transfer using this module.
• Independent data transfer of a number of channels is possible (5 ch)
• Priority ranking amongst channels
Fixed ranking (ch.0 > ch.1 > ch.2 > ch.3 > ch.4)
Ranking between channel 0 and 1 can be reversed.
• Transfer request
Dedicated external pin input (Edge detection / level detection selection are possible for channels 0 to 2 only.)
Built-in peripheral request (interruption requests are shared. External interruption is included.)
Software request (register writing)
• Transfer sequence
Consecutive / burst transfer
Step transfer / block transfer (Maximum 16 words are settable.)
• Addressing mode : 32-bit full address specification (increase / decrease / fix)
• Data types : Byte, half word, word length
• Single shot or reload can be selected.
58
MB91110 Series
• Block Diagram
DREQ0
DREQ1
DREQ2
Peripheral interruption
request
Peripheral interruption
request
External input
setting
Input setting register
Each channel
request setting
Request setting register
Each channel
transfer mode setting
Mode setting register
External transfer
request input
Detection / processing
External transfer
request
Transfer request
processing
Each channel request
Controls arbitration of
requests, priority
judgement and decision
on transferring channels
Transfer start
request
Address control register
Each channel
address generation
control
Channel
instruction
DACK0
DACK1
DACK2
End
Counter of the number
of transfer times
Interruption
control
ACK.
Data control
Address registers
No. of times registers
D−BUS
DEOP0
DEOP1
DEOP2
Transfer state
machine
(bus control)
Control counting
address /
the number of times
No.
of times
Hold request
Address
Address counter
Hold control
Data buffer
FR30 CPU
59
MB91110 Series
• Register List
Address
bit 31
Initial value
Access
R/W
000200H
ch.0 Control/status register
DMACS0
0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0B
XX - 0 0 0 0 0 - - - - XX - XB
000204H
ch.0 Addressing/transfer counting register
DMACC0
- - - - XXXX XXXX - XXXB
XXXXXXXX XXXXXXXXB
R/W
000208H
ch.0 Transfer originator address register
DMASA0
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
R/W
00020CH
ch.0 Destination address register
DMADA0
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
R/W
000210H
ch.1 Control/status register
DMACS1
0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0B
XX - 0 0 0 0 0 - - - - XX - XB
R/W
000214H
ch.1 Addressing/transfer counting register
DMACC1
- - - - XXXX XXXX - XXXB
XXXXXXXX XXXXXXXXB
R/W
000218H
ch.1 Transfer originator address register
DMASA1
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
R/W
00021CH
ch.1 Destination address register
DMADA1
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
R/W
000220H
ch.2 Control/status register
DMACS2
0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0B
XX - 0 0 0 0 0 - - - - XX - XB
R/W
000224H
ch.2 Addressing/transfer counting register
DMACC2
- - - - XXXX XXXX - XXXB
XXXXXXXX XXXXXXXXB
R/W
000228H
ch.2 Transfer originator address register
DMASA2
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
R/W
00022CH
ch.2 Destination address register
DMADA2
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
R/W
000230H
ch.3 Control/status register
DMACS3
0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0B
XX - 0 0 0 0 0 - - - - XX - XB
R/W
000234H
ch.3 Addressing/transfer counting register
DMACC3
- - - - XXXX XXXX - XXXB
XXXXXXXX XXXXXXXXB
R/W
000238H
ch.3 Transfer originator address register
DMASA3
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
R/W
00023CH
ch.3 Destination address register
DMADA3
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
R/W
000240H
ch.4 Control/status register
DMACS4
0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0B
XX - 0 0 0 0 0 - - - - XX - XB
R/W
000244H
ch.4 Addressing/transfer counting register
DMACC4
- - - - XXXX XXXX - XXXB
XXXXXXXX XXXXXXXXB
R/W
000248H
ch.4 Transfer originator address register
DMASA4
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
R/W
00024CH
ch.4 Destination address register
DMADA4
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
R/W
000250H
Overall control register
DMACR
- - - - - - - - - - - - - - - -B
0 0 - - - - - - - - - - - - - 0B
R/W
*: Shaded areas indicate where nothing exists.
60
0
MB91110 Series
17. Bit Search Module
Bit search module searches for 0, 1 or change points on data that has been written in the input register, and
returns the detected bit position.
• Block Diagram
D-BUS
Input latch
Address
decoder
Detection
mode
Changing to 1 detection data
Bit search circuit
Detection results
• Registers List
Address
31
Initial value
0
0003F0H
Data register for 0 detection(BSD0)
0003F4H
Data register for 1 detection(BSD1)
0003F8H
Data Register for Change Point Detection(BSDC)
0003FCH
Detection Results Register(BSRR)
Access
XXXXXXXX XXXXXXXB
XXXXXXXX XXXXXXXB
XXXXXXXX XXXXXXXB
XXXXXXXX XXXXXXXB
XXXXXXXX XXXXXXXB
XXXXXXXX XXXXXXXB
XXXXXXXX XXXXXXXB
XXXXXXXX XXXXXXXB
W
R/W
W
R
18. I-RAM
This type has 16 KB of built-in I-RAM (RAM dedicated for instructions) . Efficient processing becomes possible
by pre-arranging interruption processing programs and such like in this area. Writing on I-RAM is possible via
the data bus and is used in case of debugging.
• Register List
IRMC
7
6
5
4
3
2
1
0
Address : 0003EFH
IRMD
Initial value Access
-------0
R/W
61
MB91110 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
(VSS = AVSS = AVRL = 0 V)
Symbol
Rating
Unit
Remarks
Min.
Max.
VCC5
VCC3 − 0.3
VSS + 6.0
V
*1
VCC3
VSS − 0.3
VSS + 3.6
V
*1
Analog power voltage
AVCC
VSS − 0.3
VSS + 3.6
V
*2
Standard analog voltage
AVRH
VSS − 0.3
VSS + 3.6
V
*2
Input voltage
VI
VSS − 0.3
VCC5 + 0.3
V
Analog pin input voltage
VIA
VSS − 0.3
AVCC + 0.3
V
Output voltage
VO
VSS − 0.3
VCC5 + 0.3
V
Maximum “L” level output current
IOL
10
mA
*3
Average “L” level output current
IOLAV
4
mA
*4
Maximum total “L” level output current
ΣIOL
100
mA
ΣIOLAV
50
mA
*5
IOH
−10
mA
*3
Average “H” level output current
IOHAV
−4
mA
*4
Maximum total “H” level output current
ΣIOH
−50
mA
ΣIOHAV
−20
mA
Electricity consumption
PD
650
mW
Operating temperature
TA
0
+70
°C
Tstg
−55
+150
°C
Power voltage
Average “L” level total output current
Maximum “H” level output current
Average “H” level total output current
Storage temperature
*5
*1 : VCC3/VCC5 must not be lower than VSS − 0.3 V.
*2 : Care must be taken that this does not exceed VCC + 0.3 V when the power is turned on.
*3 : Peak value of the pin concerned is regulated as the maximum output current.
*4 : Average current within 100 ms flowing in the pin concerned is regulated as the average output current.
*5 : Average current within 100 ms flowing in all pins concerned is regulated as the average total output current.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
62
MB91110 Series
2. Recommended Operating Conditions
Parameter
Symbol
VCC5
Power voltage
(VSS = AVSS = AVRL = 0 V)
Value
Min.
Max.
4.5
5.5
Unit
Remarks
V
Keeping RAM status in the
case of normal operations /
stopping
VCC3
3.135
3.465
Analog power voltage
AVCC
VSS − 3.0
VSS + 3.465
V
Standard analog voltage
AVRH
AVSS
AVCC
V
TA
0
+70
°C
Operating temperature
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
63
MB91110 Series
3. DC Characteristics
Parameter
“H” level
input voltage
“L” level
input voltage
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Sym
bol
Pin name
Conditions
VIH
Input excluding
following
VIHS Refer to *
VIL
Input excluding
following
VILS Refer to *
Value
Unit
Min.
Typ.
Max.
0.65 ×
VCC3
VCC5 +
0.3
V
0.8 ×
VCC3
VCC5 +
0.3
V
VSS − 0.3
0.25 ×
VCC3
V
VSS − 0.3
0.2 ×
VCC3
V
“H” level
output voltage
VOH
VCC5 = 4.5 V
IOH = −4.0 mA
VCC5 −
0.5
V
“L” level
output voltage
VOL
VCC5 = 4.5 V
IOL = 4.0 mA
0.4
V
ILI
VCC5 = 5.5 V
0.45 V
< VI < VCC5
−5
+5
µA
RPULL
RST
VCC5 = 5.5 V
VI = 0.45 V
25
50
200
kΩ
50
70
mA
100
150
mA
20
30
mA
50
70
mA
Input leak
current (Hi-Z
output leak
current)
Pull-up
resistance
value
VCC5
ICC
VCC3
VCC5
Power current
ICCS
VCC3
VCC5
ICCH
Input capacity
CIN
VCC3
Other than VCC,
AVCC, AVSS and
VSS
fC = 12.5 MHz
VCC5 = 5.5 V
VCC3 = 3.465 V
fC = 12.5 MHz
VCC5 = 5.5 V
VCC3 = 3.465 V
TA = 25 °C
VCC5 = 5.5 V
VCC3 = 3.465 V
10
20
µA
200
900
µA
10
pF
Remarks
Hysteresis input
Hysteresis input
(4 times) in
case of 50 MHz
operation
In case of
sleeping
In case of
stopping
* : Hysteresis input pins : RST, HST, NMI, PE0/ATG, PE1/TRG0, 3, PE2/TRG1, 4, PE3/TRG2, 5,
PF0/INT0 to PF7/INT7, PG0/DREQ0, PG3/DREQ1, PH0/DREQ2, PH3/SI, PH5/SCK,
PH6/TI0, PI0/TI1, BGRNT/P81, WR1/P85, CS1/PA0 to CLK/PA6,
RAS0/PB0 to DW1/PB7
64
MB91110 Series
4. AC Characteristics
Measurement Conditions
The following conditions are applied to items without particular specifications.
• Alternating current standard measurement condition
VCC5 : 5.0 V ± 10%
Input
VCC5
Output
VIH
VOH
VIL
VOL
• Load condition
Output pin
C = 50 pF
0V
VIH
2.4 V
VOH
2.4 V
VIL
0.8 V
VOL
0.8 V
65
MB91110 Series
(1) Clock Timing
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Value
Pin
Conditions
Name
Unit
Min.
Max.
10.0
12.5
MHz
80
100
ns
Remarks
Clock frequency (1)
fC
X0
X1
Clock cycle time
tC
X0
X1
Frequency fluctuation rate*1
(when locked)
∆f
5
%
Clock frequency (2)
fC
X0
X1
10
25
MHz
Self oscillation
(1/2 cycle input)
Clock frequency (3)
fC
X0
X1
10
25
MHz
External clock
(1/2 cycle input)
Clock cycle time
tC
X0
X1
40
100
ns
PWH
PWL
X0
X1
10
ns
Clock is input to
X0/X1
PWH
X0
25
ns
Clock is input to
X0 only
tCR
tCF
X0
X1
8
ns
(tCR + tCF)
Input clock pulse width
Input clock
rising/falling time
0.625*2
fCP
Internal operation
clock frequency
fCPB
fCPP
tCP
Internal operation
clock cycle time
50
0.625*
2
25*
0.625*
2
25
tCPB
tCPP
CPU system
3
MHz Bus system
Peripheral system
20
1600*2
40*3
1600*2
40
Self oscillation 12.5
MHz
Internal 50 MHz
operation (via PLL,
4 times)
2
1600*
CPU system
ns
Bus system
Peripheral system
*1 : Frequency fluctuation rate indicates the maximum fluctuation ratio from the setting central frequency during
locking in case of doubling.
+α
∆f =
α
fO
×100 (%)
Central frequency fO
−α
*2 : This is the value when 10 MHz, which is the minimum value of the clock frequency, is input to X0 and 1/2 cycle
of the oscillation circuit and gearing of 1/8 are used.
*3 : This is the value when doubler is used with a 50 MHz CPU.
66
MB91110 Series
• Clock timing standard measurement conditions
tC
0.8 VCC5
0.2 VCC5
PWL
PWH
tCR
tCF
• Guaranteed operating area
5.5
Power voltage
VCC5
Guaranteed operating area (TA = 0 ∼ +70 °C)
fCPP is the shaded area.
4.5
3.465
VCC3
3.135
0 0.625
25
50
fCP / fCPP
(MHz)
Internal clock
67
MB91110 Series
• External/internal clock settable area
fCP / fCPP (MHz)
Internal clock settable limit
fCP
50
CPU
40
PLL system
(12.5 MHz / 4 times)
fCPP
Peripheral
25
20
1/2 cycle system
12.5
5
0
0
10 12.5
External clock
25
fC
(MHz)
Original oscillation
input clock
self oscillation
Notes: • 10.0 MHz to 12.5 MHz must be input for external clock input when PLL is used.
• PLL oscillation stabilization time should be larger than 100 µs.
• Internal clock gear should be set within the above range.
68
MB91110 Series
(2) Clock Output Timing
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Symbol
Parameter
Cycle time
tCYC
Pin
Name
Value
Conditions
CLK
Min.
Max.
tCP
2 × tCP
Unit
Remarks
*1
ns
In case of using
doubler
CLK ↑ → CLK ↓
tCHCL
CLK
1 / 2 × tCYC − 10 1 / 2 × tCYC + 10
ns
*2
CLK ↓ → CLK ↑
tCLCH
CLK
1 / 2 × tCYC − 10 1 / 2 × tCYC + 10
ns
*3
tCYC
tCHCL
CLK
tCLCH
VOH
VOH
VOL
*1 : tCYC is frequency of 1 clock cycle including the gear cycle.
*2 : This standard value is in the case where the gear cycle is 1.
If the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing
n with 1/2, 1/4 or 1/8.
• Minimum : (1 − n / 2) × tCYC − 10
• Maximum : (1 − n / 2) × tCYC + 10
Gear cycle of 1 should be taken when using a doubler.
*3 : This standard value is in the case where the gear cycle is 1.
If the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing
n with 1/2, 1/4 or 1/8.
• Minimum : n / 2 × tCYC − 10
• Maximum : n / 2 × tCYC + 10
Gear cycle of 1 should be taken when using a doubler.
69
MB91110 Series
The relationship between the CLK pin set using CHC/CCK1/CCK0 bit of the “Gear Control Register” (GCR) and
original oscillation input is as follows. However, original oscillation input indicates “X0 input clock” in this figure.
(When using doubler)
• PLL system (CHC bit of GCR : “0”setting)
Original oscillation input
tCYC
(a) Gear × 1 CLK pin
CCK1/0 : "00"
SLCT1, 0 : 01
or
CCK1, 0 : 01
SLCT1, 0 : 1X
• 2 cycles system (CHC bit of GCR : “1”setting)
Original oscillation input
tCYC
(a) Gear × 1 CLK pin
CCK1/0: “00”
tCYC
(b) Gear × 1/2 CLK pins
CCK1/0: “01”
tCYC
(c) Gear × 1/4 CLK pins
CCK1/0: “10”
tCYC
(d) Gear × 1/8 CLK pins
CCK1/0: “11”
70
MB91110 Series
(3) Reset / Hardware Standby Input
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Symbol
Pin
Name
Conditions
Reset input time
tRSTL
RST
Hardware standby input time
tHSTL
HST
Parameter
Value
Unit
Min.
Max.
tCP × 5
ns
tCP × 5
ns
Remarks
tRSTL, tHSTL
RST
HST
0.2 VCC5
71
MB91110 Series
(4) Power On Reset
Parameter
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Symbol
Pin
Name
Conditions
Value
Min.
VCC5 = 5 V
Power startup time
Max.
Unit
Remarks
ms
VCC is less than
0.2 V before
power is turned
on.
Repeated
operation
30
tR
VCC5
Power cut time
tOFF
VCC3
1
ms
Waiting time for
oscillation stabilization
tOSC
2 × tC × 221
+ 100 µs
ns
VCC3 = 3.3 V
18
tR
0.9 × VCC3
0.2 VCC3
VCC3
tOFF
• Other Points to Note
(1) Sudden changes in the power supply voltage may cause a power-on reset .To change the power
supply voltage while the device is in operation, it is recommended to rise the voltage smoothly to
suppress fluctuations as shown below.
VCC3
It is recommended to keep the rising speed of
the supply voltage at 50 mV/ms or slower.
VSS
(2) When power is turned on, it must be started while the RST pin is set to “L” level, after which wait for
tRSTL and change the level to “H” once the Vcc power level is reached.
VCC5
VCC3
VCC3 / AVCC / AVRH should be supplied after supplying VCC5.
AVCC / AVRH should be supplied at the same time after supplying VCC3.
tOSC (Waiting time for oscillation stabilization)
RST
tRSTL
72
MB91110 Series
(5) Normal Bus Access Read/Write Operation
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Symbol
Parameter
Pin Name
Conditions
Value
Unit Remarks
Min.
Max.
15
ns
15
ns
CS0 to CS5 delay time
tCHCSL
CS0 to CS5 delay time
tCHCSH
Address delay time
tCHAV
CLK
A23 to A00
15
ns
Data delay time (write)
tCHDV
CLK
D31 to D16
15
ns
RD delay time
tCLRL
10
ns
RD delay time
tCLRH
10
ns
WR0 to WR1 delay time
tCLWL
10
ns
WR0 to WR1 delay time
tCLWH
10
ns
Valid address →
Valid data input time
tAVDV
3 / 2 × tCYC − 40
ns
*1
*2
RD ↓ →
Valid data input time
tRLDV
tCYC − 25
ns
*1
25
ns
0
ns
Data setup →
RD ↑ time
RD ↑ →
Data holding time
Read
tDSRH
tRHDX
CLK
CS0 to CS5
CLK
RD
CLK
WR0 to WR1
A23 to A00
D31 to D16
RD
D31 to D16
*1 : Time (tCYC × number of cycles extended) needs to be added to this standard if the bus is extended by automatic
waiting insertion and RDY input.
*2 : Values of this standard are in case of gear cycle × 1.
If the gear cycle is set to 1/2, 1/4 or 1/8, calculations should be made using the following formula and replacing
n with 1/2, 1/4 or 1/8.
• Calculation formula : (2 − n / 2) × tCYC − 40
73
MB91110 Series
tCYC
BA2
BA1
CLK
2.4 V
2.4 V
2.4 V
0.8 V
0.8 V
0.8 V
tCHCSH
tCHCSL
CS0 ∼ CS5
2.4 V
0.8 V
tCHAV
A23 ∼ A00
2.4 V
0.8 V
2.4 V
0.8 V
tCLRL
tCLRH
RD
2.4 V
0.8 V
tRLDV
tRHDX
tAVDV
2.4 V
0.8 V
D31 ∼ D16
Read
2.4 V
0.8 V
tDSRH
tCLWL
WR0 ∼ WR1
2.4 V
0.8 V
tCLWH
tCHDV
D31 ∼ D16
74
2.4 V
0.8 V
Write
2.4 V
0.8 V
MB91110 Series
(6) Ready Input Timing
Parameter
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Symbol
Pin Name Conditions
RDY setup time
→ CLK ↓
tRDYS
RDY
CLK
CLK ↓ →
RDY holding time
tRDYH
RDY
CLK
Value
Unit
Min.
Max.
20
ns
0
ns
Remarks
tCYC
CLK
2.4 V
2.4 V
0.8 V
tRDYH
tRDYS
RDY
(If "wait"
is executed)
0.8 V
RDY
2.4 V
(If "wait" is
not executed)
0.8 V
tRDYH
tRDYS
2.4 V
0.8 V
75
MB91110 Series
(7) Holding timing
Parameter
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Symbol
BGRNT delay time
tCHBGL
BGRNT delay time
tCHBGH
Pin floating →
BGRNT ↓ time
tXHAL
BGRNT ↑ →
Pin valid time
tHAHV
Pin Name
Value
Conditions
CLK
BGRNT
Unit
Min.
Max.
10
ns
10
ns
tCYC − 10
tCYC + 10
ns
tCYC − 10
tCYC + 10
ns
BGRNT
Note : It takes at least one cycle from loading the BRQ to when BGRNT is changed.
tCYC
CLK
2.4 V
2.4 V
2.4 V
2.4 V
BRQ
tCHBGL
BGRNT
2.4 V
0.8 V
tXHAL
tHAHV
Each pin
High impedance
76
tCHBGH
Remarks
MB91110 Series
(8) Read/Write Cycle of the Normal DRAM Mode
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Pin Name
Conditions
Value
Unit Remarks
Min.
Max.
10
ns
10
ns
10
ns
10
ns
15
ns
15
ns
15
ns
15
ns
RAS delay time
tCLRAH
RAS delay time
tCHRAL
CAS delay time
tCLCASL
CAS delay time
tCLCASH
ROW address delay time
tCHRAV
COLUMN address delay time
tCHCAV
DW delay time
tCHDWL
DW delay time
tCHDWH
Output data delay time
tCHDV1
CLK
D31 to D16
15
ns
RAS ↓ → valid data input time
tRLDV
RAS
D31 to D16
5/2×
tCYC − 20
ns
*1
*2
CAS ↓ → valid data input time
tCLDV
tCYC − 17
ns
*1
CAS ↑ → data holding time
tCADH
0
ns
CLK
RAS
CLK
CAS
CLK
A23 to A00
CLK
DW
CAS
D31 to D16
*1 : If either the Q1 or A4 cycle is extended for one cycle, the tCYC time needs to be added to this standard.
*2 : Values of this standard are in case of gear cycle × 1.
If the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing
n with 1/2, 1/4 or 1/8.
• Calculation formula : (3 − n / 2) × tCYC − 20
77
MB91110 Series
tCYC
Q1
CLK
Q2
Q3
2.4 V
Q4
Q5
0.8 V
0.8 V
2.4 V
2.4 V
0.8 V
2.4 V
RAS
0.8 V
tCHRAL
tCLRAH
tCLCASL
CAS
0.8 V
2.4 V
0.8 V
2.4 V
tCHCAV
tCHRAV
A23 ∼ A00
tCLCASH
ROW address
2.4 V
0.8 V
2.4 V
2.4 V
COLUMN address
0.8 V
0.8 V
tRLDV
tCLDV
2.4 V
0.8 V
D31 ∼ D16
tCADH
Read
2.4 V
DW
0.8 V
tCHDWL
D31 ∼ D16
2.4 V
0.8 V
tCHDV1
78
2.4 V
0.8 V
Write
tCHDWH
2.4 V
0.8 V
MB91110 Series
(9) High Speed Page Read/Write Cycle of the Normal DRAM Mode
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Symbol
Pin Name
RAS delay time
tCLRAH
CLK, RAS
CAS delay time
tCLCASL
CAS delay time
tCLCASH
CLK
CAS
COLUMN address delay time
tCHCAV
Parameter
CLK
A23 to A00
DW delay time
tCHDWH
CLK, DW
Output data delay time
tCHDV1
CLK
D31 to D16
CAS ↓ → valid data input time
tCLDV
CAS ↑ → data holding time
tCADH
Conditions
CAS
D31 to D16
Value
Unit
Min.
Max.
10
ns
10
ns
10
ns
15
ns
15
ns
15
ns
tCYC − 17
ns
0
ns
Remarks
*
* : When Q4 cycle is extended for 1 cycle, add tCYC time to this rating.
79
MB91110 Series
Q5
CLK
2.4 V
Q4
Q5
0.8 V
0.8 V
Q4
Q5
2.4 V
0.8 V
tCLRAH
2.4 V
RAS
tCLCASL
tCLCASH
2.4 V
CAS
0.8 V
tCHCAV
A23 ∼ A00
COLUMN address
2.4 V
0.8 V
2.4 V
0.8 V
COLUMN address
tCADH
tCLDV
D31 ∼ D16
2.4 V
0.8 V
Read
COLUMN address
Read
2.4 V
0.8 V
Read
tCHDWH
2.4 V
DW
tCHDV1
D31 ∼ D16
80
2.4 V
0.8 V
Write
2.4 V
0.8 V
2.4 V
0.8 V
Write
MB91110 Series
(10) Single DRAM Timing
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
RAS delay time
tCLRAH2
RAS delay time
tCHRAL2
CAS delay time
tCHCASL2
CAS delay time
tCHCASH2
ROW address delay time
tCHRAV2
COLUMN address delay time
tCHCAV2
DW delay time
tCHDWL2
DW delay time
tCHDWH2
Output data delay time
tCHDV2
CAS ↓ → valid data input time
tCLDV2
CAS ↑ → data holding time
tCADH2
Pin Name
Conditions
CLK
RAS
CLK
CAS
CLK
A23 to A00
CLK
DW
CLK
D31 to D16
CAS
D31 to D16
Value
Unit
Min.
Max.
10
ns
10
ns
n / 2 × tCYC
+8
ns
10
ns
15
ns
15
ns
15
ns
15
ns
15
ns
(1 − n / 2) ×
tCYC − 17
ns
0
ns
Remarks
81
MB91110 Series
tCYC
*1
Q1
CLK
2.4 V
0.8 V
Q2
Q3
2.4 V
Q4S
2.4 V
0.8 V
tCHRAL2
tCLRAH2
Q4S
2.4 V
2.4 V
2.4 V
2.4 V
RAS
Q4S
tCHCASH2
tCHCASL2
2.4 V
CAS
2.4 V
0.8 V
2.4 V
A23 ∼ A00
2.4 V
0.8 V
ROW address
tCHRAV2
2.4 V
0.8 V
COLUMN-0
COLUMN-1
COLUMN-2
0.8 V
tCHCAV2
tCADH2
tCLDV2
D31 ∼ D16
(Read)
Read-0
DW
(Write)
2.4 V
0.8 V Read-1
2.4 V
*2
2.4 V
0.8 V
tCHDV2
tCHDWH2
Write-0
2.4 V
2.4 V
0.8 V
tCHDV2
2.4 V
0.8 V
2.4 V
Write-1
0.8 V
Write-2
0.8 V
*1 : Q4S cycle indicates the Q4SR (read) or Q4SW (write) cycle of the Single DRAM cycle.
*2 :
indicates when a bus cycle is started from the high-speed page mode.
82
Read-2
0.8 V
tCHDWL2
D31 ∼ D16
(Write)
2.4 V
0.8 V
MB91110 Series
(11) Hyper DRAM Timing
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
RAS delay time
tCLRAH3
RAS delay time
tCHRAL3
CAS delay time
tCHCASL3
CAS delay time
tCHCASH3
ROW address delay time
tCHRAV3
COLUMN address delay time
tCHCAV3
RD delay time
tCHRL3
RD delay time
tCHRH3
RD delay time
tCLRL3
DW delay time
tCHDWL3
DW delay time
tCHDWH3
Output data delay time
tCHDV3
CAS ↓ → valid data input time
tCLDV3
CAS ↓ → data holding time
tCADH3
Pin Name
Conditions
CLK
RAS
CLK
CAS
CLK
A23 to A00
CLK
RD
CLK
DW
CLK
D31 to D16
CAS
D31 to D16
Value
Unit Remarks
Min.
Max.
10
ns
10
ns
n / 2 × tCYC
+8
ns
10
ns
15
ns
15
ns
15
ns
15
ns
15
ns
15
ns
15
ns
15
ns
tCYC − 20
ns
0
ns
83
MB91110 Series
tCYC
*1
Q1
CLK
2.4 V
Q2
Q3
2.4 V
2.4 V
0.8 V
2.4 V
RAS
Q4H
Q4H
2.4 V
2.4 V
0.8 V
0.8 V
tCHRAL3
tCLRAH3
Q4H
tCHCASH3
tCHCASL3
CAS
0.8 V
2.4 V
0.8 V
0.8 V
COLUMN-1
COLUMN-2
2.4 V
A23 ∼ A00
V
2.4 V
ROW address 2.4
0.8 V
0.8 V
tCHRAV3
tCHCAV3
COLUMN-0
0.8 V
*2
RD
(Read)
0.8 V
2.4 V
0.8 V
tCHRL3
tCHRH3
tCLRL3
tCLDV3
tCADV3
2.4 V
Read-0
0.8 V
D31 ∼ D16
(Read)
DW
(Write)
2.4 V
*2
2.4 V
0.8 V
tCHDV3
tCHDWH3
Write-0
2.4 V
2.4 V
0.8 V
tCHDV3
2.4 V
0.8 V
2.4 V
Write-1
0.8 V
Write-2
0.8 V
*1 : Q4H cycle indicates the Q4HR (read) or Q4HW (write) cycle of the Hyper DRAM cycle.
*2 :
indicates when a bus cycle is started from the high-speed page mode.
84
2.4 V
0.8 V
0.8 V
tCHDWL3
D31 ∼ D16
(Write)
Read-1
MB91110 Series
(12) CBR Refresh
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Symbol
Parameter
RAS delay time
tCLRAH
RAS delay time
tCHRAL
CAS delay time
tCLCASL
CAS delay time
tCLCASH
CLK
RAS
RAS
10
ns
10
ns
10
ns
10
ns
R3
Remarks
R4
2.4 V
2.4 V
0.8 V
0.8 V
0.8 V
2.4 V
0.8 V
tCLRAH
CAS
Max.
CLK
CAS
R2
Unit
Min.
tCYC
R1
CLK
Value
Conditions
Pin Name
tCHRAL
0.8 V
tCLCASL
2.4 V
tCLCASH
DW
85
MB91110 Series
(13) Self Refresh
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Symbol
Parameter
RAS delay time
tCLRAH
RAS delay time
tCHRAL
CAS delay time
tCLCASL
CAS delay time
tCLCASH
tCYC
SR1
CLK
2.4 V
CLK
RAS
CLK
CAS
SR2
2.4 V
Conditions
Pin Name
SR3
Value
Unit
Min.
Max.
10
ns
10
ns
10
ns
10
ns
SR3
2.4 V
0.8 V
0.8 V
tCHRAL
tCLRAH
2.4 V
0.8 V
RAS
CAS
2.4 V
0.8 V
tCHCASL
86
Remarks
tCLCASH
MB91110 Series
(14) UART Timing
Parameter
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Symbol Pin Name
Value
Conditions
Unit
Min.
Max.
8 tCYCP
ns
−80
80
ns
100
ns
Serial clock cycle time
tSCYC
SCLK ↓ → SOUT
Delay time
tSLOV
Valid SIN → SCLK ↑
tIVSH
SCLK ↑ → Valid
SIN holding lock
tSHIX
60
ns
Serial clock “H” pulse width
tSHSL
4 tCYCP
ns
Serial clock “L” pulse width
tSLSH
4 tCYCP
ns
SCLK ↓ → SOUT
Delay time
tSLOV
150
ns
Valid SIN → SCLK ↑
tIVSH
60
ns
SCLK ↑ → Valid
SIN holding lock
tSHIX
60
ns
Internal shift
clock mode
External shift
clock mode
Remarks
Notes : • This is the AC standard in the case of CLK synchronous mode.
• tCYCP is the cycle time of the peripheral system clock.
87
MB91110 Series
• Internal shift clock mode
tSCYC
VOH
SCLK
VOL
VOL
tSLOV
VOH
SOUT
VOL
tSHIX
tIVSH
SIN
VIH
VIH
VIL
VIL
• External shift clock mode
tSLSH
tSHSL
VIH
SCLK
VIL
VIH
VIL
tSLOV
VOH
SOUT
VOL
tIVSH
SIN
88
tSHIX
VIH
VIH
VIL
VIL
MB91110 Series
(15) Trigger System Input Timing
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Parameter
SymPin Name
bol
A/D initiation trigger input time
PPG initiation trigger input time
Conditions
Value
Min.
Max.
TRG0 to
TRG5
Remarks
ns
ATG
tTRG
Unit
5 tCYCP
ns
Note : tCYCP is the cycle time of the peripheral system clock.
tTRG
ATG
TRG0
∼ TRG5
VIL
VIL
89
MB91110 Series
(16) DMA Controller Timing
(VCC5 = 5 V ± 10%, VCC3 = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Parameter
DREQ input pulse
width
DACK delay time
(Normal bus)
(Normal DRAM)
EOP delay time
(Normal bus)
(Normal DRAM)
DACK delay time
(Single DRAM)
(Hyper DRAM)
EOP delay time
(Single DRAM)
(Hyper DRAM)
Symbol
Value
Conditions
Pin Name
tDRWH DREQ0 to DREQ2
tCLDL
tCLDH
tCLEL
tCLEH
tCHDL
tCHDH
tCHEL
tCHEH
CLK
DACK0 to DACK2
CLK
DEOP0 to DEOP2
CLK
DACK0 to DACK2
CLK
DEOP0 to DEOP2
Max.
2 tCYC
ns
6
ns
6
ns
6
ns
6
ns
n / 2 × tCYC
ns
6
ns
n / 2 × tCYC
ns
6
ns
tCYC
CLK
2.4 V
2.4 V
0.8 V
0.8 V
tCLDL
tCLEL
DACK0 ∼ DACK2
DEOP0 ∼ DEOP2
tCLDH
tCLEH
2.4 V
0.8 V
DACK0 ∼ DACK2
DEOP0 ∼ DEOP2
(Single DRAM)
(Hyper DRAM)
2.4 V
0.8 V
tCHDL
tCHEL
tCHDH
tDRWH
DREQ0 ∼ DREQ2
90
2.4 V
Unit
Min.
2.4 V
Remarks
MB91110 Series
5. A/D Converter Electrical Characteristics
(VCC5 = 5 V ± 10%, VCC3 = AVCC = AVRH = 3.3 V ± 5%, VSS = AVSS = AVRL = 0 V, TA = 0 °C to +70 °C)
Symbol
Pin Name
Resolution
Conversion error
Parameter
Value
Unit
Min.
Typ.
Max.
10
10
BIT
±3.0
LSB
Linearity error
±2.5
LSB
Differential linearity error
±1.9
LSB
Zero transition error
VOT
AN0 to AN7
−1.5
+0.5
+2.5
LSB
Full-scale transition error
VFST
AN0 to AN7
AVRH − 4.5
AVRH − 1.5
AVRH + 0.5
LSB
Conversion time
5.6*
µs
Analog port input current
IAIN
AN0 to AN7
0.1
10
µA
Analog input voltage
VAIN
AN0 to AN7
AVSS
AVRH
V
AVRH
AVSS
AVCC
V
4
mA
5*2
µA
110
µA
5*
2
µA
4
Standard voltage
Power supply current
Standard voltage current supplied
Tolerance between channels
IA
IAH
IR
IRH
1
AVCC
AVRH
AN0 to AN7
LSB
*1 : In case of VCC3 = AVCC = 3.3 V ± 5%, machine clock 25 MHz
*2 : This is the current in the case that the A/D converter is not activated and the CPU is stopped (in case of VCC3
= AVCC = AVRH = 3.465 V)
Notes : • As the AVRH becomes smaller, the tolerance becomes relatively larger.
• Output impedance of external circuits other than analog input must be used under the following
condition.
Output impedance of external circuits < 7 kΩ
If the output impedance of the external circuits is too high, the sampling time for the analog voltage may be
insufficient.
91
MB91110 Series
Analog input
Sample holding circuit
C0
Comparator
RON1
RON2
RON3
RON4
C1
RON1 : 5 kΩ
RON2 : 620 Ω
RON3 : 620 Ω
RON4 : 620 Ω
C0 : 2 pF
C1 : 2 pF
Note : Figures described above should be considered as standard.
92
MB91110 Series
Definition of A/D Converter Terms
• Resolution
Analog changes that can be identified by A/D converter
• Linearity error
Difference between the straight line linking the zero transition point (00 0000 0000 ←→ 00 0000 0001) to the
full-scale transition point (11 1111 1110 ←→ 11 1111 1111) and actual conversion characteristics.
• Differential linearity error
Difference compared to the ideal input voltage value required to change the output code 1LSB
[Linearity error]
3FF
[Differential linearity error]
Ideal characteristics
Actual conversion characteristics
3FE
N+1
{1 LSB × (N − 1) + VOT}
Actual conversion
characteristics
VFST
(Actual
measured value)
004
Digital output
Digital output
3FD
VNT
(Actual measured value)
003
Actual conversion
characteristics
N
N−1
V(N + 1)T
(Actual measured value)
002
VNT
(Actual measured value)
Ideal characteristics
N−2
001
Actual conversion
characteristics
VOT (Actual measured value)
AVRL
AVRH
Analog input
AVRL
Analog input
Linearity error of digital output N
=
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
[LSB]
Differential linearity error of digital output N
=
V (N + 1) T − VNT
1 LSB
[LSB]
1 LSB =
VFST − VOT
1022
1 LSB (Ideal value) =
−1
AVRH
[V]
AVRH − AVRL
1024
[V]
VOT : Voltage with digital output transferred from (000) H to (001) H
VFST : Voltage with digital output transferred from (3FE) H to (3FF) H
VNT : Voltage with digital output transferred from (N − 1) H to N
93
MB91110 Series
• Total error
This indicates the difference between the actual and theoretical values and includes zero transition, full-scale
transition and linearity error.
[Total error]
3FF
1.5 LSB
3FE
Actual conversion
characteristics
3FD
Digital output
{1 LSB × (N − 1) + 0.5 LSB}
004
VNT
(Actual measured value)
003
Actual conversion
characteristics
002
Ideal characteristics
001
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
1 LSB
(Ideal value) = AVRL + 0.5 LSB [V]
Total tolerance of digital output N =
VOT
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : Voltage with digital output transferred from (N − 1) H to N
94
MB91110 Series
■ INSTRUCTIONS (165 INSTRUCTIONS)
1. How to Read Instruction Set Summary
Mnemonic
ADD
* ADD
↓
(1)
Rj,
Ri
#s5, Ri
,
,
↓
(2)
Type
OP
CYC
NZVC
Operation
A
C
,
,
A6
A4
,
,
1
1
,
,
CCCC
CCCC
,
,
Ri + Rj → Ri
Ri + s5 → Ri
,
,
↓
(3)
↓
(4)
↓
(5)
↓
(6)
↓
(7)
Remarks
(1) Names of instructions
Instructions marked with * are not included in CPU specifications. These are extended instruction codes
added/extended at assembly language levels.
(2) Addressing modes specified as operands are listed in symbols.
Refer to “2. Addressing mode symbols” for further information.
(3) Instruction types
(4) Hexa-decimal expressions of instructions
(5) The number of machine cycles needed for execution
a: Memory access cycle and it has possibility of delay by Ready function.
b: Memory access cycle and it has possibility of delay by Ready function.
If an object register in a LD operation is referenced by an immediately following instruction, the interlock
function is activated and number of cycles needed for execution increases.
c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or
if the instruction belongs to instruction format A group, the interlock function is activated and number of
cycles needed for execution increases by 1 to make the total number of 2 cycles needed.
d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number
of cycles needed for execution increases by 1 to make the total number of 2 cycles needed.
For a, b, c and d, minimum execution cycle is 1.
(6) Change in flag sign
• Flag change
C : Change
– : No change
0 : Clear
1 : Set
• Flag meanings
N : Negative flag
Z : Zero flag
V : Over flag
C : Carry flag
(7) Operation carried out by instruction
95
MB91110 Series
2. Addressing Mode Symbols
Ri
Rj
R13
Ps
Rs
CRi
CRj
#i8
: Register direct (R0 to R15, AC, FP, SP)
: Register direct (R0 to R15, AC, FP, SP)
: Register direct (R13, AC)
: Register direct (Program status register)
: Register direct (TBR, RP, SSP, USP, MDH, MDL)
: Register direct (CR0 to CR15)
: Register direct (CR0 to CR15)
: Unsigned 8-bit immediate (–128 to 255)
Note: –128 to –1 are interpreted as 128 to 255
#i20
: Unsigned 20-bit immediate (–0X80000 to 0XFFFFF)
Note: –0X7FFFF to –1 are interpreted as 0X7FFFF to 0XFFFFF
#i32
: Unsigned 32-bit immediate (–0X80000000 to 0XFFFFFFFF)
Note: –0X80000000 to –1 are interpreted as 0X80000000 to 0XFFFFFFFF
#s5
: Signed 5-bit immediate (–16 to 15)
#s10
: Signed 10-bit immediate (–512 to 508, multiple of 4 only)
#u4
: Unsigned 4-bit immediate (0 to 15)
#u5
: Unsigned 5-bit immediate (0 to 31)
#u8
: Unsigned 8-bit immediate (0 to 255)
#u10
: Unsigned 10-bit immediate (0 to 1020, multiple of 4 only)
@dir8
: Unsigned 8-bit direct address (0 to 0XFF)
@dir9
: Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only)
@dir10
: Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only)
label9
: Signed 9-bit branch address (–0X100 to 0XFC, multiple of 2 only)
label12
: Signed 12-bit branch address (–0X800 to 0X7FC, multiple of 2 only)
label20
: Signed 20-bit branch address (–0X80000 to 0X7FFFF)
label32
: Signed 32-bit branch address (–0X80000000 to 0X7FFFFFFF)
@Ri
: Register indirect (R0 to R15, AC, FP, SP)
@Rj
: Register indirect (R0 to R15, AC, FP, SP)
@(R13, Rj)
: Register relative indirect (Rj: R0 to R15, AC, FP, SP)
@(R14, disp10) : Register relative indirect (disp10: –0X200 to 0X1FC, multiple of 4 only)
@(R14, disp9) : Register relative indirect (disp9: –0X100 to 0XFE, multiple of 2 only)
@(R14, disp8) : Register relative indirect (disp8: –0X80 to 0X7F)
@(R15, udisp6) : Register relative (udisp6: 0 to 60, multiple of 4 only)
@Ri+
: Register indirect with post-increment (R0 to R15, AC, FP, SP)
@R13+
: Register indirect with post-increment (R13, AC)
@SP+
: Stack pop
@–SP
: Stack push
(reglist)
: Register list
96
MB91110 Series
3. Instruction Types
MSB
Type A
Type B
LSB
16 bits
OP
Rj
Ri
8
4
4
OP
i8/o8
Ri
4
8
4
Type C
OP
u4/m4
Ri
8
4
4
ADD, ADDN, CMP, LSL, LSR and ASR instructions only
Type *C’
Type D
Type E
Type F
OP
s5/u5
Ri
7
5
4
OP
u8/rel8/dir/reglist
8
8
OP
SUB-OP
Ri
8
4
4
OP
rel11
5
11
97
MB91110 Series
4. Detailed Description of Instructions
• Add/subtract operation instructions (10 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
ADD
* ADD
Rj, Ri
#s5, Ri
A
C’
A6
A4
1
1
C C C C Ri + Rj → Ri
C C C C Ri + s5 → Ri
ADD
ADD2
#i4, Ri
#i4, Ri
C
C
A4
A5
1
1
C C C C Ri + extu (i4) → Ri
C C C C Ri + extu (i4) → Ri
ADDC
Rj, Ri
A
A7
1
C C C C Ri + Rj + c → Ri
ADDN
* ADDN
Rj, Ri
#s5, Ri
A
C’
A2
A0
1
1
– – – – Ri + Rj → Ri
– – – – Ri + s5 → Ri
ADDN
ADDN2
#i4, Ri
#i4, Ri
C
C
A0
A1
1
1
– – – – Ri + extu (i4) → Ri
– – – – Ri + extu (i4) → Ri
SUB
Rj, Ri
A
AC
1
C C C C Ri – Rj → Ri
SUBC
Rj, Ri
A
AD
1
C C C C Ri – Rj – c → Ri
SUBN
Rj, Ri
A
AE
1
– – – – Ri – Rj → Ri
Remarks
MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension
Add operation with
sign
MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension
Subtract operation with
carry
• Compare operation instructions (3 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
CMP
* CMP
Rj, Ri
#s5, Ri
A
C’
AA
A8
1
1
C C C C Ri – Rj
C C C C Ri – s5
CMP
CMP2
#i4, Ri
#i4, Ri
C
C
A8
A9
1
1
C C C C Ri + extu (i4)
C C C C Ri + extu (i4)
Remarks
MSB is interpreted as
a sign in assembly
language
Zero-extension
Sign-extension
• Logical operation instructions (12 instructions)
98
Mnemonic
Type
OP
Cycle N Z V C
AND
AND
ANDH
ANDB
Rj, Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
A
A
A
A
82
84
85
86
1
1 + 2a
1 + 2a
1 + 2a
CC
CC
CC
CC
–
–
–
–
–
–
–
–
Ri &
(Ri) &
(Ri) &
(Ri) &
= Rj
= Rj
= Rj
= Rj
Word
Word
Half word
Byte
OR
OR
ORH
ORB
Rj, Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
A
A
A
A
92
94
95
96
1
1 + 2a
1 + 2a
1 + 2a
CC
CC
CC
CC
–
–
–
–
–
–
–
–
Ri
(Ri)
(Ri)
(Ri)
|
|
|
|
= Rj
= Rj
= Rj
= Rj
Word
Word
Half word
Byte
EOR
EOR
EORH
EORB
Rj, Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
A
A
A
A
9A
9C
9D
9E
1
1 + 2a
1 + 2a
1 + 2a
CC
CC
CC
CC
–
–
–
–
–
–
–
–
Ri ^
(Ri) ^
(Ri) ^
(Ri) ^
= Rj
= Rj
= Rj
= Rj
Word
Word
Half word
Byte
Operation
Remarks
MB91110 Series
• Bit manipulation arithmetic instructions (8 instructions)
Mnemonic
BANDL
BANDH
* BAND
BORL
BORH
* BOR
BEORL
BEORH
* BEOR
BTSTL
BTSTH
#u4, @Ri
(u4: 0 to 0FH)
#u4, @Ri
(u4: 0 to 0FH)
#u8, @Ri
#u4, @Ri
(u4: 0 to 0FH)
#u4, @Ri
(u4: 0 to 0FH)
#u8, @Ri
#u4, @Ri
(u4: 0 to 0FH)
#u4, @Ri
(u4: 0 to 0FH)
#u8, @Ri
Type
OP
Cycle N Z V C
C
80
1 + 2a – – – – (Ri) & = (F0H + u4)
Manipulate lower 4 bits
C
81
1 + 2a – – – – (Ri) & = ((u4<<4) + 0FH)
Manipulate upper 4 bits
–
*1
Remarks
– – – – (Ri) & = u8
C
90
1 + 2a – – – – (Ri) | = u4
Manipulate lower 4 bits
C
91
1 + 2a – – – – (Ri) | = (u4<<4)
Manipulate upper 4 bits
–
*2
– – – – (Ri) | = u8
C
98
1 + 2a – – – – (Ri) ^ = u4
Manipulate lower 4 bits
C
99
1 + 2a – – – – (Ri) ^ = (u4<<4)
Manipulate upper 4 bits
–
*3
#u4, @Ri
(u4: 0 to 0FH)
#u4, @Ri
(u4: 0 to 0FH)
Operation
– – – – (Ri) ^ = u8
C
88
2+a
0 C – – (Ri) & u4
Test lower 4 bits
C
89
2+a
C C – – (Ri) & (u4<<4)
Test upper 4 bits
*1: Assembler generates BANDL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BANDH if “u8&0xF0” leaves an active bit. Depending on the value in the “u8” format, both BANDL and BANDH
may be generated.
*2: Assembler generates BORL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BORH if “u8&0xF0” leaves an active bit.
*3: Assembler generates BEORL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BEORH if “u8&0xF0” leaves an active bit.
• Add/subtract operation instructions (10 instructions)
Mnemonic
Type
OP
Cycle N Z V C
MUL
MULU
MULH
MULUH
Rj, Ri
Rj, Ri
Rj, Ri
Rj, Ri
A
A
A
A
AF
AB
BF
BB
5
5
3
3
CCC
CCC
CC–
CC–
DIVOS
DIVOU
DIV1
DIV2
DIV3
DIV4S
* DIV
Ri
Ri
Ri
Ri
E
E
E
E
E
E
97 – 4
97 – 5
97 – 6
97 – 7
9F – 6
9F – 7
Ri
*1
1
1
d
1
1
1
–
–
–
–
–
–
–
–
* DIVU
Ri
*2
–
–
–
C
C
–
–
C
–
–
–
–
–
–
–
–
–
–
–
Operation
Rj × Ri → MDH, MDL
Rj × Ri → MDH, MDL
Rj × Ri → MDL
Rj × Ri → MDL
–
–
C
C
–
–
C MDL/Ri → MDL,
MDL%Ri → MDH
– C – C MDL/Ri → MDL,
MDL%Ri → MDH
Remarks
32-bit × 32-bit = 64-bit
Unsigned
16-bit × 16-bit = 32-bit
Unsigned
Step calculation
32-bit/32-bit = 32-bit
Unsigned
*1: DIVOS, DIV1 × 32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes.
*2: DIVOU and DIV1 × 32 are generated. A total instruction code length of 66 bytes.
99
MB91110 Series
• Shift arithmetic instructions (9 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
LSL
* LSL
LSL
LSL2
Rj, Ri
#u5, Ri
#u4, Ri
#u4, Ri
A
C’
C
C
B6
B4
B4
B5
1
1
1
1
CC
CC
CC
CC
–
–
–
–
C
C
C
C
Ri<<Rj → Ri
Ri<<u5 → Ri
Ri<<u4 → Ri
Ri<<(u4 + 16) → Ri
Logical shift
LSR
* LSR
LSR
LSR2
Rj, Ri
#u5, Ri
#u4, Ri
#u4, Ri
A
C’
C
C
B2
B0
B0
B1
1
1
1
1
CC
CC
CC
CC
–
–
–
–
C
C
C
C
Ri>>Rj → Ri
Ri>>u5 → Ri
Ri>>u4 → Ri
Ri>>(u4 + 16) → Ri
Logical shift
ASR
* ASR
ASR
ASR2
Rj, Ri
#u5, Ri
#u4, Ri
#u4, Ri
A
C’
C
C
BA
B8
B8
B9
1
1
1
1
CC
CC
CC
CC
–
–
–
–
C
C
C
C
Ri>>Rj → Ri
Ri>>u5 → Ri
Ri>>u4 → Ri
Ri>>(u4 + 16) → Ri
Logical shift
• Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer
instruction) (3 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
LDI: 32
LDI: 20
#i32, Ri
#i20, Ri
E
C
9F – 8
9B
3
2
– – – – i32 → Ri
– – – – i20 → Ri
LDI: 8
* LDI
#i8, Ri
# {i8 | i20 | i32}, Ri
*1
B
C0
1
– – – – i8 → Ri
{i8 | i20 | i32} → Ri
Remarks
Upper 12 bits are zeroextended
Upper 24 bits are zeroextended
*1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection.
If an immediate value contains relative value or external reference, assembler selects i32.
• Memory load instructions (13 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
(Rj) → Ri
(R13 + Rj) → Ri
(R14 + disp10) → Ri
(R15 + udisp6) → Ri
(R15) → Ri, R15 + = 4
(R15) → Rs, R15 + = 4
Remarks
LD
LD
LD
LD
LD
LD
@Rj, Ri
@(R13, Rj), Ri
@(R14, disp10), Ri
@(R15, udisp6), Ri
@R15 +, Ri
@R15 +, Rs
A
A
B
C
E
E
04
00
20
03
07 – 0
07 – 8
b
b
b
b
b
b
LD
@R15 +, PS
E
07 – 9
1+a+b
LDUH
LDUH
LDUH
@Rj, Ri
@(R13, Rj), Ri
@(R14, disp9), Ri
A
A
B
05
01
40
b
b
b
– – – – (Rj) → Ri
– – – – (R13 + Rj) → Ri
– – – – (R14 + disp9) → Ri
Zero-extension
Zero-extension
Zero-extension
LDUB
LDUB
LDUB
@Rj, Ri
@(R13, Rj), Ri
@(R14, disp8), Ri
A
A
B
06
02
60
b
b
b
– – – – (Rj) → Ri
– – – – (R13 + Rj) → Ri
– – – – (R14 + disp8) → Ri
Zero-extension
Zero-extension
Zero-extension
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
C C C C (R15) → PS, R15 + = 4
Rs: Special-purpose
register
Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler
description from disp8 to disp10 are as follows:
disp8 → o8 = disp8:Each disp is a code extension.
disp9 → o8 = disp9>>1:Each disp is a code extension.
disp10 → o8 = disp10>>2:Each disp is a code extension.
udisp6 → u4 = udisp6>>2:udisp4 is a 0 extension.
100
MB91110 Series
• Memory store instructions (13 instructions)
Mnemonic
Type
OP
Cycle N Z V C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Operation
Ri → (Rj)
Ri → (R13 + Rj)
Ri → (R14 + disp10)
Ri → (R15 + usidp6)
R15 – = 4, Ri → (R15)
R15 – = 4, Rs → (R15)
Remarks
ST
ST
ST
ST
ST
ST
Ri, @Rj
Ri, @(R13, Rj)
Ri, @(R14, disp10)
Ri, @(R15, udisp6)
Ri, @–R15
Rs, @–R15
A
A
B
C
E
E
14
10
30
13
17 – 0
17 – 8
a
a
a
a
a
a
–
–
–
–
–
–
Word
Word
Word
ST
PS, @–R15
E
17 – 9
a
– – – – R15 – = 4, PS → (R15)
STH
STH
STH
Ri, @Rj
Ri, @(R13, Rj)
Ri, @(R14, disp9)
A
A
B
15
11
50
a
a
a
– – – – Ri → (Rj)
– – – – Ri → (R13 + Rj)
– – – – Ri → (R14 + disp9)
Half word
Half word
Half word
STB
STB
STB
Ri, @Rj
Ri, @(R13, Rj)
Ri, @(R14, disp8)
A
A
B
16
12
70
a
a
a
– – – – Ri → (Rj)
– – – – Ri → (R13 + Rj)
– – – – Ri → (R14 + disp8)
Byte
Byte
Byte
Rs: Special-purpose
register
Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler
description from disp8 to disp10 are as follows:
disp8 → o8 = disp8:Each disp is a code extension.
disp9 → o8 = disp9>>1:Each disp is a code extension.
disp10 → o8 = disp10>>2:Each disp is a code extension.
udisp6 → u4 = udisp6>>2:udisp4 is a 0 extension.
• Transfer instructions between registers/special-purpose registers transfer instructions
(5 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
MOV
Rj, Ri
A
8B
1
– – – – Rj → Ri
MOV
Rs, Ri
A
B7
1
– – – – Rs → Ri
MOV
Ri, Rs
A
B3
1
– – – – Ri → Rs
MOV
MOV
PS, Ri
Ri, PS
E
E
17 – 1
07 – 1
1
c
– – – – PS → Ri
C C C C Ri → PS
Remarks
Transfer between
general-purpose
registers
Rs: Special-purpose
register
Rs: Special-purpose
register
101
MB91110 Series
• Non-delay normal branch instructions (23 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
JMP
@Ri
E
97 – 0
2
– – – – Ri → PC
CALL
label12
F
D0
2
CALL
@Ri
E
97 – 1
2
– – – – PC + 2 → RP,
PC + 2 + rel11 × 2 → PC
– – – – PC + 2 → RP, Ri → PC
E
97 – 2
2
– – – – RP → PC
D
1F
3+3a
RET
INT
#u8
Remarks
Return
– – – – SSP – = 4, PS → (SSP),
SSP – = 4,
PC + 2 → (SSP),
0 → I flag,
0 → S flag,
(TBR + 3FC – u8 × 4) → PC
INTE
E
9F – 3 3 + 3a – – – – SSP – = 4, PS → (SSP),
For emulator
SSP – = 4,
PC + 2 → (SSP),
0 → S flag,
(TBR + 3D8 – u8 × 4) → PC
RETI
E
97 – 3 2 + 2a C C C C (R15) → PC, R15 – = 4,
(R15) → PS, R15 – = 4
BNO
BRA
BEQ
BNE
BC
BNC
BN
BP
BV
BNV
BLT
BGE
BLE
BGT
BLS
BHI
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
E1
E0
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
1
2
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Non-branch
PC + 2 + rel8 × 2 → PC
PCif Z = = 1
PCif Z = = 0
PCif C = = 1
PCif C = = 0
PCif N = = 1
PCif N = = 0
PCif V = = 1
PCif V = = 0
PCif V xor N = = 1
PCif V xor N = = 0
PCif (V xor N) or Z = = 1
PCif (V xor N) or Z = = 0
PCif C or Z = = 1
PCif C or Z = = 0
Notes: • “2/1” in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch.
• The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and
assembler discription label9 and label12 are as follows.
label9 → rel8 = (label9 – PC – 2)/2
label12 → rel11 = (label12 – PC – 2)/2
• RETI must be operated while S flag = 0.
102
MB91110 Series
• Branch instructions with delays (20 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
JMP:D
@Ri
E
9F – 0
1
– – – – Ri → PC
CALL:D
label12
F
D8
1
CALL:D
@Ri
E
9F – 1
1
– – – – PC + 4 → RP,
PC + 2 + rel11 × 2 → PC
– – – – PC + 4 → RP, Ri → PC
E
9F – 2
1
– – – – RP → PC
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
F1
F0
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
RET:D
BNO:D
BRA:D
BEQ:D
BNE:D
BC:D
BNC:D
BN:D
BP:D
BV:D
BNV:D
BLT:D
BGE:D
BLE:D
BGT:D
BLS:D
BHI:D
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Remarks
Return
Non-branch
PC + 2 + rel8 × 2 → PC
PCif Z = = 1
PCif Z = = 0
PCif C = = 1
PCif C = = 0
PCif N = = 1
PCif N = = 0
PCif V = = 1
PCif V = = 0
PCif V xor N = = 1
PCif V xor N = = 0
PCif (V xor N) or Z = = 1
PCif (V xor N) or Z = = 0
PCif C or Z = = 1
PCif C or Z = = 0
Notes: • The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and
assembler discription label9 and label12 are as follows.
label9 → rel8 = (label9 – PC – 2)/2
label12 → rel11 = (label12 – PC – 2)/2
• Delayed branch operation always executes next instruction (delay slot) before making a branch.
• Instructions allowed to be stored in the delay slot must meet one of the following conditions. If the other
instruction is stored, this device may operate other operation than defined.
The instruction described “1” in the other cycle column than branch instruction.
The instruction described “a”, “b”, “c” or “d” in the cycle column.
103
MB91110 Series
• Direct addressing instructions
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
DMOV
DMOV
DMOV
DMOV
DMOV
DMOV
@dir10,
R13,
@dir10,
@R13+,
@dir10,
@R15+,
R13
@dir10
@R13+
@dir10
@–R15
@dir10
D
D
D
D
D
D
08
18
0C
1C
0B
1B
b
a
2a
2a
2a
2a
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(dir10) → R13
R13 → (dir10)
(dir10) → (R13), R13 + = 4
(R13) → (dir10), R13 + = 4
R15 – = 4, (dir10) → (R15)
(R15) → (dir10), R15 + = 4
Word
Word
Word
Word
Word
Word
DMOVH
DMOVH
DMOVH
DMOVH
@dir9,
R13,
@dir9,
@R13+,
R13
@dir9
@R13+
@dir9
D
D
D
D
09
19
0D
1D
b
a
2a
2a
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(dir9) → R13
R13 → (dir9)
(dir9) → (R13), R13 + = 2
(R13) → (dir9), R13 + = 2
Half word
Half word
Half word
Half word
DMOVB
DMOVB
DMOVB
DMOVB
@dir8,
R13,
@dir8,
@R13+,
R13
@dir8
@R13+
@dir8
D
D
D
D
0A
1A
0E
1E
b
a
2a
2a
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(dir8) → R13
R13 → (dir8)
(dir8) → (R13), R13 + +
(R13) → (dir8), R13 + +
Byte
Byte
Byte
Byte
Note: The relations between the dir field of TYPE-D in the instruction format and the assembler description from
disp8 to disp10 are as follows:
disp8 → dir + disp8:Each disp is a code extension
disp9 → dir = disp9>>1:Each disp is a code extension
disp10 → dir = disp10>>2:Each disp is a code extension
• Resource instructions (2 instructions)
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
LDRES
@Ri+,
#u4
C
BC
a
– – – – (Ri) → u4 resource
Ri + = 4
u4: Channel number
STRES
#u4,
@Ri+
C
BD
a
– – – – u4 resource → (Ri)
Ri + = 4
u4: Channel number
• Co-processor instructions (4 instructions)
Mnemonic
COPOP
COPLD
COPST
COPSV
104
#u4, #CC, CRj, CRi
#u4, #CC, Rj, CRi
#u4, #CC, CRj, Ri
#u4, #CC, CRj, Ri
Type
OP
E
E
E
E
9F – C
9F – D
9F – E
9F – F
Cycle N Z V C
2+a
1 + 2a
1 + 2a
1 + 2a
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Operation
Calculation
Rj → CRi
CRj → Ri
CRj → Ri
Remarks
No error traps
MB91110 Series
• Other instructions (16 instructions)
Type
OP
NOP
E
9F – A
1
– – – – No changes
ANDCCR #u8
ORCCR #u8
D
D
83
93
c
c
C C C C CCR and u8 → CCR
C C C C CCR or u8 → CCR
STILM
#u8
D
87
1
– – – – i8 → ILM
Set ILM immediate
value
ADDSP
#s10
D
A3
1
– – – – R15 + = s10
ADD SP instruction
EXTSB
EXTUB
EXTSH
EXTUH
Ri
Ri
Ri
Ri
E
E
E
E
97 – 8
97 – 9
97 – A
97 – B
1
1
1
1
–
–
–
–
LDM0
(reglist)
D
8C
*4
Load-multi R0 to R7
LDM1
(reglist)
D
8D
*4
* LDM
(reglist)
– – – – (R15) → reglist,
R15 increment
– – – – (R15) → reglist,
R15 increment
– – – – (R15 + +) → reglist,
STM0
(reglist)
D
8E
*
Store-multi R0 to R7
STM1
(reglist)
D
8F
*6
* STM2
(reglist)
*5
– – – – R15 decrement,
reglist → (R15)
– – – – R15 decrement,
reglist → (R15)
– – – – reglist → (R15 + +)
ENTER
#u10
*2
Mnemonic
LEAVE
XCHB
@Rj, Ri
*1
*3
Cycle N Z V C
–
6
–
–
–
–
–
–
–
–
–
–
–
–
–
Operation
Remarks
Sign extension 8 → 32 bits
Zero extension 8 → 32 bits
Sign extension 16 → 32 bits
Zero extension 16 → 32 bits
Load-multi R8 to R15
Load-multi R0 to R15
Store-multi R8 to R15
Store-multi R0 to R15
D
0F
1+a
– – – – R14 → (R15 – 4),
R15 – 4 → R14,
R15 – u10 → R15
Entrance processing
of function
E
9F – 9
b
– – – – R14 + 4 → R15,
(R15 – 4) → R14
Exit processing of
function
A
8A
2a
– – – – Ri → TEMP,
(Rj) → Ri,
TEMP → (Rj)
For SEMAFO
management
Byte data
*1: In the ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler
description s10 is as follows.
s10 → s8 = s10>>2
*2: In the ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler
description u10 is as follows.
u10 → u8 = u10>>2
*3: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified,
assembler generates LDM1. Both LDM0 and LDM1 may be generated.
*4: The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following
calculation; a × (n – 1) + b + 1 when “n” is number of registers specified.
*5: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified,
assembler generates STM1. Both STM0 and STM1 may be generated.
*6: The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following
calculation; a × n + 1 when “n” is number of registers specified.
105
MB91110 Series
• 20-bit normal branch macro instructions
Mnemonic
Operation
Remarks
* CALL20
label20, Ri
Next instruction address → RP, label20 → PC
Ri: Temporary register
*1
* BRA20
* BEQ20
* BNE20
* BC20
* BNC20
* BN20
* BP20
* BV20
* BNV20
* BLT20
* BGE20
* BLE20
* BGT20
* BLS20
* BHI20
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20 → PC
if (Z = = 1) then label20 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*1: CALL20
(1) If label20 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL
label12
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
CALL
@Ri
*2: BRA20
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA
label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
JMP
@Ri
*3: Bcc20 (BEQ20 to BHI20)
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc
label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:20 #label20, Ri
JMP
@Ri
false:
106
MB91110 Series
• 20-bit delayed branch macro instructions
Mnemonic
Operation
Remarks
* CALL20:D label20, Ri
Next instruction address + 2 → RP, label20 → PC
Ri: Temporary register
*1
* BRA20:D
* BEQ20:D
* BNE20:D
* BC20:D
* BNC20:D
* BN20:D
* BP20:D
* BV20:D
* BNV20:D
* BLT20:D
* BGE20:D
* BLE20:D
* BGT20:D
* BLS20:D
* BHI20:D
label20 → PC
if (Z = = 1) then label20 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
*1: CALL20:D
(1) If label20 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL:D label12
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
CALL:D @Ri
*2: BRA20:D
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA:D label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
JMP:D @Ri
*3: Bcc20:D (BEQ20:D to BHI20:D)
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc:D
label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:20 #label20, Ri
JMP:D @Ri
false:
107
MB91110 Series
• 32-bit normal macro branch instructions
Mnemonic
Operation
Remarks
* CALL32
label32, Ri
Next instruction address → RP, label32 → PC
Ri: Temporary register
*1
* BRA32
* BEQ32
* BNE32
* BC32
* BNC32
* BN32
* BP32
* BV32
* BNV32
* BLT32
* BGE32
* BLE32
* BGT32
* BLS32
* BHI32
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32 → PC
if (Z = = 1) then label32 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*1: CALL32
(1) If label32 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL
label12
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
CALL
@Ri
*2: BRA32
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA
label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
JMP
@Ri
*3: Bcc32 (BEQ32 to BHI32)
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc
label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:32 #label32, Ri
JMP
@Ri
false:
108
MB91110 Series
• 32-bit delayed macro branch instructions
Mnemonic
Operation
Remarks
* CALL32:D label32, Ri
Next instruction address + 2 → RP, label32 → PC
Ri: Temporary register
*1
* BRA32:D
* BEQ32:D
* BNE32:D
* BC32:D
* BNC32:D
* BN32:D
* BP32:D
* BV32:D
* BNV32:D
* BLT32:D
* BGE32:D
* BLE32:D
* BGT32:D
* BLS32:D
* BHI32:D
label32 → PC
if (Z = = 1) then label32 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*2
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
*3
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
*1: CALL32:D
(1) If label32 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL:D label12
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
CALL:D @Ri
*2: BRA32:D
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA:D label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
JMP:D @Ri
*3: Bcc32:D (BEQ32:D to BHI32:D)
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc:D
label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:32 #label32, Ri
JMP:D @Ri
false:
109
MB91110 Series
■ ORDERING INFORMATION
Part number
110
Package
MB911110PMT2
144-pin plastic LQFP
(FPT-144P-M08)
MB911V110CR
PGA-299C-A01
Remarks
MB91110 Series
■ PACKAGE DIMENSION
144-pin plastic LQFP
(FPT-144P-M08)
22.00±0.20(.866±.008)SQ
20.00±0.10(.787±.004)SQ
108
0.145±0.055
(.006±.002)
73
109
72
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
0°~8°
INDEX
144
37
"A"
LEAD No.
1
36
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
M
2000 FUJITSU LIMITED F144019S-c-2-4
Dimensions in mm (inches) .
111
MB91110 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0101
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.