3.1 MB

The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16613-3E
32-bit Microcontroller
CMOS
FR60 MB91460M Series
MB91F467MA
■ DESCRIPTION
MB91460M series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control
applications which require high-speed real-time processing, such as consumer devices and on-board vehicle
systems. This series uses the FR60 CPU, which is compatible with the FR family*1 of CPUs.
This series contains the LIN-USART, CAN controllers, MediaLB(512Fs)*2, and I2S.
*1 : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Semiconductor Limited.
*2 : This product is licensed by SMSC Europe in conditions where it is used in the MediaLB system compliant with
the MediaLB specification of the SMSC Europe.
■ FEATURES
1. FR60 CPU core
•
•
•
•
32-bit RISC, load/store architecture, five-stage pipeline
16-bit fixed-length instructions (basic instructions)
Instruction execution speed: 1 instruction per cycle
Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions
suitable for embedded applications
• Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C
language
• Register interlock function: Facilitating assembly-language coding
• Built-in multiplier with instruction-level support
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
(Continued)
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2008-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.5
MB91460M Series
• Interrupts (save PC/PS) : 6 cycles (16 priority levels)
• Harvard architecture enabling program access and data access to be performed simultaneously
• Instructions compatible with the FR family
2. Internal peripheral resources
• General-purpose ports : Maximum 175 ports
• DMAC (DMA Controller)
Maximum of 5 channels able to operate simultaneously. (External to external : 1 channel)
3 transfer sources (external pin/internal peripheral/software)
Activation source can be selected using software.
Addressing mode specifies full 32-bit addresses (increment/decrement/fixed)
Transfer mode (demand transfer/burst transfer/step transfer/block transfer)
Fly-by transfer support (between external I/O and memory)
Transfer data size selectable from 8/16/32-bit
Multi-byte transfer enabled (by software)
DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)
• A/D converter (successive approximation type)
10-bit resolution: 12 channels
Conversion time: minimum 3 μs
• External interrupt inputs : 16 channels
4 channels shared with CAN RX or I2C pins
• Bit search module (for REALOS)
Function to search from the MSB (most significant bit) for the position of the first “0”, “1”, or changed bit in a word
• LIN-USART (full duplex double buffer): 9 channels
Clock synchronous/asynchronous selectable
Sync-break detection
Internal dedicated baud rate generator
4 channel is equipped with 16 stages of transmission and reception FIFO buffers.
• I2C bus interface (supports 400 kbps): 8 channels
Master/slave transmission and reception
Arbitration function, clock synchronization function
• CAN controller (C-CAN): 2 channels
Maximum transfer speed: 1 Mbps
32 transmission/reception message buffers
• MediaLB
Supports 512Fs
15 channels
Contains local channel buffers: 32 bit × 2 k.
Contains a 32 bit × 2 k FIFO buffer for between MediaLB and I2S.
• I2S : 10 channels
(Continued)
2
DS07-16613-3E
MB91460M Series
(Continued)
• 16-bit PPG timer : 8 channels
• 16-bit reload timer: 5 channels
• 16-bit free-run timer: 4 channels (1 channel each for ICU and OCU)
• Input capture: 4 channels (operates in conjunction with the free-run timer)
• Output compare: 4 channels (operates in conjunction with the free-run timer)
• Watchdog timer
• Real-time clock
• Low-power consumption modes : Sleep/stop mode function
• Low voltage detection circuit
• Clock modulator
• Sub-clock calibration
Corrects the real-time clock timer when operating with the 32 kHz or CR oscillator
• Main oscillator stabilization timer
Generates an interrupt in sub-clock mode after the stabilization wait time has elapsed on the 23-bit stabilization
wait time counter
• Sub-oscillator stabilization timer
Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization
wait time counter
3. Package and technology
•
•
•
•
Package : QFP-216
CMOS 0.18 μm technology
Power supply range 3 V to 5 V (1.8 V internal logic provided by a step-down voltage converter)
Operating temperature range: between − 40°C and + 105°C
DS07-16613-3E
3
MB91460M Series
■ PRODUCT LINEUP
Feature
MB91F467MA
MB91V460 (Reference)
Core frequency
80 MHz
80 MHz
Resource frequency
20 MHz
40 MHz
External bus frequency
40 MHz
40 MHz
Watchdog timer
Yes
Yes
Bit Search
Yes
Yes
Reset input pin
Yes
Yes
Low power consumption mode
Yes
Yes
DMA
5 channels
5 channels
Flash
1 Mbyte
SRAM
Yes
No
D-RAM
48 Kbytes
64 Kbytes
I/D-RAM
16 Kbytes
64 Kbytes
Direct map cache
8 Kbytes
16 Kbytes
I-Cache
4 Kbytes
4 Kbytes
Boot-ROM
4 Kbytes
4 Kbytes
RTC
1 channel
1 channel
Free-run timer
4 channels
8 channels
ICU
4 channels
8 channels
OCU
4 channels
8 channels
Reload timer
5 channels
8 channels
PPG
8 channels
16 channels
C_CAN
2 channels (32 msg + 64 msg)
6 channels (128 msg)
LIN-USART
5 channels + 4 channels FIFO
4 channels + 4 channels FIFO +
8 channels
8 channels
4 channels
512Fs
No
10 channels
No
24 bit address / 16 bit data
32 bit address / 32 bit data
External Interrupts
16 channels
16 channels
A/D converter
12 channels
32 channels
DSU4
Yes
Yes
EDSU
Yes
Yes
Flash security
I2C
MediaLB
2
IS
External bus
4
DS07-16613-3E
MB91460M Series
■ PIN ASSIGNMENT
VCC5
P24_2/INT2
P17_3/PPG3
P17_2/PPG2
P17_1/PPG1
P17_0/PPG0
P14_3/ICU3/TIN3/TRG3
P14_2/ICU2/TIN2/TRG2
P14_1/ICU1/TIN1/TRG1
P14_0/ICU0/TIN0/TRG0
P22_3/INT15
P22_2/INT13
P22_1/INT14
P22_0/INT12
P23_6/INT11
P23_4/INT10
P40_5/SCL6
P40_4/SDA6
P40_3/SCL5
P40_2/SDA5
P40_1/SCL4
P40_0/SDA4
P24_7/SCL3/INT7
P24_6/SDA3/INT6
VCC5
VSS
P15_3/OCU3/TOT3
P15_2/OCU2/TOT2
P15_1/OCU1/TOT1
P15_0/OCU0/TOT0
P18_2/SCK6
P18_1/SOT6
P18_0/SIN6
P19_6/SCK5
P19_5/SOT5
P19_4/SIN5
P19_2/SCK4
P19_1/SOT4
P19_0/SIN4
VCC5
VSS
P20_6/SCK3/FRCK3
P20_5/SOT3
P20_4/SIN3
P20_2/SCK2/FRCK2
P20_1/SOT2
P20_0/SIN2
P21_6/SCK1/FRCK1
P21_5/SOT1
P21_4/SIN1
P21_2/SCK0/FRCK0
P21_1/SOT0
P21_0/SIN0
VCC5
(TOP VIEW)
(2)
(3)
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
MB91F467MA
LQFP-216
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VSS
TRSTX
INITX
MD0
MD1
MD2
MD3
MD4
P23_3/TX1
P23_2/RX1/INT9
P23_1/TX0
P23_0/RX0/INT8
P24_1/INT1
P24_0/INT0
P22_5/SCL0
P22_4/SDA0/INT14
P40_7/SCL7
P40_6/SDA7
AVRH
AVCC3
AVSS/AVRL
P28_3/AN11
P28_2/AN10
P28_1/AN9
P28_0/AN8
P29_7/AN7
P29_6/AN6
P29_5/AN5
P29_4/AN4
P29_3/AN3
P29_2/AN2
P29_1/AN1
P29_0/AN0
VSS
WDRESETX
P35_2/SCK8
P35_1/SOT8
P35_0/SIN8
P17_7/PPG7
P17_6/PPG6
P17_5/PPG5
P17_4/PPG4
P16_7/ATGX
P38_1/SD9
P38_0/SD8
P39_7/SD7
P39_6/SD6
P39_5/SD5
P39_4/SD4
P39_3/SD3
P39_2/SD2
P39_1/SD1
P39_0/SD0
VCC3
VSS
P01_0/D16
P01_1/D17
P01_2/D18
P01_3/D19
P01_4/D20
P01_5/D21
P01_6/D22
P01_7/D23
P00_0/D24
P00_1/D25
P00_2/D26
P00_3/D27
P00_4/D28
P00_5/D29
P00_6/D30
P00_7/D31
VCC3
VSS
P07_0/A00
P07_1/A01
P07_2/A02
P07_3/A03
P07_4/A04
P07_5/A05
P07_6/A06
P07_7/A07
P06_0/A08
P06_1/A09
P06_2/A10
P06_3/A11
P06_4/A12
P06_5/A13
P06_6/A14
P06_7/A15
VCC3
VSS
P05_0/A16
P05_1/A17
P05_2/A18
P05_3/A19
P05_4/A20
P05_5/A21
P05_6/A22
P05_7/A23
P18_6/SCK7
P18_5/SOT7
P18_4/SIN7
P36_5/MLBDAT
P36_6/MLBSIG
P36_7/MLBCLK
P36_2/WS0
P36_3/SCK0
VSS
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
VSS
INT3/P24_3
INT15/SDA1/P22_6
SCL1/P22_7
SDA2/INT4/P24_4
SCL2/INT5/P24_5
ICS2/P16_6
ICS1/P16_5
ICS0/P16_4
ICD3/P16_3
ICD2/P16_2
ICD1/P16_1
ICD0/P16_0
BREAK/P15_7
ICLK/P15_6
SHUTDOWN
DREQ0/P13_0
DACKX0/P13_1
DEOP0/DEOTX0/P13_2
VCC3
VSS
C_2
CS6X/P09_6
CS5X/P09_5
CS4X/P09_4
CS3X/P09_3
CS2X/P09_2
CS1X/P09_1
CS0X/P09_0
IORDX/P11_0
IOWRX/P11_1
RDY/P08_7
BRQ/P08_6
BGRNTX/P08_5
RDX/P08_4
WR1X/P08_1
WR0X/P08_0
MCLKE/P10_6
MCLKI/P10_5
MCLKO/P10_4
WEX/P10_3
BAAX/P10_2
ASX/P10_1
SYSCLK/P10_0
VCC3
VCC3
C_1
VSS
X0
X1
VSS
X0A
X1A
VCC3
(FPT-216P-M01)
The 5 V/3 V block is the area (1) to (3) in the figure.
This area is available for both 5 V and 3 V.However, when 5 V is used in at least one place, 5 V must be
used for the area (3).
DS07-16613-3E
5
MB91460M Series
■ PIN DESCRIPTION
Pin no.
2
Pin name
P24_3
INT3
I/O
I/O circuit
type*
I/O
D
P22_6
3
SDA1
P22_7
SCL1
I/O
C
6
INT4
I/O
C
8
9
10
11
12
13
14
15
16
Serial data input/output pin of I2C 1.
General-purpose input/output ports
Serial clock input/output pin of I2C 1.
General-purpose input/output ports
I/O
C
Request input pin of external interrupt ch.4.
SDA2
Serial data input/output pin of I2C 2.
P24_5
General-purpose input/output ports
INT5
I/O
C
P16_6
ICS2
P16_5
ICS1
P16_4
ICS0
P16_3
ICD3
P16_2
ICD2
P16_1
ICD1
P16_0
ICD0
P15_7
BREAK
P15_6
ICLK
SHUTDOWN
Request input pin of external interrupt ch.5.
Serial clock input/output pin of I2C 2.
SCL2
7
Request input pin of external interrupt ch.3.
Request input pin of external interrupt ch.15. Exclusive from
P22_3.
P24_4
5
General-purpose input/output ports
General-purpose input/output ports
INT15
4
Function
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
I
O
J
General-purpose input/output ports. Enabled when MD4 = “0”.
Status output pin of DSU4. Enabled when MD4 = “1”.
General-purpose input/output ports.Enabled when MD4 = “0”.
Status output pin of DSU4. Enabled when MD4 = “1”.
General-purpose input/output ports. Enabled when MD4 = “0”.
Status output pin of DSU4. Enabled when MD4 = “1”.
General-purpose input/output ports. Enabled when MD4 = “0”.
Data input/output pin of DSU4. Enabled when MD4 = “1”.
General-purpose input/output ports. Enabled when MD4 = “0”.
Data input/output pin of DSU4. Enabled when MD4 = “1”.
General-purpose input/output ports. Enabled when MD4 = “0”.
Data input/output pin of DSU4. Enabled when MD4 = “1”.
General-purpose input/output ports. Enabled when MD4 = “0”.
Data input/output pin of DSU4. Enabled when MD4 = “1”.
General-purpose input/output ports. Enabled when MD4 = “0”.
BREAK input pin of DSU4. Enabled when MD4 = “1”.
General-purpose input/output ports. Enabled when MD4 = “0”.
Clock output pin of DSU4. Enabled when MD4 = “1”.
Shutdown output, H active.
(Continued)
6
DS07-16613-3E
MB91460M Series
Pin no.
17
18
Pin name
P13_0
DREQ0
P13_1
DACKX0
I/O
I/O circuit
type*
I/O
H
I/O
H
P13_2
19
DEOTX0
24
25
26
27
28
29
30
31
P09_6
CS6X
P09_5
CS5X
P09_4
CS4X
P09_3
CS3X
P09_2
CS2X
P09_1
CS1X
P09_0
CS0X
P11_0
IORDX
P11_1
IOWRX
I/O
H
RDY
Input pin for DMA transfer request.
General-purpose input/output ports.
Output pin for DMA transfer request acknowledge.
Input pin for DMA transfer stop request.
Output pin for DMA transfer end.
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
P08_7
32
General-purpose input/output ports.
General-purpose input/output ports.
DEOP0
23
Function
General-purpose input/output ports.
Output pin of external bus chip select area 6.
General-purpose input/output ports.
Output pin of external bus chip select area 5.
General-purpose input/output ports.
Output pin of external bus chip select area 4.
General-purpose input/output ports.
Output pin of external bus chip select area 3.
General-purpose input/output ports.
Output pin of external bus chip select area 2.
General-purpose input/output ports.
Output pin of external bus chip select area 1.
General-purpose input/output ports.
Output pin of external bus chip select area 0.
General-purpose input/output ports.
Output pin for DMA fly-by transfer from I/O to memory.
General-purpose input/output ports.
Output pin for DMA fly-by transfer from memory to I/O.
General-purpose input/output ports.
I/O
H
External bus ready input pin (when RDY is enabled to a
corresponding CS area).
(Continued)
DS07-16613-3E
7
MB91460M Series
Pin no.
Pin name
I/O
I/O circuit
type*
P08_6
33
BRQ
General-purpose input/output ports.
I/O
H
P08_5
34
35
36
37
38
39
40
41
42
43
44
BGRNTX
P08_4
RDX
P08_1
WR1X
P08_0
WR0X
P10_6
MCLKE
P10_5
MCLKI
P10_4
MCLKO
P10_3
WEX
P10_2
BAAX
P10_1
ASX
P10_0
SYSCLK
Function
External bus open request input pin (when sharing is enabled
to a corresponding CS area) .
General-purpose input/output ports.
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
External bus release acceptance output pin (when sharing is
enabled to a corresponding CS area)
General-purpose input/output ports.
Output pin for external bus read strobe.
General-purpose input/output ports.
Output pin for external bus write strobe.
General-purpose input/output ports.
Output pin for external bus write strobe.
General-purpose input/output ports.
Output pin for external bus memory clock enabled.
General-purpose input/output ports.
Input pin for external bus memory clock.
General-purpose input/output ports.
Output pin for external bus memory clock.
General-purpose input/output ports.
Output pin for external bus write strobe.
General-purpose input/output ports.
Output pin for external bus burst access.
General-purpose input/output ports.
Output pin for external bus address strobe.
General-purpose input/output ports.
Output pin for external bus clock.
49
X0
⎯
G
Main oscillation pin
50
X1
⎯
G
Main oscillation pin
52
X0A
⎯
G
Sub oscillation pin
53
X1A
⎯
G
Sub oscillation pin
I/O
H
56
P01_0
D16
General-purpose input/output ports.
I/O pin for 16-bit external data bus.
(Continued)
8
DS07-16613-3E
MB91460M Series
Pin no.
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
74
75
Pin name
P01_1
D17
P01_2
D18
P01_3
D19
P01_4
D20
P01_5
D21
P01_6
D22
P01_7
D23
P00_0
D24
P00_1
D25
P00_2
D26
P00_3
D27
P00_4
D28
P00_5
D29
P00_6
D30
P00_7
D31
P07_0
A00
P07_1
A01
I/O
I/O circuit
type*
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
Function
General-purpose input/output ports.
I/O pin for 17-bit external data bus.
General-purpose input/output ports.
I/O pin for 18-bit external data bus.
General-purpose input/output ports.
I/O pin for 19-bit external data bus.
General-purpose input/output ports.
I/O pin for 20-bit external data bus.
General-purpose input/output ports.
I/O pin for 21-bit external data bus.
General-purpose input/output ports.
I/O pin for 22-bit external data bus.
General-purpose input/output ports.
I/O pin for 23-bit external data bus.
General-purpose input/output ports.
I/O pin for 24-bit external data bus.
General-purpose input/output ports.
I/O pin for 25-bit external data bus.
General-purpose input/output ports.
I/O pin for 26-bit external data bus.
General-purpose input/output ports.
I/O pin for 27-bit external data bus.
General-purpose input/output ports.
I/O pin for 28-bit external data bus.
General-purpose input/output ports.
I/O pin for 29-bit external data bus.
General-purpose input/output ports.
I/O pin for 30-bit external data bus.
General-purpose input/output ports.
I/O pin for 31-bit external data bus.
General-purpose input/output ports.
I/O pin for 0-bit external address bus.
General-purpose input/output ports.
I/O pin for 1-bit external address bus.
(Continued)
DS07-16613-3E
9
MB91460M Series
Pin no.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
92
93
94
Pin name
P07_2
A02
P07_3
A03
P07_4
A04
P07_5
A05
P07_6
A06
P07_7
A07
P06_0
A08
P06_1
A09
P06_2
A10
P06_3
A11
P06_4
A12
P06_5
A13
P06_6
A14
P06_7
A15
P05_0
A16
P05_1
A17
P05_2
A18
I/O
I/O circuit
type*
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
Function
General-purpose input/output ports.
I/O pin for 2-bit external address bus.
General-purpose input/output ports.
I/O pin for 3-bit external address bus.
General-purpose input/output ports.
I/O pin for 4-bit external address bus.
General-purpose input/output ports.
I/O pin for 5-bit external address bus.
General-purpose input/output ports.
I/O pin for 6-bit external address bus.
General-purpose input/output ports.
I/O pin for 7-bit external address bus.
General-purpose input/output ports.
I/O pin for 8-bit external address bus.
General-purpose input/output ports.
I/O pin for 9-bit external address bus.
General-purpose input/output ports.
I/O pin for 10-bit external address bus.
General-purpose input/output ports.
I/O pin for 11-bit external address bus.
General-purpose input/output ports.
I/O pin for 12-bit external address bus.
General-purpose input/output ports.
I/O pin for 13-bit external address bus.
General-purpose input/output ports.
I/O pin for 14-bit external address bus.
General-purpose input/output ports.
I/O pin for 15-bit external address bus.
General-purpose input/output ports.
I/O pin for 16-bit external address bus.
General-purpose input/output ports.
I/O pin for 17-bit external address bus.
General-purpose input/output ports.
I/O pin for 18-bit external address bus.
(Continued)
10
DS07-16613-3E
MB91460M Series
Pin no.
95
96
97
98
99
100
101
102
103
104
105
106
107
110
111
112
113
Pin name
P05_3
A19
P05_4
A20
P05_5
A21
P05_6
A22
P05_7
A23
P18_6
SCK7
P18_5
SOT7
P18_4
SIN7
P36_5
MLBDAT
P36_6
MLBSIG
P36_7
MLBCLK
P36_2
WS0
P36_3
SCK0
P39_0
SD0
P39_1
SD1
P39_2
SD2
P39_3
SD3
I/O
I/O circuit
type*
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
L
I/O
L
I/O
L
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
Function
General-purpose input/output ports.
I/O pin for 19-bit external address bus.
General-purpose input/output ports.
I/O pin for 20-bit external address bus.
General-purpose input/output ports.
I/O pin for 21-bit external address bus.
General-purpose input/output ports.
I/O pin for 22-bit external address bus.
General-purpose input/output ports.
I/O pin for 23-bit external address bus.
General-purpose input/output ports.
Clock input/output pin of LIN-USART 7.
General-purpose input/output ports.
Serial data output pin of LIN-USART 7
General-purpose input/output ports.
Serial data input pin of LIN-USART 7
General-purpose input/output ports.
Data input/output pin for MediaLB.
General-purpose input/output ports.
Data input/output pin for MediaLB.
General-purpose input/output ports.
Clock input pin for MediaLB.
General-purpose input/output ports.
Input/output pin of L/R judgement signal for I2S.
General-purpose input/output ports.
Clock input/output pin for I2S.
General-purpose input/output ports.
Sound data input/output pin for I2S ch.0.
General-purpose input/output ports.
Sound data input/output pin for I2S ch.1.
General-purpose input/output ports.
Sound data input/output pin for I2S ch.2.
General-purpose input/output ports.
Sound data input/output pin for I2S ch.3.
(Continued)
DS07-16613-3E
11
MB91460M Series
Pin no.
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
130
Pin name
P39_4
SD4
P39_5
SD5
P39_6
SD6
P39_7
SD7
P38_0
SD8
P38_1
SD9
P16_7
ATGX
P17_4
PPG4
P17_5
PPG5
P17_6
PPG6
P17_7
PPG7
P35_0
SIN8
P35_1
SOT8
P35_2
SCK8
WDRESETX
P29_0
AN0
I/O
I/O circuit
type*
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
O
J
I/O
F
Function
General-purpose input/output ports.
Sound data input/output pin for I2S ch.4.
General-purpose input/output ports.
Sound data input/output pin for I2S ch.5.
General-purpose input/output ports.
Sound data input/output pin for I2S ch.6.
General-purpose input/output ports.
Sound data input/output pin for I2S ch.7.
General-purpose input/output ports.
Sound data input/output pin for I2S ch.8.
General-purpose input/output ports.
Sound data input/output pin for I2S ch.9.
General-purpose input/output ports.
A/D converter external trigger input.
General-purpose input/output ports.
Waveform output pin of programmable pulse generator PPG 4.
General-purpose input/output ports.
Waveform output pin of programmable pulse generator PPG 5.
General-purpose input/output ports.
Waveform output pin of programmable pulse generator PPG 6.
General-purpose input/output ports.
Waveform output pin of programmable pulse generator PPG 7.
General-purpose input/output ports.
Serial data input of LIN-USART 8.
General-purpose input/output ports.
Serial data output of LIN-USART 8.
General-purpose input/output ports.
Clock input/output of LIN-USART 8.
Watchdog reset output, L Active.
General-purpose input/output ports.
Analog input ch.0 for A/D converter.
(Continued)
12
DS07-16613-3E
MB91460M Series
Pin no.
131
132
133
134
135
136
137
138
139
140
141
145
146
Pin name
P29_1
AN1
P29_2
AN2
P29_3
AN3
P29_4
AN4
P29_5
AN5
P29_6
AN6
P29_7
AN7
P28_0
AN8
P28_1
AN9
P28_2
AN10
P28_3
AN11
P40_6
SDA7
P40_7
SCL7
I/O
I/O circuit
type*
I/O
F
I/O
F
I/O
F
I/O
F
I/O
F
I/O
F
I/O
F
I/O
F
I/O
F
I/O
F
I/O
F
I/O
C
I/O
C
P22_4
SDA0
147
149
P22_5
SCL0
P24_0
INT0
General-purpose input/output ports.
Analog input ch.1 for A/D converter.
General-purpose input/output ports.
Analog input ch.2 for A/D converter.
General-purpose input/output ports.
Analog input ch.3 for A/D converter.
General-purpose input/output ports.
Analog input ch.4 for A/D converter.
General-purpose input/output ports.
Analog input ch.5 for A/D converter.
General-purpose input/output ports.
Analog input ch.6 for A/D converter.
General-purpose input/output ports.
Analog input ch.7 for A/D converter.
General-purpose input/output ports.
Analog input ch.8 for A/D converter.
General-purpose input/output ports.
Analog input ch.9 for A/D converter.
General-purpose input/output ports.
Analog input ch.10 for A/D converter.
General-purpose input/output ports.
Analog input ch.11 for A/D converter.
General-purpose input/output ports.
Serial data input/output pin of I2C 7.
General-purpose input/output ports.
Serial clock input/output pin of I2C 7.
General-purpose input/output ports.
I/O
C
Serial data input/output pin of I2C 0.
Request input pin of external interrupt ch.14. Exclusive from
P22_1.
INT14
148
Function
I/O
C
I/O
D
General-purpose input/output ports.
Serial clock input/output pin of I2C 0.
General-purpose input/output ports.
Request input pin of external interrupt ch.0.
(Continued)
DS07-16613-3E
13
MB91460M Series
Pin no.
150
Pin name
P24_1
INT1
I/O
I/O circuit
type*
I/O
D
P23_0
151
RX0
P23_1
TX0
I/O
D
RX1
I/O
D
P23_3
TX1
Reception input pin of CAN 0.
General-purpose input/output ports.
Transmission output pin of CAN 0.
General-purpose input/output ports.
I/O
D
INT9
154
Request input pin of external interrupt ch.1.
Request input pin of external interrupt ch.8.
P23_2
153
General-purpose input/output ports.
General-purpose input/output ports.
INT8
152
Function
Reception input pin of CAN 1.
Request input pin of external interrupt ch.9.
I/O
D
General-purpose input/output ports.
Transmission output pin of CAN 1.
155
MD4
I
A
Mode pin 4
156
MD3
I
A
Mode pin 3
157
MD2
I
K
Mode pin 2
158
MD1
I
K
Mode pin 1
159
MD0
I
K
Mode pin 0
160
INITX
I
B
MCU reset input pin, L active doesn't change.
161
TRSTX
I
E
Tool reset input pin, L active doesn't change.
I/O
D
I/O
D
164
165
P21_0
SIN0
P21_1
SOT0
P21_2
166
SCK0
168
P21_4
SIN1
P21_5
SOT1
I/O
D
SCK1
I/O
D
I/O
D
P20_0
SIN2
Serial data output pin of LIN-USART 0.
Clock input/output pin of LIN-USART 0.
General-purpose input/output ports.
Serial data input pin of LIN-USART 1 .
General-purpose input/output ports.
Serial data output pin of LIN-USART 1.
General-purpose input/output ports.
I/O
D
FRCK1
170
General-purpose input/output ports.
Clock input pin of Free-run timer FRT0.
P21_6
169
Serial data input pin of LIN-USART 0.
General-purpose input/output ports.
FRCK0
167
General-purpose input/output ports.
Clock input/output pin of LIN-USART 1.
Clock input pin of Free-run timer FRT1.
I/O
D
General-purpose input/output ports.
Serial data input pin of LIN-USART 2 .
(Continued)
14
DS07-16613-3E
MB91460M Series
Pin no.
171
Pin name
P20_1
SOT2
I/O
I/O circuit
type*
I/O
D
P20_2
172
SCK2
174
P20_4
SIN3
P20_5
SOT3
I/O
D
SCK3
I/O
D
I/O
D
179
180
181
182
183
184
185
186
P19_0
SIN4
P19_1
SOT4
P19_2
SCK4
P19_4
SIN5
P19_5
SOT5
P19_6
SCK5
P18_0
SIN6
P18_1
SOT6
P18_2
SCK6
I/O
D
OCU0
TOT0
General-purpose input/output ports.
Serial data input pin of LIN-USART 3 .
General-purpose input/output ports.
Serial data output pin of LIN-USART 3.
Clock input/output pin of LIN-USART 3.
Clock input pin of Free-run timer FRT3.
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
P15_0
187
Clock input/output pin of LIN-USART 2.
General-purpose input/output ports.
FRCK3
178
Serial data output pin of LIN-USART 2.
Clock input pin of Free-run timer FRT2.
P20_6
175
General-purpose input/output ports.
General-purpose input/output ports.
FRCK2
173
Function
General-purpose input/output ports.
Serial data input pin of LIN-USART 4 .
General-purpose input/output ports.
Serial data output pin of LIN-USART 4.
General-purpose input/output ports.
Clock input/output pin of LIN-USART 4.
General-purpose input/output ports.
Serial data input pin of LIN-USART 5 .
General-purpose input/output ports.
Serial data output pin of LIN-USART 5.
General-purpose input/output ports.
Clock input/output pin of LIN-USART 5.
General-purpose input/output ports.
Serial data input pin of LIN-USART 6 .
General-purpose input/output ports.
Serial data output pin of LIN-USART 6.
General-purpose input/output ports.
Clock input/output pin of LIN-USART 6.
General-purpose input/output ports.
I/O
D
Waveform output pin of output compare OCU 0.
Output pin of reload timer RLT 0.
(Continued)
DS07-16613-3E
15
MB91460M Series
Pin no.
Pin name
I/O
I/O circuit
type*
P15_1
188
189
190
193
194
OCU1
General-purpose input/output ports.
I/O
D
196
197
198
199
200
201
202
203
Output pin of reload timer RLT 1.
P15_2
General-purpose input/output ports.
OCU2
I/O
D
Waveform output pin of output compare OCU 2.
TOT2
Output pin of reload timer RLT 2.
P15_3
General-purpose input/output ports.
OCU3
I/O
D
Waveform output pin of output compare OCU 3.
TOT3
Output pin of reload timer RLT 3.
P24_6
General-purpose input/output ports.
INT6
I/O
D
Request input pin of external interrupt ch.6.
SDA3
Serial data input/output pin of I2C 3.
P24_7
General-purpose input/output ports.
INT7
I/O
D
P40_0
SDA4
P40_1
SCL4
P40_2
SDA5
P40_3
SCL5
P40_4
SDA6
P40_5
SCL6
P23_4
INT10
P23_6
INT11
P22_0
INT12
INT14
Request input pin of external interrupt ch.7.
Serial clock input/output pin of I2C 3.
I/O
C
I/O
C
I/O
C
I/O
C
I/O
C
I/O
C
I/O
D
I/O
D
I/O
D
I/O
D
P22_1
204
Waveform output pin of output compare OCU 1.
TOT1
SCL3
195
Function
General-purpose input/output ports.
Serial data input/output pin of I2C 4.
General-purpose input/output ports.
Serial clock input/output pin of I2C 4.
General-purpose input/output ports.
Serial data input/output pin of I2C 5.
General-purpose input/output ports.
Serial clock input/output pin of I2C 5.
General-purpose input/output ports.
Serial data input/output pin of I2C 6.
General-purpose input/output ports.
Serial clock input/output pin of I2C 6.
General-purpose input/output ports.
Request input pin of external interrupt ch.10.
General-purpose input/output ports.
Request input pin of external interrupt ch.11.
General-purpose input/output ports.
Request input pin of external interrupt ch.12.
General-purpose input/output ports.
Request input pin of external interrupt ch.14. Exclusive from
P22_4.
(Continued)
16
DS07-16613-3E
MB91460M Series
(Continued)
Pin no.
205
Pin name
P22_2
INT13
I/O
I/O circuit
type*
I/O
D
I/O
D
P22_3
206
INT15
ICU0
TIN0
General-purpose input/output ports.
I/O
D
215
Event input pin of reload timer RLT 0.
General-purpose input/output ports.
ICU1
TIN1
I/O
D
Data sample input pin of Input capture ICU 1.
Event input pin of reload timer RLT 1.
TRG1
Event input pin of programmable pulse generator PPG 1.
P14_2
General-purpose input/output ports.
ICU2
TIN2
I/O
D
Data sample input pin of input capture ICU 2.
Event input pin of reload timer RLT 2.
TRG2
Event input pin of programmable pulse generator PPG 2.
P14_3
General-purpose input/output ports.
ICU3
TIN3
I/O
D
TRG3
214
Data sample input pin of Input capture ICU 0.
P14_1
210
213
Request input pin of external interrupt ch.15. Exclusive from
P22_6.
Event input pin of programmable pulse generator PPG 0.
209
212
Request input pin of external interrupt ch.13.
TRG0
208
211
General-purpose input/output ports.
General-purpose input/output ports.
P14_0
207
Function
P17_0
PPG0
P17_1
PPG1
P17_2
PPG2
P17_3
PPG3
P24_2
INT2
Data sample input pin of input capture ICU 3.
Event input pin of reload timer RLT 3.
Event input pin of programmable pulse generator PPG 3.
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
General-purpose input/output ports.
Waveform output pin of programmable pulse generator PPG 0.
General-purpose input/output ports.
Waveform output pin of programmable pulse generator PPG 1.
General-purpose input/output ports.
Waveform output pin of programmable pulse generator PPG 2.
General-purpose input/output ports.
Waveform output pin of programmable pulse generator PPG 3.
General-purpose input/output ports.
Request input pin of external interrupt ch.2.
* : For information about the I/O circuit type, refer to “■ I/O CIRCUIT TYPES”.
DS07-16613-3E
17
MB91460M Series
[Power supply/Ground pins]
Pin no.
Pin name
I/O
Function
1, 21, 48, 51, 55, 73, 91,
108, 129, 162, 176, 191
VSS
20, 45, 46, 54, 72, 90,
109
VCC3
Power supply pins for external data bus and internal
regulator.
163, 177, 192, 216
VCC5
Power supply pins
143
AVCC3
142
AVSS/AVRL
144
AVRH
Reference power supply pin for A/D converter
47
C_1
Capacitor connection pin for internal regulator.
22
C_2
Capacitor connection pin for internal regulator.
18
Ground pins
Supply
Power supply pin for A/D converter
Analog ground pin, reference power supply pin for
A/D converter.
DS07-16613-3E
MB91460M Series
■ I/O CIRCUIT TYPES
Type
Circuit
A
5.0 V
Input
Remarks
• 5.0 V CMOS level hysteresis input
• With Pull-down
N-ch
B
• 5.0 V CMOS level hysteresis input
• With Pull-up
P-ch
5.0 V
Input
C
Pull-up control
P-ch
5.0 V
N-ch
P-ch
Output drive P-ch
N-ch
Output drive N-ch
• 5.0 V CMOS level output
IOL = 3 mA, IOH = − 3 mA
• 5.0 V CMOS level input
• 5.0 V CMOS level hysteresis input
• 5.0 V Automotive level input
With standby control
With Pull-up/down control
• Pseudo open drain when using I2C
Pull- down control
CMOS level input
Standby control
CMOS level
hysteresis input
Standby control
Automotive level input
Standby control
(Continued)
DS07-16613-3E
19
MB91460M Series
Type
Circuit
D
P-ch
Pull-up control
5.0 V
N-ch
P-ch
Output drive P-ch
N-ch
Output drive N-ch
Remarks
• 5.0 V CMOS level output
IOL = 4 mA, IOH = − 4 mA
• 5.0 V CMOS level input
• 5.0 V CMOS level hysteresis input
• 5.0 V Automotive level input
With standby control
With Pull-up/down control
Pull- down control
CMOS level input
Standby control
CMOS level
Hysteresis input
Standby control
Automotive level input
Standby control
E
P-ch
Pull-up control
3.3 V CMOS level hysteresis input
Withstand voltage 5 V
5.0 V pull-up function (When DSU4 is unused)
5.0 V
Input
(Continued)
20
DS07-16613-3E
MB91460M Series
Type
Circuit
Remarks
F
Pull-up control
P-ch
3.3 V
N-ch
P-ch
Output drive P-ch
N-ch
Output drive N-ch
• 3.3 V CMOS level output
IOL = 4 mA, IOH = − 4 mA
• 3.3 V CMOS level input
• 3.3 V CMOS level hysteresis input
With standby control
• Analog input for A/D converter
Pull- down control
CMOS level input
Standby control
CMOS level
hysteresis input
Standby control
Analog input
G
3.3 V
Input
3.3 V Oscillation cell
Feedback resistor 1 MΩ
With standby control
Standby control
(Continued)
DS07-16613-3E
21
MB91460M Series
Type
Circuit
H
P-ch
Pull-up control
3.3 V
P-ch
Output drive P-ch
N-ch
Output drive N-ch
Remarks
• 3.3 V CMOS level output
IOL = 4 mA, IOH = − 4 mA
• 3.3 V CMOS level input
• 3.3 V CMOS level hysteresis input
With standby control
With Pull-up/down control
Pull- down control
N-ch
CMOS level input
Standby control
CMOS level
hysteresis input
Standby control
I
3.3 V
P-ch
Output drive P-ch
N-ch
Output drive N-ch
• 3.3 V CMOS level output
IOL = 8 mA, IOH = − 8 mA
• 3.3 V CMOS level hysteresis input
With standby control
CMOS level
hysteresis input
Standby control
J
3.3 V CMOS level output
IOL = 4 mA, IOH = − 4 mA
3.3 V
P-ch
N-ch
K
Output drive P-ch
Output drive N-ch
5.0 V CMOS level hysteresis input
5.0 V
Input
(Continued)
22
DS07-16613-3E
MB91460M Series
(Continued)
Type
Circuit
L
P-ch
Pull-up control
3.3 V
N-ch
P-ch
Output drive P-ch
N-ch
Output drive N-ch
Remarks
• 3.3 V CMOS level output
IOL = 6 mA, IOH = − 6 mA
• 3.3 V CMOS level input
• 3.3 V CMOS level hysteresis input
• 3.3 V MediaLB level hysteresis input
With standby control
With Pull-up/down control
Pull- down control
CMOS level input
Standby control
CMOS level
hysteresis input
Standby control
Dedicated MediaLB input
Standby control
DS07-16613-3E
23
MB91460M Series
■ HANDLING DEVICES
• Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage higher than VCC or less than VSS is applied to an input or output
pin or if a voltage exceeding the rating is applied between VCC and VSS pins.
If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings.
• Handling of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistor (2 KΩ or more) or enable internal pull up or pull down resistors before setting the
global port enable bit.
Unused input and output pins need to leave open at the output state, or treat the same as for the input pin when
they are at the input state.
• Power supply pins
The MB91460M series has multiple of VCC and VSS pins.
The device is designed such that pins necessary to be at the same potential are interconnected internally to
prevent malfunctions such as latch-up. However, all of these pins must be connected externally to the power
supply or ground in order to minimize undesired electromagnetic radiation, prevent strobe signal malfunctions
due to the rise in ground level, and conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also recommended that a ceramic capacitor of around 0.1 μF be connected as a bypass capacitor between
the VCC and VSS pins at a location close to the device.
This series has a built-in regulator. Connect a bypass capacitor of 4.7 μF to C_1 and C_2 pins for the regulator.
• Crystal oscillator circuit
Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit
boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator (or ceramic oscillator),
as well as bypass capacitors connected to ground, are placed as close together as possible. When the signal
wires for transmitting from X0 and X1 pins are pulled along, use the circuit with them shielded on board. Be
careful especially when a pin next to X0 pin is used.
It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and
X1A pins are surrounded by ground plane for the stable operation. Sub clock is also needed when dual clock
product is used as single clock product.
Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this
device.
• Treatment of NC and OPEN pins
Pins marked as NC and OPEN must be left open-circuit.
• Mode pins (MD0 to MD4)
These pins should be connected directly to Vcc or Vss. To prevent the device from entering test mode accidentally
due to noise, minimize the lengths of the patterns between each mode pin and Vcc or Vss on the printed circuit
board as possible and connect them with low impedance.
Especially, MD3 must be directly connected to Vss with 0 Ω.
24
DS07-16613-3E
MB91460M Series
• Operation at Start-up
Be sure to execute the setting initialized reset (INIT) with INITX pin immediately after start-up.
Hold the “L” level input to the INITX pin during the stabilization wait time immediately after the power on to ensure
the stabilization wait time as required by the oscillator circuit (the stabilization wait time is initialized to the
minimum value when INIT is asserted to reset using the INITX pin).
• Note on oscillator input at power-on
At power-on, ensure that the clock is input until the oscillator stabilization wait time has elapsed.
• Notes on operating in PLL clock mode
If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may
continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this selfrunning operation cannot be guaranteed.
• Notes on using external clock
When using an external clock, simultaneously supply the clock signal to the X1 (X1A) pin and a clock signal with
the reverse phase to X0(X0A).
However, the external clock must not be used while the microcontroller is in stop mode (oscillator stop mode).
The X1 pin outputs the H level and stops in STOP mode.
• Setting external bus
This model guarantees the maximum frequency of 40 MHz for the external clock operation.
Setting the base clock frequency to the maximum operation frequency without changing the initial value of DIVR1
(external bus base clock division setting register) sets the external bus frequency that is not guaranteed.
Before changing the base clock frequency, set SYSCLK not to exceed the maximum guaranteed frequency.
The AC ratings cannot be guaranteed if a pull-up resistor is connected to the pin serving as an external bus pin.
• Clock control
Input the “L” signal to INIT to assure the clock oscillation stabilization wait time.
Immediately after power-on or when returning from shutdown by INITX input, keep the "L" level input to the INITX
pin for oscillation stabilization wait time (8ms) in order to secure stabilization wait for the built-in regulator or
oscillation stabilization wait time for the oscillation circuit.
• Switching multiplexed ports
Use PFR (port function register) to switch between the use as a PORT and the multiplexed port.
DS07-16613-3E
25
MB91460M Series
• Low power consumption mode
• For the standby mode, enable the synchronous standby mode (TBCR.SYNCS="1") to use and be sure to
follow the sequence below.
LDI
#value_of_standby, R0 ; value_of_standby is write data of STCR.
LDI
#_STCR, R12
; _STCR is address (481H) of STCR.
STB R0, @R12
; Write to standby control register (STCR)
LDUB @12, R0
; Read STCR for synchronous standby
LDUB @12, R0
; Dummy re-read of STCR
NOP
; NOP x 5 for arrangement of timing
NOP
NOP
NOP
NOP
In addition, set I flag, ILM and ICR to diverge to the interruption handler which triggers the return after returning
to the standby mode.
• Do not do the following when the monitor debugger is used.
- Break point setting for the above instruction lines
- Step execution for above instruction lines
• Power-on sequence for dual-power-supply model
Notes on the power-on and power-off sequences
Power-on sequence : (1) VCC5 (2) VCC3 (3) AVRH, AVCC
Power-off sequence : (1) AVRH, AVCC (2) VCC3 (3) VCC5
Follow the above sequence.
Turn on VCC3 before applying power supply to the analog power supply AVCC3 and AVRH, or the analog signal.
AVRH must not exceed voltage of AVCC3.
• Multiplexed pin for analog input
Input voltage must not exceed AVCC3 when the multiplexed pin serving for the analog input is used as a generalpurpose port.
• Recommended operating condition
VCC3 = AVCC3 = AVRH : Recommended condition
26
DS07-16613-3E
MB91460M Series
• Notes on PS register
As the PS register is processed in advance by some instructions, when the debugger is being used, the exception
handling described below may result in execution breaking in an interrupt handling routine or the displayed values
of the flags in the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,
the operation before and after the EIT always proceeds according to specification.
• The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/
DIV0S instruction:
- a user interrupt is accepted;
- single-step execution is performed;
- or execution breaks due to a data event or from the emulator menu.
1 D0 and D1 flags are updated in advance.
2 An EIT handling routine (user interrupt or emulator) is executed.
3 Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated
to the same values as those in 1).
• The following behavior occurs when an ORCCR, STILM, MOV Ri or PS instruction is executed to enable a
user interrupt while that interrupt is in the active state.
4 The PS register is updated in advance.
5 An EIT handling routine (user interrupt) is executed.
6 Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same
value as in 4.
• Watchdog timer
The watchdog timer built in this model monitors a program and resets the CPU if the reset defer function is not
executed within a certain period of time or the program runs out of control. Once the function of the watchdog
timer is enabled, the watchdog timer keeps on operating program until it resets the CPU.
As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops
executing the program. For those conditions to which this exception applies, see “Chapter 20 Watch dog timer
in Hardware manual”.
• Frequency fluctuation
This chip which contains PLL can switch divide-by-two external clock to PLL output fast clock. The clock gear
function which is built in this model prevents consumption power from increasing rapidly at this time.
• Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore,
design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example, apply a checksum to detect an error.
If an error is detected, retransmit the data.
DS07-16613-3E
27
MB91460M Series
• Write to registers which include a status flag (1)
Be careful not to accidentally clear a status flag, when writing into registers which include a status flag (especially
the interrupt request flag).
Take notice that a flag of a status bit is not cleared and the control bit is set to the expected value at writing.
When overwriting the control bit structured by multiple bits simultaneously, it is not possible to use the bit
manipulation instruction. As a result, it is necessary to access data with usual byte/half word/word when writing
to both a control bit and a status flag simultaneously. At this time, be careful not to accidentally clear other bits
(bits in a status flag).
Almost all registers shown below include multiple control bits and status flags.
• TBCR
• OSCR
• TCCS0, TCCS1
• ICS01
• TMCSR0, TMCSR1, TMCSR2, TMCSR3
• PCN0, PCN1, PCN2, PCN3, PCN4, PCN5
• ADCSL0, ADCSL1
Note: It is not necessary to take special care when overwriting a single bit by the bit manipulation instruction.
• Write to registers which include a status flag (2)
Take notice that actual access will be delayed when writing into registers which include a status flag (especially
the interrupt request flag).
This is because data is written via multiple busses.
For example, when the program exits the interrupt routine after clearing the interrupt request flag, the interrupt
flag may be cleared after accepting the RETI instructions. In this case, the interrupts may be accepted again
because some of the interrupt requests are left at the time of returning from the interrupt routine.
To adjust any discord between this register address and instruction execution, read synchronous registers
(RBSYNC, CBSYNC0/1, and MBSYNC) along with the area where written registers exist.
Adjustment at every writing makes a bus data band width narrow. Therefore, we recommend to adjust only if
necessary. For example, when continuous writing is executed, adjustment at the last writing will be enough.
The table below shows the correspondence between a target area and a synchronous register.
Register name
Target area
RBSYNC
CBSYNC0/1
MBSYNC
28
0x0000-0x01FF, 0x0280-0x037D, 0x0400-0x063F, 0x0C00-0x0FFF
(Peripheral function on R-bus)
0xC000-0xFFFF (CAN on D-bus)
0x6000-0x6FFF (MediaLB, I2S and FIFO buffer on F-bus)
DS07-16613-3E
MB91460M Series
■ NOTES ON DEBUGGER
• Execution of the RETI Command
If an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed
repeatedly after step execution. As the result of that, the main routine and low-interrupt-level programs will not
be executed.
Do not perform the step execution of RETI instruction to prevent this issue.
Disable the corresponding interrupt and execute debugger when the corresponding interrupt routine no longer
needs debugging.
• Operand break
Do not set the access to the areas containing the address of system stack pointer as a target of data event break.
•Flash security
DSU4 will not be available due to security issues when Flash security is used.
• Shutdown mode
It is impossible to execute debugger in the shutdown mode.
DS07-16613-3E
29
MB91460M Series
■ BLOCK DIAGRAM
• MB91F467MA
TRSTX
BREAK
ICS0 to ICS2
ICD0 to ICD3
FR60 CPU
DSU
EDSU/MPU
core
Bit search
32
I-bus
Direct Mapped
Cachannelse
8 Kbytes
D-bus
32
RAM 48 Kbytes
16 Kbytes (0wait)
32 Kbytes (1wait)
RX0/RX1
TX0/TX1
I - Cache
SYSCLK
ASX
RDX
WR0X
WR1X
32 to 16
4 Kbytes
Flash
CAN 2channels
32msg+64msg
BUS adaptor
1 Mbyte
RAM
External BUS I/F
BUS
16 Kbytes
BOOT ROM
4 Kbytes
F-bus
convertor
32
32
32
MediaLB
R-bus
DREQ0
DACKX0
DEOP0
IOWRX
IORDX
DMAC
5 channels
MediaLB
HB-bus
Interrupt
Controller
32
HB
decoder
PB-bus
32
TRQ0 to TRQ3
PPG0 to PPG7
PPG
8 channels
TIN0 to TIN3
TOT0 to TOT3
Reload Timer
5 channels
FRCK0 to FRCK3
FIFO buffer
WS0
SCK0
SD0 to SD9
BRQ
BGRNTX
CS0X to CS6X
A23 to A00
BUS I/F
MLBCLK
MLBSIG
MLBDAT
MCLKE
MCLKI
MCLKO
WEX
BAAX
ICU0 to ICU3
I2S 10 channels
Free Run Timer
4 channels
Input Capture
4 channels
D31 to D16
16
A/D Convertor
12 channels
AN0 to AN11
ATGX
External Interrupt
16 channels
INT0 to INT15
General Purpose
Port
GPxx_x
LIN-USART
9 channels
SIN0 to SIN8
SOT0 to SOT8
SCK0 to SCK8
I2C
8 channels
SDA0 to SDA7
SCL0 to SCL7
Real Time Clock
OCU0 to OCU3
Output Compare
4 channels
Clock Controller
X0
Clock Controller
for MediaLB
30
DS07-16613-3E
MB91460M Series
■ CPU AND CONTROL UNIT
The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced
instructions for embedded applications.
1. Features
• Adoption of RISC architecture
Basic instruction: 1 instruction per cycle
• General-purpose registers: 32-bit × 16 registers
• 4 Gbytes linear memory space
• Multiplier installed
32-bit × 32-bit multiplication: 5 cycles
16-bit × 16-bit multiplication: 3 cycles
• Enhanced interrupt processing function
Quick response speed (6 cycles)
Multiple-interrupt support
Level mask function (16 levels)
• Enhanced instructions for I/O operation
Memory-to-memory transfer instruction
Bit processing instruction
Basic instruction word length: 16 bits
• Low-power consumption
Sleep mode/stop mode
2. Internal architecture
• The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent
of each other.
• A 32-bit ↔ 16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and
peripheral resources.
• A Harvard ↔ Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between
the CPU and the bus controller.
DS07-16613-3E
31
MB91460M Series
3. Programming model
3.1.
Basic programming model
32 bits
Initial value
R0
XXXX XXXXH
...
R1
General-purpose registers
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Program counter
PC
Program status
RS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiply & divide registers
MDH
ILM
SCR
CCR
MDL
32
DS07-16613-3E
MB91460M Series
4. Registers
4.1.
General-purpose register
32 bits
Initial value
R0
XXXX XXXXH
...
R1
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation
operations and as pointers for memory access.
Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular
applications.
R13 : Virtual accumulator
R14 : Frame pointer
R15 : Stack pointer
Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
4.2.
PS (Program Status)
This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.
All undefined bits (-) in the diagram are reserved bits. The read values are always “0”. Write access to these bits
is invalid.
Bit position → bit 31
bit 20
bit 16
ILM
DS07-16613-3E
bit 10 bit 8 bit 7
SCR
bit 0
CCR
33
MB91460M Series
4.3.
CCR (Condition Code Register)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SV
S
I
N
Z
V
C
Initial value
- 000XXXXB
SV : Supervisor flag
S
: Stack flag
I
: Interrupt enable flag
N : Negative enable flag
Z
: Zero flag
V
: Overflow flag
C : Carry flag
4.4.
SCR (System Condition Register)
bit 10 bit 9
D1
bit 8
D0
T
Initial value
XX0B
Flag for step division (D1, D0)
This flag stores interim data during execution of step division.
Step trace trap flag (T)
This flag indicates whether the step trace trap is enabled or disabled.
The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution
of user programs.
4.5.
ILM (Interrupt Level Mask register)
bit 20 bit 19 bit 18 bit 17 bit 16
Initial value
ILM4 ILM3 ILM2 ILM1 ILM0
01111B
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking.
The register is initialized to value “01111B” at reset.
4.6.
PC (Program Counter)
bit 31
bit 0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed.
The initial value at reset is undefined.
34
DS07-16613-3E
MB91460M Series
4.7.
TBR (Table Base Register)
bit 31
bit 0
Initial value
000FFC00H
The table base register stores the starting address of the vector table used in EIT processing.
The initial value at reset is 000FFC00H.
4.8.
RP (Return Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The return pointer stores the address for return from subroutines.
During execution of a CALL instruction, the PC value is transferred to this RP register.
During execution of a RET instruction, the contents of the RP register are transferred to PC.
The initial value at reset is undefined.
4.9.
USP (User Stack Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The user stack pointer, when the S flag is “1”, this register functions as the R15 register.
• The USP register can also be explicitly specified.
The initial value at reset is undefined.
• This register cannot be used with RETI instructions.
4.10. Multiply & divide registers
bit 31
MDH
MDL
bit 0
Initial value
XXXXXXXXH
XXXXXXXXH
These registers are for multiplication and division, and are 32 bits each in length.
The initial value at reset is undefined.
DS07-16613-3E
35
MB91460M Series
■ EMBEDDED PROGRAM/DATA MEMORY (FLASH)
1. Flash features
•
•
•
•
MB91F467MA: 1088 Kbytes (16 × 64 Kbytes + 8 × 8 Kbytes = 8.7 Mbits)
Programmable wait state for read/write access
Flash and Boot security with security vector at 0014:8000H to 0014:800FH
Basic specification: Same as MBM29LV400TC (except size and part of sector configuration)
2. Operation modes
(1) 64-bit CPU mode
• CPU reads and executes programs in word (32-bit) length units.
• Flash writing is not possible.
• Actual Flash Memory access is performed in d-word (64-bit) length units.
(2) 32-bit CPU mode :
• Actual Flash Memory access is performed in word (32-bit) length units.
(3) 16-bit CPU mode :
• CPU reads and writes in half-word (16-bit) length units.
• Program execution from the Flash is not possible.
• Actual Flash Memory access is performed in half-word (16-bit) length units.
36
DS07-16613-3E
MB91460M Series
3. Flash access in CPU mode
3.1.
Flash configuration
3.1.1.
Flash memory map MB91F467MA
Address
0014:FFFFH
0014:C000H
SA6 (8kB)
SA7 (8kB)
0014:BFFFH
0014:8000H
SA4 (8kB)
SA5 (8kB)
0014:7FFFH
0014:4000H
SA2 (8kB)
SA3 (8kB)
0014:3FFFH
0014:0000H
SA0 (8kB)
SA1 (8kB)
0013:FFFFH
0012:0000H
SA22 (64kB)
SA23 (64kB)
0011:FFFFH
0010:0000H
SA20 (64kB)
SA21 (64kB)
000F:FFFFH
000E:0000H
SA18 (64kB)
SA19 (64kB)
ROMS5
000D:FFFFH
000C:0000H
SA16 (64kB)
SA17 (64kB)
ROMS4
000B:FFFFH
000A:0000H
SA14 (64kB)
SA15 (64kB)
ROMS3
0009:FFFFH
0008:0000H
SA12 (64kB)
SA13 (64kB)
ROMS2
0007:FFFFH
0006:0000H
SA10 (64kB)
SA11 (64kB)
ROMS1
0005:FFFFH
0004:0000H
SA8 (64kB)
SA9 (64kB)
ROMS0
ROMS7
ROMS6
addr+0
16bit read/write
32bit read/write
64bit read
DS07-16613-3E
addr+1
addr+2
dat[31:16]
addr+3
addr+4
dat[15:0]
addr+5
addr+6
dat[31:16]
dat[31:0]
addr+7
dat[15:0]
dat[31:0]
dat[63:0]
37
MB91460M Series
3.2.
Flash access timing settings in CPU mode
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or
maximum clock modulation) for Flash read and write access.
3.2.1.
ATD
ALEH
EQ
WEXH
WTC
to 24 MHz
0
0
0
-
1
to 48 MHz
0
0
1
-
2
to 80 MHz
1
1
3
-
4
3.2.2.
38
Flash read timing settings (synchronous read)
Core clock (CLKB)
Remark
Flash write timing settings (synchronous write)
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 32 MHz
1
-
-
0
4
to 48 MHz
1
-
-
0
5
to 64 MHz
1
-
-
0
6
to 80 MHz
1
-
-
0
7
Remark
DS07-16613-3E
MB91460M Series
3.3.
Address mapping from CPU to parallel programming mode
The following tables show the calculation from CPU addresses to flash macro addresses which are used in
parallel programming.
Notes: • Address mapping MB91F467MA
CPU Address
Flash
Condition
(addr)
sectors
FA (flash address) Calculation
14:0000H
to
14:FFFFH
addr[2]=0
SA0, SA2, SA4, SA6
(8 Kbyte)
FA = addr - addr%00:4000H + (addr%00:4000H)/2
- (addr/2)%4 + addr%4 - 05:0000H
14:0000H
to
14:FFFFH
addr[2]=1
SA1, SA3, SA5, SA7
(8 Kbyte)
FA = addr - addr%00:4000H + (addr%00:4000H)/2
- (addr/2)%4 + addr%4 - 05:0000H
+ 00:2000H
04:0000H
to
13:FFFFH
addr[2]=0
SA8, SA10, SA12, SA14,
SA16, SA18, SA20, SA22
(64 Kbyte)
FA = addr - addr%02:0000H + (addr%02:0000H)/2
- (addr/2)%4 + addr%4 + 0C:0000H
04:0000H
to
13:FFFFH
addr[2]=1
SA9, SA11, SA13, SA15,
SA17, SA19, SA21, SA23
(64 Kbyte)
FA = addr - addr%02:0000H + (addr%02:0000H)/2
- (addr/2)%4 + addr%4 + 0C:0000H
+ 01:0000H
Notes: • FA result is without 20:0000H offset for parallel Flash programming.
Set offset by keeping FA[21] = 1 as described in section “Parallel Flash programming mode”.
• addr[2] is the value of the third lower bit when CPU address (addr) is described by binary numbers.
• FA[21] is the value of the twenty second lower bit when the flash address (FA) is described by binary
numbers.
• “%” represents remainder. For example, “addr%00:4000H” is the remainder after addr is divided by 4000H.
DS07-16613-3E
39
MB91460M Series
4. Parallel Flash programming mode
4.1.
Flash configuration in parallel Flash programming mode
Parallel Flash programming mode (MD[2:0] = 111):
MB91F467MA
FA[21:0]
003F:FFFFH
003F:0000H
SA23 (64kB)
003E:FFFFH
003E:0000H
SA22 (64kB)
003D:FFFFH
003D:0000H
SA21 (64kB)
003C:FFFFH
003C:0000H
SA20 (64kB)
003B:FFFFH
003B:0000H
SA19 (64kB)
003A:FFFFH
003A:0000H
SA18 (64kB)
0039:FFFFH
0039:0000H
SA17 (64kB)
0038:FFFFH
0038:0000H
SA16 (64kB)
0037:FFFFH
0037:0000H
SA15 (64kB)
0036:FFFFH
0036:0000H
SA14 (64kB)
0035:FFFFH
0035:0000H
SA13 (64kB)
0034:FFFFH
0034:0000H
SA12 (64kB)
0033:FFFFH
0033:0000H
SA11 (64kB)
0032:FFFFH
0032:0000H
SA10 (64kB)
0031:FFFFH
0031:0000H
SA9 (64kB)
0030:FFFFH
0030:0000H
SA8 (64kB)
002F:FFFFH
002F:E000H
SA7 (8kB)
002F:DFFFH
002F:C000H
SA6 (8kB)
002F:BFFFH
002F:A000H
SA5 (8kB)
002F:9FFFH
002F:8000H
SA4 (8kB)
002F:7FFFH
002F:6000H
SA3 (8kB)
002F:5FFFH
002F:4000H
SA2 (8kB)
002F:3FFFH
002F:2000H
SA1 (8kB)
002F:1FFFH
002F:0000H
SA0 (8kB)
16bit write mode
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
Note: Always keep FA[0] = 0 and FA[21] = 1.
40
DS07-16613-3E
MB91460M Series
4.2.
Pin connections in parallel programming mode
Resetting after setting the MD[4:0] pins to [00111] will halt CPU functioning. At this time, the Flash memory’s
interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of
the signals to general purpose ports. Please see table below for signal mapping.
In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set
when writing/erasing using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash
memory’s Auto Algorithms are available.
Correspondence between MBM29LV400TC and Flash Memory Control Signals
MBM29LV400TC
Flash memory
Normal
CPU mode
External pins
mode
function
Pin number
⎯
INITX
⎯
INITX
160
RESET
⎯
FRSTX
P13_2
19
⎯
⎯
MD2
MD2
157
⎯
⎯
MD1
MD1
156
⎯
⎯
MD0
MD0
155
RY/BY
FMCS:RDY
RY/BYX
P09_4
25
BYTE
“H”fixed
BYTEX
P13_1
18
WEX
P09_3
26
OEX
P09_2
27
CE
CEX
P09_1
28
A-1
FA0
P17_4
121
A0 to A7
FA1 to FA8
P17_5 to P17_7
P29_0 to P29_4
122 to 124
130 to 134
FA9 to FA16
P29_5 to P29_7
P28_0 to P28_3
P16_3
135 to 141
10
A16 to A19
FA17 to FA21
P16_4 to P16_6
P22_4, P22_5
9 to 7
147, 148
DQ0 to DQ7
DQ0 to DQ7
P36_2, P36_3
P39_0 to P39_5
106, 107
110 to 115
DQ8 to DQ15
P39_6, P39_7
P38_0, P38_1
P16_7
P35_0 to P35_2
116 to 120
125 to 127
WE
OE
A8 to A15
Internal bus control
Internal address
Internal data
DQ8 to DQ15
DS07-16613-3E
41
MB91460M Series
■ MEMORY SPACE
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct addressing area
The following address space area is used for I/O.
This area is called direct addressing area, and the address of an operand can be specified directly in an
instruction.
The size of directly addressable area depends on the length of the data being accessed as shown below.
Byte data access
: 000H to 0FFH
Half word access
: 000H to 1FFH
Word data access : 000H to 3FFH
42
DS07-16613-3E
MB91460M Series
■ MEMORY MAP
• MB91F467M
MB91F467M
0000:0000H
0000:00FFH
0000:0100H
0000:01FFH
0000:0200H
0000:03FFH
0000:0400H
0000:0FFFH
0000:1000H
0000:10FFH
0000:1100H
0000:1FFFH
0000:2000H
0000:3FFFH
0000:4000H
0000:5FFFH
0000:6000H
0000:6FFFH
0000:7000H
0000:70FFH
0000:7100H
0000:AFFFH
0000:B000H
0000:BFFFH
0000:C000H
0000:CFFFH
0000:D000H
0000:FFFFH
0001:0000H
0001:FFFFH
0002:0000H
0002:3FFFH
0002:4000H
I/O (byte)
I/O (Harf Word)
I/O (Word)
I/O
DMA
reserved
reserved
I-cache or I-RAM
(8 Kbytes)
MediaLB & I2S
Flash control
Flash I-cache
reserved
Boot ROM
(4 Kbytes)
CAN
reserved
ExtBUS I-cache or I-RAM
(4 Kbytes)
reserved
D-RAM (1wait)
(32 Kbytes)
0002:BFFFH
0002:C000H
0002:FFFFH
0003:0000H
0003:3FFFH
0003:4000H
D-RAM (No wait)
(16 Kbytes)
I/D-RAM
(16 Kbytes)
reserved
0003:FFFFH
0004:0000H
Flash
(1088 Kbytes)
or
External BUS
(depends on
ROMA/ROMS)
0014:FFFFH
0015:0000H
External BUS
FFFF:FFFFH
DS07-16613-3E
43
MB91460M Series
■ I/O MAP
1. MB91F467M
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W]
XXXXXXXX
PDR1 [R/W]
XXXXXXXX
PDR2 [R/W]
XXXXXXXX
PDR3 [R/W]
XXXXXXXX
Block
T-unit
port data register
Read/write attribute
Register initial value after reset
Register name (column 1 register at address 4n, column 2 register at
address 4n + 1...)
Leftmost register address (for word access, the register in column 1
becomes the MSB side of the data.)
Note: Initial values of register bits are represented as follows:
“ 1 ” : Initial value “ 1 ”
“ 0 ” : Initial value “ 0 ”
“ X ” : Initial value “ undefined ”
“ - ” : No physical register at this location
Access is barred with an undefined data access attribute.
44
DS07-16613-3E
MB91460M Series
Register
Address
+0
+1
000000H
PDR00 [R/W]
XXXXXXXX
PDR01 [R/W]
XXXXXXXX
000004H
Reserved
PDR05 [R/W]
XXXXXXXX
PDR06 [R/W]
XXXXXXXX
PDR07 [R/W]
XXXXXXXX
000008H
PDR08 [R/W]
XXXX--XX
PDR09 [R/W]
-XXXXXXX
PDR10 [R/W]
-XXXXXXX
PDR11 [R/W]
------XX
00000CH
Reserved
PDR13 [R/W]
-----XXX
PDR14 [R/W]
----XXXX
PDR15 [R/W]
XX--XXXX
000010H
PDR16 [R/W]
XXXXXXXX
PDR17 [R/W]
XXXXXXXX
PDR18 [R/W]
-XXX-XXX
PDR19 [R/W]
-XXX-XXX
000014H
PDR20 [R/W]
-XXX-XXX
PDR21 [R/W]
-XXX-XXX
PDR22 [R/W]
XXXXXXXX
PDR23 [R/W]
-X-XXXXX
000018H
PDR24 [R/W]
XXXXXXXX
00001CH
PDR28 [R/W]
----XXXX
000020H
+2
+3
Reserved
PDR36 [R/W]
XXX-XX--
000028H
PDR40 [R/W]
XXXXXXXX
00002CH
PDR29 [R/W]
XXXXXXXX
Reserved
PDR35 [R/W]
-----XXX
PDR38 [R/W]
------XX
Reserved
PDR39 [R/W]
XXXXXXXX
Reserved
Reserved
Reserved
000030H
EIRR0 [R/W]
00000000
ENIR0 [R/W]
00000000
ELVR0 [R/W]
00000000 00000000
000034H
EIRR1 [R/W]
00000000
ENIR1 [R/W]
00000000
ELVR1 [R/W]
00000000 00000000
000038H
DICR [R/W]
-------0
HRCL [R/W]
0--11111
RBSYNC [R]
XXXXXXXX XXXXXXXX
Reserved
00003CH
SCR00 [R/W, W]
00000000
SMR00 [R/W, W]
00000000
000044H
ESCR00 [R/W]
00000X00
ECCR00
[R/W, R, W]
-00000XX
000048H
SCR01 [R/W, W]
00000000
SMR01 [R/W, W]
00000000
ESCR01 [R/W]
00000X00
ECCR01
[R/W, R, W]
-00000XX
000040H
00004CH
Port Data Register
[R-bus]
Reserved
Reserved
000024H
Block
External interrupt
Delay Interrupt
I-unit
Reserved
SSR00 [R/W, R]
00001000
RDR00/TDR00
[R/W]
00000000
LIN-USART 0
Reserved
SSR01 [R/W, R]
00001000
RDR01/TDR01
[R/W]
00000000
LIN-USART 1
Reserved
(Continued)
DS07-16613-3E
45
MB91460M Series
Address
Register
+0
+1
+2
+3
000050H
SCR02 [R/W, W]
00000000
SMR02 [R/W, W]
00000000
SSR02 [R/W, R]
00001000
RDR02/TDR02
[R/W]
00000000
000054H
ESCR02 [R/W]
00000X00
ECCR02
[R/W, R, W]
-00000XX
000058H
SCR03 [R/W, W]
00000000
SMR03 [R/W, W]
00000000
00005CH
ESCR03 [R/W]
00000X00
ECCR03
[R/W, R, W]
-00000XX
000060H
SCR04 [R/W, W]
00000000
SMR04 [R/W, W]
00000000
SSR04 [R/W, R]
00001000
RDR04/TDR04
[R/W]
00000000
000064H
ESCR04 [R/W]
00000X00
ECCR04
[R/W, R, W]
-00000XX
FSR04 [R]
---00000
FCR04 [R/W]
0001-000
000068H
SCR05 [R/W, W]
00000000
SMR05 [R/W, W]
00000000
SSR05 [R/W, R]
00001000
RDR05/TDR05
[R/W]
00000000
00006CH
ESCR05 [R/W]
00000X00
ECCR05
[R/W, R, W]
-00000XX
FSR05 [R]
---00000
FCR05 [R/W]
0001-000
000070H
SCR06 [R/W, W]
00000000
SMR06 [R/W, W]
00000000
SSR06 [R/W, R]
00001000
RDR06/TDR06
[R/W]
00000000
000074H
ESCR06 [R/W]
00000X00
ECCR06
[R/W, R, W]
-00000XX
FSR06 [R]
---00000
FCR06 [R/W]
0001-000
000078H
SCR07 [R/W, W]
00000000
SMR07 [R/W, W]
00000000
SSR07 [R/W, R]
00001000
RDR07/TDR07
[R/W]
00000000
00007CH
ESCR07 [R/W]
00000X00
ECCR07
[R/W, R, W]
-00000XX
FSR07 [R]
---00000
FCR07 [R/W]
0001-000
000080H
BGR100 [R/W]
00000000
BGR000 [R/W]
00000000
BGR101 [R/W]
00000000
BGR001 [R/W]
00000000
000084H
BGR102 [R/W]
00000000
BGR002 [R/W]
00000000
BGR103 [R/W]
00000000
BGR003 [R/W]
00000000
000088H
BGR104 [R/W]
00000000
BGR004 [R/W]
00000000
BGR105 [R/W]
00000000
BGR005 [R/W]
00000000
00008CH
BGR106 [R/W]
00000000
BGR006 [R/W]
00000000
BGR107 [R/W]
00000000
BGR007 [R/W]
00000000
Block
LIN-USART 2
Reserved
SSR03 [R/W, R]
00001000
RDR03/TDR03
[R/W]
00000000
LIN-USART 3
Reserved
LIN-USART 4
with FIFO
LIN-USART 5
with FIFO
LIN-USART 6
with FIFO
LIN-USART 7
with FIFO
Baud rate
Generator
LIN-USART
0 to 7
(Continued)
46
DS07-16613-3E
MB91460M Series
Register
Address
+0
+1
000090H
to
0000CCH
+2
+3
Reserved
Reserved
0000D0H
IBCR0 [R/W]
00000000
IBSR0 [R]
00000000
ITBAH0 [R/W]
------00
ITBAL0 [R/W]
00000000
0000D4H
ITMKH0 [R/W]
00----11
ITMKL0 [R/W]
11111111
ISMK0 [R/W]
01111111
ISBA0 [R/W]
-0000000
0000D8H
Reserved
IDAR0 [R/W]
00000000
ICCR0 [R/W]
-0011111
Reserved
0000DCH
IBCR1 [R/W]
00000000
IBSR1 [R]
00000000
ITBAH1 [R/W]
------00
ITBAL1 [R/W]
00000000
0000E0H
ITMKH1 [R/W]
00----11
ITMKL1 [R/W]
11111111
ISMK1 [R/W]
01111111
ISBA1 [R/W]
-0000000
0000E4H
Reserved
IDAR1 [R/W]
00000000
ICCR1 [R/W]
-0011111
Reserved
0000E8H
to
0000FCH
Block
Reserved
I2C 0
I2C 1
Reserved
000100H
GCN10 [R/W]
00110010 00010000
Reserved
GCN20 [R/W]
----0000
PPG Control
0-3
000104H
GCN11 [R/W]
00110010 00010000
Reserved
GCN21 [R/W]
----0000
PPG Control
4-7
000108H,
00010CH
Reserved
000110H
PTMR00 [R]
11111111 11111111
000114H
PDUT00 [W]
XXXXXXXX XXXXXXXX
000118H
PTMR01 [R]
11111111 11111111
00011CH
PDUT01 [W]
XXXXXXXX XXXXXXXX
000120H
PTMR02 [R]
11111111 11111111
000124H
PDUT02 [W]
XXXXXXXX XXXXXXXX
000128H
PTMR03 [R]
11111111 11111111
00012CH
PDUT03 [W]
XXXXXXXX XXXXXXXX
Reserved
PCSR00 [W]
XXXXXXXX XXXXXXXX
PCNH00 [R/W]
0000000-
PCNL00 [R/W]
000000-0
PCSR01 [W]
XXXXXXXX XXXXXXXX
PCNH01 [R/W]
0000000-
PCNL01 [R/W]
000000-0
PCSR02 [W]
XXXXXXXX XXXXXXXX
PCNH02 [R/W]
0000000-
PCNL02 [R/W]
000000-0
PCSR03 [W]
XXXXXXXX XXXXXXXX
PCNH03 [R/W]
0000000-
PCNL03 [R/W]
000000-0
PPG 0
PPG 1
PPG 2
PPG 3
(Continued)
DS07-16613-3E
47
MB91460M Series
Address
Register
+0
+1
000130H
PTMR04 [R]
11111111 11111111
000134H
PDUT04 [W]
XXXXXXXX XXXXXXXX
000138H
PTMR05 [R]
11111111 11111111
00013CH
PDUT05 [W]
XXXXXXXX XXXXXXXX
000140H
PTMR06 [R]
11111111 11111111
000144H
PDUT06 [W]
XXXXXXXX XXXXXXXX
000148H
PTMR07 [R]
11111111 11111111
00014CH
PDUT07 [W]
XXXXXXXX XXXXXXXX
000150H
to
00017CH
000180H
+2
+3
PCSR04 [W]
XXXXXXXX XXXXXXXX
PCNH04 [R/W]
0000000-
PCNL04 [R/W]
000000-0
PCSR05 [W]
XXXXXXXX XXXXXXXX
PCNH05 [R/W]
0000000-
PCNL05 [R/W]
000000-0
PCSR06 [W]
XXXXXXXX XXXXXXXX
PCNH06 [R/W]
0000000-
PCNL06 [R/W]
000000-0
PCSR07 [W]
XXXXXXXX XXXXXXXX
PCNH07 [R/W]
0000000-
PCNL07 [R/W]
000000-0
Reserved
Reserved
ICS01 [R/W]
00000000
Reserved
IPCP1 [R]
XXXXXXXX XXXXXXXX
000188H
IPCP2 [R]
XXXXXXXX XXXXXXXX
IPCP3 [R]
XXXXXXXX XXXXXXXX
00018CH
OCS01 [R/W]
---0--00 0000--00
OCS23 [R/W]
---0--00 0000--00
000190H
OCCP0 [R/W]
XXXXXXXX XXXXXXXX
OCCP1 [R/W]
XXXXXXXX XXXXXXXX
000194H
OCCP2 [R/W]
XXXXXXXX XXXXXXXX
OCCP3 [R/W]
XXXXXXXX XXXXXXXX
Reserved
ADERH [R/W]
00000000 00000000
PPG 6
PPG 7
Input Capture
0 to 3
Input Capture
0 to 3
Reserved
ADERL [R/W]
00000000 00000000
0001A4H
ADCS1 [R/W]
00000000
ADCS0 [R/W]
00000000
ADCR1 [R]
000000XX
ADCR0 [R]
XXXXXXXX
0001A8H
ADCT1 [R/W]
00010000
ADCT0 [R/W]
00101100
ADSCH [R/W]
---00000
ADECH [R/W]
---00000
0001ACH
PPG 5
ICS23 [R/W]
00000000
IPCP0 [R]
XXXXXXXX XXXXXXXX
0001A0H
PPG 4
Reserved
000184H
000198H,
00019CH
Block
Reserved
A/D
Converter
Reserved
(Continued)
48
DS07-16613-3E
MB91460M Series
Address
Register
+0
+1
0001B0H
TMRLR0 [W]
XXXXXXXX XXXXXXXX
0001B4H
Reserved
0001B8H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
0001BCH
Reserved
0001C0H
TMRLR2 [W]
XXXXXXXX XXXXXXXX
0001C4H
Reserved
0001C8H
TMRLR3 [W]
XXXXXXXX XXXXXXXX
0001CCH
Reserved
0001D0H
to
0001E4H
+2
+3
TMR0 [R]
XXXXXXXX XXXXXXXX
TMCSRH0 [R/W]
---00000
TMCSRL0 [R/W]
0-000000
TMR1 [R]
XXXXXXXX XXXXXXXX
TMCSRH1 [R/W]
---00000
TMCSRL1 [R/W]
0-000000
TMR2 [R]
XXXXXXXX XXXXXXXX
TMCSRH2 [R/W]
---00000
TMCSRL2 [R/W]
0-000000
TMR3 [R]
XXXXXXXX XXXXXXXX
TMCSRH3 [R/W]
---00000
TMCSRL3 [R/W]
0-000000
Reserved
Block
Reload Timer 0
(PPG0, PPG1)
Reload Timer 1
(PPG2, PPG3)
Reload Timer 2
(PPG4, PPG5)
Reload Timer 3
(PPG6, PPG7)
Reserved
0001E8H
TMRLR7 [W]
XXXXXXXX XXXXXXXX
TMR7 [R]
XXXXXXXX XXXXXXXX
0001ECH
Reserved
TMCSRH7 [R/W]
---00000
TMCSRL7 [R/W]
0-000000
0001F0H
TCDT0 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS0 [R/W]
00000000
Free-run Timer 0
(ICU0, ICU1)
0001F4H
TCDT1 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS1 [R/W]
00000000
Free-run Timer 1
(ICU2, ICU3)
0001F8H
TCDT2 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS2 [R/W]
00000000
Free-run Timer 2
(OCU0, OCU1)
0001FCH
TCDT3 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS3 [R/W]
00000000
Free-run Timer 3
(OCU2, OCU3)
000200H
DMACA0 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
Reload Timer 7
(A/D Converter)
DMAC
(Continued)
DS07-16613-3E
49
MB91460M Series
Address
Register
+0
+1
+2
+3
000210H
DMACA2 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH
Reserved
000240H
DMACR [R/W]
0--00000
DMAC
Reserved
000244H
to
00027CH
Reserved
000280H
SCR08 [R/W, W]
00000000
SMR08 [R/W, W]
00000000
000284H
ESCR08 [R/W]
00000X00
ECCR08
[R/W, R, W]
000000XX
000288H
to
0002BCH
0002C0H
Reserved
SSR08 [R/W, R]
00001000
RDR08/TDR08
[R/W]
00000000
BGR008 [R/W]
00000000
0002C4H
to
000364H
LIN-USART 8
Reserved
Reserved
BGR108 [R/W]
00000000
Block
Reserved
Baud rate
Generator
LIN-USART8
Reserved
Reserved
Reserved
000368H
IBCR2 [R/W]
00000000
IBSR2 [R]
00000000
ITBAH2 [R/W]
------00
ITBAL2 [R/W]
00000000
00036CH
ITMKH2 [R/W]
00----11
ITMKL2 [R/W]
11111111
ISMK2 [R/W]
01111111
ISBA2 [R/W]
-0000000
000370H
Reserved
IDAR2 [R/W]
00000000
ICCR2 [R/W]
-0011111
Reserved
I2C 2
(Continued)
50
DS07-16613-3E
MB91460M Series
Register
Address
+0
+1
+2
+3
000374H
IBCR3 [R/W]
00000000
IBSR3 [R]
00000000
ITBAH3 [R/W]
------00
ITBAL3 [R/W]
00000000
000378H
ITMKH3 [R/W]
00----11
ITMKL3 [R/W]
11111111
ISMK3 [R/W]
01111111
ISBA3 [R/W]
-0000000
00037CH
Reserved
IDAR3 [R/W]
00000000
ICCR3 [R/W]
-0011111
Reserved
000380H
IBCR4 [R/W]
00000000
IBSR4 [R]
00000000
ITBAH4 [R/W]
------00
ITBAL4 [R/W]
00000000
000384H
ITMKH4 [R/W]
00----11
ITMKL4 [R/W]
11111111
ISMK4 [R/W]
01111111
ISBA4 [R/W]
-0000000
000388H
Reserved
IDAR4 [R/W]
00000000
ICCR4 [R/W]
-0011111
Reserved
00038CH
Reserved
ROMS [R]
11111111 00000000
000390H
IBSR5 [R]
00000000
ITBAH5 [R/W]
------00
ITBAL5 [R/W]
00000000
000398H
ITMKH5 [R/W]
00----11
ITMKL5 [R/W]
11111111
ISMK5 [R/W]
01111111
ISBA5 [R/W]
-0000000
00039CH
Reserved
IDAR5 [R/W]
00000000
ICCR5 [R/W]
-0011111
Reserved
0003A0H
IBCR6 [R/W]
00000000
IBSR6 [R]
00000000
ITBAH6 [R/W]
------00
ITBAL6 [R/W]
00000000
0003A4H
ITMKH6 [R/W]
00----11
ITMKL6 [R/W]
11111111
ISMK6 [R/W]
01111111
ISBA6 [R/W]
-0000000
0003A8H
Reserved
IDAR6 [R/W]
00000000
ICCR6 [R/W]
-0011111
Reserved
0003ACH
IBCR7 [R/W]
00000000
IBSR7 [R]
00000000
ITBAH7 [R/W]
------00
ITBAL7 [R/W]
00000000
0003B0H
ITMKH7 [R/W]
00----11
ITMKL7 [R/W]
11111111
ISMK7 [R/W]
01111111
ISBA7 [R/W]
-0000000
0003B4H
Reserved
IDAR7 [R/W]
00000000
ICCR7 [R/W]
-0011111
Reserved
Reserved
Reserved
I2C 4
ROM
Select Register
Reserved
IBCR5 [R/W]
00000000
0003C4H
I2C 3
Reserved
000394H
0003B8H,
to
0003C0H
Block
I2C 5
I2C 6
I2C 7
Reserved
ISIZE [R/W]
------10
I-Cache
(Continued)
DS07-16613-3E
51
MB91460M Series
Address
Register
+0
+1
0003C8H
to
0003E0H
+2
+3
Reserved
Reserved
ICHCR [R/W]
0-000000
Reserved
0003E4H
Block
0003E8H,
0003ECH
Reserved
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
to
00043CH
Reserved
I-Cache
Reserved
Bit search
Reserved
000440H
ICR00 [R/W]
---11111
ICR01 [R/W]
---11111
ICR02 [R/W]
---11111
ICR03 [R/W]
---11111
000444H
ICR04 [R/W]
---11111
ICR05 [R/W]
---11111
ICR06 [R/W]
---11111
ICR07 [R/W]
---11111
000448H
ICR08 [R/W]
---11111
ICR09 [R/W]
---11111
Reserved
ICR11 [R/W]
---11111
00044CH
ICR12 [R/W]
---11111
ICR13 [R/W]
---11111
000450H
ICR16 [R/W]
---11111
000454H
ICR20 [R/W]
---11111
ICR21 [R/W]
---11111
ICR22 [R/W]
---11111
ICR23 [R/W]
---11111
000458H
Reserved
ICR25 [R/W]
---11111
ICR26 [R/W]
---11111
ICR27 [R/W]
---11111
00045CH
ICR28 [R/W]
---11111
ICR29 [R/W]
---11111
ICR30 [R/W]
---11111
ICR31 [R/W]
---11111
000460H
Reserved
ICR33 [R/W]
---11111
000464H
ICR36 [R/W]
---11111
ICR37 [R/W]
---11111
Reserved
ICR19 [R/W]
---11111
Reserved
Interrupt Control
Unit
Reserved
ICR38 [R/W]
---11111
ICR39 [R/W]
---11111
(Continued)
52
DS07-16613-3E
MB91460M Series
Register
Address
+0
+1
000468H
Reserved
00046CH
000470H
+2
+3
ICR42 [R/W]
---11111
ICR43 [R/W]
---11111
Reserved
ICR48 [R/W]
---11111
ICR49 [R/W]
---11111
ICR50 [R/W]
---11111
ICR51 [R/W]
---11111
Reserved
000474H
000478H
Reserved
ICR58 [R/W]
---11111
ICR59 [R/W]
---11111
00047CH
Reserved
ICR61 [R/W]
---11111
ICR62 [R/W]
---11111
ICR63 [R/W]
---11111
000480H
RSRR [R/W]
10000000
STCR [R/W]
00110011
TBCR [R/W]
00XXX-00
CTBR [W]
XXXXXXXX
000484H
CLKR [R/W]
----0000
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011
DIVR1 [R/W]
00000000
00048CH
PLLDIVM [R/W]
----0000
000490H
PLLCTRL [R/W]
----0000
PLLDIVN [R/W]
--000000
PLLDIVG [R/W]
----0000
PLLMULG [R/W]
00000000
Reserved
000494H
Reserved
PORTEN [R/W]
------00
Clock Control Unit
Port Input Enable
Control
Reserved
WTCER [R/W]
------00
0004A0H
Reserved
0004A4H
Reserved
0004A8H
WTHR [R/W]
---00000
Reserved
WTCR [R/W]
00000000 000-00-X
WTBR [R/W]
---XXXXX XXXXXXXX XXXXXXXX
WTMR [R/W]
--000000
WTSR [R/W]
--000000
Reserved
CSCFG [R/W]
0X000000
CMCFG [R/W]
00000000
0004ACH
Reserved
0004B0H
CUCR [R/W]
-------- ---0--00
CUTD [R/W]
10000000 00000000
0004B4H
CUTR1 [R]
-------- 00000000
CUTR2 [R]
00000000 00000000
0004B8H
CMPR [R/W]
--000010 11111101
0004BCH
CMT1 [R/W]
00000000 1---0000
CANPRE [R/W]
00000000
PLL
Clock Gear Unit
Reserved
Reserved
00049CH
0004C0H
Interrupt Control
Unit
Reserved
000488H
000498H
Block
Reserved
CMCR [R/W]
-001--00
CMT2 [R/W]
--000000 --000000
Reserved
Real Time Clock
(Watch Timer)
Clock Monitor
Sub-Oscillation
Calibration Unit
Clock Modulator
CAN Clock Control
(Continued)
DS07-16613-3E
53
MB91460M Series
Address
0004C4H
Register
+0
+1
Reserved
0004C8H
OSCRH [R/W]
000--001
0004CCH
OSCCR [R/W]
------00
Reserved
0004D4H
0004D8H
HWWDE [R/W]
------00
HWWD [R/W]
00011000
Hardware-Watchdog
WPCRH [R/W]
000--001
Reserved
Main-/Sub-Oscillation
Stabilization Timer
Main- Oscillation
Standby Control
Reserved
SHDE [R/W]
0-------
Reserved
EXTE [R/W]
00000000
EXTLV [R/W]
00000000 00000000
0004DCH
to
0004E4H
0004E8H
+3
Reserved
0004D0H
0004ECH,
0004F0H
Shutdown control
Reserved
Reserved
MLBCNT [R/W]
000----0
MLBPRE [R/W]
--000000
Reserved
MPLLDIVM [R/W] MPLLDIVN [R/W] MPLLDIVG [R/W]
----0000
--000000
----0000
0004F8H
MPLLCTRL [R/W]
----0000
Reserved
Reserved
MediaLB
Clock Control
Reserved
0004F4H
0004FCH
to
00063CH
EXTF [R/W]
00000000
Reserved
Reserved
Block
+2
MPLLMULG [R/
W]
00000000
MediaLB
PLL
Clock Gear Unit
Reserved
(Continued)
54
DS07-16613-3E
MB91460M Series
Register
Address
+0
+1
+2
+3
000640H
ASR0 [R/W]
00000000 00000000
ACR0 [R/W]
1111**00 00100000*1
000644H
ASR1 [R/W]
XXXXXXXX XXXXXXXX
ACR1 [R/W]
XXXXXXXX XXXXXXXX
000648H
ASR2 [R/W]
XXXXXXXX XXXXXXXX
ACR2 [R/W]
XXXXXXXX XXXXXXXX
00064CH
ASR3 [R/W]
XXXXXXXX XXXXXXXX
ACR3 [R/W]
XXXXXXXX XXXXXXXX
000650H
ASR4 [R/W]
XXXXXXXX XXXXXXXX
ACR4 [R/W]
XXXXXXXX XXXXXXXX
000654H
ASR5 [R/W]
XXXXXXXX XXXXXXXX
ACR5 [R/W]
XXXXXXXX XXXXXXXX
000658H
ASR6 [R/W]
XXXXXXXX XXXXXXXX
ACR6 [R/W]
XXXXXXXX XXXXXXXX
00065CH
Reserved
000660H
AWR0 [R/W]
01001111 11111011
AWR1 [R/W]
XXXXXXXX XXXXXXXX
000664H
AWR2 [R/W]
XXXXXXXX XXXXXXXX
AWR3 [R/W]
XXXXXXXX XXXXXXXX
000668H
AWR4 [R/W]
XXXXXXXX XXXXXXXX
AWR5 [R/W]
XXXXXXXX XXXXXXXX
00066CH
AWR6 [R/W]
XXXXXXXX XXXXXXXX
Reserved
000670H
MCRA [R/W]
XXXXXXXX
000674H
000678H
Block
MCRB [R/W]
XXXXXXXX
External bus Unit
Reserved
Reserved
IOWR0 [R/W]
XXXXXXXX
00067CH
IOWR1 [R/W]
XXXXXXXX
IOWR2 [R/W]
XXXXXXXX
IOWR3 [R/W]
XXXXXXXX
Reserved
000680H
CSER [R/W]
-0000001
CHER [R/W]
-1111111
000684H
RCRH [R/W]
00XXXXXX
RCRL [R/W]
XXXX0XXX
000688H
to
0007F8H
0007FCH
000800H
to
000CFCH
Reserved
TCR [R/W]
0000**** *2
Reserved
Reserved
Reserved
MODR [W]
XXXXXXXX
Reserved
Reserved
Mode register
Reserved
*1 : ACR0 [11:10] depends on the mode vector fetch information of bus width.
*2 : TCR [3:0] INIT value = 0000, and keeps the value after RST.
(Continued)
DS07-16613-3E
55
MB91460M Series
Address
Register
+0
+1
000D00H
PDRD00 [R]
XXXXXXXX
PDRD01 [R]
XXXXXXXX
000D04H
Reserved
PDRD05 [R]
XXXXXXXX
PDRD06 [R]
XXXXXXXX
PDRD07 [R]
XXXXXXXX
000D08H
PDRD08 [R]
XXXX--XX
PDRD09 [R]
-XXXXXXX
PDRD10 [R]
-XXXXXXX
PDRD11 [R]
------XX
000D0CH
Reserved
PDRD13 [R]
-----XXX
PDRD14 [R]
----XXXX
PDRD15 [R]
XX--XXXX
000D10H
PDRD16 [R]
XXXXXXXX
PDRD17 [R]
XXXXXXXX
PDRD18 [R]
-XXX-XXX
PDRD19 [R]
-XXX-XXX
000D14H
PDRD20 [R]
-XXX-XXX
PDRD21 [R]
-XXX-XXX
PDRD22 [R]
XXXXXXXX
PDRD23 [R]
-X-XXXXX
000D18H
PDRD24 [R]
XXXXXXXX
000D1CH
PDRD28 [R]
----XXXX
000D20H
+3
PDRD36 [R]
XXX-XX--
000D28H
PDRD40 [R]
XXXXXXXX
Block
Reserved
Port Data Direct Read
Register
[R-bus]
Reserved
PDRD29 [R]
XXXXXXXX
Reserved
PDRD35 [R]
-----XXX
Reserved
000D24H
000D2CH
to
000D3CH
+2
Reserved
PDRD38 [R]
------XX
PDRD39 [R]
XXXXXXXX
Reserved
Reserved
Reserved
(Continued)
56
DS07-16613-3E
MB91460M Series
Register
Address
+0
+1
000D40H
DDR00 [R/W]
00000000
DDR01 [R/W]
00000000
000D44H
Reserved
DDR05 [R/W]
00000000
DDR06 [R/W]
00000000
DDR07 [R/W]
00000000
000D48H
DDR08 [R/W]
0000--00
DDR09 [R/W]
-0000000
DDR10 [R/W]
-0000000
DDR11 [R/W]
------00
000D4CH
Reserved
DDR13 [R/W]
-----000
DDR14 [R/W]
----0000
DDR15 [R/W]
00--0000
000D50H
DDR16 [R/W]
00000000
DDR17 [R/W]
00000000
DDR18 [R/W]
-000-000
DDR19 [R/W]
-000-000
000D54H
DDR20 [R/W]
-000-000
DDR21 [R/W]
-000-000
DDR22 [R/W]
00000000
DDR23 [R/W]
-0-00000
000D58H
DDR24 [R/W]
00000000
000D5CH
DDR28 [R/W]
----0000
000D60H
+2
+3
Reserved
DDR36 [R/W]
000-00--
000D68H
DDR40 [R/W]
00000000
000D6CH
to
000D7CH
Port Direction
Register
[R-bus]
Reserved
DDR29 [R/W]
00000000
Reserved
DDR35 [R/W]
-----000
Reserved
000D64H
Block
Reserved
DDR38 [R/W]
------00
DDR39 [R/W]
00000000
Reserved
Reserved
Reserved
(Continued)
DS07-16613-3E
57
MB91460M Series
Address
Register
+0
+1
+2
+3
000D80H
PFR00 [R/W]
11111111
PFR01 [R/W]
11111111
000D84H
Reserved
PFR05 [R/W]
11111111
PFR06 [R/W]
11111111
PFR07 [R/W]
11111111
000D88H
PFR08 [R/W]
1111--11
PFR09 [R/W]
-1111111
PFR10 [R/W]
-1111111
PFR11 [R/W]
------00
000D8CH
Reserved
PFR13 [R/W]
-----000
PFR14 [R/W]
----0000
PFR15 [R/W]
00--0000
000D90H
PFR16 [R/W]
0-------
PFR17 [R/W]
00000000
PFR18 [R/W]
-000-000
PFR19 [R/W]
-000-000
000D94H
PFR20 [R/W]
-000-000
PFR21 [R/W]
-000-000
PFR22 [R/W]
00000000
PFR23 [R/W]
-0-00000
000D98H
PFR24 [R/W]
00000000
000D9CH
PFR28 [R/W]
----0000
Reserved
PFR29 [R/W]
00000000
Reserved
PFR35 [R/W]
-----000
Reserved
PFR36 [R/W]
000-00--
000DA8H
PFR40 [R/W]
00000000
PFR38 [R/W]
------00
Reserved
PFR39 [R/W]
00000000
Reserved
000DACH
to
000DBCH
Reserved
000DC0H,
000DC4H
Reserved
000DC8H
Reserved
Reserved
EPFR10 [R/W]
--00---0
Reserved
000DCCH
Reserved
EPFR13 [R/W]
----0--
EPFR14 [R/W]
----0000
EPFR15 [R/W]
----0000
000DD0H
EPFR16 [R/W]
0-------
Reserved
EPFR18 [R/W]
-00--00-
EPFR19 [R/W]
-0---0--
000DD4H
EPFR20 [R/W]
-0---0--
EPFR21 [R/W]
-0---0--
EPFR22 [R/W]
----0-0-
Reserved
000DD8H,
000DDCH
000DE0H
000DE4H
to
000DFCH
Port Function
Register
[R-bus]
Reserved
000DA0H
000DA4H
Block
Port Expansion
Function Register
[R-bus]
Reserved
EPFR35 [R/W]
-----000
Reserved
Reserved
Reserved
(Continued)
58
DS07-16613-3E
MB91460M Series
Register
Address
+0
+1
000E00H
to
000E3CH
+2
+3
Reserved
Reserved
000E40H
PILR00 [R/W]
00000000
PILR01 [R/W]
00000000
000E44H
Reserved
PILR05 [R/W]
00000000
PILR06 [R/W]
00000000
PILR07 [R/W]
00000000
000E48H
PILR08 [R/W]
0000--00
PILR09 [R/W]
-0000000
PILR10 [R/W]
-0000000
PILR11 [R/W]
------00
000E4CH
Reserved
PILR13 [R/W]
-----000
PILR14 [R/W]
----0000
PILR15 [R/W]
00--0000
000E50H
PILR16 [R/W]
00000000
PILR17 [R/W]
00000000
PILR18 [R/W]
-000-000
PILR19 [R/W]
-000-000
000E54H
PILR20 [R/W]
-000-000
PILR21 [R/W]
-000-000
PILR22 [R/W]
00000000
PILR23 [R/W]
-0-00000
000E58H
PILR24 [R/W]
00000000
000E5CH
PILR28 [R/W]
----0000
000E60H
Reserved
PILR36 [R/W]
000-00--
000E68H
PILR40 [R/W]
00000000
000E6CH
to
000E7CH
Port Input Level
Select Register
[R-bus]
Reserved
PILR29 [R/W]
00000000
Reserved
PILR35 [R/W]
-----000
Reserved
000E64H
Block
Reserved
PILR38 [R/W]
------00
PILR39 [R/W]
00000000
Reserved
Reserved
Reserved
(Continued)
DS07-16613-3E
59
MB91460M Series
Address
Register
+0
+1
000E80H
to
000E88H
+2
+3
EPILR14 [R/W]
----0000
EPILR15 [R/W]
----0000
Block
Reserved
000E8CH
Reserved
000E90H
Reserved
EPILR17 [R/W]
----0000
EPILR18 [R/W]
-----000
EPILR19 [R/W]
-000-000
000E94H
EPILR20 [R/W]
-000-000
EPILR21 [R/W]
-000-000
EPILR22 [R/W]
00000000
EPILR23 [R/W]
-0-00000
000E98H
EPILR24 [R/W]
00000000
Reserved
000E9CH,
000EA0H
Port Expansion
Input Level Select
Register
[R-bus]
Reserved
000EA4H
EPILR36 [R/W]
000-----
Reserved
000EA8H
EPILR40 [R/W]
00000000
Reserved
000EACH
to
000EBCH
Reserved
Reserved
000EC0H
PPER00 [R/W]
00000000
PPER01 [R/W]
00000000
000EC4H
Reserved
PPER05 [R/W]
00000000
PPER06 [R/W]
00000000
PPER07 [R/W]
00000000
000EC8H
PPER08 [R/W]
0000--00
PPER09 [R/W]
-0000000
PPER10 [R/W]
-0000000
PPER11 [R/W]
------00
000ECCH
Reserved
PPER13 [R/W]
-----000
PPER14 [R/W]
----0000
PPER15 [R/W]
0---0000
000ED0H
PPER16 [R/W]
00000000
PPER17 [R/W]
00000000
PPER18 [R/W]
-000-000
PPER19 [R/W]
-000-000
000ED4H
PPER20 [R/W]
-000-000
PPER21 [R/W]
-000-000
PPER22 [R/W]
00000000
PPER23 [R/W]
-0-00000
000ED8H
PPER24 [R/W]
00000000
000EDCH
PPER28 [R/W]
----0000
000EE0H
Reserved
Reserved
PPER29 [R/W]
00000000
Reserved
PPER35 [R/W]
-----000
Reserved
000EE4H
PPER36 [R/W]
000-00--
000EE8H
PPER40 [R/W]
00000000
Port Pull-Up/Down
Enable Register
[R-bus]
Reserved
PPER38 [R/W]
------00
PPER39 [R/W]
00000000
Reserved
(Continued)
60
DS07-16613-3E
MB91460M Series
Register
Address
+0
+1
000EECH
to
000EFCH
+2
+3
Reserved
Reserved
000F00H
PPCR00 [R/W]
11111111
PPCR01 [R/W]
11111111
000F04H
Reserved
PPCR05 [R/W]
11111111
PPCR06 [R/W]
11111111
PPCR07 [R/W]
11111111
000F08H
PPCR08 [R/W]
1111--11
PPCR09 [R/W]
-1111111
PPCR10 [R/W]
-1111111
PPCR11 [R/W]
------11
000F0CH
Reserved
PPCR13 [R/W]
-----111
PPCR14 [R/W]
----1111
PPCR15 [R/W]
1---1111
000F10H
PPCR16 [R/W]
11111111
PPCR17 [R/W]
11111111
PPCR18 [R/W]
-111-111
PPCR19 [R/W]
-111-111
000F14H
PPCR20 [R/W]
-111-111
PPCR21 [R/W]
-111-111
PPCR22 [R/W]
11111111
PPCR23 [R/W]
-1-11111
000F18H
PPCR24 [R/W]
11111111
000F1CH
PPCR28 [R/W]
----1111
000F20H
Reserved
PPCR36 [R/W]
111-11--
000F28H
PPCR40 [R/W]
11111111
000F20H
to
000FFCH
Port Pull-Up/Down
Control Register
[R-bus]
Reserved
PPCR29 [R/W]
11111111
Reserved
PPCR35 [R/W]
-----111
Reserved
000F24H
Block
Reserved
PPCR38 [R/W]
------11
PPCR39 [R/W]
11111111
Reserved
Reserved
Reserved
(Continued)
DS07-16613-3E
61
MB91460M Series
Address
Register
+0
+1
+2
001000H
DMASA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to
005FFCH
Reserved
006000H
DCCR [R/W]
00000000 0------- -------- 00000000
006004H
SSCR [R/W]
-------- -------- -------- 00000000
006008H
SDCR [R/W]
00000000 00000000 00000000 0000000
00600CH
SMCR [R/W]
-------- -------- -------- -1100000
006010H
to
006018H
Reserved
00601CH
VCCR [R]
-------- 00000001 00000010 00000010
006020H
to
00602CH
Reserved
006030H
CICR [R/W]
-------- -------- -0000000 00000000
+3
Block
DMAC
Reserved
MediaLB
(Continued)
62
DS07-16613-3E
MB91460M Series
Address
Register
+0
+1
+2
006034H
to
00603CH
Reserved
006040H
CECR0 [R/W]
0000000- 00000000 00000000 00000000
006044H
CSCR0 [R/W]
10------ ----0000 00000000 00000000
006048H
CCBCR0 [R]
00000000 00000000 00000000 00000000
00604CH
CNBCR0 [R/W]
00000000 00000000 00000000 00000000
006050H
CECR1 [R/W]
0000000- 00000000 00000000 00000000
006054H
CSCR1 [R/W]
10------ ----0000 00000000 00000000
006058H
CCBCR1 [R]
00000000 00000000 00000000 00000000
00605CH
CNBCR1 [R/W]
00000000 00000000 00000000 00000000
006060H
CECR2 [R/W]
0000000- 00000000 00000000 00000000
006064H
CSCR2 [R/W]
10------ ----0000 00000000 00000000
006068H
CCBCR2 [R]
00000000 00000000 00000000 00000000
00606CH
CNBCR2 [R/W]
00000000 00000000 00000000 00000000
006070H
CECR3 [R/W]
0000000- 00000000 00000000 00000000
006074H
CSCR3 [R/W]
10------ ----0000 00000000 00000000
006078H
CCBCR3 [R]
00000000 00000000 00000000 00000000
00607CH
CNBCR3 [R/W]
00000000 00000000 00000000 00000000
+3
Block
MediaLB
(Continued)
DS07-16613-3E
63
MB91460M Series
Address
Register
+0
+1
+2
006080H
CECR4 [R/W]
0000000- 00000000 00000000 00000000
006084H
CSCR4 [R/W]
10------ ----0000 00000000 00000000
006088H
CCBCR4 [R]
00000000 00000000 00000000 00000000
00608CH
CNBCR4 [R/W]
00000000 00000000 00000000 00000000
006090H
CECR5 [R/W]
0000000- 00000000 00000000 00000000
006094H
CSCR5 [R/W]
10------ ----0000 00000000 00000000
006098H
CCBCR5 [R]
00000000 00000000 00000000 00000000
00609CH
CNBCR5 [R/W]
00000000 00000000 00000000 00000000
0060A0H
CECR6 [R/W]
0000000- 00000000 00000000 00000000
0060A4H
CSCR6 [R/W]
10------ ----0000 00000000 00000000
0060A8H
CCBCR6 [R]
00000000 00000000 00000000 00000000
0060ACH
CNBCR6 [R/W]
00000000 00000000 00000000 00000000
0060B0H
CECR7 [R/W]
0000000- 00000000 00000000 00000000
0060B4H
CSCR7 [R/W]
10------ ----0000 00000000 00000000
0060B8H
CCBCR7 [R]
00000000 00000000 00000000 00000000
0060BCH
CNBCR7 [R/W]
00000000 00000000 00000000 00000000
+3
Block
MediaLB
(Continued)
64
DS07-16613-3E
MB91460M Series
Address
Register
+0
+1
+2
0060C0H
CECR8 [R/W]
0000000- 00000000 00000000 00000000
0060C4H
CSCR8 [R/W]
10------ ----0000 00000000 00000000
0060C8H
CCBCR8 [R]
00000000 00000000 00000000 00000000
0060CCH
CNBCR8 [R/W]
00000000 00000000 00000000 00000000
0060D0H
CECR9 [R/W]
0000000- 00000000 00000000 00000000
0060D4H
CSCR9 [R/W]
10------ ----0000 00000000 00000000
0060D8H
CCBCR9 [R]
00000000 00000000 00000000 00000000
0060DCH
CNBCR9 [R/W]
00000000 00000000 00000000 00000000
0060E0H
CECR10 [R/W]
0000000- 00000000 00000000 00000000
0060E4H
CSCR10 [R/W]
10------ ----0000 00000000 00000000
0060E8H
CCBCR10 [R]
00000000 00000000 00000000 00000000
0060ECH
CNBCR10 [R/W]
00000000 00000000 00000000 00000000
0060F0H
CECR11 [R/W]
0000000- 00000000 00000000 00000000
0060F4H
CSCR11 [R/W]
10------ ----0000 00000000 00000000
0060F8H
CCBCR11 [R]
00000000 00000000 00000000 00000000
0060FCH
CNBCR11 [R/W]
00000000 00000000 00000000 00000000
+3
Block
MediaLB
(Continued)
DS07-16613-3E
65
MB91460M Series
Address
Register
+0
+1
+2
006100H
CECR12 [R/W]
0000000- 00000000 00000000 00000000
006104H
CSCR12 [R/W]
10------ ----0000 00000000 00000000
006108H
CCBCR12 [R]
00000000 00000000 00000000 00000000
00610CH
CNBCR12 [R/W]
00000000 00000000 00000000 00000000
006110H
CECR13 [R/W]
0000000- 00000000 00000000 00000000
006114H
CSCR13 [R/W]
10------ ----0000 00000000 00000000
006118H
CCBCR13 [R]
00000000 00000000 00000000 00000000
00611CH
CNBCR13 [R/W]
00000000 00000000 00000000 00000000
006120H
CECR14 [R/W]
0000000- 00000000 00000000 00000000
006124H
CSCR14 [R/W]
10------ ----0000 00000000 00000000
006128H
CCBCR14 [R]
00000000 00000000 00000000 00000000
00612CH
CNBCR14 [R/W]
00000000 00000000 00000000 00000000
006130H
to
00627FH
Reserved
+3
Block
MediaLB
(Continued)
66
DS07-16613-3E
MB91460M Series
Address
Register
+0
+1
+2
006280H
LCBCR0 [R/W]
00000000 01000000 00000000 00000000
006284H
LCBCR1 [R/W]
00000000 01000000 00000000 00000001
006288H
LCBCR2 [R/W]
00000000 01000000 00000000 00000010
00628CH
LCBCR3 [R/W]
00000000 01000000 00000000 00000011
006290H
LCBCR4 [R/W]
00000000 01000000 00000000 00000100
006294H
LCBCR5 [R/W]
00000000 01000000 00000000 00000101
006298H
LCBCR6 [R/W]
00000000 01000000 00000000 00000110
00629CH
LCBCR7 [R/W]
00000000 01000000 00000000 00000111
0062A0H
LCBCR8 [R/W]
00000000 01000000 00000000 00001000
0062A4H
LCBCR9 [R/W]
00000000 01000000 00000000 00001001
0062A8H
LCBCR10 [R/W]
00000000 01000000 00000000 00001010
0062ACH
LCBCR11 [R/W]
00000000 01000000 00000000 00001011
0062B0H
LCBCR12 [R/W]
00000000 01000000 00000000 00001100
0062B4H
LCBCR13 [R/W]
00000000 01000000 00000000 00001101
0062B8H
LCBCR14 [R/W]
00000000 01000000 00000000 00001110
0062BCH
to
00630FH
Reserved
+3
Block
MediaLB
Reserved
(Continued)
DS07-16613-3E
67
MB91460M Series
Address
006310H
Register
+0
+1
I2SCCR [R/W]
00100000 0----000
006314H
006318H
00631CH
006320H
006324H
006328H
00632CH
006330H
006334H
006338H
00633CH
006340H
006344H
006348H
00634CH
006350H
006354H
006358H
00635CH
006360H
006364H
I2SSCR0 [R/W]
----0000 0--00000
LTDT0 [R/W]
00000000 00000000
I2SSCR1 [R/W]
----0000 0--00000
LTDT1 [R/W]
00000000 00000000
I2SSCR2 [R/W]
----0000 0--00000
LTDT2 [R/W]
00000000 00000000
I2SSCR3 [R/W]
----0000 0--00000
LTDT3 [R/W]
00000000 00000000
I2SSCR4 [R/W]
----0000 0--00000
LTDT4 [R/W]
00000000 00000000
I2SSCR5 [R/W]
----0000 0--00000
LTDT5 [R/W]
00000000 00000000
I2SSCR6 [R/W]
----0000 0--00000
LTDT6 [R/W]
00000000 00000000
I2SSCR7 [R/W]
----0000 0--00000
LTDT7 [R/W]
00000000 00000000
I2SSCR8 [R/W]
----0000 0--00000
LTDT8 [R/W]
00000000 00000000
I2SSCR9 [R/W]
----0000 0--00000
LTDT9 [R/W]
00000000 00000000
+2
+3
I2SRSR [R/W]
-------- 00000000
Reserved
I2SBT0 [R]
I2SBCR0 [R/W]
----0000
---00000
RTDT0 [R/W]
00000000 00000000
I2SBT1 [R]
I2SBCR1 [R/W]
----0000
---00000
RTDT1 [R/W]
00000000 00000000
I2SBT2 [R]
I2SBCR2 [R/W]
----0000
---00000
RTDT2 [R/W]
00000000 00000000
I2SBT3 [R]
I2SBCR3 [R/W]
----0000
---00000
RTDT3 [R/W]
00000000 00000000
I2SBT4 [R]
I2SBCR4 [R/W]
----0000
---00000
RTDT4 [R/W]
00000000 00000000
I2SBT5 [R]
I2SBCR5 [R/W]
----0000
---00000
RTDT5 [R/W]
00000000 00000000
I2SBT6 [R]
I2SBCR6 [R/W]
----0000
---00000
RTDT6 [R/W]
00000000 00000000
I2SBT7 [R]
I2SBCR7 [R/W]
----0000
---00000
RTDT7 [R/W]
00000000 00000000
I2SBT8 [R]
I2SBCR8 [R/W]
----0000
---00000
RTDT8 [R/W]
00000000 00000000
I2SBT9 [R]
I2SBCR9 [R/W]
----0000
---00000
RTDT9 [R/W]
00000000 00000000
Block
I2S
0 to 9
I2S 0
I2S 1
I2S 2
I2S 3
I2S 4
I2S 5
I2S 6
I2S 7
I2S 8
I2S 9
(Continued)
68
DS07-16613-3E
MB91460M Series
Address
Register
+0
+1
+2
006368H
to
00640CH
Reserved
006410H
BUFAR0 [R/W]
00000000 00000000 00000000 00000000
006414H
BUFAR1 [R/W]
00000000 00000000 00000000 00000000
006418H
BUFAR2 [R/W]
00000000 00000000 00000000 00000000
00641CH
BUFAR3 [R/W]
00000000 00000000 00000000 00000000
006420H
BUFAR4 [R/W]
00000000 00000000 00000000 00000000
006424H
BUFAR5 [R/W]
00000000 00000000 00000000 00000000
006428H
BUFAR6 [R/W]
00000000 00000000 00000000 00000000
00642CH
BUFAR7 [R/W]
00000000 00000000 00000000 00000000
006430H
MSTD [R/W]
-0000000 00000000
+3
Block
Reserved
MBSYNC [R]
XXXXXXXX XXXXXXXX
006434H
BUFAR8 [R/W]
00000000 00000000 00000000 00000000
006438H
BUFAR9 [R/W]
00000000 00000000 00000000 00000000
00643CH
BUFAR10 [R/W]
00000000 00000000 00000000 00000000
006440H
BUFAR11 [R/W]
00000000 00000000 00000000 00000000
006444H
BUFAR12 [R/W]
00000000 00000000 00000000 00000000
006448H
BUFAR13 [R/W]
00000000 00000000 00000000 00000000
00644CH
BUFAR14 [R/W]
00000000 00000000 00000000 00000000
006450H
to
00649CH
Reserved
MediaLB
Reserved
(Continued)
DS07-16613-3E
69
MB91460M Series
Address
Register
+0
+1
+2
0064A0H
ASLR [R/W]
00000000 00000000 00000000 00000000
0064A4H
BUFDCR [R/W]
00000000 00000000 00000000 00000000
0064A8H
BUFIER [R/W]
00000000 00000000 -0000000 00000000
0064ACH
BUFSR [R/W]
00000000 00000000 -0000000 00000000
0064B0H
BUFER [R/W]
00000000 00000000 -0000000 00000000
0064B4H
BUFRST [R/W]
00000000 00000000 -0000000 00000000
0064B8H,
0064BCH
Reserved
0064C0H
BUFCT0 [R/W]
----0000 00000000 ----0000 00000000
0064C4H
BUFCT1 [R/W]
----0000 00000000 ----0000 00000000
0064C8H
BUFCT2 [R/W]
----0000 00000000 ----0000 00000000
0064CCH
BUFCT3 [R/W]
----0000 00000000 ----0000 00000000
0064D0H
BUFCT4 [R/W]
----0000 00000000 ----0000 00000000
0064D4H
BUFCT5 [R/W]
----0000 00000000 ----0000 00000000
0064D8H
BUFCT6 [R/W]
----0000 00000000 ----0000 00000000
0064DCH
BUFCT7 [R/W]
----0000 00000000 ----0000 00000000
0064E0H
to
0064FCH
Reserved
+3
Block
FIFO buffer
Reserved
(Continued)
70
DS07-16613-3E
MB91460M Series
Address
Register
+0
+1
+2
006500H
BUF0CR [R/W]
00000000 00000000 000----0 00000000
006504H
BUF1CR [R/W]
00000000 00000000 000----0 00000000
006508H
BUF2CR [R/W]
00000000 00000000 000----0 00000000
00650CH
BUF3CR [R/W]
00000000 00000000 000----0 00000000
006510H
BUF4CR [R/W]
00000000 00000000 000----0 00000000
006514H
BUF5CR [R/W]
00000000 00000000 000----0 00000000
006518H
BUF6CR [R/W]
00000000 00000000 000----0 00000000
00651CH
BUF7CR [R/W]
00000000 00000000 000----0 00000000
006520H
BUF8CR [R/W]
00000000 00000000 000----0 00000000
006524H
BUF9CR [R/W]
00000000 00000000 000----0 00000000
006528H
BUF10CR [R/W]
00000000 00000000 000----0 00000000
00652CH
BUF11CR [R/W]
00000000 00000000 000----0 00000000
006530H
BUF12CR [R/W]
00000000 00000000 000----0 00000000
006534H
BUF13CR [R/W]
00000000 00000000 000----0 00000000
006538H
BUF14CR [R/W]
00000000 00000000 000----0 00000000
00653CH
to
00657CH
Reserved
+3
Block
FIFO buffer
Reserved
(Continued)
DS07-16613-3E
71
MB91460M Series
Address
Register
+0
+1
+2
+3
006580H
BUF0DTR [R/W]
00000000 00000000 00000000 00000000
006584H
BUF1DTR [R/W]
00000000 00000000 00000000 00000000
006588H
BUF2DTR [R/W]
00000000 00000000 00000000 00000000
00658CH
BUF3DTR [R/W]
00000000 00000000 00000000 00000000
006590H
BUF4DTR [R/W]
00000000 00000000 00000000 00000000
006594H
BUF5DTR [R/W]
00000000 00000000 00000000 00000000
006598H
BUF6DTR [R/W]
00000000 00000000 00000000 00000000
00659CH
BUF7DTR [R/W]
00000000 00000000 00000000 00000000
0065A0H
BUF8DTR [R/W]
00000000 00000000 00000000 00000000
0065A4H
BUF9DTR [R/W]
00000000 00000000 00000000 00000000
0065A8H
BUF10DTR [R/W]
00000000 00000000 00000000 00000000
0065ACH
BUF11DTR [R/W]
00000000 00000000 00000000 00000000
0065B0H
BUF12DTR [R/W]
00000000 00000000 00000000 00000000
0065B4H
BUF13DTR [R/W]
00000000 00000000 00000000 00000000
0065B8H
BUF14DTR [R/W]
00000000 00000000 00000000 00000000
0065BCH
Reserved
006600H
MLBINTR [R]
-0000-00 00000000 ------00 00000000
006604H
BUFINTCH [R]
0---0000
FIFO buffer
Reserved
Reserved
006608H
BUFPRI0001 [R/W] BUFPRI0203 [R/W] BUFPRI0405 [R/W] BUFPRI0607 [ R/W]
11101101
11001011
10101001
10000111
00660CH
BUFPRI0809 [R/W] BUFPRI1011 [R/W] BUFPRI1213 [R/W]
01100101
01000011
00100001
006610H
to
0067FCH
Reserved
Block
MediaLB
I2S
FIFO buffer
Interrupt
BUFPRI14 [R/W]
0000---Reserved
(Continued)
72
DS07-16613-3E
MB91460M Series
Address
007000H
007004H
007008H
00700CH
007010H
Register
Block
+0
+1
+2
+3
FMCS [R/W]
FMCR [R/W]
FCHCR [R/W]
01101000
---00000
------00 10000011
FMWT [R/W]
FMWT2 [R/W]
FMPS [R/W]
11111111 01011101
-101--------000
FMAC [R]
00000000 00000000 00000000 00000000
FCHA0 [R/W]
-------- -0000000 00000000 00000000
FCHA1 [R/W]
-------- -0000000 00000000 00000000
I-Cache
Non-cacheable
area setting
Register
Reserved
Reserved
Boot ROM area
Boot ROM
4Kbytes
007014H
to
00AFFCH
00B000H
to
00BFFCH
00C000H
00C004H
00C008H
00C00CH
00C010H
00C014H
00C018H
00C01CH
00C020H
00C024H
CTRLR0 [R/W]
00000000 00000001
ERRCNT0 [R]
00000000 00000000
INTR0 [R]
00000000 00000000
BRPE0 [R/W]
00000000 00000000
IF1CREQ0 [R/W]
00000000 00000001
IF1MSK20 [R/W]
11111111 11111111
IF1ARB20 [R/W]
00000000 00000000
IF1MCTR0 [R/W]
00000000 00000000
IF1DTA10 [R/W]
00000000 00000000
IF1DTB10 [R/W]
00000000 00000000
00C028H,
00C02CH
00C030H
00C034H
00C038H,
00C03CH
STATR0 [R/W]
00000000 00000000
BTR0 [R/W]
00100011 00000001
TESTR0 [R/W]
00000000 X0000000
CBSYNC0 [R]
XXXXXXXX XXXXXXXX
IF1CMSK0 [R/W]
00000000 00000000
IF1MSK10 [R/W]
11111111 11111111
IF1ARB10 [R/W]
00000000 00000000
Flash Memory/
Cache Control
Register
CAN0
Control Register
Reserved
IF1DTA20 [R/W]
00000000 00000000
IF1DTB20 [R/W]
00000000 00000000
CAN0
IF 1 Register
Reserved
IF1DTA20 [R/W]
00000000 00000000
IF1DTB20 [R/W]
00000000 00000000
IF1DTA10 [R/W]
00000000 00000000
IF1DTB10 [R/W]
00000000 00000000
Reserved
(Continued)
DS07-16613-3E
73
MB91460M Series
Address
Register
+0
+1
+2
+3
00C040H
IF2CREQ0 [R/W]
00000000 00000001
IF2CMSK0 [R/W]
00000000 00000000
00C044H
IF2MSK20 [R/W]
11111111 11111111
IF2MSK10 [R/W]
11111111 11111111
00C048H
IF2ARB20 [R/W]
00000000 00000000
IF2ARB10 [R/W]
00000000 00000000
00C04CH
IF2MCTR0 [R/W]
00000000 00000000
Reserved
00C050H
IF2DTA10 [R/W]
00000000 00000000
IF2DTA20 [R/W]
00000000 00000000
00C054H
IF2DTB10 [R/W]
00000000 00000000
IF2DTB20 [R/W]
00000000 00000000
00C058H,
00C05CH
IF2DTA20 [R/W]
00000000 00000000
IF2DTA10 [R/W]
00000000 00000000
00C064H
IF2DTB20 [R/W]
00000000 00000000
IF2DTB10 [R/W]
00000000 00000000
00C068H
to
00C07CH
Reserved
TREQR20 [R]
00000000 00000000
00C084H
to
00C08CH
00C090H
NEWDT20 [R]
00000000 00000000
00C0B4H
to
00C0FCH
NEWDT10 [R]
00000000 00000000
CAN0
Status Flags
Reserved
INTPND20 [R]
00000000 00000000
00C0A4H
to
00C0ACH
00C0B0H
TREQR10 [R]
00000000 00000000
Reserved
00C094H
to
00C09CH
00C0A0H
CAN0
IF 2 Register
Reserved
00C060H
00C080H
Block
INTPND10 [R]
00000000 00000000
Reserved
MSGVAL20 [R]
00000000 00000000
MSGVAL10 [R]
00000000 00000000
Reserved
Reserved
(Continued)
74
DS07-16613-3E
MB91460M Series
Address
Register
+0
+1
+2
+3
00C100H
CTRLR1 [R/W]
00000000 00000001
STATR1 [R/W]
00000000 00000000
00C104H
ERRCNT1 [R]
00000000 00000000
BTR1 [R/W]
00100011 00000001
00C108H
INTR1 [R]
00000000 00000000
TESTR1 [R/W]
00000000 X0000000
00C10CH
BRPE1 [R/W]
00000000 00000000
CBSYNC1 [R]
XXXXXXXX XXXXXXXX
00C110H
IF1CREQ1 [R/W]
00000000 00000001
IF1CMSK1 [R/W]
00000000 00000000
00C114H
IF1MSK21 [R/W]
11111111 11111111
IF1MSK11 [R/W]
11111111 11111111
00C118H
IF1ARB21 [R/W]
00000000 00000000
IF1ARB11 [R/W]
00000000 00000000
00C11CH
IF1MCTR1 [R/W]
00000000 00000000
Reserved
00C120H
IF1DTA11 [R/W]
00000000 00000000
IF1DTA21 [R/W]
00000000 00000000
00C124H
IF1DTB11 [R/W]
00000000 00000000
IF1DTB21 [R/W]
00000000 00000000
00C128H,
00C12CH
CAN1
Control Register
CAN1
IF 1 Register
Reserved
00C130H
IF1DTA21 [R/W]
00000000 00000000
IF1DTA11 [R/W]
00000000 00000000
00C134H
IF1DTB21 [R/W]
00000000 00000000
IF1DTB11 [R/W]
00000000 00000000
00C138H,
00C13CH
Block
Reserved
(Continued)
DS07-16613-3E
75
MB91460M Series
Address
Register
+0
+1
+2
+3
00C140H
IF2CREQ1 [R/W]
00000000 00000001
IF2CMSK1 [R/W]
00000000 00000000
00C144H
IF2MSK21 [R/W]
11111111 11111111
IF2MSK11 [R/W]
11111111 11111111
00C148H
IF2ARB21 [R/W]
00000000 00000000
IF2ARB11 [R/W]
00000000 00000000
00C14CH
IF2MCTR1 [R/W]
00000000 00000000
Reserved
00C150H
IF2DTA11 [R/W]
00000000 00000000
IF2DTA21 [R/W]
00000000 00000000
00C154H
IF2DTB11 [R/W]
00000000 00000000
IF2DTB21 [R/W]
00000000 00000000
00C158H,
00C15CH
Block
CAN1
IF 2 Register
Reserved
00C160H
IF2DTA21 [R/W]
00000000 00000000
IF2DTA11 [R/W]
00000000 00000000
00C164H
IF2DTB21 [R/W]
00000000 00000000
IF2DTB11 [R/W]
00000000 00000000
00C168H
to
00C17CH
Reserved
00C180H
TREQR21 [R]
00000000 00000000
TREQR11 [R]
00000000 00000000
00C184H
TREQR41 [R]
00000000 00000000
TREQR31 [R]
00000000 00000000
00C188H,
00C18CH
Reserved
00C190H
NEWDT21 [R]
00000000 00000000
NEWDT11 [R]
00000000 00000000
00C194H
NEWDT41 [R]
00000000 00000000
NEWDT31 [R]
00000000 00000000
00C198H,
00C19CH
CAN1
Status Flags
Reserved
00C1A0H
INTPND21 [R]
00000000 00000000
INTPND11 [R]
00000000 00000000
00C1A4H
INTPND41 [R]
00000000 00000000
INTPND31 [R]
00000000 00000000
00C1A8H,
00C1ACH
Reserved
00C1B0H
MSGVAL21 [R]
00000000 00000000
MSGVAL11 [R]
00000000 00000000
00C1B4H
MSGVAL41 [R]
00000000 00000000
MSGVAL31 [R]
00000000 00000000
(Continued)
76
DS07-16613-3E
MB91460M Series
Address
Register
+0
+1
+2
+3
Block
00C1B8H
to
00C1FCH
Reserved
CAN1
Status Flags
00C200H
to
00EFFCH
Reserved
Reserved
00F000H
BCTRL [R/W]
-------- -------- 11111100 00000000
00F004H
BSTAT [R/W]
-------- -----000 00000000 10--0000
00F008H
BIAC [R]
-------- -------- 00000000 00000000
00F00CH
BOAC [R]
-------- -------- 00000000 00000000
00F010H
BIRQ [R/W]
-------- -------- 00000000 00000000
00F014H
to
00F01CH
Reserved
00F020H
BCR0 [R/W]
-------- 00000000 00000000 00000000
00F024H
BCR1 [R/W]
-------- 00000000 00000000 00000000
00F028H
BCR2 [R/W]
-------- 00000000 00000000 00000000
00F02CH
BCR3 [R/W]
-------- 00000000 00000000 00000000
00F030H
to
00F07CH
Reserved
EDSU / MPU
(Continued)
DS07-16613-3E
77
MB91460M Series
Address
Register
+0
+1
+2
00F080H
BAD0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F084H
BAD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F088H
BAD2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F08CH
BAD3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F090H
BAD4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F094H
BAD5 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F098H
BAD6 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F09CH
BAD7 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A0H
BAD8 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A4H
BAD9 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A8H
BAD10 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0ACH
BAD11 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B0H
BAD12 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B4H
BAD13 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B8H
BAD14 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0BCH
BAD15 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0C0H
to
00FFFCH
Reserved
+3
Block
EDSU / MPU
Reserved
(Continued)
78
DS07-16613-3E
MB91460M Series
Address
Register
+0
+1
+2
+3
00010000H
to
000107FCH
TAG RAM (way1)
00010800H
to
00013FFCH
Reserved
00014000H
to
000147FCH
TAG RAM (way2)
00014800H
to
00017FFCH
Reserved
00018000H
to
000187FCH
CACHE RAM (way1) / I-RAM (2 Kbytes)
00018800H
to
0001BFFCH
Reserved
0001C000H
to
0001C7FCH
CACHE RAM (way2) / I-RAM (2 Kbytes)
0001C800H
to
0001FFFCH
Reserved
020000H
to
027FFCH
Reserved
024000H
to
02BFFCH
D-RAM area (32 Kbytes)
(It is not possible to use instruction access, data access is 1 wait cycle)
02C000H
to
02FFFCH
D-RAM area (16 Kbytes)
(It is not possible to use instruction access, data access is 0 wait cycle)
030000H
to
033FFCH
I/D-RAM area (16 Kbytes)
(instruction access is 0 wait cycles, data access is 1 wait cycle)
034000H
to
03FFFCH
Reserved
Block
Reserved
Reserved
Reserved
Reserved
RAM
(64 Kbytes)
(Continued)
DS07-16613-3E
79
MB91460M Series
(Continued)
Address
Register
+0
+1
+2
040000H
to
05FFFCH
ROMS00 area (128 Kbytes)
060000H
to
07FFFCH
ROMS01 area (128 Kbytes)
080000H
to
09FFFCH
ROMS02 area (128 Kbytes)
0A0000H
to
0BFFFCH
ROMS03 area (128 Kbytes)
0C0000H
to
0DFFFCH
ROMS04 area (128 Kbytes)
0E0000H
to
0FFFFCH
ROMS05 area (128 Kbytes)
Mode Vector:0FFFF8H Reset Vector:0FFFFCH
100000H
to
13FFFCH
ROMS06 area (256 Kbytes)
140000H
to
14FFFCH
ROMS07 area (64 Kbytes)
150000H
to
17FFFCH
Reserved
+3
Block
Flash
(1088 Kbytes)
Note: It is not allowed to write into 0FFFF8H and 0FFFFCH. When these addresses are read, values shown above
will be read.
80
DS07-16613-3E
MB91460M Series
■ INTERRUPT VECTOR TABLE
Interrupt number
Interrupt
Decimal
Interrupt level*1
Interrupt vector*2
HexaSetting Register
decimal Register address
Offset
Default Vector
address
RN
Reset
0
0H
⎯
⎯
3FCH
000FFFFCH
Mode vector
1
1H
⎯
⎯
3F8H
000FFFF8H
System reserved
2
2H
⎯
⎯
3F4H
000FFFF4H
System reserved
3
3H
⎯
⎯
3F0H
000FFFF0H
System reserved
4
4H
⎯
⎯
3ECH
000FFFECH
CPU supervisor mode
(INT #5 instruction)*6
5
5H
⎯
⎯
3E8H
000FFFE8H
Memory Protection exception
6
6H
⎯
⎯
3E4H
000FFFE4H
Co-processor fault trap*5
7
7H
⎯
⎯
3E0H
000FFFE0H
Co-processor error trap*5
8
8H
⎯
⎯
3DCH
000FFFDCH
9
9H
⎯
⎯
3D8HH
000FFFD8H
10
0AH
⎯
⎯
3D4H
000FFFD4H
11
0BH
⎯
⎯
3D0H
000FFFD0H
12
0CH
⎯
⎯
3CCH
000FFFCCH
13
0DH
⎯
⎯
3C8H
000FFFC8H
Undefined instruction
exception
14
0EH
⎯
⎯
3C4H
000FFFC4H
NMI request
15
0FH
3C0H
000FFFC0H
External Interrupt 0
16
10H
3BCH
000FFFBCH
0, 16
External Interrupt 1
17
11H
3B8H
000FFFB8H
1, 17
External Interrupt 2
18
12H
3B4H
000FFFB4H
2, 18
External Interrupt 3
19
13H
3B0H
000FFFB0H
3, 19
External Interrupt 4
20
14H
3ACH
000FFFACH
20
External Interrupt 5
21
15H
3A8H
000FFFA8H
21
External Interrupt 6
22
16H
3A4H
000FFFA4H
22
External Interrupt 7
23
17H
3A0H
000FFFA0H
23
External Interrupt 8
24
18H
39CH
000FFF9CH
External Interrupt 9
25
19H
398H
000FFF98H
External Interrupt 10
26
1AH
394H
000FFF94H
External Interrupt 11
27
1BH
390H
000FFF90H
External Interrupt 12
28
1CH
38CH
000FFF8CH
External Interrupt 13
29
1DH
388H
000FFF88H
External Interrupt 14
30
1EH
384H
000FFF84H
External Interrupt 15
31
1FH
380H
000FFF80H
INTE instruction*5
Instruction break exception*
Operand break trap*
Step trace trap*
5
5
NMI request (tool) *
5
5
FH fixed
ICR00
440H
ICR01
441H
ICR02
442H
ICR03
443H
ICR04
444H
ICR05
445H
ICR06
446H
ICR07
447H
(Continued)
DS07-16613-3E
81
MB91460M Series
Interrupt number
Interrupt
Decimal
Interrupt level*1
HexaSetting Register
decimal Register address
Reload Timer 0
32
20H
Reload Timer 1
33
21H
Reload Timer 2
34
22H
Reload Timer 3
35
23H
Reserved
36
24H
Reserved
37
25H
Reserved
38
26H
Reload Timer 7
39
27H
Free Run Timer 0
40
28H
Free Run Timer 1
41
29H
Free Run Timer 2
42
2AH
Free Run Timer 3
43
2BH
Reserved
44
2CH
Reserved
45
2DH
Reserved
46
2EH
Reserved
47
2FH
CAN 0
48
30H
CAN 1
49
31H
Reserved
50
32H
Reserved
51
33H
Reserved
52
34H
Reserved
53
35H
LIN-USART0 RX
54
36H
LIN-USART0 TX
55
37H
LIN-USART1 RX
56
38H
LIN-USART1 TX
57
39H
LIN-USART2 RX
58
3AH
LIN-USART2 TX
59
3BH
LIN-USART3 RX
60
3CH
LIN-USART3 TX
61
3DH
System reserved
62
3EH
Delayed Interrupt
63
3FH
ICR08
448H
ICR09
449H
ICR10
44AH
ICR11
44BH
ICR12
44CH
ICR13
44DH
ICR14
44EH
ICR15
44FH
ICR16
450H
ICR17
451H
ICR18
452H
ICR19
453H
ICR20
454H
ICR21
455H
ICR22
456H
ICR23*4
457H
Interrupt vector*2
Offset
Default Vector
address
RN
37CH
000FFF7CH
4, 32
378H
000FFF78H
5, 33
374H
000FFF74H
34
370H
000FFF70H
35
36CH
000FFF6CH
368H
000FFF68H
364H
000FFF64H
360H
000FFF60H
35CH
000FFF5CH
40
358H
000FFF58H
41
354H
000FFF54H
42
350H
000FFF50H
43
34CH
000FFF4CH
348H
000FFF48H
344H
000FFF44H
340H
000FFF40H
33CH
000FFF3CH
338H
000FFF38H
334H
000FFF34H
330H
000FFF30H
32CH
000FFF2CH
328H
000FFF28H
324H
000FFF24H
6, 48
320H
000FFF20H
7, 49
31CH
000FFF1CH
8, 50
318H
000FFF18H
9, 51
314H
000FFF14H
52
310H
000FFF10H
53
30CH
000FFF0CH
54
308H
000FFF08H
55
304H
000FFF04H
300H
000FFF00H
(Continued)
82
DS07-16613-3E
MB91460M Series
Interrupt number
Interrupt
Decimal
HexaSetting Register
decimal Register address
System reserved *3
64
40H
System reserved *3
65
41H
LIN-USART (FIFO) 4 RX
66
42H
LIN-USART (FIFO) 4 TX
67
43H
LIN-USART (FIFO) 5 RX
68
44H
LIN-USART (FIFO) 5 TX
69
45H
LIN-USART (FIFO) 6 RX
70
46H
LIN-USART (FIFO) 6 TX
71
47H
LIN-USART (FIFO) 7 RX
72
48H
LIN-USART (FIFO) 7 TX
73
49H
I2C 0 / I2C 2
74
4AH
IC1/IC3
75
4BH
LIN-USART (LIN) 8 RX
76
4CH
LIN-USART (LIN) 8 TX
77
4DH
I2C 4 / I2C 6
78
4EH
IC5/IC7
79
4FH
Reserved
80
50H
Reserved
81
51H
FIFO buffer
82
52H
Reserved
83
53H
Reserved
84
54H
Reserved
85
55H
Reserved
86
56H
Reserved
87
57H
MediaLB
88
58H
I2S ERROR
89
59H
I2S EVEN
90
5AH
I S ODD
91
5BH
Input Capture 0
92
5CH
Input Capture 1
93
5DH
Input Capture 2
94
5EH
Input Capture 3
95
5FH
2
2
2
2
2
Interrupt level*1
(ICR24)
(458H)
ICR25
459H
ICR26
45AH
ICR27
45BH
ICR28
45CH
ICR29
45DH
ICR30
45EH
ICR31
45FH
ICR32
460H
ICR33
461H
ICR34
462H
ICR35
463H
ICR36
464H
ICR37
465H
ICR38
466H
ICR39
467H
Interrupt vector*2
RN
Offset
Default Vector
address
2FCH
000FFEFCH
2F8H
000FFEF8H
2F4H
000FFEF4H
10, 56
2F0H
000FFEF0H
11, 57
2ECH
000FFEECH
12, 58
2E8H
000FFEE8H
13, 59
2E4H
000FFEE4H
60
2E0H
000FFEE0H
61
2DCH
000FFEDCH
62
2D8H
000FFED8H
63
2D4H
000FFED4H
2D0H
000FFED0H
2CCH
000FFECCH
64
2C8H
000FFEC8H
65
2C4H
000FFEC4H
2C0H
000FFEC0H
2BCH
000FFEBCH
2B8H
000FFEB8H
2B4H
000FFEB4H
2B0H
000FFEB0H
2ACH
000FFEACH
2A8H
000FFEA8H
2A4H
000FFEA4H
2A0H
000FFEA0H
29CH
000FFE9CH
298H
000FFE98H
294H
000FFE94H
125
290H
000FFE90H
126
28CH
000FFE8CH
80
288H
000FFE88H
81
284H
000FFE84H
82
280H
000FFE80H
83
(Continued)
DS07-16613-3E
83
MB91460M Series
Interrupt number
Interrupt
Decimal
Interrupt level*1
HexaSetting Register
decimal Register address
Reserved
96
60H
Reserved
97
61H
Reserved
98
62H
Reserved
99
63H
Output Compare 0
100
64H
Output Compare 1
101
65H
Output Compare 2
102
66H
Output Compare 3
103
67H
Reserved
104
68H
Reserved
105
69H
Reserved
106
6AH
Reserved
107
6BH
Reserved
108
6CH
Reserved
109
6DH
Reserved
110
6EH
Reserved
111
6FH
PPG0
112
70H
PPG1
113
71H
PPG2
114
72H
PPG3
115
73H
PPG4
116
74H
PPG5
117
75H
PPG6
118
76H
PPG7
119
77H
Reserved
120
78H
Reserved
121
79H
Reserved
122
7AH
Reserved
123
7BH
Reserved
124
7CH
Reserved
125
7DH
Reserved
126
7EH
Reserved
127
7FH
Reserved
128
80H
Reserved
129
81H
ICR40
468H
ICR41
469H
ICR42
46AH
ICR43
46BH
ICR44
46CH
ICR45
46DH
ICR46
46EH
ICR47*4
46FH
ICR48
470H
ICR49
471H
ICR50
472H
ICR51
473H
ICR52
474H
ICR53
475H
ICR54
476H
ICR55
477H
ICR56
478H
Interrupt vector*2
RN
Offset
Default Vector
address
27CH
000FFE7CH
278H
000FFE78H
274H
000FFE74H
270H
000FFE70H
26CH
000FFE6CH
88
268H
000FFE68H
89
264H
000FFE64H
90
260H
000FFE60H
91
25CH
000FFE5CH
258H
000FFE58H
254H
000FFE54H
250H
000FFE50H
24CH
000FFE4CH
248H
000FFE48H
244H
000FFE44H
240H
000FFE40H
23CH
000FFE3CH
15, 96
238H
000FFE38H
97
234H
000FFE34H
98
230H
000FFE30H
99
22CH
000FFE2CH
100
228H
000FFE28H
101
224H
000FFE24H
102
220H
000FFE20H
103
21CH
000FFE1CH
218H
000FFE18H
214H
000FFE14H
210H
000FFE10H
20CH
000FFE0CH
208H
000FFE08H
204H
000FFE04H
200H
000FFE00H
1FCH
000FFDFCH
1F8H
000FFDF8H
(Continued)
84
DS07-16613-3E
MB91460M Series
(Continued)
Interrupt number
Interrupt
Decimal
Interrupt level*1
HexaSetting Register
decimal Register address
Reserved
130
82H
Reserved
131
83H
Real Time Clock
132
84H
Calibration Unit
133
85H
A/D Converter 0
134
86H
Reserved
135
87H
Reserved
136
88H
Reserved
137
89H
Low Voltage Detection
138
8AH
Reserved
139
8BH
Timebase Overflow
140
8CH
PLL Clock Gear
141
8DH
DMA Controller
142
8EH
Main/Sub OSC stability wait
143
8FH
Reserved
144
Used by the INT instruction.
145
to
255
Interrupt vector*2
Offset
Default Vector
address
1F4H
000FFDF4H
1F0H
000FFDF0H
1ECH
000FFDECH
1E8H
000FFDE8H
1E4H
000FFDE4H
1E0H
000FFDE0H
1DCH
000FFDDCH
1D8H
000FFDD8H
1D4H
000FFDD4H
1D0H
000FFDD0H
1CCH
000FFDCCH
1C8H
000FFDC8H
1C4H
000FFDC4H
1C0H
000FFDC0H
ICR57
479H
ICR58
47AH
ICR59
47BH
ICR60
47CH
ICR61
47DH
ICR62
47EH
ICR63
47FH
90H
⎯
⎯
1BCH
000FFDBCH
91H
to
FFH
⎯
⎯
1B8H
to
000H
000FFDB8H
to
000FFC00H
RN
14, 112
*1 : The ICRs set the interrupt level for each interrupt request.
*2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the
table base register value (TBR). The TBR specifies the top of the EIT vector table. The addresses listed in
the table are for the default TBR value (0x000FFC00). The TBR is initialized to this value by a reset.
*3 : Used by REALOS.
*4 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0xC03 : IOS[0])
*5 : System reserved.
*6 : Memory Protection Unit (MPU) support.
DS07-16613-3E
85
MB91460M Series
■ RECOMMENDED SETTINGS
1. PLL and Clockgear settings
Recommended PLL divider and clockgear settings
PLL
Input (CLK)
[MHz]
86
Frequency Parameter
Clockgear Parameter
PLL
Core Base
Output (X)
Clock
[MHz]
[MHz]
DIVM
DIVN
DIVG
MULG
4
2
20
16
20
160
80
4
2
19
16
20
152
76
4
2
18
16
20
144
72
4
2
17
16
16
136
68
4
2
16
16
16
128
64
4
2
15
16
16
120
60
4
2
14
16
16
112
56
4
2
13
16
12
104
52
4
2
12
16
12
96
48
4
2
11
16
12
88
44
4
4
10
16
24
160
40
4
4
9
16
24
144
36
4
4
8
16
24
128
32
4
4
7
16
24
112
28
4
6
6
16
24
144
24
4
8
5
16
28
160
20
4
10
4
16
32
160
16
4
12
3
16
32
144
12
Remarks
MULG
DS07-16613-3E
MB91460M Series
2. Clock Modulator settings
The following table shows all possible settings for the Clock Modulator in a center clock frequency range from
32MHz up to 80 MHz.
The Flash access time settings need to be adjusted according to Fmax while the PLL and clockgear settings
should be set according to center clock frequency.
Clock Modulator settings, frequency range and supported supply voltage
Modulation
Random No
CMPR
center clk
Fmin
Degree
(N)
[hex]
[MHz]
[MHz]
(k)
Fmax
[MHz]
1
3
026FH
72
65.5
79.9
1
3
026FH
68
62
75.3
1
3
026FH
64
58.5
70.7
1
5
02AEH
64
55.3
75.9
2
3
046EH
64
55.3
75.9
1
3
026FH
60
54.9
66.1
1
5
02AEH
60
51.9
71
1
7
02EDH
60
49.3
76.7
2
3
046EH
60
51.9
71
3
3
066DH
60
49.3
76.7
1
3
026FH
56
51.4
61.6
1
5
02AEH
56
48.6
66.1
1
7
02EDH
56
46.1
71.4
1
9
032CH
56
43.8
77.6
2
3
046EH
56
48.6
66.1
2
5
04ACH
56
43.8
77.6
3
3
066DH
56
46.1
71.4
4
3
086CH
56
43.8
77.6
1
3
026FH
52
47.8
57
1
5
02AEH
52
45.2
61.2
1
7
02EDH
52
42.9
66.1
1
9
032CH
52
40.8
71.8
1
11
036BH
52
38.8
78.6
2
3
046EH
52
45.2
61.2
2
5
04ACH
52
40.8
71.8
3
3
066DH
52
42.9
66.1
4
3
086CH
52
40.8
71.8
5
3
0A6BH
52
38.8
78.6
1
3
026FH
48
44.2
52.5
1
5
02AEH
48
41.8
56.4
Remarks
(Continued)
DS07-16613-3E
87
MB91460M Series
Modulation
Degree
(k)
Random No
(N)
CMPR
[hex]
center clk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
1
7
02EDH
48
39.6
60.9
1
9
032CH
48
37.7
66.1
1
11
036BH
48
35.9
72.3
1
13
03AAH
48
34.3
79.9
2
3
046EH
48
41.8
56.4
2
5
04ACH
48
37.7
66.1
2
7
04EAH
48
34.3
79.9
3
3
066DH
48
39.6
60.9
3
5
06AAH
48
34.3
79.9
4
3
086CH
48
37.7
66.1
5
3
0A6BH
48
35.9
72.3
6
3
0C6AH
48
34.3
79.9
1
3
026FH
44
40.6
48.1
1
5
02AEH
44
38.4
51.6
1
7
02EDH
44
36.4
55.7
1
9
032CH
44
34.6
60.4
1
11
036BH
44
33
66.1
1
13
03AAH
44
31.5
73
2
3
046EH
44
38.4
51.6
2
5
04ACH
44
34.6
60.4
2
7
04EAH
44
31.5
73
3
3
066DH
44
36.4
55.7
3
5
06AAH
44
31.5
73
4
3
086CH
44
34.6
60.4
5
3
0A6BH
44
33
66.1
6
3
0C6AH
44
31.5
73
1
3
026FH
40
37
43.6
1
5
02AEH
40
34.9
46.8
1
7
02EDH
40
33.1
50.5
1
9
032CH
40
31.5
54.8
1
11
036BH
40
30
59.9
1
13
03AAH
40
28.7
66.1
1
15
03E9H
40
27.4
73.7
2
3
046EH
40
34.9
46.8
Remarks
(Continued)
88
DS07-16613-3E
MB91460M Series
Modulation
Degree
(k)
Random No
(N)
CMPR
[hex]
center clk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
2
5
04ACH
40
31.5
54.8
2
7
04EAH
40
28.7
66.1
3
3
066DH
40
33.1
50.5
3
5
06AAH
40
28.7
66.1
4
3
086CH
40
31.5
54.8
5
3
0A6BH
40
30
59.9
6
3
0C6AH
40
28.7
66.1
7
3
0E69H
40
27.4
73.7
1
3
026FH
36
33.3
39.2
1
5
02AEH
36
31.5
42
1
7
02EDH
36
29.9
45.3
1
9
032CH
36
28.4
49.2
1
11
036BH
36
27.1
53.8
1
13
03AAH
36
25.8
59.3
1
15
03E9H
36
24.7
66.1
2
3
046EH
36
31.5
42
2
5
04ACH
36
28.4
49.2
2
7
04EAH
36
25.8
59.3
2
9
0528H
36
23.7
74.7
3
3
066DH
36
29.9
45.3
3
5
06AAH
36
25.8
59.3
4
3
086CH
36
28.4
49.2
4
5
08A8H
36
23.7
74.7
5
3
0A6BH
36
27.1
53.8
6
3
0C6AH
36
25.8
59.3
7
3
0E69H
36
24.7
66.1
8
3
1068H
36
23.7
74.7
1
3
026FH
32
29.7
34.7
1
5
02AEH
32
28
37.3
1
7
02EDH
32
26.6
40.2
1
9
032CH
32
25.3
43.6
1
11
036BH
32
24.1
47.7
1
13
03AAH
32
23
52.5
Remarks
(Continued)
DS07-16613-3E
89
MB91460M Series
(Continued)
Modulation
Degree
(k)
90
Random No
(N)
CMPR
[hex]
center clk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
1
15
03E9H
32
22
58.6
2
3
046EH
32
28
37.3
2
5
04ACH
32
25.3
43.6
2
7
04EAH
32
23
52.5
2
9
0528H
32
21.1
66.1
3
3
066DH
32
26.6
40.2
3
5
06AAH
32
23
52.5
3
7
06E7H
32
20.3
75.9
4
3
086CH
32
25.3
43.6
4
5
08A8H
32
21.1
66.1
5
3
0A6BH
32
24.1
47.7
6
3
0C6AH
32
23
52.5
7
3
0E69H
32
22
58.6
8
3
1068H
32
21.1
66.1
9
3
1267H
32
20.3
75.9
Remarks
DS07-16613-3E
MB91460M Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute maximum ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC3
VSS − 0.5
VSS + 4.0
V
VCC5 ≥ VCC3
VCC5
VSS − 0.5
VSS + 6.0
V
VCC5 ≥ VCC3
AVCC3
VSS − 0.5
VSS + 4.0
V
VCC3 ≥ AVCC3 ≥ AVRH
AVRH
VSS − 0.5
VSS + 4.0
V
VCC3 ≥ AVRH
Input voltage 1*1
VI1
VSS − 0.3
VCC3 + 0.3
V
3 V pin group
Input voltage 2*1
VI2
VSS − 0.3
VCC5 + 0.3
V
5 V pin group
Power supply voltage*1
VIA
VSS − 0.3
AVCC3 + 0.3
V
1
VO1
VSS − 0.3
VCC3 + 0.3
V
3 V pin group
Output voltage 2*1
VO2
VSS − 0.3
VCC5 + 0.3
V
5 V pin group
Maximum clamp current (+B input)
ICLAMP
−2
2
mA
*2
Total maximum clamp current (+B input)
ΣICLAMP
−20
20
mA
*2
IOL
⎯
10
mA
*3
“L” level average output current
IOLAV
⎯
8
mA
*4
“L” level total maximum output current
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
*5
IOH
⎯
−10
mA
*3
“H” level average output current
IOHAV
⎯
−4
mA
*4
“H” level total maximum output current
ΣIOH
⎯
−50
mA
ΣIOHAV
⎯
−20
mA
Power consumption
PD
⎯
500
mW
Operating temperature
TA
−40
+ 105
°C
Tstg
−55
+ 150
°C
Analog pin input voltage
Output voltage 1*
“L” level maximum output current
“L” level total average output current
“H” level maximum output current
“H” level total average output current
Storage temperature
*5
*1 : This parameter is based on VSS = AVSS = 0.0 V
*2 : •
•
•
•
This is a 5 V pin which works as a port or serves with a port.
Use within recommended operating conditions.
Use with DC voltage (current).
The standard value of +B input is defined as the power supply flowing through any one of the corresponding
pins.
• +B signals are input signals that exceed the VCC5 voltage.
Connect limiting resistor between the +B signal and the microcontroller.
• The value of the limiting resistor should be set so that the current input to the microcontroller pin does not
exceed the rated value at any time , either instantaneously or for an extended period, when the +B signal is
input.
• Note that when the microcontroller drive current is low, such as in the low power consumption modes, the
+B input potential can increase the potential at the power supply pin VCC5, VCC3 via a protective diode,
possibly affecting other devices.
(Continued)
DS07-16613-3E
91
MB91460M Series
(Continued)
• Note that if the +B signal is input when the microcontroller is off (not fixed at 0 V), power is supplied through
the +B input pin; therefore, the microcontroller may partially operate.
• Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on
reset may not function in the power supply voltage.
• Do not leave +B input pins open.
• Example of recommended circuit :
MB91F467MA
Protective diode
ICLAMP
Limiting resistor
+B input (0 V to 16 V)
*3 : Maximum output current is defined as the value of the peak current flowing through any one of the corresponding
pins.
*4 : Average output current is defined as the value of the average current flowing through any one of the
corresponding pins for a 100 ms period. The average value is the operation current × the operation ratio.
*5 : Total average output current is defined as the value of the average current flowing through all of the
corresponding pins for a 100 ms period. The average value is the operation current × the operation ratio.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
92
DS07-16613-3E
MB91460M Series
2. Recommended operating conditions
(VSS = AVSS = 0.0 V)
Parameter
Symbol
Power supply voltage
Value
Unit
Max
VCC5
3.0
5.5
V
5 V operation guarantee range
VCC3
3.0
3.6
V
3 V operation guarantee range
AVCC3
3.0
3.6
V
Analog operation guarantee range
μF
Use a ceramic capacitor or a
capacitor that has the similar
frequency characteristics.
Use a capacitor with a capacitance
greater than CS as the smoothing
capacitor on the VCC5, VCC3 pins.
Smoothing capacitor at
C_1, C_2 pin
CS
Power supply slew rate
⎯
1
50
V/ms
Operating temperature
TA
−40
+ 105
°C
Main oscillation stabilization
time
⎯
8
⎯
ms
Look-up time
PLL (4 MHz→16 ...80 MHz)
⎯
⎯
0.6
ms
Vsurge
2
⎯
kV
fRC100kHz
50
200
kHz
fRC2MHz
1
4
MHz
ESD Protection
( Human body model)
RC Oscillator
Remarks
Min
4.7
(accuracy within ± 50%)
Rdischarge = 1.5 kΩ
Cdischarge = 100 pF
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
• C Pin Connection Diagram
C_1
CS
DS07-16613-3E
VSS
C_2
AVSS
CS
93
MB91460M Series
3. DC characteristics
(TA = −40 °C to + 105 °C, VCC5 = 5.0 V ± 10%, VCC3 = 3.3 V ±10%, VSS = AVSS = 0.0 V)
Parameter Symbol
“H” level
input
voltage
“L” level
input
voltage
Pin name
Condition
Value
Min
Typ
Max
Unit
Remarks
VIH1
CMOS-hys
⎯
0.8 VCC5/3
⎯
VCC5/3 +
0.3
V
CMOS hysteresis
input pin
VIH2
CMOS-hys
⎯
0.7 VCC5/3
⎯
VCC5/3 +
0.3
V
CMOS hysteresis
input pin
VIH3
CMOS
⎯
0.7 VCC5
⎯
VCC5 + 0.3
V
CMOS input pin
VIH4
Automotive
⎯
0.8 VCC5
⎯
VCC5 + 0.3
V
Automotive input pin
VIH5
MediaLB
⎯
1.7
⎯
VCC3 + 0.3
V
MediaLB input pin
VIHM
MD4 to MD0
⎯
VCC5 - 0.3
⎯
VCC5 + 0.3
V
VIHX5
INITX
⎯
0.8 VCC5
⎯
VCC5 + 0.3
V
VIHX3
X0, X1, X0A,
X1A, TRSTX
⎯
0.8 VCC3
⎯
VCC3 + 0.3
V
TRSTX can
withstand 5 V.
VIL1
CMOS-hys
⎯
VSS - 0.3
⎯
0.2 VCC5/3
V
CMOS hysteresis
input pin
VIL2
CMOS-hys
⎯
VSS - 0.3
⎯
0.3 VCC5/3
V
CMOS hysteresis
input pin
VIL3
CMOS
⎯
VSS - 0.3
⎯
0.3 VCC5/3
V
CMOS input pin
VIL4
Automotive
⎯
VSS - 0.3
⎯
0.5 VCC5
V
Automotive input pin
VIL5
MediaLB
⎯
VSS - 0.3
⎯
0.7
V
MediaLB input pin
VILM
MD4 to MD0
⎯
VSS - 0.3
⎯
VSS + 0.3
V
MD pin
VILX5
INITX
⎯
VSS - 0.3
⎯
0.2 VCC5
V
VILX3
X0, X1, X0A,
X1A, TRSTX
⎯
VSS - 0.3
⎯
0.2 VCC3
V
(Continued)
94
DS07-16613-3E
MB91460M Series
(TA = −40 °C to + 105 °C, VCC5 = 5.0 V ± 10%, VCC3 = 3.3 V ±10%, VSS = AVSS = 0.0 V)
Parameter
Symbol
ICC
ICCS
Power
supply
current*
Pin
name
Condition
VCC3 At Main RUN
VCC3 At Main SLEEP
Value
Min
⎯
⎯
Typ
110
30
Max
140
55
Unit
Remarks
mA
Core : 80 MHz
Peripheral : 20 MHz
External bus : 40 MHz
CAN : 20 MHz
MediaLB : 28 MHz
(No load on the
external bus )
mA
Core : 80 MHz
Peripheral : 20 MHz
External bus : 40 MHz
CAN : 20 MHz
MediaLB : 28 MHz
(No load on the
external bus )
ICCH
TA = + 25 °C, VCC5 = 5 V,
VCC5,
VCC3 = 3.3 V,
VCC3
At STOP mode
⎯
0.1
1
mA
Main oscillation/PLL
stop
Sub oscillation stop
Main regulator stop
Low voltage detector
stop
ICCHS
TA = + 25 °C, VCC5 = 5 V,
VCC5,
VCC3 = 3.3 V,
VCC3
At shutdown
⎯
10
50
μA
Shutdown mode
Low voltage detector
stop
ICCL
Operation frequency FCP =
32 kHz,
VCC3
TA = + 25 °C, VCC3 = 3.3 V,
At Sub RUN
mA
Main oscillation/PLL
stop
Low voltage detector
stop
⎯
1
2
ICTS4M1
Main clock frequency = 4 MHz,
TA = + 25 °C, VCC3 = 3.3 V,
VCC3
At stop
(Real Time Clock Operation)
⎯
500
1000
μA
PLL/Sub oscillation
stop
Low voltage detector
stop
ICTS32K1
Sub clock frequency = 32 kHz,
TA = + 25 °C, VCC3 = 3.3 V
VCC3
At stop
(Real Time Clock Operation)
⎯
200
700
μA
Main oscillation/PLL
stop Low voltage
detector stop
ICTS4M2
Main clock frequency = 4 MHz,
TA = + 25 °C, VCC3 = 3.3 V,
VCC3
At stop
(Real Time Clock Operation)
⎯
650
1150
μA
PLL/Sub oscillation
stop
ICTS32K2
Sub clock frequency = 32 kHz,
TA = + 25 °C, VCC3 = 3.3 V
VCC3
At stop
(Real Time Clock Operation)
⎯
350
850
μA
Main oscillation/PLL
stop
* : Power supply current is obtained when an external clock is supplied from X1/X1A pins.
(Continued)
DS07-16613-3E
95
MB91460M Series
(Continued)
(TA = −40 °C to + 105 °C, VCC5 = 5.0 V ± 10%, VCC3 = 3.3 V ±10%, VSS = AVSS = 0.0 V)
Parameter
Symbol
Input leakage
current
IIL
Pin name
Condition
Value
Unit Remarks
Min
Typ
Max
VCC5 = 5 V
All input pins VCC3 = AVCC3 = 3.3 V
VSS < VI < VCC5/3
−5
⎯
+5
μA
CIN
Other than
VCC5,
VCC3, VSS,
AVCC3,
AVSS,
AVRH,
C_1, C_2
⎯
⎯
5
15
pF
Pull-up
resistance
RUP
INITX,
Pins with
pull-up
resistance
⎯
25
50
100
kΩ
Pull-down
resistance
RDOWN
Pins with
pull-down
resistance
⎯
25
50
100
kΩ
VOH1
5/3 V pin
VCC5 = 5.0 V, IOH = −5.0 mA
VCC5 − 0.5
VCC5 = 3.3 V, IOH = −2.0 mA
⎯
⎯
V
VOH2
3 V pin
VCC3 = 3.3 V, IOH = −4.0 mA VCC3 − 0.5
⎯
⎯
V
2.0
⎯
⎯
V
Input
capacitance 1
Output “H”
voltage
VOH3
Output “L”
voltage
VOL1
5/3 Vpin
VCC5 = 5.0 V, IOL = 5.0 mA
VCC5 = 3.3 V, IOL = 2.0 mA
⎯
⎯
0.4
V
VOL2
3 Vpin
VCC3 = 3.3 V, IOL = 4.0 mA
⎯
⎯
0.4
V
MediaLB pin VCC3 = 3.3 V, IOL = 6.0 mA
⎯
⎯
0.4
V
VOL3
96
MediaLB pin VCC3 = 3.3 V, IOH = −6.0 mA
DS07-16613-3E
MB91460M Series
4. A/D converter characteristics
(1) Electrical Characteristics
(TA = −40 °C to + 105 °C, VCC3 = AVCC3 = 3.3 V ± 10%, VSS = AVSS = 0.0 V)
Symbol
Pin name
Resolution
⎯
Total error
Parameter
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
10
Bit
⎯
⎯
⎯
⎯
±3
LSB
Nonlinearity error
⎯
⎯
⎯
⎯
±2.5
LSB
Differential linearity error
⎯
⎯
⎯
⎯
±1.9
LSB
AVSS
+ 0.5LSB
AVSS
+ 2.5LSB
V
Remarks
AVCC3 = 3.3 V
AVRH = 3.3 V
Zero transition voltage
VOT
AN0 to AN11
AVSS
− 1.5LSB
Full scale transition voltage
VFST
AN0 to AN11
AVRH
− 3.5LSB
AVRH
− 1.5LSB
AVRH
+ 0.5LSB
V
Sampling time
tSMP
⎯
1000
⎯
⎯
ns
Compare time
tCMP
⎯
2200
⎯
⎯
ns
A/D conversion time
tCNV
⎯
3
⎯
1000
μs
tSMP + tCMP
Analog port input current
IAIN
AN0 to AN11
⎯
⎯
10
μA
AVCC3 ≥ VAIN ≥
AVSS
Analog input voltage
VAIN
AN0 to AN11
AVSS
⎯
AVRH
V
AVR +
AVRH
AVSS
⎯
AVCC3
V
⎯
1.9
3.7
mA
⎯
⎯
5
μA
*2
Reference voltage
Power supply current
IA
IAH
AVCC3
At REXT < 4.2 kΩ
*1
IR
AVRH
⎯
500
900
μA
AVRH = 3.3 V
IRH
AVRH
⎯
⎯
5
μA
*2
Analog input equivalent
capacitance
CSH
AN0 to AN11
⎯
⎯
8.5
pF
Analog input equivalent
resistance
RIN
AN0 to AN11
⎯
⎯
12.1
kΩ
Offset between input
channels
⎯
AN0 to AN11
⎯
⎯
5
LSB
Reference voltage current
*1 : Assuming that output impedance at external analog signal source is 4.2 kΩ or less. If output impedance is more
than 4.2 kΩ, it is necessary to take a long sampling time.
Set tCNV ≤ tSMP + tCMP for actual use.
*2 : Assuming that A/D converter is inactive and power supply current is in CPU stop mode (VCC3 = AVCC3 = AVRH
= 3.3 V)
DS07-16613-3E
97
MB91460M Series
Note:
< About the external impedance of analog input and its sampling time >
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
Analog input circuit model
R
Analog input
Comparator
C
During sampling:ON
R
C
12.1 kΩ (max) 8.5 pF(max)
Note: The values are reference values.
To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and
minimum sampling time and either adjust the operating frequency or decrease the external impedance so that
the sampling time is longer than the minimum value.
<Countermeasure for noise which generates on reference power supply>
We recommend to put some μF of bypass capacitor into the reference power supply (AVRH pin).
<About errors>
As |AVRH-AVSS| becomes smaller, values of relative errors grow larger.
<Other>
• When inserting a capacitor for blocking direct current between an external circuit and an input pin, set the
capacitance value to approximately some thousand times of CSH in order to suppress any influence by the
voltage divided depending on chip's internal sampling capacitance CSH.
98
DS07-16613-3E
MB91460M Series
Definition of A/D converter terms
• Resolution
Analog variation that is recognizable by the A/D converter.
• Nonlinearity error
Deviation between actual conversion characteristics and a straight line connecting the zero transition point
(00 0000 0000B ↔ 00 0000 0001B) and the full scale transition point (11 1111 1110B ↔ 11 1111 1111B).
• Differential nonlinearity error
Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB.
• Total error
This error indicates the difference between actual and theoretical values, including the zero transition error,
full scale transition error, and nonlinearity error.
Total error
3FFH
3FEH
1.5 LSB’
Actual conversion
characteristics
Digital output
3FDH
{1 LSB’ (N − 1) + 0.5 LSB’}
004H
VNT
(measurement value)
003H
Actual conversion
characteristics
002H
Ideal characteristics
001H
0.5 LSB'
AVSS
AVRH
Analog input
1LSB' (ideal value) = AVRH − AVSS
1024
[V]
Total error of digital output N = VNT − {1 LSB' × (N − 1) + 0.5 LSB'}
1 LSB'
N : A/D converter digital output value
VOT' (ideal value) = AVSS + 0.5 LSB' [V]
VFST' (ideal value) = AVRH − 1.5 LSB' [V]
VNT : Voltage at which the digital output changes from (N + 1) to N
(Continued)
DS07-16613-3E
99
MB91460M Series
(Continued)
Nonlinearity error
3FFH
Differential nonlinearity error
Actual conversion characteristics
Actual conversion characteristics
(N+1)
3FEH
{1 LSB (N - 1) + VOT}
Digital output
004H
003H
002H
(measurement value)
VNT
(measurement value)
Actual conversion
characteristics
Digital output
VFST
3FDH
Ideal
characteristics
N
(N-1)
VFST
VNT
(measurement value)
Ideal characteristics
(N-2)
001H
Actual conversion
characteristics
VOT (measurement value)
AVSS
AVRH
AVSS
Analog input
Nonlinearity error of digital output N =
VFST − VOT
1022
AVRH
Analog input
VNT − {1LSB × (N − 1) + VOT} [LSB]
1LSB
Differential nonlinearity error of digital output N =
1LSB =
(measurement value)
V (N + 1) T − VNT
1LSB
− 1 [LSB]
[V]
N
: A/D converter digital output value
VOT : Voltage at which the digital output changes from 000H to 001H.
VFST : Voltage at which the digital output changes from 3FEH to 3FFH.
100
DS07-16613-3E
MB91460M Series
5. FLASH memory program/erase characteristics
(TA = + 25 °C, VCC5 = 5.0 V, VCC3 = 3.3 V)
Parameter
Value
Unit
Remarks
Min
Typ
Max
Sector erase time
⎯
0.5
⎯
s
Erasure programming time not
included
Chip erase time
⎯
n*0.5
⎯
s
n is the number of Flash sector of the
device
Word (16-bit width)
programming time
⎯
6
⎯
μs
System overhead time not included
Programme/Erase cycle
10000
⎯
⎯
cycle
Flash data retention time
10
⎯
⎯
year
*
*: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation
to convert high temperature measurements into normalized value at + 85oC).
DS07-16613-3E
101
MB91460M Series
6. AC characteristics
6.1.
Clock timing
(VCC5 = 5.0 V ±10%, VCC3 = 3.3 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
fC
Clock cycle time
Value
Unit
Condition
Min
Typ
Max
X0
X1
3.4
⎯
4.2
tC
X0
X1
238
⎯
294
ns
Clock frequency
fCS
X0A
X1A
32
⎯
100
kHz
Clock cycle time
tCS
X0A
X1A
10
⎯
31.25
μs
fCP
0.032
⎯
80
MHz
CPU
fCPP
0.032
⎯
20
MHz
Peripheral
0.032
⎯
40
MHz
External bus
fCAN
⎯
⎯
20
MHz
Clock after division by
CAN prescaler
fMLB
⎯
⎯
26
MHz
MediaLB
tCP
12.5
⎯
31250
ns
CPU
tCPP
50
⎯
31250
ns
Peripheral
25
⎯
31250
ns
External bus
tCAN
50
⎯
⎯
ns
Clock after division by
CAN prescaler
tMLB
38.5
⎯
⎯
ns
MediaLB
Clock frequency
Internal operation
clock frequency
Internal operation
clock cycle time
fCPT
tCPT
⎯
⎯
MHz
Main clock
Sub clock
• Clock timing condition
tC, tCS
Output pin
X0, X0A,
X1, X1A
102
0.8 VCC
C=50 pF
DS07-16613-3E
MB91460M Series
6.2.
Reset input ratings
(VCC5 = 5.0 V ±10%, VCC3 = 3.3 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
INITX input time
(at power-on, when returning from
shutdown )
Symbol
Pin name
Condition
tINTL
INITX
⎯
INITX input time
(other than the above)
Value
Unit
Min
Max
8
⎯
ms
20
⎯
μs
tINTL
0.2 VCC
INITX
6.3.
Interrupt characteristics for recover from shutdown
(VCC5 = 5.0 V ±10%, VCC3 = 3.3 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Interrupt input time
(If using level interrupt during
recover from shutdown)
DS07-16613-3E
Condition
⎯
Value
Min
Max
500
⎯
Unit
μs
103
MB91460M Series
6.4.
LIN-USART
•Bit setting : ESCR : SCES = 0, ECCR : SCDE = 0
(TA = −40 °C to + 105 °C, VCC5 = 5.0 V ±10%, VCC3 = 3.3 V ±10%, Vss = 0.0 V)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCKn
SCK↓ → SOT delay time
tSLOVI
SCKn,
SOTn
Valid SIN → SCK ↑
tIVSHI
SCKn, SINn
SCK ↑ → Valid SIN hold time
tSHIXI
Serial clock “L” pulse width
Condition
Value
Unit
Min
Max
5 tCP
⎯
ns
− 50
+ 50
ns
tCP + 80
⎯
ns
SCKn, SINn
0
⎯
ns
tSHSL
SCKn
3 tCP − tR
⎯
ns
Serial clock “H” pulse width
tSLSH
SCKn
tCP + 10
⎯
ns
SCK↓ → SOT delay time
tSLOVE
SCKn,
SOTn
⎯
2 tCP + 60
ns
Valid SIN → SCK ↑
tIVSHE
SCKn, SINn
30
⎯
ns
SCK ↑ → Valid SIN hold time
tSHIXE
SCKn, SINn
tCP + 30
⎯
ns
SCK rising time
tF
SCKn
⎯
10
ns
SCK falling time
tR
SCKn
⎯
10
ns
Internal shift clock
mode output pin
CL = 80 pF + 1 TTL
External shift clock
mode output pin
CL = 80 pF + 1 TTL
Notes: • AC characteristic in CLK synchronized mode.
• CL is the load capacity of a pin during testing.
• tCP indicates the peripheral clock (CLKP) cycle time (Unit : ns).
• Internal shift clock mode
tSCYC
SCKn
2.4 V
0.8 V
0.8 V
tSLOVI
SOTn
2.4 V
0.8 V
tIVSHI
SINn
104
tSHIXI
VIH
VIH
VIL
VIL
DS07-16613-3E
MB91460M Series
• External shift clock mode
tSLSH
tSHSL
VIL
VIL
tF
SOTn
VIH
VIH
SCKn
tSLOVE
tR
2.4 V
0.8 V
tIVSHE
SINn
DS07-16613-3E
tSHIXE
VIH
VIH
VIL
VIL
105
MB91460M Series
• Bit setting : ESCR : SCES = 1, ECCR : SCDE = 0
(TA = −40 °C to + 105 °C, VCC5 = 5.0 V ±10%, VCC3 = 3.3 V ±10%, Vss = 0.0 V)
Parameter
Serial clock cycle time
Symbol
Pin name
tSCYC
SCKn
Condition
Internal shift clock
mode output pin
CL = 80 pF + 1 TTL
Value
Unit
Min
Max
5 tCP
⎯
ns
− 50
+ 50
ns
tCP + 80
⎯
ns
SCK ↑ →SOT delay time
tSHOVI
SCKn, SOTn
Valid SIN→SCK ↓
tIVSLI
SCKn, SINn
SCK ↓ →Valid SIN hold time
tSLIXI
SCKn, SINn
0
⎯
ns
Serial clock “H” pulse width
tSHSL
SCKn
3 tCP − tR
⎯
ns
Serial clock “L” pulse width
tSLSH
SCKn
tCP + 10
⎯
ns
SCK ↑ →SOT delay time
tSHOVE
SCKn, SOTn
⎯
2 tCP + 60
ns
Valid SIN→SCK ↓
tIVSLE
SCKn, SINn
30
⎯
ns
SCK ↓ →Valid SIN hold time
tSLIXE
SCKn, SINn
tCP + 30
⎯
ns
SCK rise
tF
SCKn
⎯
10
ns
SCK fall
tR
SCKn
⎯
10
ns
External shift clock
mode output pin
CL = 80 pF + 1 TTL
Notes: • CL is the load capacity of a pin during testing.
• tCP indicates the peripheral clock (CLKP) cycle time (Unit : ns).
• Internal shift clock mode
tSCYC
SCKn
2.4 V
0.8 V
tSHOVI
SOTn
2.4 V
0.8 V
tIVSLI
SINn
106
tSLIXI
VIH
VIH
VIL
VIL
DS07-16613-3E
MB91460M Series
• External shift clock mode
tSHSL
VIL
tR
SOTn
VIH
VIH
SCKn
tSLSH
tSHOVE
VIL
tF
2.4 V
0.8 V
tIVSLE
SINn
DS07-16613-3E
tSLIXE
VIH
VIH
VIL
VIL
107
MB91460M Series
• Bit setting:ESCR:SCES = 0, ECCR:SCDE = 1
(TA = −40 °C to + 105 °C, VCC5 = 5.0 V ±10%, VCC3 = 3.3 V ±10%, Vss = 0.0 V)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCKn
SCK ↑ →SOT delay time
tSHOVI
SCKn, SOTn
Valid SIN→SCK ↓
tIVSLI
SCKn, SINn
SCK ↓ →Valid SIN hold time
tSLIXI
SCKn, SINn
SOT→SCK ↓ delay time
tSOVLI
SCKn, SOTn
Condition
Internal shift clock
mode output pin
CL = 80 pF + 1 TTL
Value
Unit
Min
Max
5 tCP
⎯
ns
− 50
+ 50
ns
tCP + 80
⎯
ns
0
⎯
ns
3 tCP − 70
⎯
ns
Notes: • CL is the load capacity of a pin during testing.
• tCP indicates the peripheral clock (CLKP) cycle time (Unit : ns).
tSCYC
2.4 V
SCKn
0.8 V
0.8 V
tSHOVI
tSOVLI
SOTn
2.4 V
2.4 V
0.8 V
0.8 V
tIVSLI
SINn
108
VIH
VIL
tSLIXI
VIH
VIL
DS07-16613-3E
MB91460M Series
• Bit setting:ESCR:SCES = 1, ECCR:SCDE = 1
(TA = −40 °C to + 105 °C, VCC5 = 5.0 V ±10%, VCC3 = 3.3 V ±10%, Vss = 0.0 V)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCKn
SCK ↓ →SOT delay time
tSLOVI
SCKn, SOTn
Valid SIN→SCK ↑
tIVSHI
SCKn, SINn
SCK ↑ →Valid SIN delay time
tSHIXI
SCKn, SINn
SOT→SCK ↑ delay time
tSOVHI
SCKn, SOTn
Value
Condition
Internal shift clock
mode output pin
CL = 80 pF + 1 TTL.
Unit
Min
Max
5 tCP
⎯
ns
− 50
+ 50
ns
tCP + 80
⎯
ns
0
⎯
ns
3 tCP − 70
⎯
ns
Notes: • CL is the load capacity of a pin during testing.
• tCP indicates the peripheral clock (CLKP) cycle time (Unit : ns).
tSCYC
2.4 V
2.4 V
SCKn
0.8 V
tSLOVI
tSOVHI
SOTn
2.4 V
2.4 V
0.8 V
0.8 V
tIVSHI
SINn
DS07-16613-3E
tSHIXI
VIH
VIH
VIL
VIL
109
MB91460M Series
6.5.
Free-run timer clock
(VCC5 = 5.0 V ±10%, VCC3 = 3.3 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
Condition
tTIWH
tTIWL
FRCKn
⎯
Input pulse width
Value
Min
Max
4tCLKP
⎯
Unit
ns
Note: tCLKP is the cycle time of the peripheral clock.
FRCKn
VIH
VIH
tTIWH
6.6.
VIL
VIL
tTIWL
Trigger input timing
(VCC5 = 5.0 V ±10%, VCC3 = 3.3 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
Condition
tINP
ICUn
tATGX
ATGX
Input capture input trigger
A/D converter trigger
Value
Unit
Min
Max
⎯
5tCLKP
⎯
ns
⎯
5tCLKP
⎯
ns
Note: tCLKP is the cycle time of the peripheral clock.
tATGX, tINP
ICUn,
ATGX
110
VIL
VIL
DS07-16613-3E
MB91460M Series
MediaLB AC characteristics
• Input
tmckc
tdhmcf
MLBCLK
tdsmcf
MLBDAT,
MLBSIG
valid
(VCC3 = 3.3 V ± 10%, VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
Pin name
Condition
MLBCLK cycle
tmckc
MLBCLK
MLBSIG, MLBDAT
input setup
tdsmcf
MLBSIG, MLBDAT
input hold
tdhmcf
Value
Unit
Min
Typ
Max
⎯
⎯
40
⎯
ns
MLBSIG
MLBDAT
⎯
1
⎯
⎯
ns
MLBSIG
MLBDAT
⎯
4
⎯
⎯
ns
Remarks
• Output
tmckc
tmcfdz
MLBCLK
tdout
MLBDAT,
MLBSIG
valid
(VCC3 = 3.3 V ± 10%, VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol Pin name Condition
Value
Min
Typ
Max
Unit
MLBCLK cycle
tmckc
MLBCLK
⎯
⎯
40
⎯
ns
MLBSIG, MLBDAT
output stop
tmcfdz
MLBSIG
MLBDAT
⎯
0
⎯
⎯
ns
MLBSIG, MLBDAT
output delay
tdout
MLBSIG
MLBDAT
⎯
⎯
⎯
11
ns
Remarks
Note: Addition capacity 50 pF
DS07-16613-3E
111
MB91460M Series
I2S AC characteristics
• Input
tCSCK
tSSD
SCK0
tHSD
SDn
valid
• Output
tCSCK
SCK0
tDSD
invalid
SDn
valid
(VCC3 = 3.3 V ± 10%, VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
Pin name
Condition
SCK cycle
tCSCK
SCK0
SD
input setup
tSSD
SD
input hold
SD
output delay
Value
Unit
Min
Typ
Max
⎯
651
⎯
⎯
ns
SDn
⎯
50
⎯
⎯
ns
tHSD
SDn
⎯
50
⎯
⎯
ns
tDSD
SDn
⎯
⎯
⎯
50
ns
Remarks
Note: Addition capacity 50 pF
112
DS07-16613-3E
MB91460M Series
6.7.
6.7.1.
External Bus AC Timings
Basic Timing
(Vcc3 = 3.3 V ± 10%, Vss = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
SYSCLK
SYSCLK ↓ →CSnX delay
SYSCLK ↑ →CSnX delay
when using CS delay
function
SYSCLK ↓ →ASX delay
SYSCLK ↓ →BAAX delay
SYSCLK ↓ →address
output delay
Symbol
tCLCH
tCHCL
Pin name
Condition
SYSCLK
tCLCSL
tCLCSH
SYSCLK
CSnX
tCHCSL
Value
Min
Typ
Max
⎯
tCLKT / 2
⎯
⎯
tCLKT / 2
⎯
−6
⎯
+6
−6
⎯
+6
−6
⎯
+6
−6
⎯
+6
−6
⎯
+6
⎯
tCLASL
tCLASH
tCLBAL
tCLBAH
tCLAV
SYSCLK
ASX
Unit
ns
SYSCLK
BAAX
−6
⎯
+6
−6
⎯
+6
SYSCLK
A23 to A00
−6
⎯
+6
Note: tCLKT is the cycle time of the external bus clock.
DS07-16613-3E
113
MB91460M Series
tCLCH
tCYC
tCHCL
VOH
SYSCLK
VOL
VOL
VOL
tCLCSL
tCLCSH
CSnX
VOH
VOL
tCHCSL
Delay CSnX
VOL
tCLASH
tCLASL
ASX
VOH
VOL
tCLAV
Address
VOH
VOL
tCLBAH
tCLBAL
BAAX
VOH
VOL
114
DS07-16613-3E
MB91460M Series
6.7.2.
Read access
(Vcc3 = 3.3 V ±10%, Vss = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
SYSCLK ↑ → RDX delay
Symbol
Pin name
tCHRL
SYSCLK
RDX
tCHRH
Condition
Value
Min
Typ
Max
−6
⎯
+6
−6
⎯
+6
Data Valid → RDX ↑ setup
tDSRH
RDX
D31 to D16
30
⎯
⎯
RDX ↑ → Valid data hold
tRHDX
RDX
D31 to D16
0
⎯
⎯
Data Valid → SYSCLK ↑ setup
tDSCH
MCLKI
D31 to D16
6
⎯
⎯
SYSCLK ↑ → Valid data hold
tCHDX
MCLKI
D31 to D16
6
⎯
⎯
SYSCLK ↓ → WRnX delay
(as byte enable)
tCLWRL
MCLKO
WRnX
⎯
3
⎯
⎯
3
⎯
MCLKO
CSnX
−6
⎯
+6
−6
⎯
+6
SYSCLK ↓ → CSnX delay
DS07-16613-3E
tCLWRH
tCLCSL
tCLCSH
⎯
Unit
ns
115
MB91460M Series
SYSCLK
VOH
VOL
VOL
VOL
MCLKI
tCLCSH
tCLCSL
CSnX
VOH
VOL
tCLWRH
tCLWRL
WRnX
(as byte enable)
VOH
VOL
tCHRH
tCHRL
VOH
RDX
VOL
tDSRH
tRHDX
tDSCH
DATA input
116
tCHDX
VIH
VIH
VIL
VIL
DS07-16613-3E
MB91460M Series
6.7.3.
Synchronous write access − Byte control type
(Vcc3 = 3.3 V ±10%, Vss = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
SYSCLK ↓ → WEX delay
Symbol
Pin name
tCLWL
SYSCLK
WEX
tCLWH
Typ
Max
−6
⎯
+6
−6
⎯
+6
⎯
0
⎯
⎯
tCLKT
⎯
SYSCLK
WRnX
⎯
3
⎯
⎯
3
⎯
SYSCLK
CSnX
−6
⎯
+6
−6
⎯
+6
tDSWL
WEX
D31 to D16
WEX ↑ → Valid data hold
tWHDH
WEX
D31 to D16
SYSCLK ↓ → WRnX delay
(as byte enable)
tCLWRL
SYSCLK ↓ → CSnX delay
tCLCSL
tCLCSH
Value
Min
Data Valid → WEX ↓ setup
tCLWRH
Condition
⎯
Unit
ns
SYSCLK
VOL
VOL
VOL
tCLCSH
tCLCSL
VOH
CSnX
VOL
tCLWRH
tCLWRL
VOH
WRnX
(as byte enable)
VOL
tCLWH
tCLWL
WEX
VOH
VOL
tDSWL
DATA output
DS07-16613-3E
tWHDH
VOH
VOH
VOL
VOL
117
MB91460M Series
6.7.4.
Synchronous write access − Non-byte control type
(Vcc3 = 3.3 V ±10%, Vss = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
SYSCLK ↑ →WRnX delay
Data Valid →WRnX ↓ setup
WRnX ↑ →Valid data hold
SYSCLK ↓ →CSnX delay
SYSCLK
Symbol Pin name Condition
tCLWRL
tCLWRH
SYSCLK
WEX
tDSWRL
WEX
D31 to
D16
tWRHDH
WEX
D31 to
D16
tCLCSL
tCLCSH
Value
Min
Typ
Max
−6
⎯
+6
−6
⎯
+6
⎯
0
⎯
⎯
ns
SYSCLK
CSnX
VOH
Unit
⎯
tCLKT
⎯
−6
⎯
+6
−6
⎯
+6
VOL
VOL
tCLCSL
tCLCSH
VOH
CSnX
VOL
tCLWRH
tCLWRL
WRnX
VOH
VOL
tDSWRL
tWRHDH
DATA output
118
VOH
VOH
VOL
VOL
DS07-16613-3E
MB91460M Series
6.7.5.
Asynchronous write access − Byte control type
(Vcc3 = 3.3 V ±10%, Vss = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
WEX ↓ →WEX ↑ pulse width
tWLWH
Data Valid →WEX ↓ setup
WEX ↑ →Valid data hold
WEX→WRnX delay
WEX→CSnX delay
Condition
Value
Min
Typ
Max
WEX
⎯
tCLKT
⎯
tDSWL
WEX
D31 to D16
⎯
tCLKT / 2
⎯
tWHDH
WEX
D31 to D16
⎯
tCLKT / 2
⎯
⎯
tCLKT / 2
⎯
⎯
tCLKT / 2
⎯
⎯
tCLKT / 2
⎯
⎯
tCLKT / 2
⎯
tWRLWL
⎯
ns
WEX
WRnX
tWHWRH
tCLWL
WEX
CSnX
tWHCH
Unit
CSnX
VOH
VOL
tCLWL
tWHCH
WRnX
VOH
(as byte enable)
VOL
tWHWRH
tWRLWL
tWLWH
WEX
tDSWL
DATA output
DS07-16613-3E
tWHDH
VOH
VOH
VOL
VOL
119
MB91460M Series
6.7.6.
Asynchronous write access − Non-byte control type
(Vcc3 = 3.3 V ±10%, Vss = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
WRnX ↓ →WRnX ↑ pulse width
tWRLWRH
Data Valid →WRnX ↓ setup
WRnX ↑ →Valid data hold
WRnX→CSnX delay
Condition
Value
Min
Typ
Max
WRnX
⎯
tCLKT
⎯
tDSWRL
WRnX
D31 to D16
⎯
tCLKT / 2
⎯
tWRHDH
WRnX
D31 to D16
⎯
tCLKT / 2
⎯
⎯
tCLKT / 2
⎯
⎯
tCLKT / 2
⎯
tCLWRL
⎯
WRnX
CSnX
tWRHCH
Unit
ns
VOH
CSnX
VOL
tWRHCH
tCLWRL
tWRLWRH
WRnX
VOH
VOL
tDSWRL
DATA output
120
tWRHDH
VOH
VOH
VOL
VOL
DS07-16613-3E
MB91460M Series
6.7.7.
RDY wait cycle insertion
(Vcc3 = 3.3 V ±10%, Vss = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
RDY setup time
tRDYS
RDY hold time
tRDYH
SYSCLK
Value
Unit
Min
Max
SYSCLK
RDY
40
⎯
ns
SYSCLK
RDY
0
⎯
ns
VOH
tRDYS
RDY
tRDYH
VIH
VIL
DS07-16613-3E
121
MB91460M Series
6.7.8.
Bus hold timing
(Vcc3 = 3.3 V ±10%, Vss = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
SYSCLK ↓ →BGRNTX
delay
Symbol
Pin name
tCLBGL
SYSCLK
BGRNTX
tCLBGH
tAXBGL
Bus High-Z→BGRNTX ↓
tBGHAV
Condition
Value
Min
Typ
2 × tCLKT
⎯
BGRNTX
MCLKE,
MCLKI
A23 to A00
RDX, ASX
WRnX,
WEX
CSnX,
BAAX
2 × tCLKT
⎯
Unit
Max
⎯
tCLKT
⎯
ns
⎯
⎯
tCLKT
Note: Keep BRQ high until bus is enabled (recognized by the falling edge of BGRNTX). Keep BRQ high during
the bus retention period.
The rising edge of BGRNTX recognizes whether bus is enabled after releasing the bus (setting BRQ to Low).
VOH
SYSCLK
VOL
VOL
VOL
BRQ
tCLBGL
VOH
BGRNTX
VOL
tAXBGL
A23 to A00, RDX,
WRnX, WEX,
CSnX, ASX,
MCLKE, MCLKI,
BAAX
122
tCLBGH
tBGHAV
VOH
VOH
VOL
VOL
DS07-16613-3E
MB91460M Series
6.7.9.
Correlation of clock
(Vcc3 = 3.3 V ±10%, Vss = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
MCLKO ↓ →MCLKE
(sleep mode)
Symbol
Pin name
Condition
tCLML
MCLKO
MCLKE
⎯
tCLMH
Value
Min
Typ
Max
⎯
3
⎯
⎯
3
⎯
Unit
ns
MCLKO
VOL
VOL
tCLML
tCLMH
MCLKE (sleep)
VOH
VOL
6.7.10. DMA transfer
(Vcc3 = 3.3 V ±10%, Vss = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
SYSCLK ↓ →DACKX0 delay
SYSCLK ↓ →DEOP0 delay
Symbol
tCLDAL
tCLDAH
tCLDEL
tCLDEH
Pin name
Condition
Value
Min
Typ
Max
SYSCLK
DACKX0
⎯
3
⎯
⎯
3
⎯
SYSCLK
DEOP0
⎯
3
⎯
⎯
3
⎯
⎯
3
⎯
⎯
3
⎯
SYSCLK ↑ →DACKX0 delay
(when using CS delay
function)
tCHDAL
SYSCLK
DACKX0
SYSCLK ↑ →DEOP0 delay
(when using CS delay
function)
tCHDEL
SYSCLK
DEOP0
DREQ0 SETUP
tDRQS
SYSCLK
DREQ0
⎯
40
⎯
DREQ0 hold
tDRQH
SYSCLK
DREQ0
⎯
0
⎯
DEOTX0 SETUP
tDTXS
SYSCLK
DEOTX0
⎯
40
⎯
DEOTX0 hold
tDTXH
SYSCLK
DEOTX0
⎯
0
⎯
DS07-16613-3E
⎯
Unit
ns
123
MB91460M Series
SYSCLK
VOH
VOH
VOL
VOL
tCLDAL
tCLDAH
VOH
DACKX0
VOL
tCLDEH
tCLDEL
VOH
DEOP0
VOL
tCHDAL
Delay DACKX0
VOL
tCHDEL
Delay DEOP0
VOL
tDRQS
DREQ0
tDRQH
VIH
VIL
tDTXS
DEOTX0
tDTXH
VIH
VIL
124
DS07-16613-3E
MB91460M Series
■ ORDERING INFORMATION
Part number
MB91F467MAPMC-GSE2
MB91F467MAPMC-GSE1
DS07-16613-3E
Package
216-pin plastic QFP
(FPT-216P-M01)
Remarks
Lead-free package
125
MB91460M Series
■ PACKAGE DIMENSION
216-pin plastic LQFP
Lead pitch
0.40 mm
Package width ×
package length
24.0 × 24.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LFQFP216-24×24-0.40
(FPT-216P-M01)
216-pin plastic LQFP
(FPT-216P-M01)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
26.00±0.20(1.024±.008)SQ
* 24.00±0.10(.945±.004)SQ
162
109
163
108
Details of "A" part
+0.20
1.50 –0.10
0.08(.003)
+.008
.059 –.004
(Mounting height)
0.25(.010)
0~8°
INDEX
216
0.60±0.15
(.024±.006)
55
"A"
LEAD No.
1
54
0.40(.016)
C
0.10±0.05
(.004±.002)
(Stand off)
0.18±0.05
(.007±.002)
0.07(.003)
M
0.145±0.055
(.006±.002)
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F216001S-c-2-4
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
126
DS07-16613-3E
MB91460M Series
■ MAIN CHANGES IN THIS EDITION
Page
83
Section
Change Results
■ INTERRUPT VECTOR TABLE Corrected the column of interrupt and RN in interrupt number 89 to 91
as follows;
Interrupt: I2S EVEN→ I2S ERROR / RN: 125 → None
Interrupt: I2S ODD→I2S EVEN / RN: 126 → 125
Interrupt: I2S error→ I2S ODD / RN: None →126
The vertical lines marked in the left side of the page show the changes.
DS07-16613-3E
127
MB91460M Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
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Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not
warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device
based on such information, you must assume any responsibility arising out of such use of the information.
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right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property
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The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
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The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department