PEMD48; PUMD48 NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k and R1 = 2.2 k, R2 = 47 k Rev. 6 — 24 January 2012 Product data sheet 1. Product profile 1.1 General description NPN/PNP double Resistor-Equipped Transistors (RET) in small Surface-Mounted Device (SMD) plastic packages. Table 1. Product overview Type number Package NXP JEITA Package configuration PEMD48 SOT666 - ultra small and flat lead PUMD48 SOT363 SC-88 very small 1.2 Features and benefits 100 mA output current capability Built-in bias resistors Simplifies circuit design Reduces component count Reduces pick and place costs AEC-Q101 qualified 1.3 Applications Low current peripheral driver Control of IC inputs Replaces general-purpose transistors in digital applications 1.4 Quick reference data Table 2. Symbol Quick reference data Parameter Conditions Min Typ Max Unit - - 50 V - - 100 mA k Per transistor; for the PNP transistor with negative polarity VCEO collector-emitter voltage IO output current open base Transistor TR1 (NPN) R1 bias resistor 1 (input) 33 47 61 R2/R1 bias resistor ratio 0.8 1.0 1.2 Transistor TR2 (PNP) R1 bias resistor 1 (input) 1.54 2.20 2.86 R2/R1 bias resistor ratio 17 21 26 k PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors 2. Pinning information Table 3. Pinning Pin Description Simplified outline Graphic symbol PEMD48 (SOT666) 1 GND (emitter) TR1 2 input (base) TR1 3 output (collector) TR2 4 GND (emitter) TR2 5 input (base) TR2 6 6 5 4 6 5 R1 4 R2 TR2 1 output (collector) TR1 2 TR1 3 R2 1 R1 2 3 006aaa143 PUMD48 (SOT363) 1 GND (emitter) TR1 2 input (base) TR1 3 output (collector) TR2 4 GND (emitter) TR2 5 input (base) TR2 6 output (collector) TR1 6 5 4 6 5 R1 1 2 3 4 R2 TR2 TR1 R2 1 R1 2 3 006aaa143 3. Ordering information Table 4. Ordering information Type number Package Name Description Version PEMD48 - plastic surface-mounted package; 6 leads SOT666 PUMD48 SC-88 plastic surface-mounted package; 6 leads SOT363 4. Marking Table 5. Type number Marking code[1] PEMD48 48 PUMD48 4*8 [1] PEMD48_PUMD48 Product data sheet Marking codes * = placeholder for manufacturing site code. All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 January 2012 © NXP B.V. 2012. All rights reserved. 2 of 16 PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors 5. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per transistor; for the PNP transistor with negative polarity VCBO collector-base voltage open emitter - 50 V VCEO collector-emitter voltage open base - 50 V VEBO emitter-base voltage open collector TR1 (NPN) - 10 V TR2 (PNP) - 5 V positive - +40 V negative - 10 V positive - +5 V negative - 12 V IO output current - 100 mA ICM peak collector current - 100 mA Ptot total power dissipation input voltage TR1 VI input voltage TR2 Tamb 25 C PEMD48 (SOT666) [1][2] - 200 mW PUMD48 (SOT363) [1] - 200 mW PEMD48 (SOT666) [1][2] - 300 mW PUMD48 (SOT363) [1] - 300 mW Per device total power dissipation Ptot PEMD48_PUMD48 Product data sheet Tamb 25 C Tj junction temperature - 150 C Tamb ambient temperature 65 +150 C Tstg storage temperature 65 +150 C [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. [2] Reflow soldering is the only recommended soldering method. All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 January 2012 © NXP B.V. 2012. All rights reserved. 3 of 16 PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors 006aac749 400 Ptot (mW) 300 200 100 0 -75 -25 25 75 125 175 Tamb (°C) SOT363 and SOT666; FR4 PCB, standard footprint Fig 1. Per device: Power derating curve 6. Thermal characteristics 006aac751 103 duty cycle = 1 Zth(j-a) (K/W) 0.75 0.5 0.33 0.2 102 0.1 0.05 0.02 10 0.01 0 1 10-5 10-4 10-3 10-2 10-1 1 10 102 103 tp (s) FR4 PCB, standard footprint Fig 2. Transient thermal impedance from junction to ambient as a function of pulse duration for PEMD48 (SOT666); typical values PEMD48_PUMD48 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 January 2012 © NXP B.V. 2012. All rights reserved. 4 of 16 PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors 006aac750 103 duty cycle = 1 Zth(j-a) (K/W) 0.75 0.5 0.33 0.2 102 0.1 0.05 0.02 10 0.01 0 1 10-5 10-4 10-3 10-2 10-1 1 102 10 103 tp (s) FR4 PCB, standard footprint Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration for PUMD48 (SOT363); typical values Table 7. Symbol Thermal characteristics Parameter Conditions Min Typ Max Unit Per transistor Rth(j-a) thermal resistance from junction to ambient Tamb 25 C PEMD48 (SOT666) [1][2] - - 625 K/W PUMD48 (SOT363) [1] - - 625 K/W PEMD48 (SOT666) [1][2] - - 417 K/W PUMD48 (SOT363) [1] - - 417 K/W Per device Rth(j-a) PEMD48_PUMD48 Product data sheet thermal resistance from junction to ambient Tamb 25 C [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [2] Reflow soldering is the only recommended soldering method. All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 January 2012 © NXP B.V. 2012. All rights reserved. 5 of 16 PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors 7. Characteristics Table 8. Characteristics Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Per transistor; for the PNP transistor with negative polarity ICBO collector-base cut-off current VCB = 50 V; IE = 0 A - - 100 nA ICEO collector-emitter cut-off current VCE = 30 V; IB = 0 A - - 1 A VCE = 30 V; IB = 0 A; Tj = 150 C - - 5 A - - 90 A Transistor TR1 (NPN) IEBO emitter-base cut-off current VEB = 5 V; IC = 0 A hFE DC current gain VCE = 5 V; IC = 5 mA 80 - - VCEsat collector-emitter saturation voltage IC = 10 mA; IB = 0.5 mA - - 150 mV VI(off) off-state input voltage VCE = 5 V; IC = 100 A - 1.2 0.8 V VCE = 0.3 V; IC = 2 mA VI(on) on-state input voltage 3 1.6 - V R1 bias resistor 1 (input) 33 47 61 k R2/R1 bias resistor ratio 0.8 1.0 1.2 Cc collector capacitance VCB = 10 V; IE = ie = 0 A; f = 1 MHz - - 2.5 pF fT transition frequency VCB = 5 V; IC = 10 mA; f = 100 MHz - 230 - MHz A [1] Transistor TR2 (PNP) IEBO emitter-base cut-off current VEB = 5 V; IC = 0 A - - 180 hFE DC current gain VCE = 5 V; IC = 10 mA 100 - - VCEsat collector-emitter saturation voltage IC = 5 mA; IB = 0.25 mA - - 100 mV VI(off) off-state input voltage VCE = 5 V; IC = 100 A - 0.6 0.5 V VI(on) on-state input voltage VCE = 0.3 V; IC = 5 mA 1.1 0.75 - V R1 bias resistor 1 (input) 1.54 2.20 2.86 k R2/R1 bias resistor ratio 17 21 26 Cc collector capacitance VCB = 10 V; IE = ie = 0 A; f = 1 MHz - - 3 pF fT transition frequency VCB = -5 V; IC = -10 mA; f = 100 MHz - 180 - MHz [1] PEMD48_PUMD48 Product data sheet [1] Characteristics of built-in transistor. All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 January 2012 © NXP B.V. 2012. All rights reserved. 6 of 16 PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors 006aac752 103 hFE 006aac753 1 (1) VCEsat (V) (2) (3) 102 (1) (2) 10-1 (3) 10 1 10-1 1 102 10 10-2 10-1 1 IC (mA) VCE = 5 V IC/IB = 20 (1) Tamb = 100 C (1) Tamb = 100 C (2) Tamb = 25 C (2) Tamb = 25 C (3) Tamb = 40 C (3) Tamb = 40 C Fig 4. TR1 (NPN): DC current gain as a function of collector current; typical values Fig 5. 006aac754 10 TR1 (NPN): Collector-emitter saturation voltage as a function of collector current; typical values 006aac755 10 VI(off) (V) VI(on) (V) (1) (1) (2) (2) (3) 1 10-1 10-1 1 (3) 1 102 10 10-1 10-1 IC (mA) VCE = 0.3 V (2) Tamb = 25 C (2) Tamb = 25 C (3) Tamb = 100 C (3) Tamb = 100 C TR1 (NPN): On-state input voltage as a function of collector current; typical values Product data sheet 10 VCE = 5 V (1) Tamb = 40 C PEMD48_PUMD48 1 IC (mA) (1) Tamb = 40 C Fig 6. 102 10 IC (mA) Fig 7. TR1 (NPN): Off-state input voltage as a function of collector current; typical values All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 January 2012 © NXP B.V. 2012. All rights reserved. 7 of 16 PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors 006aac756 2.0 006aac757 103 Cc (pF) 1.6 fT (MHz) 1.2 102 0.8 0.4 10 10-1 0.0 0 10 20 30 40 50 VCB (V) 102 10 IC (mA) f = 1 MHz; Tamb = 25 C Fig 8. 1 VCE = 5 V; Tamb = 25 C TR1 (NPN): Collector capacitance as a function of collector-base voltage; typical values 006aac814 103 Fig 9. TR1 (NPN): Transition frequency as a function of collector current; typical values of built-in transistor 006aac815 -1 (1) hFE (2) VCEsat (V) (3) 102 -10-1 (1) 10 (2) (3) 1 -10-1 -1 -102 -10 -10-2 -10-1 IC (mA) VCE = 5 V IC/IB = 20 (1) Tamb = 100 C (2) Tamb = 25 C (2) Tamb = 25 C (3) Tamb = 40 C (3) Tamb = 40 C Fig 10. TR2 (PNP): DC current gain as a function of collector current; typical values Product data sheet -102 -10 IC (mA) (1) Tamb = 100 C PEMD48_PUMD48 -1 Fig 11. TR2 (PNP): Collector-emitter saturation voltage as a function of collector current; typical values All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 January 2012 © NXP B.V. 2012. All rights reserved. 8 of 16 PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors 006aac816 -10 006aac817 -1 (1) (2) VI(on) (V) VI(off) (V) (3) (1) -1 (2) (3) -10-1 -10-1 -1 -102 -10 -10-1 -10-1 -1 IC (mA) -10 IC (mA) VCE = 0.3 V VCE = 5 V (1) Tamb = 40 C (1) Tamb = 40 C (2) Tamb = 25 C (2) Tamb = 25 C (3) Tamb = 100 C (3) Tamb = 100 C Fig 12. TR2 (PNP): On-state input voltage as a function of collector current; typical values 006aac818 9 Cc (pF) Fig 13. TR2 (PNP): Off-state input voltage as a function of collector current; typical values 006aac763 103 fT (MHz) 6 102 3 0 0 -10 -20 -30 -40 -50 VCB (V) f = 1 MHz; Tamb = 25 C Product data sheet -1 -102 -10 IC (mA) VCE = 5 V; Tamb = 25 C Fig 14. TR2 (PNP): Collector capacitance as a function of collector-base voltage; typical values PEMD48_PUMD48 10 -10-1 Fig 15. TR2 (PNP): Transition frequency as a function of collector current; typical values of built-in transistor All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 January 2012 © NXP B.V. 2012. All rights reserved. 9 of 16 PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors 8. Test information 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. 9. Package outline 1.7 1.5 6 2.2 1.8 0.6 0.5 5 6 4 1.1 0.8 5 4 2 3 0.45 0.15 0.3 0.1 1.7 1.5 2.2 1.35 2.0 1.15 1.3 1.1 pin 1 index 1 2 1 3 0.18 0.08 0.27 0.17 0.5 04-11-08 Fig 16. Package outline PEMD48 (SOT666) Product data sheet 0.3 0.2 0.65 0.25 0.10 1.3 1 Dimensions in mm PEMD48_PUMD48 pin 1 index Dimensions in mm 06-03-16 Fig 17. Package outline PUMD48 (SOT363/SC-88) All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 January 2012 © NXP B.V. 2012. All rights reserved. 10 of 16 PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors 10. Packing information Table 9. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description PEMD48 SOT666 PUMD48 [1] SOT363 Packing quantity 3000 4000 8000 10000 2 mm pitch, 8 mm tape and reel - - -315 - 4 mm pitch, 8 mm tape and reel - -115 - - 4 mm pitch, 8 mm tape and reel; T1 [2] -115 - - -135 4 mm pitch, 8 mm tape and reel; T2 [3] -125 - - -165 For further information and the availability of packing methods, see Section 14. [2] T1: normal taping [3] T2: reverse taping 11. Soldering 2.75 2.45 2.1 1.6 solder lands 0.4 (6×) 0.25 (2×) 0.538 2 1.7 1.075 0.3 (2×) 0.55 (2×) placement area solder paste occupied area 0.325 0.375 (4×) (4×) Dimensions in mm 1.7 0.45 (4×) 0.6 (2×) 0.5 (4×) 0.65 (2×) sot666_fr Reflow soldering is the only recommended soldering method. Fig 18. Reflow soldering footprint PEMD48 (SOT666) PEMD48_PUMD48 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 January 2012 © NXP B.V. 2012. All rights reserved. 11 of 16 PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors 2.65 solder lands 2.35 1.5 0.4 (2×) 0.6 0.5 (4×) (4×) solder resist solder paste 0.5 (4×) 0.6 (2×) occupied area 0.6 (4×) Dimensions in mm 1.8 sot363_fr Fig 19. Reflow soldering footprint PUMD48 (SOT363/SC-88) 1.5 solder lands 0.3 2.5 4.5 solder resist occupied area 1.5 Dimensions in mm 1.3 1.3 preferred transport direction during soldering 2.45 5.3 sot363_fw Fig 20. Wave soldering footprint PUMD48 (SOT363/SC-88) PEMD48_PUMD48 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 January 2012 © NXP B.V. 2012. All rights reserved. 12 of 16 PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors 12. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes PEMD48_PUMD48 v.6 20120124 Product data sheet - PEMD48_PUMD48 v.5 Modifications: • • • • • • • • • • Section 1 “Product profile”: updated Section 4 “Marking”: updated Table 7 “Thermal characteristics”: updated according to the latest measurements Table 6 “Limiting values”: updated according to the latest measurements Table 8 “Characteristics”: ICEO updated according to the latest measurements, fT added Figure 1 to 3, 8, 9, 14 and 15: added Figure 4 to 7 and Figure 10 to 13: updated Section 8 “Test information”: added Section 11 “Soldering”: added Section 13 “Legal information”: updated PEMD48_PUMD48 v.5 20100413 Product data sheet - PEMD48_PUMD48 v.4 PEMD48_PUMD48 v.4 20040624 Product specification - PEMD48_PUMD48 v.3 PEMD48_PUMD48 v.3 20040602 Product specification - PEMD48 v.2 PUMD48 v.2 PUMD48 v.2 20010201 Product specification PUMD48 v.1 PUMD48 v.1 19990422 Product specification - PEMD48 v.2 20011107 Product specification PEMD48 v.1 PEMD48 v.1 20010924 Preliminary specification - - PEMD48_PUMD48 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 January 2012 © NXP B.V. 2012. All rights reserved. 13 of 16 PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 13.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PEMD48_PUMD48 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 January 2012 © NXP B.V. 2012. All rights reserved. 14 of 16 PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PEMD48_PUMD48 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 24 January 2012 © NXP B.V. 2012. All rights reserved. 15 of 16 PEMD48; PUMD48 NXP Semiconductors NPN/PNP resistor-equipped transistors 15. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test information . . . . . . . . . . . . . . . . . . . . . . . . 10 Quality information . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Packing information . . . . . . . . . . . . . . . . . . . . 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 24 January 2012 Document identifier: PEMD48_PUMD48