Specifications CD54AC299/3A, CD54ACT299/3A Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current, Per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or GND Current, ICC or IGND For Up to 4 Outputs Per Device, Add ±25mA For Each Additional Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±100mA Power Dissipation Per Package, PD TA = -55oC to +100oC (Package F) . . . . . . . . . . . . . . . . . . 500mW TA = +100oC to +125oC (Package F) . . . . . . . . Derate Linearly at 8mW/ oC to 300mW Operating Temperature Range, TA Package Type F . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Storage Temperature, TSTG . . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) At Distance 1/16in. ± 1/32in. (1.59mm ± 0.79mm) From Case For 10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC Unit Inserted Into a PC Board (Min Thickness 1/16in., 1.59mm) With Solder Contacting Lead Tips Only. . . . . . . . . . . . . . . +300oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions Operating Temperature, TA . . . . . . . . . . . . . . . . . . . -55oC to +125oC Input Rise and Fall Slew Rate, dt/dv at 1.5V to 3V (AC Types) . . . . . . . . . . . . . . . . . . . 0ns/V to 50ns/V at 3.6V to 5.5V (AC Types) . . . . . . . . . . . . . . . . . 0ns/V to 20ns/V at 4.5V to 5.5V (AC Types) . . . . . . . . . . . . . . . . . 0ns/V to 10ns/V Supply Voltage Range, VCC Unless Otherwise Specified, All Voltages Referenced to GND TA = Full Package Temperature Range CD54AC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V CD54ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . . 0V to VCC 2 CD54AC299/3A CD54ACT299/3A S E M I C O N D U C T O R June 1997 COMPLETE DATA SHEET 8-Input Universal Shift/Storage Registers COMING SOON! with Common Parallel I/O Pins Description The CD54AC299/3A and CD54ACT299/3A are three-state, 8-input universal shift/storage registers with common parallel I/O pins. These devices utilize the Harris Advanced CMOS Logic technology. These registers have four synchronous operating modes controlled by the two select inputs as shown in the Mode Select (S0, S1) table. The Mode Select, the Serial Data (DS0, DS7), and the Parallel Data (I/O0 - I/O7) respond only to the LOW-to-HIGH transition of the clock pulse (CP). S0, S1 and Data inputs must be present one setup time prior to the positive transition of the clock. 2. When both S0 and S1 are HIGH, I/O terminals are in the high-impedance state but being input ports, ready for parallel data to be loaded into eight registers with one clock transition regardless of the status of OE1 and OE2. 3. Either one of the two Output Enable inputs being HIGH will force I/O terminals to be in the off state. It is noted that each I/O terminal is a three-state output and a CMOS buffer input. The CD54AC299/3A and CD54ACT299/3A are supplied in 20 lead dual-in-line ceramic packages (F suffix). The Master Reset (MR) is an asynchronous active-LOW input. When MR is LOW, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (QO) to the serial data (DS7) input of the preceding register, and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage. ACT INPUT LOAD TABLE INPUT UNIT LOAD (NOTE 1) S1, S2, OE1, OE2 0.83 SL, CP 0.67 MR 1.33 NOTE: 1. Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA Max at +25oC. The three-state input/output (I/O) port has three modes of operation 1. Both Output Enable (OE1 and OE2) inputs are LOW and S0 or S1 or both are LOW, the data in the register is present at the eight outputs. Functional Diagram CP OE1 OE2 MR 12 2 3 9 THREE-STATE CONTROL I/O0 BUS LINE OUTPUTS STANDARD OUTPUT 7 I/O THREE-STATE OUTPUTS SHIFT REGISTER I/O THREE-STATE OUTPUTS VCC 13 I/O1 I/O2 6 14 I/O3 I/O4 5 15 I/O5 I/O6 4 16 I/O7 Q0 8 17 Q7 S0 1 19 S1 MODE SELECTION 10 11 18 GND DS0 DS7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright 20 © Harris Corporation 1994 1 BUS LINE OUTPUTS STANDARD OUTPUT File Number 3907