DM54LS323/DM74LS323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins General Description Features The ’LS323 is an 8-bit universal shift/storage register with TRI-STATEÉ outputs. Its function is similar to the ’LS299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate inputs and outputs are provided for flipflops Q0 and Q7 to allow easy cascading. Four operation modes are possible: hold (store), shift left, shift right, and parallel load. All modes are activated on the LOW-to-HIGH transition of the Clock. Y Y Y Y Y Common I/O for reduced pin count Four operation modes: shift left, shift right, parallel load and store Separate continuous inputs and outputs from Q0 and Q7 allow easy cascading Fully synchronous reset TRI-STATE outputs for bus oriented applications Connection Diagram Dual-In-Line Package TL/F/9829 – 1 Order Number DM54LS323J, DM54LS323W, DM74LS323WM or DM74LS323N See NS Package Number J20A, M20B, N20A or W20A Pin Names Description CP DS0 DS7 S0, S1 SR OE1, OE2 I/O0–I/O7 Clock Pulse Input (Active Rising Edge) Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Synchronous Reset Input (Active LOW) TRI-STATE Output Enable Inputs (Active LOW) Parallel Data Inputs or TRI-STATE Parallel Outputs Serial Outputs Q0, Q7 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9829 RRD-B30M115/Printed in U. S. A. DM54LS323/DM74LS323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins April 1992 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54LS DM74LS 0§ C to a 70§ C b 65§ C to a 150§ C Storage Temperature Range Recommended Operating Conditions Symbol DM54LS323 Parameter DM74LS323 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current TA Free Air Operating Temperature ts (H) ts (L) Setup Time HIGH or LOW S0 or S1 to CP 24 24 24 24 ns th (H) th (L) Hold Time HIGH or LOW S0 or S1 to CP 5 5 0 0 ns ts (H) ts (L) Setup Time HIGH or LOW I/On, DS0, DS7 to CP 15 15 10 10 ns th (H) th (L) Hold Time HIGH or LOW I/On, DS0, DS7 to CP 5 5 0 0 ns ts (H) ts (L) Setup Time HIGH or LOW SR to CP 30 20 15 15 ns th (H) th (L) Hold Time HIGH or LOW SR to CP 0 0 0 0 ns tw (H) tw (L) CP Pulse Width HIGH or LOW 15 15 15 15 ns 2 2 0.7 0.8 V b 0.4 mA 8 mA 70 §C 125 2 V b 0.4 4 b 55 V 0 Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ (Note 1) Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max Low Level Output Voltage VCC e Min, IOL e Max VIH e Min DM74 0.35 0.5 IOL e 4 mA, VCC e Min DM74 0.25 0.4 Input Current @ Max Input Voltage VCC e Max, VI e 7V VI e 10V (DM54) Others 0.1 mA Sn Inputs 0.2 mA High Level Input Current VCC e Max, VI e 2.7V Others 20 mA Sn Inputs 40 mA Others b 0.4 mA Sn Inputs b 0.8 mA VOL II IIH IIL IOS Low Level Input Current DM54 2.5 DM74 2.7 V 3.4 DM54 VCC e Max, VI e 0.4V 0.4 DM54 b 20 b 100 DM74 b 20 b 100 V Short Circuit Output Current VCC e Max (Note 2) ICC Supply Current VCC e Max 60 mA IOZH TRI-STATE Output Off Current HIGH VCC e Max VO e 2.7V 40 mA IOZL TRI-STATE Output Off Current LOW VCC e Max VO e 0.4V b 400 mA mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics VCC e a 5.0V, TA e a 25§ C Symbol Parameter DM54LS323 DM74LS323 CL e 15 pF RL e 2 kX, CL e 15 pF Min Max 35 Min Units Max fmax Maximum Input Frequency tPLH tPHL Propagation Delay CP to Q0 or Q7 26 28 35 23 25 ns tPLH tPHL Propagation Delay CP to I/On 25 35 25 29 ns tPZH tPZL Output Enable Time CL e 50 pF 18 25 18 23 ns tPHZ tPLZ Output Disable Time CL e 5 pF 15 20 15 15 ns 3 MHz Functional Description The ’LS323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through TRI-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All other state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the TRISTATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, load, hold and reset operations can still occur. The TRI-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. Mode Select Table Inputs Response SR S1 S0 CP L H H H H X H L H H X H H L H L L L L X Synchronous Reset; Q0 – Q7 e LOW Parallel Load; I/On x Qn Shift Right; DS0 x Q0, Q0 x Q1, etc. Shift Left; DS7 x Q7, Q7 x Q6, etc. Hold H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Logic Symbol VCC e Pin 20 TL/F/9829 – 2 GND e Pin 10 4 TL/F/9829 – 3 Logic Diagram 5 Physical Dimensions inches (millimeters) 20-Lead Ceramic Dual-In-Line Package (J) Order Number DM54LS323J NS Package Number J20A 20-Lead Wide Small Outline Molded Package (M) Order Number DM74LS323WM NS Package Number M20B 6 Physical Dimensions inches (millimeters) (Continued) 20-Lead Molded Dual-In-Line Package (N) Order Number DM74LS323N NS Package Number N20A 7 DM54LS323/DM74LS323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Flat Package (W) Order Number DM54LS323W NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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