HS-303ARH ® Data Sheet December 14, 2006 Radiation Hardened CMOS Dual SPDT Analog Switch Features • QML, Per MIL-PRF-38535 The HS-303ARH analog switch is a monolithic device fabricated using Intersil’s dielectrically isolated Radiation Hardened Silicon Gate (RSG) process technology to insure latch-up free operation. It is pinout compatible and functionally equivalent to the HS-303RH, but offers improved 300kRAD(Si) total dose capability. This switch offers lowresistance switching performance for analog voltages up to the supply rails. “ON” resistance is low and stays reasonably constant over the full range of operating voltage and current. “ON” resistance also stays reasonably constant when exposed to radiation, being typically 29Ω pre-rad and 34Ω post-300kRAD(Si). Break-before-make switching is controlled by 5V digital inputs. Specifications • Radiation Performance - Total Dose: 3 x 105 RAD(Si) - SEE: For LET = 60MeV-mg/cm2 at 60° Incident Angle, <150pC Charge Transferred to the Output of an Off Switch • No Latch-Up, Dielectrically Isolated Device Islands • Pinout and Functionally Compatible with Intersil HS-303RH and HI-303 Series Analog Switches • Analog Signal Range 15V • Low Leakage . . . . . . . . . . . . . . . . 100nA (Max, Post-Rad) • Low rON . . . . . . . . . . . . . . . . . . . . . . 60Ω (Max, Post-Rad) • Low Standby Supply Current . . . . . . . . . . +150μA/-100μA (Max, Post-Rad) Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Pinouts HS1-303ARH (SBDIP), CDIP2-T14 TOP VIEW Detailed Electrical Specifications for the HS-303ARH are contained in SMD 5962-95813. A “hot-link” is provided from our website for downloading Ordering Information ORDERING NUMBER PART NUMBER TEMP. RANGE (°C) PKG. 14 LD SBDIP 5962F9581304QCC HS1-303ARH-8 -55 to +125 5962F9581304QXC HS9-303ARH-8 -55 to +125 5962F9581304V9A HS0-303ARH-Q -55 to +125 5962F9581304VCC HS1-303ARH-Q -55 to +125 5962F9581304VXC HS9-303ARH-Q HS0-303ARH/PROTO HS0-303ARH/SAMPLE HS1-303ARH/PROTO HS1-303ARH/PROTO HS9-303ARH/PROTO HS9-303ARH/PROTO 1 -55 to +125 NC 1 14 V+ S3 2 13 S4 D3 3 12 D4 D1 4 11 D2 PKG. DWG. # S1 5 10 S2 D14.3 IN1 6 9 IN2 GND 7 8 V- 14 LD K14.A Flatpack HS9-303ARH (FLATPACK) CDFP3-F14 TOP VIEW 14 LD SBDIP D14.3 NC 14 LD K14.A Flatpack S3 D3 -55 to +125 D1 -55 to +125 IN1 -55 to +125 FN6411.0 S1 14 LD SBDIP D14.3 GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 V+ S4 D4 D2 S2 IN2 V- 14 LD K14.A Flatpack CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HS-303ARH Functional Diagram SBDIP TRUTH TABLE N IN P LOGIC SW1 AND SW2 SW3 AND SW4 0 OFF ON 1 ON OFF D Die Characteristics DIE DIMENSIONS: Backside Finish: 2690μm x 5200μm (106 mils x 205 mils) Thickness: 483μm ± 25.4μm (19 mils ± 1 mil) INTERFACE MATERIALS: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Glassivation: Unbiased (DI) Type: PSG (Phosphorous Silicon Glass) Thickness: 8.0kÅ ± 1.0kÅ ADDITIONAL INFORMATION: Worst Case Current Density: Top Metallization: <2.0 x 105 A/cm2 Type: AlSiCu Thickness: 16.0kÅ ± 2kÅ Transistor Count: 196 Substrate: Radiation Hardened Silicon Gate, Dielectric Isolation Metallization Mask Layout IN2 S2 D2 D4 S4 HS-303ARH VV+ IN1 S1 D1 D3 S3 GND All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 2 FN6411.0 December 14, 2006