INTERSIL HS9-302EH-Q

Radiation Hardened CMOS Dual DPST Analog Switch
HS-302RH, HS-302EH
Features
Intersil’s Satellite Applications Flow™ (SAF) devices are fully
tested and guaranteed to 100kRAD Total Dose. These QML
Class T devices are processed to a standard flow intended to
meet the cost and shorter lead-time needs of large volume
satellite manufacturers, while maintaining a high level of
reliability.
• QML Class T, Per MIL-PRF-38535
The HS-302RH, HS-302EH analog switch is a monolithic device
fabricated using Radiation Hardened CMOS technology and
the Intersil dielectric isolation process for latch-up free
operation. Improved total dose hardness is obtained by layout
(thin oxide tabs extending to a channel stop) and processing
(hardened gate oxide). These switches offer low-resistance
switching performance for analog voltages up to the supply
rails. “ON” resistance is low and stays reasonably constant
over the full range of operating voltage and current. “ON”
resistance also stays reasonably constant when exposed to
radiation, being typically 30Ω pre-rad and 35Ω post
100kRAD(Si). This device provide break-before-make
switching.
• Radiation Performance
- Gamma Dose (γ) 1 x 105 RAD(Si)
• No Latch-Up, Dielectrically Isolated Device Islands
• Pin for Pin Compatible with Intersil HI-302 Series Analog
Switches
• Analog Signal Range 15V
• Low Leakage. . . . . . . . . . . . . . . . . . . . . 100nA (Max, Post Rad)
• Low RON . . . . . . . . . . . . . . . . . . . . . . . . . . 60Ω (Max, Post Rad)
• Low Operating Power. . . . . . . . . . . . . .100µA (Max, Post Rad)
Pin Configurations
HS1-302RH, HS1-302EH
(SBDIP), CDIP2-T14
TOP VIEW
Specifications
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed below must be used when ordering.
NC 1
14 V+
S3 2
13 S4
D3 3
12 D4
D1 4
11 D2
S1 5
10 S2
IN1 6
Detailed Electrical Specifications for the HS-302RH, HS-302EH
are contained in SMD# 5962-95812.
GND 7
9 IN2
8 V-
Functional Diagram
HS9-302RH, HS9-302EH
(FLATPACK), CDFP3-F14
TOP VIEW
N
IN
P
NC
D
S3
D3
D1
TRUTH TABLE
LOGIC
April 1, 2013
FN4603.2
S1
ALL SWITCHES
0
OFF
1
ON
1
IN1
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
V+
S4
D4
D2
S2
IN2
V-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) and Satellite Applications Flow™ (SAF) are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HS-302RH, HS-302EH
Ordering Information
ORDERING NUMBER
PART NUMBER
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
5962R9581201V9A
HS0-302RH-Q
-55 to +125
Die
N/A
5962R9581202V9A
HS0-302EH-Q
-55 to +125
Die
N/A
5962R9581201QCC
HS1-302RH-8
-55 to +125
14 Ld SBDIP
D14.3
5962R9581201VCC
HS1-302RH-Q
-55 to +125
14 Ld SBDIP
D14.3
5962R9581202VCC
HS1-302EH-Q
-55 to +125
14 Ld SBDIP
D14.3
5962R9581201QXC
HS9-302RH-8
-55 to +125
Flatpack
K14.A
5962R9581201VXC
HS9-302RH-Q
-55 to +125
Flatpack
K14.A
5962R9581202VXC
HS9-302EH-Q
-55 to +125
Flatpack
K14.A
HS9-302RH/PROTO
HS9-302RH/PROTO
-55 to +125
Flatpack
K14.A
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
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FN4603.2
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HS-302RH, HS-302EH
Die Characteristics
BACKSIDE FINISH:
Silicon
DIE DIMENSIONS:
PASSIVATION:
(2130µm x 1930µm x 533µm ±25.4µm)
Type: Silox (SiO2)
84 x 76 x 21mils ±1mil
Thickness: 8kÅ ±1kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Type: Al
< 2.0e5 A/cm2
Thickness: 12.5kÅ ±2kÅ
TRANSISTOR COUNT:
SUBSTRATE POTENTIAL:
76
Unbiased (DI)
PROCESS:
Metal Gate CMOS, Dielectric Isolation
Metallization Mask Layout
S4
S3
V+
HS-302RH, HS-302EH
D2
S1
S2
IN1
IN2
V-
D1
GND
D4
NC
D3
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Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN4603.2
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