INTERSIL ISL21007

ISL21007
®
Data Sheet
December 13, 2007
Precision, Low Noise FGA™Voltage
References
Features
The ISL21007 FGA™ voltage references are extremely low
power, high precision, and low noise voltage references
fabricated on Intersil’s proprietary Floating Gate Analog
technology. The ISL21007 features very low noise (4.5µVP-P
for 0.1Hz to 10Hz) and very low operating current (150µA,
Max). In addition, the ISL21007 family features guaranteed
initial accuracy as low as ±0.5mV.
This combination of high initial accuracy, low drift, and low
output noise performance of the ISL21007 enables versatile
high performance control and data acquisition applications
with low power consumption.
• Reference Output Voltage . . . . . .1.250V, 2.048V, 2.500V,
3.000V
• Initial Accuracy . . . . . . . . . . . . . . . . . . . . ±0.5mV (B grade)
• Input Voltage Range
ISL21007-12, 20, 25. . . . . . . . . . . . . . . . . . . . .2.7V to 5.5V
ISL21007-30. . . . . . . . . . . . . . . . . . . . . . . . . . 3.2V to 5.5V
• Low Output Voltage Noise . . . . .4.5µVP-P (0.1Hz to 10Hz)
• Supply Current . . . . . . . . . . . . . . . . . . . . . . . .150µA (Max)
• Temperature Coefficient . . . . . . . . . . . . 3ppm/°C (B grade)
• Operating Temperature Range. . . . . . . . . -40°C to +125°C
• Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld SOIC
Available Options
• Pb-Free (RoHS Compliant)
VOUT
OPTION
(V)
INITIAL
ACCURACY
(mV)
TEMPCO.
(ppm/°C)
ISL21007BFB812Z
1.250
±0.5
3
ISL21007CFB812Z
1.250
±1.0
5
ISL21007DFB812Z
1.250
±2.0
10
ISL21007BFB820Z
2.048
±0.5
3
ISL21007CFB820Z
2.048
±1.0
5
ISL21007DFB820Z
2.048
±2.0
10
ISL21007BFB825Z
2.500
±0.5
3
ISL21007CFB825Z
2.500
±1.0
5
ISL21007DFB825Z
2.500
±2.0
10
ISL21007BFB830Z
3.000
±0.5
3
ISL21007CFB830Z
3.000
±1.0
5
ISL21007DFB830Z
3.000
±2.0
10
PART NUMBER
FN6326.7
Applications
• High Resolution A/Ds and D/As
• Digital Meters
• Bar Code Scanners
• Basestations
• Battery Management/Monitoring
• Industrial/Instrumentation Equipment
Pinout
ISL21007
(8 LD SOIC)
TOP VIEW
GND or NC 1
8 DNC
VIN 2
7 DNC
DNC 3
6 VOUT
GND 4
5 TRIM
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FGA is a trademark of Intersil Corporation. Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL21007
Ordering Information
PART NUMBER
(Notes 1, 2)
PART MARKING
VOUT OPTION
(V)
GRADE
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
ISL21007BFB812Z
21007BF Z12
1.250
±0.5mV, 3ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007CFB812Z
21007CF Z12
1.250
±1.0mV, 5ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007DFB812Z
21007DF Z12
1.250
±2.0mV, 10ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007BFB820Z
21007BF Z20
2.048
±0.5mV, 3ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007CFB820Z
21007CF Z20
2.048
±1.0mV, 5ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007DFB820Z
21007DF Z20
2.048
±2.0mV, 10ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007BFB825Z
21007BF Z25
2.500
±0.5mV, 3ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007CFB825Z
21007CF Z25
2.500
±1.0mV, 5ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007DFB825Z
21007DF Z25
2.500
±2.0mV, 10ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007BFB830Z
21007BF Z30
3.000
±0.5mV, 3ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007CFB830Z
21007CF Z30
3.000
±1.0mV, 5ppm/°C
-40 to +125
8 Ld SOIC
M8.15
ISL21007DFB830Z
21007DF Z30
3.000
±2.0mV, 10ppm/°C
-40 to +125
8 Ld SOIC
M8.15
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
2. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2
FN6326.7
December 13, 2007
ISL21007
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1
GND or NC
2
VIN
Power Supply Input Connection
4
GND
Ground
5
TRIM
Allows user trim VOUT ±2.5%
6
VOUT
Voltage Reference Output Connection
3, 7, 8
DNC
Ground or No Connection
Do Not Connect; Internal Connection - Must Be Left Floating
Typical Application Circuit
1 GND
+3V
C1
10µF
2 VIN
3 NC
4 GND
NC 8
NC 7
VOUT 6
TRIM 5
ISL21007-12, 20, 25, 30
SPI BUS
X79000
1 SCK
2 A0
3 A1
4 A2
CS 20
CLR 19
VCC 18
VH 17
5 SI
6 SO
VREF 15
7 RDY
8 UP
VOUT 13
9 DOWN
10 OE
VL 16
C1
0.001µF
VSS 14
VBUF 12
LOW NOISE DAC OUTPUT
VFB 11
FIGURE 1. TYPICAL APPLICATION PRECISION 12-BIT SUBRANGING DAC
3
FN6326.7
December 13, 2007
ISL21007
Absolute Voltage Ratings
Thermal Information
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V
Max Voltage VOUT to GND (10s) . . . . . . . . . . . . . . -0.5V to VOUT + 1
Voltage on “DNC” pins . . . . No connections permitted to these pins.
ESD Rating
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600V
Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113.12
Continuous Power Dissipation (Note 3) . . . . . . . . . . . . . TA = +70°C
8 Ld SOIC derate 5.88mW/°C above +70°C . . . . . . . . . . . . 471mW
Pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at
the specified temperature and are pulsed tests, therefore: TJ = TC = TA
NOTE:
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Common Electrical Specifications (ISL21007-12, -20, -25, -30) TA = -40°C to +125°C, unless otherwise specified.
PARAMETER
VOA
TC VOUT
IIN
DESCRIPTION
VOUT Accuracy @ TA = +25°C
Output Voltage Temperature
Coefficient (Note 4)
CONDITIONS
TYP
MAX
UNIT
ISL21007B
-0.5
+0.5
mV
ISL21007C
-1.0
+1.0
mV
ISL21007D
-2.0
+2.0
mV
ISL21007B
3
ppm/°C
ISL21007C
5
ppm/°C
ISL21007D
10
ppm/°C
150
µA
Supply Current
75
Trim Range
tR
MIN
±2.0
±2.5
%
Turn-on Settling Time
VOUT = ±0.1%
120
µs
Ripple Rejection
f = 10kHz
60
dB
eN
Output Voltage Noise
0.1Hz ≤ f ≤ 10Hz
4.5
µVP-P
VN
Broadband Voltage Noise
10Hz ≤ f ≤ 1kHz
2.2
µVRMS
Noise Density
f = 1kHz
60
nV/√Hz
Electrical Specifications (ISL21007-12, VOUT = 1.250V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
5.5
V
VIN
Input Voltage Range
VOUT
Output Voltage
ΔVOUT /ΔVIN
Line Regulation
2.7V < VIN < 5.5V
100
700
µV/V
ΔVOUT/ΔIOUT
Load Regulation
Sourcing: 0mA ≤ IOUT ≤ 7mA
10
100
µV/mA
Sinking: -7mA ≤ IOUT ≤ 0mA
20
150
µV/mA
2.7
1.250
V
ISC
Short Circuit Current
TA = +25°C, VOUT tied to GND
40
mA
ΔVOUT/ΔTA
Thermal Hysteresis (Note 5)
ΔTA = +165°C
50
ppm
ΔVOUT/Δt
Long Term Stability (Note 6)
TA = +25°C
100
ppm
4
FN6326.7
December 13, 2007
ISL21007
Electrical Specifications (ISL21007-20, VOUT = 2.048V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
5.5
V
VIN
Input Voltage Range
VOUT
Output Voltage
ΔVOUT /ΔVIN
Line Regulation
2.7V < VIN < 5.5V
50
200
µV/V
ΔVOUT/ΔIOUT
Load Regulation
Sourcing: 0mA ≤ IOUT ≤ 7mA
10
100
µV/mA
Sinking: -7mA ≤ IOUT ≤ 0mA
20
150
µV/mA
2.7
2.048
V
ISC
Short Circuit Current
TA = +25°C, VOUT tied to GND
50
mA
ΔVOUT/ΔTA
Thermal Hysteresis (Note 5)
ΔTA = +165°C
50
ppm
ΔVOUT/Δt
Long Term Stability (Note 6)
TA = +25°C
75
ppm
Electrical Specifications (ISL21007-25, VOUT = 2.500V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
5.5
V
VIN
Input Voltage Range
VOUT
Output Voltage
ΔVOUT /ΔVIN
Line Regulation
2.7V < VIN < 5.5V
50
200
µV/V
ΔVOUT/ΔIOUT
Load Regulation
Sourcing: 0mA ≤ IOUT ≤ 5mA
10
100
µV/mA
Sinking: -5mA ≤ IOUT ≤ 0mA
20
150
µV/mA
2.7
2.500
V
ISC
Short Circuit Current
TA = +25°C, VOUT tied to GND
50
mA
ΔVOUT/ΔTA
Thermal Hysteresis (Note 5)
ΔTA = +165°C
50
ppm
ΔVOUT/Δt
Long Term Stability (Note 6)
TA = +25°C
50
ppm
Electrical Specifications (ISL21007-30, VOUT = 3.000V) VIN = 5.0V, TA = -40°C to +125°C, unless otherwise specified
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
5.5
V
VIN
Input Voltage Range
VOUT
Output Voltage
ΔVOUT /ΔVIN
Line Regulation
3.2V < VIN < 5.5V
50
200
µV/V
ΔVOUT/ΔIOUT
Load Regulation
Sourcing: 0mA ≤ IOUT ≤ 7mA
10
100
µV/mA
Sinking: -7mA ≤ IOUT ≤ 0mA
20
150
µV/mA
3.2
3.000
V
ISC
Short Circuit Current
TA = +25°C, VOUT tied to GND
50
mA
ΔVOUT/ΔTA
Thermal Hysteresis (Note 5)
ΔTA = +165°C
50
ppm
ΔVOUT/Δt
Long Term Stability (Note 6)
TA = +25°C
50
ppm
4. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is divided by the
temperature range; in this case, -40°C to +125°C = +165°C.
5. Thermal Hysteresis is the change of VOUT measured at TA = +25°C after temperature cycling over a specified range, ΔTA. VOUT is read initially
at TA = +25°C for the device under test. The device is temperature cycled and a second VOUT measurement is taken at +25°C. The difference
between the initial VOUT reading and the second VOUT reading is then expressed in ppm. For Δ TA = +165°C, the device under test is cycled
from +25°C to +125°C to -40°C to +25°C.
6. Long term drift is logarithmic in nature and diminishes over time. Drift after the first 1000 hours will be approximately 10ppm/√(1kHrs)
5
FN6326.7
December 13, 2007
ISL21007
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ)
95
120
UNIT 3
90
100
IIN (µA)
IIN (µA)
+125°C
85
80
UNIT 2
60
UNIT 1
40
80
+25°C
75
70
20
-40°C
65
0
2.5
3.0
3.5
4.0
4.5
VIN (V)
5.0
5.5
60
2.5
6.0
1.25015
UNIT 3
1.25005
1.25000
UNIT 2
1.24995
1.24990
UNIT 1
1.24985
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
100
50
4.5
5.0
5.5
5.5
+125°C
0
+25°C
-50
-40°C
-100
-150
-200
-250
-300
2.5
1.24980
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN (V)
FIGURE 5. LINE REGULATION OVER TEMPERATURE
FIGURE 4. LINE REGULATION (3 UNITS)
0.15
1.25010
+125°C
+25°C
1.25005
0.10
UNIT 1
1.25000
0.05
0.00
VOUT (V)
ΔVOUT (mV)
4.0
VIN (V)
150
1.25010
-40°C
-0.05
1.24995
UNIT 2
1.24990
UNIT 3
1.24985
-0.10
-0.15
3.5
FIGURE 3. IIN vs VIN OVER TEMPERATURE
ΔVO (µV)
(NORMALIZED TO VIN = 3.0V)
VOUT (V)
(NORMALIZED TO 1.250V AT VIN = 3.0V)
FIGURE 2. IIN vs VIN (3 UNITS)
3.0
1.24980
-7
-6 -5 -4
SINKING
-3 -2 -1 0 1 2 3
OUTPUT CURRENT (mA)
4 5 6 7
SOURCING
FIGURE 6. LOAD REGULATION OVER TEMPERATURE
6
1.24975
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
FIGURE 7. VOUT vs TEMPERATURE (3 UNITS)
FN6326.7
December 13, 2007
ISL21007
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ)
(Continued)
X: 200mV/DIV
Y: 10µs/DIV
0
10nF LOAD
100nF LOAD
PSRR (dB)
-20
ΔVIN = +0.3V
-40
-60
ΔVIN = -0.3V
1µF LOAD
-80
1nF LOAD
NO LOAD
-100
1.00E+00
1.00E+02
1.00E+04
1.00E+0
FREQUENCY (Hz)
FIGURE 9. LINE TRANSIENT RESPONSE, NO CAPACITIVE
LOAD
FIGURE 8. PSRR vs CAPACITIVE LOADS
X: 20µs/DIV
Y: 1V/DIV
X: 200mV/DIV
Y: 10µs/DIV
ΔVIN = +0.3V
VIN
VOUT = 1.25V
ΔVIN = -0.3V
FIGURE 11. TURN-ON TIME
FIGURE 10. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
GAIN IS x1000,
NOISE IS 4.5µVP-P
140
1nF
10nF
120
100nF
2mV/DIV
ZOUT (Ω)
100
NO LOAD
80
60
40
20
0
1.00E+00
1.00E+01
1.00E+02
1.00E+03
1.00E+04
1.00E+05
1.00E+06
FREQUENCY (Hz)
FIGURE 12. ZOUT vs FREQUENCY
7
FIGURE 13. VOUT NOISE, 0.1Hz TO 10Hz
FN6326.7
December 13, 2007
ISL21007
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ)
NO OUTPUT CAPACITANCE
X: 50µs/DIV
Y: 1V/DIV
(Continued)
+7mA
-7mA
FIGURE 14. LOAD TRANSIENT RESPONSE
Typical Performance Curves (ISL21007-20) (REXT = 100kΩ)
95
95
90
90
UNIT 2
80
IIN (uA)
IIN (µA)
85
80
UNIT 1
75
75
70
-40°C
65
+25°C
60
70
65
2.7
+125°C
85
UNIT 3
3.1
55
3.5
3.9
4.3
4.7
5.1
50
2.7
5.5
3.1
3.5
3.9
2.04815
UNIT 2
2.04810
2.04805
UNIT 1
UNIT 3
2.04795
2.04790
2.5
3.0
3.5
4.0
4.5
5.0
VIN(V)
FIGURE 17. LINE REGULATION (3 UNITS)
8
4.7
5.1
5.5
FIGURE 16. IIN vs VIN OVER TEMPERATURE
5.5
VOUT (V)
(NORMALIZED TO 2.048V AT VIN = 3V)
VOUT (V) NORMALIZED TO 2.048V AT
VIN = 3.0V
FIGURE 15. IIN vs VIN (3 UNITS)
2.04800
4.3
VIN (V)
VIN (V)
2.04815
-40°C
2.04810
+125°C
2.04805
+25°C
2.04800
2.04795
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN(V)
FIGURE 18. LINE REGULATION OVER TEMPERATURE
FN6326.7
December 13, 2007
ISL21007
Δ VOUT (mV) NORMALIZED TO 0mA
1.6
1.2
+125°C
0.0
0.4
-40°C
0.0
-0.4
+25°C
-0.8
-1.2
-7
-6
-5
-4
SINKING
-3
-2
-1
0
1
2
3
OUTPUT CURRENT (mA)
4
5
6
SOURCING
FIGURE 19. LOAD REGULATION OVER TEMPERATURE
7
VOUT(V) NORMALIZED TO 2.048V AT +25°C
Typical Performance Curves (ISL21007-20) (REXT = 100kΩ)
(Continued)
2.0496
2.0492
2.0488
UNIT 2
2.0484
UNIT 1
2.0480
2.0476
UNIT 3
2.0472
-40
-25
-10
5
20
35
50
65
80
95
110 125
TEMPERATURE (°C)
FIGURE 20. VOUT vs TEMPERATURE (3 UNITS)
X: 200mV/DIV
Y: 10µs/DIV
0
10nF LOAD
100nF LOAD
-20
PSRR (dB)
ΔVIN = +0.3V
-40
1µF LOAD
-60
-80
ΔVIN = -0.3V
NO LOAD
-100
1.0E+01
1.0E+03
1.0E+05
FREQUENCY (Hz)
FIGURE 21. PSRR vs CAPACITIVE LOADS
FIGURE 22. LINE TRANSIENT RESPONSE, NO CAPACITIVE
LOAD
X: 100µs/DIV
Y: 2V/DIV
X: 200mV/DIV
Y: 10µs/DIV
ΔVIN = +0.3V
VIN
VOUT = 2.048V
ΔVIN = -0.3V
FIGURE 23. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
9
FIGURE 24. TURN-ON TIME
FN6326.7
December 13, 2007
ISL21007
Typical Performance Curves (ISL21007-20) (REXT = 100kΩ)
(Continued)
GAIN IS x1000,
NOISE IS 4.5µVP-P
140
1nF
10nF
120
100nF
2mV/DIV
ZOUT (Ω)
100
NO LOAD
80
60
40
20
0
1.00E+00
1.00E+01
1.00E+02
1.00E+03
1.00E+04
1.00E+05
1.00E+06
FREQUENCY (Hz)
FIGURE 25. ZOUT VS FREQUENCY
FIGURE 26. VOUT NOISE, 0.1Hz TO 10Hz
X: 20µs/DIV
Y: 200mV/DIV
X: 20µs/DIV
Y: 200mV/DIV
+7mA
+7mA
-7mA
-7mA
FIGURE 27. LOAD TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
FIGURE 28. LOAD TRANSIENT RESPONSE, NO CAPACITIVE
LOAD
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ)
100
120
UNIT 3
95
100
+125°C
90
UNIT 2
85
IIN (µA)
IIN (µA)
80
UNIT 1
60
80
+25°C
-40°C
75
40
70
20
65
60
0
2.5
3.0
3.5
4.0
4.5
5.0
VIN (V)
FIGURE 29. IIN vs VIN (3 UNITS)
10
5.5
6.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
FIGURE 30. IIN vs VIN OVER TEMPERATURE
FN6326.7
December 13, 2007
ISL21007
2.5002
2.5001
UNIT 1
2.5000
UNIT 2
2.4999
UNIT 3
2.4998
2.4997
2.4996
2.5
(Continued)
100
ΔVO (µV)
(NORMALIZED TO VIN = 3.0V)
VOUT (V)
(NORMALIZED TO 2.500V AT VIN = 3V)
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ)
3.0
3.5
4.0
4.5
5.0
50
0
-50
-100
-150
+125°C
-200
-250
-300
-40°C
-350
-400
2.5
5.5
+25°C
3.0
4.0
3.5
VIN (V)
FIGURE 31. LINE REGULATION (3 UNITS)
5.5
6.0
FIGURE 32. LINE REGULATION OVER TEMPERATURE
+125°C
UNIT 2
2.5002
0.4
2.5001
-40°C
0.2
2.5000
+25°C
VOUT (V)
ΔVOUT (mV)
5.0
2.5003
0.6
0
4.5
VIN (V)
-0.2
-0.4
UNIT 1
2.4999
2.4998
2.4997
2.4996
-0.6
2.4995
-0.8
2.4994
-1.0
-7 -6 -5 -4
2.4993
-40
SINKING
-3 -2 -1
0
1
2
3
OUTPUT CURRENT (mA)
4
5
6
7
UNIT 3
-20
0
FIGURE 33. LOAD REGULATION OVER TEMPERATURE
20
40
60
80
100
120
140
TEMPERATURE (°C)
SOURCING
FIGURE 34. VOUT vs TEMPERATURE (3 UNITS)
X: 200mV/DIV
Y: 10µs/DIV
10
NO LOAD
1nF
10nF
100nF
0
-10
PSRR (dB)
-20
-30
ΔVIN = +0.3V
1µF
-40
-50
ΔVIN = -0.3V
-60
-70
-80
-90
-100
1.E+00
1.E+02
1.E+04
1.E+06
FREQUENCY (Hz)
FIGURE 35. PSRR vs CAPACITIVE LOADS
11
FIGURE 36. LINE TRANSIENT RESPONSE, NO CAPACITIVE
LOAD
FN6326.7
December 13, 2007
ISL21007
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ)
X: 200mV/DIV
Y: 10µs/DIV
(Continued)
X: 20µs/DIV
Y: 1V/DIV
ΔVIN = +0.3V
VIN
ΔVIN = -0.3V
VOUT = 2.5V
FIGURE 37. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
FIGURE 38. TURN-ON TIME
GAIN IS x1000,
NOISE IS 4.5µVP-P
140
1nF
10nF
120
100nF
2mV/DIV
ZOUT (Ω)
100
NO LOAD
80
60
40
20
0
1.00E+00
1.00E+01
1.00E+02
1.00E+03
1.00E+04
1.00E+05
1.00E+06
FREQUENCY (Hz)
FIGURE 40. VOUT NOISE, 0.1Hz TO 10Hz
FIGURE 39. ZOUT vs FREQUENCY
NO OUTPUT CAPACITANCE
X: 50µs/DIV
Y: 500mV/DIV
+5mA
-5mA
FIGURE 41. LOAD TRANSIENT RESPONSE
12
FN6326.7
December 13, 2007
ISL21007
Typical Performance Curves (ISL21007-30) (REXT = 100kΩ)
120
120
UNIT 2
100
80
80
IIN (µA)
IIN (µA)
+125°C
100
UNIT 3
UNIT 1
60
60
40
40
20
20
0
3.2
3.7
4.2
4.7
+25°C
0
3.2
5.2
-40°C
3.7
4.2
UNIT 2
UNIT 3
2.9975
2.9965
2.9955
3.2
3.6
4.0
4.4
4.8
5.2
5.6
VOUT (V) NORMALIZED TO 3.0V AT
5.0VIN
VOUT(V) NORMALIZED TO 3.0V AT
5.0VIN
2.9985
FIGURE 43. IIN vs VIN OVER TEMPERATURE
UNIT 1
2.9995
3.001
3.000
2.999
+125°C
+25°C
2.998
2.997
-40°C
2.996
2.995
2.994
3.2
3.6
4.0
VIN (V)
-0.05
-0.10
+125°C
-0.15
-0.20
-0.25
-7 -6 -5 -4 -3 -2 -1
SINKING
0
1
LOAD (mA)
2
3
4
5
6
SOURCING
FIGURE 46. LOAD REGULATION OVER TEMPERATURE
13
7
VOUT (V) NORMALIZED TO 3.0V AT +25°C
Δ VOUT (mV) NORMALIZED TO
0mA
-40°C
+25°C
4.8
5.2
5.6
FIGURE 45. LINE REGULATION OVER TEMPERATURE
0.10
0.05
4.4
VIN (V)
FIGURE 44. LINE REGULATION (3 UNITS)
0.00
5.2
VIN (V)
VIN (V)
FIGURE 42. IIN vs VIN (3 UNITS)
3.0005
4.7
3.0006
3.0004
3.0002
UNIT 3
3.0000
2.9998
UNIT 2
2.9996
2.9994
UNIT 1
2.9992
2.9990
-40 -25 -10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
FIGURE 47. VOUT vs TEMPERATURE (3 UNITS)
FN6326.7
December 13, 2007
ISL21007
Typical Performance Curves (ISL21007-30) (REXT = 100kΩ)
(Continued)
PSRR (dB)
X: 200mV/DIV
Y: 10µs/DIV
10
0 VIN (DC) = 5.0V
-10 VIN (AC) = 50mVP-P
-20
-30
-40
-50
-60
-70
-80
-90
-100
1.E+00
1.E+02
NO LOAD
1nF
10nF
100nF
ΔVIN = +0.5V
1µF
ΔVIN = -0.5V
1.E+04
1.E+06
FREQUENCY (Hz)
FIGURE 48. PSRR vs CAPACITIVE LOADS
FIGURE 49. LINE TRANSIENT RESPONSE, NO CAPACITIVE
LOAD
X: 200mV/DIV
Y: 10µs/DIV
VIN = 5.0V
ΔVIN = +0.5V
1V/DIV
VOUT = 3.0V
ΔVIN = -0.5V
20µs/DIV
FIGURE 51. TURN-ON TIME
FIGURE 50. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
GAIN IS x1000,
NOISE IS 4.5µVP-P
140
1nF
10nF
120
100nF
2mV/DIV
ZOUT (Ω)
100
NO LOAD
80
60
40
20
0
1.00E+00
1.00E+01
1.00E+02
1.00E+03
1.00E+04
1.00E+05
1.00E+06
FREQUENCY (Hz)
FIGURE 52. ZOUT vs FREQUENCY
14
FIGURE 53. VOUT NOISE, 0.1Hz TO 10Hz
FN6326.7
December 13, 2007
ISL21007
Typical Performance Curves (ISL21007-30) (REXT = 100kΩ)
(Continued)
200mV/DIV
+7mA
-7mA
100µs/DIV
FIGURE 54. LOAD TRANSIENT RESPONSE
Applications Information
FGA Technology
The ISL21007 voltage reference uses floating gate
technology to create references with very low drift and
supply current. Essentially, the charge stored on a floating
gate cell is set precisely in manufacturing. The reference
voltage output itself is a buffered version of the floating gate
voltage. The resulting reference device has excellent
characteristics which are unique in the industry: very low
temperature drift, high initial accuracy, and almost zero
supply current. Also, the reference voltage itself is not limited
by voltage bandgaps or zener settings, so a wide range of
reference voltages can be programmed (standard voltage
settings are provided, but customer-specific voltages are
available).
The process used for these reference devices is a floating
gate CMOS process, and the amplifier circuitry uses CMOS
transistors for amplifier and output transistor circuitry. While
providing excellent accuracy, there are limitations in output
noise level and load regulation due to the MOS device
characteristics. These limitations are addressed with circuit
techniques discussed in other sections.
Micropower Operation
The ISL21007 consumes extremely low supply current due
to the proprietary FGA technology. Low noise performance is
achieved using optimized biasing techniques. Supply current
is typically 75µA and noise is 4.5µVP-P benefitting precision,
low noise portable applications such as handheld meters
and instruments.
Data Converters in particular can utilize the ISL21007 as an
external voltage reference. Low power DAC and ADC
circuits will realize maximum resolution with lowest noise.
15
Board Mounting Considerations
For applications requiring the highest accuracy, board
mounting location should be reviewed. The device uses a
plastic SOIC package, which will subject the die to mild
stresses when the PC board is heated and cooled and
slightly change its shape. Placing the device in areas subject
to slight twisting can cause degradation of the accuracy of
the reference voltage due to these die stresses. It is normally
best to place the device near the edge of a board, or the
shortest side, as the axis of bending is most limited at that
location. Mounting the device in a cutout also minimizes flex.
Obviously, mounting the device on flexprint or extremely thin
PC material will likewise cause loss of reference accuracy.
Noise Performance and Reduction
The output noise voltage in a 0.1Hz to 10Hz bandwidth is
typically 4.5µVP-P. The noise measurement is made with a
bandpass filter made of a 1 pole high-pass filter with a corner
frequency at 0.1Hz and a 2-pole low-pass filter with a corner
frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth.
Noise in the 10kHz to 1MHz bandwidth is approximately
40µVP-P with no capacitance on the output. This noise
measurement is made with a 2 decade bandpass filter made
of a 1 pole high-pass filter with a corner frequency at 1/10 of
the center frequency and 1-pole low-pass filter with a corner
frequency at 10 times the center frequency. Load capacitance
up to 1000pF can be added but will result in only marginal
improvements in output noise and transient response. The
output stage of the ISL21007 is not designed to drive heavily
capacitive loads, so for load capacitances above 0.001µF, the
noise reduction network shown in Figure 55 is recommended.
This network reduces noise significantly over the full
bandwidth. Noise is reduced to less than 20µVP-P from 1Hz to
1MHz using this network with a 0.01µF capacitor and a 2kΩ
resistor in series with a 10µF capacitor. Also, transient
response is improved with higher value output capacitor. The
0.01µF value can be increased for better load transient
response with little sacrifice in output stability.
FN6326.7
December 13, 2007
ISL21007
Output Voltage Adjustment
Turn-On Time
The ISL21007 devices have low supply current and thus the
time to bias up internal circuitry to final values will be longer
than with higher power references. Normal turn-on time is
typically 120µs. This is shown in Figure 10. Circuit design
must take this into account when looking at power-up delays
or sequencing.
Temperature Coefficient
The limits stated for temperature coefficient (tempco) are
governed by the method of measurement. The overwhelming
standard for specifying the temperature drift of a reference is to
measure the reference voltage at two temperatures, take the
total variation, (VHIGH – VLOW), and divide by the temperature
extremes of measurement (THIGH – TLOW). The result is
divided by the nominal reference voltage (at T = +25°C) and
multiplied by 106 to yield ppm/°C. This is the “Box” method for
specifying temperature coefficient.
The output voltage can be adjusted up or down by 2.5% by
placing a potentiometer from VOUT to ground, and connecting
the wiper to the TRIM pin. The TRIM input is high impedance,
so no series resistance is needed. The resistor in the
potentiometer should be a low tempco (<50ppm/°C) and the
resulting voltage divider should have very low tempco
<5ppm/°C. A digital potentiometer such as the ISL95810
provides a low tempco resistance and excellent resistor and
tempco matching for trim applications. See Figure 58 and
TB473 for further information.
VIN = 5.0V
10µF
VIN
VO
0.1µF
ISL21007
GND
2kΩ
0.01µF
10µF
FIGURE 55. HANDLING HIGH LOAD CAPACITANCE
Typical Application Circuits
VIN = +5.0V
R = 200Ω
2N2905
VIN
ISL21007 VOUT
VOUT = 2.500V
2.5V/50mA
0.001µF
GND
FIGURE 56. PRECISION 2.500V 50mA REFERENCE
16
FN6326.7
December 13, 2007
ISL21007
Typical Application Circuits (Continued)
+2.7 TO 5.5V
10µF
0.1µF
VIN
VOUT
ISL21007-25
VOUT = 2.500V
GND
0.001µF
VCC
RH
VOUT
X9119
(UNBUFFERED)
+
SDA
2-WIRE BUS
EL8178
SCL
VOUT
–
VSS
(BUFFERED)
RL
FIGURE 57. 2.500V FULL SCALE LOW-DRIFT, LOW NOISE, 10-BIT ADJUSTABLE VOLTAGE SOURCE
+2.7 TO 5.5V
0.1µF
10µF
VIN
EL8178
+
VOUT
VOUT SENSE
–
ISL21007-12
LOAD
GND
FIGURE 58. KELVIN SENSED LOAD
10µF
+2.7 TO 5.5V
0.1µF
VIN
2.5V ±2.5%
VOUT
ISL21007-12
TRIM
GND
VCC
I2C BUS
RH
SDA
SCL
ISL95810
VSS
RL
FIGURE 59. OUTPUT ADJUSTMENT USING THE TRIM PIN
17
FN6326.7
December 13, 2007
ISL21007
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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18
FN6326.7
December 13, 2007