RT9014/A

RT9014/A
Ultra Low Noise 300mA Dual LDO Regulator with POR,
NMOS Driver and Requiring No Bypass Capacitor
General Description
Features
RT9014/A is a dual channel, low noise, and low dropout
with the sourcing ability up to 300mA, an open drain driver
and power-on reset function. The open-drain output is
capable of sinking 150mA for LED backlighting
applications.
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Wide Operating Voltage Ranges : 2.5V to 5.5V
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Low-Noise for RF Application
No Noise Bypass Capacitor Required
Fast Response in Line/Load Transient
TTL-Logic-Controlled Shutdown Input
Low Temperature Coefficient
Dual LDO Outputs (300mA/300mA)
1 Open-Drain Driver
Ultra-low Quiescent Current 27μ
μA/LDO
High Output Accuracy 2%
Short Circuit Protection
Thermal Shutdown Protection
Current Limit Protection
Short Circuit Thermal Folded Back Protection
Tiny 10-Lead WDFN Package
RoHS Compliant and 100% Lead (Pb)-Free
The range of output voltage is from 1.2V to 3.6V by
operating from 2.5V to 5.5V input.
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The RT9014/A offers 2% accuracy, extremely low dropout
voltage (240mV @ 300mA), and extremely low ground
current, only 27μA per LDO. The shutdown current is near
zero current which is suitable for battery-power devices.
Other features include current limiting, over temperature,
output short circuit protection.
The RT9014/A is short circuit thermal folded back
protected. The IC lowers its OTP trip point from 165°C to
110°C when output short circuit occurs (VOUT < 0.4V)
providing maximum safety to end users.
The RT9014/A can operate stably with very small ceramic
output capacitors, reducing required board space and
component cost. The RT9014/A is available in fixed output
voltages in the WDFN-10L 3x3 package.
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Applications
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Ordering Information
RT9014/A-
Package Type
QW : WDFN-10L 3x3 (W-Type)
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
Output Voltage : VOUT1/VOUT2
VOUT2 > VOUT1 is Recommended
EN Function Independent
EN Function Dependent
Note :
Richtek products are :
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RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
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Suitable for use in SnPb or Pb-free soldering processes.
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CDMA/GSM Cellular Handsets
Battery-Powered Equipment
Laptop, Palmtops, Notebook Computers
Hand-Held Instruments
PCMCIA Cards
Portable Information Appliances
Available Voltage Version
Code
Voltage
Code
Voltage
Code
Voltage
A
3.5
B
1.3
C
1.2
D
G
1.85
1.8
E
H
2.1
2
F
J
1.5
2.5
K
N
2.6
2.85
L
P
2.7
3
M
Q
2.8
3.1
R
V
Y
3.2
2.9
1.9
S
W
3.3
1.6
T
X
2.65
3.15
Marking Information
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.
DS9014/A-11 April 2011
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1
RT9014/A
Pin Configurations
(TOP VIEW)
VOUT1
VOUT2
8 POR
7 DRV
GND
1
10
2
9
GND
3
4
11
9
5
VIN
EN1
EN2
SW
SET
VOUT1
VOUT2
8 POR
7 DRV
GND
1
10
2
9
3
GND
4
11
5
RT9014
9
VIN
EN
NC
SW
SET
RT9014A
Typical Application Circuit
100K
100K
VIN
VIN
CIN
1uF Chip Enable
EN
DRV Enable
VIN
POR
DRV
RT9014
VOUT1
COUT1
1uF
SW
100k
VOUT2
SET
VIN
CIN
1uF
COUT2
1uF
GND
VOUT1
Chip Enable
DRV Enable
POR
EN1
DRV
RT9014A
EN2
VOUT1
SW
VOUT2
100k
VOUT2
SET
GND
CDELAY
CDELAY
COUT1
1uF
COUT2
1uF
VOUT1
VOUT2
Functional Pin Description
Pin No.
RT9014-□□PQW
RT9014A-□□
Pin
Name
Pin Function
1
1
VIN
Supply Input.
2
--
EN
Chip Enable (Active High).
---
2
3
EN1
EN2
Chip Enable 1 (Active High).
Chip Enable 2 (Active High).
3
--
NC
No Internal Connection Pin.
4
4
SW
Active high signal drives open-drain N-MOSFET.
Note that this pin is high impedance. There should be a pull low
100kΩ resistor connected to GND when the control signal is
floating.
5
5
SET
Delay Set Input: Connect external capacitor to GND to set the
internal delay for the POR output. When left open, there is no
delay. This pin cannot be grounded.
6
6
GND
Common Ground.
7
7
DRV
Open-Drain Output: Capable of sinking 150mA.
8
8
POR
Power-On Reset Output: Open-drain output. Active low indicates
an output under-voltage condition on regulator 2.
9
9
VOUT2 Channel 2 Output Voltage
10
10
VOUT1 Channel 1 Output Voltage
11 (Exposed Pad) 11 (Exposed Pad) GND
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2
The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
DS9014/A-11 April 2011
RT9014/A
Function Block Diagram
Shutdown
and
Logic Control
VIN
-
VREF
MOS Driver
+
Error
Amplifier
VOUT1
Current-Limit
and
Thermal
Protection
GND
EN
Shutdown
and
Logic Control
0.2uA
-
VREF
MOS Driver
+
Error
Amplifier
Current-Limit
and
Thermal
Protection
VOUT2
GND
SET
POR& Delay
POR
DRV
SW
SW Logic
RT9014
To be continued
DS9014/A-11 April 2011
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3
RT9014/A
EN1
Shutdown
and
Logic Control
0.2uA
VIN
-
VREF
MOS Driver
+
Error
Amplifier
VOUT1
Current-Limit
and
Thermal
Protection
GND
EN2
Shutdown
and
Logic Control
0.2uA
-
VREF
MOS Driver
+
Error
Amplifier
Current-Limit
and
Thermal
Protection
VOUT2
GND
SET
POR& Delay
POR
DRV
SW
SW Logic
RT9014A
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DS9014/A-11 April 2011
RT9014/A
Absolute Maximum Ratings
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(Note 1)
Supply Input Voltage -----------------------------------------------------------------------------------------------------Other I/O Pin Voltages --------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
WDFN-10L 3x3 ------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WDFN-10L 3x3, θJA ------------------------------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Mode) ---------------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------------
Recommended Operating Conditions
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6V
6V
0.926W
108°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Supply Input Voltage ------------------------------------------------------------------------------------------------------ 2.5V to 5.5V
Enable Input Voltage ------------------------------------------------------------------------------------------------------ 0V to 5.5V
Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = VOUT + 1V, VEN = VIN, CIN = COUT = 1μF, TA = 25°C, unless otherwise specified.)
Parameter
Input Voltage
Dropout Voltage
Symbol
VIN
(Note 5)
VDROP
Test Conditions
Min
Typ
Max
Unit
2.5
--
5.5
V
IOUT = 150mA
--
120
--
mV
IOUT = 300mA
--
240
--
mV
1.2
--
3.6
V
VIN = 2.5V to 5.5V
Output voltage range
VOUT
V OUT Accuracy
ΔV
IOUT = 1mA
-2
--
+2
%
Line Regulation
ΔVLINE
VIN = (V OUT + 0.3V) to 5.5V or
VIN > 2.5V, whichever is larger
--
--
0.2
%/V
Load Regulation
ΔVLOAD 1mA < IOUT< 300mA
--
--
0.6
%
RLOAD = 1Ω
330
450
700
mA
Current Limit
Quiescent Current
IQ
VEN > 1.5V
--
58
80
uA
Shutdown Current
IQ_SD
VEN < 0.4V
--
--
1
uA
VIH
VIN = 2.5V to 5.5V, Power On
1.5
--
--
VIL
VIN = 2.5V to 5.5V, Shutdown
--
--
0.4
--
100
--
ppm/°C
EN Threshold
Output Voltage TC
V
Thermal Shutdown
T SD
--
170
--
°C
Thermal Shutdown Hysteresis
ΔTSD
--
40
--
°C
To be continued
DS9014/A-11 April 2011
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5
RT9014/A
Parameter
Min
Typ
Max
Unit
f =100Hz
--
65
--
dB
f =1kHz
--
60
--
dB
f =10kHz
--
50
--
dB
f =100Hz
--
65
--
dB
f =1kHz
--
50
--
dB
f =10kHz
--
50
--
dB
VTHL
Low Threshold, % of nominal
VOUT2 (Flag On)
85
90
93
%
VTHH
High Threshold, % of nominal
VOUT2 (Flag Off)
92
95
98
%
POR Output Logic Low Voltage
VOL
ILOW = 250uA
--
0.02
0.1
V
POR Leakage Current
IPOR
Flag Off
-1
0.01
1
μA
Set pin current source
VSET = 0
0.60
1.25
1.70
μA
Set pin threshold
POR = high
--
1.4
--
V
Voltage Low
IDRV = 150mA
--
0.2
0.5
V
Leakage current
IDRV = 0mA, VDRV = 5V, SW = 0V
-1
0.01
1
μA
VIL < 0.6V(DRV Shutdown)
-1
0.01
1
μA
VIH > 2.5V(DRV Enable)
-1
0.01
1
μA
VIL
Logic Low
--
--
0.4
V
VIH
Logic High
1.5
--
--
V
PSRR
ILOAD = 10mA
PSRR
ILOAD = 150mA
Symbol
PSRR
PSRR
Test Conditions
Power Good
Reset Threshold
DRV output
SW input current
SW input voltage
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. The dropout voltage is defined as VIN -VOUT, which is measured when VOUT is VOUT(NORMAL) − 100mV.
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DS9014/A-11 April 2011
RT9014/A
Typical Operating Characteristics
Output Voltage vs. Temperature
Output Voltage vs. Temperature
3.4
RT9014/A-GS, VOUT1
1.85
Output Voltage (V)
Output Voltage (V)
1.9
1.8
1.75
RT9014-GS, VOUT2
3.35
3.3
3.25
3.2
1.7
-50
-25
0
25
50
75
100
-50
125
-25
0
RT9014/A-GS
VIN = VEN = VSW = 4.3V
CIN = COUT1 = COUT2 = 1uF/X7R
100
125
RT9014/A-GS, VOUT2
TJ = 125°C
300
Dropout Voltage (mV)
Quiescent Current (uA)
350
60
55
250
TJ = 25°C
200
150
TJ = -40°C
100
50
50
0
-50
-25
0
25
50
75
100
0
125
50
Temperature (°C)
0
PSRR
10000
RT9014-FM, VOUT1
VIN = 4.3V ± 0.1V
CIN = COUT1 = COUT2 = 1uF/X7R
ILOAD = 100mA
ILOAD = 50mA
-20
-40
ILOAD = 10mA
-60
-80
0.01
10
0.1
100
1
1000
10k
10000
Frequency (Hz)
(Hz)
DS9014/A-11 April 2011
100
150
200
250
300
Load Current (mA)
100k
100000
1000k
1000000
POR Delay Time (ms)
20
PSRR (dB)
75
Dropout Voltage vs. Load Current
Quiescent Current vs. Temperature
65
50
Temperature (°C)
Temperature (°C)
70
25
POR Delay
RT9014/A-FM
1000
100
10
1
0.1
0.01
0.0001
0.0010
0.0100
0.1000
1.0000
POR Setting Capacitance (uF)
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RT9014/A
Line Transient Response
Line Transient Response
RT9014/A-GS, Both ILOAD = 10mA
VIN = 3.8V to 4.8V
RT9014/A-GS, Both ILOAD = 1mA
VIN = 3.8V to 4.8V
VIN 4.8
(V)
VIN 4.8
(V)
VOUT2
(10mV/Div)
VOUT2
(10mV/Div)
VOUT1
(10mV/Div)
VOUT1
(10mV/Div)
3.8
3.8
Time (100μs/Div)
Time (100μs/Div)
Line Transient Response
Line Transient Response
RT9014/A-GS, Both ILOAD = 50mA
VIN = 3.8V to 4.8V
RT9014/A-GS, Both ILOAD = 100mA
VIN = 3.8V to 4.8V
VIN 4.8
(V)
VIN 4.8
(V)
VOUT2
(10mV/Div)
VOUT2
(10mV/Div)
VOUT1
(10mV/Div)
VOUT1
(10mV/Div)
3.8
3.8
Time (100μs/Div)
Time (100μs/Div)
Load Transient Response
Load Transient Response
RT9014/A-GS, ILOAD = 10mA to 100mA
VIN = VEN = 4.3V
CIN = COUT1 = COUT2 = 1uF/X7R
RT9014/A-GS, ILOAD = 10mA to 50mA
VIN = VEN = 4.3V
CIN = COUT1 = COUT2 = 1uF/X7R
IOUT
(50mA/Div)
IOUT
(100mA/Div)
VOUT1
(20mV/Div)
VOUT1
(20mV/Div)
VOUT2
(20mV/Div)
VOUT2
(20mV/Div)
Time (250μs/Div)
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Time (250μs/Div)
DS9014/A-11 April 2011
RT9014/A
Start Up
EN Pin Shutdown Response
RT9014/A-FM, VIN = VSW = 5V
IOUT1 = IOUT2 = 50mA
RT9014/A-FM, VIN = VSW = 5V
IOUT1 = IOUT2 = 50mA
(5V/Div)
V EN
(5V/Div)
V EN
V OUT2
V OUT2
V OUT1
V OUT1
(1V/Div)
(1V/Div)
Time (5μs/Div)
Time (50μs/Div)
Power-On
Noise
RT9014/A-FM
Both ILOAD = 10mA
RT9014/A-GS, No LOAD
VIN = VEN = VSW = 4.5V(By battery)
150
CIN = COUT1 = COUT2 = 1uF/X7R
100
Noise (μV/Div)
VEN
(5V/Div)
VOUT1
(1V/Div)
VOUT2
(2V/Div)
POR
(5V/Div)
50
0
-50
-100
-150
Time (10μs/Div)
Time (10ms/Div)
Noise
300
RT9014/A-GS, ILOAD = 50mA
VIN = VEN = VSW = 4.5V(By battery)
CIN = COUT1 = COUT2 = 1uF/X7R
Noise (μV/Div)
200
100
0
-100
-200
-300
Time (10ms/Div)
DS9014/A-11 April 2011
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9
RT9014/A
Applications Information
Like any low-dropout regulator, the external capacitors used
with the RT9014/A must be carefully selected for regulator
stability and performance. Using a capacitor whose value
is > 1μF on the RT9014/A input and the amount of
capacitance can be increased without limit. The input
capacitor must be located a distance of not more than 0.5
inch from the input pin of the IC and returned to a clean
analog ground. Any good quality ceramic or tantalum can
be used for this capacitor. The capacitor with larger value
and lower ESR (equivalent series resistance) provides
better PSRR and line-transient response.
The output capacitor must meet both requirements for
minimum amount of capacitance and ESR in all LDOs
application. The RT9014/A is designed specifically to work
with low ESR ceramic output capacitor in space-saving
and performance consideration. Using a ceramic capacitor
whose value is at least 1μF with ESR is > 20mΩ on the
RT9014/A output ensures stability. The RT9014/A still
works well with output capacitor of other types due to the
wide stable ESR range. Figure 1. shows the curves of
allowable ESR range as a function of load current for various
output capacitor values. Output capacitor of larger
capacitance can reduce noise and improve load transient
response, stability, and PSRR. The output capacitor should
be located not more than 0.5 inch from the VOUT pin of
the RT9014/A and returned to a clean analog ground.
Region of Stable COUT ESR vs. Load Current
Region
ESR (Ω)
(Ω)
OUT ESR
RegionofofStable
StableCCOUT
100
RT9014-FM, VIN = 5V
CIN = COUT1 =
COUT2 = 1uF/X7R
10
Unstable Range
1
Thermal Considerations
Thermal protection limits power dissipation in RT9014/A.
When the operation junction temperature exceeds 170°C,
the OTP circuit starts the thermal shutdown function and
turns the pass element off. The pass element turn on again
after the junction temperature cools by 40°C. RT9014/A
lowers its OTP trip level from 170°C to 110°C when output
short circuit occurs (VOUT < 0.4V) as shown in Figure 2. It
limits IC case temperature under 100°C and provides
maximum safety to customer while output short circuit
occurring.
VOUT Short to GND
0.4V
VOUT
IOUT
TSD
170 °C
110 °C
OTP Trip Point
110 °C
IC Temperature
80 °C
Figure 2. Short Circuit Thermal Folded Back Protection
when Output Short Circuit Occurs (Patent)
For continuous operation, do not exceed absolute
maximum operation junction temperature 125°C. The
power dissipation definition in device is :
PD = (VIN − VOUT) x IOUT + VIN x IQ
Stable Range
0.1
0.01
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
Simulation Verify
0.001
0
50
100
150
200
Load Current (mA)
Figure 1. Stable Cout ESR Range
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10
250
300
PD(MAX) = ( TJ(MAX) − TA ) /θJA
Where T J(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
DS9014/A-11 April 2011
RT9014/A
For recommended operating conditions specification of
RT9014/A, the maximum junction temperature is 125°C.
The junction to ambient thermal resistance (θJA is layout
dependent) for WDFN-10L 3x3 package is 108°C/W on
the standard JEDEC 51-3 single-layer thermal test board.
The maximum power dissipation at TA = 25°C can be
calculated by following formula :
P D(MAX) = ( 125°C − 25°C ) / 108 = 0.926W for
WDFN-10L 3x3 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance θJA . For RT9014/A packages, the Figure 3 of
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
allowed.
1
Power Dissipation (W)
0.9
0.8
0.7
WDFN-10L 3x3
0.6
0.5
0.4
0.3
0.2
0.1
0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 3. Derating Curves for RT9014/A Packages
DS9014/A-11 April 2011
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11
RT9014/A
Outline Dimension
D2
D
L
E
E2
1
e
SEE DETAIL A
b
2
1
2
1
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
2.300
2.650
0.091
0.104
E
2.950
3.050
0.116
0.120
E2
1.500
1.750
0.059
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 10L DFN 3x3 Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
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DS9014/A-11 April 2011