A/D 8-Bit Flash MCU HT66F0182 Revision: V1.00 Date: ����������������� December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Table of Contents Features ................................................................................................................ 5 CPU Features...............................................................................................................................5 Peripheral Features.......................................................................................................................5 General Description.............................................................................................. 6 Block Diagram....................................................................................................... 6 Pin Assignment..................................................................................................... 7 Pin Description..................................................................................................... 8 Absolute Maximum Ratings................................................................................. 9 D.C. Characteristics............................................................................................ 10 A.C. Characteristics............................................................................................ 11 A/D Converter Electrical Characteristics.......................................................... 12 LVR Electrical Characteristics........................................................................... 12 Bandgap Reference Voltage Characteristics – VBG........................................................................ 12 Power-on Reset Electrical Characteristics....................................................... 13 System Architecture........................................................................................... 13 Clocking and Pipelining...............................................................................................................13 Program Counter.........................................................................................................................14 Stack ..........................................................................................................................................15 Arithmetic and Logic Unit – ALU.................................................................................................15 Flash Program Memory...................................................................................... 16 Structure .....................................................................................................................................16 Special Vectors...........................................................................................................................16 Look-up Table..............................................................................................................................16 Table Program Example..............................................................................................................17 In Circuit Programming – ICP.....................................................................................................18 On-Chip Debug Support – OCDS...............................................................................................19 RAM Data Memory.............................................................................................. 19 Structure......................................................................................................................................19 General Purpose Data Memory..................................................................................................19 Special Purpose Data Memory...................................................................................................19 Special Function Register Description............................................................. 21 Indirect Addressing Register – IAR0, IAR1.................................................................................21 Memory Pointer – MP0, MP1......................................................................................................21 Accumulator – ACC.....................................................................................................................22 Program Counter Low Register – PCL........................................................................................22 Look-up Table Register – TBLP, TBHP, TBLH.............................................................................22 Status Register – STATUS..........................................................................................................22 Rev. 1.00 2 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Oscillators........................................................................................................... 24 Oscillator Overview.....................................................................................................................24 System Clock Configurations......................................................................................................24 Internal RC Oscillator – HIRC.....................................................................................................25 Internal 32kHz Oscillator – LIRC.................................................................................................25 Supplementary Oscillators..........................................................................................................25 Operating Modes and System Clocks.............................................................. 26 System Clocks............................................................................................................................26 System Operation Modes............................................................................................................27 Control Register..........................................................................................................................28 Operating Mode Switching..........................................................................................................30 Standby Current Considerations.................................................................................................34 Wake-up......................................................................................................................................34 Watchdog Timer.................................................................................................. 35 Watchdog Timer Clock Source....................................................................................................35 Watchdog Timer Control Register...............................................................................................35 Watchdog Timer Operation.........................................................................................................36 Reset and Initialisation....................................................................................... 37 Reset Functions..........................................................................................................................37 Reset Initial Conditions...............................................................................................................40 Input/Output Ports.............................................................................................. 42 Pull-high Resistors......................................................................................................................42 Port A Wake-up...........................................................................................................................43 I/O Port Control Registers...........................................................................................................43 I/O Pin Structures........................................................................................................................44 Programming Considerations......................................................................................................45 Timer Modules – TM........................................................................................... 46 Introduction.................................................................................................................................46 TM Operation..............................................................................................................................46 TM Clock Source.........................................................................................................................46 TM Interrupt.................................................................................................................................47 TM External Pins.........................................................................................................................47 TM Input/Output Pin Control Register.........................................................................................47 Programming Considerations......................................................................................................49 Standard Type TM – STM................................................................................... 50 Standard Type TM Operation......................................................................................................50 Standard Type TM Register Description.....................................................................................50 Standard Type TM Operating Modes..........................................................................................55 Periodic Type TM – PTM..................................................................................... 65 Periodic Type TM Operation.......................................................................................................65 Periodic Type TM Register Description.......................................................................................65 Periodic Type TM Operating Modes............................................................................................70 Rev. 1.00 3 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Analog to Digital Converter – ADC.................................................................... 79 A/D Converter Overview.............................................................................................................79 A/D Converter Register Description............................................................................................79 A/D Converter Operation ............................................................................................................83 A/D Converter Reference Voltage...............................................................................................84 A/D Converter Input Signals........................................................................................................84 Conversion Rate and Timing Diagram........................................................................................85 Summary of A/D Conversion Steps.............................................................................................86 Programming Considerations......................................................................................................86 A/D Conversion Function............................................................................................................87 A/D Conversion Programming Examples....................................................................................88 Interrupts............................................................................................................. 90 Interrupt Registers.......................................................................................................................90 Interrupt Operation......................................................................................................................94 External Interrupt.........................................................................................................................95 Multi-function Interrupt................................................................................................................96 A/D Converter Interrupt...............................................................................................................96 Time Base Interrupt ....................................................................................................................96 TM Interrupts...............................................................................................................................97 Interrupt Wake-up Function.........................................................................................................98 Programming Considerations......................................................................................................98 Application Circuits............................................................................................ 99 Instruction Set................................................................................................... 100 Introduction...............................................................................................................................100 Instruction Timing......................................................................................................................100 Moving and Transferring Data...................................................................................................100 Arithmetic Operations................................................................................................................100 Logical and Rotate Operation...................................................................................................101 Branches and Control Transfer.................................................................................................101 Bit Operations...........................................................................................................................101 Table Read Operations.............................................................................................................101 Other Operations.......................................................................................................................101 Instruction Set Summary................................................................................. 102 Table Conventions.....................................................................................................................102 Instruction Definition........................................................................................ 104 Package Information........................................................................................ 113 16-pin NSOP (150mil) Outline Dimensions............................................................................... 114 20-pin NSOP (150mil) Outline Dimensions............................................................................... 115 Rev. 1.00 4 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Features CPU Features • Operating Voltage ♦♦ fSYS = 8MHz: 2.2V~5.5V • Up to 0.5μs instruction cycle with 8 MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Oscillators ♦♦ Internal RC – HIRC ♦♦ Internal 32kHz RC – LIRC • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • Fully integrated internal 8 MHz oscillator requires no external components • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • 6-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 4K×16 • RAM Data Memory: 128×8 • Watchdog Timer function • 18 bidirectional I/O lines • Two pin-shared external interrupts • Multiple Timer Modules for time measure, input capture, compare match output, PWM output or single pulse output functions • Dual Time-Base functions for generation of fixed time interrupt signals • 8-channel 12-bit resolution A/D converter • Low voltage reset function • Package type: 16-pin/20-pin NSOP Rev. 1.00 5 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU General Description The device is a Flash Memory type 8-bit high performance RISC architecture microcontroller. Offering users the convenience of Flash Memory multi-programming features, the device also includes a wide range of functions and features. Other memory includes an area of RAM Data Memory. Analog features include a multi-channel 12-bit Analog-to-Digital converter function. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Protective features such as an internal Watchdog Timer, Low Voltage Reset coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of internal high and low oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimize power consumption. The inclusion of flexible I/O programming features, Time-Base functions along with many other features ensure that the device will find excellent use in applications such as electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. Block Diagram Flash P�og�a��ing Ci��uit�y Flash P�og�a� Me�o�y Low Voltage Reset RAM Data Me�o�y Reset Ci��uit 8-�it RISC MCU Co�e Inte��upt Cont�olle� Ti�e Base Wat�hdog Ti�e� Inte�nal RC Os�illato�s I/O Rev. 1.00 Ti�e� Modules 6 1�-�it A/D Conve�te� December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Pin Assignment VSS/AVSS 1 16 VDD/AVDD PC� � 1� PB1/INT1/AN1 PA0/STP/STPI/ICPDA/OCDSDA 3 14 PB�/STCK/AN� PA1 4 13 PA4/PTCK/AN3 PA�/ICPCK/OCDSCK � 1� PA�/AN4/VREF PA3 6 11 PA6/AN� PB6 � 10 PA�/PTP/PTPI/AN6 PB� 8 9 PB4/CLO HT66F0182/HT66V0182 16 NSOP-A VSS/AVSS 1 �0 VDD/AVDD PC0 � 19 PB0/INT0/AN0 PC1 3 18 PB1/INT1/AN1 PC� 4 1� PB�/STCK/AN� PA0/STP/STPI/ICPDA/OCDSDA � 16 PA4/PTCK/AN3 PA1 6 1� PA�/AN4/VREF PA�/ICPCK/OCDSCK � 14 PA6/AN� PA3 8 13 PA�/PTP/PTPI/AN6 PB6 9 1� PB3/AN� PB� 10 11 PB4/CLO HT66F0182/HT66V0182 20 NSOP-A Note: 1. If the pin-shared pin functions have multiple outputs then the function to the right side of the “/” sign will have priority. 2. VDD/AVDD means that VDD and AVDD are bonded together.VSS/AVSS means that VSS and AVSS bonded together. 3. The OCDSDA and OCDSCK pins are used as the dedicated OCDS pins and as such only appear on the HT66V0182 device which is the OCDS EV chip for the HT66F0182 device. Rev. 1.00 7 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Pin Description With the exception of the power pins, all pins on the device can be referenced by their port name, e.g. PA0, PA1 etc, which refer to the digital I/O function of the pins. However these port pins are also shared with other function such as the Analog to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. Pin Name PA0/STP/STPI/ICPDA /OCDSDA PA1 PA2/ICPCK/OCDSCK PA3 PA4/PTCK/AN3 PA5/AN4/VREF PA6/AN5 PA7/PTP/PTPI/AN6 PB0/INT0/AN0 PB1/INT1/AN1 PB2/STCK/AN2 PB3/AN7 Rev. 1.00 Function OPT PA0 PAPU PAWU I/T O/T Description ST General purpose I/O. Register enabled pull-high and CMOS wake-up. CMOS STM output STP TMPC — STPI TMPC ST ICPDA — ST CMOS ICP Address/Data OCDSDA — ST CMOS OCDS Address/Data, for EV chip only PA1 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PA2 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. — STM capture input ICPCK — ST — ICP Clock pin OCDSCK — ST — OCDS Clock pin, for EV chip only PA3 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PA4 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PTCK PTMC0 ST — PTM clock input AN3 ACERL AN — A/D converter input channel 3 PA5 PAPU PAWU ST CMOS AN4 ACERL AN — A/D converter input channel 4 VREF ADCR1 AN — A/D converter reference voltage input pin PA6 PAPU PAWU ST CMOS AN5 ACERL AN — PA7 PAPU PAWU ST CMOS CMOS PTM output General purpose I/O. Register enabled pull-high and wake-up. General purpose I/O. Register enabled pull-high and wake-up. A/D converter input channel 5 General purpose I/O. Register enabled pull-high and wake-up. PTP TMPC — PTPI TMPC ST — PTM capture input AN6 ACERL AN — A/D converter input channel 6 PB0 PBPU ST INT0 INTC0 INTEG ST AN0 ACERL AN PB1 PBPU ST INT1 INTC2 INTEG ST AN1 ACERL AN PB2 PBPU ST STCK STMC0 ST — STM clock input AN2 ACERL AN — A/D converter input channel 2 PB3 PBPU ST AN7 ACERL AN CMOS General purpose I/O. Register enabled pull-high. — External Interrupt 0 — A/D converter input channel 0 CMOS General purpose I/O. Register enabled pull-high. — External Interrupt 1 — A/D converter input channel 1 CMOS General purpose I/O. Register enabled pull-high. CMOS General purpose I/O. Register enabled pull-high. — 8 A/D converter input channel 7 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Pin Name PB4/CLO PB5 PB6 Function OPT I/T PB4 PBPU ST CMOS General purpose I/O. Register enabled pull-high. O/T Description CLO TMPC ST CMOS System clock output PB5 PBPU ST CMOS General purpose I/O. Register enabled pull-high. PB6 PBPU ST CMOS General purpose I/O. Register enabled pull-high. PC0 ~ PC2 PCPU ST CMOS General purpose I/O. Register enabled pull-high. VDD* VDD — PWR — Power Supply AVDD* AVDD — PWR — A/D Converter Power Supply VSS** VSS — PWR — Ground AVSS** AVSS — PWR — A/D Converter Ground PC0 ~ PC2 Note: I/T: Input type; O/T: Output type; OP: Optional by register option; PWR: Power; ST: Schmitt Trigger input; CMOS: CMOS output; AN: Analog signal. *: VDD is the device power supply while AVDD is the A/D converter power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the A/D converter ground pin. The AVSS pin is bonded together internally with VSS. Absolute Maximum Ratings Supply Voltage............................................................................................................VSS-0.3V to 6.0V Input Voltage...................................................................................................... VSS-0.3V to VDD+0.3V Storage Temperature...................................................................................................... -50°C to 125°C Operating Temperature.................................................................................................... -40°C to 85°C IOL Total........................................................................................................................................ 80mA IOH Total....................................................................................................................................... -80mA Total Power Dissipation............................................................................................................ 500mW Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 9 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU D.C. Characteristics Ta=25°C Symbol VDD Parameter Operating voltage (HIRC) Operating current (HIRC) IDD Operating current (LIRC) ISTB 5.5 V 0.8 1.2 mA 5V — 1.6 2.4 mA No load, all peripherals off, fSYS = fLIRC = 32kHz — 10 20 μA — 30 50 μA No load, all peripherals off, WDT off — 0.2 0.8 μA — 0.5 1 μA No load, all peripherals off, WDT on — 1.5 3 μA — 3 5 μA No load, all peripherals off, fSUB on — 3 5 μA — 5 10 μA No load, all peripherals off, fSUB on, fSYS = fHIRC = 8MHz — 360 500 μA 5V — 600 800 μA 3V VOL = 0.1VDD 16 32 — mA 5V VOL = 0.1VDD 32 64 — mA 3V VOH = 0.9VDD -3.75 -7.5 — mA 5V VOH = 0.9VDD -7.5 -15 — mA 3V 5V Standby current (IDLE1 mode, HIRC) 3V VIL Input low voltage for I/O ports Rev. 1.00 — — 3V Pull-high resistance for I/O ports Input high voltage for I/O ports Unit 2.2 Standby current (IDLE0 mode) RPH Max. fSYS = fHIRC = 8MHz 3V Source current for I/O ports Typ. No load, all peripherals off, fSYS = fHIRC = 8MHz Standby current (SLEEP1 mode) IOH Min. — Standby current (SLEEP0 mode) Sink current for I/O port Conditions 3V 3V IOL VIH Test Conditions VDD 5V 5V 5V 3V — 20 60 100 kΩ 5V — 10 30 50 kΩ 5V — 0 — 1.5 V — — 0 — 0.2VDD V 5V — 3.5 — 5 V — — 0.8VDD — VDD V 10 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU A.C. Characteristics Ta=25°C Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit MHz fSYS System clock (HIRC) 2.2V~5.5V fSYS = fHIRC = 8MHz — 8 — fSYS System clock (LIRC) 2.2V~5.5V fSYS = fLIRC = 32kHz — 32 — kHz fHIRC High speed internal RC oscillator (HIRC) 3V/5V Ta = 25°C -2% 8 +2% MHz 3V/5V Ta = 0°C ~ 70°C -5% 8 +5% MHz 2.2V~5.5V Ta = 0°C ~ 70°C -7% 8 +7% MHz 2.2V~5.5V Ta = -40°C ~ 85°C -10% 8 +10% MHz 3V fLIRC Low speed internal RC oscillator(LIRC) -10% 32 +10% kHz 3V ± 0.3V Ta = -40°C ~ 85°C -40% 32 +40% kHz 2.2V~5.5V Ta = -40°C ~ 85°C -50% 32 +60% kHz -10% 32 +10% kHz 5V± 0.5V Ta = -40°C ~ 85°C -40% 32 +40% kHz 2.2V~5.5V Ta = -40°C ~ 85°C -50% 32 +60% kHz 5V Ta = 25°C Ta = 25°C tSTART (LIRC) System Start-up timer period 5V — — — 500 μs tTCK STCK and PTCK input pin minimum pulse width — — 0.3 — — μs tTPI STPI and PTPI input pin minimum pulse width — — 0.3 — — μs tCPW TM minimum capture pulse width — — 2 — — tTMCLK — — 25 50 100 ms tRSTD System reset delay time (POR reset, LVR hardware reset, LVR software reset, WDT software reset, reset control register software reset) System reset delay time (WDT time-out hardware cold reset) — — 8.3 16.7 33.3 ms System start-up timer period (wake-up from halt, fSYS off at HALT) tSST System start-up timer period (slow mode ↔ normal mode) System start-up timer period (wake-up from halt, fSYS on at halt state) tSRESET — fSYS = fHIRC ~ fHIRC / 64 16 — — tHIRC — fSYS = fLIRC 2 — — tLIRC — fHIRC off → on (HTO = 1) 16 — — tHIRC — fSYS = fHIRC ~ fHIRC / 64 2 — — tHIRC — fSYS = fLIRC 2 — — tLIRC System start-up timer period (WDT time-out hardware cold reset) — — 0 — — tH Minimum software reset width to reset — — 45 90 120 μs Note: 1. tHIRC=1/fHIRC ; 2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. Rev. 1.00 11 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU A/D Converter Electrical Characteristics Ta=25°C Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit VDD A/D Converter Operating voltage — — 2.7 — 5.5 V VADI A/D Converter Input voltage — — 0 — VREF V VREF A/D Converter Reference voltage — — 2 — VDD V — — ±3 LSB — — ±4 LSB — 1 2 mA mA 3V DNL INL Differential Non-linearity Integral Non-linearity VREF = VDD, tADCK = 0.5μs 5V VREF = VDD, tADCK = 0.5μs 3V VREF = VDD, tADCK = 10μs 5V VREF = VDD, tADCK = 10μs 3V VREF = VDD, tADCK = 0.5μs 5V VREF = VDD, tADCK = 0.5μs 3V VREF = VDD, tADCK = 10μs 5V VREF = VDD, tADCK = 10μs No load (tADCK = 0.5μs) 5V No load (tADCK = 0.5μs) IADC Additional Current for A/D Converter enable 3V — 1.5 3 tADCK A/D Converter Clock period — — 0.5 — 10 μs tON2ST A/D Converter on-to-start Time — — 4 — — μs tADS A/D Converter Sampling time — — — 4 — tADCK tADC A/D Conversion time (Include Sample and Hold Time) — — — 16 — tADCK Note: A/D conversion time (tADC) = n (bits A/D converter) + 4 (sampling time), the conversion for each bit needs one A/D converter clock (tADCK). LVR Electrical Characteristics Ta=25°C Symbol Parameter Test Conditions Conditions VDD VDD Operating voltage — VLVR Low voltage reset voltage — ILVRBG Operating current 5V tLVR Minimum Low voltage width to reset — — LVR enable, 2.1V LVR enable, V125EN = 0 LVR enable, V125EN = 1 — Min. Typ. Max. Unit V 1.9 — 5.5 -5% 2.1 +5% V — 20 25 μA — 180 200 μA 120 240 480 μs Bandgap Reference Voltage Characteristics – VBG Ta=25°C Symbol Parameter Test Conditions Conditions VDD — Min. Typ. Max. Unit VBG Bandgap reference voltage — -3% 1.25 +3% V tBGS VBG Turn-on Stable Time — No load — — 150 μs IBG Additional current for bandgap reference with buffer — LVR disable — — 220 μA Note: The VBG voltage can be used as the A/D converter internal signal input. Rev. 1.00 12 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Power-on Reset Electrical Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD start voltage to ensure power-on reset — — — — 100 mV RRPOR VDD rising rate to ensure power-on reset — — 0.035 — — V/ms tPOR Minimum time for VDD stays at VPOR to ensure power-on reset — — 1 — — ms VDD tPOR RRPOR VPOR Ti�e System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The device takes advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes the device suitable for lowcost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. Rev. 1.00 13 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU fSYS (Syste� Clo�k) Phase Clo�k T1 Phase Clo�k T� Phase Clo�k T3 Phase Clo�k T4 P�og�a� Counte� Pipelining PC PC+1 PC+� Fet�h Inst. (PC) Exe�ute Inst. (PC-1) Fet�h Inst. (PC+1) Exe�ute Inst. (PC) Fet�h Inst. (PC+�) Exe�ute Inst. (PC+1) System Clocking and Pipelining For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. 1 MOV A�[1�H] � CALL DELAY 3 CPL [1�H] 4 : � : 6 DELAY: NOP Fet�h Inst. 1 Exe�ute Inst. 1 Fet�h Inst. � Exe�ute Inst. � Fet�h Inst. 3 Flush Pipeline Fet�h Inst. 6 Exe�ute Inst. 6 Fet�h Inst. � Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as “JMP” or “CALL” that demands a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter Rev. 1.00 Program Counter High Byte PCL Register PC11~PC8 PCL7~PCL0 14 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly. However, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into 6 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P�og�a� Counte� Top of Sta�k Sta�k Level 1 Sta�k Level � Sta�k Pointe� Sta�k Level 3 Botto� of Sta�k Sta�k Level 6 : : : P�og�a� Me�o�y Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement INCA, INC, DECA, DEC • Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.00 15 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, the Flash device offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 4K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. 000H Initialisation Vector 004H Interrupt Vectors 024H FFFH 16 bits Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialization. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the “TABRD [m]” or “TABRDL [m]” instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0. Rev. 1.00 16 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU The accompanying diagram illustrates the addressing data flow of the look-up table. Program Memory Address Last Page or TBHP Register TBLP Register Data 16 bits Register TBLH User Selected Register High Byte Low Byte Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is “F00H” which refers to the start address of the last page within the 4K Program Memory of the microcontroller. The table pointer is setup here to have an initial value of “06H”. This will ensure that the first data read from the data table will be at the Program Memory address “F06H” or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the “TABRD [m]” instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the “TABRD [m]” instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example tempreg1 db? ; temporary register #1 tempreg2 db? ; temporary register #2 : mov a, 06h ; initialise low table pointer - note that this address mov tblp, a; is referenced mov a, 0Fh; initialise high table pointer mov tbhp, a : tabrd tempreg1 ; transfers value in table referenced by table pointer data at ; program memory address F06H transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at ; program memory address F05H transferred to tempreg2 and TBLH ; in this example the data 1AH is transferred to tempreg1 and data ; 0FH to register tempreg2 : org F00h; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : Rev. 1.00 17 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows: Holtek Writer Pins MCU Programming Pins Pin Description ICPDA PA0 Programming Serial Data/Address ICPCK PA2 Programming Clock VDD VDD Power Supply VSS VSS Ground The Program Memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, taking control of the ICPDA and ICPCK pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. W�ite� Conne�to� Signals MCU P�og�a��ing Pins W�ite�_VDD VDD ICPDA PA0 ICPCK PA� W�ite�_VSS VSS * * To othe� Ci��uit Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance of * must be less than 1nF. Rev. 1.00 18 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU On-Chip Debug Support – OCDS An EV chip exists for the purposes of device emulation. This EV chip device also provides an “On-Chip Debug” function to debug the device during the development process. The EV chip and the actual MCU devices are almost functionally compatible except for the “On-Chip Debug” function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For a more detailed OCDS description, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”. Holtek e-Link Pins EV Chip Pins Pin Description OCDSDA OCDSDA On-chip Debug Support Data/Address input/output OCDSCK OCDSCK On-chip Debug Support Clock input VDD VDD Power Supply GND VSS Ground RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two banks, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The start address of the Data Memory for the device is the address 00H. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user programing for both reading and writing operations. By using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value “00H”. Rev. 1.00 19 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU 00H 01H 0�H 03H 04H 0�H 06H 0�H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 1�H 13H 14H 1�H 16H 1�H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH �0H �1H ��H �3H �4H ��H �6H ��H �8H �9H �AH �BH �CH �DH �EH �FH IAR0 MP0 40H 41H IAR1 MP1 4�H 43H 44H 4�H Unused ACC TBLH TBHP STATUS SMOD INTC0 INTC1 INTC� �0H �1H ��H �3H MFI0 MFI1 Unused �4H ��H �6H ��H �8H �9H �AH �BH �CH �DH �EH �FH 60H 61H 6�H 63H 64H 6�H 66H 6�H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH PA PAC PAPU PAWU Unused TMPC WDTC TBC CTRL LVRC Unused ADRL ADRH ADCR0 ADCR1 ACERL PB PBC PCPU Unused STMC0 3�H 33H 34H 3�H STMDH STMAL 36H 3�H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 4AH 4BH 4CH 4DH 4EH 4FH Unused INTEG STMC1 STMDL PCPU 46H 4�H 48H 49H PCL TBLP 30H 31H PC PCC Unused �0H �1H ��H �3H STMAH Unused PTMC0 PTMC1 PTMDL PTMDH PTMAL PTMAH PTMRPL PTMRPH Unused �4H ��H �6H ��H �8H �9H �AH �BH �CH �DH �EH �FH : Unused� �ead as 00H Special Data Memory Structure Rev. 1.00 20 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional sections; however several registers require a separate description in this section. Indirect Addressing Register – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in no operation. Memory Pointer – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data.section ‘data’ adres1 db? adres2 db? adres3 db? adres4 db? block db? code.section at 0 code org 00h start: mov a, 04h; setup size of block mov block, a mov a, offset adres1 ; Accumulator loaded with first RAM address mov mp0, a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.00 21 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Register – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing the “HALT” or “CLR WDT” instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. Rev. 1.00 22 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU • PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. • TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 x x x x “x”unknown Bit 7~6 Unimplemented, read as “0” Bit 5TO: Watchdog Time-Out flag 0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred. Bit 4PDF: Power down flag 0: After power up or executing the “CLR WDT” instruction 1: By executing the “HALT” instruction Bit 3OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. Rev. 1.00 23 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Oscillators Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. Fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through the registers. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. Name Freq. Internal High Speed RC Type HIRC 8MHz Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are two methods of generating the system clock, a high speed internal RC oscillator and a low speed internal RC oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically selected. The actual source clock used for each of the high speed and low speed oscillators is chosen via registers. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a nooscillator selection for either the high or low speed oscillator. High Speed Os�illato� fH HIRC P�es�ale� fH/� fH/4 fH/8 fH/16 fSYS fH/3� fH/64 fSUB HLCLK� CKS�~CKS0 �its LIRC fSUB Low Speed Os�illato� System Clock Configurations Rev. 1.00 24 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Internal RC Oscillator – HIRC The internal high speed RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 8MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of either 3V or 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 8MHz will have a tolerance within 2%. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins are free for use as normal I/O pins. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 32kHz will have a tolerance within 10%. Supplementary Oscillators The low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to two other device functions. These are the Watchdog Timer and the Time Base Interrupts. Rev. 1.00 25 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided the device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency fH or low frequency fSUB source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from the HIRC oscillator. The low speed system clock source can be sourced from the LIRC oscillator. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. High Speed Os�illato� HIRC fH P�es�ale� fH/� fH/4 fH/8 fSYS fH/16 fH/3� fH/64 fSUB LIRC Low Speed Os�illato� HLCLK� CKS�~CKS0 �its fSUB fSYS/4 fTB fTBC Ti�e Base TBCK fS Wat�hdog Ti�e� Device Clock Configurations Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. Rev. 1.00 26 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0, SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Operating Mode Description CPU fSYS fSUB fS fTBC NORMAL Mode on fH~fH/64 on on on SLOW Mode on fSUB on on on IDLE0 Mode off off on on on IDLE1 Mode off on on on on SLEEP0 Mode off off off off off SLEEP1 Mode off off on on off Normal Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator. This mode operates allowing the microcontroller to operate normally with a clock source will come from o the high speed oscillator HIRC. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. Slow Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from the low speed oscillator – LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. SLEEP0 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fSUB and fS clocks will be stopped too, and the Watchdog Timer function is disabled. SLEEP1 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fSUB and fS clocks will continue to operate if the Watchdog Timer function is enabled and if its clock source is chosen via registers to come from fSUB. IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer and TMs. In the IDLE0 Mode, the system oscillator will be stopped. Rev. 1.00 27 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. Control Register The SMOD and CTRL registers are used to control the internal clocks within the device. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 R/W R/W R/W CKS0 — LTO HTO IDLEN HLCLK R/W — R R R/W POR 0 0 R/W 0 — 0 0 1 1 Bit 7~5CKS2~CKS0: The system clock selection when HLCLK is “0” 000: fSUB (fLIRC) 001: fSUB (fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as “0” Bit 3LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after 1~2 clock cycles. Bit 2HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to “0” by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as “1” by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wakeup has occurred, the flag will change to a high level after 15~16 clock cycles. Rev. 1.00 28 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Bit 1IDLEN: IDLE Mode control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Bit 0HLCLK: system clock selection 0: fH/2 ~ fH/64 or fSUB 1: fH This bit is used to select if the fH clock or the fH/2~fH/64 or fSUB clock is used as the system clock. When the bit is high the fH clock will be selected and if low the fH/2~fH/64 or fSUB clock will be selected. When system clock switches from the fH clock to the fSUB clock and the fH clock will be automatically switched off to conserve power. CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — R/W R/W — — — — LVRF LRF WRF R/W R/W POR 0 — — — — R/W x 0 0 “x”unknown Bit 7FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Bit 6~3 Unimplemented, read as “0” Bit 2LVRF: LVR function reset flag Described elsewhere Bit 1LRF: LVRC control register software reset flag Described elsewhere Bit 0WRF: WDTC control register software reset flag Described elsewhere Rev. 1.00 29 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fSUB. If the clock is from the fSUB, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs. The accompanying flowchart shows what happens when the device moves between the various operating modes. IDLE1 HALT inst�u�tion exe�uted CPU stop IDLEN=1 FSYSON=1 fSYS on fTBC on fSUB on NORMAL fSYS=fH~fH/64 fH on CPU �un fSYS on fTBC on fSUB on SLEEP0 HALT inst�u�tion exe�uted fSYS off CPU stop IDLEN=0 fTBC off fSUB off WDT off IDLE0 HALT inst�u�tion exe�uted CPU stop IDLEN=1 FSYSON=0 fSYS off fTBC on fSUB on SLEEP1 HALT inst�u�tion exe�uted fSYS off CPU stop IDLEN=0 fTBC off fSUB on WDT on Rev. 1.00 SLOW fSYS=fSUB CPU �un fSYS on fTBC on fSUB on fH off 30 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to “0” and set the CKS2~CKS0 bits to “000” or “001” in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillator and therefore requires the oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. NORMAL Mode CKS�~CKS0 = 00xB & HLCLK = 0 SLOW Mode WDT off IDLEN=0 HALT inst�u�tion is exe�uted SLEEP0 Mode WDT on IDLEN=0 HALT inst�u�tion is exe�uted SLEEP1 Mode IDLEN=1� FSYSON=0 HALT inst�u�tion is exe�uted IDLE0 Mode IDLEN=1� FSYSON=1 HALT inst�u�tion is exe�uted IDLE1 Mode Rev. 1.00 31 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses the LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to “1” or HLCLK bit is “0”, but CKS2~CKS0 is set to “010”, “011”, “100”, “101”, “110” or “111”. As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. SLOW Mode CKS2~CKS0 ≠ 000B or 001B as HLCLK = 0 or HLCLK = 1 NORMAL Mode WDT off IDLEN=0 HALT instruction is executed SLEEP0 Mode WDT on IDLEN=0 HALT instruction is executed SLEEP1 Mode IDLEN=1, FSYSON=0 HALT instruction is executed IDLE0 Mode IDLEN=1, FSYSON=1 HALT instruction is executed IDLE1 Mode Rev. 1.00 32 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the WDT is off. When this instruction is executed under the conditions described above, the following will occur: • The system clock, WDT clock and Time Base clock will be stopped and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and stopped no matter if the WDT clock source originates from the fSUB clock or from the system clock. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the SLEEP1 Mode There is only one way for the device to enter the SLEEP1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the WDT is on. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock will be stopped and the application program will stop at the “HALT” instruction, but the WDT will remain with the clock source coming from the fSUB clock. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. The WDT will be cleared and stop counting if the WDT is disabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in CTRL register equal to “0”. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the “HALT” instruction, but the Time Base clock and fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. The WDT will be cleared and stop counting if the WDT is disabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.00 33 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in CTRL register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock and fSUB clock will be on and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. The WDT will be cleared and stop counting if the WDT is disabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to the device which has different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred microamps. Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow If the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the “HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Rev. 1.00 34 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by the LIRC oscillator. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation and MCU reset function. This register controls the overall operation of the Watchdog Timer. WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3WE4~WE0: WDT function software control 10101: Disable 01010: Enable Other: Reset MCU When these bits are changed by the environmental noise or software setting to reset the microcontroller, the reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit in the CTRL register will be set to 1. Bit 2~0WS2~WS0: WDT time-out period selection 000: 28/fS 001: 210/fS 010: 212/fS 011: 214/fS 100: 215/fS 101: 216/fS 110: 217/fS 111: 218/fS Rev. 1.00 35 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W POR 0 — — — — x 0 0 “x” unknown Bit 7FSYSON: fSYS Control in IDLE Mode Described elsewhere Bit 6~3 Unimplemented, read as “0” Bit 2LVRF: LVR function reset flag Describe elsewhere Bit 1LRF: LVR Control register software reset flag Described elsewhere Bit 0WRF: WDT Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/disable function, there are also five bits, WE4~WE0, in the WDTC register to offer additional enable/disable and reset control of the Watchdog Timer. The WDT function will be disabled when the WE4~WE0 bits are set to a value of 10101B. The WDT function will be enabled if the WE4~WE0 bits value is equal to 01010B. If the WE4~WE0 bits are set to any other values by the environmental noise or software setting, except 01010B and 10101B, it will reset the device after 2~3 LIRC clock cycles. After power on these bits will have the value of 01010B. Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 bit filed, the second is using the Watchdog Timer software clear instructions and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single “CLR WDT” instruction to clear the WDT. The maximum time out period is when the 218 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. Rev. 1.00 36 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU WDTC Register WE4~WE0 bits Reset MCU CLR ʺHALTʺ Instruction ʺCLR WDTʺ Instruction fSUB fS 8-stage Divider fS/28 WS2~WS0 WDT Prescaler WDT Time-out (28/fS ~ 218/fS) 8-to-1 MUX (fS/28 ~ fS/218) Watchdog Timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are several ways in which a reset can occur, through events occurring internally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all I/O ports will be first set to inputs. VDD Powe�-on Reset tRSTD SST Ti�e-out Power-on Reset Timing Chart Rev. 1.00 37 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is always enabled with a specific LVR voltage, VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the CTRL register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the LVR Electrical characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR is fixed at a voltage value of 2.1V. If the LVS7~LVS0 bits are changed to some certain values by the environmental noise or software setting, the LVR will reset the device after 2~3 LIRC clock cycles. When this happens, the LRF bit in the CTRL register will be set to 1. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the SLEEP or IDLE mode. LVR tRSTD + tSST Inte�nal Reset Low Voltage Reset Timing Chart • LVRC Register Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0LVS7~LVS0: LVR voltage select 01010101: 2.1V 00110011: 2.1V 10011001: 2.1V 10101010: 2.1V Any other value: Generates MCU reset – LVRC register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage values above, an MCU reset will be generated. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the defined LVR values above, will also result in the generation of an MCU reset. The reset operation will be activated after 2~3 LIRC clock cycles. However in this situation the register contents will be reset to the POR value. Rev. 1.00 38 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU • CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W POR 0 — — — — x 0 0 “x” unknown Bit 7FSYSON: fSYS Control in IDLE Mode Described elsewhere. Bit 6~3 Unimplemented, read as “0” Bit 2LVRF: LVR function reset flag 0: Not occur 1: Occurred This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This bit can only be cleared to 0 by the application program. Bit 1LRF: LVR Control register software reset flag 0: Not occur 1: Occurred This bit is set to 1 if the LVRC register contains any non-defined LVR voltage register values. This in effect acts like a software reset function. This bit can only be cleared to 0 by the application program. Bit 0WRF: WDT Control register software reset flag Described elsewhere. Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as a hardware LVR reset except that the Watchdog time-out flag TO will be set to “1”. WDT Ti�e-out tRSTD + tSST Inte�nal Reset WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for tSST details. WDT Ti�e-out tSST Inte�nal Reset WDT Time-out Reset during Sleep Timing Chart Rev. 1.00 39 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 Power-on reset Reset Conditions u u LVR reset during Normal or SLOW Mode operation 1 u WDT time-out reset during Normal or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation Note: “u” stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition after Reset Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer Modules Timer Modules will be turned off Input / Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. Reset (Power On) WDT Time-out (Normal Operation) WDT Time-out (HALT)* MP0 xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu TBHP ---- xxxx ---- uuuu ---- uuuu STATUS --00 xxxx --1u uuuu - - 11 u u u u SMOD 0 0 0 - 0 0 11 0 0 0 - 0 0 11 uuu- uuuu INTEG ---- 0000 ---- 0000 ---- uuuu INTC0 -0-0 0-00 -0-0 0-00 -u-u u-uu INTC1 00-0 00-0 00-0 00-0 uu-u uu-u INTC2 --00 --00 --00 --00 --uu --uu MFI0 --00 --00 --00 --00 --uu --uu MFI1 --00 --00 --00 --00 --uu --uu PA 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 uuuu uuuu PAPU 0000 0000 0000 0000 uuuu uuuu PAWU 0000 0000 0000 0000 uuuu uuuu TMPC 0--- --00 0--- --00 u--- --uu Register Rev. 1.00 40 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Reset (Power On) WDT Time-out (Normal Operation) WDT Time-out (HALT)* WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 uuuu uuuu TBC 0 0 11 - 111 0 0 11 - 111 uuuu -uuu CTRL 0--- -x00 0--- -000 u--- -uuu LVRC 0101 0101 0101 0101 uuuu uuuu ADRL(ADRFS=0) xxxx ---- xxxx ---- uuuu ---- ADRL(ADRFS=1) xxxx xxxx xxxx xxxx uuuu uuuu ADRH(ADRFS=0) xxxx xxxx xxxx xxxx uuuu uuuu ADRH(ADRFS=1) ---- xxxx ---- xxxx ---- uuuu ADCR0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 uuu- -uuu ADCR1 00-0 -000 00-0 -000 uu-u -uuu ACERL 1111 1111 1111 1111 uuuu uuuu PB - 111 1111 - 111 1111 -uuu uuuu PBC - 111 1111 - 111 1111 -uuu uuuu PBPU -000 0000 -000 0000 -uuu uuuu STMC0 0000 0000 0000 0000 uuuu uuuu STMC1 0000 0000 0000 0000 uuuu uuuu STMDL 0000 0000 0000 0000 uuuu uuuu STMDH ---- --00 ---- --00 ---- --uu STMAL 0000 0000 0000 0000 uuuu uuuu STMAH ---- --00 ---- --00 ---- --uu PTMC0 0000 0--- 0000 0--- uuuu u--- PTMC1 0000 0000 0000 0000 uuuu uuuu PTMDL 0000 0000 0000 0000 uuuu uuuu PTMDH ---- --00 ---- --00 ---- --uu PTMAL 0000 0000 0000 0000 uuuu uuuu PTMAH ---- --00 ---- --00 ---- --uu PTMRPL 0000 0000 0000 0000 uuuu uuuu PTMRPH ---- --00 ---- --00 ---- --uu PC - - - - - 111 - - - - - 111 ---- -uuu PCC - - - - - 111 - - - - - 111 ---- -uuu PCPU ---- -000 ---- -000 ---- -uuu Register Note: “u” stands for unchanged “x” stands for unknown “-” stands for unimplemented Rev. 1.00 41 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PC. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Bit Register Name 7 6 5 4 3 2 1 0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PB — PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC — PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU — PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PC — — — — — PC2 PC1 PC0 PCC — — — — — PCC2 PCC1 PCC0 PCPU — — — — — PCPU2 PCPU1 PCPU0 I/O Logic Function Register List Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PCPU, and are implemented using weak PMOS transistors. PAPU Register Bit 7 6 5 4 3 2 1 0 Name PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PAPU7~PAPU0: Port A bit 7 ~ bit 0 Pull-high Control 0: Disable 1: Enable Rev. 1.00 42 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU PBPU Register Bit 7 6 5 4 3 2 1 0 Name — PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as “0” Bit 6~0PBPU6~PBPU0: Port B bit 6 ~ bit 0 Pull-high Control 0: Disable 1: Enable PCPU Register Bit 7 6 5 4 3 2 1 0 Name — — — — — PCPU2 PCPU1 PCPU0 R/W — — — — — R/W R/W R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as “0” Bit 2~0PCPU2~PCPU0: Port C bit 3 ~ bit 0 Pull-high Control 0: Disable 1: Enable Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. PAWU Register Bit 7 6 5 4 3 2 1 0 Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PAWU7~PAWU0: Port A bit 7 ~ bit 0 Wake-up Control 0: Disable 1: Enable Rev. 1.00 43 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU I/O Port Control Registers Each I/O port has its own control register known as PAC~PCC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a “1”. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a “0”, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. PAC Register Bit 7 6 5 4 3 2 1 0 Name PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0PAC7~PAC0: Port A bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input PBC Register Bit 7 6 5 4 3 2 1 0 Name — PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 1 1 1 1 1 1 1 Bit 7 Unimplemented, read as “0” Bit 6~0PBC6~PBC0: Port B bit 6 ~ bit 0 Input/Output Control 0: Output 1: Input PCC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — PCC2 PCC1 PCC0 R/W — — — — — R/W R/W R/W POR — — — — — 1 1 1 Bit 7~3 Unimplemented, read as “0” Bit 2~0PCC2~PCC0: Port C bit 2 ~ bit 0 Input/Output Control 0: Output 1: Input Rev. 1.00 44 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU I/O Pin Structures The accompanying diagram illustrates the internal structure of the I/O logic function. As the exact logical construction of the I/O pin will differ from this diagram, it is supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. VDD Control Bit Data Bus Write Control Register Chip Reset Read Control Register D Weak Pull-up CK Q S I/O pin Data Bit D Write Data Register Q Pull-high Register Select Q CK Q S Read Data Register System Wake-up M U X wake-up Select PA only Logic Function Input/Output Structure Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PCC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PC, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. The power-on reset condition of the A/D converter control registers ensures that any A/D input pins - which are always shared with other I/O functions - will be setup as analog inputs after a reset. Although these pins will be configured as A/D inputs after a reset, the A/D converter will not be switched on. It is therefore important to note that if it is required to use these pins as I/O digital input pins or as other functions, the A/D converter control registers must be correctly programmed to remove the A/D function. Note also that as the A/D channel is enabled, any internal pull-high resistor connections will be removed. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.00 45 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Standard and Periodic Types TM sections. Introduction The device contains a 10-bit Standard Type TM named as STM and a 10-bit Periodic Type TM named as PTM. Although similar in nature, the different types of TM vary in their feature complexity. The common features to all of the Standard and Periodic TMs will be described in this section, the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the two types of TMs are summarised in the accompanying table. STM PTM Timer/Counter Function √ √ I/P Capture √ √ Compare Match Output √ √ PWM Channels 1 1 Single Pulse Output 1 1 Edge Edge Duty or Period Duty or Period PWM Alignment PWM Adjustment Period & Duty TM Function Summary TM Operation The two different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the STCK2~STCK0 and PTCK2~PTCK0 bits in the STM and PTM control registers respectively. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fTBC clock source or the external STCK and PTCK pin. The STCK and PTCK pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. Rev. 1.00 46 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU TM Interrupt The Standard Type and Periodic Type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has two TM input pins, with the label STCK, PTCK and STPI, PTPI respectively. The TM input pin, STCK, PTCK, is essentially a clock source for the TM and is selected using the STCK2~STCK0 or PTCK2~PTCK0 bits in the STMC0 or PTMC0 register respectively. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the STCK2~STCK0 or PTCK2~PTCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The other TM input pins, STPI, PTPI, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the STIO1~STIO0, PTIO1~PTIO0 bits in the STMC1, PTMC1 register respectively. There is another capture input, PTCK, for PTM capture input mode, which can be used as the external trigger input source except the PTPI pin. The TMs each has one output pin with the label STP and PTP. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external STP, PTP output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other functions, the TM output function is enabled or disabled according to the internal TM on/ off control, operation mode and output control settings. When the corresponding TM configuration selects the STP or PTP pin to be used as an output pin, the associated pin will be setup as an external TM output pin. If the TM configuration selects the STP or PTP pin to be setup as an input pin, the input signal supplied on the associated pin can be derived from an external signal and other pinshared output function. If the TM configuration determines that the STP or PTP pin function is not used, the associated pin will be controlled by other pin-shared functions. The details of the external pins for each TM type and device are provided in the accompanying table. STM PTM Input Output Input Output STCK, STPI STP PTCK, PTPI PTP TM External Pins TM Input/Output Pin Control Register Selecting to have a TM input/output or whether to retain its other shared functions is implemented using one register with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output if reset to zero the pin will retain its original other functions. Rev. 1.00 47 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU PA0 Output Fun�tion 0 PA0/STP/STPI 1 0 Output 1 10-bit STM T0CP PA0 Captu�e Input TCK Input PB�/STCK STM Function Pin Control Block Diagram PA� Output Fun�tion 0 PA�/PTP/PTPI 1 0 Output T1CP 1 PA� 10-bit PTM Captu�e Input 1 0 0 1 PTCAPTS TCK Input PA4/PTCK PTM Function Pin Control Block Diagram TMPC Register Bit 7 6 5 4 3 2 1 0 Name CLOP — — — — — T1CP T0CP R/W R/W — — — — — R/W R/W POR 0 — — — — — 0 0 Bit 7CLOP: CLO pin control 0: Disable 1: Enable Bit 6~2 Unimplemented, read as “0” Bit 1T1CP: PTP pin control 0: Disable 1: Enable Bit 0T0CP: STP pin control 0: Disable 1: Enable Rev. 1.00 48 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and PTM CCRP registers is implemented in the way shown in the following diagram and accessing the register is carried out in a specific way described above, it is recommended to use the “MOV” instruction to access the CCRA or PTM CCRP low byte register, named STMAL,PTMAL and PTMRPL, using the following access procedures. Accessing the CCRA or PTM CCRP low byte register without following these access procedures will result in unpredictable values. PTM Counte� Registe� (Read only) PTMDL PTMDH STM Counte� Registe� (Read only) STMDL 8-�it Buffe� STMDH 8-�it Buffe� PTMAL PTMAH PTM CCRA Registe� (Read/W�ite) STMAL STMAH PTMRPL STM CCRA Registe� (Read/W�ite) Data Bus PTMRPH PTM CCRP Registe� (Read/W�ite) Data Bus The following steps show the read and write procedures: • Writing Data to CCRA or PTM CCRP ♦♦ Step 1. Write data to Low Byte STMAL, PTMAL or PTMRPL ––Note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte STMAH, PTMAH or PTMRPH ––Here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA or PTM CCRP Rev. 1.00 ♦♦ Step 1. Read data from the High Byte STMDH, PTMDH, STMAH, PTMAH or PTMRPH ––Here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte STMDL, PTMDL, STMAL, PTMAL or PTMRPL ––This step reads data from the 8-bit buffer. 49 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard Type TM can also be controlled with two external input pins and can drive one external output pin. CCRP 3-�it Co�pa�ato� P fSYS/4 fSYS fH/16 fH/64 fTBC fH/8 STCK 000 001 010 011 100 101 110 111 Co�pa�ato� P Mat�h STOC ��~�9 Counte� Clea� 0 1 10-�it Count-up Counte� STON STPAU STCK�~STCK0 STCCLR �0~�9 10-�it Co�pa�ato� A STMPF Inte��upt Co�pa�ato� A Mat�h Output Cont�ol Pola�ity Cont�ol STM1� STM0 STIO1� STIO0 STPOL STP STMAF Inte��upt STIO1� STIO0 Edge Dete�to� CCRA STPI Standard Type TM Block Diagram Standard Type TM Operation There is a 10-bit wide STM. At the core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 3-bit wide whose value is compared with the highest 3 bits in the counter while the CCRA is 10 bits and therefore compares all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the STON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a STM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Standard Type TM Register Description Overall operation of the Standard Type TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the CCRP bits. Rev. 1.00 50 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Bit Register Name 7 6 5 4 3 2 1 0 STMC0 STPAU STCK2 STCK1 STCK0 STON STRP2 STRP1 STRP0 STMC1 STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR D0 STMDL D7 D6 D5 D4 D3 D2 D1 STMDH — — — — — — D9 D8 STMAL D7 D6 D5 D4 D3 D2 D1 D0 STMAH — — — — — — D9 D8 10-bit Standard Type TM Register List STMC0 Register Bit 7 6 5 4 3 2 1 0 Name STPAU STCK2 STCK1 STCK0 STON STRP2 STRP1 STRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7STPAU: STM Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the STM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4STCK2~STCK0: Select STM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: fH/8 110: STCK rising edge clock 111: STCK falling edge clock These three bits are used to select the clock source for the STM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3STON: STM Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the STM. Setting the bit high enables the counter to run, clearing the bit disables the STM. Clearing this bit to zero will stop the counter from counting and turn off the STM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the STM is in the Compare Match Output Mode then the STM output pin will be reset to its initial condition, as specified by the STOC bit, when the STON bit changes from low to high. Rev. 1.00 51 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Bit 2~0STRP2~STRP0: STM CCRP 3-bit register, compared with the STM counter bit 9~bit 7 Comparator P Match period 000: 1024 STM clocks 001: 128 STM clocks 010: 256 STM clocks 011: 384 STM clocks 100: 512 STM clocks 101: 640 STM clocks 110: 768 STM clocks 111: 896 STM clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the STCCLR bit is set to zero. Setting the STCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. STMC1 Register Bit 7 6 5 4 3 2 1 0 Name STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6STM1~STM0: Select STM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the STM. To ensure reliable operation the STM should be switched off before any changes are made to the STM1 and STM0 bits. In the Timer/Counter Mode, the STM output pin control must be disabled. Bit 5~4STIO1~STIO0: Select STP output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of STPI 01: Input capture at falling edge of STPI 10: Input capture at falling/rising edge of STPI 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the STM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the STM is running. Rev. 1.00 52 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU In the Compare Match Output Mode, the STIO1 and STIO0 bits determine how the STM output pin changes state when a compare match occurs from the Comparator A. The STM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the STM output pin should be setup using the STOC bit in the STMC1 register. Note that the output level requested by the STIO1 and STIO0 bits must be different from the initial value setup using the STOC bit otherwise no change will occur on the STM output pin when a compare match occurs. After the STM output pin changes state, it can be reset to its initial level by changing the level of the STON bit from low to high. In the PWM Mode, the STIO1 and STIO0 bits determine how the STM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the STIO1 and STIO0 bits only after the STM has been switched off. Unpredictable PWM outputs will occur if the STIO1 and STIO0 bits are changed when the STM is running. Bit 3STOC: STP Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the STM output pin. Its operation depends upon whether STM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the STM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the STM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2STPOL: STP Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the STP output pin. When the bit is set high the STM output pin will be inverted and not inverted when the bit is zero. It has no effect if the STM is in the Timer/Counter Mode. Bit 1STDPX: STM PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0STCCLR: Select STM Counter clear condition 0: STM Comparatror P match 1: STM Comparatror A match This bit is used to select the method which clears the counter. Remember that the Standard Type TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the STCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The STCCLR bit is not used in the PWM Mode, Single Pulse or Input Capture Mode. Rev. 1.00 53 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU STMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: STM Counter Low Byte Register bit 7~bit 0 STM 10-bit Counter bit 7~bit 0 STMDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0D9~D8: STM Counter High Byte Register bit 1~bit 0 STM 10-bit Counter bit 9~bit 8 STMAL Register Bit 7 6 5 4 3 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: STM CCRA Low Byte Register bit 7~bit 0 STM 10-bit CCRA bit 7~bit 0 STMAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0D9~D8: STM CCRA High Byte Register bit 1~bit 0 STM 10-bit CCRA bit 9~bit 8 Rev. 1.00 54 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the STM1 and STM0 bits in the STMC1 register. Compare Match Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the STCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both STMAF and STMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the STCCLR bit in the STMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the STMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when STCCLR is high no STMPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to “0”. As the name of the mode suggests, after a comparison is made, the STM output pin, will change state. The STM output pin condition however only changes state when a STMAF interrupt request flag is generated after a compare match occurs from Comparator A. The STMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the STM output pin. The way in which the STM output pin changes state are determined by the condition of the STIO1 and STIO0 bits in the STMC1 register. The STM output pin can be selected using the STIO1 and STIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the STM output pin, which is setup after the STON bit changes from low to high, is setup using the STOC bit. Note that if the STIO1 and STIO0 bits are zero then no pin change will take place. Rev. 1.00 55 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU STCCLR = 0; STM [1:0] = 00 Counte� ove�flow Counte� Value CCRP > 0 Counte� �lea�ed �y CCRP value CCRP=0 0x3FF CCRP > 0 Counte� Resta�t Resu�e CCRP Pause CCRA Stop Ti�e STON STPAU STPOL CCRP Int. flag STMPF CCRA Int. flag STMAF STM O/P Pin Output pin set to initial Level Low if STOC=0 Output not affe�ted �y STMAF flag. Re�ains High until �eset �y STON �it Output Toggle with STMAF flag He�e STIO [1:0] = 11 Toggle Output sele�t Note STIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when STPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – STCCLR=0 Note: 1. With STCCLR=0 a Comparator P match will clear the counter 2. The TM output pin is controlled only by the STMAF flag 3. The output pin is reset to its initial state by a STON bit rising edge Rev. 1.00 56 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Counte� Value STCCLR = 1; STM [1:0] = 00 CCRA = 0 Counte� ove�flow CCRA > 0 Counte� �lea�ed �y CCRA value 0x3FF CCRA=0 Resu�e CCRA Pause Stop Counte� Resta�t CCRP Ti�e STON STPAU STPOL No STMAF flag gene�ated on CCRA ove�flow CCRA Int. flag STMAF CCRP Int. flag STMPF STM O/P Pin Output does not �hange STMPF not gene�ated Output pin set to initial Level Low if STOC=0 Output Toggle with STMAF flag He�e STIO [1:0] = 11 Toggle Output sele�t Output not affe�ted �y STMAF flag. Re�ains High until �eset �y STON �it Note STIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when STPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – STCCLR=1 Note: 1. With STCCLR=1 a Comparator A match will clear the counter 2. The TM output pin is controlled only by the STMAF flag 3. The output pin is reset to its initial state by a STON bit rising edge 4.The STMPF flag is not generated when STCCLR=1 Rev. 1.00 57 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Timer/Counter Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the STM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the STM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 10 respectively. The PWM function within the STM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the STCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the STDPX bit in the STMC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The STOC bit in the STMC1 register is used to select the required polarity of the PWM waveform while the two STIO1 and STIO0 bits are used to enable the PWM output or to force the STM output pin to a fixed high or low level. The STPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit STM, PWM Mode, Edge-aligned Mode, STDPX=0 CCRP 1~7 0 Period CCRP×128 1024 Duty CCRA If fSYS = 16MHz, STM clock source is fSYS/4, CCRP=2 and CCRA=128, The STM PWM output frequency=(fSYS/4)/(2×128)=fSYS/1024=16kHz, duty=128/(2×128)=50%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • 10-bit STM, PWM Mode, Edge-aligned Mode, STDPX=1 CCRP 1~7 Period 0 CCRA CCRP×128 Duty 1024 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value except when the CCRP value is equal to 0. Rev. 1.00 58 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Counte� Value STDPX = 0; STM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when STON �etu�ns high CCRP Pause Resu�e Counte� Stop if STON �it low CCRA Ti�e STON STPAU STPOL CCRA Int. flag STMAF CCRP Int. flag STMPF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) PWM Duty Cy�le set �y CCRA PWM Pe�iod set �y CCRP PWM �esu�es ope�ation Output �ont�olled �y othe� pin-sha�ed fun�tion Output Inve�ts when STPOL = 1 PWM Output Mode – STDPX=0 Note: 1. Here STDPX=0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when STIO [1:0] = 00 or 01 4. The STCCLR bit has no influence on PWM operation Rev. 1.00 59 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Counte� Value STDPX = 1; STM [1:0] = 10 Counte� �lea�ed �y CCRA Counte� Reset when STON �etu�ns high CCRA Pause Resu�e Counte� Stop if STON �it low CCRP Ti�e STON STPAU STPOL CCRP Int. flag STMPF CCRA Int. flag STMAF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) PWM Duty Cy�le set �y CCRP PWM Pe�iod set �y CCRA Output �ont�olled �y othe� pin-sha�ed fun�tion PWM �esu�es ope�ation Output Inve�ts when STPOL = 1 PWM Output Mode – STDPX=1 Note: 1. Here STDPX=1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when STIO [1:0] = 00 or 01 4. The STCCLR bit has no influence on PWM operation Rev. 1.00 60 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Single Pulse Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin. The trigger for the pulse output leading edge is a low to high transition of the STON bit, which can be implemented using the application program. However in the Single Pulse Mode, the STON bit can also be made to automatically change from low to high using the external STCK pin, which will in turn initiate the Single Pulse output. When the STON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The STON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the STON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the STON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a STM interrupt. The counter can only be reset back to zero when the STON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The STCCLR and STDPX bits are not used in this Mode. S/W Co��and SET“STON” o� STCK Pin T�ansition CCRA Leading Edge CCRA T�ailing Edge STON �it 0→1 STON �it 1→0 S/W Co��and CLR“STON” o� CCRA Co�pa�e Mat�h STP Output Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.00 61 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Counte� Value STM [1:0] = 10 ; STIO [1:0] = 11 Counte� stopped �y CCRA Counte� Reset when STON �etu�ns high CCRA Pause Counte� Stops �y softwa�e Resu�e CCRP Ti�e STON Softwa�e T�igge� Clea�ed �y CCRA �at�h Auto. set �y STCK pin STCK pin Softwa�e T�igge� Softwa�e Softwa�e T�igge� Clea� Softwa�e T�igge� STCK pin T�igge� STPAU STPOL CCRP Int. Flag STMPF No CCRP Inte��upts gene�ated CCRA Int. Flag STMAF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) Output Inve�ts when STPOL = 1 Pulse Width set �y CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA. 2. CCRP is not used. 3. The pulse is triggered by the STCK pin or by setting the STON bit high. 4. A STCK pin active edge will automatically set the STON bit high. 5. In the Single Pulse Mode, STIO [1:0] must be set to “11” and can not be changed. Rev. 1.00 62 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Capture Input Mode To select this mode bits STM1 and STM0 in the STMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the STPI pin, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the STIO1 and STIO0 bits in the STMC1 register. The counter is started when the STON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the STPI pin the present value in the counter will be latched into the CCRA registers and a STM interrupt generated. Irrespective of what events occur on the STPI pin the counter will continue to free run until the STON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a STM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The STIO1 and STIO0 bits can select the active trigger edge on the STPI pin to be a rising edge, falling edge or both edge types. If the STIO1 and STIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the STPI pin, however it must be noted that the counter will continue to run. The STCCLR and STDPX bits are not used in this Mode. Rev. 1.00 63 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Counte� Value STM [1:0] = 01 Counte� �lea�ed �y CCRP Counte� Stop Counte� Reset CCRP YY Pause Resu�e XX Ti�e STON STPAU A�tive edge A�tive edge A�tive edge STM �aptu�e pin STPI CCRA Int. Flag STMAF CCRP Int. Flag STMPF CCRA Value STIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge YY XX 10 – Both edges 11 – Disa�le Captu�e Capture Input Mode Note: 1. STM [1:0] = 01 and active edge set by the STIO [1:0] bits 2. A TM Capture input pin active edge transfers the counter value to CCRA 3. STCCLR bit not used 4. No output function – STOC and STPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.00 64 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic Type TM can also be controlled with two external input pins and can drive one external output pin. CCRP fSYS/4 fSYS fH/16 fH/64 fTBC fH PTCK 000 001 010 011 100 101 PTON 110 PTPAU 111 Co�pa�ato� P Mat�h 10-�it Co�pa�ato� P PTMPF Inte��upt PTOC �0~�9 PTCCLR �0~�9 10-�it Co�pa�ato� A PTCK�~PTCK0 Output Cont�ol Pola�ity Cont�ol PTM1� PTM0 PTIO1� PTIO0 PTPOL Counte� Clea� 0 1 10-�it Count-up Counte� Co�pa�ato� A Mat�h PTMAF Inte��upt PTIO1� PTIO0 PTCAPTS Edge Dete�to� 0 1 CCRA PTP PTPI Periodic Type TM Block Diagram Periodic Type TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with the CCRA and CCRP registers. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the PTON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a PTM interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control the output pin. All operating setup conditions are selected using relevant internal registers. Periodic Type TM Register Description Overall operation of the Periodic Type TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Bit Register Name 7 6 5 4 3 2 PTMC0 PTPAU PTCK2 PTCK1 PTCK0 PTON — PTMC1 PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL 1 0 — — PTCAPTS PTCCLR PTMDL D7 D6 D5 D4 D3 D2 D1 PTMDH — — — — — — D9 D0 D8 PTMAL D7 D6 D5 D4 D3 D2 D1 D0 PTMAH — — — — — — D9 D8 PTMRPL D7 D6 D5 D4 D3 D2 D1 D0 PTMRPH — — — — — — D9 D8 10-bit Periodic Type TM Register List Rev. 1.00 65 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU PTMC0 Register Bit 7 6 5 4 3 2 1 0 Name PTPAU PTCK2 PTCK1 PTCK0 PTON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7PTPAU: PTM Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the PTM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4PTCK2~PTCK0: Select PTM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: fH 110: PTCK rising edge clock 111: PTCK falling edge clock These three bits are used to select the clock source for the PTM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3PTON: PTM Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the PTM. Setting the bit high enables the counter to run, clearing the bit disables the PTM. Clearing this bit to zero will stop the counter from counting and turn off the PTM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the PTM is in the Compare Match Output Mode, PWM output Mode or Single Pulse Output Mode then the PTM output pin will be reset to its initial condition, as specified by the PTOC bit, when the PTON bit changes from low to high. Bit 2~0 Rev. 1.00 Unimplemented, read as “0” 66 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU PTMC1 Register Bit 7 6 5 4 3 2 Name PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PTCAPTS PTCCLR Bit 7~6PTM1~PTM0: Select PTM Operation Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the PTM. To ensure reliable operation the PTM should be switched off before any changes are made to the PTM1 and PTM0 bits. In the Timer/Counter Mode, the PTM output pin control must be disabled. Bit 5~4PTIO1~PTIO0: Select PTP output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of PTCK or PTPI 01: Input capture at falling edge of PTCK or PTPI 10: Input capture at falling/rising edge of PTCK or PTPI 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the PTM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTM is running. In the Compare Match Output Mode, the PTIO1 and PTIO0 bits determine how the PTM output pin changes state when a compare match occurs from the Comparator A. The PTM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When these bits are both zero, then no change will take place on the output. The initial value of the PTM output pin should be setup using the PTOC bit. Note that the output level requested by the PTIO1 and PTIO0 bits must be different from the initial value setup using the PTOC bit otherwise no change will occur on the PTM output pin when a compare match occurs. After the PTM output pin changes state, it can be reset to its initial level by changing the level of the PTON bit from low to high. In the PWM Mode, the PTIO1 and PTIO0 bits determine how the PTM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the PTIO1 and PTIO0 bits only after the PTM has been switched off. Unpredictable PWM outputs will occur if the PTIO1 and PTIO0 bits are changed when the PTM is running. Rev. 1.00 67 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Bit 3PTOC: PTP Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the PTM output pin. Its operation depends upon whether PTM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the PTM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the PTM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2PTPOL: PTP Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the PTP output pin. When the bit is set high the PTM output pin will be inverted and not inverted when the bit is zero. It has no effect if the PTM is in the Timer/Counter Mode. Bit 1PTCAPTS: PTM capture trigger source select 0: From PTPI pin 1: From PTCK pin Bit 0PTCCLR: Select PTM Counter clear condition 0: PTM Comparatror P match 1: PTM Comparatror A match This bit is used to select the method which clears the counter. Remember that the Periodic Type TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PTCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PTCCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. PTMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0PTMDL: PTM Counter Low Byte Register bit 7 ~ bit 0 PTM 10-bit Counter bit 7 ~ bit 0 PTMDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0PTMDH: PTM Counter High Byte Register bit 1 ~ bit 0 PTM 10-bit Counter bit 9 ~ bit 8 Rev. 1.00 68 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU PTMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PTMAL: PTM CCRA Low Byte Register bit 7 ~ bit 0 PTM 10-bit CCRA bit 7 ~ bit 0 PTMAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 2 1 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0PTMAH: PTM CCRA High Byte Register bit 1 ~ bit 0 PTM 10-bit CCRA bit 9 ~ bit 8 PTMRPL Register Bit 7 6 5 4 3 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PTMRPL: PTM CCRP Low Byte Register bit 7 ~ bit 0 PTM 10-bit CCRP bit 7 ~ bit 0 PTMPRH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0PTMRPH: PTM CCRP High Byte Register bit 1 ~ bit 0 PTM 10-bit CCRP bit 9 ~ bit 8 Rev. 1.00 69 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Periodic Type TM Operating Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PTM1 and PTM0 bits in the PTMC1 register. Compare Match Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the PTCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both PTMAF and PTMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the PTCCLR bit in the PTMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the PTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PTCCLR is high no PTMPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be cleared to zero. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the PTMAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the PTM output pin, will change state. The PTM output pin condition however only changes state when a PTMAF interrupt request flag is generated after a compare match occurs from Comparator A. The PTMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the PTM output pin. The way in which the PTM output pin changes state are determined by the condition of the PTIO1 and PTIO0 bits in the PTMC1 register. The PTM output pin can be selected using the PTIO1 and PTIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the PTM output pin, which is setup after the PTON bit changes from low to high, is setup using the PTOC bit. Note that if the PTIO1 and PTIO0 bits are zero then no pin change will take place. Rev. 1.00 70 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Counte� ove�flow Counte� Value 0x3FF PTCCLR = 0; PTM [1:0] = 00 CCRP > 0 Counte� �lea�ed �y CCRP value CCRP=0 CCRP > 0 Counte� Resta�t Resu�e CCRP Pause CCRA Stop Ti�e PTON PTPAU PTPOL CCRP Int. Flag PTMPF CCRA Int. Flag PTMAF PTM O/P Pin Output pin set to initial Level Low if PTOC=0 Output not affe�ted �y PTMAF flag. Re�ains High until �eset �y PTON �it Output Toggle with PTMAF flag He�e PTIO [1:0] = 11 Toggle Output sele�t Note PTIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when PTPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – PTCCLR = 0 Note: 1. With PTCCLR = 0 – a Comparator P match will clear the counter 2. The TM output pin is controlled only by the PTMAF flag 3. The output pin is reset to initial state by a PTON bit rising edge Rev. 1.00 71 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Counte� Value PTCCLR = 1; PTM [1:0] = 00 CCRA = 0 Counte� ove�flow CCRA > 0 Counte� �lea�ed �y CCRA value 0x3FF CCRA=0 Resu�e CCRA Pause Stop Counte� Resta�t CCRP Ti�e PTON PTPAU PTPOL No PTMAF flag gene�ated on CCRA ove�flow CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF PTMPF not gene�ated Output does not �hange PTM O/P Pin Output pin set to initial Level Low if PTOC=0 Output Toggle with PTMAF flag He�e PTIO [1:0] = 11 Toggle Output sele�t Output not affe�ted �y PTMAF flag. Re�ains High until �eset �y PTON �it Note PTIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when PTPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – PTCCLR = 1 Note: 1. With PTCCLR = 1 – a Comparator A match will clear the counter 2. The TM output pin is controlled only by the PTMAF flag 3. The output pin is reset to initial state by a PTON bit rising edge 4. The PTMPF flag is not generated when PTCCLR = 1. Rev. 1.00 72 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Timer/Counter Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should all be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the PTM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the PTM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively. The PWM function within the PTM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the PTM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM Output Mode, the PTCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The PTOC bit in the PTMC1 register is used to select the required polarity of the PWM waveform while the two PTIO1 and PTIO0 bits are used to enable the PWM output or to force the PTM output pin to a fixed high or low level. The PTPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit PTM, PWM Mode, Edge-aligned Mode CCRP 1~1023 0 Period 1~1023 1024 Duty CCRA If fSYS = 16MHz, PTM clock source select fSYS/4, CCRP = 512 and CCRA = 128, The PTM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 7.8125kHz, duty = 128/512= 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. Rev. 1.00 73 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Counte� Value PTM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when PTON �etu�ns high CCRP Pause Resu�e Counte� Stop if PTON �it low CCRA Ti�e PTON PTPAU PTPOL CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF PTM O/P Pin (PTOC=1) PTM O/P Pin (PTOC=0) PWM Duty Cy�le set �y CCRA PWM �esu�es ope�ation Output �ont�olled �y Output Inve�ts othe� pin-sha�ed fun�tion When PTPOL = 1 PWM Pe�iod set �y CCRP PWM Output Mode Note: 1. Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when PTIO[1:0] = 00 or 01 4. The PTCCLR bit has no influence on PWM operation Rev. 1.00 74 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Single Pulse Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTIO1 and PTIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTM output pin. The trigger for the pulse output leading edge is a low to high transition of the PTON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PTON bit can also be made to automatically change from low to high using the external PTCK pin, which will in turn initiate the Single Pulse output. When the PTON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PTON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTM interrupt. The counter can only be reset back to zero when the PTON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The PTCCLR bit is not used in this Mode. S/W Co��and SET“PTON” o� PTCK Pin T�ansition CCRA Leading Edge CCRA T�ailing Edge PTON �it 0 1 PTON �it 1 0 S/W Co��and CLR“PTON” o� CCRA Co�pa�e Mat�h PTP Output Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.00 75 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Counte� Value PTM [1:0] = 10 ; PTIO [1:0] = 11 Counte� stopped �y CCRA Counte� Reset when PTON �etu�ns high CCRA Pause Counte� Stops �y softwa�e Resu�e CCRP Ti�e PTON Softwa�e T�igge� Clea�ed �y CCRA �at�h Auto. set �y PTCK pin PTCK pin Softwa�e T�igge� Softwa�e Softwa�e T�igge� Clea� Softwa�e T�igge� PTCK pin T�igge� PTPAU PTPOL CCRP Int. Flag PTMPF No CCRP Inte��upts gene�ated CCRA Int. Flag PTMAF PTM O/P Pin (PTOC=1) PTM O/P Pin (PTOC=0) Pulse Width set �y CCRA Output Inve�ts when PTPOL = 1 Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the PTCK pin or by setting the PTON bit high 4. A PTCK pin active edge will automatically set the PTON bit high 5. In the Single Pulse Mode, PTIO[1:0] must be set to “11” and cannot be changed. Rev. 1.00 76 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Capture Input Mode To select this mode bits PTM1 and PTM0 in the PTMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTPI or PTCK pin which is selected using the PTCAPTS bit in the PTMC1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTIO1 and PTIO0 bits in the PTMC1 register. The counter is started when the PTON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPI or PTCK pin the present value in the counter will be latched into the CCRA registers and a PTM interrupt generated. Irrespective of what events occur on the PTPI or PTCK pin, the counter will continue to free run until the PTON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a PTM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTIO1 and PTIO0 bits can select the active trigger edge on the PTPI or PTCK pin to be a rising edge, falling edge or both edge types. If the PTIO1 and PTIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPI or PTCK pin, however it must be noted that the counter will continue to run. As the PTPI or PTCK pin is pin shared with other functions, care must be taken if the PTM is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTCCLR, PTOC and PTPOL bits are not used in this Mode. Rev. 1.00 77 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Counte� Value PTM [1:0] = 01 Counte� �lea�ed �y CCRP Counte� Stop Counte� Reset CCRP YY Resu�e Pause XX Ti�e PTON PTPAU A�tive edge A�tive edge A�tive edge PTM �aptu�e pin PTPI o� PTCK CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF CCRA Value PTIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disa�le Captu�e Capture Input Mode Note: 1. PTM[1:0] = 01 and active edge set by the PTIO[1:0] bits 2. A TM Capture input pin active edge transfers the counter value to CCRA 3. PTCCLR bit not used 4. No output function – PTOC and PTPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.00 78 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Analog to Digital Converter – ADC The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Converter Overview The device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. VDD fSYS ACE�~ACE0 ÷ �N (N=0~6) ADCK�~ADCK0 AN0 AN1 VREF ADOFF Bit VREFS Bit A/D Refe�en�e Voltage A/D Clo�k ADRL A/D Conve�te� ADRH AN� A/D Data Registe�s ADRFS 1.��V ACS4� ACS�~ACS0 START EOCB ADOFF VSS V1��EN A/D Converter Structure A/D Converter Register Description Overall operation of the A/D converter is controlled using five registers. A read only register pair exists to store the A/D converter data 12-bit value. The remaining three registers are control registers which setup the operating and control function of the A/D converter. Bit Register Name 7 6 5 4 3 2 1 0 ADRL(ADRFS=0) D3 D2 D1 D0 — — — — ADRL(ADRFS=1) D7 D6 D5 D4 D3 D2 D1 D0 ADRH(ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D4 — — — — D11 D10 D9 D8 ADCR0 ADRH(ADRFS=1) START EOCB ADOFF ADRFS — ACS2 ACS1 ACS0 ADCR1 ACS4 V125EN — VREFS — ADCK2 ADCK1 ADCK0 ACERL ACE7 ACE6 ACE5 ACE4 ACE3 ACE2 ACE1 ACE0 A/D Converter Register List Rev. 1.00 79 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU A/D Converter Data Register – ADRL, ADRH The device, which has an internal 12-bit A/D converter, requires two data registers, a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. ADRFS 0 1 ADRH 7 6 5 D11 D10 D9 — — — ADRL 4 3 2 1 0 7 6 5 4 3 2 1 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 — — — — — D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A/D converter Data Registers A/D Converter Control Registers – ADCR0, ADCR1, ACERL To control the function and operation of the A/D converter, three control registers known as ADCR0, ADCR1 and ACERL are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitised data format, the A/D converter clock source as well as controlling the start function and monitoring the end of A/D conversion status. The ACS2~ACS0 bits in the ADCR0 register and the ACS4 bit in the ADCR1 register define the A/D converter input channel number. As the device contains only one actual analog to digital converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter. It is the function of the ACS4 and ACS2~ACS0 bits to determine which analog channel input pin or internal 1.25V is actually connected to the internal A/D converter. The ACERL control register contains the ACE7~ACE0 bits which determine which pins on I/O Port are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. Setting the corresponding bit high will select the A/D converter input function, clearing the bit to zero will select either the I/O or other pin-shared function. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pin-shared function will be removed. In addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an A/D input. Rev. 1.00 80 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU ADCR0 Register Bit 7 6 5 4 3 2 1 0 Name START EOCB ADOFF ADRFS — ACS2 ACS1 ACS0 R/W R/W R R/W R/W — R/W R/W R/W POR 0 1 1 0 — 0 0 0 Bit 7START: Start the A/D conversion 0→1→0: Start 0→1: Reset the A/D converter and set EOCB to “1” This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process is running, the bit will be high. Bit 5ADOFF: A/D converter module power on/off control bit 0: A/D converter module power on 1: A/D converter module power off This bit controls the power to the A/D internal function. This bit should be cleared to zero to enable the A/D converter. If the bit is set high then the A/D converter will be switched off reducing the device power consumption. As the A/D converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. Note: 1. It is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving power. 2. ADOFF=1 will power down the A/D converter module. Bit 4ADRFS: A/D data format control bit 0: A/D converter Data MSB is ADRH bit 7, LSB is ADRL bit 4 1: A/D converter Data MSB is ADRH bit 3, LSB is ADRL bit 0 This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D data register section. Bit 3 Unimplemented, read as “0” Bit 2~0ACS2~ACS0: Select A/D channel (when ACS4 is “0”) 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 Rev. 1.00 81 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU ADCR1 Register Bit 7 6 5 4 3 2 1 0 Name ACS4 V125EN — VREFS — ADCK2 ADCK1 ADCK0 R/W R/W R/W — R/W — R/W R/W R/W POR 0 0 — 0 — 0 0 0 Bit 7ACS4: select internal 1.25V as A/D converter input control 0: Disable 1: Enable This bit enables 1.25V to be connected to the A/D converter. The V125EN bit must first have been set to enable the bandgap circuit 1.25V voltage to be used by the A/D converter. When the ACS4 bit is set high, the bandgap 1.25V voltage will be routed to the A/D converter and the other A/D input channels disconnected. Bit 6V125EN: internal 1.25V control 0: Disable 1: Enable This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit is set high the bandgap voltage 1.25V can be used by the A/D converter. If 1.25V is not used by the A/D converter and the LVR function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. When 1.25V is switched on for use by the A/D converter, a time tBGS should be allowed for the bandgap circuit to stabilise before implementing an A/D conversion. Bit 5 Unimplemented, read as “0” Bit 4VREFS: Selecte A/D converter reference voltage 0: Internal A/D converter power 1: VREF pin This bit is used to select the reference voltage for the A/D converter. If the bit is high, then the A/D converter reference voltage is supplied on the external VREF pin. If the pin is low, then the internal reference is used which is taken from the power supply pin VDD. When the A/D converter reference voltage is supplied on the external VREF pin which is pin-shared with other functions, all of the pin-shared functions except VREF on this pin are disabled. Bit 3 Unimplemented, read as “0” Bit 2~0ADCK2~ADCK0: Select A/D converter clock source 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: Undefined These three bits are used to select the clock source for the A/D converter. Rev. 1.00 82 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU ACERL Register Bit 7 6 5 4 3 2 1 0 Name ACE7 ACE6 ACE5 ACE4 ACE3 ACE2 ACE1 ACE0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7ACE7: Define PB3 is A/D input or not 0: Not A/D input 1: A/D input, AN7 Bit 6ACE6: Define PA7 is A/D input or not 0: Not A/D input 1: A/D input, AN6 Bit 5ACE5: Define PA6 is A/D input or not 0: Not A/D input 1: A/D input, AN5 Bit 4ACE4: Define PA5 is A/D input or not 0: Not A/D input 1: A/D input, AN4 Bit 3ACE3: Define PA4 is A/D input or not 0: Not A/D input 1: A/D input, AN3 Bit 2ACE2: Define PB2 is A/D input or not 0: Not A/D input 1: A/D input, AN2 Bit 1ACE1: Define PB1 is A/D input or not 0: Not A/D input 1: A/D input, AN1 Bit 0ACE0: Define PB0 is A/D input or not 0: Not A/D input 1: A/D input, AN0 A/D Converter Operation The START bit in the ADCR0 register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset. It is the START bit that is used to control the overall start operation of the internal analog to digital converter. The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to “0” by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS The division ratio value is determined by the ADCK2~ADCK0 bits in the ADCR1 register. Rev. 1.00 83 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Although the A/D clock source is determined by the system clock fSYS, and by bits ADCK2~ADCK0, there are some limitations on the A/D clock source speed range that can be selected. As the recommended range of permissible A/D clock period, tADCK, is from 0.5μs to 10μs, care must be taken for selected system clock frequencies. For example, if the system clock operates at a frequency of 4MHz, the ADCK2~ADCK0 bits should not be set to 000B or 110B. Doing so will give A/D clock periods that are less than the minimum A/D clock period or greater than the maximum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. A/D Clock Period (tADCK) fSYS ADCK [2:0] =000 (fSYS) ADCK [2:0] =001 (fSYS/2) ADCK [2:0] =010 (fSYS/4) ADCK [2:0] =011 (fSYS/8) ADCK [2:0] =100 (fSYS/16) ADCK [2:0] =101 (fSYS/32) ADCK [2:0] =110 (fSYS/64) ADCK [2:0] =111 1MHz 1μs 2μs 4μs 8μs 16μs* 32μs* 64μs* Undefined 2MHz 500ns 1μs 2μs 4μs 8μs 16μs* 32μs* Undefined 4MHz 250ns* 500ns 1μs 2μs 4μs 8μs 16μs* Undefined 8MHz 125ns* 250ns* 500ns 1μs 2μs 4μs 8μs Undefined A/D Clock Period Examples Controlling the power on/off function of the A/D converter circuitry is implemented using the ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When the ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs by clearing the ACE7~ACE0 bits in the ACERL registers, if the ADOFF bit is zero then some power will still be consumed. In power conscious applications it is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D converter function is not being used. A/D Converter Reference Voltage The reference voltage supply to the A/D Converter can be supplied from either the positive power supply pin, VDD, or from an external reference sources supplied on pin VREF. The desired selection is made using the VREFS bit. As the VREF pin is pin-shared with other functions, when the VREFS bit is set high, the VREF pin function will be selected and the other pin functions will be disabled automatically. A/D Converter Input Signals All of the A/D analog input pins are pin-shared with the I/O pins as well as other functions. The ACE7~ACE0 bits in the ACERL register, determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the ACE7~ACE0 bits for its corresponding pin is set high then the pins will be setup to be an A/D converter input and the original pin functions disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the port control register to enable the A/D input as when the ACE7~ACE0 bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own reference voltage pin, VREF. however the reference voltage can also be supplied from the power supply pin, a choice which is made through the VREFS bit in the ADCR1 register. The analog input values must not be allowed to exceed the value of VREF. Rev. 1.00 84 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Conversion Rate and Timing Diagram A complete A/D conversion contains two parts, data sampling and data conversion. The data sampling which is defined as tADS takes 4 A/D clock cycles and the data conversion takes 12 A/D clock cycles. Therefore a total of 16 A/D clock cycles for an external input A/D conversion which is defined as tADC are necessary. Maximum single A/D conversion rate = A/D clock period / 16 The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16 tADCK clock cycles where tADCK is equal to the A/D clock period. ADOFF ADC Module ON tON�ST off on off A/D sa�pling ti�e tADS on A/D sa�pling ti�e tADS START EOCB ACS4� ACS�~ACS0 011B Powe�-on Reset 010B 000B Sta�t of A/D �onve�sion Reset A/D �onve�te� 1: Define po�t �onfigu�ation �: Sele�t analog �hannel 001B Sta�t of A/D �onve�sion Sta�t of A/D �onve�sion Reset A/D �onve�te� Reset A/D �onve�te� End of A/D �onve�sion End of A/D �onve�sion tADC A/D �onve�sion ti�e tADC A/D �onve�sion ti�e A/D Conversion Timing Rev. 1.00 85 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the ADCR1 register. • Step 2 Enable the A/D by clearing the ADOFF bit in the ADCR0 register to zero. • Step 3 Select which channel is to be connected to the internal A/D converter by correctly programming the ACS4 and ACS2~ACS0 bits which are also contained in the ADCR1 and ADCR0 register. • Step 4 Select which pins are to be used as A/D inputs and configure them by correctly programming the ACE7~ACE0 bits in the ACERL register. • Step 5 If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and the A/D converter interrupt bit, ADE, must both be set high to do this. • Step 6 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR0 register from low to high and then low again. Note that this bit should have been originally cleared to zero. • Step 7 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0 register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR0 register is used, the interrupt enable step above can be omitted. Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the ADCR0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. The power-on reset condition of the A/D converter control registers will ensure that the shared function pins are setup as A/D converter inputs. If any of the A/D converter input pins are to be used for functions, then the A/D converter control register bits must be properly setup to disable the A/D input configuration. Rev. 1.00 86 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU A/D Conversion Function As the device contains a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the actual A/D converter reference voltage, VREF voltage, this gives a single bit analog input value of VREF divided by 4096. 1 LSB = VREF /4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage = A/D output digital value ×VREF/4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VREF level. Note that here the VREF voltage is the actual A/D converter reference voltage determined by the VREFS bit. 1.� LSB FFFH FFEH FFDH A/D Conversion Result 03H 0.� LSB 0�H 01H 0 1 � 3 4093 4094 409� 4096 VREF 4096 Analog Input Voltage Ideal A/D Conversion Function Rev. 1.00 87 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU A/D Conversion Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an EOCB polling method to detect the end of conversion clr ADE; disable A/D converter interrupt mov a, 03H mov ADCR1, a ; select fSYS/8 as A/D clock and switch off 1.25V clrADOFF mov a, 0Fh ; setup ACERL to configure pins AN0~AN3 mov ACERL, a mov a, 00h mov ADCR0, a ; enable and connect AN0 channel to A/D converter : : Start_conversion: clr START set START ; reset A/D clr START ; start A/D Polling_EOC: sz EOCB ; poll the ADCR0 register EOCB bit to detect end of A/D conversion jmp polling_EOC ; continue polling mov a, ADRL ; read low byte conversion result value mov adrl_buffer, a ; save result to user defined register mov a, ADRH ; read high byte conversion result value mov adrh_buffer, a ; save result to user defined register : jmp start_conversion ; start next A/D conversion Note: To power off the A/D converter, it is necessary to set ADOFF as “1”. Rev. 1.00 88 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Example: using the interrupt method to detect the end of conversion clr ADE; disable A/D converter interrupt mov a, 03H mov ADCR1, a ; select fSYS/8 as A/D clock and switch off 1.25V clrADOFF mov a, 0Fh ; setup ACERL to configure pins AN0~AN3 mov ACERL, a mov a, 00h mov ADCR0, a ; enable and connect AN0 channel to A/D converter : : Start_conversion: clr START set START ; reset A/D clr START ; start A/D clr ADF ; clear A/D converter interrupt request flag set ADE; enable A/D converter interrupt set EMI ; enable global interrupt : : ; A/D converter interrupt service routine ADC_ISR: mov acc_stack, a ; save ACC to user defined memory mov a, STATUS mov status_stack, a ; save STATUS to user defined memory : : mov a, ADRL ; read low byte conversion result value mov adrl_buffer, a ; save result to user defined register mov a, ADRH ; read high byte conversion result value mov adrh_buffer, a ; save result to user defined register : : EXIT_ISR: mov a, status_stack mov STATUS, a ; restore STATUS from user defined memory mov a, acc_stack ; restore ACC from user defined memory clr ADF ; clear A/D converter interrupt flag reti Note: To power off the A/D converter, it is necessary to set ADOFF as “1”. Rev. 1.00 89 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupt is generated by the action of the external INTn pin, while the internal interrupts are generated by various internal functions such as TMs, Time Base, and the A/D converter. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second is the MFI0~MFI1 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an “E” for enable/ disable bit or “F” for request flag. Function Enable Bit Global Request Flag Notes EMI — — INTn Pin INTnE INTnF n=0 or 1 Multi-function MFnE MFnF n=0~1 A/D Converter ADE ADF — Time Base TBnE TBnF n=0 or 1 STMPE STMPF — STMAE STMAF — PTMPE PTMPF — PTMAE PTMAF — Timer Modules Interrupt Register Bit Naming Conventions Bit Register Name 7 6 5 4 3 2 1 0 INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — MF0F — INT0F MF0E — INT0E EMI INTC1 TB0F ADF — MF1F TB0E ADE — MF1E INTC2 — — INT1F TB1F — — INT1E TB1E MFI0 — — STMAF STMPF — — STMAE STMPE MFI1 — — PTMAF PTMPF — — PTMAE PTMPE Interrupt Register Contents Rev. 1.00 90 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU INTEG Register Bit 7 6 5 4 3 2 1 0 Name — — — — INT1S1 INT1S0 INT0S1 INT0S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3~2INT1S1~INT1S0: Interrupt edge control for INT1 pin 00: Disable 01: Rising edge 10: Falling edge 11: Both rising and falling edges Bit 1~0INT0S1~INT0S0: Interrupt edge control for INT0 pin 00: Disable 01: Rising edge 10: Falling edge 11: Both rising and falling edges INTC0 Register Bit 7 6 5 4 3 2 1 Name — MF0F — INT0F MF0E — INT0E EMI R/W — R/W — R/W R/W — R/W R/W POR — 0 — 0 0 — 0 0 Bit 7 Unimplemented, read as “0” Bit 6MF0F: Multi-function Interrupt 0 Request Flag 0: No request 1: Interrupt request Bit 5 Unimplemented, read as “0” Bit 4INT0F: INT0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3MF0E: Multi-function 0 Interrupt Control 0: Disable 1: Enable Bit 2 Unimplemented, read as “0” Bit 1INT0E: INT0 Interrupt Control 0: Disable 1: Enable Bit 0EMI: Global Interrupt Control 0: Disable 1: Enable Rev. 1.00 91 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU INTC1 Register Bit 7 6 5 4 3 2 1 0 Name TB0F ADF — MF1F TB0E ADE — MF1E R/W R/W R/W — R/W R/W R/W — R/W POR 0 0 — 0 0 0 — 0 Bit 7TB0F: Time Base 0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 6ADF: A/D Converter Interrupt Request Flag 0: No request 1: Interrupt request Bit 5 Unimplemented, read as “0” Bit 4MF1F: Multi-function Interrupt 1 Request Flag 0: No request 1: Interrupt request Bit 3TB0E: Time Base 0 Interrupt Control 0: Disable 1: Enable Bit 2ADE: A/D Converter Interrupt Control 0: Disable 1: Enable Bit 1 Unimplemented, read as “0” Bit 0MF1E: Multi-function 1 Interrupt Control 0: Disable 1: Enable INTC2 Register Bit 7 6 5 4 3 2 1 0 Name — — INT1F TB1F — — INT1E TB1E R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5INT1F: INT1 pin interrupt request flag 0: No request 1: Interrupt request Bit 4TB1F: Time Base 1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” Bit 1INT1E: INT1 pin interrupt control 0: Disable 1: Enable Bit 0TB1E: Time Base 1 Interrupt Control 0: Disable 1: Enable Rev. 1.00 92 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU MFI0 Register Bit 7 6 5 4 3 2 1 0 Name — — STMAF STMPF — — STMAE STMPE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5STMAF: STM Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4STMPF: STM Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” Bit 1STMAE: STM Comparator A match interrupt control 0: Disable 1: Enable Bit 0STMPE: STM Comparator P match interrupt control 0: Disable 1: Enable MFI1 Register Bit 7 6 5 4 3 2 1 0 Name — — PTMAF PTMPF — — PTMAE PTMPE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5PTMAF: PTM Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4PTMPF: PTM Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” Bit 1PTMAE: PTM Comparator A match interrupt control 0: Disable 1: Enable Bit 0PTMPE: PTM Comparator P match interrupt control 0: Disable 1: Enable Rev. 1.00 93 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A match or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector, if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a “JMP” which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a “RETI”, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the Accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 1.00 94 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU EMI auto disa�led in ISR Legend xxF Request Flag� no auto �eset in ISR xxF Request Flag� auto �eset in ISR xxE Ena�le Bits STM P STMPF STMPE STM A STMAF STMAE PTM P PTMPF PTMPE PTM A PTMAF PTMAE Inte��upts �ontained within Multi-Fun�tion Inte��upts Inte��upt Na�e INT0 Pin Request Flags INT0F Ena�le Bits INT0E Maste� Ena�le EMI Vector M. Fun�t. 0 MF0F MF0E EMI 0CH M. Fun�t. 1 MF1F MF1E EMI 10H A/D ADF ADE EMI 18H Ti�e Base 0 TB0F TB0E EMI 1CH Ti�e Base 1 TB1F TB1E EMI �0H INT1 Pin INT1F INT1E EMI �4H P�io�ity High 04H Low Interrupt Structure External Interrupt The external interrupt is controlled by signal transitions on the INTn pins. An external interrupt request will take place when the external interrupt request flag, INTnF, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INTnE, must first be set. Additionally the correct interrupt edge type must be selected using the related register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared with I/O pin, it can only be configured as external interrupt pin if the external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag, INTnF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Rev. 1.00 95 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Multi-function Interrupt Within the device there are up to two Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts. A Multi-function interrupt request will take place the Multi-function interrupt request flag, MFnF is set. The Multi-function interrupt flag will be set when any of its included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to the Multi-function interrupt vector will take place. When the interrupt is serviced, the related Multi-Function request flag, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts, will not be automatically reset and must be manually reset by the application program. A/D Converter Interrupt The device contains an A/D converter which has its own independent interrupt. The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Time Base Interrupt The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several different sources, as shown in the System Operating Mode section. Rev. 1.00 96 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU TBC Register Bit 7 6 5 4 3 2 1 0 Name TBON TBCK TB11 TB10 — TB02 TB01 TB00 R/W R/W R/W R/W R/W — R/W R/W R/W POR 0 0 1 1 — 1 1 1 Bit 7TBON: TB0 and TB1 Control 0: Disable 1: Enable Bit 6TBCK: Select fTB Clock 0: fTBC 1: fSYS/4 Bit 5~4 TB11, TB10: Select Time Base 1 Time-out Period 00: 212/fTB 01: 213/fTB 10: 214/fTB 11: 215/fTB Bit 3 Unimplemented, read as “0” Bit 2~0TB02~TB00: Select Time Base 0 Time-out Period 000: 28/fTB 001: 29/fTB 010: 210/fTB 011: 211/fTB 100: 212/fTB 101: 213/fTB 110: 214/fTB 111: 215/fTB TB0� ~ TB00 fSYS/4 LIRC fTBC M U X ÷ �8 ~ �1� Ti�e Base 0 Inte��upt ÷ �1� ~ �1� Ti�e Base 1 Inte��upt fTB TBCK Bit TB11 ~ TB10 Time Base Interrupt TM Interrupts The Standard and Periodic Type TMs have two interrupts each. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the Standard and Periodic Type TMs there are two interrupt request flags xTMPF and xTMAF and two enable bits xTMPE and xTMAE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Rev. 1.00 97 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the “CALL” instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.00 98 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Application Circuits VDD VDD 0.1 F AN0~AN� VSS PA0~PA� PB0~PB6 PC0~PC� HT66F0182 Rev. 1.00 99 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of several kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions such as INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.00 100 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction “RET” in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i” instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the “HALT” instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.00 101 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.00 102 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (specific page) to TBLH and Data Memory Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note 2Note None None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch Operation JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read Operation TABRD [m] TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the “CLR WDT1” and “CLR WDT2” instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both “CLR WDT1” and “CLR WDT2” instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 103 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.00 104 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT1 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT2 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Rev. 1.00 105 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.00 106 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Rev. 1.00 107 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rev. 1.00 108 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Rev. 1.00 109 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C Rev. 1.00 110 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 1.00 111 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU TABRD [m] Description Operation Affected flag(s) Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDC [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.00 112 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.00 113 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU 16-pin NSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. — 0.236 BSC — B — 0.154 BSC — C 0.012 — 0.020 C’ — 0.390 BSC — D — — 0.069 E — 0.050 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° A Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A — 6.0 BSC — B — 3.9 BSC — 0.51 C 0.31 — C’ — 9.9 BSC — D — — 1.75 E — 1.27 BSC — F 0.10 — 0.25 G 0.40 — 1.27 H 0.10 — 0.25 α 0° — 8° 114 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU 20-pin NSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 0.228 0.236 0.244 B 0.146 0.154 0.161 C 0.009 — 0.012 C’ 0.382 0.390 0.398 D — — 0.069 E — 0.032 BSC — F 0.002 — 0.009 G 0.020 — 0.031 H 0.008 — 0.010 α 0° — 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A 5.80 6.00 6.20 B 3.70 3.90 4.10 C 0.23 — 0.30 C’ 9.70 9.90 10.10 D — — 1.75 E — 0.80 BSC — F 0.05 — 0.23 G 0.50 — 0.80 H 0.21 — 0.25 α 0° — 8° 115 December 17, 2015 HT66F0182 A/D 8-Bit Flash MCU Copyright© 2015 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 116 December 17, 2015