Wireless Voice Flash 8-Bit MCU HT66FV240 Revision: V1.30 Date: ������������� June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Table of Contents Features............................................................................................................. 7 CPU Features.......................................................................................................................... 7 Peripheral Features.................................................................................................................. 7 General Description.......................................................................................... 8 Block Diagram................................................................................................... 9 Pin Assignment................................................................................................. 9 Pin Descriptions............................................................................................. 10 Absolute Maximum Ratings........................................................................... 13 D.C. Characteristics........................................................................................ 14 A.C. Characteristics........................................................................................ 16 A/D Converter Characteristics....................................................................... 17 LVD/LVR Electrical Characteristics............................................................... 17 16-bit PCM A/D Converter Electrical Characteristics.................................. 18 D/A Converter Electrical Characteristics...................................................... 18 Power Amplifier Electrical Characteristics................................................... 18 Power-on Reset Characteristics.................................................................... 18 System Architecture....................................................................................... 19 Clocking and Pipelining.......................................................................................................... 19 Program Counter.................................................................................................................... 20 Stack...................................................................................................................................... 20 Arithmetic and Logic Unit – ALU............................................................................................ 21 Flash Program Memory.................................................................................. 22 Structure................................................................................................................................. 22 Special Vectors...................................................................................................................... 22 Look-up Table......................................................................................................................... 22 Table Program Example......................................................................................................... 23 In Circuit Programming – ICP................................................................................................ 24 On-Chip Debug Support – OCDS.......................................................................................... 25 In Application Programming – IAP......................................................................................... 25 Data Memory................................................................................................... 33 Structure................................................................................................................................. 33 General Purpose Data Memory............................................................................................. 33 Special Purpose Data Memory.............................................................................................. 34 Special Function Register Description......................................................... 35 Indirect Addressing Registers – IAR0, IAR1, IAR2................................................................ 35 Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L............................................................ 35 Accumulator – ACC................................................................................................................ 36 Program Counter Low Register – PCL................................................................................... 36 Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 36 Status Register – STATUS..................................................................................................... 37 Rev. 1.30 2 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU EEPROM Data Memory................................................................................... 39 EEPROM Data Memory Structure......................................................................................... 39 EEPROM Registers............................................................................................................... 39 Reading Data from the EEPROM.......................................................................................... 40 Writing Data to the EEPROM................................................................................................. 41 Write Protection...................................................................................................................... 41 EEPROM Interrupt................................................................................................................. 41 Programming Considerations................................................................................................. 42 Oscillator......................................................................................................... 43 Oscillator Overview................................................................................................................ 43 System Clock Configurations................................................................................................. 43 External Crystal/Ceramic Oscillator – HXT............................................................................ 43 External 32.768 kHz Crystal Oscillator – LXT........................................................................ 44 Internal 32kHz Oscillator – LIRC............................................................................................ 45 Supplementary Oscillators..................................................................................................... 45 Operating Modes and System Clocks.......................................................... 46 System Clocks....................................................................................................................... 46 System Operation Modes....................................................................................................... 47 Control Registers................................................................................................................... 48 Operating Mode Switching..................................................................................................... 50 Standby Current Considerations............................................................................................ 54 Wake-up................................................................................................................................. 54 Watchdog Timer.............................................................................................. 55 Watchdog Timer Clock Source............................................................................................... 55 Watchdog Timer Control Register.......................................................................................... 55 Watchdog Timer Operation.................................................................................................... 56 Reset and Initialisation................................................................................... 57 Reset Functions..................................................................................................................... 57 Reset Initial Conditions.......................................................................................................... 61 Input/Output Ports.......................................................................................... 65 Pull-high Resistors................................................................................................................. 65 Port A Wake-up...................................................................................................................... 66 I/O Port Control Registers...................................................................................................... 67 Pin-shared Functions............................................................................................................. 68 I/O Pin Structures................................................................................................................... 72 Programming Considerations................................................................................................. 73 Timer Modules – TM....................................................................................... 73 Introduction............................................................................................................................ 73 TM Operation......................................................................................................................... 74 TM Clock Source.................................................................................................................... 74 TM Interrupts.......................................................................................................................... 74 TM External Pins.................................................................................................................... 74 TM Input/Output Pin Control Register.................................................................................... 75 Programming Considerations................................................................................................. 76 Rev. 1.30 3 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Compact Type TM – CTM............................................................................... 77 Compact TM Operation.......................................................................................................... 77 Compact Type TM Register Description................................................................................ 78 Compact Type TM Operation Modes..................................................................................... 82 Compare Match Output Mode................................................................................................ 82 Timer/Counter Mode.............................................................................................................. 85 PWM Output Mode................................................................................................................. 85 Standard Type TM – STM............................................................................... 88 Standard TM Operation.......................................................................................................... 88 Standard Type TM Register Description................................................................................ 89 Standard Type TM Operation Modes..................................................................................... 93 Compare Match Output Mode................................................................................................ 93 Timer/Counter Mode.............................................................................................................. 96 PWM Output Mode................................................................................................................. 96 Single Pulse Output Mode..................................................................................................... 99 Capture Input Mode............................................................................................................. 101 Periodic Type TM – PTM............................................................................... 102 Periodic TM Operation......................................................................................................... 102 Periodic Type TM Register Description................................................................................ 103 Periodic Type TM Operation Modes..................................................................................... 107 Compare Match Output Mode.............................................................................................. 107 Timer/Counter Mode.............................................................................................................110 PWM Output Mode................................................................................................................110 Single Pulse Output Mode....................................................................................................112 Capture Input Mode..............................................................................................................114 Analog to Digital Converter..........................................................................116 A/D Overview........................................................................................................................116 A/D Converter Register Description......................................................................................116 A/D Operation.......................................................................................................................119 A/D Input Pins...................................................................................................................... 120 Summary of A/D Conversion Steps...................................................................................... 121 Programming Considerations............................................................................................... 122 A/D Transfer Function.......................................................................................................... 122 A/D Programming Examples................................................................................................ 123 Serial Interface Module – SIM...................................................................... 125 SPI Interface........................................................................................................................ 125 SPI Interface Operation........................................................................................................ 125 SPI Registers....................................................................................................................... 126 SPI Communication............................................................................................................. 129 I2C Interface......................................................................................................................... 131 I2C Interface Operation......................................................................................................... 131 I2C Registers........................................................................................................................ 132 I2C Bus Communication....................................................................................................... 136 I2C Bus Start Signal.............................................................................................................. 137 Rev. 1.30 4 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU I2C Slave Address................................................................................................................ 137 I2C Bus Read/Write Signal................................................................................................... 137 I2C Bus Slave Address Acknowledge Signal........................................................................ 137 I2C Bus Data and Acknowledge Signal................................................................................ 138 I2C Time-out Control............................................................................................................. 139 Serial Interface – SPIA.................................................................................. 141 SPIA Interface Operation..................................................................................................... 141 SPIA Registers..................................................................................................................... 142 SPIA Communication........................................................................................................... 144 SPIA Bus Enable/Disable..................................................................................................... 146 SPIA Operation.................................................................................................................... 147 Error Detection..................................................................................................................... 148 Direct Memory Access – DMA..................................................................... 149 DMA Controller..................................................................................................................... 149 DMA Registers..................................................................................................................... 150 DMA Data Transfer using SPIA Interface............................................................................. 152 DMA Error Management...................................................................................................... 152 DMA Interrupt....................................................................................................................... 152 SCOM Function for LCD............................................................................... 153 LCD Operation..................................................................................................................... 153 LCD Bias Control................................................................................................................. 153 Voice Controller............................................................................................ 154 PLL Operation...................................................................................................................... 154 Voice Recording Operation.................................................................................................. 155 Voice Playing Operation....................................................................................................... 155 Voice Controller Registers.................................................................................................... 156 Interrupts....................................................................................................... 160 Interrupt Registers................................................................................................................ 160 Interrupt Operation............................................................................................................... 166 External Interrupt.................................................................................................................. 167 Voice Play Interrupt.............................................................................................................. 168 Voice Record Interrupt......................................................................................................... 168 Multi-function Interrupt......................................................................................................... 168 A/D Converter Interrupt........................................................................................................ 169 Time Base Interrupt.............................................................................................................. 169 DMA Transfer Interrupt......................................................................................................... 170 DMA Error Interrupt.............................................................................................................. 171 Serial Interface Module Interrupt.......................................................................................... 171 SPIA Interface Interrupt........................................................................................................ 171 LVD Interrupt........................................................................................................................ 171 EEPROM Interrupt............................................................................................................... 172 TM Interrupt.......................................................................................................................... 172 Interrupt Wake-up Function.................................................................................................. 172 Programming Considerations............................................................................................... 173 Rev. 1.30 5 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Low Voltage Detector – LVD........................................................................ 174 LVD Register........................................................................................................................ 174 LVD Operation...................................................................................................................... 175 Application Circuits...................................................................................... 176 Wireless Voice Application Circuit (3V) − 1.......................................................................... 176 Wireless Voice Application Circuit (3V) − 2.......................................................................... 176 Record/Play Voice Application Circuit (3V) − 1.................................................................... 177 Record/Play Voice Application Circuit (3V) − 2.................................................................... 177 Record/Play Voice Application Circuit (5V) − 1.................................................................... 178 Record/Play Voice Application Circuit (5V) − 2.................................................................... 178 Instruction Set............................................................................................... 179 Introduction.......................................................................................................................... 179 Instruction Timing................................................................................................................. 179 Moving and Transferring Data.............................................................................................. 179 Arithmetic Operations........................................................................................................... 179 Logical and Rotate Operation.............................................................................................. 180 Branches and Control Transfer............................................................................................ 180 Bit Operations...................................................................................................................... 180 Table Read Operations........................................................................................................ 180 Other Operations.................................................................................................................. 180 Instruction Set Summary............................................................................. 181 Table Conventions................................................................................................................ 181 Extended Instruction Set...................................................................................................... 183 Instruction Definition.................................................................................... 185 Extended Instruction Definition............................................................................................ 194 Package Information.................................................................................... 201 48-pin LQFP (7mm×7mm) Outline Dimensions................................................................... 202 Rev. 1.30 6 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Features CPU Features • Operating Voltage ♦♦ fSYS= 4MHz: 2.2V~5.5V ♦♦ fSYS= 8MHz: 2.4V~5.5V ♦♦ fSYS=16MHz: 3.6V~5.5V • Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Oscillator Type ♦♦ External 16MHz Crystal – HXT ♦♦ External 32.768kHz Crystal – LXT ♦♦ Internal 32kHz RC – LIRC • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one to three instruction cycles • Table read instructions • 115 powerful instructions • 8-level subroutine nesting • Bit manipulation instruction Peripheral Features • Program Memory: 4K×16 • Data Memory: 384×8 • EEPROM Memory: 128×8 • Watchdog Timer function • Up to 28 bidirectional I/O lines • Software controlled 4-SCOM lines LCD driver with 1/2 bias • Two external interrupt lines shared with I/O pins • Multiple Timer Modules for time measure, input capture, compare match output, PWM output function or single pulse output function • Serial Interfaces Module – SIM for SPI or I2C • Dual Time-Base functions for generation of fixed time interrupt signals • Serial Peripheral Interface – SPIA • 8-channel 12-bit resolution A/D converter • In Application Programming function – IAP • DMA function via SPIA interface for external data transfer • G.711 standard compander • Programmable sampling rate for audio recording / audio playback • Pre-Amp(OPA) for Microphone input • High performance 16-bit PCM A/D Converter • Class AB power amplifier for speaker driving Rev. 1.30 7 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU • High performance 16-bit audio D/A converter • Digital volume control for audio playback function • Digital Programmable Gain Amplifier – PGA • Low Voltage Reset function • Low Voltage Detect function • Flash program memory can be re-programmed up to 100,000 times • Flash program memory data retention > 10 years • EEPROM data memory can be re-programmed up to 1,000,000 times • EEPROM data memory data retention > 10 years • Package type: 48-pin LQFP General Description The device is a Flash Memory A/D type 8-bit high performance RISC architecture microcontroller which is designed for wireless voice product applications. It integrates a 16-bit PCM ADC, 16bit DAC, Power Amplifier, G.711 Compander, DMA processing unit combined with an 8-bit microcontroller. The 16-bit PCM A/D Converter and D/A Converter in the device operate at a sampling rate of 8/12/16 KHz for the Microphone input/Speaker output. For the D/A Converter, the device has a digital programmable gain amplifier. The gain range is from -32dB to +6dB. For the PCM A/D Converter input, the digital gain range is from 0dB to 19.5dB. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Communication with the outside world is catered for by including fully integrated SPI or I2C interface functions, two popular interfaces which provide designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HXT, LXT and LIRC oscillator functions are provided including a fully integrated system oscillator. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. Rev. 1.30 8 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Block Diagram Watchdog Timer Flash/EEPROM Programming Circ�itry EEPROM Data Memory Flash Program Memory Internal RC Oscillator Low Voltage Detect IAP 8-bit RISC MCU Core Low Voltage Reset RAM Data Memory External HXT/LXT Oscillators Reset Circ�it Interr�pt Controller 1�-bit A/D Converter Time Base 16-bit PCM ADC PGA OPA PLL I/O SIM (SPI/I�C) Timer Mod�les SPIA DMA G.711 Compander Digital Vol�me Control 16-bit D/A Converter Power Amplifier Pin Assignment PB3/PTCK PB�/PTPI_0/PTP_0 PB0/STPI_1/STP_1 PB1/VDD_IO PD7/PTPI_1/PTP_1 PD6/CLKO PD5/SCKA PD�/SDOA PD3/SDIA PD�/INT1 PD1/SCSA PD0 SPAVSS_PA AVDD_PA SP+ AUD_IN AUD BIAS AVSS1 AVDD1 AVDD3 VAGREF VAG �8 �7 �6 �5 �� �3 �� �1 �0 3� 38 37 36 1 35 � 3� 3 33 � 5 3� HT66FV240/HT66VV240 31 6 7 30 48 LQFP-A �� 8 �8 � �7 10 �6 11 �5 1� 13 1� 15 16 17 18 1� �0 �1 �� �3 �� PA�/STCK/ICPCK/OCDSCK PA0/ICPDA/OCDSDA OSC1 OSC� PA1/STPI_0/STP_0/SCOM0 PA5/CTCK/SCOM1 PA6/CTP_1/SCOM� PA7/CTP_0/SCOM3 VSS PA3/XT1 PA�/XT� VDD PC0/VREF/AN0 PC1/AN1 PC�/AN� PC3/INT0/AN3 PC�/SCS/AN� PC5/SDO/AN5 PC6/SCK/SCL/AN6 PC7/SDI/SDA/AN7 AVSS3 TG TITI+ Note: The OCDSDA and OCDSCK pins are the OCDS dedicated pins and only available for the HT66VV240 device which is the OCDS EV chip for the HT66FV240 device. Rev. 1.30 9 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Pin Descriptions With the exception of the power pins and some relevant transformer control pins, all pins on these devices can be referenced by their Port name, e.g. PA0, PA1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Analog to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. Pad Name PA0/ICPDA/ OCDSDA PA1/STPI_0/ STP_0/SCOM0 PA2 /STCK/ ICPCK/OCDSCK PA3/XT1 PA4/XT2 PA5/CTCK/ SCOM1 PA6/CTP_1/ SCOM2 PA7/CTP_0/ SCOM3 Rev. 1.30 Function OPT PA0 PAWU PAPU I/T O/T ST General purpose I/O. Register enabled pull-up and wakeCMOS up. Description ICPDA — ST CMOS ICP Data/Address line OCDSDA — ST CMOS OCDS Data/Address line, for EV chip only. PA1 PAWU PAPU PAS0 ST CMOS STPI_0 PAS0 IFS ST — STP_0 PAS0 — CMOS STM output SCOM0 PAS0 — SCOM LCD common output PA2 PAWU PAPU ST CMOS STCK PAS0 ST ICPCK — ST OCDSCK — ST — PA3 PAWU PAPU PAS0 ST CMOS XT1 PAS0 LXT — PA4 PAWU PAPU PAS1 ST CMOS XT2 PAS1 — LXT PA5 PAWU PAPU PAS1 ST CMOS CTCK PAS1 ST — SCOM1 PAS1 — SCOM LCD common output PA6 PAWU PAPU PAS3 ST CMOS CTP_1 PAS1 — CMOS CTM output SCOM2 PAS1 — SCOM LCD common output PA7 PAWU PAPU PAS3 ST CMOS CTP_0 PAS1 — CMOS CTM output SCOM3 PAS1 — SCOM LCD common output General purpose I/O. Register enabled pull-up and wakeup. STM capture input — General purpose I/O. Register enabled pull-up and wakeup. STM clock input CMOS ICP Clock pin OCDS Clock pin, for EV chip only. General purpose I/O. Register enabled pull-up and wakeup. LXT oscillator pin General purpose I/O. Register enabled pull-up and wakeup. LXT oscillator pin General purpose I/O. Register enabled pull-up and wakeup. CTM clock input General purpose I/O. Register enabled pull-up and wakeup. General purpose I/O. Register enabled pull-up and wakeup. 10 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Pad Name PB0/STPI_1/ STP_1 PB1/VDD_IO PB2/PTPI_0/ PTP_0 PB3/PTCK PC0/VREF/AN0 PC1/AN1 PC2/AN2 PC3/INT0/AN3 PC4/SCS/AN4 PC5/SDO/AN5 PC6/SCK/SCL/ AN6 PC7/SDI/SDA/ AN7 Rev. 1.30 Function OPT I/T PB0 PBPU PBS0 O/T Description ST STPI_1 PBS0 IFS ST STP_1 PBS0 — CMOS STM output PB1 PBPU PBS0 ST CMOS General purpose I/O. Register enabled pull-up VDD_IO PBS0 PWR PB2 PBPU PBS0 ST PTPI_0 PBS0 IFS ST PTP_0 PBS0 — CMOS PTM output CMOS General purpose I/O. Register enabled pull-up CMOS General purpose I/O. Register enabled pull-up — — STM capture input PD0~PD7 I/O power for level shift CMOS General purpose I/O. Register enabled pull-up — PTM capture input PB3 PBPU ST PTCK — ST PC0 PCPU PCS0 ST VREF PCS0 AN — A/D Converter reference input AN0 PCS0 AN — A/D Converter analog input PC1 PCPU PCS0 ST AN1 PCS0 AN PC2 PCPU PCS0 ST AN2 PCS0 AN PC3 PCPU PCS0 ST INT0 PCS0 INTEG INTC0 ST — External Interrupt 0 AN3 PCS0 AN — A/D Converter analog input PC4 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up SCS PCS1 ST CMOS SPI slave select AN4 PCS1 AN PC5 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up CMOS SPI data output — PTM clock/capture input CMOS General purpose I/O. Register enabled pull-up CMOS General purpose I/O. Register enabled pull-up — A/D Converter analog input CMOS General purpose I/O. Register enabled pull-up — A/D Converter analog input CMOS General purpose I/O. Register enabled pull-up — A/D Converter analog input SDO PCS1 — AN5 PCS1 AN PC6 PCPU PCS1 ST CMOS General purpose I/O. Register enabled pull-up SCK PCS1 ST CMOS SPI serial clock SCL PCS1 ST NMOS I2C clock line AN6 PCS1 AN PC7 PCPU PCS1 ST SDI PCS1 ST SDA PCS1 ST AN7 PCS1 AN — — A/D Converter analog input A/D Converter analog input CMOS General purpose I/O. Register enabled pull-up — SPI data input NMOS I2C data line — A/D Converter analog input 11 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Pad Name PD0 PD1/SCSA PD2/INT1 PD3/SDIA PD4/SDOA PD5/SCKA PD6/CLKO PD7/PTPI_1/ PTP_1 Function OPT I/T PD0 PDPU PDS0 O/T ST CMOS General purpose I/O. Register enabled pull-up PD1 PDPU PDS0 ST CMOS General purpose I/O. Register enabled pull-up SCSA PDS0 ST CMOS SPIA slave select PD2 PDPU ST CMOS General purpose I/O. Register enabled pull-up INT1 INTEG INTC0 ST PD3 PDPU PDS0 ST SDIA PDS0 ST PD4 PDPU PDS1 ST CMOS General purpose I/O. Register enabled pull-up SDOA PDS1 — CMOS SPIA data output PD5 PDPU PDS1 ST CMOS General purpose I/O. Register enabled pull-up SCKA PDS1 ST CMOS SPIA serial clock PD6 PDPU PDS1 ST CMOS General purpose I/O. Register enabled pull-up CLKO PDS1 — CMOS HXT oscillator output with buffer PD7 PDPU PDS1 ST CMOS General purpose I/O. Register enabled pull-up PTPI_1 PDS1 IFS ST PTP_1 PDS1 — — Description External Interrupt 1 CMOS General purpose I/O. Register enabled pull-up — — SPIA data input PTM capture input CMOS PTM output OSC1 OSC1 — HXT — HXT oscillator pin OSC2 OSC2 — — HXT HXT oscillator pin VDD VDD — PWR — VSS VSS — PWR — Negative power supply, ground. SP+ SP+ — — AO Power amplifier output SPAUD_IN Positive power supply SP- — — AO Power amplifier output AUD_IN — AN — Power amplifier input BIAS BIAS — — AO Power amplifier voltage bias reference AUD AUD — — AO D/A converter output AVDD1 — PWR — Audio D/A converter positive power supply AVDD_PA — PWR — Audio Power Amplifier positive power supply Audio D/A converter negative power supply AVDD1 AVDD_PA AVSS1 AVSS_PA AVDD3 VAGREF VAG Rev. 1.30 AVSS1 — PWR — AVSS_PA — PWR — Audio Power Amplifier negative power supply AVDD3 — PWR — Audio PCM A/D converter positive power supply VAGREF — — AO PCM A/D converter analog ground reference voltage This pin should be left open or connected a bypass capacitor to ground. VAG — — AO PCM A/D converter analog ground voltage This pin should be connected a bypass capacitor to ground. 12 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Function OPT I/T O/T TI+ Pad Name TI+ — AN — Operational Amplifier non-inverting input TI- TI- — AN — Operational Amplifier inverting input TG AVSS3 Description TG — — AO Operational Amplifier gain setting output AVSS3 — PWR — Audio PCM A/D converter negative power supply Legend: I/T: Input type O/T: Output type OPT: Optional by configuration option (CO) or register option PWR: Power CO: Configuration option ST: Schmitt Trigger input AN: Analog input AO: Analog output; CMOS: CMOS output NMOS: NMOS output SCOM: Software controlled LCD COM HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator Absolute Maximum Ratings Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V Storage Temperature.....................................................................................................-50˚C to 125˚C Operating Temperature...................................................................................................-40˚C to 85˚C IOL Total...................................................................................................................................... 80mA IOH Total.....................................................................................................................................-80mA Total Power Dissipation.......................................................................................................... 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to these devices. Functional operation of these devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect devices reliability. Rev. 1.30 13 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU D.C. Characteristics Ta=25°C Symbol VDD VDD_IO Parameter Operating Voltage I/O Port D Supply Voltage Operating Current (HXT) IDD Operating Current (LXT) Operating Current (LIRC) Standby Current (IDLE0 Mode) Standby Current (IDLE0 Mode) ISTB Standby Current (IDLE1 Mode) Test Conditions VDD ─ Conditions Typ. Max. Unit V fSYS=4MHz 2.2 ─ 5.5 fSYS=8MHz 2.4 ─ 5.5 V fSYS=16MHz 3.6 ─ 5.5 V 2.2 ─ VDD V 3V fSYS=fH/2, No load, 5V all peripherals off, WDT enable ─ ─ ─ 1.2 2.0 mA ─ 3.2 4.8 mA 3V fSYS=fH/4, No load, 5V all peripherals off, WDT enable ─ 0.9 1.3 mA ─ 2.6 3.9 mA 3V fSYS=fH/8, No load, 5V all peripherals off, WDT enable ─ 0.8 1.2 mA ─ 2.3 3.5 mA 3V fSYS=fH/16, No load, 5V all peripherals off, WDT enable ─ 0.7 1.05 mA ─ 2.1 3.15 mA 3V fSYS=fH/32, No load, all 5V peripherals off, WDT enable ─ 0.69 1.04 mA ─ 2.05 3.08 mA 3V fSYS=fH/64, No load, all 5V peripherals off, WDT enable ─ 0.67 1.01 mA ─ 2.01 3.0 mA 3V fSYS=fSUB=fLXT, LXTSP=0 No load, all peripherals off, 5V WDT enable ─ 10 20 μA ─ 30 50 μA 3V fSYS=fSUB=fLXT, LXTSP=1 No load, all peripherals off, 5V WDT enable ─ 10 20 μA ─ 40 60 μA 3V fSYS=fSUB=fLIRC No load, all peripherals off, 5V WDT enable ─ 10 20 μA ─ 30 50 μA 3V LXT on, LXTSP=0 No load, all peripherals off, 5V WDT enable ─ 4 8 μA ─ 6 12 μA 3V LXT on, LXTSP=1 No load, all peripherals off, 5V WDT enable ─ 5 10 μA ─ 7 14 μA 3V LIRC on No load, all peripherals off, 5V WDT enable ─ 1.3 3.0 μA ─ 2.2 5.0 μA 3V fSYS=fH/4=4MHz No load, all peripherals off, 5V WDT enable ─ 0.6 1.2 mA ─ 1.6 3.2 mA 3V fSYS=fH/2=8MHz No load, all peripherals off, 5V WDT enable ─ 0.7 1.4 mA ─ 1.8 3.6 mA ─ 2.0 4.0 mA fSYS=fH=16MHz 5V No load, all peripherals off, WDT enable Rev. 1.30 Min. Standby Current (Sleep Mode) 3V LIRC off No load, all peripherals off, 5V WDT disable ─ 0.1 1.0 μA ─ 0.3 2.0 μA Standby Current (Sleep Mode) 3V LIRC on No load, all peripherals off, 5V WDT enable ─ 1.3 5.0 μA ─ 2.2 10 μA 14 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Symbol VIL VIH IOL Parameter Test Conditions VDD Conditions Unit V ─ 0 ─ 1.5 ─ ─ 0 ─ 0.2VDD V Input Low Voltage for I/O Port D (Supplied by VDD_IO) 5V ─ 0 ─ 1.5 V ─ ─ 0 ─ 0.2VDD_IO V Input High Voltage for I/O Ports or Input Pins 5V ─ 3.5 ─ 5.0 V ─ ─ 0.8VDD ─ VDD V Input High Voltage for I/O Port D (Supplied by VDD_IO) 5V ─ 3.5 ─ 5.0 V ─ ─ 0.8VDD_IO ─ VDD_IO V 3V VOL = 0.1VDD Sink Current for I/O Port (Except I/O Port D and CLKO pins) 5V VOL = 0.1VDD 8 16 ─ mA 16 32 ─ mA 3V VOL = 0.1VDD 2 4 ─ mA 5V VOL = 0.1VDD 5 10 ─ mA 5V VOL = 0.1VDD 10.5 14 ─ mA Sink Current for I/O Port D Source Current for I/O Port D Source Current for CLKO Pin Rev. 1.30 Max. 5V 3V VOL = 0.1VDD 2 3 ─ mA -3.75 -7.5 ─ mA -7.5 -15 ─ mA 3V VOH = 0.9VDD -1 -2 ─ mA 3V VOH = 0.9VDD Source Current for I/O Port (Except I/O Port D and CLKO pins) 5V VOH = 0.9VDD RPH Typ. Input Low Voltage for I/O Ports or Input Pins Sink Current for CLKO Pin IOH Min. Pull-high Resistance for I/O Ports 5V VOH = 0.9VDD -2.5 -5 ─ mA 5V VOH = 0.9VDD 6 8 ─ mA 3V VOH = 0.9VDD 3 4 ─ mA 3V ─ 20 60 100 kΩ 5V ─ 10 30 50 kΩ 15 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU A.C. Characteristics Ta=25°C Symbol Parameter Test Condition VDD Condition Min. Typ. Max. Unit fHXT High Speed Crystal Oscillator Clock (HXT) 2.2~ 5.5V ─ ─ 16 ─ MHz fLXT Low Speed Crystal Oscillator Clock (LXT) ─ ─ ─ 32.768 ─ kHz Ta = 25°C -10% 32 +10% kHz fLIRC Low Speed RC Oscillator Clock (LIRC) 2.2V~ Ta = -40°C to 85°C 5.5V -50% 32 +60% kHz tTCK xTCK pin Minimum Input Pulse Width ─ ─ 0.3 ─ ─ μs tTPI STPI_n, PTPI_n pin Minimum Input Pulse Width ─ ─ 0.3 ─ ─ μs tINT Interrupt Pin Minimum Input Pulse Width 5V System Start-up Timer Period (Wake-up from Power Down Mode, fSYS off) tSST System Start-up Timer period (SLOW Mode → NORMAL Mode) (NORMAL Mode → SLOW Mode) 10 ─ ─ μs ─ ─ fSYS = fH =fHXT ─ 128 ─ ─ tSYS ─ fSYS = fSUB =fLXT 1024 ─ ─ tSYS ─ fSYS = fSUB = fLIRC 2 ─ ─ tSYS ─ fSYS = fSUB → fHXT or fH=fHXT, fHXT off → on 1024 ─ ─ tHXT ─ fSYS = fH → fLXT or fSUB = fLIRC → fLXT, fLXT off → on 1024 ─ ─ tLXT ─ fSYS = fH → fLIRC or fSUB = fLXT → fLIRC, fLIRC off → on 2 ─ ─ tLIRC System Start-up Timer Period (Wake-up from Power Down Mode, fSYS on) ─ ─ 2 ─ ─ tSYS System Start-up Timer Period (WDT Hardware Reset) ─ ─ 0 ─ ─ tSYS System Reset Delay Time (Power-on Reset, MCD Reset LVR Hardware/Software Reset, WDTC/RSTC Software Reset) ─ ─ 25 50 100 ms System Reset Delay Time (WDT Hardware Reset) ─ ─ 8.3 16.7 33.3 ms tEERD EEPROM Read Time ─ ─ ─ 2 4 tSYS tEEWR EEPROM Write Time ─ ─ ─ 2 4 ms tRSTD Note: tSYS= 1/fSYS Rev. 1.30 16 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU A/D Converter Characteristics Ta=25°C Symbol Test Conditions Parameter Conditions VDD Typ. Max. Unit AVDD A/D Converter Operating Voltage ─ 2.7 ─ 5.5 V VADI A/D Converter Input Voltage ─ ─ 0 ─ VDD/VREF V VREF A/D Converter Reference Voltage ─ ─ 2 ─ VDD+0.1V V VREF=VDD, tADCK =0.5μs ─ ─ ±3 LSB VREF=VDD, tADCK =0.5μs ─ ─ ±4 LSB 3V DNL Differential Non-linearity INL Integral Non-linearity IADC Additional Current Consumption for A/D Converter Enable 3V tADCK A/D Converter Clock Period ─ tADC A/D Conversion Time (A/D Sample and Hold Time) tON2ST A/D Converter On-to-Start Time 5V 3V 5V AVDD=VDD Min. ─ 1.0 2.0 mA ─ 1.5 3.0 mA ─ 0.5 ─ 10 μs ─ ─ ─ 16 ─ tADCK ─ ─ 4 ─ ─ μs 5V No load, tADCK =0.5μs LVD/LVR Electrical Characteristics Ta=25°C Symbol VLVR VLVD Parameter Low Voltage Reset Voltage Low Voltage Detector Voltage Test Conditions Min. Typ. LVR Enable, voltage select 2.1V 2.1 LVR Enable, voltage select 2.55V Typ. - 5% 2.55 VDD ─ ─ Conditions LVR Enable, voltage select 3.15V 3.15 LVR Enable, voltage select 3.8V 3.8 LVD Enable, voltage select 2.0V 2.0 LVD Enable, voltage select 2.2V 2.2 LVD Enable, voltage select 2.4V 2.4 LVD Enable, voltage select 2.7V LVD Enable, voltage select 3.0V Typ. - 5% 2.7 3.0 LVD Enable, voltage select 3.3V 3.3 LVD Enable, voltage select 3.6V 3.6 LVD Enable, voltage select 4.0V Unit Typ. + 5% V Typ. + 5% V 4.0 Typ. - 5% 1.04 Typ. + 5% V ─ 20 25 μA VBG Bandgap Reference Voltage ─ IOP LVDLVR Operating Current 5V LVD/LVR Enable, VBGEN=1 ─ 180 200 μA tBGS VBG Turn on Stable Time ─ No load ─ ─ 150 μs ─ For LVR enable, VBGEN=0, LVD off→on ─ ─ 15 μs ─ For LVR disable, VBGEN=0, LVD off→on ─ ─ 150 μs tLVDS LVDO stable time ─ Max. LVD/LVR Enable, VBGEN=0 tLVR Minimum Low Voltage Width to Reset ─ ─ 120 240 480 μs tLVD Minimum Low Voltage Width to Interrupt ─ ─ 60 120 240 μs Rev. 1.30 17 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU 16-bit PCM A/D Converter Electrical Characteristics Ta=25°C Symbol AVDD3 Test Conditions Parameter 16-bit PCM A/D Converter Operating Voltage SNR Signal to Noise Ratio Fs Sampling Rate VDD Conditions ─ ─ Min. Typ. Max. Unit 2.4 ─ 5.5 V ─ 70 ─ dB 2.4V~ Note 5.5V tADC_RESB Minimum A/D Converter Reset Pulse Width ─ ─ 8 12 16 kHz ─ ─ 100 ─ ─ μs D/A Converter Electrical Characteristics Ta=25°C Symbol Test Conditions Parameter VDD AVDD1 16-bit Audio D/A Converter Operating Voltage ─ THD+N THD+N(Note) 3V Conditions Min. ─ 10kW Load Typ. Max. Unit 2.2 ─ 5.5 V ─ -55 ─ dB Note: sine wave input @ 1kHz, -6dB. Power Amplifier Electrical Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit AVDD_PA Audio Power Amplifier Operating Voltage ─ 2.2 ─ 5.5 V THD+N THD+N(Note) 3V 8W Load ─ -51 ─ dB POUT Output Power 3V 8W Load, THD=1% ─ 410 ─ mW 5V 8W Load, THD=1% ─ 1200 ─ mW ─ Note: sine wave input @ 1kHz, -6dB. Power-on Reset Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset ─ ─ ─ ─ 100 mV RR-POR VDD Raising Rate to Ensure Power-on Reset ─ ─ 0.035 ─ ─ V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset ─ ─ 1 ─ ─ ms Rev. 1.30 18 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes these devices suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HXT, LXT, or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. System Clocking and Pipelining Rev. 1.30 19 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter High Byte Low Byte (PCL) PC11~PC8 PC7~PC0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. Rev. 1.30 20 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU If the stack is overflow, the first Program Counter save in the stack will be lost. P ro g ra m T o p o f S ta c k S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r B o tto m C o u n te r S ta c k L e v e l 3 o f S ta c k P ro g ra m M e m o ry S ta c k L e v e l 8 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA LADD, LADDM, LADC, LADCM, LSUB, LSUBM, LSBC, LSBCM, LDAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA LAND, LOR, LXOR, LANDM, LORM, LXORM, LCPL, LCPLA • Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC LRRA, LRR, LRRCA, LRRC, LRLA, LRL, LRLCA, LRLC • Increment and Decrement: INCA, INC, DECA, DEC LINCA, LINC, LDECA, LDEC • Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI LSZ, LSZA, LSNZ, LSIZ, LSDZ, LSIZA, LSDZA Rev. 1.30 21 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For these devices series the Program Memory are Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 4K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer registers. 000H Initialisation Vector 00�H Interr�pt Vectors 03�H 038H n00H nFFH FFFH Look-�p Table 16 bits Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by these devices reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the corresponding table read instruction such as “TABRD [m]” or “TABRDL [m]” respectively when the memory [m] is located in sector 0. If the memory [m] is located in other sectors, the data can be retrieved from the program memory using the corresponding extended table read instruction such as “LTABRD [m]” or “LTABRDL [m] ”respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0". Rev. 1.30 22 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU The accompanying diagram illustrates the addressing data flow of the look-up table. A d d re s s L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r D a ta 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te Table Program Example The accompanying example shows how the table pointer and table data is defined and retrieved from the device. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is "0F00H" which refers to the start address of the last page within the 4K Program Memory of the device. The table pointer low byte register is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "0F06H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the page that TBHP pointed if the "TABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m] instruction is executed. Because the TBLH register is a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,07h ; initialise high table pointer movtbhp,a : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "0F06H" transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address "0F05H" transferred to tempreg2 and TBLH in this ; example the data "1AH" is transferred to tempreg1 and data "0FH" to ; register tempreg2 : org 0F00h ; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : Rev. 1.30 23 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller incircuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and reinsertion of the device. Holtek Writer Pins MCU Programming Pins Pin Description ICPDA PA0 Programming Serial Data/Address ICPCK PA2 Programming Clock VDD VDD Power Supply VSS VSS Ground The Program Memory and EEPROM data memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, the user must take care of the ICPDA and ICPCK pins for data and clock programming purposes to ensure that no other outputs are connected to these two pins. W r ite r C o n n e c to r S ig n a ls M C U W r ite r _ V D D V D D IC P D A P A 0 IC P C K P A 2 W r ite r _ V S S V S S * P r o g r a m m in g P in s * T o o th e r C ir c u it Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance of * must be less than 1nF. Rev. 1.30 24 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU On-Chip Debug Support – OCDS There is an EV chip named HT66VV240 which is used to emulate the real MCU device named HT66FV240. The EV chip device also provides the "On-Chip Debug" function to debug the real MCU device during development process. The EV chip and real MCU devices, HT66VV240 and HT66FV240, are almost functional compatible except the "On-Chip Debug" function. Users can use the EV chip device to emulate the real MCU device behaviors by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip device for debugging, the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the real MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide". Holtek e-Link Pins EV Chip OCDS Pins Pin Description OCDSDA OCDSDA On-Chip Debug Support Data/Address input/output OCDSCK OCDSCK On-Chip Debug Support Clock input VDD VDD Power Supply VSS VSS Ground In Application Programming – IAP This device offers IAP function to update data or application program to flash ROM. Users can define any ROM location for IAP, but there are some features which user must notice in using IAP function. • Erase Block: 256 words/block • Writing: 4 words/time • Reading: 1 word/time In Application Program Control Registers The Address register, FARL and FARH, the Data registers, FD0L/FD0H, FD1L/FD1H, FD2L/FD2H and FD3L/FD3H, and the Control registers, FC0, FC1 and FC2, are the corresponding Flash access registers located in Data Memory sector 1 for IAP. If using the indirect addressing method to access the FC0, FC1 and FC2 registers, all read and write operations to the registers must be performed using the Indirect Addressing Register, IAR1 or IAR2, and the Memory Pointer pair, MP1L/MP1H or MP2L/MP2H. Because the FC0, FC1 and FC2 control registers are located at the address of 50H~52H in Data Memory sector 1, the desired value ranged from 50H to 52H must first be written into the MP1L or MP2L Memory Pointer low byte and the value "01H" must also be written into the MP1H or MP2H Memory Pointer high byte. Rev. 1.30 25 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Bit Register Name 7 6 5 4 3 2 1 0 FC0 CFWEN FMOD2 FMOD1 FMOD0 FWPEN FWT FRDEN FRD FC1 D7 D6 D5 D4 D3 D2 D1 D0 FC2 — — — — — — — CLWB FARL A7 A6 A5 A4 A3 A2 A1 A0 FARH — — — — A11 A10 A9 A8 FD0L D7 D6 D5 D4 D3 D2 D1 D0 FD0H D15 D14 D13 D12 D11 D10 D9 D8 FD1L D7 D6 D5 D4 D3 D2 D1 D0 FD1H D15 D14 D13 D12 D11 D10 D9 D8 FD2L D7 D6 D5 D4 D3 D2 D1 D0 FD2H D15 D14 D13 D12 D11 D10 D9 D8 FD3L D7 D6 D5 D4 D3 D2 D1 D0 FD3H D15 D14 D13 D12 D11 D10 D9 D8 IAP Registers List • FC0 Register Bit 7 6 5 4 3 2 1 0 Name CFWEN FMOD2 FMOD1 FMOD0 FWPEN FWT FRDEN FRD R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 1 1 0 0 0 0 Bit 7CFWEN: Flash Memory Write enable control 0: Flash memory write function is disabled 1: Flash memory write function has been successfully enabled When this bit is cleared to 0 by application program, the Flash memory write function is disabled. Note that writing a "1" into this bit results in no action. This bit is used to indicate that the Flash memory write function status. When this bit is set to 1 by hardware, it means that the Flash memory write function is enabled successfully. Otherwise, the Flash memory write function is disabled as the bit content is zero. Bit 6~4FMOD2~FMOD0: Mode selection 000: Write program memory 001: Block erase program memory 010: Reserved 011: Read program memory 10x: Reserved 110: FWEN mode – Flash memory Write function Enabled mode 111: Reserved Bit 3FWPEN: Flash memory Write Procedure Enable control 0: Disable 1: Enable When this bit is set to 1 and the FMOD field is set to "110", the IAP controller will execute the "Flash memory write function enable" procedure. Once the Flash memory write function is successfully enabled, it is not necessary to set the FWPEN bit any more. Bit 2FWT: Flash memory Write Initiate control 0: Do not initiate Flash memory write or Flash memory write process is completed 1: Initiate Flash memory write process This bit is set by software and cleared by hardware when the Flash memory write process is completed. Rev. 1.30 26 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Bit 1FRDEN: Flash memory Read Enable control 0: Flash memory read disable 1: Flash memory read enable Bit 0FRD: Flash memory Read Initiate control 0: Do not initiate Flash memory read or Flash memory read process is completed 1: Initiate Flash memory read process This bit is set by software and cleared by hardware when the Flash memory read process is completed. • FC1 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: Whole chip reset pattern When user writes a specific value of "55H" to this register, it will generate a reset signal to reset whole chip. • FC2 Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — — CLWB R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7~1 Unimplemented, read as 0. Bit 0CLWB: Flash memory Write Buffer Clear control 0: Do not initiate Write Buffer Clear process or Write Buffer Clear process is completed 1: Initiate Write Buffer Clear process This bit is set by software and cleared by hardware when the Write Buffer Clear process is completed. • FARL Register Bit 7 6 5 4 3 2 1 0 Name A7 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Flash Memory Address bit 7 ~ bit 0 • FARH Register Bit 7 6 5 4 3 2 1 0 Name — — — — A11 A10 A9 A8 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0. Bit 3~0 Flash Memory Address bit 11 ~ bit 0 • FD0L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.30 The first Flash Memory data bit 7 ~ bit 0 27 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU • FD0H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The first Flash Memory data bit 15 ~ bit 8 • FD1L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 3 2 1 0 Bit 7~0 The second Flash Memory data bit 7 ~ bit 0 • FD1H Register Bit 7 6 5 4 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The second Flash Memory data bit 15 ~ bit 8 • FD2L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The third Flash Memory data bit 7 ~ bit 0 • FD2H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The third Flash Memory data bit 15 ~ bit 8 • FD3L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The fourth Flash Memory data bit 7 ~ bit 0 • FD3H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.30 The fourth Flash Memory data bit 15 ~ bit 8 28 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Flash Memory Write Function Enable Procedure In order to allow users to change the Flash memory data through the IAP control registers, users must first enable the Flash memory write operation by the following procedure: • Write "110" into the FMOD2~FMOD0 bits to select the FWEN mode. • Set the FWPEN bit to "1". The step 1 and step 2 can be executed simultaneously. • The pattern data with a sequence of 00H, 04H, 0DH, 09H, C3H and 40H must be written into the FD1L, FD1H, FD2L, FD2H, FD3L and FD3H registers respectively. • A counter with a time-out period of 300μs will be activated to allow users writing the correct pattern data into the FD1L/FD1H ~ FD3L/FD3H register pairs. The counter clock is derived from LIRC oscillator. • If the counter overflows or the pattern data is incorrect, the Flash memory write operation will not be enabled and users must again repeat the above procedure. Then the FWPEN bit will automatically be cleared to 0 by hardware. • If the pattern data is correct before the counter overflows, the Flash memory write operation will be enabled and the FWPEN bit will automatically be cleared to 0 by hardware. The CFWEN bit will also be set to 1 by hardware to indicate that the Flash memory write operation is successfully enabled. • Once the Flash memory write operation is enabled, the user can change the Flash ROM data through the Flash control register. • To disable the Flash memory write operation, the user can clear the CFWEN bit to 0. Is counter overflow ? Flash Memory Write Function Enable Procedure No Yes FWPEN=0 Set FMOD [2:0] =110 & FWPEN=1 à Select FWEN mode & Start Flash write Hardware activate a counter Is pattern correct ? Wrtie the following pattern to Flash Data registers FD1L= 00h , FD1H = 04h FD2L= 0Dh , FD2H = 09h FD3L= C3h , FD3H = 40h No Yes CFWEN = 1 CFWEN=0 Success Failed END Flash Memory Write Function Enable Procedure Rev. 1.30 29 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Flash Memory Write Procedure After the Flash memory write function is successfully enabled through the preceding IAP procedure, users must first erase the corresponding Flash memory block and then initiate the Flash memory write operation. Since the number of the block erase operation is 256 words per block, the available block erase address is only specified by FARH register and the content in the FARL register is not used to specify the block address. Erase Block FARH [3:0] FARL [7:0] 0 0000 xxxx xxxx 1 0001 xxxx xxxx 2 0010 xxxx xxxx 3 0011 xxxx xxxx 4 0100 xxxx xxxx 5 0101 xxxx xxxx 6 0110 xxxx xxxx 7 0111 xxxx xxxx 8 1000 xxxx xxxx 9 1001 xxxx xxxx 10 1010 xxxx xxxx 11 1011 xxxx xxxx 12 1100 xxxx xxxx 13 1101 xxxx xxxx 14 1110 xxxx xxxx 15 1111 xxxx xxxx "x": don’t care Rev. 1.30 30 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Write Flash Memory Flash Memory Write Function Enable Procedure Set Block Erase address: FARH/FARL Set FMOD [2:0]=001 & FWT=1 à Select “Block Erase mode” & Initiate write operation No FWT=0 ? Yes Set FMOD [2:0]=000 à Select “Write Flash Mode” Set Write starting address: FARH/FARL Write data to data register: FD0L/FD0H, FD1L/FD1H, FD2L/FD2H, FD3L/FD3H, Set FWT=1 No FWT=0 ? Yes Write Finish ? No Yes Clear CFWEN=0 END Write Flash Memory Procedure Rev. 1.30 31 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Read Flash Memory Set FMOD [�:0]=011 & FRDEN=1 Set Flash Address Registers FARH=xxh� FARL=xxh Set FRD=1 No FRD=0 ? Yes Read data val�e: FD0L=xxh� FD0H=xxh Read Finish ? No Yes Clear FRDEN bit END Read Flash Memory Procedure Note: When the FWT or FRD bit is set to 1, the MCU is stopped. Rev. 1.30 32 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Data Memory The Data Memory is an 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two types, the first of Data Memory is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Switching between the different Data Memory sectors is achieved by properly setting the Memory Pointers to correct value. Structure The Data Memory is subdivided into several sectors, all of which are implemented in 8-bit wide Memory. Each of the Data Memory sectors is categorized into two types, the Special Purpose Data Memory and the General Purpose Data Memory. The address range of the Special Purpose Data Memory for the device is from 00H to 7FH while the address range of the General Purpose Data Memory is from 80H to FFH. Type Special Purpose Data Memory General Purpose Data Memory Sector 0 Sector 1 Sector 2 Start Address 00H 00H — End Address 7FH 7FH — Capacity-bytes 128 128 — Start Address 80H 80H 80H End Address FFH FFH FFH Capacity-bytes 128 128 128 Data Memory Summary 00H Special P�rpose Data Memory �0H 50H 5CH 7FH 80H General P�rpose Data Memory FFH Sector 0 Sector 1 Sector � Data Memory Structure General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user programing for both reading and writing operations. By using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Rev. 1.30 33 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value "00H". 00H 01H 0�H 03H 0�H 05H 06H 07H 08H 0�H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 1�H 13H 1�H 15H 16H 17H 18H 1�H 1AH 1BH 1CH 1DH 1EH 1FH �0H �1H ��H �3H ��H �5H �6H �7H �8H ��H �AH �BH �CH �DH �EH �FH 30H 31H 3�H 33H 3�H 35H 36H 37H 38H 3�H 3AH 3BH 3CH 3DH 3EH 3FH Bank 0 IAR0 MP0 IAR1 MP1L MP1H ACC PCL TBLP TBLH TBHP STATUS IAR� MP�L MP�H INTC0 PA PAC PAPU PAWU RSTFC PB PBC PBPU PSCR TB0C TB1C SCC HXTC LXTC RSTC CTRL CTMC0 CTMC1 CTMDL CTMDH CTMAL CTMAH CTMRP LVDC LVRC STMC0 STMC1 STMDL STMDH STMAL STMAH STMRP INTEG INTC1 INTC� INTC3 MFI0 MFI1 MFI� MFI3 SCOMC Bank 1 ~ Bank 2 Bank 0 �0H �1H EEA EED ��H �3H PTMC0 ��H PTMC1 �5H PTMDL �6H PTMDH �7H PTMAL �8H PTMAH PTMRPL ��H PTMRPH �AH �BH �CH �DH WDTC PCPU �EH PC �FH PCC 50H PDPU 51H PD 5�H PDC 53H ADRL 5�H ADRH 55H ADCR0 56H 57H ADCR1 58H PAS0 PAS1 5�H PBS0 5AH 5BH PCS0 5CH PCS1 5DH PDS0 5EH PDS1 IFS 5FH SIMTOC 60H SIMC0 61H SIMC1 6�H SIMD 63H SIMA/SIMC� 6�H SPIAC0 65H SPIAC1 66H SPIAD 67H SPIADMAC 68H 6�H SPIA_DMA_LEN 6AH SPIA_DMA_ADDR 6BH SPIA_DMA_RW_P 6CH 6DH 6EH USVC 6FH PGAC 70H RECPLAC 71H COMPANDC 7�H RECDL 73H RECDH 7�H PLADL 75H PLADH 76H 77H Bank 1 EEC Bank 2 FC0 FC1 FC� FARL FARH FD0L FD0H FD1L FD1H FD�L FD�H FD3L FD3H 7FH : Un�sed� read as 00H Special Purpose Data Memory Structure Rev. 1.30 34 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section. However, several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/ MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only from Sector 0 while the IAR1 register together with MP1L/MP1H register pair and IAR2 register together with MP2L/MP2H register pair can access data from any Data Memory sector. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L and MP2H, are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Sector 0, while MP1L/MP1H together with IAR1 and MP2L/MP2H together with IAR2 are used to access data from all data sectors according to the corresponding MP1H or MP2H register. Direct Addressing can be used in all data sectors using the corresponding instruction which can address all available data memory space. Indirect Addressing Program Example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: : The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. Rev. 1.30 35 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Rev. 1.30 36 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), SC flag, CZ flag, power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/ logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC, C, SC and CZ flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction. • TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out. • SC is the result of the "XOR" operation which is performed by the OV flag and the MSB of the current instruction operation result. • CZ is the operational result of different flags for different instuctions. Refer to register definitions for more details. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 1.30 37 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU STATUS Register Bit 7 6 5 4 3 2 1 0 Name SC CZ TO PDF OV Z AC C R/W R R R R R/W R/W R/W R/W POR x x 0 0 x x x x "x": unknown Bit 7SC: The result of the "XOR" operation which is performed by the OV flag and the MSB of the instruction operation result. Bit 6CZ: The the operational result of different flags for different instuctions. For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag. For SBC/ SBCM/ LSBC/ LSBCM instructions, the CZ flag is the "AND" operation result which is performed by the previous operation CZ flag and current operation zero flag. For other instructions, the CZ flag willl not be affected. Bit 5TO: Watchdog Time-out flag 0: After power up ow executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred Bit 4PDF: Power down flag 0: After power up ow executing the "CLR WDT" instruction 1: By executing the "HALT" instructin Bit 3OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles, in addition, or no borrow from the high nibble into the low nibble in substraction Bit 0C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation The "C" flag is also affected by a rotate through carry instruction. Rev. 1.30 38 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU EEPROM Data Memory The device contains an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 128×8 bits. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in sector 0 and a single control register in sector 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in sector 0, they can be directly accessed in the same was as any other Special Function Register. The EEC register, however, being located in sector 1, can be read from or written to indirectly using the MP1H/MP1L or MP2H/MP2L Memory Pointer pair and Indirect Addressing Register, IAR1 or IAR2. Because the EEC control register is located at address 40H in sector 1, the Memory Pointer low byte register, MP1L or MP2L, must first be set to the value 40H and the Memory Pointer high byte register, MP1H or MP2H, set to the value, 01H, before any operations on the EEC register are executed. Bit Register Name 7 6 5 4 3 2 1 0 EEA — EEA6 EEA5 EEA4 EEA3 EEA2 EEA1 EEA0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD EEPROM Registers List EEA Register Bit 7 6 5 4 3 2 1 0 Name — EEA6 EEA5 EEA4 EEA3 EEA2 EEA1 EEA0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as 0. Bit 6~0EEA6~EEA0: Data EEPROM address bit 6~bit0 EED Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: Data EEPROM data bit 7~bit0 Rev. 1.30 39 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0. Bit 3WREN: Data EEPROM write enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2WR: EEPROM write control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1RDEN: Data EEPROM read enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0RD: EEPROM read control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set to "1" at the same time in one instruction. The WR and RD can not be set to "1" at the same time. Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Rev. 1.30 40 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Writing Data to the EEPROM To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. Then the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered on, the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Memory Pointer high byte register, MP1H, will be reset to zero, which means that Data Memory sector 0 will be selected. As the EEPROM control register is located in sector 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However, as the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program. Rev. 1.30 41 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Memory Pointer high byte register could be normally cleared to zero as this would inhibit access to sector 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Programming Example • Reading data from the EEPROM − polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 040H MOV MP1L, A MOV A, 01H MOV MP1H, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR MP1H MOV A, EED MOV READ_DATA, A ; user defined address ; setup memory pointer low byte MP1L ; MP1L points to EEC register ; setup Memory Pointer high byte MP1H ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ; disable EEPROM write ; move read data to register • Writing Data to the EEPROM − polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, EEPROM_DATA MOV EED, A MOV A, 040H MOV MP1L, A MOV A, 01H MOV MP1H, A CLR EMI SET IAR1.3 SET IAR1.2 SET EMI BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR MP1H Rev. 1.30 ; user defined address ; user defined data ; setup memory pointer low byte MP1L ; MP1L points to EEC register ; setup Memory Pointer high byte MP1H ; set WREN bit, enable write operations ; start Write Cycle - set WR bit ; check for write cycle end ; disable EEPROM write 42 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Oscillator Various oscillator types offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of application program and relevant control registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external components as well as fully integrated internal oscillator, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through register programming. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Type Name Freq. Pins External High Speed Crystal HXT 16 MHz OSC1/OSC2 External Low Speed Crystal LXT 32.768 kHz XT1/XT2 Internal Low Speed RC LIRC 32 kHz — Oscillator Types System Clock Configurations There are three methods of generating the system clock, one high speed oscillator and two low speed oscillators. The high speed oscillator is the external crystal/ceramic oscillator. The two low speed oscillators are the internal 32 kHz RC oscillator and the external 32.768 kHz crystal oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the CKS2~CKS0 bits in the SCC register and as the system clock can be dynamically selected. The actual source clock used for the low speed oscillators is chosen via the FSS bit in the SCC register. The frequency of the slow speed or high speed system clock is determined using the CKS2~CKS0 bits in the SCC register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. External Crystal/Ceramic Oscillator – HXT The External Crystal/Ceramic System Oscillator is the high frequency oscillator, which is the default oscillator clock source after power on. For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. Rev. 1.30 43 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU OSC1 OSC� Crystal/Resonator Oscillator MCD fH/� High Speed Oscillation HXTEN MCD Reset fH/� fH/8 fH HXT Prescaler fH/16 fSYS fH/3� Low Speed Oscillation LIRC LXTEN fH/6� FSS fLIRC CKS�~CKS0 fSUB fSUB LXT fLXT MCD MCD Reset System Clock Configurations External 32.768 kHz Crystal Oscillator – LXT The External 32.768 kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via a software control bit, FSS. This clock source has a fixed frequency of 32.768 kHz and requires a 32.768 kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768 kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. After the LXT oscillator is enabled by setting the LXTEN bit to 1, there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer’s specification. The external parallel feedback resistor, Rp, is required. The pin-shared software control bits determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O pins. Rev. 1.30 44 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU • If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O pins. • If the LXT oscillator is used for any clock source, the 32.768 kHz crystal should be connected to the XT1/XT2 pins. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. External LXT Oscillator LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Speed-Up Mode and the Low-Power Mode. The mode selection is executed using the LXTSP bit in the LXTC register LXTSP LXT Operating Mode 0 Low Power 1 Speed up When the LXTSP bit is set to high, the LXT Quick Start Mode will be enabled. In the Speed-Up Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up, it can be placed into the Low-Power Mode by clearing the LXTSP bit to zero and the oscillator will continue to run bit with reduced current consumption. It is important to note that the LXT operating mode switching must be properly controlled before the LXT oscillator clock is selected as the system clock source. Once the LXT oscillator clock is selected as the system clock source using the CKS bit field and FSS bit in the SCC register, the LXT oscillator operating mode can not be changed. It should be note, that no matter what condition the LXTSP is set to, the LXT oscillator will always function normally. The only difference is that it will take more time to start up if in the Low Power Mode. Internal 32kHz Oscillator – LIRC The Internal 32 kHz System Oscillator is one of the low frequency oscillator choices, which is selected via a software control bit, FSS. It is a fully integrated RC oscillator with a typical frequency of 32 kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25˚C degrees, the fixed oscillation frequency of 32 kHz will have a tolerance within 10%. Supplementary Oscillators The low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to two other device functions. These are the Watchdog Timer and the Time Base Interrupts. Rev. 1.30 45 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock selections using register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, fH, or low frequency, fSUB, source, and is selected using the CKS2~CKS0 bits in the SCC register. The high speed system clock is sourced from an HXT oscillator. The low speed system clock source can be sourced from the internal clock fSUB. If fSUB is selected then it can be sourced by either the LXT or LIRC oscillators, selected via configuring the FSS bit in the SCC register. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. The CLKO signal which is derived from the HXT oscillator is shared with an I/O line and can be sent out to the external pin which is determined by the corresponding pin-shared function selection bits. The CLKO output slew rate can be programmed using the SR1 and SR0 bits in the CTRL register. CLKO MCD fH/� High Speed Oscillation HXTEN MCD Reset fH/� fH/8 fH HXT Prescaler fH/16 fSYS fH/3� Low Speed Oscillation LXTEN LXT fH/6� FSS fLXT CKS�~CKS0 fSUB fSUB LIRC MCD fLIRC MCD Reset WDT fLIRC LVR System Clock Configurations Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation can be stopped to conserve the power or continue to oscillate to provide the clock source, fH~fH/64, for peripheral circuit to use, which is determined by configuring the corresponding high speed oscillator enable control bit. Rev. 1.30 46 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP, IDLE0, IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve power. Operation Mode CPU NORMAL On SLOW On Register Setting FHIDEN FSIDEN CKS2~CKS0 x x 000~110 x x IDLE0 Off 0 1 IDLE1 Off 1 1 IDLE2 Off 1 0 SLEEP Off 0 0 fSYS fH fH~fH/64 On 111 fSUB 000~110 Off 111 On x On 000~110 On 111 Off x Off fSUB fLIRC On On On On Off On On On On On On Off On Off Off On/Off (1) On/Off (2) Note: 1. The fH clock will be switched on or off by configuring the corresponding oscillator enable bit in the SLOW mode. 2. The fLIRC clock can be switched on or off which is controlled by the WDT function being enabled or disabled. NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator. This mode operates allowing the microcontroller to operate normally with a clock source will come from the high speed oscillator, HXT oscillator. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from fSUB. The fSUB clock is derived from either the LIRC or LXT oscillator. SLEEP Mode The SLEEP Mode is entered when an HALT instruction is executed and when the FHIDEN and FSIDEN bit are low. In the SLEEP mode the CPU will be stopped. However the fSUB clock can still continue to operate if the WDT function is enabled. IDLE0 Mode The IDLE0 Mode is entered when an HALT instruction is executed and when the FSIDEN bit in the SCC register is high and the FHIDEN bit in the SCC register is low. In the IDLE0 Mode the CPU will be switched off but the low speed oscillator will be turned on to drive some peripheral functions. Rev. 1.30 47 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU will be switched off but both the high and low speed oscillators will be turned on to provide a clock source to keep some peripheral functions operational. IDLE2 Mode The IDLE2 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the CPU will be switched off but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational. Missing Clock Detector Function – MCD There is a Missing Clock Detector, MCD, in this device. The MCD is used to detect the high speed HXT or low speed LXT oscillator operation when the corresponding oscillator is enabled and selected as the system clock. If the oscillator is enabled to be used as the system clock and no clock cycle is detected by the MCD in a certain period of time, it means that the oscillator does not oscillate successfully and then the MCD will generate a signal to reset the microcontroller. Control Registers The registers, SCC, HXTC and LXTC, are used to control the system clock and the corresponding oscillator configurations. Bit Register Name 7 6 5 4 3 2 1 0 CTRL — — — — — — SR1 SR0 SCC CKS2 CKS1 CKS0 — — FSS FHIDEN FSIDEN HXTC — — — — — — HXTF HXTEN LXTC — — — — — LXTSP LXTF LXTEN System Operating Mode Control Registers List CTRL Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — SR1 SR0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as 0. Bit 1~0SR1~SR0: CLKO pin slew rate selection 00: 0 ns 01: 10 ns 10: 15 ns 11: 20 ns Rev. 1.30 48 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU SCC Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — — FSS FHIDEN FSIDEN R/W R/W R/W R/W — — R/W R/W R/W POR 0 1 0 — — 0 0 0 Bit 7~5CKS2~CKS0: System clock selection 000: fH 001: fH/2 010: fH/4 011: fH/8 100: fH/16 101: fH/32 110: fH/64 111: fSUB These three bits are used to select which clock is used as the system clock source. In addition to the system clock source directly derived from fH or fSUB, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4~3 Unimplemented, read as 0. Bit 2FSS: Low Frequency clock selection 0: LIRC 1: LXT Bit 1FHIDEN: High Frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing an "HALT" instruction. Bit 0FSIDEN: Low Frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing an "HALT" instruction. The LIRC oscillator is controlled by this bit together with the WDT function enable control when the LIRC is selected to be the low speed oscillator clock source or the WDT function is enabled respectively. If this bit is cleared to 0 but the WDT function is enabled, the LIRC oscillator will also be enabled. HXTC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — HXTF HXTEN R/W — — — — — — R R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as 0. Bit 1HXTF: HXT oscillator stable flag 0: HXT unstable 1: HXT stable This bit is used to indicate whether the HXT oscillator is stable or not. When the HXTEN bit is set to 1 to enable the HXT oscillator, the HXTF bit will first be cleared to 0 and then set to 1 after the HXT oscillator is stable. Bit 0HXTEN: HXT oscillator enable control 0: Disable 1: Enable Rev. 1.30 49 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU LXTC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — LXTSP LXTF LXTEN R/W — — — — — RW R R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as 0. Bit 2LXTSP: LXT oscillator speed-up control 0: Disable – Low power 1: Enable – Speed up This bit is used to control whether the LXT oscillator is operating in the low power or quick start mode. When the LXTSP bit is set to 1, the LXT oscillator will oscillate quickly but consume more power. If the LXTSP bit is cleared to 0, the LXT oscillator will consume less power but take longer time to stablise. It is important to note that this bit can not be changed after the LXT oscillator is selected as the system clock source using the CKS2~CKS0 and FSS bits in the SCC register. Bit 1LXTF: LXT oscillator stable flag 0: LXT unstable 1: LXT stable This bit is used to indicate whether the LXT oscillator is stable or not. When the LXTEN bit is set to 1 to enable the LXT oscillator, the LXTF bit will first be cleared to 0 and then set to 1 after the LXT oscillator is stable. Bit 0LXTEN: LXT oscillator enable control 0: Disable 1: Enable Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the CKS2~CKS0 bits in the SCC register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When an HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the FHIDEN and FSIDEN bits in the SCC register. Rev. 1.30 50 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU NORMAL fSYS=fH~fH/6� fH on CPU r�n fSYS on fSUB on SLOW fSYS=fSUB fSUB on CPU r�n fSYS on fH on/off IDLE0 HALT instr�ction exec�ted CPU stop FHIDEN=0 FSIDEN=1 fH off fSUB on SLEEP HALT instr�ction exec�ted CPU stop FHIDEN=0 FSIDEN=0 fH off fSUB off IDLE2 HALT instr�ction exec�ted CPU stop FHIDEN=1 FSIDEN=0 fH on fSUB off IDLE1 HALT instr�ction exec�ted CPU stop FHIDEN=1 FSIDEN=1 fH on fSUB on NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the CKS2~CKS0 bits to "111" in the SCC register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the FSS bit in the SCC register and therefore requires this oscillator to be stable before full mode switching occurs. SLOW Mode to NORMAL Mode Switching In SLOW mode the system clock is derived from fSUB. When system clock is switched back to the NORMAL mode from fSUB, the CKS2~CKS0 bits should be set to "000" ~"110" and then the system clock will respectively be switched to fH~ fH/64. However, if fH is not used in SLOW mode and thus switched off, it will take some time to reoscillate and stabilise when switching to the NORMAL mode from the SLOW Mode. This is monitored using the HXTF bit in the HXTC register. The time duration required for the high speed system oscillator stabilization is specified in the A.C. characteristics. Rev. 1.30 51 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the "HALT" instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to "0". In this mode all the clocks and functions will be switched off except the WDT function. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting if the WDT function is enabled. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the FSIDEN bit in the SCC register equal to "1" and the FHIDEN bit in the SCC register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The fH clock will be stopped and the application program will stop at the "HALT" instruction, but the fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting if the WDT function is enabled. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The fH and fSUB clocks will be on but the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting if the WDT function is enabled. Entering the IDLE2 Mode There is only one way for the device to enter the IDLE2 Mode and that is to execute the "HALT" instruction in the application program with the FHIDEN bit in the SCC register equal to "1" and the FSIDEN bit in the SCC register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The fH clock will be on but the fSUB clock will be off and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting if the WDT function is enabled. Rev. 1.30 52 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU NORMAL Mode CKS�~CKS0 = 111 SLOW Mode FHIDEN=0� FSIDEN=0 HALT instr�ction is exec�ted SLEEP Mode FHIDEN=0� FSIDEN=1 HALT instr�ction is exec�ted IDLE0 Mode FHIDEN=1� FSIDEN=1 HALT instr�ction is exec�ted IDLE1 Mode FHIDEN=1� FSIDEN=0 HALT instr�ction is exec�ted IDLE2 Mode SLOW Mode CKS�~CKS0 = 000~110 NORMAL Mode HFIDEN=0� FSIDEN=0 HALT instr�ction is exec�ted SLEEP Mode HFIDEN=0� FSIDEN=1 HALT instr�ction is exec�ted IDLE0 Mode HFIDEN=1� FSIDEN=1 HALT instr�ction is exec�ted IDLE1 Mode HFIDEN=1� FSIDEN=0 HALT instr�ction is exec�ted IDLE2 Mode Rev. 1.30 53 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LIRC oscillator has enabled. In the IDLE1 and IDLE 2 Mode the high speed oscillator is on, if the peripheral function clock source is derived from the high speed oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the CPU will be switched off. However, when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stablise and allow normal operation to resume. After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow When the device executes the "HALT" instruction, the PDF flag will be set to 1. The PDF flag will be cleared to 0 if the device experiences a system power-up or executes the clear Watchdog Timer instruction. If the system is woken up by a WDT overflow, a Watchdog Timer reset will be initiated and the TO flag will be set to 1. The TO flag is set if a WDT time-out occurs and causes a wake-up that only resets the Program Counter and Stack Pointer, other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke up the device will not be immediately serviced, but wukk rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.30 54 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal RC oscillator, fLIRC. The LIRC internal oscillator has an approximate frequency of 32 kHz and this specified internal clock period can vary with VDD, temperature and process variations. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. This register controls the overall operation of the Watchdog Timer. WDTC Register Bit Register Name 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3WE4~WE0: WDT function enable control 10101: Disabled 01010: Enabled Other values: Reset MCU If these bits are changed due to adverse environmental conditions, the microcontroller will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit in the RSTFC register will be set to 1. Bit 2~0WS2~WS0: WDT time-out period selection 000: 28/fLIRC 001: 210/fLIRC 010: 212/fLIRC 011: 214/fLIRC 100: 215/fLIRC 101: 216/fLIRC 110: 217/fLIRC 111: 218/fLIRC These three buts determine the division ratio of the watchdog timer source clock, which in turn determines the time-out period. Rev. 1.30 55 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU RSTFC Register Bit Register Name 7 6 5 4 3 2 1 0 Name — — — — RSTF LVRF LRF WRF R/W — — — — R/W R/W R/W R/W POR — — — — 0 x 0 0 "x": unknown Bit 7~4 Unimplemented, read as "0" Bit 3RSTF: Reset control register software reset flag Described elsewhere. Bit 2LVRF: LVR function reset flag Described elsewhere. Bit 1LRF: LVR control register software reset flag Described elsewhere. Bit 0WRF: WDT control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the WDT control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instruction. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, the clear instruction will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/disable function, there are five bits, WE4~WE0, in the WDTC register to offer the enable/disable control and reset control of the Watchdog Timer. The WDT function will be disabled when the WE4~WE0 bits are set to a value of 10101B while the WDT function will be enabled if the WE4~WE0 bits are equal to 01010B. If the WE4~WE0 bits are set to any other values, other than 01010B and 10101B, it will reset the device after 2~3 fLIRC clock cycles. After power on these bits will have a value of 01010B. WE4 ~ WE0 Bits WDT Function 10101B Disable 01010B Enable Any other value Reset MCU Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 field, the second is using the Watchdog Timer software clear instruction and the third is via a HALT instruction. Rev. 1.30 56 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single "CLR WDT" instruction to clear the WDT contents. The maximum time out period is when the 218 division ratio is selected. As an example, with a 32 kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. WDTC WE�~WE0 bits Register Reset MCU CLR “HALT”Instr�ction “CLR WDT”Instr�ction LIRC fLIRC 8-stage Divider fLIRC/�8 WDT Prescaler WS�~WS0 (fLIRC/�8 ~ fLIRC/�18) 8-to-1 MUX WDT Time-o�t (�8/fLIRC ~ �18/fLIRC ) Watchdog timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, another reset exists in the form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally. Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Note: tRSTD is power-on delay, typical time=50ms Power-On Reset Timing Chart Rev. 1.30 57 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Internal Reset Control There is an internal reset control register, RSTC, which is used to provide a reset when the device operates abnormally due to the environmental noise interference. If the content of the RSTC register is set to any value other than 01010101B or 10101010B, it will reset the device after 2~3 fLIRC clock cycles. After power on the register will have a value of 01010101B. RSTC7 ~ RSTC0 Bits Reset Function 01010101B No operation 10101010B No operation Any other value Reset MCU Internal Reset Function Control • RSTC Register Bit Register Name 7 6 5 4 3 2 1 0 Name RSTC7 RSTC6 RSTC5 RSTC4 RSTC3 RSTC2 RSTC1 RSTC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0RSTC7~RSTC0: Reset function control 01010101: No operation 10101010: No operation Other values: Reset MCU If these bits are changed due to adverse environmental conditions, the microcontroller will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the RSTF bit in the RSTFC register will be set to 1. • RSTFC Register Bit Register Name 7 6 5 4 3 2 1 0 Name — — — — RSTF LVRF LRF WRF R/W — — — — R/W R/W R/W R/W POR — — — — 0 x 0 0 "x": unknown Bit 7~4 Unimplemented, read as "0" Bit 3RSTF: Reset control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the RSTC control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Bit 2LVRF: LVR function reset flag Described elsewhere. Bit 1LRF: LVR control register software reset flag Described elsewhere. Bit 0WRF: WDT control register software reset flag Described elsewhere. Rev. 1.30 58 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is always enabled with a specific LVR voltage, VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the RSTFC register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~ VLVR must exist for a time greater than that specified by tLVR in the LVD/LVR characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected by the LVS bits in the LVRC register. If the LVS7~LVS0 bits have any other value, which may perhaps occur due to adverse environmental conditions such as noise, the LVR will reset the device after 2~3 fLIRC clock cycles. When this happens, the LRF bit in the RSTFC register will be set to 1. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode. Note: tRSTD is power-on delay, typical time=50ms Low Voltage Reset Timing Chart • LVRC Register Bit Register Name 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0LVS7~LVS0: LVR voltage select 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Other values: Generates a MCU reset – register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage value above, an MCU reset will generated. The reset operation will be activated after 2~3 fLIRC clock cycles. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined register values above, will also result in the generation of an MCU reset. The reset operation will be activated after 2~3 fLIRC clock cycles. However in this situation the register contents will be reset to the POR value. Rev. 1.30 59 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU • RSTFC Register Bit Register Name 7 6 5 4 3 2 1 0 Name — — — — RSTF LVRF LRF WRF R/W — — — — R/W R/W R/W R/W POR — — — — 0 x 0 0 "x": unknown Bit 7~4 Unimplemented, read as "0" Bit 3RSTF: Reset control register software reset flag Described elsewhere. Bit 2LVRF: LVR function reset flag 0: Not occurred 1: Occurred This bit is set to 1 when a specific low voltage reset condition occurs. Note that this bit can only be cleared to 0 by the application program. Bit 1LRF: LVR control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the LVRC control register contains any undefined LVR voltage register values. This in effect acts like a software-reset function. Note that this bit can only be cleared to 0 by the application program. Bit 0WRF: WDT control register software reset flag Described elsewhere. Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as the hardware Low Voltage Reset except that the Watchdog time-out flag TO will be set to "1". Note: tRSTD is power-on delay, typical time=16.7ms WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for tSST details. WDT Time-out Reset during SLEEP or IDLE Mode Timing Chart Rev. 1.30 60 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF Reset Function 0 0 Power-on reset u u LVR reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation "u" stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Rev. 1.30 Reset Function Program Counter Reset to zero Interrupts All interrupts will be disabled WDT, Time Base Clear after reset, WDT begins counting Timer Modules Timer Modules will be turned off Input/Output Ports I/O ports will be setup as inputs Stack pointer Stack pointer will point to the top of the stack 61 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects the microcontroller internal registers. Register Reset (Power On) LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* IAR0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP0 0000 0000 0000 0000 0000 0000 uuuu uuuu IAR1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1L 0000 0000 0000 0000 0000 0000 uuuu uuuu MP1H 0000 0000 0000 0000 0000 0000 uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP ---- xxxx - - - - uuuu - - - - uuuu - - - - uuuu STATUS --00 xxxx - - uu uuuu - - uu uuuu - - uu uuuu IAR2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP2L 0000 0000 0000 0000 0000 0000 uuuu uuuu MP2H 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC0 -000 0000 -000 0000 -000 0000 - uuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu RSTFC ---- 0x00 - - - - uuuu - - - - uuuu - - - - uuuu PB - - - - 1111 - - - - 1111 - - - - 1111 - - - - uuuu PBC - - - - 1111 - - - - 1111 - - - - 1111 - - - - uuuu PBPU ---- 0000 ---- 0000 ---- 0000 - - - - uuuu PSCR ---- --00 ---- --00 ---- --00 - - - - - - uu TBC0 0--- -000 0--- -000 0--- -000 u - - - - uuu TBC1 0--- -000 0--- -000 0--- -000 u - - - - uuu SCC 010- -000 010- -000 010- -000 uuu - - uuu HXTC ---- --01 ---- --01 ---- --01 - - - - - - uu LXTC ---- -000 ---- -000 ---- -000 - - - - - uuu RSTC 0101 0101 0101 0101 0101 0101 uuuu uuuu CTRL ---- --00 ---- --00 ---- --00 - - - - - - uu CTMC0 0000 0--- 0000 0--- 0000 0--- uuuu u - - - CTMC1 0000 0000 0000 0000 0000 0000 uuuu uuuu CTMDL 0000 0000 0000 0000 0000 0000 uuuu uuuu CTMDH 0000 0000 0000 0000 0000 0000 uuuu uuuu CTMAL 0000 0000 0000 0000 0000 0000 uuuu uuuu CTMAH 0000 0000 0000 0000 0000 0000 uuuu uuuu CTMRP 0000 0000 0000 0000 0000 0000 uuuu uuuu LVDC --00 -000 --00 -000 --00 -000 - - uu - uuu LVRC 0101 0101 0101 0101 0101 0101 uuuu uuuu STMC0 0000 0--- 0000 0--- 0000 0--- uuuu u - - - STMC1 0000 0000 0000 0000 0000 0000 uuuu uuuu STMDL 0000 0000 0000 0000 0000 0000 uuuu uuuu Rev. 1.30 62 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Register Reset (Power On) LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* STMDH 0000 0000 0000 0000 0000 0000 uuuu uuuu STMAL 0000 0000 0000 0000 0000 0000 uuuu uuuu STMAH 0000 0000 0000 0000 0000 0000 uuuu uuuu STMRP 0000 0000 0000 0000 0000 0000 uuuu uuuu INTEG ---- 0000 ---- 0000 ---- 0000 - - - - uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC3 --00 --00 --00 --00 --00 --00 - - uu - - uu MFI0 --00 --00 --00 --00 --00 --00 - - uu - - uu MFI1 --00 --00 --00 --00 --00 --00 - - uu - - uu MFI2 --00 --00 --00 --00 --00 --00 - - uu - - uu MFI3 0000 0000 0000 0000 0000 0000 uuuu uuuu LCDC -000 ---- -000 ---- -000 ---- - uuu - - - - EEA -000 0000 -000 0000 -000 0000 - uuu uuuu EED 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMC0 0000 0--- 0000 0--- 0000 0--- uuuu u - - - PTMC1 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMDL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMDH 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMAL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMAH 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMRPL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMRPH 0000 0000 0000 0000 0000 0000 uuuu uuuu WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 uuuu uuuu PCPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PD 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu ADRL (ADRFS=0) xxxx ---- xxxx ---- xxxx ---- uuuu - - - - ADRL (ADRFS=1) xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ADRH (ADRFS=0) xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ADRH (ADRFS=1) ---- xxxx - - - - uuuu - - - - uuuu - - - - uuuu ADCR0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 uuuu – uuu ADCR1 -000 -000 -000 -000 -000 -000 - uuu – uuu PAS0 0000 0000 0000 0000 0000 0000 uuuu uuuu PAS1 0000 0000 0000 0000 0000 0000 uuuu uuuu PBS0 0000 0000 0000 0000 0000 0000 uuuu uuuu PCS0 0000 0000 0000 0000 0000 0000 uuuu uuuu PCS1 0000 0000 0000 0000 0000 0000 uuuu uuuu PDS0 0000 0000 0000 0000 0000 0000 uuuu uuuu PDS1 0000 0000 0000 0000 0000 0000 uuuu uuuu IFS --00 00-- --00 00-- --00 00-- - - uu uu - - SIMTOC 0000 0000 0000 0000 0000 0000 uuuu uuuu SIMC0 111 - 0 0 0 0 111 - 0 0 0 0 111 - 0 0 0 0 uuu - uuuu SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu Rev. 1.30 63 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Register Reset (Power On) LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA 0000 0000 0000 0000 0000 0000 uuuu uuuu SPIC0 111 - - - 0 0 111 - - - 0 0 111 - - - 0 0 uuu - - - uu SPIC1 --00 0000 --00 0000 --00 0000 - - uu uuuu SPID xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SPIADMAC 0--- 0000 0--- 0000 0--- 0000 u - - - uuuu SPIA_DMA_LEN - 0 11 1111 - 0 11 1111 - 0 11 1111 - uuu uuuu SPIA_DMA_ADDR 1000 0000 1000 0000 1000 0000 1 uuu uuuu SPIA_DMA_RW_P 1000 0000 1000 0000 1000 0000 uuuu uuuu USVC 0000 0000 0000 0000 0000 0000 uuuu uuuu PGAC 0000 0000 0000 0000 0000 0000 uuuu uuuu RECPLAC 0000 -000 0000 -000 0000 -000 uuuu - 0 0 0 COMPANDC ---- 0000 ---- 0000 ---- 0000 - - - - uuuu RECDL 0000 0000 0000 0000 0000 0000 uuuu uuuu RECDH 0000 0000 0000 0000 0000 0000 uuuu uuuu PLADL 0000 0000 0000 0000 0000 0000 uuuu uuuu PLADH 0000 0000 0000 0000 0000 0000 uuuu uuuu EEC ---- 0000 ---- 0000 ---- 0000 - - - - uuuu FC0 0000 0000 0000 0000 0000 0000 uuuu uuuu FC1 0000 0000 0000 0000 0000 0000 uuuu uuuu FC2 ---- ---0 ---- ---0 ---- ---0 ---- ---u FARL 0000 0000 0000 0000 0000 0000 uuuu uuuu FARH ---- 0000 ---- 0000 ---- 0000 - - - - uuuu FD0L 0000 0000 0000 0000 0000 0000 uuuu uuuu FD0H 0000 0000 0000 0000 0000 0000 uuuu uuuu FD1L 0000 0000 0000 0000 0000 0000 uuuu uuuu FD1H 0000 0000 0000 0000 0000 0000 uuuu uuuu FD2L 0000 0000 0000 0000 0000 0000 uuuu uuuu FD2H 0000 0000 0000 0000 0000 0000 uuuu uuuu FD3L 0000 0000 0000 0000 0000 0000 uuuu uuuu FD3H 0000 0000 0000 0000 0000 0000 uuuu uuuu Note: "u" stands for unchanged "x" stands for "unknown" "-" stands for unimplemented Rev. 1.30 64 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. These devices provide bidirectional input/output lines labeled with port names PA~PD These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Bit Register Name 7 6 5 4 3 2 1 0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PB — — — — PB3 PB2 PB1 PB0 PBC — — — — PBC3 PBC2 PBC1 PBC0 PBPU — — — — PBPU3 PBPU2 PBPU1 PBPU0 PC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PCPU PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PDC PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PDPU PDPU7 PDPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 I/O Registers List "—": Unimplemented, read as "0". PAn/PBn/PCn/PDn: I/O Port Data bit 0: Data 0 1: Data 1 Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PDPU, and are implemented using weak PMOS transistors. PAPU Register 7 6 5 4 3 2 1 0 Name PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.30 Bit Register Name I/O Port A bit 7 ~ bit 0 Pull-high Control 0: Disable 1: Enable 65 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU PBPU Register Bit Register Name 7 6 5 4 3 2 1 0 Name — — — — PBPU3 PBPU2 PBPU1 PBPU0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 "—" Unimplemented, read as 0 Bit 3~0 I/O Port B bit 3 ~ bit 0 Pull-high Control 0: Disable 1: Enable PCPU Register Bit Register Name 7 6 5 4 3 2 1 0 Name PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 I/O Port C bit 7 ~ bit 0 Pull-high Control 0: Disable 1: Enable PDPU Register Bit Register Name 7 6 5 4 3 2 1 0 Name PDPU7 PDPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 I/O Port D bit 7 ~ bit 0 Pull-high Control 0: Disable 1: Enable Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. PAWU Register 7 6 5 4 3 2 1 0 Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.30 Bit Register Name I/O Port A bit 7 ~ bit 0 wake-up function Control 0: Disable 1: Enable 66 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU I/O Port Control Registers Each Port has its own control register, known as PAC~PDC, which controls the input/output configuration. With this control register, each I/O pin with or without pull-high resistors can be reconfigured dynamically under software control. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. PAC Register Bit Register Name 7 6 5 4 3 2 1 0 Name PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0 I/O Port A bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input PBC Register Bit Register Name 7 6 5 4 3 2 1 0 Name — — — — PBC3 PBC2 PBC1 PBC0 R/W — — — — R/W R/W R/W R/W POR — — — — 1 1 1 1 Bit 7~4 Bit 3~0 "—" Unimplemented, read as 0 I/O Port B bit 3 ~ bit 0 Input/Output Control 0: Output 1: Input PCC Register Bit Register Name 7 6 5 4 3 2 1 0 Name PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0 I/O Port C bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input PDC Register 7 6 5 4 3 2 1 0 Name PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0 Rev. 1.30 Bit Register Name I/O Port D bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input 67 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the desired function of the multi-function I/O pins is selected by a series of registers via the application program control. Pin-shared Function Selection Registers The device includes Port "x" output function Selection register "n", labeled as PxSn, and Input Function Selection register, labeled as IFS, which can select the desired functions of the multifunction pins. When the pin-shared input function is selected to be used, the corresponding input and output functions selection should be properly managed. For example, if the I2C SDA line is used, the corresponding output pin-shared function should be configured as the SDI/SDA function by configuring the PxSn register and the SDA signal intput should be properly selected using the IFS register. However, if the external interrupt function is selected to be used, the relevant output pinshared function should be selected as an I/O function and the interrupt input signal should be selected. Bit Register Name 7 6 5 4 3 2 1 0 PAS0 PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 PAS1 PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PAS11 PAS10 PBS0 PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 PCS0 PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 PCS1 PCS17 PCS16 PCS15 PCS14 PCS13 PCS12 PCS11 PCS10 PDS0 PDS07 PDS06 PDS05 PDS04 PDS03 PDS02 PDS01 PDS00 PDS1 PDS17 PDS16 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 IFS — — IFS5 IFS4 IFS3 IFS2 — — Pin-shared Function Selection Registers List • PAS0 Register Bit Register Name 7 6 5 4 3 2 1 0 Name PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PAS07~PAS06: PA3 pin function selection 00/01/10: PA3 11: XT1 Bit 5~4PAS05~PAS04: PA2 pin function selection 00/01/10/11: PA2/STCK Bit 3~2PAS03~PAS02: PA1 pin function selection 00/10: PA1/STPI_0 01: STP_0 11: SCOM0 Bit 1~0PAS01~PAS00: PA0 pin function selection 00/01/10/11: PA0 Rev. 1.30 68 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU • PAS1 Register Bit Register Name 7 6 5 4 3 2 1 0 Name PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PAS11 PAS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PAS17~PAS16: PA7 pin function selection 00/10: PA7 01: CTP_0 11: SCOM3 Bit 5~4PAS15~PAS14: PA6 pin function selection 00/10: PA6 01: CTP_1 11: SCOM2 Bit 3~2PAS13~PAS12: PA5 pin function selection 00/01/10: PA5/CTCK 11: SCOM1 Bit 1~0PAS11~PAS10: PA4 pin function selection 00/01/10: PA4 11: XT2 • PBS0 Register Bit Register Name 7 6 5 4 3 2 1 0 Name PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PBS07~PBS06: PB3 pin function selection 00/01/10/11: PB3/PTCK Bit 5~4PBS05~PBS04: PB2 pin function selection 00/10/11: PB2/PTPI_0 01: PTP_0 Bit 3~2PBS03~PBS02: PB1 pin function selection 00/01/10: PB1 11: VDD_IO Bit 1~0PBS01~PBS00: PB0 pin function selection 00/10/11: PB0/STPI_1 01: STP_1 Rev. 1.30 69 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU • PCS0 Register Bit Register Name 7 6 5 4 3 2 1 0 Name PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PCS07~PCS06: PC3 pin function selection 00/01/10: PC3/INT0 11: AN3 Bit 5~4PCS05~PCS04: PC2 pin function selection 00/01/10: PC2 11: AN2 Bit 3~2PCS03~PCS02: PC1 pin function selection 00/01/10: PC1 11: AN1 Bit 1~0PCS01~PCS00: PC0 pin function selection 00/01/10: PC0 11: AN0/VREF • PCS1 Register Bit Register Name 7 6 5 4 3 2 1 0 Name PCS17 PCS16 PCS15 PCS14 PCS13 PCS12 PCS11 PCS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PCS17~PCS16: PC7 pin function selection 00/10: PC7 01: SDI/SDA 11: AN7 Bit 5~4PCS15~PCS14: PC6 pin function selection 00/10: PC6 01: SCK/SCL 11: AN6 Bit 3~2PCS13~PCS12: PC5 pin function selection 00/10: PC5 01: SDO 11: AN5 Bit 1~0PCS11~PCS10: PC4 pin function selection 00/10: PC4 01: SCS 11: AN4 Rev. 1.30 70 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU • PDS0 Register Bit Register Name 7 6 5 4 3 2 1 0 Name PDS07 PDS06 PDS05 PDS04 PDS03 PDS02 PDS01 PDS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PDS07~PDS06: PD3 pin function selection 00/10/11: PD3 01: SDIA Bit 5~4PDS05~PDS04: PD2 pin function selection 00/01/10/11: PD2/INT1 Bit 3~2PDS03~PDS02: PD1 pin function selection 00/10/11: PD1 01: SCSA Bit 1~0PDS01~PDS00: PD0 pin function selection 00/01/10/11: PD0 • PDS1 Register Bit Register Name 7 6 5 4 3 2 1 0 Name PDS17 PDS16 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PDS17~PDS16: PD7 pin function selection 00/10/11: PD7/PTPI_1 01: PTP_1 Bit 5~4PDS15~PDS14: PD6 pin function selection 00/10/11: PD6 01: CLKO Bit 3~2PDS13~PDS12: PD5 pin function selection 00/10/11: PD5 01: SCKA Bit 1~0PDS11~PDS10: PD4 pin function selection 00/10/11: PD4 01: SDOA • IFS Register Bit Register Name 7 6 5 4 3 2 1 0 Name — — IFS5 IFS4 IFS3 IFS2 — — R/W — — R/W R/W R/W R/W — — POR — — 0 0 0 0 — — Bit 7~6 "—" Unimplemented, read as 0 Bit 5~4IFS5~IFS4: PTPI input source pin selection 00: PTPI_0 01/10/11: PTPI_1 Bit 3~2IFS3~IFS2: STPI input source pin selection 00: STPI_0 01/10/11: STPI_1 Bit 1~0 Rev. 1.30 "—" Unimplemented, read as 0 71 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Generic Input/Output Structure A/D Input/Output Structure Rev. 1.30 72 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Programming Considerations Within the user program, one of the things first to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set to high. This means that all I/O pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Timer Modules – TM One of the most fundamental functions in any microcontroller devices is the ability to control and measure time. To implement time related functions the device includes several Timer Modules, generally abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact, Standard and Periodic TM sections. Introduction The device contains three TMs and each individual TM cab be categorised as a certain type, namely Compact Type TM, Standard Type TM or Periodic Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact, Standard and Periodic TMs will be described in this section and the the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the three types of TMs are summarised in the accompanying table. CTM STM PTM Timer/Counter TM Function √ √ √ Input Capture — √ √ Compare Match Output √ √ √ PWM Channels 1 1 1 Single Pulse Output — 1 1 Edge Edge Edge Duty or Period Duty or Period Duty or Period PWM Alignment PWM Adjustment Period & Duty TM Function Summary Rev. 1.30 73 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU TM Operation The different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running count-up counter whose value is then compared with the value of pre-programmed internal comparators. When the free running count-up counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the xTCK2~xTCK0 bits in the xTM control registers, where "x" can stand for C, S or P. The clock source can be a ratio of the system clock, fSYS, or the internal high clock, fH, the fSUB clock source or the external xTCK pin. The xTCK pin clock source is used to allow an external signal to drive the TM as an external clock source for event counting. TM Interrupts The Compact, Standard or Periodic type TM has two internal interrupt, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one or three TM input pins, with the label xTCK and xTPI_n respectively. The TM input pin, xTCK, is essentially a clock source for the TM and is selected using the xTCK2~xTCK0 bits in the xTMC0 register. This external TM input pin allows an external clock source to drive the internal TM. The TM input pin can be chosen to have either a rising or falling active edge. The STCK and PTCK pins are also used as the external trigger input pin in single pulse output mode for the STM and PTM respectively. The other TM input pin, STPI_n and PTPI_n, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the STIO1~STIO0 or PTIO1~PTIO0 bits in the STMC1 or PTMC1 register respectively. There is another capture input, PTCK, for PTM capture input mode, which can be used as the external trigger input source except the PTPI pin. The TMs each have two output pins known as the name, xTP, with a "_n" suffix. The "_n" suffix indicates that they are from a TM with multiple output pins which is selected using the corresponding pin-shared function selection bits described in the Pin-shared Function section. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external xTP output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pinshared with other functions, the TM output function must first be setup using relevant pin-shared function selection register. CTM STM PTM CTCK CTP_0, CTP_1 STCK, STPI_0, STPI_1 STP_0, STP_1 PTCK, PTPI_0, PTPI_1 PTP_0, PTP_1 TM External Pins Rev. 1.30 74 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU TM Input/Output Pin Control Register Selecting to have a TM input/output or whether to retain its other shared function is implemented using the relevant pin-shared function selection registers, with the corresponding selection bits in each pin-shared function register corresponding to a TM input/output pin. Configuring the selection bits correctly will setup the corresponding pin as a TM input/output. The details of the pin-shared function selection are described in the pin-shared function section. CTCK CTM CCR o�tp�t CTP CTM Function Pin Control Block Diagram STCK STM CCR capt�re inp�t STPI CCR o�tp�t STP STM Function Pin Control Block Diagram PTCK PTM CCR capt�re inp�t PTPI CCR o�tp�t PTP PTM Function Pin Control Block Diagram Rev. 1.30 75 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRB registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the "MOV" instruction to access the CCRA and CCRP low byte registers, named xTMAL and PTMRPL, using the following access procedures. Accessing the CCRA or CCRB low byte registers without following these access procedures will result in unpredictable values. xTM Co�nter Register (Read only) xTMDL xTMDH 8-bit B�ffer xTMAL xTMAH xTM CCRA Register (Read/Write) PTMRPL PTMRPH PTM CCRP Register (Read/Write) Data B�s The following steps show the read and write procedures: • Writing Data to CCRA or CCRP ♦♦ Step 1. Write data to Low Byte xTMAL or PTMRPL ––note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte xTMAH or PTMRPH ––here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA or CCRP Rev. 1.30 ♦♦ Step 1. Read data from the High Byte xTMDH, xTMAH or PTMRPH ––here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte xTMDL, xTMAL or PTMRPL ––this step reads data from the 8-bit buffer. 76 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Compact Type TM – CTM Although the simplest form of the TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive two external output pins. These two external output pins can be the same signal or the inverse signal. Compact Type TM Block Diagram Compact TM Operation The Compact TM core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is eight bits wide whose value is compared with the highest eight bits in the counter while the CCRA is sixteen-bit wide and therefore compares with all counter bits. The only way of changing the value of the 16-bit counter using the application program, is to clear the counter by changing the CTON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.30 77 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Compact Type TM Register Description Overall operation of the Compact TM is controlled using a series of registers. A read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit CCRA value. The CTMRP register is used to store the 8-bit CCRP bits. The remaining two registers are control registers which setup the different operating and control modes. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 CTMC0 CTPAU CTCK2 CTCK1 CTCK0 CTON — — Bit0 — CTMC1 CTM1 CTM0 CTIO1 CTIO0 CTOC CTPOL CTDPX CTCCLR CTMDL D7 D6 D5 D4 D3 D2 D1 D0 CTMDH D15 D14 D13 D12 D11 D10 D9 D8 CTMAL D7 D6 D5 D4 D3 D2 D1 D0 CTMAH D15 D14 D13 D12 D11 D10 D9 D8 CTMRP CTRP7 CTRP6 CTRP5 CTRP4 CTRP3 CTRP2 CTRP1 CTRP0 16-bit Compact TM Registers List CTMDL Register Bit Register Name 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 CTM Counter Low Byte Register bit 7 ~ bit 0 CTM 16-bit Counter bit 7 ~ bit 0 CTMDH Register Bit Register Name 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 CTM Counter High Byte Register bit 7 ~ bit 0 CTM 16-bit Counter bit 15 ~ bit 8 CTMAL Register 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.30 Bit Register Name CTM CCRA Low Byte Register bit 7 ~ bit 0 CTM 16-bit CCRA bit 7 ~ bit 0 78 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU CTMAH Register Bit Register Name 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 CTM CCRA High Byte Register bit 7 ~ bit 0 CTM 16-bit CCRA bit 15 ~ bit 8 CTMC0 Register Bit Register Name 7 6 5 4 3 2 1 0 Name CTPAU CTCK2 CTCK1 CTCK0 CTON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7CTPAU: CTM Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4CTCK2~CTCK0: Select CTM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: CTCK rising edge clock 111: CTCK falling edge clock These three bits are used to select the clock source for the TM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3CTON: CTM Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run while clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the CTOC bit, when the CTON bit changes from low to high. Bit 2~0 Rev. 1.30 Unimplemented, read as "0" 79 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU CTMC1 Register Bit Register Name 7 6 5 4 3 2 1 0 Name CTM1 CTM0 CTIO1 CTIO0 CTOC CTPOL CTDPX CTCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6CTM1~CTM0: Select CTM Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the CTM1 and CTM0 bits. In the Timer/Counter Mode, the TM output pin control will be disabled. Bit 5~4CTIO1~CTIO0: Select CTM external pin CTP_n function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Undefined Timer/Counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the CTIO1 and CTIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the CTOC bit in the CTMC1 register. Note that the output level requested by the CTIO1 and CTIO0 bits must be different from the initial value setup using the CTOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state, it can be reset to its initial level by changing the level of the CTON bit from low to high. In the PWM Mode, the CTIO1 and CTIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the CTIO1 and CTIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the CTIO1 and CTIO0 bits are changed when the TM is running. Rev. 1.30 80 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Bit 3CTOC: CTM CTP_n Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of he TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2CTPOL: CTM CTP_n Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the CTP_n output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1CTDPX: CTM PWM duty/period control 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0CTCCLR: CTM Counter Clear condition selection 0: Comparator P match 1: Comparator A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the CTCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The CTCCLR bit is not used in the PWM Mode. Rev. 1.30 81 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU CTMRP Register Bit Register Name 7 6 5 4 3 2 1 0 Name CTRP7 CTRP6 CTRP5 CTRP4 CTRP3 CTRP2 CTRP1 CTRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 CTRP7~CTRP0: CTM CCRP 8-bit register, compared with the CTM counter bit 15~bit 8 Comparator P match period = 0: 65536 CTM clocks 1~255: (1~255) x 256 CTM clocks These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter’s highest eight bits. The result of this comparison can be selected to clear the internal counter if the CTCCLR bit is set to zero. Setting the CTCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. Compact Type TM Operation Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the CTM1 and CTM0 bits in the CTMC1 register. Compare Match Output Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register, should be set to "00" respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the CTCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both CTMAF and CTMPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the CTCCLR bit in the CTMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the CTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when CTCCLR is high no CTMPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 16-bit, FFFF Hex, value, however here the CTMAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when a CTMAF interrupt request flag is generated after a compare match occurs from Comparator A. The CTMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the CTIO1 and CTIO0 bits in the CTMC1 register. The TM output pin can be selected using the CTIO1 and CTIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the CTON bit changes from low to high, is setup using the CTOC bit. Note that if the CTIO1 and CTIO0 bits are zero then no pin change will take place. Rev. 1.30 82 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU 0xFFFF CTCCLR = 0; CTM[1:0] = 00 Counter overflow Counter Value CCRP > 0 Counter cleared by CCRP value CCRP = 0 Counter Reset Resume CCRP > 0 CCRP Pause CCRA Stop Time CTON CTPAU CTPOL CCRP Int. Flag CTMPF CCRA Int. Flag CTMAF CTM O/P Pin Output Pin set to Initial Level Low if CTOC = 0 Output Toggle with CTMAF flag Now CTIO[1:0] = 10 Active High Output Select Output inverts when CTPOL is high Output Pin Reset to initial value Output not affected by CTMAF flag. Remains High until reset by CTON bit Output controlled by other pin-shared function Here CTIO[1:0] = 11 Toggle Output Select Compare Match Match Output – CTCCLR=0 Compare OutputMode Mode - CTCCLR = 0 Note: 1. With CTCCLR = 0 a Comparator P match will clear the counter 2. The TM output pin controlled only by CTMAF flag 3. The output pin is reset to its initial state by CTON bit rising edge Rev. 1.30 83 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU CTCCLR = 1; CTM[1:0] = 00 Counter Value CCRA > 0 Counter cleared by CCRA value 0xFFFF Resume CCRA CCRA = 0 Counter overflow CCRA = 0 Pause CCRP Stop Counter Reset Time CTON CTPAU CTPOL No CTMAF flag generated on CCRA overflow CCRA Int. Flag CTMAF CCRP Int. Flag CTMPF CTM O/P Pin Output does not change CTMPF not generated Output not affected by Output Pin set to Initial Level Low if CTOC = 0 Output Toggle with CTMAF flag Output inverts when CTPOL is high Output Pin Reset to initial value Output controlled by other pin- shared function CTMAF flag. Remains High Now CTIO[1:0] = 10 Active High Output Select until reset by CTON bit Here CTIO[1:0] = 11 Toggle Output Select Compare Match Output Mode – CTCCLR=1 Compare Match Output Mode - CTCCLR = 1 Note: 1. With CTCCLR = 1, a Comparator A match will clear the counter 2. The TM output pin is controlled only by CTMAF flag 3. The TM output pin is reset to initial state by CTON rising edge 4. The CTMPF flags is not generated when CTCCLR = 1 Rev. 1.30 84 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Timer/Counter Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the CTCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the CTDPX bit in the CTMC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The CTOC bit in the CTMC1 register is used to select the required polarity of the PWM waveform while the two CTIO1 and CTIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The CTPOL bit is used to reverse the polarity of the PWM output waveform. 16-bit CTM, PWM Mode, Edge-aligned Mode, CTDPX=0 CCRP 1~255 Period CCRPx256 Duty 0 65536 CCRA If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 2 and CCRA = 128, The CTM PWM output frequency = (fSYS/4) / (2x256) = fSYS/2048 = 7.8125 kHz, duty = 128/(2x256)= 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. 16-bit CTM, PWM Mode, Edge-aligned Mode, CTDPX=1 CCRP 1~255 0 Period CCRA CCRA Duty CCRPx256 65536 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value except when the CCRP value is equal to 0. Rev. 1.30 85 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Counter Value CTDPX=0; CTM[1:0]=10 Counter Cleared by CCRP Counter reset when CTON returns high CCRP Pause Resume CCRA Counter Stop If CTON bit low Time CTON CTPAU CTPOL CCRA Int. Flag CTMAF CCRP Int. Flag CTMPF CTM O/P Pin (CTOC=1) CTM O/P Pin (CTOC=0) PWM Duty Cycle set by CCRA Output controlled by Other pin-shared function PWM resumes operation Output Inverts When CTPOL = 1 PWM Period set by CCRP PWM Mode – CTDPX = 0 PWM Mode – CTDPX=0 Note: 1. Here CTDPX = 0 - Counter cleared by CCRP 2. A counter clear sets PWM Period 3. The internal PWM function continues even when CTIO1, CTIO0 = 00 or 01 4. The CTCCLR bit has no influence on PWM operation Rev. 1.30 86 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Counter Value CTDPX=1; CTM[1:0]=10 Counter Cleared by CCRA Counter reset when CTON returns high CCRA Pause Resume CCRP Counter Stop If CTON bit low Time CTON CTPAU CTPOL CCRP Int. Flag CTMPF CCRA Int. Flag CTMAF CTM O/P Pin (CTOC=1) CTM O/P Pin (CTOC=0) PWM Duty Cycle set by CCRP Output controlled by Other pin-shared function PWM resumes operation Output Inverts When CTPOL = 1 PWM Period set by CCRA PWM Mode – CTDPX=1 PWM Mode– CTDPX = 1 Note: 1. Here CTDPX = 1 – Counter cleared by CCRA 2. A counter clear sets PWM Period 3. The internal PWM function continues even when CTIO [1:0] = 00 or 01 4. The CTCCLR bit has no influence on PWM operation Rev. 1.30 87 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with two external input pin and can drive two external output pins. Standard Type TM Block Diagram Standard TM Operation The size of Standard TM is 16-bit wide and its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 8-bit wide whose value is compared the with highest 8 bits in the counter while the CCRA is the sixteen bits and therefore compares all counter bits. The only way of changing the value of the 16-bit counter using the application program, is to clear the counter by changing the STON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.30 88 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit CCRA value. The STMRP register is used to store the 8-bit CCRP bits. The remaining two registers are control registers which setup the different operating and control modes. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 STMC0 STPAU STCK2 STCK1 STCK0 STON — — Bit0 — STMC1 STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR STMDL D7 D6 D5 D4 D3 D2 D1 D0 STMDH D15 D14 D13 D12 D11 D10 D9 D8 STMAL D7 D6 D5 D4 D3 D2 D1 D0 STMAH D15 D14 D13 D12 D11 D10 D9 D8 STMRP STRP7 STRP6 STRP5 STRP4 STRP3 STRP2 STRP1 STRP0 16-bit Standard TM Registers List STMDL Register Bit Register Name 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 STM Counter Low Byte Register bit 7 ~ bit 0 STM 16-bit Counter bit 7 ~ bit 0 STMDH Register Bit Register Name 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 STM Counter High Byte Register bit 7 ~ bit 0 STM 16-bit Counter bit 15 ~ bit 8 STMAL Register 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.30 Bit Register Name STM CCRA Low Byte Register bit 7 ~ bit 0 STM 16-bit CCRA bit 7 ~ bit 0 89 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU STMAH Register Bit Register Name 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 STM CCRA High Byte Register bit 7 ~ bit 0 STM 16-bit CCRA bit 15 ~ bit 8 STMC0 Register Bit Register Name 7 6 5 4 3 2 1 0 Name STPAU STCK2 STCK1 STCK0 STON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7STPAU: STM Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4STCK2~STCK0: Select STM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: STCK rising edge clock 111: STCK falling edge clock These three bits are used to select the clock source for the TM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3STON: STM Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run while clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the STOC bit, when the STON bit changes from low to high. Bit 2~0 Rev. 1.30 Unimplemented, read as "0" 90 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU STMC1 Register Bit Register Name 7 6 5 4 3 2 1 0 Name STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6STM1~STM0: Select STM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the STM1 and STM0 bits. In the Timer/Counter Mode, the TM output pin control will be disabled. Bit 5~4STIO1~STIO0: Select STM external pin STP_n or STPI_n function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of STPI_n 01: Input capture at falling edge of STPI_n 10: Input capture at rising/falling edge of STPI_n 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the STIO1 and STIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the STOC bit in the STMC1 register. Note that the output level requested by the STIO1 and STIO0 bits must be different from the initial value setup using the STOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state, it can be reset to its initial level by changing the level of the STON bit from low to high. In the PWM Mode, the STIO1 and STIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the STIO1 and STIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the STIO1 and STIO0 bits are changed when the TM is running. Rev. 1.30 91 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Bit 3STOC: STM STP_n Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of he TM output pin before a compare match occurs. In the PWM Mode/Single Pulse Output Mode it determines if the PWM signal is active high or active low. Bit 2STPOL: STM STP_n Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the STP_n output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1STDPX: STM PWM duty/period control 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0STCCLR: STM Counter Clear condition selection 0: Comparator P match 1: Comparator A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the STCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The STCCLR bit is not used in the PWM Output, Single Pulse Output or Capture Input Mode. Rev. 1.30 92 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU STMRP Register Bit Register Name 7 6 5 4 3 2 1 0 Name STRP7 STRP6 STRP5 STRP4 STRP3 STRP2 STRP1 STRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 STRP7~STRP0: STM CCRP 8-bit register, compared with the STM counter bit 15~bit 8 Comparator P match period = 0: 65536 STM clocks 1~255: (1~255) x 256 STM clocks These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter’s highest eight bits. The result of this comparison can be selected to clear the internal counter if the STCCLR bit is set to zero. Setting the STCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. Standard Type TM Operation Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the STM1 and STM0 bits in the STMC1 register. Compare Match Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the STCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both STMAF and STMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the STCCLR bit in the STMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the STMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when STCCLR is high no STMPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a STMAF interrupt request flag is generated after a compare match occurs from Comparator A. The STMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the STIO1 and STIO0 bits in the STMC1 register. The TM output pin can be selected using the STIO1 and STIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the STON bit changes from low to high, is setup using the STOC bit. Note that if the STIO1 and STIO0 bits are zero then no pin change will take place. Rev. 1.30 93 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU 0xFFFF STCCLR = 0; STM[1:0] = 00 Counter overflow Counter Value CCRP > 0 Counter cleared by CCRP value CCRP = 0 Counter Reset Resume CCRP > 0 CCRP Pause CCRA Stop Time STON STPAU STPOL CCRP Int. Flag STMPF CCRA Int. Flag STMAF STM O/P Pin Output Pin set to Initial Level Low if STOC = 0 Output Toggle with STMAF flag Now STIO [1:0] = 10 Active High Output Select Output inverts when STPOL is high Output Pin Reset to initial value Output not affected by STMAF flag. Remains High until reset by STON bit un-defined Here STIO [1:0] = 11 Toggle Output Select Compare OutputMode Mode - STCCLR = 0 CompareMatch Match Output – STCCLR=0 Note: 1. With STCCLR=0 a Comparator P match will clear the counter 2. The STM output pin is controlled only by the STMAF flag 3. The output pin is reset to itsinitial state by a STON bit rising edge Rev. 1.30 94 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU STCCLR = 1; STM [1:0] = 00 Counter Value CCRA > 0 Counter cleared by CCRA value 0xFFFF Resume CCRA Pause CCRP CCRA = 0 Counter overflow CCRA = 0 Stop Counter Reset Time STON STPAU STPOL No STMAF flag generated on CCRA overflow CCRA Int. Flag STMAF CCRP Int. Flag STMPF STM O/P Pin Output does not change STMPF not generated Output not affected by Output Pin set to Initial Level Low if STOC = 0 Output Toggle with STMAF flag Output inverts when STPOL is high Output Pin Reset to initial value STMAF flag. Remains High Now STIO [1:0] = 10 Active High Output Select until reset by STON bit un-defined Here STIO [1:0] = 11 Toggle Output Select Compare Match Output Mode - –STCCLR =1 Compare Match Output Mode STCCLR=1 Note: 1. With STCCLR=1 a Comparator A match will clear the counter 2. The STM output pin is controlled only by the STMAF flag 3. The output pin is reset to its initial state by a STON bit rising edge 4. A STMPF flag is not generated when STCCLR=1 Rev. 1.30 95 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Timer/Counter Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the STCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the STDPX bit in the STMC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The STOC bit in the STMC1 register is used to select the required polarity of the PWM waveform while the two STIO1 and STIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The STPOL bit is used to reverse the polarity of the PWM output waveform. 16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=0 CCRP 1~255 0 Period CCRPx256 65536 Duty CCRA If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 2 and CCRA = 128, The STM PWM output frequency = (fSYS/4) / (2x256) = fSYS/2048 = 7.8125 kHz, duty = 128/(2x256)= 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. 16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=1 CCRP 1~255 0 Period CCRA CCRA Duty CCRPx256 65536 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value except when the CCRP value is equal to 0. Rev. 1.30 96 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Counter Value STDPX=0; STM [1:0]=10 Counter Cleared by CCRP Counter reset when STON returns high CCRP Counter Stop If STON bit low Pause Resume CCRA Time STON STPAU STPOL CCRA Int. Flag STMAF CCRP Int. Flag STMPF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) PWM Duty Cycle set by CCRA un-defined PWM resumes operation Output Inverts When STPOL = 1 PWM Period set by CCRP PWM Mode – STDPX PWM Mode – STDPX =0 =0 Note: 1. Here STDPX=0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when STIO [1:0] = 00 or 01 4. The STCCLR bit has no influence on PWM operation Rev. 1.30 97 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Counter Value STDPX=1; STM [1:0]=10 Counter Cleared by CCRA Counter reset when STON returns high CCRA Pause Resume CCRP Counter Stop If STON bit low Time STON STPAU STPOL CCRP Int. Flag STMPF CCRA Int. Flag STMAF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) PWM Duty Cycle set by CCRP un-defined PWM resumes operation Output Inverts When STPOL = 1 PWM Period set by CCRA PWM Mode– STDPX = 1 PWM Mode – STDPX = 1 Note: 1. Here STDPX=1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when STIO [1:0] = 00 or 01 4. The STCCLR bit has no influence on PWM operation Rev. 1.30 98 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Single Pulse Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the STON bit, which can be implemented using the application program. However in the Single Pulse Mode, the STON bit can also be made to automatically change from low to high using the external STCK pin, which will in turn initiate the Single Pulse output. When the STON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The STON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the STON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the STON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the STON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The STCCLR and STDPX bits are not used in this Mode. S/W Command SET“STON” or STCK Pin Transition CCRA Leading Edge CCRA Trailing Edge STON bit 0à1 STON bit 1à0 S/W Command CLR“STON” or CCRA Compare Match STP_n Output Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.30 99 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Counter Value STM [1:0] = 10 ; STIO [1:0] = 11 Counter stopped by CCRA Counter Reset when STON returns high CCRA Pause Counter Stops by software Resume CCRP Time STON Software Trigger Auto. set by STCK pin Cleared by CCRA match STCK pin Software Trigger Software Clear Software Trigger Software Trigger STCK pin Trigger STPAU STPOL No CCRP Interrupts generated CCRP Int. Flag STMPF CCRA Int. Flag STMAF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) Output Inverts when STPOL = 1 Pulse Width set by CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse triggered by the STCK pin or by setting the STON bit high 4. A STCK pin active edge will automatically set the STON bit high. 5. In the Single Pulse Mode, STIO [1:0] must be set to "11" and can not be changed. Rev. 1.30 100 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Capture Input Mode To select this mode bits STM1 and STM0 in the STMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the STPI_n pin, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the STIO1 and STIO0 bits in the STMC1 register. The counter is started when the STON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the STPI_n pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the STPI_n pin the counter will continue to free run until the STON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The STIO1 and STIO0 bits can select the active trigger edge on the STPI_n pin to be a rising edge, falling edge or both edge types. If the STIO1 and STIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the STPI_n pin, however it must be noted that the counter will continue to run. The STCCLR and STDPX bits are not used in this Mode. Counter Value STM [1:0] = 01 Counter cleared by CCRP Counter Counter Stop Reset CCRP YY Pause Resume XX Time STON STPAU STM Capture Pin STPI_n Active edge Active edge Active edge CCRA Int. Flag STMAF CCRP Int. Flag STMPF CCRA Value STIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disable Capture Capture Input Mode Note: 1. STM [1:0] = 01 and active edge set by the STIO [1:0] bits 2. A TM Capture input pin active edge transfers the counter value to CCRA 3. STCCLR bit not used 4. No output function -- STOC and STPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.30 101 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can also be controlled with three external input pins and can drive two external output pins. Periodic Type TM Block Diagram Periodic TM Operation The size of Periodic TM is 16-bit wide and its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP or CCRA comparator is 16-bit wide whose value is compared with all counter bits. The only way of changing the value of the 16-bit counter using the application program is to clear the counter by changing the PTON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control the output pins. All operating setup conditions are selected using relevant internal registers. Rev. 1.30 102 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Periodic Type TM Register Description Overall operation of the Periodic TM is controlled using a series of registers. A read only register pair exists to store the internal counter 16-bit value, while two read/write register pairs exist to store the internal 16-bit CCRA and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PTMC0 PTPAU PTCK2 PTCK1 PTCK0 PTON — — — PTMC1 PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR PTMDL D7 D6 D5 D4 D3 D2 D1 D0 PTMDH D15 D14 D13 D12 D11 D10 D9 D8 D0 PTMAL D7 D6 D5 D4 D3 D2 D1 PTMAH D15 D14 D13 D12 D11 D10 D9 D8 PTMRPL PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0 PTMRPH PTRP15 PTRP14 PTRP13 PTRP12 PTRP11 PTRP10 PTRP9 PTRP8 Periodic TM Registers List PTMDL Register Bit Register Name 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 PTM Counter Low Byte Register bit 7 ~ bit 0 PTM 16-bit Counter bit 7 ~ bit 0 PTMDH Register Bit Register Name 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 PTM Counter High Byte Register bit 7 ~ bit 0 PTM 16-bit Counter bit 15 ~ bit 8 PTMAL Register 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.30 Bit Register Name PTM CCRA Low Byte Register bit 7 ~ bit 0 PTM 16-bit CCRA bit 7 ~ bit 0 103 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU PTMAH Register Bit Register Name 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PTM CCRA High Byte Register bit 7 ~ bit 0 PTM 16-bit CCRA bit 15 ~ bit 8 PTMRPL Register Bit Register Name 7 6 5 4 3 2 1 0 Name PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PTRP7~PTRP0: PTM CCRP Low Byte Register bit 7 ~ bit 0 PTM 16-bit CCRP bit 7 ~ bit 0 PTMRPH Register Bit Register Name 7 6 5 4 3 2 1 0 Name PTRP15 PTRP14 PTRP13 PTRP12 PTRP11 PTRP10 PTRP9 PTRP8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PTRP15~PTRP8: PTM CCRP High Byte Register bit 7 ~ bit 0 PTM 16-bit CCRP bit 15 ~ bit 8 PTMC0 Register Bit Register Name 7 6 5 4 3 2 1 0 Name PTPAU PTCK2 PTCK1 PTCK0 PTON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7PTPAU: PTM Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Rev. 1.30 104 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Bit 6~4PTCK2~PTCK0: Select PTM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: PTCK rising edge clock 111: PTCK falling edge clock These three bits are used to select the clock source for the TM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3PTON: PTM Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run while clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the PTOC bit, when the PTON bit changes from low to high. Bit 2~0 Unimplemented, read as "0" PTMC1 Register Bit Register Name 7 6 5 4 3 2 1 0 Name PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PTM1~PTM0: Select PTM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the PTM1 and PTM0 bits. In the Timer/Counter Mode, the TM output pin control will be disabled. Bit 5~4PTIO1~PTIO0: Select PTM external pin PTP_n, PTPI_n or PTCK function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of PTPI_0/PTPI_1 or PTCK 01: Input capture at falling edge of PTPI_0/PTPI_1 or PTCK 10: Input capture at rising/falling edge of PTPI_0/PTPI_1 or PTCK 11: Input capture disabled Rev. 1.30 105 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Timer/Counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the PTIO1 and PTIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the PTOC bit in the PTMC1 register. Note that the output level requested by the PTIO1 and PTIO0 bits must be different from the initial value setup using the PTOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state, it can be reset to its initial level by changing the level of the PTON bit from low to high. In the PWM Mode, the PTIO1 and PTIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the PTIO1 and PTIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the PTIO1 and PTIO0 bits are changed when the TM is running. Bit 3PTOC: PTM PTP_n Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of he TM output pin before a compare match occurs. In the PWM Mode/Single Pulse Output Mode it determines if the PWM signal is active high or active low. Bit 2PTPOL: PTM PTP_n Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the PTP_n output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1PTCAPTS: PTM Capture Triiger Source selection 0: From PTP_n, PTPI_n or PTCK pin 1: From PTCK pin Bit 0PTCCLR: PTM Counter Clear condition selection 0: Comparator P match 1: Comparator A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PTCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PTCCLR bit is not used in the PWM Output, Single Pulse Output or Capture Input Mode. Rev. 1.30 106 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Periodic Type TM Operation Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PTM1 and PTM0 bits in the PTMC1 register. Compare Match Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the PTCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both PTMAF and PTMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the PTCCLR bit in the PTMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the PTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PTCCLR is high no PTMPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when a PTMAF interrupt request flag is generated after a compare match occurs from Comparator A. The PTMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the PTIO1 and PTIO0 bits in the PTMC1 register. The TM output pin can be selected using the PTIO1 and PTIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the PTON bit changes from low to high, is setup using the PTOC bit. Note that if the PTIO1 and PTIO0 bits are zero then no pin change will take place. Rev. 1.30 107 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Counter Value Counter overflow CCRP=0 0xFFFF PTCCLR = 0; PTM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value CCRP > 0 Counter Restart Resume CCRP Pause CCRA Stop Time PTON PTPAU PTPOL CCRP Int. Flag PTMPF CCRA Int. Flag PTMAF PTM O/P Pin Output pin set to initial Level Low if PTOC=0 Output not affected by PTMAF flag. Remains High until reset by PTON bit Output Toggle with PTMAF flag Here PTIO [1:0] = 11 Toggle Output select Note PTIO [1:0] = 10 Active High Output select Output Inverts when PTPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – PTCCLR = 0 Note: 1. With PTCCLR=0, a Comparator P match will clear the counter 2. The TM output pin is controlled only by the PTMAF flag 3. The output pin is reset to its initial state by a PTON bit rising edge Rev. 1.30 108 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Counter Value PTCCLR = 1; PTM [1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared by CCRA value 0xFFFF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time PTON PTPAU PTPOL No PTMAF flag generated on CCRA overflow CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF PTM O/P Pin PTMPF not generated Output pin set to initial Level Low if PTOC=0 Output does not change Output not affected by PTMAF flag. Remains High until reset by PTON bit Output Toggle with PTMAF flag Here PTIO [1:0] = 11 Toggle Output select Note PTIO [1:0] = 10 Active High Output select Output Inverts when PTPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – PTCCLR = 1 Note: 1. With PTCCLR=1, a Comparator A match will clear the counter 2. The TM output pin is controlled only by the PTMAF flag 3. The output pin is reset to its initial state by a PTON bit rising edge 4. A PTMPF flag is not generated when PTCCLR =1 Rev. 1.30 109 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Timer/Counter Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTIO1 and PTIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control, etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the PTCCLR bit has no effect as the PWM period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The PTOC bit in the PTMC1 register is used to select the required polarity of the PWM waveform while the two PTIO1 and PTIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The PTPOL bit is used to reverse the polarity of the PWM output waveform. 16-bit PTM, PWM Mode, Period Duty CCRP = 0 CCRP = 1~65535 65536 1~65535 CCRA If fSYS=16MHz, TM clock source select fSYS/4, CCRP=512 and CCRA=128, The PTM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 7.8125kHz, duty=128/512=25%, If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. Rev. 1.30 110 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Counter Value PTM [1:0] = 10 Counter cleared by CCRP Counter Reset when PTON returns high CCRP Pause Resume CCRA Counter Stop if PTON bit low Time PTON PTPAU PTPOL CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF PTM O/P Pin (PTOC=1) PTM O/P Pin (PTOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function When PTPOL = 1 PWM Mode Note: 1. The counter is cleared by CCRP. 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when PTIO [1:0] = 00 or 01 4. The PTCCLR bit has no influence on PWM operation Rev. 1.30 111 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Single Pulse Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTIO1 and PTIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the PTON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PTON bit can also be made to automatically change from low to high using the external PTCK pin, which will in turn initiate the Single Pulse output. When the PTON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PTON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the PTON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The PTCCLR is not used in this Mode. S/W Command SET“PTON” or PTCK Pin Transition CCRA Leading Edge CCRA Trailing Edge PTON bit 0 1 PTON bit 1 0 S/W Command CLR“PTON” or CCRA Compare Match PTP_n O�tp�t Pin P�lse Width = CCRA Val�e Single Pulse Generation Rev. 1.30 112 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Counter Value PTM [1:0] = 10 ; PTIO [1:0] = 11 Counter stopped by CCRA Counter Reset when PTON returns high CCRA Pause Counter Stops by software Resume CCRP Time PTON Software Trigger Auto. set by PTCK pin Cleared by CCRA match PTCK pin Software Trigger Software Clear Software Trigger Software Trigger PTCK pin Trigger PTPAU PTPOL No CCRP Interrupts generated CCRP Int. Flag PTMPF CCRA Int. Flag PTMAF PTM O/P Pin (PTOC=1) PTM O/P Pin (PTOC=0) Output Inverts when PTPOL = 1 Pulse Width set by CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse triggered by the PTCK pin or by setting the PTON bit high 4. A PTCK pin active edge will automatically set the PTON bit high. 5. In the Single Pulse Mode, PTIO [1:0] must be set to "11" and can not be changed. Rev. 1.30 113 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Capture Input Mode To select this mode bits PTM1 and PTM0 in the PTMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTPI_0/PTPI_1 or PTCK pin, selected by the PTCAPTS bit in the PTMC1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTIO1 and PTIO0 bits in the PTMC1 register. The counter is started when the PTON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPI_0/PTPI_1 or PTCK pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the PTPI_0/PTPI_1 or PTCK pin the counter will continue to free run until the PTON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTIO1 and PTIO0 bits can select the active trigger edge on the PTPI_0/PTPI_1 or PTCK pin to be a rising edge, falling edge or both edge types. If the PTIO1 and PTIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPI_0/ PTPI_1 or PTCK pin, however it must be noted that the counter will continue to run. As the PTPI_0/PTPI_1 or PTCK pin is pin shared with other functions, care must be taken if the TM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTCCLR, PTOC and PTPOL bits are not used in this Mode. Rev. 1.30 114 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Counter Value PTM [1:0] = 01 Counter cleared by CCRP Counter Counter Stop Reset CCRP YY Pause Resume XX Time PTON PTPAU Active edge Active edge Active edge PTM capture pin PTPI_n or PTCK CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF CCRA Value PTIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disable Capture Capture Input Mode Note: 1. PTM [1:0] = 01 and active edge set by the PTIO [1:0] bits 2. A TM Capture input pin active edge transfers the counter value to CCRA 3. PTCCLR bit not used 4. No output function – PTOC and PTPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.30 115 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. The accompanying block diagram shows the internal structure of the A/D converter together with its associated registers. PC0/VREF Pin-shared selection AN0 AN1 : AN7 VBG ACS4, ACS2~ACS0 VBGEN A/D Converter Structure A/D Converter Register Description Overall operation of the A/D converter is controlled using four registers. A read only register pair exists to store the A/D Converter data 12-bit value. The remaining two registers are control registers which setup the operating and control function of the A/D converter. Register Name Bit 7 6 5 4 3 2 1 0 ADRL (ADRFS=0) D3 D2 D1 D0 — — — — ADRL (ADRFS=1) D7 D6 D5 D4 D3 D2 D1 D0 ADRH (ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D4 ADRH (ADRFS=1) — — — — D11 D10 D9 D8 ADCR0 START EOCB ADOFF ACS4 — ACS2 ACS1 ACS0 ADCR1 — VBGEN ADRFS VREFS — ADCK2 ADCK1 ADCK0 A/D Converter Registers List Rev. 1.30 116 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU A/D Converter Data Registers – ADRL, ADRH As the device contains an internal 12-bit A/D converter, it requires two data registers to store the converted value. These are a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR1 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. ADRFS 0 1 ADRH 7 6 5 D11 D10 D9 0 0 ADRL 4 3 2 1 0 7 6 5 4 3 2 1 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 A/D Converter Data Registers A/D Converter Control Registers – ADCR0, ADCR1 To control the function and operation of the A/D converter, three or four control registers known as ADCR0 and ADCR1 are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitised data format, the A/ D clock source as well as controlling the start function and monitoring the A/D converter end of conversion status. The ACS2~ACS0 and ACS4 bits in the ADCR0 register define the A/D Converter input channel number. As the device contains only one actual analog to digital converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter. It is the function of the ACS4 and ACS2~ACS0 bits to determine which analog channel input pins or internal Bandgap reference voltage is actually connected to the internal A/D converter. The relevant pin-shared function selection bits determine which pins on I/O Ports are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pinshared function will be removed. In addition, any internal pull-high resistor connected to the pin will be automatically removed if the pin is selected to be an A/D converter input. • ADCR0 Register Bit Register Name 7 6 5 4 3 2 1 0 Name START EOCB ADOFF ACS4 — ACS2 ACS1 ACS0 R/W R/W R R/W R/W — R/W R/W R/W POR 0 1 1 0 — 0 0 0 Bit 7START: Start the A/D Conversion 0→1→0: Start 0→1: Reset the A/D converter and set EOCB to "1" This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high, the A/D converter will be reset. Bit 6EOCB: End of A/D Conversion flag 0: A/D conversion ended 1: A/D conversion in progressReset the A/D converter and set EOCB to "1" This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process is running, the bit will be high. Rev. 1.30 117 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Bit 5ADOFF: A/D Converter power On/Off control 0: A/D converter powered on 1: A/D converter powered off This bit controls the power to the A/D internal function. This bit should be cleared to zero to enable the A/D comverter. If the bit is set high, then the A/D converter will be switched off reducing the device power consumption. As the A/D converter will consume a limited amount of power, even when not executing a voncersion, this may be an important consideration in power sensitive battery powered applications. Note: 1. It is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for savong power. 2. ADOFF=1 will power down the A/D Converter. Bit 4ACS4: Select Internal Bandgap reference voltage as A/D converter input control 0: Disable 1: Enable This bit enables the internal Bandgap reference voltage to be connected to the A/D converter. The VBGEN bit must first have been set to enable the Bandgap reference voltage to be used by the A/D converter. When the ACS4 bit is set high, the Bandgap reference voltage will be routed to the A/D converter and other A/D input channels will be disconnected. Bit 3 Unimplemented, read as "0" Bit 2~0ACS2~ACS0: Select A/D input channel (when ACS4 is "0") 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 These bits are the A/D input channel selection bits. As there is only one internal hardware A/D converter, each of the eight A/D inputs must be routed to the internal converter using these bits. If bit ACS4 is set high, then the internal Bandgap reference voltage will be routed to the A/D converter. • ADCR1 Register Bit Register Name 7 6 5 4 3 2 1 0 Name — VBGEN ADRFS VREFS — ADCK2 ADCK1 ADCK0 R/W — R R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6VBGEN: Internal Bandgap reference voltage enable control 0: Disable 1: Enable This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit is set high, the bandgap reference voltage can be used by the A/ D converter. If the Bandgap reference voltage is not used by the A/D converter and the LVD/LVR function is disabled, then the bandgap reference circuit will be automatically switched off to conserve power. When the Bandgap reference voltage is switched on for use by the A/D converter, a time, tBG, should be allowed for the Bandgap circuit to stabilise before implementing an A/D conversion. Bit 5ADRFS: A/D Converter data format control 0: A/D converter data MSB is in ADRH bit 7, LSB is in ADRL bit 4. 1: A/D converter data MSB is in ADRH bit 3, LSB is in ADRL bit 0. This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D data register section. Rev. 1.30 118 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Bit 4VREFS: A/D converter reference voltage selection control 0: Internal A/D converter power 1: VREF pin This bit is used to select the reference voltage for the A/D converter. If the bit is high, then the A/D converter reference voltage is supplied on the external VREF pin. If the bit is low, then the internal A/D converter reference voltage is used which is taken from the A/D converter power supply pin. Bit 3 Unimplemented, read as "0" Bit 2~0ADCK2~ADCK0: A/D clock source selection 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: Undefined These bits are used to select the clock source for the A/D converter. A/D Operation The START bit in the ADCR0 register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset. It is the START bit that is used to control the overall start operation of the internal analog to digital converter. The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the ADCK2~ADCK0 bits in the ADCR1 register. Although the A/D clock source is determined by the system clock fSYS, and by bits ADCK2~ADCK0, there are some limitations on the maximum A/D clock source speed that can be selected. As the recommended range of permissible A/D clock period, tADCK, is from 0.5μs to 10μ, care must be taken for system clock frequencies. For example, as the system clock operates at a frequency of 16MHz, the ADCK2~ADCK0 bits should not be set to 000, 001 or 010. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. Rev. 1.30 119 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU A/D Clock Period (tADCK) fSYS 16 MHz ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] = 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 (fSYS) (fSYS/2) (fSYS/4) (fSYS/8) (fSYS/16) (fSYS/62) (fSYS/64) 62.5ns * 125ns * 250ns * 500ns 1μs 2μs 4μs Undefined A/D Clock Period Examples Controlling the power on/off function of the A/D converter circuitry is implemented using the ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When the ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs, if the ADOFF bit is zero then some power will still be consumed. In power conscious applications it is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D converter function is not being used. The reference voltage supply to the A/D Converter can be supplied from either the positive power supply pin, VDD, or from an external reference sources supplied on pin VREF. The desired selection is made using the VREFS and relecant pin-shared function selection bits. As the VREF pin is pinshared with other functions, when the VREFS bit is set high and the relevant pin-shared function selection bits are selected as the VREF function, the VREF pin function will be selected and therefore other pin functions will be disabled. A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port C as well as other functions. The corresponding selection bits in the PCS0 and PCS1 registers, determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the corresponding pin is setup to be an A/D converter input, the original pin functions will be disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the port control register to enable the A/D input as when the relevant A/D input function selection bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own reference voltage pin, VREF, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the VREFS bit in the ADCR1 register. The analog input values must not be allowed to exceed the value of VREF. PC0/AN0 PC7/AN7 VBG PC0/VREF A/D Input Structure Rev. 1.30 120 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/ D conversion process. • Step 1 Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the ADCR1 register. • Step 2 Enable the A/D by clearing the ADOFF bit in the ADCR0 register to zero. • Step 3 Select which channel is to be connected to the internal A/D converter by correctly programming the ACS4 and ACS2~ACS0 bits which are also contained in the ADCR0 register. • Step 4 Select which pins are to be used as A/D inputs and configure them by correctly programming the corresponding pin-shared function selection registers. • Step 5 If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and the A/D converter interrupt bit, ADE, must both be set high to do this. • Step 6 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR0 register from low to high and then low again. Note that this bit should have been originally cleared to zero. • Step 7 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0 register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data register ADRL and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR0 register is used, the interrupt enable step above can be omitted. The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16 tADCK where tADCK is equal to the A/D clock period. Rev. 1.30 121 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU A/D Conversion Timing Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the ADCR0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Transfer Function As the devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the VDD or VREF voltage, this gives a single bit analog input value of VDD or VREF divided by 4096. 1 LSB = (VDD or VREF) ÷ 4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage = A/D output digital value × (VDD or VREF) ÷ 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VDD or VREF level. Ideal A/D Transfer Function Rev. 1.30 122 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU A/D Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an EOCB polling method to detect the end of conversion clr ADE; disable ADC interrupt mov a,03H mov ADCR1,a ; select fSYS/8 as A/D clock and switch off VBG voltage clr ADOFF mov a,03H ; setup PCS0 to configure pin AN0 mov PCS0,a mov a,00H mov ADCR0,a ; enable and connect AN0 channel to A/D converter : start_conversion: clr START ; high pulse on start bit to initiate conversion set START ; reset A/D clr START ; start A/D : polling_EOC: sz EOCB ; poll the ADCR0 register EOCB bit to detect end of A/D conversion jmp polling_EOC ; continue polling : mov a,ADRL ; read low byte conversion result value mov ADRL_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov ADRH_buffer,a ; save result to user defined register : jmp start_conversion ; start next A/D conversion Rev. 1.30 123 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Example: using the interrupt method to detect the end of conversion clr ADE; disable ADC interrupt mov a,03H mov ADCR1,a ; select fSYS/8 as A/D clock and switch off VBG voltage clr ADOFF mov a,03h ; setup PCS0 to configure pin AN0 mov PCS0,a mov a,00h mov ADCR0,a ; enable and connect AN0 channel to A/D converter : Start_conversion: clr START ; high pulse on START bit to initiate conversion set START ; reset A/D clr START ; start A/D clr ADF ; clear ADC interrupt request flag set ADE; enable ADC interrupt set EMI ; enable global interrupt : : ADC_ISR: ; ADC interrupt service routine mov acc_stack,a ; save ACC to user defined memory mov a,STATUS mov status_stack,a ; save STATUS to user defined memory : mov a, ADRL ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a, ADRH ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1.30 124 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Serial Interface Module – SIM These devices contain a Serial Interface Module, which includes both the four-line SPI interface or two-line I 2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and therefore the SIM interface functional pins must first be selected using the corresponding pin-shared function selection bits. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/ O pins are selected using pull-high control registers when the SIM function is enabled and the corresponding pins are used as SIM input pins. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the devices can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, these devices provided only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface pins must first be selected by configuring the pin-shared function selection bits and setting the correct bits in the SIMC0 and SIMC2 registers. After the desired SPI configuration has been set it can be disabled or enabled using the SIMEN bit in the SIMC0 register. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to 1 to enable SCS pin function, set CSEN bit to 0 the SCS pin will be placed into I/O pin or other pin-shared functions. The SPI function in this device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. Rev. 1.30 125 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU SPI Master/Slave Connection SPI Block Diagram SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only used by the I2C interface. Bit Register Name 7 6 5 SIMC0 SIM2 SIM1 SIM0 — SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMC2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF 4 3 2 SIMDEB1 SIMDEB0 1 0 SIMEN SIMICF SPI Registers List • SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Rev. 1.30 126 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag, etc. SIMC0 Register Bit 7 6 5 4 Name SIM2 SIM1 SIM0 — 3 R/W R/W R/W R/W — R/W POR 1 1 1 — 0 2 1 0 SIMEN SIMICF R/W R/W R/W 0 0 0 SIMDEB1 SIMDEB0 Bit 7~5SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS /4 001: SPI master mode; SPI clock is fSYS /16 010: SPI master mode; SPI clock is fSYS /64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is CTM CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from CTM. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 Unimplemented, read as "0" Bit 3~2SIMDEB1~SIMDEB0: I2C Debounce Time Selection 00: No debounce 01: 2 system clock debounce 1x: 4 system clock debounce Bit 1SIMEN: SIM Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0SIMICF: SIM Incomplete Flag 0: SIM incomplete condition not occurred 1: SIM incomplete condition occured This bit is only available when the SIM is configured to operate in an SPI slave mode. If the SPI operates in the slave mode with the SIMEN and CSEN bits both being set to 1 but the SCS line is pulled high by the external master device before the SPI data transfer is completely finished, the SIMICF bit will be set to 1 together with the TRF bit. When this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. However, the TRF bit will not be set to 1 if the SIMICF bit is set to 1 by software application program. Rev. 1.30 127 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU SIMC2 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Undefined bits These bits can be read or written by the application program. Bit 5CKPOLB: SPI clock line base condition selection 0: The SCK line will be high when the clock is inactive. 1: The SCK line will be low when the clock is inactive. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4CKEG: SPI SCK clock active edge type selection CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Bit 3MLS: SPI data shift order 0: LSB first 1: MSB first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2CSEN: SPI SCS pin control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and placed into I/O pin or other pin-shared functions. If the bit is high, the SCS pin will be enabled and used as a select pin. Bit 1WCOL: SPI write collision flag 0: No collision 1: Collision The WCOL flag is used to detect whether a data collision has occurred or not. If this bit is high, it means that data has been attempted to be written to the SIMD register duting a data transfer operation. This writing operation will be ignored if data is being transferred. This bit can be cleared by the application program. Bit 0TRF: SPI Transmit/Receive complete flag 0: SPI data is being transferred 1: SPI data transfer is completed The TRF bit is the Transmit/Receive Complete flag and is set to 1 automatically when an SPI data transfer is completed, but must cleared to 0 by the application program. It can be used to generate an interrupt. Rev. 1.30 128 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output a SCS signal to enable the slave devices before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. SPI Master Mode Timing SPI Slave Mode Timing – CKEG=0 Rev. 1.30 129 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU SPI Slave Mode Timing – CKEG=1 SPI Transfer Control Flowchart Rev. 1.30 130 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. I2C Master/Slave Bus Connection I2C Interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For these devices, which only operate in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r Rev. 1.30 131 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU I2C Block Diagram The SIMDEB1 and SIMDEB0 bits determine the debounce time of the I2C interface. This uses the system clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 2 or 4 system clocks. To achieve the required I2C data transfer speed, there exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C Standard or Fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table. I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz) No Devounce fSYS > 2 MHz fSYS > 5 MHz 2 system clock debounce fSYS > 4 MHz fSYS > 10 MHz fSYS > 8 MHz fSYS > 20 MHz 4 system clock debounce I2C Minimum fSYS Frequency I2C Registers There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMA, and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. Bit Register Name 7 SIMC0 SIMC1 6 5 4 SIM2 SIM1 SIM0 — HCF HAAS HBB HTX 3 2 SIMDEB1 SIMDEB0 TXAK SRW 1 0 SIMEN SIMICF IAMWU RXAK SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMA IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 I C Registers List 2 Rev. 1.30 132 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the device can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown SIMA Register The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 7 6 5 4 3 2 1 0 Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~1IICA6~IICA0: I2C slave address IICA6~IICA0 is the I2C slave address bit 6 ~ bit 0 Bit 0 Undefined bit The bit can be read or written by the application program. There are also two control registers for the I2C interface, SIMC0 and SIMC1. The register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency.The SIMC1 register contains the relevant flags which are used to indicate the I2C communication status. SIMC0 Register Bit 7 6 5 4 Name SIM2 SIM1 SIM0 — 3 R/W R/W R/W R/W — R/W POR 1 1 1 — 0 2 1 0 SIMEN SIMICF R/W R/W R/W 0 0 0 SIMDEB1 SIMDEB0 Bit 7~5SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS /4 001: SPI master mode; SPI clock is fSYS /16 010: SPI master mode; SPI clock is fSYS /64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is CTM CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from CTM. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Rev. 1.30 133 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Bit 4 Unimplemented, read as "0" Bit 3~2SIMDEB1~SIMDEB0: I2C Debounce Time Selection 00: No debounce 01: 2 system clock debounce 1x: 4 system clock debounce Bit 1SIMEN: SIM Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0SIMICF: SIM Incomplete Flag 0: SIM incomplete condition not occurred 1: SIM incomplete condition occured This bit is only available when the SIM is configured to operate in an SPI slave mode. If the SPI operates in the slave mode with the SIMEN and CSEN bits both being set to 1 but the SCS line is pulled high by the external master device before the SPI data transfer is completely finished, the SIMICF bit will be set to 1 together with the TRF bit. When this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. However, the TRF bit will not be set to 1 if the SIMICF bit is set to 1 by software application program. SIMC1 Register Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R/W R/W R POR 1 0 0 0 0 0 0 1 Bit 7HCF: I C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6HAAS: I2C Bus data transfer completion flag 0: Not address match 1: Address match The HAAS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. 2 Rev. 1.30 134 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Bit 5HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to "0" when the bus is free which will occur when a STOP signal is detected. Bit 4HTX: I2C slave device transmitter/receiver selection 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3TXAK: I2C bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave does not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to "0" before further data is received. Bit 2SRW: I2C slave read/write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1IAMWU: I2C Address Match Wake-Up control 0: Disable 1: Enable – must be cleared by the application program after wake-up This bit should be set to 1 to enable the I2C address match wake up from the SLEEP or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable the I2C address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. Bit 0RXAK: I2C bus receive acknowledge flag 0: Slave receives acknowledge flag 1: Slave does not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is "1". When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. Rev. 1.30 135 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS and SIMTOF bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer or I2C time-out. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: • Step 1 Set the SIM2~SIM0 bits to "110" and SIMEN bit to "1" in the SIMC0 register to enable the I2C bus. • Step 2 Write the slave address of the device to the I2C bus address register SIMA. • Step 3 Set the SIME and SIM Muti-Function interrupt enable bit of the interrupt control register to enable the SIM interrupt and Multi-function interrupt. I2C Bus Initialisation Flow Chart Rev. 1.30 136 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. I2C Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I 2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit and SIMTOF bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer or I2C timeout. When a slave address is matched, the devices must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I 2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to "1". If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to "0". Rev. 1.30 137 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. I2C Communication Timing Diagram Note: *When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. Rev. 1.30 138 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU I2C Bus ISR Flow Chart I2C Time-out Control In order to reduce the I2C lockup problem due to reception of erroneous clock sources, a time-out function is provided. If the clock source connected to the I2C bus is not received for a while, then the I2C circuitry and registers will be reset after a certain time-out period. The time-out counter starts to count on an I2C bus "START" & "address match"condition, and is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out period specified by the SIMTOC register, then a time-out condition will occur. The time-out function will stop when an I2C "STOP" condition occurs. S C L S ta rt S R W S la v e A d d r e s s 0 1 S D A 1 1 0 1 0 1 A C K 0 I2 C t i m e - o u t c o u n te r s ta rt S to p S C L 1 0 0 1 0 1 0 0 S D A I2 C t im e - o u t c o u n t e r r e s e t o n S C L n e g a tiv e tr a n s itio n I2C Time-out Diagram Rev. 1.30 139 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU When an I2C time-out counter overflow occurs, the counter will stop and the I2CTOEN bit will be cleared to zero and the I2CTF bit will be set high to indicate that a time-out condition has occurred. The time-out condition will also generate an interrupt which uses the I2C interrrupt vector. When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the following condition: Register After I2C Time-out SIMD, SIMA, SIMC0 No change SIMC1 Reset to POR condition I2C Register after Time-out The I2CTOF flag can be cleared by the application program. There are 64 time-out period selections which can be selected using the I2CTOS bits in the SIMTOC register. The time-out duration is calculated by the formula: ((1~64) × (32/fSUB)). This gives a time-out period which ranges from about 1ms to 64ms. SIMTOC Register Bit 7 6 5 4 3 2 1 0 Name SIMTOEN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 Bit 7 SIMTOEN: I C Time-out control Bit 6 SIMTOF: I2C Time-out flag Bit 5~0 SIMTOS5~SIMTOS0: I2C Time-out period selection 2 0: Disable 1: Enable 0: No time-out occurred 1: Time-out occurred I2C Time-out clock source is fSUB/32 I2C Time-out period is equal to (I2CTOS[5 : 0] + 1) × Rev. 1.30 140 32 f SUB June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Serial Interface – SPIA The device contains an independent SPI function. It is important not to confuse this independent SPI function with the additional one contained within the combined SIM function, which is described in another section of this datasheet. This independent SPI function will carry the name SPIA to distinguish it from the other one in the SIM. This SPIA interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPIA interface specification can control multiple slave devices from a single master, this device is provided only one SCSA pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pins to select the slave devices. SPIA Interface Operation The SPIA interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDIA, SDOA, SCKA and SCSA Pins SDIA and SDOA are the Serial Data Input and Serial Data Output lines, SCKA is the Serial Clock line and SCSA is the Slave Select line. As the SPIA interface pins are pin-shared with other functions, the SPIA interface pins must first be selected by configuring the corresponding selection bits in the pin-shared function selection registers. The SPIA interface function is disabled or enabled using the SPIAEN bit in the SPIAC0 register. Communication between devices connected to the SPIA interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The master also controls the clock/signal. As the device only contains a single SCSA pin only one slave device can be utilised. The SCSA pin is controlled by the application program, set the the SACSEN bit to "1" to enable the SCSA pin function and clear the SACSEN bit to "0" to place the SCSA pin into an I/O function. SPIA Master/Slave Connection The SPIA Serial Interface function includes the following features: • Full-duplex synchronous data transfer • Both Master and Slave mode • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge The status of the SPIA interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as SACSEN and SPIAEN. Rev. 1.30 141 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU SPIA Block Diagram SPIA Registers There are three internal registers which control the overall operation of the SPIA interface. These are the SIMD data register and two registers SPIAC0 and SPIAC1. Bit Register Name 7 6 SPIAC0 SASPI2 SASPI1 SPIAC1 — — SPIAD D7 D6 5 4 SASPI0 — SACKPOLB SACKEG D5 3 — SAMLS D4 D3 2 1 0 — SPIAEN SPIAICF SACSEN SAWCOL D2 D1 SATRF D0 SPIA Registers List SPIAD Register The SPIAD register is used to store the data being transmitted and received. Before the device writes data to the SPIA bus, the actual data to be transmitted must be placed in the SPIAD register. After the data is received from the SPIA bus, the device can read it from the SPIAD register. Any transmission or reception of data from the SPIA bus must be made via the SPIA register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown There are also two control registers for the SPIA interface, SPIAC0 and SPIAC1. Register SPIAC0 is used to control the enable/disable function and to set the data transmission clock frequency. Register SPIAC1 is used for other control functions such as LSB/MSB selection, write collision flag, etc. Rev. 1.30 142 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU SPIAC0 Register Bit 7 6 5 4 3 2 1 0 Name SASPI2 SASPI1 SASPI0 — — — SPIAEN SPIAICF R/W R/W R/W R/W — — — R/W R/W POR 1 1 1 — — — 0 0 Bit 7~5SASPI2~SASPI0: SPIA Master/Slave clock select 000: SPIA master mode with clock fSYS /4 001: SPIA master mode with clock fSYS /16 010: SPIA master mode with clock fSYS /64 011: SPIA master mode with clock fSUB 100: SPIA master mode with clock CTM CCRP match frequency/2 101: SPIA slave mode 11x: Reserved Bit 4~2 Unimplemented, read as "0" Bit 1SPIAEN: SPIIA Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SPIA interface. When the SPIAEN bit is cleared to zero to disable the SPIA interface, the SDIA, SDOA, SCKA and SCSA lines will lose the SPI function and the SPIA operating current will be reduced to a minimum value. When the bit is high the SPIA interface is enabled. Bit 0SPIAICF: SPIA Incomplete Flag 0: SPIA incomplete condition not occurred 1: SPIA incomplete condition occured This bit is only available when the SPIA is configured to operate in an SPIA slave mode. If the SPIA operates in the slave mode with the SPIAEN and SACSEN bits both being set to 1 but the SCSA line is pulled high by the external master device before the SPIA data transfer is completely finished, the SPIAICF bit will be set to 1 together with the SATRF bit. When this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. However, the SATRF bit will not be set to 1 if the SPIAICF bit is set to 1 by software application program. SPIAC1 Register Bit 7 6 5 4 3 Name — — SACKPOLB SACKEG SAMLS 2 1 0 SACSEN SAWCOL SATRF R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5SACKPOLB: SPIA clock line base condition selection 0: The SCKA line will be high when the clock is inactive. 1: The SCKA line will be low when the clock is inactive. The SACKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOLB bit is low, then the SCKA line will be high when the clock is inactive. Bit 4SACKEG: SPIA SCKA clock active edge type selection SACKPOLB=0 0: SCKA is high base level and data capture at SCKA rising edge 1: SCKA is high base level and data capture at SCKA falling edge SACKPOLB=1 0: SCKA is low base level and data capture at SCKA falling edge 1: SCKA is low base level and data capture at SCKA rising edge Rev. 1.30 143 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU The SACKEG and SACKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPIA bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The SACKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCKA line will be low when the clock is inactive. When the SACKPOLB bit is low, then the SCKA line will be high when the clock is inactive. The SACKEG bit determines active clock edge type which depends upon the condition of SACKPOLB bit. Bit 3SAMLS: SPIA data shift order 0: LSB first 1: MSB first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2SACSEN: SPIA SCSA pin control 0: Disable 1: Enable The SACSEN bit is used as an enable/disable for the SCSA pin. If this bit is low, then the SCSA pin function will be disabled and can be placed into I/O pin or other pinshared functions. If the bit is high, the SCSA pin will be enabled and used as a select pin. Bit 1SAWCOL: SPIA write collision flag 0: No collision 1: Collision The SAWCOL flag is used to detect whether a data collision has occurred or not. If this bit is high, it means that data has been attempted to be written to the SPIAD register duting a data transfer operation. This writing operation will be ignored if data is being transferred. This bit can be cleared by the application program. Bit 0SATRF: SPIA Transmit/Receive complete flag 0: SPIA data is being transferred 1: SPIA data transfer is completed The SATRF bit is the Transmit/Receive Complete flag and is set to 1 automatically when an SPIA data transfer is completed, but must cleared to 0 by the application program. It can be used to generate an interrupt. SPIA Communication After the SPIA interface is enabled by setting the SPIAEN bit high, then in the Master Mode, when data is written to the SPIAD register, transmission/reception will begin simultaneously. When the data transfer is complete, the SATRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SPIAD register will be transmitted and any data on the SDIA pin will be shifted into the SPIAD registers. The master should output a SCSA signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCSA signal depending upon the configurations of the SACKPOLB bit and SACKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCSA signal for various configurations of the SACKPOLB and SACKEG bits. The SPIA will continue to function if the SPIA clock source is active. Rev. 1.30 144 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU SPIA Master Mode Timing SPIA Slave Mode Timing – SACKEG=0 SPIA Slave Mode Timing – SACKEG=1 Rev. 1.30 145 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU SPIA Transfer Control Flowchart SPIA Bus Enable/Disable To enable the SPIA bus, set SACSEN=1 and SCSA =0, then wait for data to be written into the SPIAD (TXRX buffer) register. For the Master Mode, after data has been written to the SPIAD (TXRX buffer) register, then transmission or reception will start automatically. When all the data has been transferred the SATRF bit should be set. For the Slave Mode, when clock pulses are received on SCKA, data in the TXRX buffer will be shifted out or data on SDIA will be shifted in. To Disable the SPIA bus SCKA, SDIA, SDOA, SCSA will become I/O pins or other pin-shared functions. Rev. 1.30 146 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU SPIA Operation All communication is carried out using the 4-line interface for either Master or Slave Mode. The SACSEN bit in the SPIAC1 register controls the overall function of the SPIA interface. Setting this bit high will enable the SPIA interface by allowing the SCSA line to be active, which can then be used to control the SPIA interface. If the SACSEN bit is low, the SPIA interface will be disabled and the SCSA line will be an I/O pin or other pin-shared functions and can therefore not be used for control of the SPIA interface. If the SACSEN bit and the SPIAEN bit in the SPIAC0 register are set high, this will place the SDIA line in an I/O pin or other pin-shared functions and the SDOA line high. If in Master Mode the SCKA line will be either high or low depending upon the clock polarity selection bit SACKPOLB in the SPIAC1 register. If in Slave Mode the SCKA line will be in an I/O pin or other pin-shared functions. If SPIAEN is low then the bus will be disabled and SCSA, SDIA, SDOA and SCKA pins will all become I/O pins or other pin-shared functions. In the Master Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written into the SPIAD register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission and reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode. Master Mode • Step 1 Select the clock source and Master mode using the SASPI2~SASPI0 bits in the SPIAC0 control register • Step 2 Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB shifted first, this must be same as the Slave device. • Step 3 Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface. • Step 4 For write operations: write the data to the SPIAD register, which will actually place the data into the TXRX buffer. Then use the SCKA and SCSA lines to output the data. After this go to step 5. For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SPIAD register. • Step 5 Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the SATRF bit or wait for a SPIA serial bus interrupt. • Step 7 Read data from the SPIAD register. • Step 8 Clear SATRF. • Step 9 Go to step 4. Rev. 1.30 147 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Slave Mode • Step 1 Select the SPI Slave mode using the SASPI2~SASPI0 bits in the SPIAC0 control register • Step 2 Setup the SACSEN bit and setup the SAMLS bit to choose if the data is MSB or LSB shifted first, this setting must be the same with the Master device. • Step 3 Setup the SPIAEN bit in the SPIAC0 control register to enable the SPIA interface. • Step 4 For write operations: write the data to the SPIAD register, which will actually place the data into the TXRX buffer. Then wait for the master clock SCKA and SCSA signal. After this, go to step 5. For read operations: the data transferred in on the SDIA line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SPIAD register. • Step 5 Check the SAWCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the SATRF bit or wait for a SPIA serial bus interrupt. • Step 7 Read data from the SPIAD register. • Step 8 Clear SATRF. • Step 9 Go to step 4. Error Detection The SAWCOL bit in the SPIAC1 register is provided to indicate errors during data transfer. The bit is set by the SPIA serial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SPIAD register takes place during a data transfer operation and will prevent the write operation from continuing. Rev. 1.30 148 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Direct Memory Access – DMA The device contains a Direct Memory Access, DMA, controller which is used for direct data exchange with external devices without using the MCU resources. This assumes that the data to be transferred is prepared and ready. The DMA controller exchanges the data with the external device using the independent Serial Interface. This has the name SPIA and is described in another section. The SPIA name is used to distinguish it from other SPI interface which exists in the Serial Interface Module, SIM. The data to be transmitted by the DMA controller must first be written into Data Memory Sector 2. The received data will also be stored in Data Memory Sector 2. After the DMA data transfer is completed, a DMA interrupt will be generated if the corresponding interrupt control is enabled. SPIA_DMA_LEN (from start addr. to end addr.) SPIA_DMA_ADDR SPIA_DMA_RW_P Data Length 80H 81H : : : End Address : : : Start Address Address+1 Address+� : : : FEH FFH Data Memory Sector � : : : Data (m) : : : Data (n) Data (n+1) Data (n+�) : : : DMA interr�pt (Data transfer complete) SPIA Master Mode External Device DMA Using SPIA Interface DMA Controller The DMA controller implements data exchange with external devices using the SPIA interface setup in the master mode. If there is data to be transmitted to an external device, the data needs to be first written into the Data Memory Sector 2. The SPIA related registers must also be properly configured to set it up as an SPIA master device. Then the corresponding DMA configurations such as the DMA transfer start address and data length should be specified. After the configurations described above are setup, the DMA transfer start bit can be set from 0 to 1 to activate the DMA transfer. The DMA transfer start address can be set from 80H to FFH in Data Memory Sector 2 and the transfer data length can be from 1 to 128 bytes. The DMA transfer current address is specified by the read-only DMA address pointer which will be automatically incremented by 1 after each data byte is successfully transferred on the SPIA interface. When the address is greater than the maximum available address, FFH, and the desired DMA data transfer has not completed, the address will be wrapped around to the start address, 80H. Then the current address pointer will continue to be incremented by 1 until the desired DMA data transfer has completed. After the desired data transaction has completed, a DMA interrupt will be generated if the corresponding DMA interrupt control is enabled. The enable control bit, DMA_ON, will not be cleared to 0 automatically by hardware so must therefore be cleared to 0 by the application program after the current DMA data transfer has finished. Note that the DMA_ON bit must be set from 0 to 1 if the next DMA data transaction is necessary to be re-initiated after the current data transfer has completed. For another DMA transfer to take place the DMA_ON bit must be cleared to zero and again set high. If the DMA_ON bit remains high, further DMA data transfers will not be re-initiated. Rev. 1.30 149 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU DMA Registers There are four registers related to the DMA data transfer, which control the overall DMA data transfer operation. A DMA control register exists to store the DMA related error flags together with the DMA enable control and mode select. There is a data length register which is used to store the overall DMA data transfer length. There is also an address register together with a read-only address pointer which are used to manage the data address during the DMA data transfer operation. Bit Register Name 7 SPIA_ DMAC 6 5 4 3 2 1 0 DMA_ STERR DMA_ FST DMA_ ERROR DMA_ON — — — DMA_ HALTERR SPIA_DMA_ LEN — DL6 DL5 DL4 DL3 DL2 DL1 DL0 SPIA_DMA_ ADDR DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 SPIA_DMA_ RW_P DP7 DP6 DP5 DP4 DP3 DP2 DP1 DP0 DMA Registers List SPIADMAC Register Bit 7 6 5 4 3 2 1 0 DMA_ STERR DMA_ FST DMA_ ERROR Name DMA_ON — — — DMA_ HALTERR R/W R/W — — — R R R/W R POR 0 — — — 0 0 0 0 Bit 7DMA_ON: DMA enable control 0 → 1: DMA enabled 1 → 0: DMA disable Before using the DMA data transfer function the SPIA interface should first be properly configured to be in the master mode together with its other related configurations. After this the DMA data transfer will be activated when the DMA_ON bit is set from 0 to 1 if the corresponding DMA configurations are also properly setup. Note that this bit should be cleared to 0 by the application program after the whole DMA data transfer is completed. Bit 6~4 Unimplemented, read as "0" Bit 3DMA_HALTERR: DMA HALT error flag 0: No HALT instruction is executed during a DMA operation 1: HALT instruction is executed during a DMA operation This bit is set to 1 by the hardware when the MCU executes a HALT instruction during a DMA operation. This bit can be cleared to 0 by the application program or automatically cleared to 0 when the DMA_ON bit is re-set from 0 to 1. The DMA data transfer will immediately be terminated and the address pointer will remain unchanged if the MCU executes a HALT instruction during the DMA operation. This will result in the DMA_HALTERR bit being set to 1. Bit 2DMA_STERR: DMA Start error flag 0: No Start error occurs during a DMA operation 1: Start error occurs during a DMA operation This bit is set to 1 by the hardware if the DMA_ON or SPIAEN bit is cleared to 0 to stop the DMA transfer when the DMA transfer is operating. This bit can be cleared to 0 by the application program or automatically cleared to 0 when the DMA_ON bit is re-set from 0 to 1. When the DMA_STERR bit is set to 1, the DMA error interrupt will be generated if the corresponding interrupt is enabled. Rev. 1.30 150 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU If the DMA_ON bit is cleared to 0 during the DMA operation, the current DMA data byte transfer will not immediately be terminated until the current byte transfer is finished. The address pointer will then be incremented by one. Then overall DMA data transfer will be terminated and the DMA_STERR bit will be set to 1. However, if the SPIAEN bit is cleared to 0 during the DMA operation, the current data byte transfer will immediately be terminated and the address pointer will be incremented by one followed by the DMA_STERR bit being set to 1. Bit 1DMA_FST: DMA transfer mode select 0: Normal mode 1: Fast mode Bit 0DMA_ERROR: DMA Write error flag 0: No write error occurs during a DMA operation 1: Write error occurs during a DMA operation This bit is set to 1 by the hardware if the MCU writes a data byte into a certain location in Data memory Sector 2, during a time where data is being transferred to the external device via the SPIA interface. This bit can be cleared to 0 by the application program or automatically cleared to 0 when the DMA_ON bit is re-set from 0 to 1. When the DMA_ERROR bit is set to 1, a DMA error interrupt will be generated if the corresponding interrupt is enabled. The MCU write operation will be ignored and the DMA controller will continue to transfer data with the DMA_ERROR bit being set to 1 when the same Data Memory address is accessed by the DMA transfer and the MCU write access. SPIA_DMA_LEN Register Bit 7 6 5 4 3 2 1 0 Name — DL6 DL5 DL4 DL3 DL2 DL1 DL0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 1 1 1 1 1 1 Bit 7 Unimplemented, read as "0" Bit 6~0DL6~DL0: DMA data transfer length DMA data transfer length = [DL6 ~ DL0] + 1 DMA data transfer length can be from 1 to 128 byte. SPIA_DMA_ADDR Register Bit 7 6 5 4 3 2 1 0 Name DA7 R/W — DA6 DA5 DA4 DA3 DA2 DA1 DA0 R/W R/W R/W R/W R/W R/W POR 1 0 R/W 0 0 0 0 0 0 Bit 7DA7: MSB of the DMA address, fixed as "1" Bit 6~0DA6~DA0: DMA data transfer start address DMA data transfer start address can be from 80H to FFH. SPIA_DMA_RW_P Register Bit 7 6 5 4 3 2 1 0 Name DP7 DP6 DP5 DP4 DP3 DP2 DP1 DP0 R/W R R R R R R R R POR 1 0 0 0 0 0 0 0 Bit 7~0DP7~DP0: DMA data transfer current address pointer DMA data transfer start address can be from 80H to FFH. Rev. 1.30 151 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU DMA Data Transfer using SPIA Interface When there is data to be transferred by the DMA controller, the data has to first be written into Data Memory Sector 2. The SPIA interface master mode is used to transfer the data stored in the Data Memory Sector 2 and therefore the corresponding SPIA registers should be properly configured. The DMA relevant registers should also be setup before the DMA_ON bit is correctly initiated. After the DMA_ON is set from 0 to 1, the data which has been written into Data Memory Sector 2 will automatically be transmitted via the SDOA line to the external device while data from the external device will be received on the SDIA line. After the whole data transaction has finished, a DMA interrupt will be generated if the relevant interrupt function is enabled. The DMA_ON bit should be cleared to 0 by the application program. When the DMA data transfer is activated and one byte of data has completely transferred using the SPIA master mode, the SPIA transfer complete flag, SATRF, will be set to 1 and an SPIA complete transfer interrupt will be generated if the related interrupt control is enabled. Then the data byte at the same time received from the SDIA line will be moved into Data Memory Sector 2. After this the DMA address pointer will be incremented by one and the SATRF flag will be cleared to 0 automatically and the next data byte will be loaded into the SPIA data register, SPIAD, in preparation for the next data byte transfer. DMA Error Management When data is transferring via the DMA controller, three types of errors may occur. These errors are DMA HALT error, DMA Start error and DMA Write error. When the DMA data is transferring and the MCU executes a HALT instruction, the DMA HALT error condition will occur. If a DMA HALT error occurs, the current DMA data transfer will immediately be terminated, the address pointer will remain unchanged and the corresponding error flag, DMA_HALTERR, will be set to 1. When the DMA_ON or SPIAEN bit is cleared to 0 to stop a presently executing DMA transfer, a DMA Start error condition will occur and the DMA error interrupt request will be generated. If a DMA Start error occurs due to the DMA operation being disabled by clearing the DMA_ON bit to 0, the current DMA data byte transfer will not immediately be terminated until the current byte transfer is finished. The address pointer will then be incremented by one and the corresponding error flag, DMA_STERR, will be set to 1. However, if a DMA Start error occurs due to the SPIA interface being disabled by clearing the SPIAEN bit to 0, the current DMA data transfer will immediately be terminated, the address pointer will be incremented by one and the DMA_STERR bit will set to 1. When the MCU writes a data byte into a certain location in Data Memory Sector 2, during a time in which data is being transferred to the external device via the SPIA interface, a DMA Write error condition will occur and a DMA error interrupt request will be generated. If a DMA Write error occurs, the MCU write operation will be ignored, the DMA controller will continue to transfer data and the DMA_ERROR bit will be set to 1. Note that any of these error flags will be set to 1 by the hardware when the corresponding error condition occurs and will be cleared to 0 by the application program or automatically cleared when the DMA_ON bit is re-set from 0 to 1. DMA Interrupt There are two kinds of DMA interrupts, the DMA transfer interrupt and DMA error interrupt. The DMA transfer interrupt will occur when the whole of the DMA data is completely transferred while the DMA error interrupt will occur when the corresponding error condition occurs. The corresponding DMA interrupts must be enabled along with the EMI being enabled. Rev. 1.30 152 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU SCOM Function for LCD The device has the capability of driving external LCD panels. The common pins for LCD driving, SCOM0~SCOM3, are pin shared with the I/O pins. The LCD signals (COM and SEG) are generated using the application program. LCD Operation An external LCD panel can be driven using this device by configuring the I/O pins as common pins and using other output ports lines as segment pins. The LCD driver function is controlled using the SCOMC register which in addition to controlling the overall on/off function also controls the bias voltage setup function. This enables the LCD COM driver to generate the necessary VDD/2 voltage levels for LCD 1/2 bias operation. The SCOMEN bit in the SCOMC register is the overall master control for the LCD driver. The LCD SCOMn pin is selected to be used for LCD driving by the corresponding pin-shared function selection bits. Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation. Pin-shared selection bits SCOMEN LCD COM Bias LCD Bias Control The LCD COM driver enables a range of selections to be provided to suit the requirement of the LCD panel which is being used. The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in the SCOMC register. SCOMC Register Bit 7 6 5 4 3 2 1 0 Name — ISEL1 ISEL0 SCOMEN — — — — R/W — R/W R/W R/W — — — — POR — 0 0 0 — — — — Bit 7 Unimplemented, read as "0" Bit 6~5ISEL1~ISEL0: Select SCOM typical bias current (VDD=5V) 00: 25μA 01: 50μA 10: 100μA 11: 200μA Bit 4SCOMEN: SCOM Function enable control 0: Disable 1: Enable Bit 3~0 Rev. 1.30 Unimplemented, read as "0" 153 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Voice Controller The device contains a highly flexible and full featured voice controller to manage the voice recording and voice playback operations. On the recording side is 16-bit A/D converter and programmable gain control amplifier for the microphone input signal processing. To manage the problem of signals with large dynamic ranges and reduce memory storage requirements, there is the option to compress the digitised recorded data using the fully integrated compander function. Both μ-law and a-law algorithms can be selected as the compression technique. On the playback side there is a fully integrated 16-bit D/A converter complete with volume control. A power amplifier offers the possibility of directly driving external speakers. If the recorded data has been compressed, the internal compander will decode the recorded digitised data before being transmitted to the D/A converter for conversion to an analog signal. An external crystal provides the oscillator source for the internal Phase Locked Loop, PLL, which offers a wide range of recording and playback frequencies. RECFQ[1:0] HXT PLL PLAFQ[1:0] Divider Voice play frequency Voice record frequency 8 16 PGA[5:0] Microphone Record 16-bit PCM A/D Converter MICMUTEB ADC_RESB ADEN 16 RECDL 8 PGA 8 16 G.711 Compander REC_COMP_OPT M U X 8 RECDH REC_UA_EN PLA_EXPAND_OPT 16-bit D/A + Power Amplifier Play M U X 16 Speaker DAEN, PAEN, MUTEB USVC[6:0] 16 16 PLA_UA_EN 8 8 8 PLADH PLADL Voice Controller Block Diagram PLL Operation The voice recording and playback clock are derived from a fully integrated PLL circuit. There is no individual enable control bit for the PLL operation. The PLL circuit is controlled by several control bits including the ADEN, ADC_RESB and DAEN bits together with the corresponding voice record and play interrupt enable control bits, RECE and PLAYE. The PLL circuit will be disabled if the related control bits are all cleared to 0 or if the device enters the power down mode. Otherwise, the PLL circuit will be enabled when any of the related control bits are set to 1. After the PLL is enabled and has stabilised, the clock output is further divided by a specific ratio determined by the recording and playing clock frequency selection bits, RECFQ and PLAFQ bit fields. It is recommended that the same frequency is used for both voice recording and playback. Rev. 1.30 154 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Note that the PLL circuit is enabled by the voice record or play interrupt enable control bits even if the voice recording or playing function is not enabled. This is because the voice recording or playing frequency source can also be used as a general purpose time base when the recording or playing function is not enabled. Device Power Down Yes No ADEN ADC_RESB DAEN RECE PLAE PLL Circuit x x x x x Disabled 0 0 0 0 0 Disabled 1 x x x x x 1 x x x x x 1 x x x x x 1 x x x x x 1 Enabled Voice Recording Operation The voice input from the external microphone is recorded by sampling with a specific recording frequency. This frequency is selected by the RECFQ1 and RECFQ0 bits and then digitised by a 16bit PCM A/D converter. The 16-bit digitised PCM value is then amplified by a PGA which has a programmable gain, the value of which is setup using the PGA [5:0] bits. The 16-bit PCM data can be stored in two different ways, direct data storage or first compressed and then stored. This is determined by the REC_UA_EN bit. If the REC_UA_EN bit is cleared to zero, the G.711 Compander compressor function will be disabled and the 16-bit PCM data will be directly stored in the RECDH and RECDL register pair. If the REC_UA_EN bit is set high, the 16-bit PCM data will be first compressed and encoded into 8-bit data using a μ-law or a-law algorithm and then stored into in the RECDH register. The compression type selection is selected by the REC_COMP_ OPT bit. The RECDH/RECDL register pair should be read with a fixed frequency, i.e. the voice recording sample rate, which is determined using the RECFQ [1:0] bits. The voice record interrupt request will be generated with a specific frequency, which is known as the voice recording sample rate. Voice Playing Operation The voice data located in the PLADH and PLADL register pair can be output with a specific play frequency to the external speaker using the 16-bit D/A converter and a power amplifier whose volume control is setup using the USVC [6:0] bits. The 16-bit voice data in the PLADH and PLADL registers can be directly sent to the D/A converter if the PLA_UA_EN bit is cleared to 0 to disable the G.711 Compander expander function. If the PLA_UA_EN bit is set to 1, the 8-bit data in the PLADH register will be expanded and decoded into 16-bit data using either a μ-law or a-law algorithm. The algorithm selection is determined using the PLA_EXPAND_OPT bit. This expanded 16-bit data will then be transmitted to the 16-bit D/A converter and power amplifier for playback. The volume control can be adjusted using the relevant bits. The PLADH/PLADL register pair should be setup with a fixed frequency, which will be what determines the voice playing sample rate. This is setup using the PLAFQ [1:0] bits. The voice play interrupt request will be generated with a specific frequency, which is known as the voice playing sample rate. Rev. 1.30 155 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Voice Controller Registers The overall voice record and play functions are controlled using a series of registers. Four control registers exist to control the 16-bit PCM A/D converter, PGA, G.711 Compander, 16-bit D/A converter and power amplifier functions together with the microphone and speaker mute control. Two data register pairs exist to store the data which is recorded and to be played. Bit Register Name PGAC RECPLAC COMPANDC 7 6 5 4 3 2 1 0 MICMUTEB ADC_ RESB PGA5 PGA4 PGA3 PGA2 PGA1 PGA0 RECFQ1 RECFQ0 — ADEN PLAFQ1 PLAFQ0 — — — — REC_ PLA_ COMP_OPT EXPAND_OPT PAEN DAEN REC_ UA_EN PLA_ UA_EN MUTEB USVC6 USVC5 USVC4 USVC3 USVC2 USVC1 USVC0 RECDL R_D7 R_D6 R_D5 R_D4 R_D3 R_D2 R_D1 R_D0 RECDH R_D15 R_D14 R_D13 R_D12 R_D11 R_D10 R_D9 R_D8 PLADL P_D7 P_D6 P_D5 P_D4 P_D3 P_D2 P_D1 P_D0 PLADH P_D15 P_D14 P_D13 P_D12 P_D11 P_D10 P_D9 P_D8 USVC Voice Controller Registers List PGAC Register Bit Name 7 6 MICMUTEB ADC_RESB 5 4 3 2 1 0 PGA5 PGA4 PGA3 PGA2 PGA1 PGA0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7MICMUTEB: Microphone Mute control 0: Mute microphone input 1: Enable microphone input Bit 6ADC_RESB: 16-bit PCM A/D converter reset control 0: PCM A/D converter in reset condition 1: PCM A/D converter in normal operation This bit is used to control the 16-bit PCM A/D converter reset function. The PCM A/D converter will be reset when any MCU reset condition occurs or if the ADC_RESB bit is cleared to 0 by the application program. Note that the PCM A/D converter should be reset for at least 100μs by clearing the ADC_RESB bit to 0 to successfully reset the PCM A/D converter after it is enabled by setting the ADEN bit to 1. Bit 5~0PGA5~PGA0: PGA gain control 000000: Gain ≈ 0 dB 000001: Gain ≈ 0.5 dB 000010: Gain ≈ 1.0 dB 000011: Gain ≈ 1.5 dB : : 100110: Gain ≈ 19.0 dB 100111: Gain ≈ 19.5 dB 101000: Gain ≈ 19.5 dB : : 111111: Gain ≈ 19.5 dB These bits are used to control the PGA gain which ranges from 0dB~19.5dB. The PGA is a digital amplifier used to amplify the 16-bit data that comes from the PCM A/D converter. Rev. 1.30 156 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU RECPLAC Register Bit Name 7 6 RECFQ1 RECFQ0 5 4 3 2 1 0 PLAFQ1 PLAFQ0 — ADEN PAEN DAEN R/W R/W R/W R/W R/W — R/W R/W R/W POR 0 0 0 0 — 0 0 0 Bit 7~6RECFQ1~RECFQ0: Recording frequency selection 00: 8 kHz 01: 16 kHz 10: 12 kHz 11: 24 kHz Bit 5~4PLAFQ1~PLAFQ0: Playing frequency selection 00: 8 kHz 01: 16 kHz 10: 12 kHz 11: 24 kHz Bit 3 Unimplemented, read as "0" Bit 2ADEN: 16-bit PCM A/D converter Enable control 0: Disable 1: Enable This bit is used to control the 16-bit PCM A/D converter enable function. After the PCM A/D converter is enabled by setting the ADEN bit to 1, it is recommended to clear the ADC_RESB bit to 0 for at least 100μs to successfully complete the PCM A/ D converter reset procedure. Bit 1PAEN: Power Amplifier Enable control 0: Disable 1: Enable Bit 0DAEN: 16-bit D/A converter Enable control 0: Disable 1: Enable Note that the PLL circuit, 16-bit PCM A/D converter, 16-bit D/A converter and power amplifier will all be disabled when the MCU enters the Power down Mode. COMPANDC Register Bit Name 7 6 5 4 3 2 1 REC_ PLA_ REC_ COMP_OPT EXPAND_OPT UA_EN 0 PLA_ UA_EN — — — — R/W — — — — — R/W R/W R/W POR — — — — — 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3REC_COMP_OPT: Record Compressing algorithm select 0: μ-law 1: a-law Bit 2PLA_EXPAND_OPT: Play Expanding algorithm select 0: μ-law 1: a-law Bit 1REC_UA_EN: Record Compressor Enable control 0: Disable 1: Enable This bit is used to control the record compressor function. When this bit is cleared to 0, the record compressor will be disabled and the 16-bit recorded data will be stored in the RECDH and RECDL registers without compression. If this bit is set to 1, the record compressor will be enabled and the 16-bit recorded data will be compressed into an 8-bit encoded data in μ-law or a-law algorithm determined using the corresponding algorithm selection bit. After compression this encoded data will be stored in the RECDH register. Rev. 1.30 157 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Bit 0PLA_UA_EN: Play Expander Enable control 0: Disable 1: Enable This bit is used to control the play expander function. When this bit is cleared to 0, the play expander will be disabled and the 16-bit data which is stored in the PLADH and PLADL registers will be sent to the D/A converter without being expanded. If this bit is set to 1, the play expander will be enabled and the 8-bit encoded data stored in the PLADH register will be expanded into 16-bit decoded data using a μ-law or a-law algorithm determined using the corresponding algorithm selection bit. After decoding the data will be sent to the D/A converter and played. USVC Register Bit 7 6 5 4 3 2 1 0 Name MUTEB USVC6 USVC5 USVC4 USVC3 USVC2 USVC1 USVC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7MUTEB: Speaker Mute control 0: Mute speaker output 1: Enable speaker output This bit is used to enable the speaker function. When this bit is cleared to 0, the speaker function will be disabled. The D/A converter and power amplifier will also be disabled. Bit 6~0USVC6~USVC0: Speaker volume control 000_1100: Gain ≈ 6.0 dB 000_1011: Gain ≈ 5.5 dB 000_1010: Gain ≈ 5.0 dB 000_1001: Gain ≈ 4.5 dB 000_1000: Gain ≈ 4.0 dB 000_0111: Gain ≈ 3.5 dB 000_0110: Gain ≈ 3.0 dB 000_0101: Gain ≈ 2.5 dB 000_0100: Gain ≈ 2.0 dB 000_0011: Gain ≈ 1.5 dB 000_0010: Gain ≈ 1.0 dB 000_0001: Gain ≈ 0.5 dB 000_0000: Gain ≈ 0.0 dB 111_1111: Gain ≈ -0.5 dB 111_1110: Gain ≈ -1.0 dB 111_1101: Gain ≈ -1.5 dB 111_1100: Gain ≈ -2.0 dB 111_1011: Gain ≈ -2.5 dB 111_1010: Gain ≈ -3.0 dB 111_1001: Gain ≈ -3.5 dB 111_1000: Gain ≈ -4.0 dB 111_0111: Gain ≈ -4.5 dB 111_0110: Gain ≈ -5.0 dB 111_0101: Gain ≈ -5.5 dB 111_0100: Gain ≈ -6.0 dB 111_0011: Gain ≈ -6.5 dB 111_0010: Gain ≈ -7.0 dB 111_0001: Gain ≈ -7.5 dB 111_0000: Gain ≈ -8.0 dB 110_1111: Gain ≈ -8.5 dB 110_1110: Gain ≈ -9.0 dB 110_1101: Gain ≈ -9.5 dB Rev. 1.30 158 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU 110_1100: Gain ≈ -10.0 dB 110_1011: Gain ≈ -10.5 dB 110_1010: Gain ≈ -11.0 dB 110_1001: Gain ≈ -11.5 dB 110_1000: Gain ≈ -12.0 dB 110_0111: Gain ≈ -13.0 dB 110_0110: Gain ≈ -14.0 dB 110_0101: Gain ≈ -15.0 dB 110_0100: Gain ≈ -16.0 dB 110_0011: Gain ≈ -17.0 dB 110_0010: Gain ≈ -18.0 dB 110_0001: Gain ≈ -19.0 dB 110_0000: Gain ≈ -20.0 dB 101_1111: Gain ≈ -21.0 dB 101_1110: Gain ≈ -22.0 dB 101_1101: Gain ≈ -23.0 dB 101_1100: Gain ≈ -24.0 dB 101_1011: Gain ≈ -25.0 dB 101_1010: Gain ≈ -26.0 dB 101_1001: Gain ≈ -27.0 dB 101_1000: Gain ≈ -28.0 dB 101_0111: Gain ≈ -29.0 dB 101_0110: Gain ≈ -30.0 dB 101_0101: Gain ≈ -31.0 dB 101_0100: Gain ≈ -32.0 dB Others: Reserved These bits are used to control the output volume which ranges from -32dB~6dB. RECDL Register Bit 7 6 5 4 3 2 1 0 Name R_D7 R_D6 R_D5 R_D4 R_D3 R_D2 R_D1 R_D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0R_D7~R_D0: Recorded data low byte register bit 7~bit 0 This register is used to store the 16-bit recorded PCM data low byte. RECDH Register Bit 7 6 5 4 3 2 1 0 Name R_D15 R_D14 R_D13 R_D12 R_D11 R_D10 R_D9 R_D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0R_D15~R_D8: Recorded data high byte register bit 7~bit 0 This register is used to store the 16-bit PCM data high byte when the REC_UA_EN bit is cleared to 0. If the REC_UA_EN bit is set to 1, this register is used to store the 8-bit compressed μ-law or a-law data. Rev. 1.30 159 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU PLADL Register Bit 7 6 5 4 3 2 1 0 Name P_D7 P_D6 P_D5 P_D4 P_D3 P_D2 P_D1 P_D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0P_D7~P_D0: Play data low byte register bit 7~bit 0 This register is used to store the 16-bit PCM play data low byte PLADH Register Bit 7 6 5 4 3 2 1 0 Name P_D15 P_D14 P_D13 P_D12 P_D11 P_D10 P_D9 P_D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0P_D15~P_D8: Played data high byte register bit 7~bit 0 This register is used to store the 16-bit PCM play data high byte data when the PLA_ UA_EN bit is cleared to 0. If the PLA_UA_EN bit is set to 1, this register is used to store the 8-bit compressed μ-law or a-law data which will be expanded to 16-bit PCM data and then played. Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0 and INT1 pins, while the internal interrupts are generated by various internal functions such as the TMs, Time Base, LVD, EEPROM, SIM, Voice Play/Record, DMA and the A/ D converter, etc. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. The first is the INTC0~INTC3 registers which setup the primary interrupts, the second is the MFI0~MFI3 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual interrupts as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Rev. 1.30 160 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Function Enable Bit Request Flag EMI — — INTn Pins INTnE INTnF n=0~1 Voice Play PLAYE PLAYF — Voice Record RECE RECF — Multi-function MFnE MFnF n=0~3 A/D Converter ADE ADF — Time Base TBnE TBnF n=0~1 — Global DMA Transfer Notes DMAE DMAF DMAERRE DMAERRF — LVD LVE LVF — EEPROM write operation DEE DEF — DMA Error SIM SIME SIMF — SPIA SPIAE SPIAF — CTMPE CTMPF CTMAE CTMAF STMPE STMPF STMAE STMAF PTMPE PTMPF PTMAE PTMAF CTM STM PTM — — — Interrupt Register Bit Naming Conventions Bit Register Name 7 6 5 4 3 2 1 0 INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — RECF PLAYF INT0F RECE PLAYE INT0E EMI INTC1 MF3F MF2F MF1F MF0F MF3E MF2E MF1E MF0E INTC2 INT1F TB1F TB0F ADF INT1E TB1E TB0E ADE INTC3 — — DMAERRF DMAF — — DMAERRE DMAE MFI0 — — CTMAF CTMPF — — CTMAE CTMPE MFI1 — — STMAF STMPF — — STMAE STMPE MFI2 — — PTMAF PTMPF — — PTMAE PTMPE MFI3 SPIAF SIMF DEF LVF SPIAE SIME DEE LVE Interrupt Registers List INTEG Register Bit 7 6 5 4 3 2 1 0 Name — — — — INT1S1 INT1S0 INT0S1 INT0S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~2INT1S1~INT1S0: Interrupt edge control for INT1 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Bit 1~0INT0S1~INT0S0: Interrupt edge control for INT0 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Rev. 1.30 161 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU INTC0 Register Bit 7 6 5 4 3 2 1 0 Name — RECF PLAYF INT0F RECE PLAYE INT0E EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6RECF: Voice Record interrupt request flag 0: no request 1: interrupt request Bit 5PLAYF: Voice Play interrupt request flag 0: no request 1: interrupt request Bit 4INT0F: INT0 interrupt request flag 0: no request 1: interrupt request Bit 3RECE: Voice Record interrupt control 0: Disable 1: Enable Bit 2PLAYE: Voice Play interrupt control 0: Disable 1: Enable Bit 1INT0E: INT0 interrupt control 0: Disable 1: Enable Bit 0EMI: Global interrupt control 0: Disable 1: Enable INTC1 Register Bit 7 6 5 4 3 2 1 0 Name MF3F MF2F MF1F MF0F MF3E MF2E MF1E MF0E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 MF3F: Multi-function 3 interrupt request flag 0: no request 1: interrupt request Bit 6MF2F: Multi-function 2 interrupt request flag 0: no request 1: interrupt request Bit 5MF1F: Multi-function 1 interrupt request flag 0: no request 1: interrupt request Bit 4MF0F: Multi-function 0 interrupt request flag 0: no request 1: interrupt request Bit 3MF3E: Multi-function 3 interrupt control 0: Disable 1: Enable Bit 2MF2E: Multi-function 2 interrupt control 0: Disable 1: Enable Bit 1MF1E: Multi-function 1 interrupt control 0: Disable 1: Enable Bit 0MF0E: Multi-function 0 interrupt control 0: Disable 1: Enable Bit 7 Rev. 1.30 162 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU INTC2 Register Bit 7 6 5 4 3 2 1 0 Name INT1F TB1F TB0F ADF INT1E TB1E TB0E ADE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request Bit 6TB1F: Time Base 1 interrupt request flag 0: No request 1: Interrupt request Bit 5TB0F: Time Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 4ADF: A/D Converter interrupt request flag 0: No request 1: Interrupt request Bit 3INT1E: INT1 interrupt control 0: Disable 1: Enable Bit 2TB1E: Time Base 1 interrupt control 0: Disable 1: Enable Bit 1TB0E: Time Base 0 interrupt control 0: Disable 1: Enable Bit 0ADE: A/D Converter interrupt control 0: Disable 1: Enable INTC3 Register Bit 7 6 5 4 3 2 1 0 Name — — DMAERRF DMAF — — DMAERRE DMAE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5DMAERRF: DMA Error interrupt request flag 0: No request 1: Interrupt request Bit 5DMAF: DMA transfer interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1DMAERRE: DMA Error interrupt control 0: Disable 1: Enable Bit 0DMAE: DMA Transfer interrupt control 0: Disable 1: Enable Rev. 1.30 163 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU MFI0 Register Bit 7 6 5 4 3 2 1 0 Name — — CTMAF CTMPF — — CTMAE CTMPE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5CTMAF: CTM Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4CTMPF: CTM Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1CTMAE: CTM Comparator A match Interrupt control 0: Disable 1: Enable Bit 0CTMPE: CTM Comparator P match Interrupt control 0: Disable 1: Enable MFI1 Register Bit 7 6 5 4 3 2 1 0 Name — — STMAF STMPF — — STMAE STMPE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5STMAF: STM Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4STMPF: STM Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1STMAE: STM Comparator A match Interrupt control 0: Disable 1: Enable Bit 0STMPE: STM Comparator P match Interrupt control 0: Disable 1: Enable Rev. 1.30 164 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU MFI2 Register Bit 7 6 5 4 3 2 1 0 Name — — PTMAF PTMPF — — PTMAE PTMPE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5PTMAF: PTM Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4PTMPF: PTM Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1PTMAE: PTM Comparator A match Interrupt control 0: Disable 1: Enable Bit 0PTMPE: PTM Comparator P match Interrupt control 0: Disable 1: Enable MFI3 Register Bit 7 6 5 4 3 2 1 0 Name SPIAF SIMF DEF LVF SPIAE SIME DEE LVE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7SPIAF: SPIA Interrupt request flag 0: No request 1: Interrupt request Bit 6SIMF: SIM Interrupt request flag 0: No request 1: Interrupt request Bit 5DEF: Data EEPROM Interrupt request flag 0: No request 1: Interrupt request Bit 4LVF: LVD Interrupt request flag 0: No request 1: Interrupt request Bit 3SPIAE: SPIA Interrupt control 0: Disable 1: Enable Bit 2SIME: SIM Interrupt control 0: Disable 1: Enable Bit 1DEE: Data EEPROM Interrupt control 0: Disable 1: Enable Bit 0LVE: LVD Interrupt control 0: Disable 1: Enable Rev. 1.30 165 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A or A/ D conversion completion, etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 1.30 166 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU EMI auto disabled in ISR Legend xxF Request Flag, no auto reset in ISR xxF Request Flag, auto reset in ISR xxE Enable Bits Interrupts contained within Multi-Function Interrupts Interrupt Name Request Flags Enable Bits Master Enable INT0 Pin INT0F INT0E EMI Play INT PLAYF PLAYE EMI 08H Record INT RECF RECE EMI 0CH M. Funct. 0 MF0F MF0E EMI 10H M. Funct. 1 MF1F MF1E EMI 14H M. Funct. 2 MF2F MF2E EMI 18H M. Funct. 3 MF3F MF3E EMI 1CH Vector Priority High 04H CTM P CTMPF CTMPE CTM A CTMAF CTMAE STM P STMPF STMPE STM A STMAF STMAE PTM P PTMPF PTMPE PTM A PTMAF PTMAE A/D ADF ADE EMI 20H LVD LVF LVE Time Base 0 TB0F TB0E EMI 24H EEPROM DEF DEE SIM SIMF SIME Time Base 1 TB1F TB1E EMI 28H SPIA SPIAF SPIAE INT1 Pin INT1F INT1E EMI 2CH DMA INT DMAF DMAE EMI 30H DMAERRE EMI 34H DMA Error DMAERRF Low Interrupt Scheme External Interrupt The external interrupts are controlled by signal transitions on the pins INT0~INT1. An external interrupt request will take place when the external interrupt request flags, INT0F~INT1F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT1E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins and the external interrupt pin is selected by the corresponding pin-shared function selection bits. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. Rev. 1.30 167 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Voice Play Interrupt The Voice Play interrupt is controlled by a dedicated voice-play timer whose time-out frequency is determined by the PLAFQ1 and PLAFQ0 bits in the RECPLAC register. When the timer with specific frequency time-out occurs, the voice play interrupt request will take place and the relevant request flag will be set. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and voice play interrupt enable bit, PLAYE, must first be set. When the interrupt is enabled, the stack is not full and the voice play timer time-out occurs, a subroutine call to the voice play interrupt vector will take place. When the interrupt is serviced, the voice play interrupt request flag will be automatically reset and the EMI bit will also be automatically cleared to disable other interrupts. Voice Record Interrupt The Voice Record interrupt is controlled by a dedicated voice-record timer whose time-out frequency is determined by the RECFQ1 and RECFQ0 bits in the RECPLAC register. When the voice-record timer with specific frequency time-out occurs, the voice record interrupt request will take place and the relevant request flag will be set. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and voice record interrupt enable bit, RECE, must first be set. When the interrupt is enabled, the stack is not full and the voice record timer time-out occurs, a subroutine call to the voice record interrupt vector will take place. When the interrupt is serviced, the voice record interrupt request flag will be automatically reset and the EMI bit will also be automatically cleared to disable other interrupts. Multi-function Interrupt Within the device there are up to four Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM interrupts, LVD interrupt, EEPROM write operation interrupt, SIM and SPIA interface interrupts. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags MFnF are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt request flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts will not be automatically reset and must be manually reset by the application program. Rev. 1.30 168 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU A/D Converter Interrupt The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/ D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Time Base Interrupt The function of the Time Base Interrupt is to provide regular time signal in the form of an internal interrupt. It is controlled by the overflow signal from its internal timer. When this happens its interrupt request flag, TBnF, will be set. To allow the program to branch to its respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bit, TBnE, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to its respective vector location will take place. When the interrupt is serviced, the interrupt request flag, TBnF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source, fPSC, originates from the internal clock source fSYS, fSYS/4 or fSUB and then passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TB0C and TB1C registers to obtain longer interrupt periods whose value ranges. The clock source which in turn controls the Time Base interrupt period is selected using the CLKSEL1 and CLKSEL0 bits in the PSCR register. M U X TB0ON fSYS fSYS/� fSUB M U X fPSC Prescaler fPSC/�8 ~ fPSC/�15 TB0[�:0] M U X TB1ON CLKSEL[1:0] Time Base 0 Interr�pt Time Base 1 Interr�pt TB1[�:0] Time Base Interrupts PSCR Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — CLKSEL1 CLKSEL0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 unimplemented, read as "0" Bit 1~0CLKSEL1~CLKSEL0: Prescaler clock source selection 00: fSYS 01: fSYS/4 1x: fSUB Rev. 1.30 169 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU TB0C Register Bit 7 6 5 4 3 2 1 0 Name TB0ON — — — — TB02 TB01 TB00 R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7TB0ON: Time Base 0 Enable Control 0: Disable 1: Enable Bit 6~3 unimplemented, read as "0" Bit 2~0TB02~TB00: Time Base 0 time-out division ratio selection 000: 28/fPSC 001: 29/fPSC 010: 210/fPSC 011: 211/fPSC 100: 212/fPSC 101: 213/fPSC 110: 214/fPSC 111: 215/fPSC TB1C Register Bit 7 6 5 4 3 2 1 0 Name TB1ON — — — — TB12 TB11 TB10 R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7TB1ON: Time Base 1 Enable Control 0: Disable 1: Enable Bit 6~3 unimplemented, read as "0" Bit 2~0TB12~TB10: Time Base 1 time-out period selection 000: 28/fPSC 001: 29/fPSC 010: 210/fPSC 011: 211/fPSC 100: 212/fPSC 101: 213/fPSC 110: 214/fPSC 111: 215/fPSC DMA Transfer Interrupt The DMA Transfer Interrupt is controlled by the termination of a DMA transfer process. A DMA Transfer Interrupt request will take place when the DMA data Transfer Interrupt request flag, DMAF, is set, which occurs when the DMA data transfer process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and DMA Transfer Interrupt enable bit, DMAE, must first be set. When the interrupt is enabled, the stack is not full and the DMA transfer process has ended, a subroutine call to the DMA Transfer Interrupt vector, will take place. When the interrupt is serviced, the DMA Transfer Interrupt flag, DMAF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Rev. 1.30 170 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU DMA Error Interrupt The DMA Error Interrupt is controlled by a DMA error occurrence. A DMA Error Interrupt request will take place when the DMA Error Interrupt request flag, DMAERRF, is set, which occurs when a DMA error occurs. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and DMA Error Interrupt enable bit, DMAERRE, must first be set. When the interrupt is enabled, the stack is not full and a DMA Error occurred, a subroutine call to the DMA Error Interrupt vector, will take place. When the interrupt is serviced, the DMA Error Interrupt flag, DMAERRF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Serial Interface Module Interrupt The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the Multi-function Interrupt. A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF or I2C address match or I2C time-out, is set, which occurs when a byte of data has been received or transmitted by the SIM interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, the Serial Interface Interrupt enable bit, SIME, and Muti-function interrupt enable bit must first be set. When the interrupt is enabled, the stack is not full and any of these situations occur, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SIMF flag will not be automatically cleared, it has to be cleared by the application program. SPIA Interface Interrupt The SPIA Interface Module Interrupt is contained within the Multi-function Interrupt. A SPIA Interrupt request will take place when the SPIA Interrupt request flag, SPIAF, is set, which occurs when a byte of data has been received or transmitted by the SPIA interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, the Serial Interface Interrupt enable bit, SPIAE, and Muti-function interrupt enable bit must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SPIA interface, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the SPIA Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SPIAF flag will not be automatically cleared, it has to be cleared by the application program. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. However, only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program. Rev. 1.30 171 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU EEPROM Interrupt The EEPROM Write Interrupt is contained within the Multi-function Interrupt. An EEPROM Write Interrupt request will take place when the EEPROM Write Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, EEPROM Write Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective Multi-function Interrupt vector will take place. When the EEPROM Write Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. However, only the Multi-function interrupt request flag will be automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. TM Interrupt The Compact, Standard and Periodic TMs have two interrupts, one comes from the comparator A match situation and the other comes from the comparator P match situation. All of the TM interrupts are contained within the Multi-function Interrupts. For all of the TM types there are two interrupt request flags and two enable control bits. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. However, only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though these devices are in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Rev. 1.30 172 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.30 173 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 3 2 1 0 Name — — LVDO LVDEN — VLVD2 VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7~6 unimplemented, read as "0" Bit 5LVDO: LVD output flag 0: No Low Voltage Detected 1: Low Voltage Detected Bit 4LVDEN: Low Voltage Detector Enable control 0: Disable 1: Enable Bit 3 unimplemented, read as "0" Bit 2~0VLVD2~VLVD0: LVD Voltage selection 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V Rev. 1.30 174 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. Rev. 1.30 175 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Application Circuits Wireless Voice Application Circuit (3V) − 1 VDD: Digital Power AVDD1: DAC Power AVDD_PA: Power Amplifier Power AVDD3: 16-bit PCM ADC Power PD5/SCKA PD4/SDOA PD3/SDIA PD1/SCSAB PD0 VDD SCK MOSI MISO CSN CE IRQ Matching Network PD2/INT1 VSS: Digital Ground AVSS1: DAC Ground AVSS3: 16-bit PCM ADC Ground AVSS_PA: Power Amplifier Ground Wireless Voice Application Circuit (3V) − 2 VDD: Digital Power AVDD1: DAC Power AVDD_PA: Power Amplifier Power AVDD3: 16-bit PCM ADC Power PD5/SCKA PD4/SDOA PD3/SDIA PD1/SCSAB PD0 VDD SCK MOSI MISO CSN CE IRQ Matching Network PD2/INT1 VSS: Digital Ground AVSS1: DAC Ground AVSS3: 16-bit PCM ADC Ground AVSS_PA: Power Amplifier Ground Rev. 1.30 176 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Record/Play Voice Application Circuit (3V) − 1 VDD: Digital Power AVDD1: DAC Power AVDD_PA: Power Amplifier Power AVDD3: 16-bit PCM ADC Power VSS: Digital Ground AVSS1: DAC Ground AVSS3: 16-bit PCM ADC Ground AVSS_PA: Power Amplifier Ground Record/Play Voice Application Circuit (3V) − 2 VDD: Digital Power AVDD1: DAC Power AVDD_PA: Power Amplifier Power AVDD3: 16-bit PCM ADC Power VSS: Digital Ground AVSS1: DAC Ground AVSS3: 16-bit PCM ADC Ground AVSS_PA: Power Amplifier Ground Rev. 1.30 177 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Record/Play Voice Application Circuit (5V) − 1 VDD: Digital Power AVDD1: DAC Power AVDD_PA: Power Amplifier Power AVDD3: 16-bit PCM ADC Power VSS: Digital Ground AVSS1: DAC Ground AVSS3: 16-bit PCM ADC Ground AVSS_PA: Power Amplifier Ground Record/Play Voice Application Circuit (5V) − 2 VDD: Digital Power AVDD1: DAC Power AVDD_PA: Power Amplifier Power AVDD3: 16-bit PCM ADC Power VSS: Digital Ground AVSS1: DAC Ground AVSS3: 16-bit PCM ADC Ground AVSS_PA: Power Amplifier Ground Rev. 1.30 178 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of several kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions such as INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.30 179 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction “RET” in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i” instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the “HALT” instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.30 180 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Instruction Set Summary The instructions related to the data memory access in the following table can be used when the desired data memory is located in Data Memory sector 0. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract immediate data from ACC with Carry Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1 1Note 1Note Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,x SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.30 181 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Mnemonic Description Cycles Flag Affected Data Move MOV A,[m] MOV [m],A MOV A,x Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None None 2Note 2Note 2Note None None None 2Note None 1 1Note 1Note 1 1Note 1 1 None None None TO, PDF None None TO, PDF Bit Operation CLR [m].i SET [m].i Branch Operation JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m] SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if Data Memory is not zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt Table Read Operation TABRD [m] Read table to TBLH and Data Memory TABRDL [m] Read table (last page) to TBLH and Data Memory ITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory Increment table pointer TBLP first and Read table (last page) to TBLH and ITABRDL [m] Data Memory Miscellaneous NOP CLR [m] SET [m] CLR WDT SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode Note: 1. For skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the “CLR WDT” instruction the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after the “CLR WDT” instructions is executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.30 182 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Extended Instruction Set The extended instructions are used to support the full range address access for the data memory. When the accessed data memory is located in any data memory sections except sector 0, the extended instruction can be used to access the data memory instead of using the indirect addressing access to improve the CPU firmware performance. Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 2 2Note 2 2Note 2 2Note 2 2Note 2Note Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ C 2 2 2 2Note 2Note 2Note 2Note 2 Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 2 2Note 2 2Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 2 2Note 2 2Note 2 2Note 2 2Note None None C C None None C C Move Data Memory to ACC Move ACC to Data Memory 2 2Note None None Clear bit of Data Memory Set bit of Data Memory 2Note 2Note None None Arithmetic LADD A,[m] LADDM A,[m] LADC A,[m] LADCM A,[m] LSUB A,[m] LSUBM A,[m] LSBC A,[m] LSBCM A,[m] LDAA [m] Logic Operation LAND A,[m] LOR A,[m] LXOR A,[m] LANDM A,[m] LORM A,[m] LXORM A,[m] LCPL [m] LCPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement LINCA [m] LINC [m] LDECA [m] LDEC [m] Rotate LRRA [m] LRR [m] LRRCA [m] LRRC [m] LRLA [m] LRL [m] LRLCA [m] LRLC [m] Data Move LMOV A,[m] LMOV [m],A Bit Operation LCLR [m].i LSET [m].i Rev. 1.30 183 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Mnemonic Description Cycles Flag Affected Branch LSZ [m] LSZA [m] LSNZ [m] LSZ [m].i LSNZ [m].i LSIZ [m] LSDZ [m] LSIZA [m] LSDZA [m] Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if Data Memory is not zero Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC 2Note 2Note 2Note 2Note 2Note 2Note 2Note 2Note 2Note None None None None None None None None None 3Note 3Note 3Note None None None 3Note None 2Note 2Note 2Note 2 None None None None Table Read LTABRD [m] Read table to TBLH and Data Memory LTABRDL [m] Read table (last page) to TBLH and Data Memory LITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory Increment table pointer TBLP first and Read table (last page) to TBLH and LITABRDL [m] Data Memory Miscellaneous LCLR [m] LSET [m] LSWAP [m] LSWAPA [m] Clear Data Memory Set Data Memory Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Note: 1. For these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. Any extended instruction which changes the contents of the PCL register will also require three cycles for execution. Rev. 1.30 184 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C, SC ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C, SC Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C, SC ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C, SC ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C, SC AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.30 185 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C Rev. 1.30 186 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None Rev. 1.30 187 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None Rev. 1.30 188 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C Rev. 1.30 189 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C, SC, CZ SBC A, x Description Operation Affected flag(s) Subtract immediate data from ACC with Carry The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC - [m] - C OV, Z, AC, C, SC, CZ SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C, SC, CZ SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None Rev. 1.30 190 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SNZ [m] Description Operation Affected flag(s) Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m]≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C, SC, CZ Rev. 1.30 191 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C, SC, CZ SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C, SC, CZ SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 1.30 192 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU TABRD [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None ITABRD [m] Description Operation Affected flag(s) Increment table pointer low byte first and read table to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None ITABRDL [m] Description Operation Affected flag(s) Increment table pointer low byte first and read table (last page) to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.30 193 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C, SC LADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C, SC LADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C, SC LADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C, SC LAND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z LANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z LCLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None LCLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None Rev. 1.30 Add Data Memory to ACC 194 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU LCPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z LCPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z LDAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C LDEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z LDECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z LINC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z LINCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.30 195 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU LMOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None LMOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None LOR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z LORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z LRL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None LRLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None LRLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C LRLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C Rev. 1.30 196 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU LRR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None LRRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None LRRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C LRRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C LSBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C, SC, CZ LSBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C, SC, CZ Rev. 1.30 197 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU LSDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None LSDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None LSET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None LSET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None LSIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None LSIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None LSNZ [m].i Description Operation Affected flag(s) Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None Rev. 1.30 198 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU LSNZ [m] Description Operation Affected flag(s) Skip if Data Memory is not 0 If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m] ≠ 0 None LSUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C, SC, CZ LSUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C, SC, CZ LSWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None LSWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None LSZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None LSZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None Rev. 1.30 199 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU LSZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None LTABRD [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None LTABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None LITABRD [m] Description Operation Increment table pointer low byte first and read table to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None LITABRDL [m] Description Operation Affected flag(s) Increment table pointer low byte first and read table (last page) to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None LXOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z LXORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z Rev. 1.30 200 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.30 201 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU 48-pin LQFP (7mm×7mm) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.354 BSC — B — 0.276 BSC — C — 0.354 BSC — D — 0.276 BSC — E — 0.020 BSC — F 0.007 0.009 0.011 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 ― 0.008 α 0° ― 7° Symbol Rev. 1.30 Dimensions in mm Min. Nom. Max. A — 9.00 BSC — B — 7.00 BSC — C — 9.00 BSC — D — 7.00 BSC — E — 0.50 BSC — F 0.17 0.22 0.27 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° ― 7° 202 June 19, 2014 HT66FV240 Wireless Voice Flash 8-Bit MCU Copyright© 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.30 203 June 19, 2014