HS-81C55RH, HS-81C56RH Radiation Hardened 256 x 8 CMOS RAM March 1996 Features Description • Devices QML Qualified in Accordance with MIL-PRF-38535 The HS-81C55/56RH are radiation hardened RAM and I/O chips fabricated using the Intersil radiation hardened SelfAligned Junction Isolated (SAJI) silicon gate technology. Latch-up free operation is achieved by the use of epitaxial starting material to eliminate the parasitic SCR effect seen in conventional bulk CMOS devices. • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95818 and Intersil’ QM Plan • Radiation Hardened EPI-CMOS - Parametrics Guaranteed 1 x 105 RAD(Si) - Transient Upset > 1 x 108 RAD(Si)/s - Latch-Up Free > 1 x 1012 RAD(Si)/s The HS-81C55/56RH is intended for use with the HS-80C85RH radiation hardened microprocessor system. The RAM portion is designed as 2048 static cells organized as 256 x 8. A maximum post irradiation access time of 500ns allows the HS-81C55/56RH to be used with the HS-80C85RH CPU without any wait states. The HS-81C55RH requires an active low chip enable while the HS-81C56RH requires an active high chip enable. These chips are designed for operation utilizing a single 5V power supply. • Electrically Equivalent to Sandia SA 3001 • Pin Compatible with Intel 8155/56 • Bus Compatible with HS-80C85RH • Single 5V Power Supply Functional Diagram • Low Standby Current 200µA Max • Low Operating Current 2mA/MHz IO/M • Completely Static Design AD0 - AD7 • Internal Address Latches CE OR CE† 256 x 8 STATIC RAM PORT A 8 PA0 - PA7 PORT B ALE • Two Programmable 8-Bit I/O Ports A B PB0 - PB7 8 RD • One Programmable 6-Bit I/O Port PORT C WR C RESET • Programmable 14-Bit Binary Counter/Timer TIMER CLK • Multiplexed Address and Data Bus 8 TIMER PC0 - PC5 VDD (10V) GND TIMER OUT • Self Aligned Junction Isolated (SAJI) Process †81C55RH = CE 81C56RH = CE • Military Temperature Range -55oC to +125oC Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962R9XXXX01QRC -55oC +125oC MIL-PRF-38535 Level Q 40 Lead SBDIP 5962R9XXXX01VRC -55oC to +125oC MIL-PRF-38535 Level V 40 Lead SBDIP 5962R9XXXX01QXC -55oC to +125oC MIL-PRF-38535 Level Q 42 Lead Ceramic Flatpack 5962R9XXXX01VXC -55oC to +125oC MIL-PRF-38535 Level V 42 Lead Ceramic Flatpack 5962R9XXXX02QRC -55oC to +125oC MIL-PRF-38535 Level Q 40 Lead SBDIP 5962R9XXXX02VRC -55oC to +125oC MIL-PRF-38535 Level V 40 Lead SBDIP 5962R9XXXX02QXC -55oC to +125oC MIL-PRF-38535 Level Q 42 Lead Ceramic Flatpack 5962R9XXXX02VXC -55oC to +125oC MIL-PRF-38535 Level V 42 Lead Ceramic Flatpack to HS1-81C55RH/Sample +25oC Sample 40 Lead SBDIP HS9-81C55RH/Sample +25oC Sample 42 Lead Ceramic Flatpack HS1-81C56RH/Sample +25oC Sample 40 Lead SBDIP HS9-81C56RH/Sample +25oC Sample 42 Lead Ceramic Flatpack CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 Spec Number File Number 518056 3039.1 HS-81C55RH, HS-81C56RH Pinouts 40 LEAD DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T40 TOP VIEW PC3 1 40 VDD PC4 2 39 PC2 TIMER IN 3 38 PC1 RESET 4 37 PC0 PC5 5 36 PB7 TIMER OUT 6 35 PB6 IO / M 7 34 PB5 CE or CE* 8 33 PB4 RD 9 32 PB3 WR 10 31 PB2 ALE 11 30 PB1 *81C55RH = CE 81C56RH = CE AD0 12 29 PB0 AD1 13 28 PA7 AD2 14 27 PA6 AD3 15 26 PA5 AD4 16 25 PA4 AD5 17 24 PA3 AD6 18 23 PA2 AD7 19 22 PA1 GND 20 21 PA0 42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE INTERSIL OUTLINE K42.A TOP VIEW PC3 1 42 VDD PC4 2 41 PC2 TIMER IN 3 40 PC1 RESET 4 39 PC0 PB7 PC5 5 38 TIMER OUT 6 37 PB6 IO/M CE OR CE 7 8 36 35 PB5 RD 9 34 PB3 PB4 WR 10 33 PB2 ALE 11 32 PB1 AD0 12 31 AD1 13 30 AD2 14 29 PB0 PA7 PA6 AD3 15 28 PA5 NC 16 27 AD4 AD5 AD6 17 18 19 26 25 24 NC PA4 AD7 20 23 PA1 GND 21 22 PA0 PA3 PA2 Spec Number 2 518056 HS-81C55RH, HS-81C56RH Pin Description SYMBOL TYPE NAME AND FUNCTION I Reset: Pulse provided by the HS-80C85RH to initialize the system (connect to HS-80C85RH RESET OUT). Input high on this line resets the chip and initializes the three I/O ports to input mode. The width of RESET pulse should typically be two HS-80C85RH clock cycle times. AD0 - AD7 I/O Address/Data: Tri-state Address/Data lines that interface with the CPU lower 8-bit Address/Data Bus. The 8-bit address is latched into the address latch inside the HS-81C55 and HS-81C56RH on the falling edge of ALE. The address can be either for the memory section or the I/O section depending on the IO/ M input. The 8-bit data is either written into the chip or read from the chip, depending on the WR or RD input signal. CE or CE I Chip Enable: On the HS-81C55RH, this pin is CE and is ACTIVE LOW. On the HS-81C56RH, this pin is CE and is ACTIVE HIGH. RD I Read Control: Input low on this line with the Chip Enable active enables and AD0 - AD7 buffers. If IO/ M pin is low, the RAM content will be read out to the AD bus. Otherwise the content of the selected I/O port or command/status registers will be read to the AD bus. WR I Write Control: Input low on this line with the Chip Enable active causes the data on the Address/Data bus to be written to the RAM or I/O ports and command/status register, depending on IO/M. ALE I Address Latch Enable: This control signal latches both the address on the AD0 - AD7 lines and the state of the Chip Enable and IO/M into the chip at the falling edge of ALE. IO/M I I/O Memory: Selects memory if low and I/O and command/status registers if high. RESET PA0 - PA7 (8) I/O Port A: These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the command register. PB0 - PB7 (8) I/O Port B: These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the command register. PC0 - PC7 (8) I/O Port C: These 6 pins can function as either input port, output port, or as control signals for PA and PB. Programming is done through the command register. When PC0 - PC5 are used as control signals, they will provide the following: PC0 - A INTR (Port A Interrupt) PC1 - ABF (Port A Buffer Full) PC2 - A STB (Port A Strobe) PC3 - B INTR (Port B Interrupt) PC4 - B BF (Port B Buffer Full) PC5 - B STB (Port B Strobe) TIMER IN I Timer Input: Input to the counter-timer. TIMER OUT O Timer Output: This output can be either a square wave or a pulse, depending on the timer mode. VDD I Voltage: +5V. GND I Ground: Ground reference. Spec Number 3 518056 Specifications HS-81C55RH, HS-81C56RH Absolute Maximum Ratings Reliability Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC Typical Derating Factor . . . . . . . . . . . . 2mA/MHz Increase in IDDOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC SBDIP Package . . . . . . . . . . . . . . . . . . . . 40.0oC/W 5.0oC/W Ceramic Flatpack Package . . . . . . . . . . . 45.0oC/W 5.0oC/W Maximum Package Power Dissipation at +125oC SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 1.11W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.0mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . 22.2mW/oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . VDD -0.5V to VDD TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETERS SYMBOL GROUP A SUBGROUPS CONDITIONS LIMITS TEMPERATURE MIN MAX UNITS High Input Leakage Current IIH VDD = 5.25V, VIN = 0V, Pin under test = VDD 1, 2, 3 -55oC, +25oC, +125oC - 1 µA Low Input Leakage Current IIL VDD = 5.25V, VIN = 5.25V, Pin under test = 0V 1, 2, 3 -55oC, +25oC, +125oC -1 - µA Low Output Voltage VOL VDD = 5.25V, IOL = 2mA 1, 2, 3 -55oC, +25oC, +125oC - 0.5 V High Output Voltage VOH VDD = 4.75V, IOH = 2mA 1, 2, 3 -55oC, +25oC, +125oC 4.25 - V Static Current IDDSB VDD = 5.25V 1, 2, 3 -55oC, +25oC, +125oC - 200 µA Dynamic Current IDDOP VDD = 5.25V, f = 1MHz 1, 2, 3 -55oC, +25oC, +125oC - 2 mA Functional Tests FT 7, 8A, 8B -55oC, +25oC, +125oC - - - VDD = 4.75V and 5.25V, VIH = VDD-0.5V, VIL = 0.8V NOTE: All devices are guaranteed at worst case limits and over radiation. Dynamic current is proportional to operating frequency (2mA/MHz). TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETERS SYMBOL CONDITIONS LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS Address Latch Setup Time TAL Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC 60 - ns Address Hold Time After Latch TLA Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC 60 - ns Latch to READ/WRITE Control TLC Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC 200 - ns Valid Data Out From Read Control TRD Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC - 250 ns Address Stable to Data Out Valid TAD Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC - 500 ns Latch Enable Width TLL Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC 200 - ns READ/WRITE Control to Latch Enable TCL Notes 1, 4,7 9, 10, 11 -55oC ≤ TA ≤ +125oC 20 - ns READ/WRITE Control Width TCC Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC 9, 10, 11 -55oC 9, 10, 11 -55oC Data In to WRITE Setup Time Data In Hold Time After WRITE TDW TWD Notes 1, 4 Notes 1, 4 250 - ns ≤ TA ≤ +125oC 200 - ns ≤ TA ≤ +125oC 25 - ns Spec Number 4 518056 Specifications HS-81C55RH, HS-81C56RH TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETERS SYMBOL CONDITIONS LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS WRITE to Port Output TWP Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC - 300 ns Port Input Setup Time TPR Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC 50 - ns Port Input Hold Time TRP Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC 15 - ns Strobe to Buffer Full TSBF Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC - 300 ns TSS Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC 150 - ns TRBE Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC - 300 ns Strobe to INTR Off TSI Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC - 300 ns READ to INTR Off TRDI Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC 360 ns Port Setup Time to Strobe TPSS Notes 1, 4, 5 9, 10, 11 -55oC ≤ TA ≤ +125oC 100 - ns Post Hold Time After Strobe TPHS Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC 100 - ns Strobe to Buffer Empty TSBE Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC - 300 ns WRITE to Buffer full TWBF Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC - 300 ns WRITE to INTR Off TWI Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC - 340 ns TIMER-IN to TIMER OUT Low TTL Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC - 300 ns TIMER-IN to TIMER-OUT High TTH Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC - 300 ns TRDE Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC 120 - ns Strobe Width READ to Buffer Empty Data Bus Enable from READ Control TIMER-IN Low Time T1 Notes 1, 4, 6 9, 10, 11 -55oC ≤ TA ≤ +125oC 40 - ns TIMER-IN High Time T2 Notes 1, 4 9, 10, 11 -55oC ≤ TA ≤ +125oC 115 - ns NOTES: 1. All devices guaranteed at worst case limits and over radiation. 2. Operating supply current (IDDOP) is proportional to operating frequency. 3. Output timings are measured with purely capacitive load. 4. For design purposes the limits are given as shown. For compatibility with the 80C85RH microprocessor, the AC parameters are tested as maximums. 5. Parameter tested as part of the functional test. No read and record data available. 6. At low temperature, T1 is measured down to 10ns. If the reading is less than 10ns, the parameter will read 10ns. 7. Read and Record data available on failing data only. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETERS SYMBOL CONDITIONS TEMPERATURE MIN MAX UNITS +25oC - 10 pF Input Capacitance CIN VDD = Open, f = 1MHz, All measurements referenced to device ground TA = I/O Capacitance CI/O VDD = Open, f = 1MHz, All measurements referenced to device ground TA = +25oC - 12 pF Output Capacitance COUT VDD = Open, f = 1MHz, All measurements referenced to device ground TA = +25oC - 10 pF Data Bus Float After READ TRDF VDD = 4.75V -55oC, +25oC, +125oC 10 100 ns TRV VDD = 4.75V -55oC, +25oC, +125oC - 220 ns Recovery Time Between Controls NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. Spec Number 5 518056 Specifications HS-81C55RH, HS-81C56RH Waveforms READ CE (81C55RH) OR CE (81C56RH) IO/M tAD AD0-7 ADDRESS tAL DATA VALID tLA ALE tLL tRIDE tRDF tRD RD tCL tLC tCC tRV WRITE CE (81C55RH) OR CE (81C56RH) IO/M AD0-7 ADDRESS tAL DATA VALID tLA tDW tCL ALE tLL tLC tWD WR tCL tCC tRV Spec Number 6 518056 HS-81C55RH, HS-81C56RH Waveforms (Continued) STROBED INPUT BF tSBF STROBED tSS tRBE tSI INTR tRDI RD tPSS tPHS INPUT DATA FROM PORT STROBED OUTPUT BF tSBE STROBE tSI tWBF INTR tWI WR tWP OUTPUT DATA TO PORT Spec Number 7 518056 HS-81C55RH, HS-81C56RH Waveforms (Continued) BASIC INPUT BASIC INPUT tRP RD RD tWP tPR INPUT INPUT DATA BUS DATA BUS TIMER OUTPUT COUNTDOWN FROM 5 TO 1 LOAD COUNTER CLR 2 1 RELOAD COUNTER CLR 5 4 3 tF 2 1 5 t2 TIMER IN t1 tR TIMER OUT (PULSE) tCYC (NOTE 1) tTL TIMER OUT (SQUARE WAVE) tTH (NOTE 1) tTL tTH NOTE: THE TIMER OUTPUT IS PERIODIC IF IN AN AUTOMATIC RELOAD MODE (M, MODE BIT = 1) Spec Number 8 518056 HS-81C55RH, HS-81C56RH Metallization Topology DIE DIMENSIONS: 222 x 202 x 14 ± 1mil (Die Thickness) METALLIZATION: Type: AlSi Thickness: 11kÅ ± 2kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ Metallization Mask Layout (35)PB6 (36) PB7 (37) PC0 (38) PC1 (39) PC2 (40) VDD (1) PC3 (2) PC4 (3) TIMER IN (4) RESET (5) PC5 HS-81C55RH, HS-81C56RH TIMER OUT (6) IO/M (7) (34) PB5 CE OR CE (8) RD (9) (33) PB4 WR (10) (32) PB3 ALE (11) (31) PB2 (30) PB1 AD0 (12) (29) PB0 (28) PA7 AD1 (13) AD2 (14) PA5 (26) PA4 (25) PA3 (24) PA2 (23) PA1 (22) PA0 (21) AD7 (19) GND (20) AD6 (18) AD5 (17) AD4 (16) AD3 (15) (27) PA6 Spec Number 9 518056 HS-81C55RH, HS-81C56RH Functional Description 7 6 5 TM2 TM1 IEB The HS-81C55RH and 81C56RH contains the following: 4 3 2 1 IEA PC2 PC1 PB 0 PA • 2K Bit Static RAM Organized as 256 x 8 DEFINES PA0 - PA7 • Two 8-Bit I/O Ports (PA and PB) and One 6-Bit I/O Port (PC) 0 = INPUT DEFINES PB0 - PB7 • 14-Bit Timer-Counter The IO/M (IO/Memory Select) pin selects either the five register (Command, Status, PA0 - PA7, PB0 - PB7, PC0 - PC5) or the memory (RAM) portion. The 8-bit address on the Address/Data lines, Chip Enable input CE or CE and IO/M are all latched on-chip at the falling edge of ALE. PB 8 0 = INPUT 1 = OUTPUT 10 = STOP AFTER TC - STOP IMMEDIATELY AFTER PRESENT TC IS REACHED (NOP IF TIMER HAS NOT STARTED) 11 = START - LOAD MODE AND CNT LENGTH AND START IMMEDIATELY AFTER LOADING (IF TIMER IS NOT PRESENTLY RUNNING). IF TIMER IS RUNNING, START THE NEW MODE AND CNT LENGTH IMMEDIATELY AFTER PRESENT TC IS REACHED. TIMER LSB STATUS 6 ENABLE PORT A INTERRUPT 01 = STOP - NOP IF TIMER HAS NOT STARTED; STOP COUNTING IF THE TIMER IS RUNNING PA TIMER MSB 00 = ALT1 11 = ALT2 01 = ALT3 10 = ALT4 00 = NOP - DO NOT AFFECT COUNTER OPERATION TIMER COMMAND PC DEFINES PC0 - PC5 ENABLE PORT B INTERRUPT 8-BIT INTERNAL DATA BUS COMMAND 1 = OUTPUT 8 TIMER MODE FIGURE 3. COMMAND REGISTER BIT ASSIGNMENT FIGURE 1. INTERNAL REGISTERS Reading the Status Register The status register consists of seven latches, one for each bit six (0-5) for the status of the ports and one (6) for the status of the timer. CE (81C55RH) OR CE (81C56RH) The status of the timer and the I/O section can be polled by reading the Status Register (Address XXXXX000). Status word format is shown in Figure 4. Note that you may never write to the status register since the command register shares the same I/O address and the command register is selected when a write to that address is issued. IO/M AD0 - AD7 ALE ADDRESS DATA VALID AD7 AD6 AD5 AD4 INTE TIMER B B BF AD2 AD1 AD0 INTR INTE B A AD3 A BF INTR A RD OR WR FIGURE 2. ON-BOARD MEMORY READ/WRITE CYCLE PORT A INTERRUPT REQUEST Programming of the Command Register PORT A BUFFER FULL/EMPTY (INPUT/OUTPUT) The command register consists of eight latches. Four bits (03) define the mode of the ports, two bit (4-5) enable or disable the interrupt from port C when it acts as control port, and the last two bits (6-7) are for the timer. PORT A INTERRUPT ENABLE PORT B INTERRUPT REQUEST PORT B BUFFER FULL/EMPTY (INPUT/OUTPUT) The command register contents can be altered at anytime by using the I/O address XXXXX000 during a WRITE operation with the Chip Enable active and IO/M = 1. The meaning of each bit of the command byte is defined in Figure 3. The contents of the command register may never be read. PORT B INTERRUPT ENABLE TIMER INTERRUPT (THIS BIT IS LATCHED HIGH WHEN TERMINAL COUNT IS REACHED, AND IS RESET TO LOW READING OF THE C/S REGISTER & BY HARDWARE RESET). FIGURE 4. STATUS REGISTER BIT ASSIGNMENT Spec Number 10 518056 HS-81C55RH, HS-81C56RH Input/Output Section When the ‘C’ port is programmed to either ALT3 or ALT4, the control signals for PA and Pb are initialized as follows: : The I/O section of the HS-81C55RH and HS-81C56RH consists of five registers: (See Figure 5) CONTROL INPUT MODE OUTPUT MODE BF Low Low INTR Low High STB Input Control Input Control • Command/Status Register (C/S) - Both register are assigned the address XXXXX000. The C/S address serves the dual prupose. When the C/S registers are selected during WRITE operation, a command is written into the command register. The contents of this register are not accessible through the pins. I/O ADDRESS† A7 A6 A5 A4 A3 A2 A1 A0 When the C/S (XXXXX000) is selected during a READ operation, the status information of the I/O ports and the timer becomes available on the AD0 - AD7 lines. • PA Register - This register can be programmed to be either input or output ports depending on the status of the contents of the C/S Register. also depending on the command, this port can operate in either the basic mode or the strobed mode (See timing diagram). the I/O pins assigned in relation to this register are PA0 - PA7. The address of this register is XXXXX001. • PB Register - This register functions the same as PA Register. the I/O pins assigned are PB0 - PB7. The address of this register is XXXXX010 • PC Register - This register has the address XXXXX011 and contains only 6 bits. The 6 bits can be programmed to be either input ports, output ports or as control signals for PA and PB by properly programming the AD2 and AD3 bits of the C/S register. SELECTION X X X X X 0 0 0 Interval Command/ Status Register X X X X X 0 0 1 General Purpose I/O Port A X X X X X 0 1 0 General Purpose I/O Port B X X X X X 0 1 1 General Purpose I/O or Control Port C X X X X X 1 0 0 Low-Order 8 Bits of Timer Count X X X X X 1 0 1 High 6 Bits of Timer Count and 2 Bits of Timer Mode † I/O Address must be qualified by CE = 1(81C56RH) or CE = 0(81C55RH) and IO/M = 1 in order to select the appropriate register. X = Don’t Care FIGURE 5. I/O PORT AND TIMER ADDRESSING SCHEME Figure 6 shows how I/O Ports A and B are structured within the HS-81C55RH and HS-81C56RH. When PC0 - PC5 is used as a control port, 3 bits are assigned for Port A and 3 for Port B. The first bit is an Interrupt that the HS-81C55RH and HS-81C56RH sends out. The second is an output signal indicating whether the buffer is full or empty, and the third is an input pin to accept a strobe for the strobed input mode. (See Table 1). Note in the diagram that when the I/O ports are programmed to be output ports, the contents of the output ports can still be read by a READ operation when appropriately addressed. HS-81C55RH AND HS-81C56RH ONE BIT OF PORT A OR PORT B D OUTPUT LATCH INTERNAL DATA BUS CLK (1) (2) (3) (4) Q CLR OUTPUT MODE MULTIPLEXER SIMPLE INPUT CONTROL STROBED INPUT = 1 FOR OUTPUT MODE = 0 FOR INPUT MODE PA/PB PIN WRITE PORT MUX (1) MODE (4) (2) (3) NOTES: LATCH READ PORT Q 1. READ Port = (IO/M = 1)(RD = 0)(CE Active) (Port Address Selected) D CLK 2. WRITE Port = (IO/M = 1)(wr = 0)(CE Active) (Port Address Selected) STB FIGURE 6. HS-81C55RH AND HS-81C56RH PORT FUNCTION Spec Number 11 518056 HS-81C55RH, HS-81C56RH The outputs of the HS-81C55/56RH are “glitch-free” meaning that you can write a “1” to a bit position that was previously “1” and the level at the output pin will not change. TO HS-80C85RH RST INPUT PORT A Note also that the output latch is cleared when the port enters the input mode. the output latch cannot be loaded by writing to the port if the port is in theinput mode. The result is that each time a port mode is changed from input to output, the output pins will go low. When the HS-81C55/56RH is RESET, the output latches are all cleared and all 3 ports enter the input mode. OUTPUT PORT A A INTR (SIGNAL DATA RECEIVED) A BF (SIGNALS DATA READY) A STB (ACKNOWL. DATA RCV’D) PORT C TO/FROM PERIPHERAL INTERFACE B STB (LOAD PORT B LATCH) B BF (SIGNALS BUFFER IS FULL) When in the ALT1 or ALT2 modes, the bits of Port C are structured like the diagram above in the simple input or output mode, respectively. B INTR (SIGNALS BUFFER READY FOR READING) TO INPUT PORT (OPTIONAL) INPUT PORT B Reading from an input port with nothing connected to the pins will provide unpredictable results. TO HS-80C85RH RST INPUT Figure 7 shows how the HS-81C55/56RH I/O ports might be configured in a typical system. FIGURE 7. EXAMPLE: COMMAND REGISTER = 00111001 Timer Section The timer is a 14 bit down counter that counts the TIMER IN pulses and provides either a square wave or pulse when terminal count (TC) is reached. The timer has the I/O address XXXXX100 for the low order byte of the register and the I/O address XXXXX101 for the high order byte of the register. (See Figure 5). 7 6 5 4 M2 M1 T13 T12 TIMER MODE To program the timer, the COUNT LENGTH REG is loaded first, one byte at a time, by selecting the timer addresses. Bits 0-13 of the high order count register will specify the length of the next count and bits 14-15 of the high order register will specify the timer output mode (see Figure 8). The value loaded into the count length register can have any value from 2H through 3FFH in Bits 0-13. 3 2 T11 T10 1 T9 0 T8 MSB OF CNT LENGTH 7 6 5 4 3 2 1 0 T7 T6 T5 T4 T3 T2 T1 T0 LSB OF CNT LENGTH FIGURE 8. TIMER FORMAT TABLE 1. PORT CONTROL ASSIGNMENT PIN ALT1 ALT2 ALT3 ALT4 PC0 Input Port Output Port A INTR (Port A Interrupt) A INTR (Port A Interrupt) PC1 Input Port Output Port A BF (Port A Buffer Full) A BF (Port A Buffer Full) PC2 Input Port Output Port A STB (Port A Strobe) A STB (Port A Strobe) PC3 Input Port Output Port Output Port B INTR (Port B Interrupt) PC4 Input Port Output Port Output Port B BF (Port B Buffer Full) PC5 Input Port Output Port Output Port B STB (Port B Strobe) Spec Number 12 518056 HS-81C55RH, HS-81C56RH There are four modes to choose from: M2 and M1 define the timer mode, as shown in Figure 9. TIMER OUT WAVEFORMS: 4 START TERMINAL COUNT COUNT MODE BITS (TERMINAL COUNT) 5 M2 M1 0 0 1. SINGLE SQ. WAVE 0 1 2. CONTINUOUS SQ. WAVE 1 0 3. SINGLE PULSE ON TERM. COUNT 1 1 4. CONTINUOUS PULSES FIGURE 10. ASYMMETRICAL SQUARE-WAVE OUTPUT RESULTING FROM COUNT OF 9 The counter in the HS-81C55/56RH is not initialized to any particular mode or count when hardware RESET occurs, but RESET does stop the counting. Therefore, counting cannot begin following RESET until a START command is issued via the C/S register. Please note that the timer circuit on the HS-81C55/56RH chip is designed to be a square-wave timer, not an event counter. To achieve this, it counts down by twos twice in completing one cycle. Thus, its registers do not contain values directly representing the number of TIMER IN pulses received. You cannot load an initial value of 1 into the count register and cause the timer to operate, as its terminal count value is 10 (binary) or 2 (decimal). (For the detection of single pulses, it is suggested that one of the hardware interrupt pins on the HS-80C85RH be used.) After the timer has started counting down, the values residing in the count registers can be used to calculate the actual number of TIMER IN pulses required to complete the timer cycle if desired. To obtain the remaining count, perform the following operations in order: FIGURE 9. TIMER MODES Bits 6-7 (TM2 and TM1) of command register contents are used to start and stop the counter. there are four commands to choose from: TM2 TM1 0 0 NOP - Do not affect counter operation 0 1 STOP-NOP - If timer has not started; stop counting if the timer is running 1 0 STOP AFTER TC - Stop immediately after present TC is reached (NOP if timer has not started) 1 1 START - Load mode and CNT length and start immediately after loading (if timer is not presently running). If timer is running, start the new mode and CNT length immediately after present TC is reached. 1. Stop the count 2. Read in the 16 bit value from the count length registers 3. Reset the upper two mode bits 4. Reset the carry and rotate right one position all 16 bits through carry 5. If carry is set, add 1/2 of the full original count (1/2 full count - 1 if full count is odd). Note that while the counter is counting, you may load a new count and mode into the count length registers. Before the new count and mode will be used by the counter, you must issue a START command to the counter. This applies even thought you may only want to change the count and use the previous mode. NOTE: If you started with an odd count and you read the count length register before the third count pulse occurs, you will not be able to discern whether one or two counts has occurred. Regardless of this, the HS-81C55/56RH always counts out the right number of pulses in generating the TIMER OUT waveforms. In case of an odd-numbered count, the first half-cycle of the squarewave output, which is high, is one count longer than the second (low) half-cycle, as shown in Figure 10. Spec Number 13 518056 HS-81C55RH, HS-81C56RH Ceramic Metal Seal Flatpack Packages (Flatpack) E 1 K42.A TOP BRAZED 42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE N INCHES e MILLIMETERS A A D b E1 SYMBOL MIN MAX MIN MAX NOTES A - 0.100 - 2.54 - b 0.017 0.025 0.43 0.64 - b1 0.017 0.023 0.43 0.58 - S1 c L c1 C A Q E2 c1 LEAD FINISH BASE METAL (c) M M (b) 0.013 0.18 0.33 - 0.010 0.18 0.25 3 D 1.045 1.075 26.54 27.31 16.00 16.51 - 17.27 3 E 0.630 0.650 E1 - 0.680 E2 0.530 0.550 e b1 0.007 0. 007 13.46 0.050 BSC 13.97 - 1.27 BSC 11 k - - - - - L 0.320 0.350 8.13 8.89 - Q 0.045 0.065 1.14 1.65 8 S1 0.000 - 0.00 - 6 M - 0.0015 - SECTION A-A NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. N 42 0.04 - 42 Rev. 0 6/17/94 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 11. The basic lead spacing is 0.050 inch (1.27mm) between center lines. Each lead centerline shall be located within ±0.005 inch (0.13mm) of its exact longitudinal position relative to lead 1 and the highest numbered (N) lead. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Spec Number 14 518056