A/D, D/C Converters for Image Signal Processing MN65752H Low Power 8-Bit, 2-Channel CMOS A/D Converter for Image Processing Pin Assignment Features Maximum conversion rate: 20 MSPS (min.) Linearity error: ±0.9 LSB (typ.) Differential linearity error: ±0.5 LSB (typ.) Power supply voltage: 3.6 V or 2.6 V Power consumption: 50 mW (typ.) (fCLK=16 MHz) 36 35 34 33 32 31 30 29 28 27 26 25 VRBSO VRBB DVDD DVSS NPOWDB DVSS CLK NOE DB7 DB6 DB5 DB4 The MN65752H is an 8-bit, 2-channel CMOS analogto-digital converter for image processing applications. It uses a half flash structure based on chopper comparators and achieves both high speed and low power consumption with multiplexing. It provides separate power supply pins for the circuits driving the low-voltage digital output pins. VRTSB VRTB AVDD VINB AVSS AVDD AVSS AVSS VINA AVDD VRTA VRTSA 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 Overview DB3 DB2 DB1 DB0 DVDD DVDDL DVDDL DVDD DA7 DA6 DA5 DA4 Digital video equipment Digital image processing equipment VRBSA VRBA DVDD DVSS NPOWDA DVSS TEST1 TEST2 DA0 DA1 DA2 DA3 Applications Digital television receivers (TOP VIEW) QFH048-P-0707 1 2 DA3 DA2 DA1 12 11 10 9 Clock generator (LSB)DA0 45 8 44 (Channel A) Encoder (4 bits) Lower comparator (4 bits) Reference resistor (Channel B) Encoder (4 bits) 38 DB1 Data latch 23 Clock generator 22 Lower comparator (4 bits) Reference resistor 40 TEST2 47 7 VRTA TEST1 AVDD 6 VINA DVSS AVSS 5 43 NPOWDA 39 4 AVSS Upper comparator (4 bits) AVDD DVSS 42 Upper comparator (4 bits) 41 3 AVDD DVDD AVSS Encoder (4 bits) VINB Encoder (4 bits) VRTB 2 1 VRTSB VRBA VRBSA 25 26 27 28 29 30 31 32 33 34 35 36 DB4 DB5 DB6 DB7(MSB) NOE CLK DVSS NPOWDB DVSS DVDD VRBB VRBSB MN65752H A/D, D/C Converters for Image Signal Processing Block Diagram 24 DB3 37 DB2 21 20 19 16 46 Data latch 14 13 DB0(LSB) DVDD DVDD 18 DVDD 17 DVDD DA7(MSB) 15 DA6 DA5 VRTSA 48 DA4 A/D, D/C Converters for Image Signal Processing MN65752H Pin Descriptions Pin No. 1 Symbol VRBSA Function Description Reference voltage power supply (BOTTOM) 2 VRBA Reference voltage input (BOTTOM) 3 DVDD Power supply for digital circuits 4 DVSS 5 NPOWDA Ground for digital circuits Power down mode selection 6 DVSS 7 TEST1 Test mode selection Ground for digital circuits 8 TEST2 Test mode selection 9 DA0 Digital code output (LSB) 10 DA1 Digital code output 11 DA2 Digital code output 12 DA3 Digital code output 13 DA4 Digital code output 14 DA5 Digital code output 15 DA6 Digital code output 16 DA7 Digital code output (MSB) 17 DVDD Power supply for digital circuits 18 DVDDL Power supply for low-voltage digital outputs 19 DVDDL Power supply for low-voltage digital outputs 20 DVDD Power supply for digital circuits 21 DB0 Digital code output (LSB) 22 DB1 Digital code output 23 DB2 Digital code output 24 DB3 Digital code output 25 DB4 Digital code output 26 DB5 Digital code output 27 DB6 Digital code output 28 DB7 Digital code output (MSB) 29 NOE Digital output enable 30 CLK Sampling clock 31 DVSS Ground for digital circuits 32 NPOWDB 33 DVSS Ground for digital circuits 34 DVDD Power supply for digital circuits 35 VRBB Reference voltage input (BOTTOM) 36 VRBSB Reference voltage power supply (BOTTOM) 37 VRTSB Reference voltage power supply (TOP) 38 VRTB Reference voltage input (TOP) 39 AVDD Power supply for analog circuits 40 VINB Ground for analog circuits Power down mode selection 3 MN65752H A/D, D/C Converters for Image Signal Processing Pin Descriptions (continued) Pin No. 41 Symbol AVSS Function Description Ground for analog circuits 42 AVDD Power supply for analog circuits 43 AVSS Ground for analog circuits 44 AVSS Ground for analog circuits 45 VINA Analog signal input 46 AVDD Power supply for analog circuits 47 VRTA Reference voltage input (TOP) 48 VRTSA Reference voltage power supply (TOP) Absolute Maximum Ratings Ta=25˚C Parameter Power supply voltage Symbol VDD Rating – 0.3 to +7.0 Unit V Power supply voltage for digital output circuits DVDDL – 0.3 to VDD+0.3 V Input voltage VI – 0.3 to VDD+0.3 V Output voltage VO – 0.3 to VDD+0.3 V Operating ambient temperature Topr –20 to +70 ˚C Storage temperature Tstg –55 to +125 ˚C Recommended Operating Conditions VDD=AVDD=DVDD=3.6V, DVDDL=2..6V, VSS=AVSS=DVSS=0V, Ta=25˚C Parameter Power supply voltage Symbol VDD min 3.30 typ 3.60 max 5.25 Unit V Power supply voltage for digital output circuits DVDDL 2.50 2.60 5.25 V Digital input "H" level VIH VDD × 0.55 VDD V voltage "L" level VIL VSS VDD × 0.2 V Reference voltage "H" level VRT "L" level VRB VSS "H" level pulse width tWH 20 ns "L" level pulse width tWL 20 ns VAIN VSS Clock Analog input voltage Electrical Characteristics Parameter Power consumption 2.80 4 V VDD=AVDD=DVDD=3.6V, DVDDL=2.6V, AVSS=DVSS=0V, Ta=25˚C Symbol Conditions PC fCLK= 16 MSPS min RES Linearity error V V VDD (not including reference current) Resolution VDD 1.30 typ max Unit 50 90 mW ±0.9 ±1.8 LSB ±0.5 ±1.0 8 EL fCLK=20MSPS Differential linearity error ED VRT=2.8V, VRB=1.3V Maximum conversion rate FC(max.) bit 20 LSB MSPS Clock frequency fCLK 1 20 MHz Analog input dynamic range DR 1.5 VRT –VRB V Output "H" level IOH VOH=DVDDL– 0.8V current "L" level IOL VOL=0.4V 1.5 Output delay time td CL=20pF 10 Analog input capacitance CI –1.5 mA mA 25 15 40 ns pF A/D, D/C Converters for Image Signal Processing MN65752H Timing Chart The chip samples the analog input at the falling edge of the clock signal and provides the corresponding digital output 2.5 clock cycles later at the rising edge of the clock signal. tWH tWL Clock Analog input Data output N N–3 N+1 N–2 N+2 N+3 N–1 N N+4 N+1 td(25ns) Note: The circles indicate analog signal sampling points. 5 MN65752H A/D, D/C Converters for Image Signal Processing Package Dimensions (Unit:mm) QFH048-P-0707 9.0±0.2 7.0±0.2 36 25 24 9.0±0.2 7.0±0.2 (0.75) 37 13 48 1 0.5 (0.75) 12 0.2±0.1 0.1 SEATING PLANE 6 0.1±0.1 0.15 +0.10 -0.05 2.9 max. 2.5±0.2 (1.0) 0.5±0.2 0 to 10°