HI2303 Data Sheet December 1998 File Number 4106.2 Triple 8-Bit, 50 MSPS, Video A/D Converter with Clamp Function Features The HI2303 is a highly integrated 8-bit, 3-channel analog-todigital converter that is designed for component (like RGB) digitizing applications. The internal DC Restore (video clamp) function and voltage reference simplifies system design and saves board space. The HI2303 can digitize RGB, YUV, YIQ and any other analog component color signals used in video systems. The variety of sub-sampling modes is compatible with RGB, YUV and YIQ color systems where 4:4:4, 4:2:2 and 4:1:1 data reduction is needed. The 2-step architecture boasts, low power operation, and excellent video performance. • Low Power Consumption (at 50 MSPS Typ) (Reference Current Excluded) . . . . . . . . . . . . . . . .500mW • Resolution 8-Bit 1/2 LSB (DL) Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE HI2303JCQ -40 to 85 80 Ld MQFP HI2303EVAL 25 Evaluation Kit PKG. NO. • Synchronizing Digital Clamp Function • Clamp ON/OFF Function • Reference Voltage Self-Bias Circuit • Input CMOS/TTL Compatible • Three-State TTL Compatible Output • Single 5V Power Supply or Dual 5V or 3.3V Power Supplies • Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . .15pF • Different Digital Output Multiplex Format - 4:4:4 - 4:2:2 - 4:1:1 • Direct Replacement for Sony CXD2303 Q80.14x20-S Applications • Video Digitizing (Composite and Y-C) • LCD Projectors • LCD Panels • RGB Graphics Processing Pinout AVSS DVDD DVDD TGR A7 (MSB) A6 A5 A4 A3 A2 A1 A0 (LSB) DVSS DVSS B7 (MSB) B6 B5 B4 B3 B2 B1 B0 (LSB) DVDD DVDD HI2303 (MQFP) TOP VIEW 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 C7 (MSB) C6 C5 C4 C3 C2 C1 C0 (LSB) DVSS DVSS CRTS CRT AVDD CIO CIN AVSS AVDD AVDD TEST XAOE XBOE XCOE CTL0 CTL1 CTL2 SY SEL CLK CLP REF0 REF1 REF2 REF3 CLE TEST AVSS AVSS AVDD CRBS CRB ARBS ARB AVSS AIN AIO AVDD ART ARTS BRTS BRT AVDD BIO BIN AVSS BRB BRBS 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HI2303 AVDD AVDD AVDD AVDD AVDD AVDD DVDD DVDD DVDD DVDD DVSS DVSS DVSS Functional Block Diagram 30 35 41 42 62 68 22 23 1 2 11 12 71 72 DVSS ARTS 32 8 ART 31 13 A0 (LSB) A-CH 8-BIT ADC AIN 28 ARB 26 8-BIT DAC AIO 29 20 A7 (MSB) DIGITAL CLAMP CIRCUIT 8 ARBS 25 44 XAOE BRTS 33 8 BRT 34 DATA SELECTOR + LATCH B-CH 8-BIT ADC BIN 37 BRB 39 8 BRBS 40 BIO DIGITAL CLAMP CIRCUIT 8-BIT DAC 36 73 C0 (LSB) 8 C-CH 8-BIT ADC CIN 66 80 C7 (MSB) CRB 64 DIGITAL CLAMP CIRCUIT 8 CRBS 63 8-BIT DAC CIO 67 10 B7 (MSB) 45 XBOE CRTS 70 CRT 69 3 B0 (LSB) 46 XCOE 21 TGR AVSS 24 47 CTL0 AVSS 27 48 CTL1 DIGITAL CONTROL DECODER AVSS 38 49 CTL2 2 54 57 REF0 REF3 59 43 TEST 51 TEST 53 SEL 58 CLE 52 CLK AVSS AVSS AVSS 60 61 65 CLP 50 SY HI2303 Pin Description PIN NO. SYMBOL EQUIVALENT CIRCUIT 1, 2, 22, 23 DVDD - 13 to 20 3 to 10 73 to 80 A0 to A7 B0 to B7 C0 to C7 O 21 TGR O DESCRIPTION Digital Power Supply. +5V or +3.3V. Digital output. A0 (LSB) to A7 (MSB) B0 (LSB) to B7 (MSB) C0 (LSB) to C7 (MSB). DVDD Trigger Output DVSS 11, 12, 71, 72 DVSS - Digital Ground. 24, 27, 38, 60, 61, 65 AVSS - Analog Ground. 25 40 63 ARBS BRBS CRBS - AVDD RTS 32 RB 33 26 39 64 ARB BRB CRB - 31 34 69 ART BRT CRT - 26 70 ARTS BRTS CRTS - 28 37 66 AIN BIN CIN I 64 RREF 34 25 RB 69 32 33 70 Reference Voltage (Bottom). 39 RT 31 Shorting the RBS pins to AVSS generates voltage of approximately 0.6V at the ARB, BRB and CRB pins. 40 RT 63 AVSS Reference Voltage (Top). RBS Shorting the RTS pins to AVDD generates voltage of about 2.5V at the ART, BRT and CRT pins. Analog Input. AVDD 28 37 66 AVSS 29 36 67 AIO BIO CIO O 29 200Ω 36 67 AVSS 3 Analog Output. These pins are the D/A converter outputs which comprise the digital clamp circuit. AVDD HI2303 Pin Description (Continued) PIN NO. SYMBOL EQUIVALENT CIRCUIT DESCRIPTION 30, 35, 41, 42, 62, 68 AVDD 43 59 TEST I Normally open. Pull-down resistors are incorporated. 44 45 46 XAOE XBOE XCOE I Output Enable Input. When these pins are Low, data is output from the digital output pins. When these pins are High, the digital output pins are High impedance. The A, B and C Channels can be controlled separately. Also, these pins are not synchronized with the clock signal. Pull-down resistors are incorporated. Analog +5V Power Supply. AVDD 47 48 49 CTL0 CTL1 CLT2 I 50 SY I Determines the digital output mode. See the Mode tables and Timing Charts. Pull-down resistors are incorporated. AVSS 51 SEL I 52 CLK I Controls the digital output mode switching timing. The mode is switched by detecting the transition point where this pin changes from Low to High. See the Mode Tables and Timing Charts for details. A pull-down resister is incorporated. Controls the CLP signal polarity. When this pin is Low, CLP is High active. When this pin is High, CLP is Low active. This pin has a built-in pulldown resistor. AVDD Clock Input. A pull-down resistor is incorporated. 53 CLP I Clamp Pulse Input. The polarity can be set to either High or Low by setting SEL. This pin has a built-in pull-down resistor. 54 55 56 57 REF0 REF1 REF2 REF3 I Determines the clamp circuit reference data. See the mode tables for the set data. These pins are not synchronized with the clock input signal. Pull-down resistors are incorporated. AVSS 58 CLE I 4 Clamp Enable. When this pin is Low the clamp circuit does not operate. When this pin is High, the clamp circuit operates. A pull-down resistor is incorporated. HI2303 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage (AVDD, DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Input Voltage (VIN , All Pins). . . . . . . . . . . . VDD +0.5V to VSS -0.5V Output Voltage (VD, Digital) . . . . . . . . . . . . VDD +0.5V to VSS -0.5V Operating Conditions Supply Voltage: AVDD, AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V DVDD, DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0V to 5.5V |DVSS , AVSS| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mV to 100mV Reference Input Voltage: VARB , VBRB , VCRB . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V or More VART, VBRT, VCRT . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V or Less Analog Input: AIN , BIN , CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.7VP-P or More Clock Pulse Width: tPW1 , tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . 9ns (Min) to 1.1ms (Max) Ambient Temperature (TOPR) . . . . . . . . . . . . . . . . . . -40oC to 85oC Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range (TSTG). . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. fC = 50 MSPS, AVDD = 5V, DVDD = 3.0V to 5.0V, VRB = 0.5V, VRT = 2.5V, TA = 25oC Electrical Specifications PARAMETER SYMBOL ANALOG CHARACTERISTICS TEST CONDITIONS MIN TYP MAX UNITS 0.5 - 50 MSPS DVDD = 3V to 5.5V Conversion Rate fC Analog Input Band (-1dB) BW Differential Non-Linearity Error ED Integral Non-Linearity Error EL Offset Voltage (Note 2) AVDD = 4.75V to 5.25V, TA = -20oC to 75oC, VIN = 0.5V to 2.5V, fIN = 1kHz Triangular Wave Envelope -1dB - 60 - MHz RIN = 33Ω -3dB - 100 - MHz - ±0.3 ±0.5 LSB - ±0.7 ±1.5 LSB End Point EOT Potential Difference to ART , BRT , CRT -50 - -10 mV EOB Potential Difference to ARB , BRB , CRB 0 - 40 mV Differential Gain Error DG NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS - 3 - % Differential Phase Error DP - 1.5 - Deg Cross Talk CT - 52 - dB Ref Data = 00010000 - - ±1 LSB Ref Data = 10000000 - - ±1 LSB fIN = 150kHz - 43 - dB fIN = 500kHz - 42 - dB fIN = 1MHz - 42 - dB fIN = 3MHz - 41 - dB fIN = 10MHz - 38 - dB fIN = 20MHz - 35 - dB Clamp Offset Voltage EOC Signal To Noise Ratio SNR 5 fIN = 1MHz Sinewave VIN = DC CIN = 10µF tPCW = 2.75µs fCLK = 14.3MHz fCLP = 15.75kHz HI2303 fC = 50 MSPS, AVDD = 5V, DVDD = 3.0V to 5.0V, VRB = 0.5V, VRT = 2.5V, TA = 25oC Electrical Specifications PARAMETER SYMBOL Spurious Free Dynamic Range DC CHARACTERISTICS Supply Current SFDR TEST CONDITIONS MIN TYP MAX UNITS fIN = 150kHz - 59 - dB fIN = 500kHz - 59 - dB fIN = 1MHz - 55 - dB fIN = 3MHz - 49 - dB fIN = 10MHz - 44 - dB fIN = 20MHz - 41 - dB DVDD = 5V - 80 100 mA DVDD = 3.3V - 70 90 mA - 5 10 mA DVDD = 5V - 70 90 mA DVDD = 3.3V - 60 80 mA - 5 10 mA DVDD = 5V or 3.3V Both IAD + IDD Analog IAD Digital IDD Both IAD + IDD Analog IAD Digital IDD NTSC Ramp Wave Input CLE = High fCLP = 15.75kHz NTSC Ramp Wave Input CLE = Low Reference Current IREF For Every Channel 4.1 5.4 7.7 mA Reference Resistance (VRT to VRB) RREF For Every Channel 260 370 480 Ω Short AVSS and ARBS , BRBS , CRBS 0.50 0.54 0.58 V VRT - VRB Short AVDD and ARTS , BRTS , CRTS 1.8 1.92 2.04 V fCLK = 50MHz - 13 - kΩ fCLK = 35MHz - 16 - kΩ fCLK = 20MHz - 30 - kΩ Self Bias VRB Analog Input Resistance RIN Input Capacitance Output Capacitance Digital Input Voltage VIN CA11 AIN , BIN , CIN , VIN = 1.5V + 0.07VRMS - 15 - pF CA12 ARTS , ART , ARB , ARBS , BRTS , BRT , BRB , BRBS , CRTS , CRT , CRB , CRBS - - 9 pF CDIN Digital Input Pin - - 9 pF CAO AIO , BIO , CIO - - 11 pF CDO Digital Output Pin - - 11 pF VIH AVDD = 4.75V to 5.25V, DVDD = 3V to 5.5V 2.2 - - V - - 0.8 V -40 - 240 µA -40 - 240 µA VIL Digital Input Current IIH VI = 0V to AVDD IIL Digital Output Current IOH IOL IOH IOL IOZH IOZL 6 XOE = 0V DVDD = 5V VOH = DVDD - 0.8V - - -2 mA VOL = 0.4V 4 - - mA XOE = 0V DVDD = 3.3V VOH = DVDD - 0.8V - - -1.2 mA VOL = 0.4V 2.4 - - mA XOE = 3V DVDD = 3V to 5.5V VOH = DVDD -40 - 40 mA VOL = 0V -40 - 40 mA HI2303 fC = 50 MSPS, AVDD = 5V, DVDD = 3.0V to 5.0V, VRB = 0.5V, VRT = 2.5V, TA = 25oC Electrical Specifications PARAMETER SYMBOL Digital Output Voltage VOH VOL VOH VOL TEST CONDITIONS MIN TYP MAX UNITS XOE = 0V DVDD = 5V IOH = -2mA DVDD -0.8 - - V IOL = 4mA - - 0.4 V XOE = 0V DVDD = 3.3V IOH = -1.2mA DVDD -0.8 - - V IOL = -2.4mA - - 0.4 V NOTES: 2. The offset voltage EOB is a potential difference between ARB , BRB , CRB and a point of position where the voltage drops equivalent to 1/2 LSB of the voltage when the output data changes from “00000000” to “00000001”. EOR is a potential difference between ART , BRT , CRT and a potential of point where the voltage rises equivalent to 1/2 LSB of the voltage when the output data changes from “11111111” to “11111110”. (2V + E OT -E OB ) of each channel 3. Full scale input ratio = --------------------------------------------------------------------------------------------------------------------------- -1 x100(%) . Average of (2V + E OT -E OB ) of each channel Timing fC = 50 MSPS, AVDD = 5V, DVDD = 5V or 3.3V, VRB = 0.5V, VRT = 2.5V, TA = 25oC PARAMETER SYMBOL MIN TYP MAX UNIT 4.5 8.5 11 ns 4.5 7.4 11 ns 3.8 10 13.8 ns 3.8 6.7 13.8 ns 4.2 7.1 11.3 ns 4.2 8.0 11.3 ns 3.5 8.4 12.8 ns 3.5 7.2 12.8 ns 3.6 6.8 9.5 ns 3.6 6.3 9.5 ns 2.9 6.8 10.5 ns tPLZ 2.9 6.0 10.5 ns tSD - -3 - ns Set-up Time tS 3.5 - - ns Hold Time tH 4.5 - - ns Pulse Width CLP 2.0 - - Cycles Pulse Width SY 1 - - Cycles Output Data Delay tPLH tPHL TEST CONDITIONS CL = 15pF XOE = 0V tPLH DVDD = 5V DVDD = 3.3V tPHL Three-State Output Enable Time tPZH tPZL RL = 1kΩ CL = 15PF XOE = 0V → 3V tPZH DVDD = 5V DVDD = 3.3V tPZL Three-State Output Disable Time tPHZ tPLZ tPHZ Sampling Delay 7 RL = 1kΩ CL = 15pF XOE = 0V → 3V DVDD = 5V DVDD = 3.3V HI2303 Digital Output The following table shows the relationship between analog input voltage and digital output code. . TABLE 1. I/O CORRESPONDENCE DIGITAL OUTPUT CODE INPUT SIGNAL VOLTAGE VART, VBRT, VCRT • • • • • • VARB , VBRB , VCRB STEP MSB 0 • • 1 1 1 1 LSB 1 1 1 1 • • 127 128 • • 1 0 0 0 0 0 0 0 0 1 1 1 • 1 1 1 1 • • 255 0 0 0 0 0 0 0 0 Test Circuits MEASUREMENT POINT TO OUTPUT PIN DVDD MEASUREMENT POINT RL CL TO OUTPUT PIN CL RL NOTE: CL includes capacitance of probes. FIGURE 1. OUTPUT DATA DELAY MEASUREMENT CIRCUIT FIGURE 2. THREE-STATE MEASUREMENT CIRCUIT +V S2 +5V S1: ON IF A < B S2: ON IF B > A - S1 + 2.5V VDD ART, BRT, CRT -V AIN A BIN CIN DUT HI2303 B 8 + A<B A>B 8 COMPARATOR A8 B8 8 A AIN , BIN , CIN 8 BUFFER ARB , BRB , CRB 8 A1 A0 C “0” DVM B1 B0 + “1” 8 CLK (50MHz) 000...00 111...10 V CLK 0.5V GND CONTROLLER FIGURE 3. INTEGRAL NON-LINEARITY ERROR, DIFFERENTIAL NON-LINEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT 8 FIGURE 4. ANALOG INPUT RESISTANCE TEST CIRCUIT HI2303 Test Circuits (Continued) HI20201 AIN NTSC SIGNAL SOURCE AMP A BIN DUT HI2303 CIN 40 IRE MODULATION IAE 100 B 8 8 TTL 8 8 ↓ 8 VECTOR SCOPE 620 C CLK 2.5V D.G. D.P. -5.2V BURST 0 -40 10-BIT D/A ECL 0.5V SYNC 620 FC TTL ↓ S.G. (CW) -5.2V ECL FIGURE 5. DIFFERENTIAL GAIN AND PHASE ERROR vs TEST CIRCUIT VDD 2.5V AIN , BIN , CIN 0.5V VDD 2.5V ART, BAT, CRT ART, BRT, CRT AIN , BIN , CIN IOL DATA ARB , BRB , CRB OUT A IOL DATA ARB , BRB , CAB OUT 0.5V CLK A CLK VOL OE + - + - VOL OE VSS VSS FIGURE 6. DIGITAL OUTPUT TEST CIRCUIT Description of Operation TABLE 2. SETTING VALUES AND OUTPUT FORMATS Digital Output Format The HI2303 supports eight different output formats as detailed in Table 2. For clarity, these formats are labeled mode 0 to 7. The modes are selected via three control pins labeled CTL0, CTL1 and CTL2. The converter has a latency of five clock cycles which places a constraint on the users ability to change the mode on the fly without corrupting the data within the converter. Please refer to Figure 10. The SY pin is used to control mode changes. This is achieved by using the SY as a reset/latch signal. The Mode is reset when the SY is asserted low. When SY transitions from low to high the control pins are latched internally and mode is changed per timing diagram latency. 9 SETTING OUTPUT CTL2 CTL1 CTLO MODE FORMAT L L L 0 4:4:4 L L H 1 4:2:2 (8FS) L H L 2 4:2:2 (D2) L H H 3 4:2:2 (Special) H L L 4 4:1:1 H L H 5 4:1:1 (Special) H H L 6 Simple Boundary, Scan 1 H H H 7 Simple Boundary, Scan 2 HI2303 Timing Diagrams tr 4ns tf 4ns 3V 90% CLOCK INPUT 1.3V 10% 0V 3V 2.2V DIGITAL INPUT 0.8V 0V tS tH 0.7VDD DIGITAL OUTPUT 0.3VDD tPLH, tPHL FIGURE 7. tr = 4.5ns tf = 4.5ns 3V 90% 1.3V OE INPUT 10% 0V tPZL tPLZ VOH 1.3V OUTPUT 1 10% VOL (DVSS) tPHZ tPZH VOH (DVDD) 90% 1.3V OUTPUT 2 VOL FIGURE 8. TIMING CHART I-2 tPW1 tPW0 CLOCK 1.3V INPUT tSD ANALOG INPUT DIGITAL OUTPUT N N-5 N+1 N-4 N+2 N-3 N+3 N-2 N+4 N-1 N+5 N N+6 N+1 N+7 N+2 N+8 N+9 N+3 N+4 N + 10 N + 11 N+5 N+6 : ANALOG SIGNAL SAMPLING POINT FIGURE 9. 10 HI2303 Timing Diagrams (Continued) N-5 N-4 N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 CLOCK 1.3V INPUT SY CTL2 TO CTL0 MODE N MODE M 2CLK DIGITAL OUTPUT N - 10 N-9 5CLK 5CLK N-8 N-4 PROHIBITED MODE N N-3 N-2 N-1 MODE #0 N N+1 N+2 MODE M FIGURE 10. Mode #0 4:4:4 BIT A73 SAMPLING TIMING (NOTE) ADC CHANNEL ADC CHANNEL OUTPUT A A7 A70 A71 A72 A73 A74 A75 A76 A77 A6 A60 A61 A62 A63 A64 A65 A66 A67 A5 A50 A51 A52 A53 A54 A55 A56 A57 A4 A40 A41 A42 A43 A44 A45 A46 A47 A3 A30 A31 A32 A33 A34 A35 A36 A37 A2 A20 A21 A22 A23 A24 A25 A26 A27 A1 A10 A11 A12 A13 A14 A15 A16 A17 B C DATA A0 A00 A01 A02 A03 A04 A05 A06 A07 B7 B70 B71 B72 B73 B74 B75 B76 B77 B6 B60 B61 B62 B63 B64 B65 B66 B67 B5 B50 B51 B52 B53 B54 B55 B56 B57 B4 B40 B41 B42 B43 B44 B45 B46 B47 B3 B30 B31 B32 B33 B34 B35 B36 B37 B2 B20 B21 B22 B23 B24 B25 B26 B27 B1 B10 B11 B12 B13 B14 B15 B16 B17 B0 B00 B01 B02 B03 B04 B05 B06 B07 C7 C70 C71 C72 C73 C74 C75 C76 C77 C6 C60 C61 C62 C63 C64 C65 C66 C67 C5 C50 C51 C52 C53 C54 C55 C56 C57 C4 C40 C41 C42 C43 C44 C45 C46 C47 C3 C30 C31 C32 C33 C34 C35 C36 C37 C2 C20 C21 C22 C23 C24 C25 C26 C27 C1 C10 C11 C12 C13 C14 C15 C16 C17 C0 C00 C01 C02 C03 C04 C05 C06 C07 TGR Low NOTE: See Figure 9. 11 HI2303 Mode #2 4:2:2 (D2) BIT A73 SAMPLING TIMING (NOTE) ADC CHANNEL ADC CHANNEL OUTPUT A A7 A70 A71 A72 A73 A74 A75 A76 A77 A6 A60 A61 A62 A63 A64 A65 A66 A67 A5 A50 A51 A52 A53 A54 A55 A56 A57 A4 A40 A41 A42 A43 A44 A45 A46 A47 A3 A30 A31 A32 A33 A34 A35 A36 A37 A2 A20 A21 A22 A23 A24 A25 A26 A27 A1 A10 A11 A12 A13 A14 A15 A16 A17 A0 A00 A01 A02 A03 A04 A05 A06 A07 B7 B70 C70 B72 C72 B74 C74 B76 C76 B6 B60 C60 B62 C62 B64 C64 B66 C66 B5 B50 C50 B52 C52 B54 C54 B56 C56 B4 B40 C40 B42 C42 B44 C44 B46 C46 B3 B30 C30 B32 C32 B34 C34 B36 C36 B2 B20 C20 B22 C22 B24 C24 B26 C26 B1 B10 C10 B12 C12 B14 C14 B16 C16 B0 B00 C00 B02 C02 B04 C05 B06 C06 C7 HiZ C6 HiZ C5 HiZ C4 HiZ C3 HiZ C2 HiZ C1 HiZ C0 HiZ LOW HIGH LOW HIGH LOW HIGH LOW B C TGR DATA HIGH HiZ: High Impedance NOTE: See Figure 9. 12 HI2303 Mode #3 4:2:2 (Special) BIT A73 SAMPLING TIMING (NOTE) ADC CHANNEL ADC CHANNEL OUTPUT A A7 A70 A71 A72 A73 A74 A75 A76 A77 A6 A60 A61 A62 A63 A64 A65 A66 A67 A5 A50 A51 A52 A53 A54 A55 A56 A57 A4 A40 A41 A42 A43 A44 A45 A46 A47 A3 A30 A31 A32 A33 A34 A35 A36 A37 A2 A20 A21 A22 A23 A24 A25 A26 A27 A1 A10 A11 A12 A13 A14 A15 A16 A17 A0 A00 A01 A02 A03 A04 A05 A06 A07 B7 B70 C71 B72 C73 B74 C75 B76 C77 B6 B60 C61 B62 C63 B64 C65 B66 C67 B5 B50 C51 B52 C53 B54 C55 B56 C57 B4 B40 C41 B42 C43 B44 C45 B46 C47 B3 B30 C31 B32 C33 B34 C35 B36 C37 B2 B20 C21 B22 C23 B24 C25 B26 C27 B1 B10 C11 B12 C13 B14 C15 B16 C17 B0 B00 C01 B02 C03 B04 C05 B06 C07 C7 HiZ C6 HiZ C5 HiZ C4 HiZ C3 HiZ C2 HiZ C1 HiZ C0 HiZ LOW HIGH LOW HIGH LOW HIGH LOW B C TGR DATA HIGH HiZ: High Impedance NOTE: See Figure 9. 13 HI2303 Mode #1 4:2:2 (8FS) BIT A73 SAMPLING TIMING (NOTE) ADC CHANNEL ADC CHANNEL OUTPUT A A7 A70 A70 A72 A72 A74 A74 A76 A76 A6 A60 A60 A62 A62 A64 A64 A66 A66 A5 A50 A50 A52 A52 A54 A54 A56 A56 A4 A40 A40 A42 A42 A44 A44 A46 A46 A3 A30 A30 A32 A32 A34 A34 A36 A36 A2 A20 A20 A22 A22 A24 A24 A26 A26 A1 A10 A10 A12 A12 A14 A14 A16 A16 A0 A00 A00 A02 A02 A04 A04 A06 A06 B7 B70 B70 C70 C70 B74 B74 C74 C74 B6 B60 B60 C60 C60 B64 B64 C64 C64 B5 B50 B50 C50 C50 B54 B54 C54 C54 B4 B40 B40 C40 C40 B44 B44 C44 C44 B3 B30 B30 C30 C30 B34 B34 C34 C34 B2 B20 B20 C20 C20 B24 B24 C24 C24 B1 B10 B10 C10 C10 B14 B14 C14 C14 B0 B00 B00 C00 C00 B04 B04 C04 C04 C7 B70 A70 C70 A72 B74 A74 C74 A76 C6 B60 A60 C60 A62 B64 A64 C64 A66 C5 B50 A50 C50 A52 B54 A54 C54 A56 C4 B40 A40 C40 A42 B44 A44 C44 A46 C3 B30 A30 C30 A32 B34 A34 C34 A36 C2 B20 A20 C20 A22 B24 A24 C24 A26 C1 B10 A10 C10 A12 B14 A14 C14 A16 C0 B00 A00 C00 A02 B04 A04 C04 A06 HIGH LOW HIGH LOW B C TGR NOTE: See Figure 9. 14 DATA HI2303 Mode #4 4:1:1 BIT A73 SAMPLING TIMING (NOTE) ADC CHANNEL ADC CHANNEL OUTPUT A A7 A70 A71 A72 A73 A74 A75 A76 A77 A6 A60 A61 A62 A63 A64 A65 A66 A67 A5 A50 A51 A52 A53 A54 A55 A56 A57 A4 A40 A41 A42 A43 A44 A45 A46 A47 A3 A30 A31 A32 A33 A34 A35 A36 A37 A2 A20 A21 A22 A23 A24 A25 A26 A27 A1 A10 A11 A12 A13 A14 A15 A16 A17 A0 A00 A01 A02 A03 A04 A05 A06 A07 B7 B70 B60 B30 B10 B74 B54 B34 B14 B6 B60 B40 B20 B00 B64 B44 B24 B04 B5 C10 C50 C30 C10 C74 C54 C34 C14 B4 C60 C40 C20 C00 C64 C44 C24 C04 B3 HiZ B2 HiZ B1 HiZ B0 HiZ C7 HiZ C6 HiZ C5 HiZ C4 HiZ C3 HiZ C2 HiZ C1 HiZ C0 HiZ HIGH LOW B C TGR DATA HIGH LOW HiZ: High Impedance NOTE: See Figure 9. 15 HI2303 Mode #5 4:1:1 (Special) BIT A73 SAMPLING TIMING (NOTE) ADC CHANNEL ADC CHANNEL OUTPUT A A7 A70 A71 A72 A73 A74 A75 A76 A77 A6 A60 A61 A62 A63 A64 A65 A66 A67 A5 A50 A51 A52 A53 A54 A55 A56 A57 A4 A40 A41 A42 A43 A44 A45 A46 A47 A3 A30 A31 A32 A33 A34 A35 A36 A37 A2 A20 A21 A22 A23 A24 A25 A26 A27 A1 A10 A11 A12 A13 A14 A15 A16 A17 A0 A00 A01 A02 A03 A04 A05 A06 A07 B7 B30 B70 C32 C72 B34 B74 C36 C76 B6 B20 B60 C22 C62 B24 B64 C26 C66 B5 B10 B50 C12 C52 B14 B54 C16 C56 B4 B00 B40 C02 C42 B04 B44 C06 C46 B3 HiZ B2 HiZ B1 HiZ B0 HiZ C7 HiZ C6 HiZ C5 HiZ C4 HiZ C3 HiZ C2 HiZ C1 HiZ C0 HiZ HIGH LOW B C TGR DATA HIGH LOW HiZ: High Impedance NOTE: See Figure 9. 16 HI2303 Mode #6, #7 - Simple Boundary Scan 1 and Scan 2 The HI2303 has a simple boundary scan function. TABLE 3. SIMPLE BOUNDARY SCAN OUTPUT DATA BITS MODE #6 MODE #7 A7 B7 C7 H L A6 B6 C6 L H A5 B5 C5 H L A4 B4 C4 L H A3 B3 C3 H L A2 B2 C2 L H A1 B1 C1 H L A0 B0 C0 L H NOTE: CLK and SY must be set. Clamp Function The following two points should be noted when using the digital clamp circuit. - The clamp pulse must be supplied externally. - The clamp circuit is not designed for V cycle clamping. 16 different reference levels can be selected for the digital clamp circuit through a combination of the REF0, REF1, REF2 and REF3 inputs as shown in the table below. Note that the REF0, REF1, REF2 and REF3 input signals are fetched asynchronously with the clock input signal. A IN ( pedestal ) = V RB + ( Binary Code * LSB ) + E OB TABLE 4. SETTING VALUES AND REFERENCE LEVEL SETTING REFERENCE LEVEL CHANNEL A CHANNELS B AND C REF3 REF2 REF1 REF0 MODE DECIMAL BINARY DECIMAL BINARY L L L L 0 16 00010000 128 10000000 L L L H 1 32 00100000 128 10000000 L L H L 2 48 00110000 128 10000000 L L H H 3 64 01000000 128 10000000 L H L L 4 1 00000001 1 00000001 L H L H 5 16 00010000 16 00010000 L H H L 6 32 00100000 32 00100000 L H H H 7 48 00110000 48 00110000 H L L L 8 239 11101111 127 01111111 H L L H 9 223 11011111 127 01111111 H L H L A 207 11001111 127 01111111 H L H H B 191 10111111 127 01111111 H H L L C 254 11111110 254 11111110 H H L H D 239 11101111 239 11101111 H H H L E 223 11011111 223 11011111 H H H H F 207 11001111 207 11001111 17 HI2303 Metric Plastic Quad Flatpack Packages (MQFP/PQFP) D Q80.14x20-S D1 80 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES E E1 e PIN 1 -H- SEATING PLANE A MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.103 0.122 2.60 3.10 - A1 0.002 0.011 0.05 0.30 - B 0.010 0.019 0.25 0.50 5 D 0.926 0.956 23.50 24.30 2 D1 0.784 0.803 19.90 20.40 3, 4 E 0.689 0.720 17.50 18.30 2 E1 0.548 0.566 13.90 14.40 3, 4 L 0.024 0.039 0.60 1.00 - N 80 80 6 e 0.032 BSC 0.80 BSC - ND 24 24 - NE 16 16 Rev. 0 5/97 0.10 0.004 -C0.24 M 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. Dimensions D and E to be determined at seating plane -C- . B 3. Dimensions D1 and E1 to be determined at datum plane -H- . 4. Dimensions D1 and E1 do not include mold protrusion. A1 0o-10o NOTES: 5. Dimension B does not include dambar protrusion. 6. “N” is the number of terminal positions. L 0.100/0.250 0.004/0.010 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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