HCS240MS Radiation Hardened Octal Buffer/Line Driver, Three-State September 1995 Features Pinouts 20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T20, LEAD FINISH C TOP VIEW • 3 Micron Radiation Hardened CMOS SOS • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ) • Dose Rate Survivability: >1 x 1012 RAD (Si)/s 10 • Dose Rate Upset >10 RAD (Si)/s 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to LSTTL ICs AE 1 AI1 2 19 BE BO4 3 18 AO1 20 VCC AI2 4 17 BI4 BO3 5 16 AO2 AI3 6 15 BI3 BO2 7 14 AO3 AI4 8 13 BI2 BO1 9 12 AO4 GND 10 • DC Operating Voltage Range: 4.5V to 5.5V 11 BI1 • Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min • Input Current Levels Ii ≤ 5µA at VOL, VOH 20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F20, LEAD FINISH C TOP VIEW Description The Intersil HCS240MS is a Radiation Hardened Inverting Octal Buffer/Line Driver, Three-State, with two active-low output enables. 20 VCC 2 19 BE 3 18 AO1 AI2 4 17 BI4 BO3 5 16 AO2 AI3 6 15 BI3 BO2 7 14 AO3 AI4 8 13 BI2 BO1 9 12 AO4 GND 10 11 BI1 AE The HCS240MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS240MS is supplied in a 20 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). AI1 BO4 1 Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE HCS240DMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead SBDIP HCS240KMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead Ceramic Flatpack HCS240D/Sample +25oC Sample 20 Lead SBDIP HCS240K/Sample +25oC Sample 20 Lead Ceramic Flatpack HCS240HMSR +25oC Die Die CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 1 Spec Number File Number 518837 3562.1 HCS240MS Functional Diagram AO1 18 N 1 AE P 2 AI1 AO2 16 N P 4 AI2 AO3 14 N P AO4 12 N 6 AI3 P BO1 9 P 8 AI4 N 11 BI1 BO2 7 P N BO3 5 P N 13 BI2 15 BI3 BO4 3 P N 17 BI4 19 BE TRUTH TABLE INPUTS OUTPUT AE, BE An Yn L L H L H L H X Z H = High Voltage Level, L =Low Voltage Level X = Immaterial, Z =High Impedance Spec Number 2 518837 Specifications HCS240MS Absolute Maximum Ratings Reliability Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±35mA Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (All Voltage Reference to the VSS Terminal) Thermal Resistance θJA θJC SBDIP Package. . . . . . . . . . . . . . . . . . . . 72oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 107oC/W 28oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.47W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.9mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 9.3mW/oC Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Time at 4.5V VCC (tr, tf) . . . . . . . 100ns/V Max. Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . VCC to 70% of VCC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . .0V to 30% of VCC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Output Current (Source) Output Current (Sink) Output Voltage High Output Voltage Low Input Leakage Current Three-State Output Leakage Current Noise Immunity Functional Test SYMBOL ICC IOH IOL VOH VOL IIN IOZ FN (NOTE 1) CONDITIONS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 40 µA 2, 3 +125oC, -55oC - 750 µA 1 +25oC -7.2 - mA 2, 3 +125oC, -55oC -6.0 - mA 1 +25oC 7.2 - mA 6.0 - mA VCC = 5.5V, VIN = VCC or GND VCC = 4.5V, VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0V, (Note 2) VCC = 4.5V, VIH = 4.5V, VOUT = 0.4V, VIL = 0V, (Note 2) 2, 3 LIMITS +125oC, -55oC VCC = 5.5V, VIH = 3.85V, VIL = 1.65V, IOH = -50µA 1, 2, 3 +25oC, +125oC, -55oC VCC -0.1 - V VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, IOH = -50µA 1, 2, 3 +25oC, +125oC, -55oC VCC -0.1 - V VCC = 5.5V, VIH = 3.85V, VIL = 1.65V, IOL = 50µA 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, IOL = 50µA 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V VCC = 5.5V, VIN = VCC or GND 1 +25oC - ±0.5 µA 2, 3 +125oC, -55oC - ±5.0 µA 1 +25oC - ±1 µA 2, 3 +125oC, -55oC - ±50 µA - - V VCC = 5.5V, Force Voltage = 0V or VCC VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, (Note 3) 7, 8A, 8B +25oC, +125oC, -55oC NOTES: 1. All voltages reference to device GND. 2. Force/Measure functions may be interchanged. 3. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”. Spec Number 3 518837 Specifications HCS240MS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Propagation Delay Propagation Delay Propagation Delay Propagation Delay Propagation Delay (NOTES 1, 2) CONDITIONS SYMBOL TPHL1 GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 9 +25oC 2 18 ns 10, 11 +125oC, -55oC 2 20 ns 9 +25oC 2 19 ns 10, 11 +125oC, -55oC 2 21 ns 9 +25oC 2 22 ns 10, 11 +125oC, -55oC 2 25 ns 9 +25oC 2 21 ns 10, 11 +125oC, -55oC 2 23 ns 9 +25oC 2 20 ns 10, 11 +125oC, -55oC 2 22 ns 9 +25oC 2 20 ns 10, 11 +125oC, -55oC 2 21 ns VCC = 4.5V, VIH = 4.5V, VIL = 0V TPLH1 VCC = 4.5V, VIH = 4.5V, VIL = 0V TPZL1 VCC = 4.5V, VIH = 4.5V, VIL = 0V TPLZ1 VCC = 4.5V, VIH = 4.5V, VIL = 0V TPZH1 VCC = 4.5V, VIH = 4.5V, VIL = 0V TPHZ1 VCC = 4.5V, VIH = 4.5V, VIL = 0V LIMITS NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Capacitance Power Dissipation Input Capacitance Output Capacitance Output Transition Time SYMBOL CPD CIN COUT TTHL TTLH (NOTE 1) CONDITIONS VCC = 5.0V, VIH = 5.0V, VIL = 0V, f = 1MHz VCC = 5.0V, VIH = 5.0V, VIL = 0V, f = 1MHz VCC = 5.0V, VIH = 5.0V, VIL = 0V, f = 1MHz VCC = 4.5V, VIH = 4.5V, VIL = 0V TEMPERATURE MIN MAX UNITS +25oC - 56 pF +125oC, -55oC - 86 pF +25oC - 10 pF +125oC, -55oC - 10 pF +25oC - 20 pF +125oC, -55oC - 20 pF +25oC 1 15 ns +125oC, -55oC 1 22 ns NOTE: 1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. Spec Number 4 518837 Specifications HCS240MS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS 200K RAD LIMITS PARAMETER (NOTE 1) CONDITIONS SYMBOL TEMPERATURE MIN MAX UNITS Supply Current ICC VCC = 5.5V, VIN = VCC or GND +25oC - 0.75 mA Output Current (Source) IOH VCC = VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0 +25oC -6.0 - mA Output Current (Sink) IOL VCC = VIH = 4.5V, VOUT = 0.4V, VIL = 0 +25oC 6.0 - mA Output Voltage High VOH VCC = 5.5V, VIH = 3.85V, VIL = 1.65V, IOH = -50µA +25oC VCC -0.1 - V VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, IOH = -50µA +25oC VCC -0.1 - V VCC = 5.5V, VIH = 3.85V, VIL = 1.65V, IOL = 50µA +25oC - 0.1 V VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, IOL = 50µA +25oC - 0.1 V Output Voltage Low VOL Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND +25oC - ±5 µA Three-State Output Leakage Current IOZ VCC = 5.5V, Force Voltage = 0V or VCC +25oC - ±50 µA Noise Immunity Functional Test FN VCC = 4.5V, VIH = 3.15V, VIL = 1.35V, (Note 2) +25oC - - V Propagation Delay TPHL1 VCC = 4.5V, VIH = 4.5V, VIL = 0V +25oC 2 20 ns Propagation Delay TPLH1 VCC = 4.5V, VIH = 4.5V, VIL = 0V +25oC 2 21 ns Propagation Delay TPZL1 VCC = 4.5V, VIH = 4.5V, VIL = 0V +25oC 2 25 ns Propagation Delay TPLZ1 VCC = 4.5V, VIH = 4.5V, VIL = 0V +25oC 2 23 ns Propagation Delay TPZH1 VCC = 4.5V, VIH = 4.5V, VIL = 0V +25oC 2 22 ns Propagation Delay TPHZ1 VCC = 4.5V, VIH = 4.5V, VIL = 0V +25oC 2 21 ns NOTES: 1. All voltages referenced to device GND. 2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”. TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC) GROUP B SUBGROUP DELTA LIMIT ICC 5 12µA IOL/IOH 5 -15% of 0 Hour IOZ 5 ±200nA PARAMETER Spec Number 5 518837 Specifications HCS240MS TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD GROUP A SUBGROUPS Initial Test (Preburn-In) 100%/5004 1, 7, 9 ICC, IOL/H, IOZL/H Interim Test I (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H, IOZL/H Interim Test II (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H, IOZL/H PDA 100%/5004 1, 7, 9, Deltas Interim Test III (Postburn-In) 100%/5004 1, 7, 9 PDA 100%/5004 1, 7, 9, Deltas Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Sample/5005 1, 7, 9 Sample/5005 1, 7, 9 Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D READ AND RECORD ICC, IOL/H, IOZL/H Subgroups 1, 2, 3, 9, 10, 11 NOTE: 1. Alternate group A testing in accordance with Method 5005 of Mil-Std-883 may be exercised. TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUPS READ AND RECORD METHOD PRE RAD POST RAD PRE RAD POST RAD 5005 1, 7, 9 Table 4 1, 9 Table 4 (Note 1) Group E Subgroup 2 NOTE: 1. Except FN test which will be performed 100% go/no-go. TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OSCILLATOR GROUND 1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V 50kHz 25kHz 1, 2, 4, 6, 8, 10, 11, 13, 15, 17, 19 - 20 - - 10 - 1, 2, 4, 6, 8, 11, 13, 15, 17, 19, 20 - - 1, 10, 19 3, 5, 7, 9, 12, 14, 16, 18 20 2, 4, 6, 8, 11, 13, 15, 17 - OPEN STATIC I BURN-IN (Note 1) 3, 5, 7, 9, 12, 14, 16, 18 STATIC II BURN-IN (Note 1) 3, 5, 7, 9, 12, 14, 16, 18 DYNAMIC BURN-IN (Note 2) NOTES: 1. Each pin except VCC and GND will have a series resistor of 10kΩ ± 5%. 2. Each pin except VCC and GND will have a series resistor of 680Ω ± 5%. TABLE 9. IRRADIATION TEST CONNECTIONS OPEN GROUND VCC = 5V ± 0.5V 3, 5, 7, 9, 12, 14, 16, 18 10 1, 2, 4, 6, 8, 11, 13, 15, 17, 19, 20 NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing. Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Spec Number 6 518837 HCS240MS Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) 100% Interim Electrical Test 1 (T1) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Static Burn-In 2, Condition A or B, 24 hrs. min., +125oC min., Method 1015 100% Nondestructive Bond Pull, Method 2023 100% Interim Electrical Test 2 (T2) Sample - Wire Bond Pull Monitor, Method 2011 100% Delta Calculation (T0-T2) Sample - Die Shear Monitor, Method 2019 or 2027 100% PDA 1, Method 5004 (Notes 1and 2) 100% Internal Visual Inspection, Method 2010, Condition A 100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or Equivalent, Method 1015 100% Delta Calculation (T0-T1) 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Interim Electrical Test 3 (T3) 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% Delta Calculation (T0-T3) 100% PDA 2, Method 5004 (Note 2) 100% PIND, Method 2020, Condition A 100% Final Electrical Test 100% External Visual 100% Fine/Gross Leak, Method 1014 100% Serialization 100% Radiographic, Method 2012 (Note 3) 100% Initial Electrical Test (T0) 100% External Visual, Method 2009 100% Static Burn-In 1, Condition A or B, 24 hrs. min., +125oC min., Method 1015 Sample - Group A, Method 5005 (Note 4) 100% Data Package Generation (Note 5) NOTES: 1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1. 2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Data Package Contents: • Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). • Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. • GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. • X-Ray report and film. Includes penetrometer measurements. • Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). • Lot Serial Number Sheet (Good units serial number and lot number). • Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. Spec Number 7 518837 HCS240MS Propagation Delay Timing Diagram Propagation Delay Load Circuit VIH TEST POINT DUT INPUT VS VSS TPLH CL TPHL RL CL = 50pF RL = 500Ω VOH VS OUTPUT VOL Transition Timing Diagram TTLH VOH TTHL 80% 20% VOL 80% 20% OUTPUT VOLTAGE LEVELS PARAMETER HCS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VIL 0 V GND 0 V Three-State High Timing Diagrams Three-State High Load Circuit VIH TEST POINT DUT VS INPUT VSS TPZH CL TPHZ RL CL = 50pF RL = 500Ω VOH VT VW OUTPUT VOZ THREE-STATE HIGH VOLTAGE LEVELS PARAMETER HCS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VT 2.25 V VW 3.60 V 0 V GND Spec Number 8 518837 HCS240MS Three-State Low Timing Diagrams Three-State Low Load Circuit VCC VIH VS INPUT VSS RL TPZL TPLZ VOZ VT TEST POINT DUT VW OUTPUT VOL CL CL = 50pF THREE-STATE LOW VOLTAGE LEVELS PARAMETER RL = 500Ω HCS UNITS VCC 4.50 V VIH 4.50 V VS 2.25 V VT 2.25 V VW 0.90 V 0 V GND Spec Number 9 518837 HCS240MS Die Characteristics DIE DIMENSIONS: 108 x 106 x 19 ± 1mils METALLIZATION: Type: Si - Al Thickness: 11kÅ ± 1kÅ GLASSIVATION: Type: SiO2 Thickness: 13kÅ ± 2.6kÅ WORST CASE CURRENT DENSITY: <2.0 x 105 A/cm2 BOND PAD SIZE: 4 x 4 (mils) 100 x 100µm Metallization Mask Layout (19) BE (20) VCC (1) AE (2) AI1 (3)BO4 HCS240MS (18) AO1 AI2 (4) (17) BI4 BO3 (5) (16) AO2 AI3 (6) (15) BI3 BO2 (7) BI2 (13) AO4 (12) BI1 (11) GND (10) BO1 (9) AI4 (8) (14) AO3 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Spec Number 10 518837