AN1287

AN1287
Using C18/HI-TECH C® Compiler to Interface Serial SRAM Devices
to PIC16F/PIC18F Microcontrollers
Author:
This application note is part of a series that provide
source code to help the user implement the protocol
with minimal effort.
Deepak Kumar Rana
Microchip Technology Inc.
INTRODUCTION
Microchip’s serial SRAM product line represents a new
way to add additional RAM to an application. With the
small 8-pin packages and the SPI interface, these
devices give designers added system flexibility. The
23XXXX series of serial SRAM devices from Microchip
Technology support a half-duplex protocol that
functions on a master-slave paradigm that is ideally
suited to data stream applications.
Figure 1 describes the hardware schematic for the
interface between Microchip’s 23XXXX series devices
and the PIC16F/18F series of MCUs. The schematic
shows the connections necessary between either
controller and the serial SRAM as tested, and the software was written assuming these connections. The
HOLD pin is tied to VCC because this feature is not
used in the examples provided.
The bus is controlled by the Microcontroller (master),
which accesses the 23XXXX using the MSSP peripheral built into the MCU configured for SPI operation.
The MSSP peripheral can support throughput up to 5 or
8 MHz depending upon the device family of PIC16/18
MCU Selected. Communication can be paused using
the HOLD pin.
FIGURE 1:
CIRCUIT FOR PIC16F887 AND 23XXXX SERIES DEVICE
VCC
CS
VCC
SO
HOLD
NC
SCK
VSS
SI
23XXXX
15
16
17
18
23
24
25
26
19
20
21
22
27
28
29
30
8
9
10
U1
RE3/MCLR/VPP
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/PA1/CCP1
RA0/AN0/ULPWU/C12IN0RC3/SCK/SCL
RA1/AN1/C12IN1RA2/AN2/VREF-/CVREF/C2IN+
RC4/SDI/SDA
RA3/AN3/VREF+/C1IN+
RC5/SDO
RC6/TX/CK
RA4/TOCKI/C1OUT
RC7/RX/DT
RA5/AN4/SS/C2OUT
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RD0
RD1
RD2
RB0/AN12/INT
RB1/AN10/C12IN3RD3
RB2/AN8
RD4
RB3/AN9/PGM/C12IN2RD5/P1B
RB4/AN11
RD6/P1C
RD7/P1D
RB5/AN13/T1G
RB6/ICSPCLK
RE0/AN5
RB7/ICSPDAT
RE1/AN6
RE2/AN7
1
2
3
4
5
6
7
14
13
33
34
35
36
37
38
39
40
PIC16F887
Note:
CS and HOLD pins should all have pull-up resistors (~10k-ohms). See application note AN1245,
“Recommended Usage of Microchip SPI Serial SRAM Devices.”
© 2009 Microchip Technology Inc.
DS01287A-page 1
AN1287
FIRMWARE DESCRIPTION
The purpose of this application note is to offer the
designer a set of examples for the read and write functions for using the Microchip SPI serial SRAM. Examples are included for the following modes: Byte, Page
and Sequential Read and Writes. The code uses onchip MSSP hardware peripheral to communicate with
the serial SRAM.
The code was tested using the 23K256 SRAM
mounted on the general purpose section of the
PICDEM™ 2 Plus development board. The MSSP
module is configured for SPI Master mode with a clock
frequency of 5 MHz. The code is compatible with the
PIC16F/18F families of MCUs with the MSSP module.
Oscilloscope screen shots are shown in this application
note.
The following functions are provided to access the
Serial SRAM.
•
•
•
•
•
•
•
•
SRAMWriteStatusReg
SRAMReadStatusReg
SRAMWriteByte
SRAMReadByte
SRAMWritePage
SRAMReadPage
SRAMWriteSeq
SRAMReadSeq
The above functions are defined in the driver files
SRAM_Driver.asm (for PIC16 assembly code and
PIC18 C code) and SRAM_Driver.c (for PIC16 HITECH), with a respective SRAM_Driver.inc and
SRAM_Driver.h files.
The respective file pairs can be directly imported into
the users application code. For the PIC18 C code we
use the driver file in assembly (SRAM_Driver.asm)
and call the assembly functions from C file
Main_Demo.c.
Four Code examples accompanying the application
note are:
• Assembly code example for PIC16 (MPASM™
assembler)
• HI-TECH C® code example for PIC16 (HI-TECH
C compiler)
• C Code example for PIC18 (MPASM assembler
and C18 compiler)
• C Code example for PIC18 (HI-TECH C compiler)
DS01287A-page 2
© 2009 Microchip Technology Inc.
AN1287
INITIALIZATION
WRITE STATUS REGISTER
Only one function needs to be called to initialize the
SRAM. To communicate with the SRAM we need to
configure the on-chip MSSP module of the MCU for
SPI operation. The InitSRAM() function initializes the
MSSP module for SPI (Master mode 1, CKP=0,
CKE=1) functionality. Using the on-chip MSSP peripheral makes the communication easier than bit-banging
the I/O port, reducing software overhead.
The default mode of operation for the serial SRAM is
Byte mode and the user must select the appropriate
mode (Byte, Page, Sequential) before the read or write
operation. The functions that are provided configure
the SRAM for the correct mode of operation, for example if a SRAMWritePage command is called, then the
appropriate operating mode is selected. The STATUS
register also has provision for enabling the HOLD feature, but this is not used in these examples. Figure 2
shows an example of the Write Status Register
command. Chip Select is brought low (active) and the
opcode is sent out through the SPI port. The Write
Status command is given followed by the data to be
written, in this case, Byte mode is selected.
© 2009 Microchip Technology Inc.
DS01287A-page 3
AN1287
FIGURE 2:
WRITE STATUS REGISTER
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
Data to STATUS Register
0
0
0
1
7
6
5
4
3
2
High-Impedance
SO
DS01287A-page 4
© 2009 Microchip Technology Inc.
AN1287
READ STATUS REGISTER
Figure 3 shows an example of the Read Status
Register command to check for the mode of operation
and also the current status of the HOLD function.
FIGURE 3:
READ STATUS REGISTER
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
0
1
0
1
Data from STATUS Register
High-Impedance
SO
© 2009 Microchip Technology Inc.
7
6
5
4
3
2
DS01287A-page 5
AN1287
BYTE WRITE
The byte write operation consists of the following
sequence: The Write command followed by the word
address and data byte. The serial SRAM uses a 16-bit
address, so two bytes must be transmitted for the entire
word address, with the Most Significant Byte (MSB)
first.
FIGURE 4:
Figure 4 shows an example of the Write command. For
this, the device is selected and the opcode, 0x02, is
sent. The High Address byte is given 0x00, followed by
the Low Address byte, 0x20. Finally, the data is clocked
in last, in this case, 0x55.
BYTE WRITE COMMAND, ADDRESS AND DATA
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0
1
0 15 14 13 12
Data Byte
2
1
0
7
6
5
4
3
2
1
0
High-Impedance
SO
DS01287A-page 6
© 2009 Microchip Technology Inc.
AN1287
BYTE READ
The byte read operation can be used to read data from
the serial SRAM. The MCU/DSC sends the command
byte followed by the word address. Figure 5 shows an
example of the Read command, followed by the MSB
and LSB address bytes, followed by the read byte.
FIGURE 5:
BYTE READ (COMMAND BYTE, WORD ADDRESS AND READ BYTE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0
1
1 15 14 13 12
2
1
0
Data Out
High-Impedance
SO
© 2009 Microchip Technology Inc.
7
6
5
4
3
2
1
0
DS01287A-page 7
AN1287
PAGE WRITE
Page write operations provide a technique for increasing throughput when writing large blocks of data. The
Serial SRAM features a 32-byte page. By using the
page write feature, up to 1 full page of data can be written consecutively. It is important to point out that page
write operations are limited to writing bytes within a single physical page regardless of the number of bytes
being written. Physical page boundaries start at
FIGURE 6:
addresses that are integer multiples of the page size
and end at addresses that are [integer multiples of the
page size] – 1. Attempting to write across a page
boundary results in the data being wrapped back to the
beginning of the current page. Figure 6 shows Write
command, address and data byte during a page write
operation.
PAGE WRITE (FIRST DATA BYTE)
CS
0
1
2
3
4
5
6
Instruction
SI
0
0
0
0
0
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
Page X, Word Y
16-bit Address
0 1
0 15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
Page X, Word Y
DS01287A-page 8
© 2009 Microchip Technology Inc.
AN1287
PAGE READ
Page read operations read a complete string, starting
with the specified address. The page read operation
also works similar to a page write operation and thus a
maximum of 32 bytes can be read consecutively.
Figure 7 shows an example of the entire sequence of
commands necessary to perform the page read operation. For clarity, only the first byte is shown.
FIGURE 7:
PAGE READ (FIRST READ DATA BYTE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0 1
1 15 14 13 12
2
1
0
Page X, Word Y
SO
© 2009 Microchip Technology Inc.
Page X, Word Y
High Impedance
7
6
5
4
3
2
1
0
DS01287A-page 9
AN1287
SEQUENTIAL WRITE
This operation is very useful while writing a long string
which is more than the page size (32 bytes). This operation needs Write command (0x02) to be sent followed
by upper address byte and lower address byte. The
SRAM keeps writing data as long as it receives clock
and valid data. When the last location of memory is
reached, the next location that is written is the first
address (0x0000), that is, the internal address counter
rolls over. Figure 8 depicts the entire sequence of commands necessary to perform the sequential write operation. For clarity, only the first byte is shown.
FIGURE 8:
SEQUENTIAL WRITE (FIRST DATA BYTE)
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
DS01287A-page 10
0
0
0
16-bit Address
0 1
0 15 14 13 12
Data Byte 1
2
1
0
7
6
5
4
3
2
1
0
© 2009 Microchip Technology Inc.
AN1287
SEQUENTIAL READ
Sequential read operation allows the entire array to be
read from the SRAM. The internal address counter
automatically increments and page boundaries are
ignored. When the internal address counter reaches
the end of the array, the address counter will roll over
to 0x0000. Figure 9 shows an example of the sequence
of commands necessary to perform a sequential read
operation.
FIGURE 9:
SEQUENTIAL READ (FIRST READ DATA BYTE)
CS
0
1
2
0
0
0
3
4
5
6
Instruction
SI
0
0
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
16-bit Address
0 1
1 15 14 13 12
2
1
0
Page X, Word Y
SO
© 2009 Microchip Technology Inc.
7
6
5
4
3
2
1
0
DS01287A-page 11
AN1287
CONCLUSION
This application note offers designers a set of firmware
routines to access SPI serial SRAM. The code demonstrates read and write operations for Byte, Page and
Sequential modes. All the routines were written under
the Microchip development environment MPLAB® IDE,
using tools MPASM assembler, C18 and HI-TECH C
compilers. The code was tested on Microchip’s
PICDEM™ 2 Plus development board with the
connections shown in Figure 1 with the PIC16F887 and
PIC18F45K20.
DS01287A-page 12
© 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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© 2009 Microchip Technology Inc.
DS01287A-page 13
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DS01287A-page 14
© 2009 Microchip Technology Inc.