PIC18F23/43K20 PIC18F23/43K20 Family Silicon Errata and Data Sheet Clarification The PIC18F23/43K20 family devices that you have received conform functionally to the current Device Data Sheet (DS41303H), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. The errata described in this document will be addressed in future revisions of the PIC18F23/43K20 silicon. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (B0). Data Sheet clarifications and corrections start on page 6, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip’s programmers, debuggers and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2, MPLAB ICD 3, PICkit™ 2 or PICkit 3: 1. Using the appropriate interface, connect the device to the MPLAB ICD 2 programmer/ debugger, PICkit 2 or PICkit 3. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Programmer>Select Tool). Perform a “Connect” operation to the device (Programmer>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. 2. 3. 4. Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The Device ID values for the various devices and silicon revisions are shown in Table 1. SILICON DEVREV VALUES Part Number Revision ID for Silicon Revision(2) Device ID(1) A0 A1 B0 PIC18F23K20 20E0h 00h 01h 02h PIC18F43K20 20C0h 00h 01h 02h Note 1: 2: The device and revision data is stored in the Device ID located at 3FFFFE:3FFFFFh in Configuration and ID memory. Refer to the “PIC18F2XK20/4XK20 Memory Programming Specification” (DS41297) for detailed information. 2009-2015 Microchip Technology Inc. DS80000469E-page 1 PIC18F23/43K20 TABLE 2: SILICON ISSUE SUMMARY (PIC18F23/43K20) Module BOR Feature Item Number Issue Summary Affected Revisions(1) A0 A1 X X B0 Reset 1. Unexpected Reset when using comparator. Comparator Comparator 2. Output glitch with FVR selected for ADC. ECCP Full-Bridge 3. Dead-band time is 4/FOSC instead of 1/FOSC. X X X ECCP Full-Bridge 4. Compromised dead band. X X X MSSP (SPI clock) SPI clock 5. Improper start in Timer2/2 Clock mode. X X X MSSP (SPI Master mode) SPI Master 6. Improper sampling of last bit. X X X MSSP (SPI Master mode) SPI Master 7. Write collision on transmission. X X X MSSP (Master I2C mode) I2C Master 8. Improper handling of Stop event. X X X X EUSART OERR Flag 9. Clearing SPEN bit does not clear OERR flag. X X X EUSART BAUDCON 10. RCIDL may improperly stay low. X X X Data EEPROM Memory Endurance 11. Endurance limited to 10K cycles. X X Program Flash Memory Endurance 12. Endurance limited to 1K cycles. X X ADC Conversion 13. ADC conversion may be limited to half scale. X ADC Note 1: Only those issues indicated in the last column apply to the current silicon revision. DS80000469E-page 2 2009-2015 Microchip Technology Inc. PIC18F23/43K20 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B0). 1. Module: BOR An unexpected Brown-out Reset may occur when enabling the comparator with the Fixed Voltage Reference (FVR) selected as the VIN+ input. Work around Disconnect the FVR from the VIN+ comparator inputs prior to enabling the comparator and then reconnect it after enabling the comparator. Affected Silicon Revisions A0 A1 X X B0 2. Module: Comparator There may be a glitch on the comparator output when both the comparator and the ADC are using the Fixed Voltage Reference (FVR) as an input and the ADC is enabled, disabled, or starts a conversion. Work around Do not use the FVR as an input to both the comparator and the ADC at the same time. Affected Silicon Revisions 4. Module: ECCP In Full-Bridge mode when PR2 = CCPR1L and DC1B<1:0> = 00 and the direction is changed then the dead time before the modulated output starts is compromised. The modulated signal improperly starts immediately with the direction change and stays on for Tosc * TMR2Presale * DC1B<1:0>. Work around Avoid changing direction when the duty cycle is within three Least Significant steps of 100% duty cycle. Instead, clear the DC1B<1:0> bits before the direction change and then set them to the desired value after the direction change is complete. Affected Silicon Revisions PIC18F23/43K20 A0 A1 B0 X X X 5. Module: MSSP (SPI clock) When the SPI clock is configured for Timer2/2 (SSPCON1<3:0> = 0011), and the CKE bit of the SSPSTAT register is ‘1’, then when SSPBUF is written the SCK output is improperly and immediately driven to the non-Idle state together with the MSb value of the SSPBUF. The duration at which SDO and SCK remain at these levels may be shorter than a full half-bit period. The remaining bits in the byte are output properly. Work around None. A0 A1 B0 X Affected Silicon Revisions PIC18F23/43K20 3. Module: ECCP Changing direction in Full-Bridge mode inserts a dead band time of 4/FOSC * (TMR2 Prescale) instead of 1/FOSC * (TMR2 Prescale) as specified in the data sheet. A0 A1 B0 X X X Work around None. Affected Silicon Revisions PIC18F23/43K20 A0 A1 B0 X X X 2009-2015 Microchip Technology Inc. DS80000469E-page 3 PIC18F23/43K20 6. Module: MSSP (SPI Master mode) 8. Module: MSSP (Master I2C mode) none. In Master I2C Receive mode, if a Stop condition occurs in the middle of an address or data reception, then the SCL clock stream will continue endlessly and the RCEN bit of the SSPCON2 register will remain set improperly. When a Start condition occurs after the improper Stop condition, then nine additional clocks will be generated followed by the RCEN bit going low. Affected Silicon Revisions Work around PIC18F23/43K20 Use low-impedance pull-ups on the SDA line to reduce the possibility of noise glitches, which may trigger an improper Stop event. Use a time-out event timer to detect the unexpected Stop condition and resulting stuck RCEN bit. Clear stuck RCEN bit by clearing SSPEN bit of SSPCON1. In SPI Master mode, when the CKE bit of the SSPSTAT register is cleared and the SMP bit of the SSPSTAT register is set, then the last bit of the incoming data stream (bit 0) at the SDI pin will not be sampled properly. Work around A0 A1 B0 X X X 7. Module: MSSP (SPI Master mode) In SPI Master mode, if the SSPBUF register is written while a byte is actively being transmitted, an extra clock pulse will be improperly generated at the end of the transmission. Further writes to the SSPBUF register will be inhibited although 8 or 9 clock pulses will be generated for each attempted write. The WCON bit of the SSPCON register is properly set indicating that a write collision occurred. However, the write collision condition can only be cleared by resetting the MSSP module. Clear the MSSP by clearing the SSPEN bit of the SSPCON1 register. Affected Silicon Revisions PIC18F23/43K20 A0 A1 B0 X X X 9. Module: EUSART The OERR flag of the RCSTA register is reset only by clearing the CREN bit of the RCSTA register or by a device Reset. Clearing the SPEN bit of the RCSTA register does not clear the OERR flag. Work around Work around Use the SSPIF bit of the PIR1 register or the BF bit of the SSPSTAT register to determine that the transmission is complete before writing the SSPBUF register. In the event that a write collision does occur, use the Slave Select feature to resynchronize the Slave clock. Clear the OERR flag by clearing the CREN bit instead of clearing the SPEN bit. Affected Silicon Revisions Affected Silicon Revisions PIC18F23/43K20 A0 A1 B0 X X X PIC18F23/43K20 A0 A1 B0 X X X DS80000469E-page 4 2009-2015 Microchip Technology Inc. PIC18F23/43K20 10. Module: EUSART In Asynchronous Receive mode, the RCIDL bit of the BAUDCON register will properly go low when an invalid Start bit less than 1/16th of a bit time is received. The RCIDL bit will then properly go high 1/8th of a bit time later. However, if another invalid Start bit occurs less than 1 bit time after the leading edge of the first invalid Start bit then the RCIDL bit will improperly stay high then improperly go low one bit time later. The RCIDL bit will then stay low improperly until a valid Start bit is received. Work around When monitoring the RCIDL bit, measure the length of time between the RCIDL going low and the RCIF flag going high. If this time is greater than one character time then restore the RCIDL bit by resetting the EUSART module. The EUSART module is reset when the SPEN bit of the RCSTA register is cleared. Affected Silicon Revisions PIC18F23/43K20 A0 A1 B0 X X X 11. Module: Data EEPROM Memory The write/erase endurance of Data EE Memory is limited to 10K cycles. Work around Use error correction method that stores data in multiple locations. Affected Silicon Revisions 13. Module: ADC After extended stress the Most Significant bit (MSb) of the ADC conversion result can become stuck at ‘0’. Conversions resulting in code 511 or less are still accurate, but conversions that should result in codes greater than 511 are instead pinned at 511. The potential for failures is a function of several factors: • The potential for failures increases over the life of the part. No failures have ever been seen for accelerated stress estimated to be equivalent to 34 years at room temperature. The failure rate after accelerated stress estimated to be equivalent to 146 years at room temperature can be as high as 10% for VDD = 1.8V. The time to failure will decrease as the operating temperature increases. • The potential for failures is highest at low VDD and decreases as VDD increases. Work around 1. Restrict the input voltage to less than 1/2 of the ADC voltage reference so that the expected result is always a code less than or equal to 511. 2. Use manual acquisition time (ACQT<2:0> = 000) and put the part to Sleep after each conversion. Affected Silicon Revisions PIC18F23/43K20 A0 A1 B0 X PIC18F23/43K20 A0 A1 X X B0 12. Module: Program Flash Memory The write/erase endurance of the Program Flash Memory is limited to 1K cycles when VDD is above 3V. Endurance degrades when VDD is below 3V. Work around For data tables in Program Flash Memory use error correction method that stores data in multiple locations. Affected Silicon Revisions PIC18F23/43K20 A0 A1 X X B0 2009-2015 Microchip Technology Inc. DS80000469E-page 5 PIC18F23/43K20 Data Sheet Clarifications The following typographical corrections and clarifications are to be noted for the latest version of the device data sheet (DS41303H): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Product Identification System The temperature range values have been corrected. PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) X /XX XXX Device Tape and Reel Option Temperature Range Package Pattern Examples: a) b) Device: PIC18F23K20; PIC18F43K20; PIC16F884; PIC18F26K20; PIC16F886; PIC16F887; PIC18F45K20; PIC18F46K20. c) d) Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I E = -40C to +85C = -40C to +125C Package: PT SS SO SP P ML MV = = = = = = = Pattern: PIC18F45K20 - E/P 301 = Industrial temp., PDIP package, QTP pattern #301. PIC18F23K20 - I/SO = Industrial temp., SOIC package. PIC16F887 - E/P = Extended temp., PDIP package. PIC18F46K20 - I/PT = Industrial temp., TQFP package, tape and reel. (Industrial) (Extended) TQFP (Thin Quad Flatpack) SSOP SOIC SPDIP (Skinny Plastic DIP) PDIP QFN UQFN Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. QTP, SQTP, Code or Special Requirements (blank otherwise) DS80000469E-page 6 2009-2015 Microchip Technology Inc. PIC18F23/43K20 APPENDIX A: DOCUMENT REVISION HISTORY Rev. A Document (4/2009) First revision of this document. Data Sheet Clarification: Added Module 1: MSSP I2C™ (Table 17-3); Module 2: ADC (Equation 19-1); Module 3: Interrupts. Added Module 1: ECCP; Module 2: ECCP; Module 3: MSSP; Module 4: MSSP; Module 5: MSSP; Module 6: MSSP; Module 7: EUSART; Module 8: EUSART; Module 9: Data EEPROM Memory; Module 10: Program Flash Memory; Added Module 11: ADC. Rev. B Document (9/2009) Added Silicon Revision A1. Removed Data Sheet Clarification items. Rev. C Document (7/2010) Removed ADC Work around #2 and changed #3 to #2 (Module 11). Rev. D Document (7/2011) Added Silicon Revision B0; Added Modules BOR and Comparator. Rev. E Document (9/2015) Data Sheet Clarifications: Added Module 1: Product Identification System. 2009-2015 Microchip Technology Inc. DS80000469E-page 7 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2009-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-797-3 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == DS80000469E-page 8 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2009-2015 Microchip Technology Inc. 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