TI CD74HCT173M

[ /Title
(CD74H
C173,
CD74H
CT173)
/Subject
(High
Speed
CMOS
Logic
Quad DType
CD74HC173,
CD74HCT173
Data sheet acquired from Harris Semiconductor
SCHS158
High Speed CMOS Logic
Quad D-Type Flip-Flop, Three-State
February 1998
Features
Description
• Three-State Buffered Outputs
The Harris CD74HC173 and CD74HCT173 high speed
three-state quad D-type flip-flops are fabricated with silicon
gate CMOS technology. They possess the low power consumption of standard CMOS Integrated circuits, and can
operate at speeds comparable to the equivalent low power
Schottky devices. The buffered outputs can drive 15 LSTTL
loads. The large output drive capability and three-state feature make these parts ideally suited for interfacing with bus
lines in bus oriented systems.
• Gated Input and Output Enables
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
The four D-type flip-flops operate synchronously from a common clock. The outputs are in the three-state mode when
either of the two output disable pins are at the logic “1” level.
The input ENABLES allow the flip-flops to remain in their
present states without having to disrupt the clock If either of
the 2 input ENABLES are taken to a logic “1” level, the Q
outputs are fed back to the inputs, forcing the flip-flops to
remain in the same state. Reset is enabled by taking the
MASTER RESET (MR) input to a logic “1” level. The data
outputs change state on the positive going edge of the clock.
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
The CD74HCT173 logic family is functionally, as well as pin
compatible with the standard 74LS logic family.
Pinout
Ordering Information
CD74HC173, CD74HC173
(PDIP, SOIC)
TOP VIEW
PART NUMBER
TEMP. RANGE
(oC)
PKG.
NO.
PACKAGE
OE 1
16 VCC
CD74HC173E
-55 to 125
16 Ld PDIP
E16.3
OE2 2
15 MR
CD74HCT173E
-55 to 125
16 Ld PDIP
E16.3
Q0 3
14 D0
CD74HC173M
-55 to 125
16 Ld SOIC
M16.15
Q1 4
13 D1
Q2 5
12 D2
CD74HCT173M
-55 to 125
16 Ld SOIC
M16.15
Q3 6
11 D3
CP 7
10 E2
GND 8
9 E1
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
File Number
1641.1
CD74HC173, CD74HCT173
Functional Diagram
E1
E2
10
D0
D1
9
14
3
Q0
13
4
Q1
12
D2
5
Q2
11
D3
6
Q3
7
CP
15
MR
1
2
OE1
OE2
TRUTH TABLE
INPUTS
DATA ENABLE
DATA
OUTPUT
MR
CP
E1
E2
D
Qn
H
X
X
X
X
L
L
L
X
X
X
Q0
L
↑
H
X
X
Q0
L
↑
X
H
X
Q0
L
↑
L
L
L
L
L
↑
L
L
H
H
NOTE:
When either OE1 or OE2 (or both) is (are) high the output is disabled
to the high-impedance state, however, sequential operation of the
flip-flops is not affected.
H = High Voltage Level
L = Low Voltage Level
X = Irrelevant
↑ = Transition from Low to High Level
Q0 = Level Before the Indicated Steady-State Input Conditions Were
Established
2
CD74HC173, CD74HCT173
Logic Diagram
9
E1
10
E2
D
Q
14
VCC
P
D0
3
Q0
7
CP
CP
Q
N
R
15
MR
1
OE1
2
OE2
13
4
D1
12
D2
11
3 CIRCUITS IDENTICAL TO ABOVE CIRCUIT
IN DASHED ENCLOSURE
D3
5
Q1
Q2
6
Q3
3
CD74HC173, CD74HCT173
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
VIH
-
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
-7.8
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
7.8
6
-
-
0.26
-
0.33
-
0.4
V
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
VIL
VOH
-
VIH or
VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
-
-
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
4
CD74HC173, CD74HCT173
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
IOZ
VIL or
VIH
-
High Level Input
Voltage
VIH
-
Low Level Input
Voltage
VIL
High Level Output
Voltage
CMOS Loads
VOH
Three-State Leakage
Current
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
6
-
-
±0.5
-
±0.5
-
±10
µA
-
4.5 to
5.5
2
-
-
2
-
2
-
V
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
VIH or
VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-6
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
6
4.5
-
-
0.26
-
0.33
-
0.4
V
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
II
VCC to
GND
0
5.5
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
Three-State Leakage
Current
IOZ
VIL or
VIH
-
5.5
-
-
±0.5
-
±5.0
-
±10
µA
Input Leakage
Current
Quiescent Device
Current
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
D0-D3
0.15
E1 and E2
0.15
CP
0.25
MR
0.2
OE1 and OE2
0.5
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.
5
CD74HC173, CD74HCT173
Switching Specifications
PARAMETER
Input tr, tf = 6ns
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
VCC (V)
-40oC TO 85oC -55oC TO 125oC
TYP
MAX
MAX
MAX
UNITS
HC TYPES
Propagation Delay, Clock to
Output
Propagation Delay, MR to
Output
Propagation Delay Output
Enable to Q (Figure 6)
Output Transition Times
Maximum Clock Frequency
tPHL
tPLZ, tPHZ
tPZL, tPZH
tTLH, tTHL
fMAX
2
-
200
250
300
ns
4.5
-
40
50
60
ns
CL = 15pF
5
17
-
-
-
ns
CL = 50pF
6
-
34
43
51
ns
CL = 50pF
2
-
175
220
265
ns
4.5
-
35
44
53
ns
CL = 15pF
5
12
-
-
-
ns
CL = 50pF
6
-
30
37
45
ns
CL = 50pF
2
150
190
225
ns
CL = 50pF
4.5
30
38
45
ns
CL = 15pF
5
-
-
-
ns
CL = 50pF
6
26
33
38
ns
CL = 50pF
CL = 15pF
12
2
-
60
75
90
ns
4.5
-
12
15
18
ns
6
-
10
13
15
ns
5
60
-
-
-
MHz
Input Capacitance
CIN
-
-
-
10
10
10
pF
Three-State Output
Capacitance
CO
-
-
-
10
10
10
pF
Power Dissipation
Capacitance
(Notes 5, 6)
CPD
-
5
29
-
-
-
pF
CL = 50pF
4.5
-
40
50
60
ns
CL = 15pF
5
17
-
-
-
ns
CL = 50pF
4.5
-
44
55
66
ns
CL = 15pF
5
18
-
-
-
ns
CL = 50pF
2
150
190
225
ns
CL = 50pF
4.5
30
38
45
ns
CL = 15pF
5
14
-
-
-
ns
HCT TYPES
Propagation Delay, Clock to
Output
tPLH, tPHL
Propagation Delay, MR to
Output
tPHL
Propagation Delay Output
Enable to Q (Figure 6)
tPZL, tPZH
Output Transition Times
Maximum Clock Frequency
CL = 50pF
6
26
33
38
ns
tTLH, tTHL
CL = 50pF
4.5
-
15
19
22
ns
fMAX
CL = 15pF
5
60
-
-
-
MHz
Input Capacitance
CIN
-
-
-
10
10
10
pF
Power Dissipation
Capacitance
(Notes 5, 6)
CPD
-
5
34
-
-
-
pF
NOTES:
5. CPD is used to determine the dynamic power consumption, per package.
6. PD = VCC2 fi + ∑ (CL VCC2 + fO) where fi = Input Frequency, fO = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
6
CD74HC173, CD74HCT173
Prerequisite For Switching Specifications
25oC
PARAMETER
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
fMAX
2
6
-
5
-
4
-
MHz
4.5
30
-
24
-
20
-
MHz
6
35
-
28
-
24
-
MHz
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
2
60
-
75
-
90
-
ns
4.5
12
-
15
-
18
-
ns
6
10
-
13
-
15
-
ns
2
3
-
3
-
3
-
ns
4.5
3
-
3
-
3
-
ns
6
3
-
3
-
3
-
ns
2
0
-
0
-
0
-
ns
4.5
0
-
0
-
0
-
ns
6
0
-
0
-
0
-
ns
2
60
-
75
-
90
-
ns
4.5
12
-
15
-
18
-
ns
6
10
-
13
-
15
-
ns
fMAX
4.5
20
-
16
-
13
-
MHz
MR Pulse Width
tw
4.5
15
-
19
-
22
-
ns
Clock Pulse Width
tw
4.5
25
-
31
-
38
-
ns
Set-up Time, E to Clock
tSU
4.5
12
-
15
-
18
-
ns
Set-up Time, Data to Clock
tSU
4.5
18
-
23
-
27
-
ns
Hold Time, Data to Clock
tH
4.5
0
-
0
-
0
-
ns
Hold Time, E to Clock
tH
4.5
0
-
0
-
0
-
ns
tREM
4.5
12
-
15
-
18
-
ns
HC TYPES
Maximum Clock Frequency
MR Pulse Width
Clock Pulse Width
Set-up Time, Data to Clock
and E to Clock
Hold Time, Data to Clock
Hold Time, E to Clock
Removal Time, MR to Clock
tw
tw
tSU
tH
tH
tREM
HCT TYPES
Maximum Clock Frequency
Removal Time, MR to Clock
7
CD74HC173, CD74HCT173
Test Circuits and Waveforms
tWL + tWH =
tfCL
trCL
50%
10%
10%
tf = 6ns
tr = 6ns
GND
tTLH
90%
INVERTING
OUTPUT
tPHL
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
trCL
VCC
tfCL
GND
1.3V
0.3V
GND
tH(H)
tH(L)
VCC
DATA
INPUT
3V
2.7V
CLOCK
INPUT
50%
tH(H)
tPLH
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tfCL
10%
tTLH
1.3V
10%
tPLH
90%
GND
tTHL
90%
50%
10%
trCL
3V
2.7V
1.3V
0.3V
INPUT
tTHL
tPHL
tWH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
VCC
INVERTING
OUTPUT
GND
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
tf = 6ns
90%
50%
10%
1.3V
1.3V
tWL
tWH
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
INPUT
1.3V
0.3V
0.3V
GND
tr = 6ns
DATA
INPUT
50%
tH(L)
3V
1.3V
1.3V
1.3V
GND
tSU(H)
tSU(H)
tSU(L)
tTLH
90%
OUTPUT
tTHL
90%
50%
10%
tTLH
90%
1.3V
OUTPUT
tREM
3V
SET, RESET
OR PRESET
GND
tTHL
1.3V
10%
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
tPHL
1.3V
GND
IC
CL
50pF
GND
90%
tPLH
50%
IC
tSU(L)
tPHL
tPLH
I
fCL
3V
2.7V
CLOCK
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
tREM
VCC
SET, RESET
OR PRESET
tfCL = 6ns
fCL
50%
50%
tWL
CLOCK
INPUT
tWL + tWH =
trCL = 6ns
VCC
90%
CLOCK
I
CL
50pF
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
8
Test Circuits and Waveforms
6ns
(Continued)
6ns
OUTPUT
DISABLE
90%
50%
10%
OUTPUTS
ENABLED
2.7
1.3
OUTPUT HIGH
TO OFF
50%
OUTPUTS
DISABLED
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
IC WITH
THREESTATE
OUTPUT
GND
1.3V
tPZH
90%
OUTPUTS
ENABLED
OUTPUTS
ENABLED
0.3
10%
tPHZ
tPZH
90%
3V
tPZL
tPLZ
OUTPUT LOW
TO OFF
50%
OUTPUT HIGH
TO OFF
6ns
GND
10%
tPHZ
tf
OUTPUT
DISABLE
tPZL
tPLZ
OUTPUT LOW
TO OFF
6ns
tr
VCC
1.3V
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OUTPUT
RL = 1kΩ
CL
50pF
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZH
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to
VCC, CL = 50pF.
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
9
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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