CAT9555 16-bit I2C and SMBus I/O Port with Interrupt Description The CAT9555 is a CMOS device that provides 16−bit parallel input/output port expansion for I2 C and SMBus compatible applications. These I/O expanders provide a simple solution in applications where additional I/Os are needed: sensors, power switches, LEDs, pushbuttons, and fans. The CAT9555 consists of two 8−bit Configuration ports (input or output), Input, Output and Polarity inversion registers, and an I2C/SMBus−compatible serial interface. Any of the sixteen I/Os can be configured as an input or output by writing to the configuration register. The system master can invert the CAT9555 input data by writing to the active−high polarity inversion register. The CAT9555 features an active low interrupt output which indicates to the system master that an input state has changed. The three address input pins provide the device’s extended addressing capability and allow up to eight devices to share the same bus. The fixed part of the I2C slave address is the same as the CAT9554, allowing up to eight of these devices in any combination to be connected on the same bus. http://onsemi.com Applications • White Goods (dishwashers, washing machines) • Handheld Devices (cell phones, PDAs, digital cameras) • Data Communications (routers, hubs and servers) TQFN−24 HV6 SUFFIX CASE 510AG TQFN−24 HT6 SUFFIX CASE 510AN A3B CAT9555WI YMXXXX I2C 400 kHz Bus Compatible 2.3 V to 5.5 V Operation Low Stand−by Current 5 V Tolerant I/Os 16 I/O Pins that Default to Inputs at Power−up High Drive Capability Individual I/O Configuration Polarity Inversion Register Active Low Interrupt Output Internal Power−on Reset No Glitch on Power−up Noise Filter on SDA/SCL Inputs Cascadable up to 8 Devices Industrial Temperature Range 24−lead SOIC and TSSOP, and 24−pad TQFN (4 x 4 mm) Packages These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant TSSOP−24 Y SUFFIX CASE 948AR MARKING DIAGRAMS Features • • • • • • • • • • • • • • • • SOIC−24 W SUFFIX CASE 751BK AB CAT9555YI 3YMXXX (SOIC) (TSSOP) A = Assembly Location 3 = Matte−Tin Lead Finish B = Product Revision (Fixed as “B”) CAT955W = Device Code (SOIC) CAT9555Y = Device Code (TSSOP) I = Industrial Temperature Range Y = Production Year (Last Digit) M = Production Month (1−9, O, N, D) XXX = Last Three Digits of Assembly Lot Number XXXX = Last Four Digits of Assembly Lot Number HHHH AXXX YMCC (TQFN) HHHH = Device Code MAAB = HT6 LAAB = HV6 A XXX Y M CC = Assembly Location = Last Three Digits of Assembly Lot Number = Production Year (Last Digit) = Production Month (1−9, O, N, D) = Country Code TH = Thailand MY = Malaysia ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. © Semiconductor Components Industries, LLC, 2011 June, 2011 − Rev. 11 1 Publication Order Number: CAT9555/D SCL SDA VCC INT VCC 1 A1 INT A2 CAT9555 A1 SDA A2 I/O0.0 A0 I/O0.0 SCL A0 I/O0.1 I/O1.7 I/O0.1 I/O1.7 I/O0.2 I/O1.6 I/O0.2 I/O1.6 I/O0.3 I/O1.5 I/O0.3 I/O1.5 I/O0.4 I/O1.4 I/O0.4 I/O1.4 I/O0.5 I/O1.3 I/O0.5 I/O1.3 SOIC (W), TSSOP (Y) (Top View) I/O1.2 I/O1.1 I/O1.0 I/O1.0 VSS I/O1.1 VSS I/O0.6 I/O1.2 I/O0.7 I/O0.6 I/O0.7 1 TQFN (HV6, HT6) (Top View) Figure 1. Pin Configurations A0 8−BIT A1 A2 INPUT/ OUTPUT WRITE pulse PORTS READ pulse I2C/SMBUS CONTROL SCL SDA VCC VSS INPUT FILTER POWER−ON RESET 8−BIT INPUT/ OUTPUT WRITE pulse PORTS READ pulse LP FILTER I/O1.0 I/O1.1 I/O1.2 I/O1.3 I/O1.4 I/O1.5 I/O1.6 I/O1.7 I/O0.0 I/O0.1 I/O0.2 I/O0.3 I/O0.4 I/O0.5 VINT I/O0.6 I/O0.7 INT Note: All I/Os are set to inputs at RESET. Figure 2. Block Diagram http://onsemi.com 2 CAT9555 Table 1. PIN DESCRIPTION SOIC / TSSOP TQFN Pin Name Function 1 22 INT Interrupt Output (open drain) 2 23 A1 Address Input 1 3 24 A2 Address Input 2 4−11 1−8 I/O0.0 − I/O0.7 12 9 VSS 13−20 10−17 I/O1.0 − I/O1.7 21 18 A0 22 19 SCL Serial Clock 23 20 SDA Serial Data 24 21 VCC Power Supply I/O Port 0.0 to I/O Port 0.7 Ground I/O Port 1.0 to I/O Port 1.7 Address Input 0 Table 2. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units VCC with Respect to Ground −0.5 to +6.5 V Voltage on Any Pin with Respect to Ground −0.5 to +5.5 V DC Current on I/O1.0 to I/O1.7, I/O0.0 to I/O0.7 ±50 mA DC Input Current ±20 mA VCC Supply Current 160 mA VSS Supply Current 200 mA Package Power Dissipation Capability (TA = 25°C) 1.0 W Junction Temperature +150 °C Storage Temperature −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. RELIABILITY CHARACTERISTICS Symbol Parameter VZAP (Note 1) ESD Susceptibility ILTH (Note 1) Latch−up Reference Test Method Min Units JEDEC Standard JESD 22 2000 V JEDEC JESD78A 100 mA 1. This parameter is tested initially and after a design or process change that affects the parameter. http://onsemi.com 3 CAT9555 Table 4. D.C. OPERATING CHARACTERISTICS (VCC = 2.3 V to 5.5 V; VSS = 0 V; TA = −40°C to +85°C, unless otherwise specified.) Symbol Parameter Conditions Min Typ Max Unit 2.3 − 5.5 V SUPPLIES VCC Supply voltage ICC Supply current Operating mode; VCC = 5.5 V; no load; fSCL = 100 kHz − 135 200 mA Istbl Standby current Standby mode; VCC = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs − 1.1 1.5 mA Istbh Standby current Standby mode; VCC = 5.5 V; no load; VI = VCC; fSCL = 0 kHz; I/O = inputs − 0.75 1 mA Power−on reset voltage No load; VI = VCC or VSS − 1.5 1.65 V VPOR SCL, SDA, INT VIL (Note 2) Low level input voltage −0.5 − 0.3 x VCC V VIH (Note 2) High level input voltage 0.7 x VCC − 5.5 V IOL Low level output current VOL = 0.4 V 3 − − mA Leakage current VI = VCC = VSS −1 − +1 mA CI (Note 3) IL Input capacitance VI = VSS − − 6 pF CO (Note 3) Output capacitance VO = VSS − − 8 pF A0, A1, A2 VIL (Note 2) Low level input voltage −0.5 − 0.3 x VCC V VIH (Note 2) High level input voltage 0.7 x VCC − 5.5 V −1 − 1 mA ILI Input leakage current VIL Low level input voltage −0.5 − 0.3 x VCC V VIH High level input voltage 0.7 x VCC − 5.5 V IOL Low level output current VOL = 0.5 V; VCC = 2.3 V to 5.5 V (Note 4) 8 8 to 20 − mA VOL = 0.7 V; VCC = 2.3 V to 5.5 V (Note 4) 10 10 to 24 − IOH = −8 mA; VCC = 2.3 V (Note 5) 1.8 − − IOH = −10 mA; VCC = 2.3 V (Note 5) 1.7 − − IOH = −8 mA; VCC = 3.0 V (Note 5) 2.6 − − IOH = −10 mA; VCC = 3.0 V (Note 5) 2.5 − − IOH = −8 mA; VCC = 4.75 V (Note 5) 4.1 − − IOH = −10 mA; VCC = 4.75 V (Note 5) 4.0 − − I/Os VOH High level output voltage V IIH Input leakage current VCC = 3.6 V; VI = VCC − − 1 mA IIL Input leakage current VCC = 5.5 V; VI = VSS − − −100 mA CI (Note 3) Input capacitance − − 5 pF CO (Note 3) Output capacitance − − 8 pF 2. VIL min and VIH max are reference values only and are not tested. 3. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 4. Each I/Os must be externally limited to a maximum of 25 mA and each octal (I/O0.0 to I/O0.7 and I/O1.0 to I/O1.7) must be limited to a maximum current of 100 mA for a device total of 200 mA. 5. The total current sourced by all I/Os must be limited to 160 mA. http://onsemi.com 4 CAT9555 Table 5. A.C. CHARACTERISTICS (VCC = 2.3 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified) (Note 6) Standard I2C Min Parameter Symbol FSCL Clock Frequency tHD:STA Max Fast I2C Min 100 START Condition Hold Time Max Units 400 kHz 4 0.6 ms tLOW Low Period of SCL Clock 4.7 1.3 ms tHIGH High Period of SCL Clock 4 0.6 ms 4.7 0.6 ms tSU:STA START Condition Setup Time tHD:DAT Data In Hold Time 0 0 ms tSU:DAT Data In Setup Time 250 100 ns tR (Note 7) SDA and SCL Rise Time tF (Note 7) 1000 SDA and SCL Fall Time tSU:STO 300 STOP Condition Setup Time tBUF (Note 7) Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH Data Out Hold Time Ti (Note 7) 300 ns 300 ns 4 0.6 ms 4.7 1.3 ms 3.5 100 Noise Pulse Filtered at SCL and SDA Inputs 0.9 50 100 ms ns 100 ns PORT TIMING tPV Output Data Valid 200 ns tPS Input Data Setup Time 100 ns tPH Input Data Hold Time 1 ms INTERRUPT TIMING tIV Interrupt Valid 4 ms tIR Interrupt Reset 4 ms 6. Test conditions according to “AC Test Conditions” table. 7. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. Table 6. A.C. TEST CONDITIONS Input Rise and Fall time ≤ 10 ns CMOS Input Voltages 0.2 VCC to 0.8 VCC CMOS Input Reference Voltages 0.3 VCC to 0.7 VCC Output Reference Voltages 0.5 VCC Output Load: SDA, INT Current Source: IOL = 3 mA; CL = 100 pF Output Load: I/Os Current Source: IOL/IOH = 10 mA; CL = 50 pF tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tDH tAA SDA OUT Figure 3. I2C Serial Interface Timing http://onsemi.com 5 tBUF CAT9555 Pin Description A0, A1, A2: Device Address Inputs These inputs are used for extended addressing capability. The A0, A1, A2 pins should be hardwired to VCC or VSS. When hardwired, up to eight CAT9555s may be addressed on a single bus system. The levels on these inputs are compared with corresponding bits, A2, A1, A0, from the slave address byte. SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. The SCL line requires a pull−up resistor if it is driven by an open drain output. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire−ORed with other open drain or open collector outputs. A pull−up resistor must be connected from SDA line to VCC. The value of the pull−up resistor, RP, can be calculated based on minimum and maximum values from Figure 4 and Figure 5 (see Note). I/O0.0 to I/O0.7, I/O1.0 to I/O1.7: Input / Output Ports Any of these pins may be configured as input or output. The simplified schematic of I/O0 to I/O7 is shown in Figure 6. When an I/O is configured as an input, the Q1 and Q2 output transistors are off creating a high impedance input with a weak pull−up resistor (typical 100 kW). If the I/O pin is configured as an output, the push−pull output stage is enabled. Care should be taken if an external voltage is applied to an I/O pin configured as an output due to the low impedance paths that exist between the pin and either VCC or VSS. 8 2.5 IOL = 3 mA @ VOLmax 2.0 6 RPmax (KW) RPmin (KW) Fast Mode I2C Bus / tr max − 300 ns 7 1.5 1.0 5 4 3 2 0.5 1 0 NOTE: 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 0 5.6 0 50 100 150 200 250 300 350 VCC (V) CBUS (pF) Figure 4. Minimum RP as a Function of Supply Voltage Figure 5. Maximum RP Value vs. Bus Capacitance 400 According to the Fast Mode I2C bus specification, for bus capacitance up to 200 pF, the pull up device can be a resistor. For bus loads between 200 pF and 400 pF, the pull−up device can be a current source (Imax = 3 mA) or a switched resistor circuit. http://onsemi.com 6 CAT9555 INT: Interrupt Output Since there are two 8−bit ports that are read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1, or vice versa. Changing an I/O from an output to an input may cause a false interrupt if the state of the pin does not match the contents of the input port register. The open−drain interrupt output is activated when one of the port pins configured as an input changes state (differs from the corresponding input port register bit state). The interrupt is deactivated when the input returns to its previous state or the input port register is read. Data from Shift Register Data from Shift Register Output Port Register Data Configuration Register VCC Q D FF Write Configuration Pulse CK Q1 Q 100 kW Q D FF Write Pulse CK I/O Pin Q Output Port Register Q2 Input Port Register Q D LATCH Read Pulse Data from Shift Register CK Q D Q FF Write Polarity Register CK Q Polarity Inversion Register Figure 6. Simplified Schematic of I/Os http://onsemi.com 7 VSS Input Port Register Data To INT Polarity Register Data CAT9555 FUNCTIONAL DESCRIPTION START and STOP Conditions The CAT9555 general purpose input/output (GPIO) peripheral provides up to sixteen I/O ports, controlled through an I2C compatible serial interface. The CAT9555 supports the I2C Bus data transmission protocol. This Inter−Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT9555 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT9555 monitors the SDA and SCL lines and will not respond until this condition is met. A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. Device Addressing After the bus Master sends a START condition, a slave address byte is required to enable the CAT9555 for a read or write operation. The four most significant bits of the slave address are fixed as binary 0100 (Figure 8). The CAT9555 uses the next three bits as address bits. The address bits A2, A1 and A0 are used to select which device is accessed from maximum eight devices on the same bus. These bits must compare to their hardwired input pins. The 8th bit following the 7−bit slave address is the R/W bit that specifies whether a read or write operation is to be performed. When this bit is set to “1”, a read operation is initiated, and when set to “0”, a write operation is selected. Following the START condition and the slave address byte, the CAT9555 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT9555 then performs a read or a write operation depending on the state of the R/W bit. I2C Bus Protocol The features of the I2C bus protocol are defined as follows: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition (Figure 7). SCL SDA START CONDITION STOP CONDITION Figure 7. START/STOP Condition SLAVE ADDRESS 0 1 0 FIXED 0 A2 A1 A0 R/W PROGRAMMABLE HARDWARE SELECTABLE Figure 8. CAT9555 Slave Address Acknowledge When the CAT9555 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT9555 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a stop condition to return the CAT9555 to the standby power mode and place the device in a known state. After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The SDA line remains stable LOW during the HIGH period of the acknowledge related clock pulse (Figure 9). The CAT9555 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each data byte. http://onsemi.com 8 CAT9555 Registers and Bus Transactions Table 7. REGISTER COMMAND BYTE The CAT9555 internal registers and their address and function are shown in Table 7. The command byte is the first byte to follow the device address byte during a write/read bus transaction. The register command byte acts as a pointer to determine which register will be written or read. The input port register is a read only port. It reflects the incoming logic levels of the I/O pins, regardless of whether the pin is defined as an input or an output by the configuration register. Writes to the input port register are ignored. Command (hex) Register 0h Input Port 0 1h Input Port 1 2h Output Port 0 3h Output Port 1 4h Polarity Inversion Port 0 5h Polarity Inversion Port 1 6h Configuration Port 0 7h Configuration Port 1 Table 8. REGISTERS 0 AND 1 – INPUT PORT REGISTERS bit I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0 default X X X X X X X X bit I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0 default X X X X X X X X O0.3 O0.2 O0.1 O0.0 Table 9. REGISTERS 2 AND 3 – OUTPUT PORT REGISTERS bit O0.7 O0.6 O0.5 O0.4 default 1 1 1 1 1 1 1 1 bit O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0 default 1 1 1 1 1 1 1 1 Table 10. REGISTERS 4 AND 5 – POLARITY INVERSION REGISTERS bit N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0 default 0 0 0 0 0 0 0 0 bit N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0 default 0 0 0 0 0 0 0 0 Table 11. REGISTERS 6 AND 7 – CONFIGURATION REGISTERS bit C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0 default 1 1 1 1 1 1 1 1 bit C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0 default 1 1 1 1 1 1 1 1 BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 8 BUS RELEASE DELAY (RECEIVER) 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK DELAY (≤ tAA) Figure 9. Acknowledge Timing http://onsemi.com 9 ACK SETUP (≥ tSU:DAT) CAT9555 Writing to the Port Registers The output port register sets the outgoing logic levels of the I/O ports, defined as outputs by the configuration register. Bit values in this register have no effect on I/O pins defined as inputs. Reads from the output port register reflect the value that is in the flip-flop controlling the output, not the actual I/O pin value. The polarity inversion register allows the user to invert the polarity of the input port register data. If a bit in this register is set (“1”) the corresponding input port data is inverted. If a bit in the polarity inversion register is cleared (“0”), the original input port polarity is retained. The configuration register sets the directions of the ports. Set the bit in the configuration register to enable the corresponding port pin as an input with a high impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At power-up, the I/Os are configured as inputs with a weak pull-up resistor to VCC. 1 2 3 4 5 6 7 8 Data is transmitted to the CAT9555 registers using the write mode shown in Figure 10 and Figure 11. The CAT9555 registers are configured to operate at four register pairs: Input Ports, Output Ports, Polarity Inversion Ports and Configuration Ports. After sending data to one register, the next data byte will be sent to the other register in the pair. For example, if the first byte of data is sent to the Configuration Port 1 (register 7), the next byte will be stored in the Configuration Port 0 (register 6). Each 8-bit register may be updated independently of the other registers. Reading the Port Registers The CAT9555 registers are read according to the timing diagrams shown in Figure 12 and Figure 13. Data from the register, defined by the command byte, will be sent serially on the SDA line. Data is clocked into the register on the failing edge of the acknowledge clock pulse. After the first byte is read, additional data bytes may be read, but the second read will reflect the data from the other register in the pair. For example, if the first read is data from Input Port 0, the next read data will be from Input Port 1. The transfer is stopped when the master will not acknowledge the data byte received and issue the STOP condition. 9 SCL command byte slave address data to port 0 SDA S 0 1 0 0 A2 A1 A0 0 A 0 0 0 0 0 0 1 0 A 0.7 start condition R/W acknowledge from slave DATA 0 data to port 1 0.0 A 1.7 1.0 A P DATA 1 acknowledge from slave acknowledge from slave stop condition WRITE TO PORT DATA OUT FROM PORT 0 tpv DATA VALID DATA OUT FROM PORT 1 tpv Figure 10. Write to Output Port Register SCL 1 2 4 5 6 7 8 9 1 1 2 3 4 5 6 7 8 9 command byte slave address SDA S 0 3 0 0 A2 A1 A0 0 start condition R/W A 0 0 0 acknowledge from slave 0 0A 1 1 1 2 3 4 5 6 7 data to configuration 0 0 A MSB DATA 0 Figure 11. Write to Configuration Register 10 9 1 2 3 4 5 data to configuration 1 LSB A MSB acknowledge from slave http://onsemi.com 8 DATA 1 acknowledge from slave LSB A P CAT9555 Power-On Reset Operation When the power supply is applied to VCC pin, an internal power-on reset pulse holds the CAT9555 in a reset state until VCC reaches VPOR level. At this point, the reset condition is released and the internal state machine and the CAT9555 registers are initialized to their default state. slave address acknowledge from slave acknowledge from slave 1 0 0 A2 A1 A0 0 A S 0 COMMAND BYTE R/W NOTE: acknowledge from slave slave address A S 0 0 1 0 A2 A1 A0 1 A MSB at this moment master−transmitter becomes master−receiver and slave−receiver becomes slave−transmitter LSB A DATA first byte R/W data from upper or lower byte of no acknowledge register from master Transfer can be stopped at any time by a STOP condition. MSB DATA LSB NA P last byte Figure 12. Read from Register SCL data from lower or upper byte acknowledge of register from master 1 2 3 4 5 6 7 8 9 SDA S 0 1 0 0 A2A1A0 1 A R/W I0.x I1.x DATA 00 ACKNOWLEDGE FROM SLAVE A DATA 10 ACKNOWLEDGE FROM MASTER tph READ FROM PORT 0 DATA INTO PORT 0 DATA 00 READ FROM PORT 1 DATA INTO PORT 1 INT NOTE: tIV DATA 01 I0.x A DATA 03 ACKNOWLEDGE FROM MASTER tps DATA 02 A DATA 12 ACKNOWLEDGE FROM MASTER 1 P NON ACKNOWLEDGE FROM MASTER DATA 03 tps tph DATA 10 I1.x DATA 11 DATA 12 tIR Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to 00 (read input port register). Figure 13. Read Input Port Register http://onsemi.com 11 CAT9555 PACKAGE DIMENSIONS SOIC−24, 300 mils CASE 751BK−01 ISSUE O E1 SYMBOL MIN A 2.35 2.65 A1 0.10 0.30 A2 2.05 2.55 b 0.31 0.51 c 0.20 0.33 D 15.20 15.40 E 10.11 10.51 E1 7.34 E e PIN#1 IDENTIFICATION MAX 7.60 1.27 BSC e b NOM h 0.25 0.75 L 0.40 1.27 θ 0º 8º θ1 5º 15º TOP VIEW h D A2 A A1 SIDE VIEW h q1 q q1 L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013. http://onsemi.com 12 c CAT9555 PACKAGE DIMENSIONS TSSOP24, 4.4x7.8 CASE 948AR−01 ISSUE A b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 D 7.70 7.80 7.90 E 6.25 6.40 6.55 E1 4.30 4.40 4.50 e L 0.65 BSC 0.50 0.60 0.70 1.00 REF L1 θ 0.20 0º 8º e TOP VIEW D c A2 A θ1 L A1 SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. http://onsemi.com 13 L1 CAT9555 PACKAGE DIMENSIONS TQFN24, 4x4 CASE 510AG−01 ISSUE B A D DETAIL A E E2 PIN#1 ID PIN#1 INDEX AREA TOP VIEW SIDE VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 A3 b 0.20 2.70 e 0.05 0.25 L 0.30 2.80 DETAIL A 2.90 4.00 BSC 2.70 e L b 4.00 BSC E E2 BOTTOM VIEW 0.20 REF D D2 D2 A1 2.80 2.90 0.50 BSC 0.30 0.50 A Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-220. (3) Minimum space between leads and flag cannot be smaller than 0.15 mm. http://onsemi.com 14 FRONT VIEW A3 CAT9555 PACKAGE DIMENSIONS TQFN24, 4x4 TA CASE 510AN−01 ISSUE O A D DETAIL A E E2 PIN#1 ID PIN#1 INDEX AREA TOP VIEW SIDE VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 − 0.05 A3 b 0.20 2.00 0.25 − e L 0.30 DETAIL A 2.20 4.00 BSC 2.00 e L b 4.00 BSC E E2 BOTTOM VIEW 0.20 REF D D2 D2 A1 − 2.20 0.50 BSC 0.30 − 0.50 A Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-220. (3) Minimum space between leads and flag cannot be smaller than 0.15 mm. http://onsemi.com 15 FRONT VIEW A3 CAT9555 Example of Ordering Information (Notes 8 to 12) Prefix Device # Suffix CAT 9555 HV6 Business Group ID Product Number 9555 −G I Temperature Range I = Industrial (−40°C to +85°C) Package W: SOIC Y: TSSOP HV6: TQFN HT6: TQFN T2 Tape & Reel T: Tape & Reel 1: 1,000 / Reel (SOIC Only) 2: 2,000 / Reel Lead Finish G: NiPdAu Blank: Matte−Tin 8. All packages are RoHS−compliant (Lead−free, Halogen−free). 9. The standard lead finish is Matte−Tin for SOIC and TSSOP packages and NiPdAu for TQFN package. 10. The device used in the above example is a CAT9555HV6I−GT2 (TQFN, Industrial Temperature, NiPdAu, Tape & Reel, 2,000/Reel). 11. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 12. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Table 12. ORDERING PART NUMBER Package Lead Finish CAT9555WI Part Number SOIC Matte−Tin CAT9555WI−T1 SOIC Matte−Tin CAT9555YI TSSOP Matte−Tin CAT9555YI−T2 TSSOP Matte−Tin CAT9555HV6I−G TQFN NiPdAu CAT9555HV6I−GT2 TQFN NiPdAu CAT9555HT6I−G TQFN NiPdAu CAT9555HT6I−GT2 TQFN NiPdAu ON Semiconductor is licensed by Philips Corporation to carry the I2C Protocol. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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