CAT9555 16-bit I²C and SMBus I/O Port with Interrupt FEATURES DESCRIPTION 400kHz I²C bus compatible 2.3V to 5.5V operation Low stand-by current 5V tolerant I/Os 16 I/O pins that default to inputs at power-up High drive capability Individual I/O configuration Polarity inversion register Active low interrupt output Internal power-on reset No glitch on power-up Noise filter on SDA/SCL inputs Cascadable up to 8 devices Industrial temperature range RoHS-compliant 24-lead SOIC and TSSOP, and 24-pad TQFN (4 x 4mm) packages The CAT9555 is a CMOS device that provides 16-bit parallel input/output port expansion for I²C and SMBus compatible applications. These I/O expanders provide a simple solution in applications where additional I/Os are needed: sensors, power switches, LEDs, pushbuttons, and fans. The CAT9555 consists of two 8-bit Configuration ports (input or output), Input, Output and Polarity inversion registers, and an I²C/SMBus-compatible serial interface. Any of the sixteen I/Os can be configured as an input or output by writing to the configuration register. The system master can invert the CAT9555 input data by writing to the active-high polarity inversion register. The CAT9555 features an active low interrupt output which indicates to the system master that an input state has changed. The three address input pins provide the device's extended addressing capability and allow up to eight devices to share the same bus. The fixed part of the I²C slave address is the same as the CAT9554, allowing up to eight of these devices in any combination to be connected on the same bus. APPLICATIONS White goods (dishwashers, washing machines) Handheld devices (cell phones, PDAs, digital cameras) Data Communications (routers, hubs and servers) BLOCK DIAGRAM For Ordering Information details, see page 17. (1) A0 I/O1.0 I/O1.1 8-BIT A1 A2 WRITE pulse INPUT/ OUTPUT PORTS READ pulse I2C/SMBUS CONTROL SCL SDA WRITE pulse VSS I/O1.5 I/O1.6 I/O1.7 I/O0.0 I/O0.1 8-BIT INPUT FILTER VCC I/O1.2 I/O1.3 I/O1.4 INPUT/ OUTPUT PORTS READ pulse POWER-ON RESET LP FILTER I/O0.2 I/O0.3 I/O0.4 I/O0.5 VINT I/O0.6 I/O0.7 INT Notes: (1) All I/Os are set to inputs at RESET © 2010 SCILLC. All rights reserved Characteristics subject to change without notice 1 Doc. No. MD-9003, Rev. J CAT9555 PIN CONFIGURATION TQFN 4 x 4mm (HV6, HT6) (Top View) INT 1 24 VCC A2 A1 INT VCC SDA SCL SOIC (W), TSSOP (Y) A1 2 23 SDA 24 23 22 21 20 19 A2 3 22 SCL I/O0.0 4 21 A0 I/O0.4 8 17 I/O1.4 I/O0.5 9 16 I/O1.3 I/O0.6 10 15 I/O1.2 I/O0.7 11 14 I/O1.1 Vss 12 13 I/O1.0 I/O0.2 3 16 I/O1.6 I/O0.3 4 15 I/O1.5 I/O0.4 5 14 I/O1.4 I/O0.5 6 13 I/O1.3 7 8 9 10 11 12 I/O1.2 18 I/O1.5 17 I/O1.7 I/O1.1 I/O0.3 7 2 I/O1.0 19 I/O1.6 I/O0.1 Vss I/O0.2 6 18 A0 I/O0.7 20 I/O1.7 1 I/O0.6 I/O0.1 5 I/O0.0 PIN DESCRIPTION SOIC / TSSOP TQFN Pin Name 1 22 Interrupt Output (open drain) 2 23 ¯¯¯ INT A1 3 24 A2 Address Input 2 4-11 1-8 I/O0.0 - I/O0.7 12 9 VSS 13-20 10-17 I/O1.0 - I/O1.7 21 18 A0 22 19 SCL Serial Clock 23 20 SDA Serial Data 24 21 VCC Power Supply Doc. No. MD-9003 Rev. J 2 Function Address Input 1 I/O Port 0.0 to I/O Port 0.7 Ground I/O Port 1.0 to I/O Port 1.7 Address Input 0 © 2010 SCILLC. All rights reserved Characteristics subject to change without notice CAT9555 ABSOLUTE MAXIMUM RATINGS (1) Parameters VCC with Respect to Ground Voltage on Any Pin with Respect to Ground DC Current on I/O1.0 to I/O1.7, I/O0.0 to I/O0.7 DC Input Current VCC Supply Current VSS Supply Current Package Power Dissipation Capability (TA = 25°C) Junction Temperature Storage Temperature Ratings -0.5 to +6.5 -0.5 to +5.5 ±50 ±20 160 200 1.0 +150 -65 to +150 Units V V mA mA mA mA W ºC ºC RELIABILITY CHARACTERISTICS Symbol VZAP(2) ILTH (2) P Parameter ESD Susceptibility Latch-up Reference Test Method JEDEC Standard JESD 22 JEDEC JESD78A Min 2000 100 Units Volts mA Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) This parameter is tested initially and after a design or process change that affects the parameter. © 2010 SCILLC. All rights reserved Characteristics subject to change without notice 3 Doc. No. MD-9003, Rev. J CAT9555 D.C. OPERATING CHARACTERISTICS VCC = 2.3V to 5.5V; VSS = 0V; TA = -40°C to +85°C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 2.3 — 5.5 V Supplies VCC Supply voltage ICC Supply current Operating mode; VCC = 5.5V; no load; fSCL = 100kHz — 135 200 µA Istbl Standby current Standby mode; VCC = 5.5V; no load; VI = VSS; fSCL = 0kHz; I/O = inputs — 1.1 1.5 mA Istbh Standby current Standby mode; VCC = 5.5V; no load; VI = VCC; fSCL = 0kHz; I/O = inputs — 0.75 1 µA VPOR Power-on reset voltage No load; VI = VCC or VSS — 1.5 1.65 V SCL, SDA, ¯¯¯ INT VIL (1) Low level input voltage -0.5 — 0.3 x VCC V VIH (1) High level input voltage 0.7 x VCC — 5.5 V IOL Low level output current VOL = 0.4V 3 — — mA IL Leakage current VI = VCC = VSS 1– — +1 µA Input capacitance VI = VSS — — 6 pF Output capacitance VO = VSS — — 8 pF CI (2) CO (2) A0, A1, A2 VIL(1) Low level input voltage -0.5 — 0.3 x VCC V VIH(1) High level input voltage 0.7 x VCC — 5.5 V -1 — 1 µA ILI Input leakage current I/Os VIL Low level input voltage -0.5 — 0.3 x VCC V VIH High level input voltage 0.7 x VCC — 5.5 V VOL = 0.5V; (3) VCC = 2..3V to 5.5V 8 8 to 20 — mA VOL = 0.7V; (3) VCC = 2.3V to 5.5V 10 10 to 24 — mA 1.8 — — V 1.7 — — V IOL Low level output current (4) IOH = -8 mA; VCC = 2.3V IOH = -10 mA; VCC = 2.3V VOH High level output voltage IOH = -8 mA; VCC = 3.0V (4) (4) 2.6 — — V IOH = -10 mA; VCC = 3.0V (4) 2.5 — — V IOH = -8 mA; VCC = 4.75V (4) 4.1 — — V 4.0 — — V IOH = -10mA; VCC = 4.75V (4) IIH Input leakage current VCC = 3.6V; VI = VCC — — 1 µA IIL Input leakage current VCC = 5.5V; VI = VSS — — -100 µA CI (2) Input capacitance — — 5 pF CO (2) Output capacitance — — 8 pF Notes: (1) VIL min and VIH max are reference values only and are not tested. (2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (3) Each I/Os must be externally limited to a maximum of 25mA and each octal (I/O0.0 to I/O0.7 and I/O1.0 to I/O1.7) must be limited to a maximum current of 100mA for a device total of 200mA. (4) The total current sourced by all I/Os must be limited to 160mA. Doc. No. MD-9003 Rev. J 4 © 2010 SCILLC. All rights reserved Characteristics subject to change without notice CAT9555 A.C. CHARACTERISTICS VCC = 2.3V to 5.5V; TA = -40°C to +85°C, unless otherwise specified. (1) 2 Symbol Min FSCL tHD:STA 2 Standard I C Parameter Clock Frequency Max Fast I C Min 100 START Condition Hold Time Units Max 400 kHz 4 0.6 µs tLOW Low Period of SCL Clock 4.7 1.3 µs tHIGH High Period of SCL Clock 4 0.6 µs 4.7 0.6 µs tSU:STA START Condition Setup Time tHD:DAT Data In Hold Time 0 0 µs tSU:DAT Data In Setup Time 250 100 ns tR(2) tF(2) tSU:STO tBUF (2) SDA and SCL Rise Time 1000 300 ns SDA and SCL Fall Time 300 300 ns STOP Condition Setup Time Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH Data Out Hold Time Ti (2) Symbol 4 0.6 µs 4.7 1.3 µs 3.5 100 Noise Pulse Filtered at SCL and SDA Inputs Parameter 0.9 50 100 Min µs ns 100 ns Max Units 200 ns Port Timing tPV Output Data Valid tPS Input Data Setup Time 100 ns tPH Input Data Hold Time 1 µs Interrupt Timing tIV Interrupt Valid 4 µs tIR Interrupt Reset 4 µs Notes: (1) Test conditions according to "AC Test Conditions" table. (2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. © 2010 SCILLC. All rights reserved Characteristics subject to change without notice 5 Doc. No. MD-9003, Rev. J CAT9555 A.C. TEST CONDITIONS Input Rise and Fall time ≤ 10ns CMOS Input Voltages 0.2VCC to 0.8VCC CMOS Input Reference Voltages 0.3VCC to 0.7VCC Output Reference Voltages 0.5VCC Output Load: SDA, ¯¯¯ INT Current Source IOL = 3mA; CL = 100pF Output Load: I/Os Current Source: IOL/IOH = 10mA; CL = 50pF tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT Figure 1. I²C Serial Interface Timing Doc. No. MD-9003 Rev. J 6 © 2010 SCILLC. All rights reserved Characteristics subject to change without notice CAT9555 PIN DESCRIPTION SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. The SCL line requires a pull-up resistor if it is driven by an open drain output. A0, A1, A2: Device Address Inputs These inputs are used for extended addressing capability. The A0, A1, A2 pins should be hardwired to VCC or VSS. When hardwired, up to eight CAT9555s may be addressed on a single bus system. The levels on these inputs are compared with corresponding bits, A2, A1, A0, from the slave address byte. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A pullup resistor must be connected from SDA line to VCC. The value of the pull-up resistor, RP, can be calculated based on minimum and maximum values from Figure 2 and Figure 3 (see Note). I/O0.0 to I/O0.7, I/O1.0 to I/O1.7: Input / Output Ports Any of these pins may be configured as input or output. The simplified schematic of I/O0 to I/O7 is shown in Figure 4. When an I/O is configured as an input, the Q1 and Q2 output transistors are off creating a high impedance input with a weak pull-up resistor (typical 100kΩ). If the I/O pin is configured as an output, the push-pull output stage is enabled. Care should be taken if an external voltage is applied to an I/O pin configured as an output due to the low impedance paths that exist between the pin and either VCC or VSS. IOL = 3mA @ VOLmax Fast Mode I²C Bus / tr max - 300ns 8.00 RPmax (KΩ) RPmin (KΩ) 2.5 2 1.5 1 0.5 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0 2 2.4 2.8 3.2 3.6 4 0.00 4.4 4.8 5.2 5.6 VCC (V) 50 100 150 200 250 300 350 400 CBUS (pF) Figure 2. Minimum RP as a Function of Supply Voltage Figure 3. Maximum RP Value versus Bus Capacitance Note: According to the Fast Mode I²C bus specification, for bus capacitance up to 200pF, the pull up device can be a resistor. For bus loads between 200pF and 400pF, the pull-up device can be a current source (Imax = 3mA) or a switched resistor circuit. © 2010 SCILLC. All rights reserved Characteristics subject to change without notice 7 Doc. No. MD-9003, Rev. J CAT9555 ¯¯¯ INT : Interrupt Output The open-drain interrupt output is activated when one of the port pins configured as an input changes state (differs from the corresponding input port register bit state). The interrupt is deactivated when the input returns to its previous state or the input port register is read. Data from Shift Register Data from Shift Register Since there are two 8-bit ports that are read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1, or vice versa. Changing an I/O from an output to an input may cause a false interrupt if the state of the pin does not match the contents of the input port register. Output Port Register Data Configuration Register D Q VCC FF Write Configuration Pulse CK Q1 100kΩ Q D Q FF I/O Pin Write Pulse CK Q Output Port Register Q2 Input Port Register D Q Input Port Register Data CK Q To INT D Q Polarity Register Data LATCH Read Pulse Data from Shift Register VSS FF Write Polarity Register CK Q Polarity Inversion Register Figure 4. Simplified Schematic of I/Os Doc. No. MD-9003 Rev. J 8 © 2010 SCILLC. All rights reserved Characteristics subject to change without notice CAT9555 FUNCTIONAL DESCRIPTION SDA and SCL lines and will not respond until this condition is met. The CAT9555 general purpose input/output (GPIO) peripheral provides up to sixteen I/O ports, controlled through an I²C compatible serial interface A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. The CAT9555 supports the I²C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT9555 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. DEVICE ADDRESSING After the bus Master sends a START condition, a slave address byte is required to enable the CAT9555 for a read or write operation. The four most significant bits of the slave address are fixed as binary 0100 (Figure 6). The CAT9555 uses the next three bits as address bits. The address bits A2, A1 and A0 are used to select which device is accessed from maximum eight devices on the same bus. These bits must compare to their hardwired input pins. The 8th bit following the 7bit slave address is the R/ ¯W¯ bit that specifies whether a read or write operation is to be performed. When this bit is set to “1”, a read operation is initiated, and when set to “0”, a write operation is selected. I²C BUS PROTOCOL The features of the I²C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition (Figure 5). Following the START condition and the slave address byte, the CAT9555 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT9555 then performs a read or a write operation ¯¯ bit. depending on the state of the R/W START AND STOP CONDITIONS The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT9555 monitors the SCL SDA START CONDITION STOP CONDITION Figure 5. START/STOP Condition SLAVE ADDRESS 0 1 0 FIXED 0 A2 A1 A0 R/W PROGRAMMABLE HARDWARE SELECTABLE Figure 6. CAT9555 Slave Address © 2010 SCILLC. All rights reserved Characteristics subject to change without notice 9 Doc. No. MD-9003, Rev. J CAT9555 The command byte is the first byte to follow the device address byte during a write/read bus transaction. The register command byte acts as a pointer to determine which register will be written or read. ACKNOWLEDGE After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The SDA line remains stable LOW during the HIGH period of the acknowledge related clock pulse (Figure 7). The input port register is a read only port. It reflects the incoming logic levels of the I/O pins, regardless of whether the pin is defined as an input or an output by the configuration register. Writes to the input port register are ignored. The CAT9555 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each data byte. Table 2. Registers 0 and 1 – Input Port Registers When the CAT9555 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT9555 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a stop condition to return the CAT9555 to the standby power mode and place the device in a known state. bit I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0 default X X X X X X X X bit I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0 default X X X X X X X X Table 3. Registers 2 and 3 – Output Port Registers bit O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0 default 1 1 1 1 1 1 1 1 bit O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0 default 1 1 1 1 1 1 1 1 REGISTERS AND BUS TRANSACTIONS Table 4. Registers 4 and 5 – Polarity Inversion Registers The CAT9555 internal registers and their address and function are shown in Table 1. Table 1. Register Command Byte Command (hex) Register bit N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0 default 0 0 0 0 0 0 0 0 bit N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0 default 0 0 0 0 0 0 0 0 0h Input Port 0 1h Input Port 1 2h Output Port 0 3h Output Port 1 4h Polarity Inversion Port 0 bit C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0 5h Polarity Inversion Port 1 default 1 1 1 1 1 1 1 1 6h Configuration Port 0 bit C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0 7h Configuration Port 1 default 1 1 1 1 1 1 1 1 Table 5. Registers 6 and 7 – Configuration Registers BUS RELEASE DELAY (RECEIVER) BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK SETUP (≥ tSU:DAT) ACK DELAY (≤ tAA) Figure 7. Acknowledge Timing Doc. No. MD-9003 Rev. J 10 © 2010 SCILLC. All rights reserved Characteristics subject to change without notice CAT9555 The output port register sets the outgoing logic levels of the I/O ports, defined as outputs by the configuration register. Bit values in this register have no effect on I/O pins defined as inputs. Reads from the output port register reflect the value that is in the flip-flop controlling the output, not the actual I/O pin value. The CAT9555 registers are configured to operate at four register pairs: Input Ports, Output Ports, Polarity Inversion Ports and Configuration Ports. After sending data to one register, the next data byte will be sent to the other register in the pair. For example, if the first byte of data is sent to the Configuration Port 1 (register 7), the next byte will be stored in the Configuration Port 0 (register 6). Each 8-bit register may be updated independently of the other registers. The polarity inversion register allows the user to invert the polarity of the input port register data. If a bit in this register is set (“1”) the corresponding input port data is inverted. If a bit in the polarity inversion register is cleared (“0”), the original input port polarity is retained. Reading the Port Registers The CAT9555 registers are read according to the timing diagrams shown in Figure 10 and Figure 11. Data from the register, defined by the command byte, will be sent serially on the SDA line. Data is clocked into the register on the failing edge of the acknowledge clock pulse. After the first byte is read, additional data bytes may be read, but the second read will reflect the data from the other register in the pair. For example, if the first read is data from Input Port 0, the next read data will be from Input Port 1. The transfer is stopped when the master will not acknowledge the data byte received and issue the STOP condition. The configuration register sets the directions of the ports. Set the bit in the configuration register to enable the corresponding port pin as an input with a high impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At power-up, the I/Os are configured as inputs with a weak pull-up resistor to VCC. Writing to the Port Registers Data is transmitted to the CAT9555 registers using the write mode shown in Figure 8 and Figure 9. 1 SCL 2 3 4 5 6 7 8 9 command byte slave address SDA S 0 1 0 0 A2 A1 A0 start condition 0 R/W A 0 0 0 0 0 data to port 0 0 1 0 A acknowledge from slave 0.7 data to port 1 DATA 0 A 1.7 0.0 acknowledge from slave DATA 1 1.0 acknowledge from slave A P stop condition WRITE TO PORT DATA OUT FROM PORT 0 tpv DATA OUT FROM PORT 1 DATA VALID tpv Figure 8. Write to Output Port Register 1 SCL 2 3 4 5 6 7 8 9 1 2 S 0 1 start condition 0 0 A2 A1 A0 4 5 6 7 8 9 1 command byte slave address SDA 3 0 R/W A 0 0 acknowledge from slave 0 0 0A 1 2 3 4 5 6 7 8 9 1 data to configuration 0 1 0 A MSB DATA 0 acknowledge from slave 2 3 4 5 data to configuration 1 LSB A MSB DATA 1 LSB A P acknowledge from slave Figure 9. Write to Configuration Register © 2010 SCILLC. All rights reserved Characteristics subject to change without notice 11 Doc. No. MD-9003, Rev. J CAT9555 Power-On Reset Operation the reset condition is released and the internal state machine and the CAT9555 registers are initialized to their default state. When the power supply is applied to VCC pin, an internal power-on reset pulse holds the CAT9555 in a reset state until VCC reaches VPOR level. At this point, acknowledge from slave slave address S 0 1 0 0 A2 A1 A0 acknowledge from slave COMMAND BYTE A 0 A S slave address 0 0 1 0 data from lower or upper byte of register acknowledge from slave A2 A1 A0 1 DATA A MSB at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter LSB data from upper or lower byte of register MSB Note: Transfer can be stopped at any time by a STOP condition. A first byte R/W R/W acknowledge from master no acknowledge from master LSB NA DATA P last byte Figure 10. Read from Register SCL 1 2 3 4 5 6 7 8 9 I0.x SDA S 0 1 0 0 A2 A1 A0 1 A DATA 00 R/W ACKNOWLEDGE FROMSLAVE I1.x A DATA 10 ACKNOWLEDGE FROMMASTER I0.x A DATA 03 ACKNOWLEDGE FROM MASTER I1.x A DATA 12 P ACKNOWLEDGE FROM MASTER tps tph 1 NON ACKNOWLEDGE FROM MASTER READFROMPORT 0 DATA 00 DATA INTO PORT 0 DATA 01 DATA 02 DATA 03 tph READFROMPORT 1 DATA 10 DATA INTO PORT 1 tps DATA 11 DATA 12 INT tIV Note: tIR Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to 00 (read input port register). Figure 11. Read Input Port Register Doc. No. MD-9003 Rev. J 12 © 2010 SCILLC. All rights reserved Characteristics subject to change without notice CAT9555 PACKAGE OUTLINE DRAWINGS SOIC 24-LEAD 300MILS (W) (1) (2) E1 SYMBOL MIN A 2.35 2.65 A1 0.10 0.30 A2 2.05 2.55 b 0.31 0.51 E e PIN#1 IDENTIFICATION MAX c 0.20 0.33 D 15.20 15.40 E 10.11 10.51 E1 7.34 7.60 e b NOM 1.27 BSC h 0.25 0.75 1.27 L 0.40 θ 0° 8° θ1 5° 15° TOP VIEW h D A2 A A1 SIDE VIEW h θ1 θ θ1 L c END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-013 © 2010 SCILLC. All rights reserved Characteristics subject to change without notice 13 Doc. No. MD-9003, Rev. J CAT9555 TSSOP 24-LEAD 4.4MM (Y) (1) (2) b SYMBOL MIN NOM A A1 E1 E MAX 1.20 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 D 7.70 0.20 7.80 7.90 E 6.25 6.40 6.55 E1 4.30 4.40 4.50 e 0.65 BSC L 1.00 REF L1 0.50 θ1 0° 0.60 0.70 8° e TOP VIEW D c A2 A θ1 L1 A1 L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-153. Doc. No. MD-9003 Rev. J 14 © 2010 SCILLC. All rights reserved Characteristics subject to change without notice CAT9555 TQFN 24-PAD 4 X 4MM (HV6) (1)(2)(3) A D DETAIL A E E2 PIN#1 ID PIN#1 INDEX AREA T O P V IE W SYMBOL SIDE VIEW MIN NOM A 0.70 0.75 A1 0.00 A3 b 0.20 b 0.80 e 0.05 L 0.25 0.30 2.80 DETAIL A 2.90 4.00 BSC 2.70 e L MAX 4.00 BSC 2.70 E E2 B O T T O M V IE W 0.20 REF D D2 D2 A1 2.80 2.90 0.50 BSC 0.30 0.50 A FRONT VIEW A3 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-220 (3) Minimum space between leads and flag cannot be smaller than 0.15 mm. © 2010 SCILLC. All rights reserved Characteristics subject to change without notice 15 Doc. No. MD-9003, Rev. J CAT9555 TQFN 24-PAD 4 X 4MM (HT6) (1)(2)(3) A D DETAIL A E E2 PIN#1 ID PIN#1 INDEX AREA D2 A1 TOP VIEW SIDE VIEW BOTTOM VIEW b SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 — 0.05 A3 b D D2 DETAIL A 0.30 — 2.20 4.00 BSC 2.00 e L 0.25 4.00 BSC 2.00 E E2 L 0.20 REF 0.20 e — A 2.20 0.50 BSC 0.30 — 0.50 FRONT VIEW A3 Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC standard MO-220 (3) Minimum space between leads and flag cannot be smaller than 0.15 mm. Doc. No. MD-9003 Rev. J 16 © 2010 SCILLC. All rights reserved Characteristics subject to change without notice CAT9555 EXAMPLE OF ORDERING INFORMATION Prefix Device # CAT 9555 Optional Company ID Product Number (1) Suffix 9555 HV6 I -G Package W: SOIC Y: TSSOP HV6: TQFN HT6: TQFN Lead Finish Blank: Matte-Tin G: NiPdAu T2 Tape & Reel T: Tape & Reel 1: 1,000/Reel SOIC only 2: 2,000/Reel Temperature Range I = Industrial (-40ºC to 85ºC) ORDERING PART NUMBER Part Number Package Lead Finish CAT9555WI SOIC Matte-Tin CAT9555WI-T1 SOIC Matte-Tin CAT9555YI TSSOP Matte-Tin CAT9555YI-T2 TSSOP Matte-Tin CAT9555HV6I-G TQFN NiPdAu CAT9555HV6I-GT2 TQFN NiPdAu CAT9555HT6I-G TQFN NiPdAu CAT9555HT6I-GT2 TQFN NiPdAu Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is Matte-Tin for SOIC and TSSOP packages and NiPdAu on TQFN package. (3) The device used in the above example is a CAT9555HV6I-GT2 (TQFN, Industrial Temperature, NiPdAu, Tape & Reel, 2,000/Reel). (4) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. © 2010 SCILLC. All rights reserved Characteristics subject to change without notice 17 Doc. No. MD-9003, Rev. J CAT9555 REVISION HISTORY Date 09-Dec-04 Revision A Description Advance Information - Initial Issue 07-Jan-05 B 11-Mar-05 C 25-Sep-06 D Advance Information - Minor changes Advance Information - Edit Features - Edit Ordering Information Initial Release 12-Mar-07 E Update Ordering Information: Tape and Reel for SOIC package 07-Jun-07 F 21-Jan-08 G Update Figure 6 Add NiPdAu lead finish for TQFN package Update Example of Ordering Information Update Package Outline Drawings Change document number from 8551 05-May-08 H 02-Dec-08 I 2 2 Update A.C. Characteristics table to include Standard I C and Fast I C. Change logo and fine print to ON Semiconductor 17-Mar-10 J Update TQFN Packages Delete TQFN package in Matte-Tin Update Package Outline Drawings - TQFN 24-Pad 4 x 4mm ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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All rights reserved Characteristics subject to change without notice N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 18 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative Doc. No. MD-9003, Rev. J