PCS3P25811 D

PCS3P25811,
PCS3P25812,
PCS3P25814
Spread Spectrum Clock
Generator
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Product Description
The PCS3P25811/12/14 devices are versatile spread spectrum
frequency modulators designed specifically for a wide range of input
clock frequencies from 4 MHz to 32 MHz.
The PCS3P25811/12/14 reduce electromagnetic interference (EMI)
at the clock source, allowing system wide reduction of EMI of down
stream clock and data dependent signals. It allows significant system
cost savings by reducing the number of circuit board layers, ferrite
beads, shielding, and other passive components that are traditionally
required to pass EMI regulations.
The PCS3P25811/12/14 can generate an EMI reduced clock from
crystal, ceramic resonator, or system clock.
The PCS3P25811/12/14 modulate the output of a single PLL in
order to “spread” the bandwidth of a synthesized clock, and more
importantly, decreases the peak amplitudes of its harmonics. This
results in significantly lower system EMI compared to the typical
narrow band signal produced by oscillators and most frequency
generators. Lowering EMI by increasing a signal’s bandwidth is called
‘spread spectrum clock generation’.
The PCS3P25811/12/14 use the most efficient and optimized
modulation profile approved by the FCC and is implemented in a
proprietary all−digital method.
The PCS3P25811/12/14 have 2 pins S0 and S1 to control the
selection of Center Spread, Down Spread and No−Spread functions.
Additionally there is a 3 level logic contol FSEL, for selecting one of
the three different frequency ranges within the operating frequency
range. Refer Input/Output Frequency Range Selection Table.
The PCS3P25811/12/14 operate from a 2.8 V to 3.6 V supply and
are available in 8 pin SOIC, and 8L 2 mm x 2 mm WDFN packages.
The PCS3P25811/12/14 are targeted towards EMI
management in applications such as LCD Panels, MFPs,
Digital copiers, Networking, PC peripheral devices,
consumer electronics, and embedded controller systems.
•
•
•
•
•
Features
• Generates a 1x (PCS3P25811), 2x (PCS3P25812) and
4x(PCS3P25814) Low EMI Spread Spectrum Clock of
the Input Frequency
Provides up to 15 dB of EMI Suppression
Input Frequency: 4 MHz − 32 MHz
Output Frequency: PCS3P25811: 4 MHz − 32 MHz
PCS3P25812: 8 MHz − 64 MHz
PCS3P25814: 16 MHz − 128 MHz
© Semiconductor Components Industries, LLC, 2015
February, 2015 − Rev. 0
1
1
SOIC−8 NB
CASE 751
WDFN8 2x2, 0.5P
CASE 511AQ
PIN CONFIGURATION
XIN / CLKIN
1
VSS
2
S1
3
S0
4
PCS3P25811
PCS3P25812
PCS3P25814
8
XOUT
7
VDD
6
FSEL
5
ModOUT
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
• Selectable Spread Options: Down Spread and Center
Applications
•
•
•
8
•
•
1
Spread
Low Power Dissipation: 3.3 V: 20 mW (typ) @ 6 MHz
3.3 V: 24 mW (typ) @ 12 MHz
3.3 V: 30 mW (typ) @ 24 MHz
Low Inherent Cycle−to−Cycle Jitter
Supply Voltage: 2.8 V to 3.6 V
LVCMOS Input and Output
Functional and Pinout Compatible to Cypress
CY25811, CY25812 and CY25814
8−pin SOIC, and 8L 2 mm x 2 mm WDFN (TDFN)
Packages
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
Publication Order Number:
PCS3P25811/D
PCS3P25811, PCS3P25812, PCS3P25814
FSEL S1
VDD
S0
PLL
Input Decoder
& Modulation Control
XIN /CLKIN
Crystal
Oscillator
Frequency
Divider
XOUT
Feedback
Divider
Phase
Detector
Loop
Filter
Output
Divider
VCO
ModOUT
VSS
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin #
Pin Name
Type
Description
1
XIN / CLKIN
Input
2
VSS
Power
3
S1
Input
Digital 3 level logic input (1−M−0) used to select Center, Down and No spread options.
(Refer to Frequency Deviation Selection Table). Default = M.
4
S0
Input
Digital 3 level logic input (1−M−0) used to select Center, Down and No spread options.
(Refer to Frequency Deviation Selection Table). Default = M.
5
ModOUT
Output
6
FSEL
Input
7
VDD
Power
Power supply for the entire chip (2.8 V to 3.6 V).
8
XOUT
Output
Crystal connection. If using an external reference, this pin must be left unconnected.
Crystal connection or External Clock input.
Ground to entire chip.
Spread Spectrum Clock Output.
Frequency range select. Digital 3 level logic input (1−M−0) used to select Input Clock
frequency range (Refer to Input/Output Frequency Range Selection Table). Default = M.
Table 2. OUTPUT FREQUENCY RANGE SELECTION
Part Number
PCS3P25811 (1x)
PCS3P25812 (2x)
PCS3P25814 (4x)
FSEL (pin 6)
Input (MHz)
Output (MHz)
Input (MHz)
Output (MHz)
Input (MHz)
Output (MHz)
Modulation Rate
0
4−8
4−8
4−8
8 − 16
4−8
16 − 32
Input Frequency / 128
1
8 − 16
8 − 16
8 − 16
16 − 32
8 − 16
32 − 64
Input Frequency / 256
M
16 − 32
16 − 32
16 − 32
32 − 64
16 − 32
64 − 128
Input Frequency / 512
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PCS3P25811, PCS3P25812, PCS3P25814
Table 3. OUTPUT FREQUENCY DEVIATION SELECTION
S1 = 0
S0 = 0
S1 = 0
S0 = M
S1 = 0
S0 = 1
S1 = M
S0 = 0
S1 = 1
S0 = 1
S1 = 1
S0 = 0
S1 = M
S0 = 1
S1 = 1
S0 = M
S1 = M
S0 = M
CLKIN (MHz)
FSEL
Center
Center
Center
Center
Down
Down
Down
Down
No Spread
4−5
0
±1.4
±1.2
±0.6
±0.5
−3
−2.2
−1.9
−0.7
0
5−6
0
±1.3
±1.1
±0.5
±0.4
−2.7
−1.9
−1.7
−0.6
0
6−7
0
±1.2
±0.9
±0.5
±0.4
−2.5
−1.8
−1.5
−0.6
0
7−8
0
±1.1
±0.9
±0.4
±0.3
−2.3
−1.7
−1.4
−0.5
0
8 − 10
1
±1.4
±1.2
±0.6
±0.5
−3
−2.2
−1.9
−0.7
0
10 − 12
1
±1.3
±1.1
±0.5
±0.4
−2.7
−1.9
−1.7
−0.6
0
12 − 14
1
±1.2
±0.9
±0.5
±0.4
−2.5
−1.8
−1.5
−0.6
0
14 − 16
1
±1.1
±0.9
±0.4
±0.3
−2.3
−1.7
−1.4
−0.5
0
16 − 20
M
±1.4
±1.2
±0.6
±0.5
−3
−2.2
−1.9
−0.7
0
20 − 24
M
±1.3
±1.1
±0.5
±0.4
−2.7
−1.9
−1.7
−0.6
0
24 − 28
M
±1.2
±0.9
±0.5
±0.4
−2.5
−1.8
−1.5
−0.6
0
28 − 32
M
±1.1
±0.9
±0.4
±0.3
−2.3
−1.7
−1.4
−0.5
0
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3 Level Digital Logic
S0, S1, and FSEL digital inputs are designed to sense 3
different logic levels designated as High “1”, Low “0” and
Middle “M”. With this 3−Level digital input logic 9 different
logic states can be detected.
S0, S1 and FSEL pins include an on chip 100 K (50 K /
50 K) resistor divider. No external application resistors are
needed to implement the 3−Level logic levels as shown in
table on the right:
VDD
Logic
Control Pins
1
FSEL, S0, S1 to VDD
M
FSEL, S0, S1
UNCONNECTED
0
FSEL, S0, S1 to VSS
VSS
Table 4. OPERATING CONDITIONS
Symbol
VDD, VIN
Parameter
Voltage on any pin with respect to VSS
Min
Max
Unit
2.8
3.6
V
0
+70
°C
TA
Operating temperature
CL
Load Capacitance
15
pF
CIN
Input Capacitance
7
pF
Table 5. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD, VIN
TSTG
Parameter
Rating
Unit
Voltage on any pin with respect to Ground
−0.5 to +4.6
V
Storage temperature
−65 to +125
°C
Ts
Max. Soldering Temperature (10 sec)
260
°C
TJ
Junction Temperature
150
°C
2
KV
TDV
Static Discharge Voltage (As per JEDEC STD 22− A114−B)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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PCS3P25811, PCS3P25812, PCS3P25814
Table 6. DC ELECTRICAL CHARACTERISTICS
Symbol
VDD
VIL
Parameter
Supply Voltage
Input low voltage
(S0, S1, FSEL Inputs)
Min
Typ
Max
Units
2.8
3.3
3.6
V
V
Commercial Temperature
0
0.15 VDD
Industrial Temperature
0
0.13 VDD
VIM
Input middle voltage (S0, S1, FSEL Inputs)
0.4 VDD
0.60 VDD
V
VIH
Input high voltage (S0, S1, FSEL Inputs)
0.85 VDD
VDD
V
VOL
Output low voltage
(ModOUT Output)
IOL = 4 mA
0.4
V
IOL = 10 mA
1.2
Output high voltage
(ModOUT Output)
IOH = −4 mA
2.4
IOH = −6 mA
2
VOH
CIN
Input Capacitance (XIN and XOUT)
IDD
Dynamic supply current
V
6
Commercial
Temperature
(Unloaded Output)
Industrial
Temperature
9
pF
XIN / CLKIN = 12 MHz
8
mA
XIN / CLKIN = 24 MHz
10
XIN / CLKIN = 32 MHz
13
XIN / CLKIN = 12 MHz
10
XIN / CLKIN = 24 MHz
12
XIN / CLKIN = 32 MHz
ICC
mA
15
Static supply current (XIN / CLKIN pulled to VSS)
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Table 7. AC ELECTRICAL CHARACTERISTICS
Symbol
fIN
Parameter
Min
Typ
Max
Units
Input Clock frequency for PCS3P25811/12/14
4
32
MHz
ModOUT Clock frequency for PCS3P25811
4
32
MHz
ModOUT Clock frequency for PCS3P25812
8
64
ModOUT Clock frequency for PCS3P25814
16
128
tLH
(Notes 1, 2)
ModOUT Rise time
(Measured from 20% to 80%)
PCS3P25811/12/14
2
5
PCS3P25814 when FSEL = M
1
2.2
tHL
(Notes 1, 2)
ModOUT Fall time
(Measured from 80% to 20%)
PCS3P25811/12/14
2
4.4
PCS3P25814 when FSEL = M
1
2.2
Input Clock Duty Cycle (XIN / CLKIN)
40
60
%
Output Clock Duty Cycle (ModOUT)
40
60
%
fOUT
TDCIN
TDCOUT
(Notes 1, 2)
1. Parameters are specified with 15 pF loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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4
nS
nS
PCS3P25811, PCS3P25812, PCS3P25814
Table 7. AC ELECTRICAL CHARACTERISTICS
Symbol
TJC
(Note 2)
Parameter
Cy−Cy Jitter,
for ModOUT with Spread ON
Min
(for Commercial temperature)
PCS3P25812
PCS3P25814
Cy−Cy Jitter,
for ModOUT with Spread ON
PCS3P25811
PCS3P25812
PCS3P25814
(for Industrial temperature)
tON
(Note 2)
Max
Units
4 MHz
600
pS
8 MHz
450
16 MHz
400
32 MHz
380
64 MHz
380
128 MHz
380
CLKIN = 6 MHz
500
CLKIN = 12 MHz
400
CLKIN = 24 MHz
380
PCS3P25811
PLL Lock Time
(Stable power supply, valid
input clock to valid Clock on
ModOUT)
Typ
Commercial Temperature
2
Industrial Temperature
3
pS
mS
1. Parameters are specified with 15 pF loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Application Schematic
VDD
7
CL
0.1 mF
VDD
1 XIN
CL
C3
Y1
12 MHz
Center Spread ±0.5%
ModOUT 5
8 XOUT
VDD
12 MHz (PCS3P25811)
24 MHz (PCS3P25812)
48 MHz (PCS3P25814)
VDD
PCS3P25811/12/14
S0 4
6 FSEL
S1 3
VSS
2
Figure 2. Application Schematic
Table 8. TYPICAL CRYSTAL SPECIFICATIONS
Fundamental AT Cut Parallel Resonant Crystal
Nominal frequency
12 MHz
Frequency tolerance
±30 ppm or better at 25°C
Operating temperature range
−25°C to +85°C
Storage temperature
−40°C to +85°C
Load capacitance
18 pF
Shunt capacitance
7 pF maximum
ESR
25 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
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PCS3P25811, PCS3P25812, PCS3P25814
R
Crystal
CX
Rx
CX
CX = 2*(CP − CS),
Where CP = Load capacitance of crystal.
CS = Stray capacitance due to CIN, PCB, Trace, etc.
Figure 3. Typical Crystal Interface Circuit
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PCS3P25811, PCS3P25812, PCS3P25814
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
PCS3P25811, PCS3P25812, PCS3P25814
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AQ
ISSUE A
D
A
B
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
L
L1
PIN ONE
REFERENCE
2X
0.10 C
2X
ÍÍ
ÍÍ
0.10 C
OPTIONAL
CONSTRUCTIONS
DIM
A
A1
A3
b
D
E
e
L
L1
ÉÉÉ
ÉÉÉ
TOP VIEW
EXPOSED Cu
A3
DETAIL B
0.05 C
DETAIL A
E
MOLD CMPD
MILLIMETERS
MIN
MAX
0.80
0.70
0.05
0.00
0.20 REF
0.30
0.20
2.00 BSC
2.00 BSC
0.50 BSC
0.50
0.60
--0.15
DETAIL B
A
8X
0.05 C
OPTIONAL
CONSTRUCTION
RECOMMENDED
SOLDERING FOOTPRINT*
A1
C
SIDE VIEW
SEATING
PLANE
7X
0.78
DETAIL A
1
8X
4
PACKAGE
OUTLINE
L
2.30
0.88
8
5
8X
e/2
e
b
0.10 C A
0.05 C
1
8X
B
0.35
0.50
PITCH
DIMENSIONS: MILLIMETERS
NOTE 3
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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PCS3P25811, PCS3P25812, PCS3P25814
Table 9. ORDERING INFORMATION
Part Number
Marking
Package Type
Temperature
PCS3P25811AG08SR
CGL
8−pin SOIC − Tape & Reel, Green
0°C to +70°C
P3P25812AG−08SR
CIL
8−pin SOIC − Tape & Reel, Green
0°C to +70°C
P3P25814AG−08SR
CKL
8−pin SOIC − Tape & Reel, Green
0°C to +70°C
P3P25811AG−08CR
CG
8L−WDFN (2 mm x 2 mm) − Tape & Reel, Green
0°C to +70°C
P3P25812AG−08CR
CI
8L−WDFN (2 mm x 2 mm) − Tape & Reel, Green
0°C to +70°C
P3P25814AG−08CR
CK
8L−WDFN (2 mm x 2 mm) − Tape & Reel, Green
0°C to +70°C
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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For additional information, please contact your local
Sales Representative
PCS3P25811/D