P3PSL450A D

P3PSL450A
Low Voltage, Timing-Safe]
Peak EMI Reduction IC
Functional Description
P3PSL450A/AH is a versatile low voltage peak EMI reduction IC
based on Timing−Safe technology. P3PSL450A/AH accepts one input
from an external reference, and locks on to it delivering a 1x
Timing−Safe output clock. P3PSL450A/AH has a Frequency
Selection (FS) control that facilitates selecting one of the two
frequency ranges within the operating frequency range. Refer
frequency Selection table. The device has an SSEXTR pin to select
different deviations depending upon the value of an external resistor
connected at this pin to GND. P3PSL450A/AH has an MR pin for
selecting one of the two Modulation Rates. PD# provides the Power
Down option.
P3PSL450A is a Low drive part and P3PSL450AH is a High drive
part. Refer to DC/AC Electrical characteristic table.
P3PSL450A/AH operates over a supply voltage range of 1.8 V $
0.2 V, and is available in an 8 Pin WDFN (2 mm x 2 mm) Package.
General Features
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MARKING
DIAGRAM
1
1
WDFN8
CASE 511AQ
XX MG
G
XX = Specific Device Code
M = Date Code
G
= Pb−Free Device
PIN CONFIGURATION
1x, LVCMOS Timing−Safe Peak EMI Reduction
Input Clock Frequency: 15 MHz − 60 MHz
Output Clock Frequency (Timing−Safe): 15 MHz − 60 MHz
Analog Frequency Deviation Selection
Two different Modulation Rate Selection Option
Power Down option for Power Save
Low and High Drive Parts
Supply Voltage: 1.8 V $ 0.2 V
8 Pin WDFN (2 mm X 2 mm) Package
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
CLKIN 1
FS 2
8 VDD
7 SSEXTR
PD# 3
6 MR
GND 4
5 ModOUT
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Application
• P3PSL450A/AH is targeted for use in consumer electronic
applications like mobile phones, Camera modules, MFP and DPF
MR
VDD
SSEXTR
CLKIN
PLL
ModOUT
(Timing−Safe)
PD#
GND
FS
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2010
July, 2010 − Rev. 1
1
Publication Order Number:
P3PSL450A/D
P3PSL450A
Table 1. PIN DESCRIPTION
Pin #
Pin Name
Type
1
CLKIN
I
External reference Clock input.
Description
2
FS
I
Frequency Select. Has an internal pull−down resistor. see Frequency Selection table
3
PD#
I
Power Down. Pull LOW to enable Power Down. Pull HIGH to disable power down.
Output Clock will be LOW when power down is enabled. Has an internal pull−up resistor
4
GND
P
Ground
5
ModOUT
O
Buffered modulated Timing−Safe clock output
6
MR
I
Modulation Rate Select. When LOW selects Low Modulation Rate. Selects High
Modulation Rate when pulled HIGH. Has an internal pull−up resistor.
7
SSEXTR
I
Analog Frequency Deviation Selection through external resistor to GND.
8
VDD
P
1.8 V Supply Voltage
Table 2. FREQUENCY SELECTION TABLE
FS
Frequency (MHz)
0
15−30
1
30−60
Table 3. ABSOLUTE MAXIMUM RATING
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
−0.3
+2.7
V
DC Input Voltage(CLKIN)
−0.3
+2.7
V
DC Input Voltage (Except CLKIN)
−0.3
VDD + 0.3
V
Storage Temperature
−65
+150
°C
Max. Soldering Temperature (10 sec)
260
°C
Junction Temperature
150
°C
Static Discharge Voltage
(As per JEDEC STD22−A114−B)
2000
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. OPERATING CONDITIONS
Symbol
Min
Max
Unit
Supply Voltage
1.6
2
V
TA
Operating Temperature
−20
+85
°C
CL
Load Capacitance
15
pF
CIN
Input Capacitance
7
pF
VDD
Parameter
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P3PSL450A
Table 5. DC ELECTRICAL CHARACTERISTICS FOR VDD = 1.8 V $ 0.2 V
Symbol
Parameter
VDD
Test Conditions
Supply Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
VOH
Min
Typ
Max
Unit
1.6
1.8
2
V
0.65 * VDD
Output HIGH Voltage
V
0.35 * VDD
V
VIN = VDD
5
mA
VIN = 0 V
5
mA
IOH = −8 mA (P3PSL450A)
0.75 * VDD
V
IOH = −16 mA (P3PSL450AH)
VOL
Output LOW Voltage
IOL = 8 mA (P3PSL450A)
0.25 * VDD
V
10
mA
mA
IOL = 16 mA (P3PSL450AH)
ICC
Static Supply Current
IDD
Dynamic Supply Current
Zo
CLKIN & PD# pins pulled to GND
Unloaded
Output
Output Impedance
FS = 0, @ 15 MHz
1.7
2.2
FS = 0, @ 30 MHz
3.0
3.7
FS = 1, @ 30 MHz
2.6
3.7
FS = 1, @ 60 MHz
4.3
6.4
P3PSL450A
23
P3PSL450AH
17
W
Table 6. AC ELECTRICAL CHARACTERISTICS FOR VDD = 1.8 V $ 0.2 V
Parameter
Test Conditions
Min
Max
Unit
FS = 0
15
30
MHz
FS = 1
30
60
FS = 0
15
30
FS = 1
30
60
Measured at VDD / 2
45
Input Frequency
ModOUT
Duty Cycle
(Notes 1 and 2)
Rise Time
(Notes 1 and 2)
Measured between 20% to
80%
Fall Time
(Notes 1 and 2)
Measured between 80% to
20%
Cycle−to−Cycle Jitter
(Note 2)
Unloaded output with
SSEXTR pin OPEN
50
55
%
P3PSL450A
1.3
2.1
ns
P3PSL450AH
1
1.7
P3PSL450A
1.3
2.1
P3PSL450AH
FS = 0
FS = 1
PLL Lock Time
2
Typ
1
1.7
15 MHz
$150
$250
24 MHz
$100
$150
30 MHz
$80
$150
30 MHz
$150
$250
60 MHz
$100
$150
Stable power supply, valid clock presented on CLKIN pin,
PD# toggled from Low to High
1. All parameters are specified with 15 pF loaded output.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production
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3
1
ns
ps
ms
P3PSL450A
SWITCHING WAVEFORMS
t1
t2
VDD/2
VDD/2
VDD/2
OUTPUT
Figure 2. Duty Cycle Timing
80%
80%
20%
20%
OUTPUT
t3
t4
Figure 3. Output Rise/Fall Time
Input
Timing−Safe Output
TSKEW
ÎÎÎ ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ ÎÎÎ
TSKEW/2
TSKEW/2
One clock cycle (T)
TSKEW represents input−output skew when spread spectrum is ON
For example, TSKEW/2 = $0.20 * T for an Input clock of 24 MHz, translates in to
(1/24 MHz) * 0.20 = 8.33 ns
Figure 4. Input−Output Skew
Input
Input
Timing-Safe ModOUT
ModOUT with SSOFF
Figure 5. Typical Example of Timing−Safe Waveform
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P3PSL450A
DEVIATION VERSUS SSEXTR RESISTANCE CHARTS
3.0
2.0
1.5
1.0
0.5
0.0
0
1.5
1.0
0.0
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
RESISTANCE (kW)
Figure 6. Deviation vs SSEXTR Chart
(CLKIN = 15 MHz)
Figure 7. Deviation vs SSEXTR Chart
(CLKIN = 15 MHz)
3
FS = 0,
MR = 0
FS = 0,
MR = 1
2.5
DEVIATION ($%)
2.5
DEVIATION ($%)
2.0
0.5
3
2
1.5
1
2
1.5
1
0.5
0.5
0
FS = 0,
MR = 1
2.5
DEVIATION ($%)
2.5
DEVIATION ($%)
3.0
FS = 0,
MR = 0
0
0
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
RESISTANCE (kW)
Figure 8. Deviation vs SSEXTR Chart
(CLKIN = 24 MHz)
Figure 9. Deviation vs SSEXTR Chart
(CLKIN = 24 MHz)
2.5
1.5
FS = 0,
MR = 0
FS = 0,
MR = 1
DEVIATION ($%)
DEVIATION ($%)
2.0
1.5
1.0
1.0
0.5
0.5
0.0
0
0.0
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
RESISTANCE (kW)
Figure 10. Deviation vs SSEXTR Chart
(CLKIN = 30 MHz)
Figure 11. Deviation vs SSEXTR Chart
(CLKIN = 30 MHz)
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P3PSL450A
DEVIATION VERSUS SSEXTR RESISTANCE CHARTS
3.0
2.0
1.5
1.0
0
1.0
0
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
RESISTANCE (kW)
Figure 12. Deviation vs SSEXTR Chart
(CLKIN = 30 MHz)
Figure 13. Deviation vs SSEXTR Chart
(CLKIN = 30 MHz)
3.0
FS = 1,
MR = 0
2.0
1.5
1.0
FS = 1,
MR = 1
2.5
DEVIATION ($%)
2.5
DEVIATION ($%)
1.5
0.0
100 200 300 400 500 600 700 800 900 1000
3.0
2.0
1.5
1.0
0.5
0.5
0.0
2.0
0.5
0.5
0.0
FS = 1,
MR = 1
2.5
DEVIATION ($%)
2.5
DEVIATION ($%)
3.0
FS = 1,
MR = 0
0
0.0
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
RESISTANCE (kW)
Figure 14. Deviation vs SSEXTR Chart
(CLKIN = 48 MHz)
Figure 15. Deviation vs SSEXTR Chart
(CLKIN = 48 MHz)
2.5
1.5
FS = 1,
MR = 0
FS = 1,
MR = 1
DEVIATION ($%)
DEVIATION ($%)
2.0
1.5
1.0
1.0
0.5
0.5
0.0
0
0.0
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
RESISTANCE (kW)
RESISTANCE (kW)
Figure 16. Deviation vs SSEXTR Chart
(CLKIN = 60 MHz)
Figure 17. Deviation vs SSEXTR Chart
(CLKIN = 60 MHz)
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P3PSL450A
Recommended Noise
reduction Filter
VDDIN
R
C1
0.1 mF
C2
2.2 mF
8
1 CLKIN
VDD
VDD
Rs
ModOUT
Frequency Selection
Control
2 FS
VDD
P3PSL450A/AH
SSEXTR
ModOUT Clock
5
Rx
Analog Deviation Control.
SSEXTR can be Pulled HIGH
to turn OFF SS.
7
VDD
Power down
Control
3 PD#
MR
GND
6
Modulation Rate
Control
4
NOTE:
Refer to Pin Description table for Functionality details
Figure 18. Typical Application Schematic
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P3PSL450A
PCB LAYOUT RECOMMENDATION
For optimum device performance, following guidelines are recommended.
• Dedicated VDD and GND planes.
• The device must be isolated from system power supply noise. A 0.1 mF and a 2.2 mF decoupling capacitor should be
mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the
decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as possible.
All the VDD pins should have decoupling capacitors.
• In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers.
A typical layout is shown in the Figure below:
As short as
possible
R
As short as
possible
CLKIN
VDD
FS
SSEXTR
PD#
MR
GND
ModOUT
Rs
ORDERING INFORMATION
Marking
Temperature
Package Type
Shipping†
P3PSL450AG−08CR
FA
−20°C to +85°C
8− pin (2 mm x 2 mm) WDFN
(Pb−Free)
Tape & Reel
P3PSL450AHG−08CR
FC
−20°C to +85°C
8− pin (2 mm x 2 mm) WDFN
(Pb−Free)
Tape & Reel
Ordering Code
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−Free.
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P3PSL450A
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AQ−01
ISSUE A
D
PIN ONE
REFERENCE
2X
A
B
L1
ÍÍÍ
ÍÍÍ
ÍÍÍ
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
0.10 C
2X
0.10 C
ÉÉ
ÉÉ
TOP VIEW
EXPOSED Cu
A3
DETAIL B
0.05 C
0.05 C
MOLD CMPD
OPTIONAL
CONSTRUCTION
C
MILLIMETERS
MIN
MAX
0.80
0.70
0.05
0.00
0.20 REF
0.20
0.30
2.00 BSC
2.00 BSC
0.50 BSC
0.50
0.60
--0.15
RECOMMENDED
SOLDERING FOOTPRINT*
A1
SIDE VIEW
DIM
A
A1
A3
b
D
E
e
L
L1
DETAIL B
A
8X
SEATING
PLANE
7X
0.78
PACKAGE
OUTLINE
DETAIL A
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
L
L
8X
4
L
2.30
0.88
8
5
e/2
e
8X
b
0.10 C A
0.05 C
8X
1
0.35
B
0.50
PITCH
DIMENSIONS: MILLIMETERS
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
Timing−Safe is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
P3PSL450A/D